a8e re AdLib OCR Evaluation systems Preliminary Data Sheet December 2002 LCK4972A Low-Voltage PLL Clock Driver Features Description . Fully integrated PLL . Agere Systems' LCK4972A is a 3.3 V PLL-based clock driver for high-performance RISC or CISC processor-based systems . The LCK4972A has output frequencies of up to 240 MHz and skews of less than 250 ps, making it ideal for synchronous systems . The LCK4972A contains 12 low-skew outputs and a feedback/sync output for flexibility and simple implementation . . Output frequency up to 240 MHz . . Compatible with PowerPC(c) and Pentiume microprocessors . . 52-pin TQFPT. . 3.3 V power supply. . Pin compatible with 972 type devices . . 100 ps typical cycle-to-cycle jitter. . Output skews of less than 250 ps. There is a robust level of frequency programmability between the 12 low-skew outputs in addition to the input/output relationships . This allows for very flexible programming of the input reference versus the output frequency. The LCK4972A contains a flexible output enable and disable scheme . This helps execute system debug as well as offer multiple powerdown schemes, which meet green-class machine requirements. The LCK4972A features a power-on reset function, which automatically resets the device on powerup, providing automatic synchronization between QFB and other outputs. The LCK4972A is 3.3 V compatible and requires no external loop filters . It has the capability of driving 50 tl transmission lines. Series terminated lines have the ability of driving two 50 tl lines in parallel, effectively doubling the fanout. AdLib OCR Evaluation LCK4972A Low-Voltage PLL Clock Driver Preliminary Data Sheet December 2002 Pin Information Pin Diagram 75 I > 52 > cc c~ o o > c~ 51 50 49 48 0 > cc cc c~ > c~ 47 46 45 44 0 a) 0 a) w w w a) w a) 43 42 41 40 39 Vss 2 38 Qb0 Frz Clk 3 37 VDDO Frz Data 4 36 Qb1 fselFB2 5 35 Vss PLL EN 6 34 Qb2 Ref Sel 7 33 VDDO TCLK Sel 8 32 Qb3 TCLKO 9 31 Ext FB TCLK1 10 30 Vss xtal1 11 29 QFB xtal2 12 28 VDDI VDDA 13 27 fselFBO Vss 1 MROEB 0 LCK4972A 14 ~C V >I c 15 16 17 18 !A CID O N > o > 19 20 21 O w a) <n '~ 22 23 O O 0o > c~ 24 25 !A U > > C7 26 75 2331 (F) r.1 Note : All inputs have internal pull-up resistors (50 kn) except forxtal1 and xtal2. Figure 1 . 52-Pin TQFPT 2 Agere Systems Inc. AdLib OCR Evaluation LCK4972A LowVoltage PLL Clock Driver Preliminary Data Sheet December 2002 Pin Information (continued) Pin Descriptions Table 1 . Pin Descriptions Pin Symbol Type 1, 15, 24, 30, 35, 39, 47,51 Vss Ground 2 MROEB LVTTL 3 4 5 Frz Clk Frz Data fselFB2 LVTTL LVTTL LVTTL 6 PLL EN LVTTL 7 Ref_Sel LVTTL 8 TCLK_Sel LVTTL 9,10 TCLK[0 :1] LVTTL 11 xtal1 LVTTL 12 xtal2 LVTTL 13 14 VDDA Inv_Clk Power LVTTL 16, 18, 21,23 Qc[3:0] LVTTL 17, 22, 33, 37, 45,49 19,20 VDDO Power fselc[1 :0] LVTTL Agere Systems Inc. I/O Description - Ground . I Master Reset and Output Enable Input. Note : When MR/OE is set high, the PLL will have been disturbed and the outputs will be at an indeterminate frequency until MR/OE is relocked . I Freeze Mode. I Freeze Mode. I Feedback Output Divider Function Select. This input, along with pins fseIFB0 and fselFB1, controls the divider function of the feedback bank of outputs . See Table 3 for more details . I PLL Bypass Select. 0 = The internal PLL is bypassed and the selected reference input provides the clocks to operate the device . 1 = The internal PLL provides the internal clocks to operate the device . I Reference Select Input. The Ref_Sel input controls the reference input to the PLL . 0 = The input is selected by the TCLK_Sel input . 1 = The PCLK is selected . I TTL Clock Select Input. The TCLK_Sel input controls which TCLK input will be used as the reference input if Ref Sel is set to 0. 0 = TCLKO is selected . 1 = TCLK1 is selected . I LVTLL Reference Input. These inputs provide the reference frequency for the internal PLL when selected by Ref Sel and TCLK Sel . I Xtal Reference Input. This input provides the reference frequency for the internal PLL when selected by Ref Sel . I Xtal Reference Input. This input provides the reference frequency for the internal PLL when selected by Ref Sel . - PLL Power. I Invert Mode. This input only affects the Qc bank. 0 = All outputs of the Qc bank are in the normal phase alignment. 1 = Qc2 and Qc3 are inverted from the normal phase of Qc0 and Qc1 . O Clock Output. These outputs, along with the Qa[0:3], Qb[0:3], and QFB outputs, provide numerous divide functions determined by the fsela[0 :3], fselb[0:3], and the fselFB[0:2] See Table 2 and Table 3 for more details . - Output Buffer Power. I Output Divider Function Select . Each pair controls the divider function of the respective bank of outputs . See Table 2 for more details. AdLib OCR Evaluation LCK4972A Low-Voltage PLL Clock Driver Preliminary Data Sheet December 2002 Pin Information (continued) Pin Descriptions (continued) Table 1 . Pin Descriptions (continued) Pin Symbol Type I/O Description 25 QSync LVTTL O PLL Lock Indicator. 0 = The PLL is attempting to acquire lock. 1 = This output indicates that the internal PLL is locked to the reference signal . 26 fselFB1 LVTTL 27 fselFBO LVTTL 28 29 VDDI QFB Power LVTTL 31 Ext FB LVTTL 32, 34, 36,38 Qb[3 :0] LVTTL 40,41 fselb[1 :0] LVTTL 42,43 fsela[1 :0] LVTTL 44, 46, 48,50 Qa[3 :0] LVTTL 52 VCO Sel LVTTL Note : If there is no activity on the selected reference input, QSync may not accurately reflect the state of the internal PLL . This pin will drive logic, but not Thevenin terminated transmission lines. It is always active and does not go to a high-impedance state . QSync provides TEST MODE information when PLL EN is set to 0. I Feedback Output Divider Function Select. This input, along with pins fselFB1 and fselFB2, controls the divider function of the feedback bank of outputs . See Table 3 for more details . I Feedback Output Divider Function Select. This input, along with pins fselFBO and fselFB2, controls the divider function of the feedback bank of outputs . See Table 3 for more details . - PLL Power. O Clock Output . This output, along with the Qa[0 :3] and Qc[0:3] outputs, provides numerous divide functions determined by the fsela[0 :3], fselb[0 :3], and the fselFB[0:2] . See Table 2 and Table 3 for more details. I PLL Feedback Input. This input is used to connect one of the clock outputs (usually QFB) to the feedback input of the PLL. O Clock Output. These outputs, along with the Qa[0:3], Qc[0:3], and QFB outputs, provide numerous divide functions determined by the fsela[0 :3], fselb[0 :3], and the fselFB[0:2] . See Table 2 and Table 3 for more details. I Output Divider Function Select . Each pair controls the divider function of the respective bank of outputs. See Table 2 for more details. I Output Divider Function Select . Each pair controls the divider function of the respective bank of outputs. See Table 2 for more details. O Clock Output. These outputs, along with the Qb[0:3], Qc[0:3], and QFB outputs, provide numerous divide functions determined by the fsela[0 :3], fselb[0 :3], and the fselFB[0:2] . See Table 2 and Table 3 for more details. I VCO Frequency Select Input. This input selects the nominal operating range of the VCO used in the PLL . 0 = The VCO range is 100 MHz-240 MHz . 1 = The VCO range is 200 MHz-480 MHz . Agere Systems Inc. AdLib OCR Evaluation LCK4972A LowVoltage PLL Clock Driver Preliminary Data Sheet December 2002 Functional Description Using the select lines (fsela[1 :0], fselb[1 :0], fselc[1 :0], fselFB[2:0]), the following output frequency ratios between outputs can be obtained: M 1 :1 2 :1 3:1 3:2 4:1 4:3 5:1 5:2 5:3 6:1 6:5 These ratios can be achieved by pushing the control signal low one clock edge before the coincident edges of outputs Qa and Qc. The synchronization output indicates when these rising edges will occur. Selectability of feedback frequency is independent of the output frequencies . Output frequencies can be odd or even multiples of the input reference clock, as well as being less than the input frequency. The power-on reset function is designed to reset the system after powerup for synchronization between QFB and other outputs . This solves the problem of resetting if fselFB2 is held high on powerup . All other conditions of the fsel pins automatically synchronize during PLL clock acquisition . All outputs are initialized active on power on. The LCK4972A independently enables each output through a serial input port. When disabled (frozen), the outputs will lock in the low state, but internal state machines are unaffected. When re-enabled, the outputs initialize in phase and synchronous with those not reactivating . This freezing only happens when the outputs are in the low state, preventing runt pulse generation . Agere Systems Inc. Table 2. Function Table for Qa, Qb, and Qc fsela1 fsela0 Qa fselb1 fselb0 Qb fselc1 fselc0 Qc 0 0 1 1 I 0 1 .4 0 1 I :12I I 1 0 :6 .8 0 1 0 1 .4 0 1 I .10I I 1 :6 .8 0 I 0 1 I 0 1 :2 :4 1 I :8I 0 :6 Table 3. Function Table for QFB fseIFB21 0 0 0 0 1 1 1 1 I fselFB1 0 0 1 1 0 0 1 1 I fselFBO 0 1 0 1 0 1 0 1 QFB .4 .6 .8 =10 .8 =12 =16 -20 I 1 . If fselFB2 is set to 1, it may be necessary to apply a reset pulse after powerup in order to ensure synchronization between the QFB and other inputs. Table 4. Function Table for Logic Selection Control Pin Logic 0 Logic 1 VCO Sel VCO/2 VCO Ref Sel TCLK Xtal (PECL) TCLK Sel TCLKO TCLK1 PLL EN Bypass PLL Enable PLL MR/OE Master Reset/ Output High-Z Enable Outputs Inv_Clk Noninverted Qc2, Qc3 Inverted Qc2, Qc3 5 AdLib OCR Evaluation LCK4972A Low-Voltage PLL Clock Driver Preliminary Data Sheet December 2002 Functional Description (continued) F RE Qa0 Qa1 Qa2 TC Qa3 Qb0 Qb1 Qb2 Qb3 Qc0 Qc1 Qc2 Qc3 QFB QSync fSi Fr 2332 (F) Figure 2. Logic Diagram 6 Agere Systems Inc. AdLib OCR Evaluation LCK4972A LowVoltage PLL Clock Driver Preliminary Data Sheet December 2002 Functional Description (continued) frequency is half of the lowest frequency output. This multiplies the output frequencies by a factor of two, relative to the input reference frequency. Device Programming The LCK4972A contains three independent banks of four outputs as well as an independent PLL feedback output. The possible configurations make Agere Systems Inc .'s LCK4972A one of the most versatile frequency programming devices . Table 5 shows various selection possibilities . Assume the previously mentioned 5:3:2 ratio with the highest output frequency of 100 MHz . If the only available reference frequency is 50 MHz, the setup of Figure 3 can be used. The device provides 100 MHz, 66 MHz, and 40 MHz outputs, all generated from the 50 MHz source . Figure 4 and Figure 5 also show possible configurations of the LCK4972A . Table 5. Programmable Output Frequency Relationships for Qa, Qb, and Qc (VCO Sel = 1) v v 0 0 1 1 I 0 1 0 1 1 4) 42 4) 42 Qa VCO/4 VCO/6 VCO/8 1 1 VCO/12 1 1 M M 0 0 1 1 1 0 1 0 1 1 Z 42 Z 42 Qb VCO/4 VCO/6 VCO/8 1 1 VCO/101 1 2 4) 42 0 0 1 1 1 , 4) 42 Qc 0 1 0 1 1 VCO/2 VCO/4 VC01/6 VC8/8I 50 MHz Table 6. Programmable Output Frequency Relationships for QFB (VCO Sel = 1) fselFB2 fselFB1 fselFBO QFB 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 VCO/4 VCO/6 VCO/8 VCO/10 VCO/8 VCO/12 VCO/16 VCO/20 To determine the relationship between the three banks, compare their divide ratios . For example, if a ratio of 5:3:2 is desired, set Qa to =10, Qb to =6, and Qc to =4. These selections would yield a 5:3:2 ratio. For low frequency circumstances, the VCO Sel pin allows the option of an additional -2 to be added to the clock path. This pin maintains the output relationships, but provides an extended clock range for the PLL . The feedback output is matched to the input reference frequency after the output frequency relationship is set and VCO is in a stable range. LCK4972A fsela0 fselal fselb0 fselbl fselc0 fselcl fse!FBO fseIFB1 fselFB2 0 0 1 1 0 1 0 1 0 Qa 4 100 MHz Qb 4 40 MHz Qc 4 66.66 MHz QFB 50 MHz Input Ref Ext_FB VCO = 400 MHz 2334 (F) r.1 Figure 3. 100 MHz from 50 MHz Example LCK4972A 0 fsela0 0 0 1 1 1 1 0 fselb0 fselbl fselc0 fselc1 fseIFBO fselFB1 fselFB2 24 MHz Oa 4 60 MHz (PROCESSOR) Qb 4 60 MHz (PROCESSOR) QC 4 30 MHz (PCI) QFB 24 MHz (FLOPPY DISK CLK) Input Ref Ext FB 2335 (F) r.1 Figure 4. Pentium Compatible Clocks Example Only an external feedback is provided to the PLL in the LCK4972A device to optimize flexibility. If, in the previous example, the input reference frequency were equal to the lowest output frequency, the output would be set to =10 mode. The fselFB2 input could be asserted to half the frequency if the needed feedback Agere Systems Inc. 7 AdLib OCR Evaluation LCK4972A Low-Voltage PLL Clock Driver Preliminary Data Sheet December 2002 Functional Description (continued) Device Programming (continued) 1 1 0 1 1 1 1 1 1 20 MHz LC K4972A fsela0 fsela1 fselb0 fselbl fselc0 fselcl fseIFBO fselFB1 fselFB2 Qa Qb 4 4 33 MHz (PCI) 50 MHz (PROCESSOR) Qc r~ 50 MHz (PROCESSOR) QFB r---l 20 MHz (ETHERNET) Input Ref Ext_FB 2336 (F) r.1 Figure 5. 20 MHz Source Example The Lnv_Clk input pin, when asserted, will invert the Qc2 and Qc3 outputs . This inversion does not affect the output-output skew of the device and allows for the development of 180 phase-shifted clocks. This output can also be used as a feedback output or routed to a second PLL to generate early/late clocks . Figure 5 on page 8 shows a 180 phase-shift configuration . SYNC Output When the output frequencies are not integer multiples of each other, there is a need for a signal for synchronization purposes. The SYNC output is designed to address this need. The Qa and Qc banks of outputs are monitored by the device, and a low-going pulse (one period in duration, one period before the coincident rising edges of Qa and Qc) is provided . The duration and placement of the pulse is dependent on the highest of Qa and Qc output frequencies . The timing diagram, (Figure 8 on page 10) shows the various waveforms for SYNC. Note : SYNC is defined for all possible combinations of Qa and Qc, even though the lower frequency clock should be used as a synchronizing signal in most cases . 8 Agere Systems Inc. AdLib OCR Evaluation LCK4972A LowVoltage PLL Clock Driver Preliminary Data Sheet December 2002 Functional Description (continued) SYNC Output (continued) 0 0 0 0 1 0 0 0 0 1 66 MHz LCK4972A fsela0 fselal fselb0 fselbl fselc0 fselcl fseIFB0 fseIFB1 fseIFB2 Inv Clk Qa 4 66 MHz Qb 4 66 MHz QC 2 66 MHz Qc 2 66 MHz 0 1 0 1 1 1 0 0 0 0 QFB Input Ref LCK4972A fsela0 fsela1 fselb0 fselbl fselc0 fselcl fseIFB0 fseIFB1 fseIFB2 Inv-Clk Qa 4 33 MHz SHIFTED 90 Qb 4 33 MHz SHIFTED 90- QC 4 33 MHz SHIFTED 90 QFB 66 MHz 66 MHz Input Ref Ext FB 66 MHz 33 MHz SHIFTED 90 Ext FB 2337 (F) r.1 Figure 6. Phase Delay Example Using Two LCK4972As 100 75 50 25 a 0 -25 -50 -75 -100 Qc3 Qc2 Qc1 Qc0 Qb3 Qb2 Qb1 Qb0 Qa3 Qa2 Qal Qa0 QFB 2338.a (F) r.1 Figure 7. Typical Skews Relative to QA Agere Systems Inc. 9 AdLib OCR Evaluation LCK4972A Low-Voltage PLL Clock Driver Preliminary Data Sheet December 2002 Functional Description (continued) SYNC Output (continued) rvcO 1 :1 MODE Qa Qc Sync 2:1 MODE Qa Qc Sync 3:1 MODE Qc(-2) Qa(-6) Sync 3:2 MODE Qa(-4) Qc(-6) Sync 4:1 MODE Qc(-2) Qa(-8) Sync 4:3 MODE Qa(-6) Qc(-8) Sync 6:1 MODE Qa(-12) Qc(-2) Sync 2333 (F) Figure 8. LCK4972A Timing 10 Agere Systems Inc. AdLib OCR Evaluation Preliminary Data Sheet December 2002 Functional Description (continued) On-Board Crystal Oscillator The LCK4972A features an on-board crystal oscillator for seed clock generation . The oscillator is selfcontained . The only external component required is the crystal. The circuit is a series resonant circuit, eliminating the need for large on-board capacitors. This series resonant design calls for a series resonant crystal, but most crystals are characterized in parallel resonant mode. Physically, a parallel resonant crystal is no different from a series resonant crystal . Overall, a parallel crystal can be used with this device with a small frequency error due to the actual series resonant frequency of the parallel resonant crystal. A parallel specified crystal will exhibit an oscillatory frequency 100 ppm lower than the specified value. This translates to ineffectual kHz inaccuracies, which effectually will not effect the device . buffer switching from the internal phase-locked loop, the LCK4972A provides separate power supplies for the internal PLL (VDDA) and for the output buffers (VDDO). In a digital system environment, besides this isolation technique, it is highly recommended that both VDDA and VDD power supplies be filtered to reduce the random noise as much as possible. Figure 9 illustrates a typical power supply filter scheme . Due to its susceptibility to noise with spectral content in this range, a filter for the LCK4972A should be designed to target noise in the 100 kHz to 10 MHz range. The RC filter in Figure 9 will provide a broadband filter with approximately 100:1 attenuation for noise with spectral content above 20 kHz . More elaborate power supply schemes may be used to achieve increased power supply noise filtering . 3 .3 V Table 7. Crystal Recommendations Parameter Rs = 512-10 12 Value Crystal Cut Resonance Functional AT Cut Series Resonance) Frequency Tolerance Frequency/Temperature Stability Operating Range Shunt Capacitance Equivalent Series Resistance (ESR) Correlation Drive Level Aging 75 ppm at 25 C 150 ppm at 0 C-70 C 0 C-70 C 5 pF-7 pF 50 t2-80 tl max VDDA 0.01 RF 1 22 RF y LCK4972A VDD 0 .01 RF_t 2344 (F) r.1 Figure 9. Power Supply Filter 100 pW I 5 ppm/year (first 3 years) 1 . Consult the On-Board Crystal Oscillator section for details on parallel versus series crystals . The LCK4972A is not designed to be a synthesizer with a fixed input frequency, but a clock driver capable of generating outputs with programmable frequency relationships . Because of this intent, the crystal input frequency is a function of the output frequency. When the external feedback to the PLL is enabled, choose a crystal equal in frequency to the fed-back signal . Power Supply Filtering The LCK4972A is a mixed-signal product which is susceptible to random noise, especially when this noise is on the power supply pins. To isolate the output Agere Systems Inc. LCK4972A LowVoltage PLL Clock Driver Driving Transmission Lines The output drivers of the LCK4972A were designed for the lowest impedance possible for maximum flexibility. The LCK4972A's 10 tl impedance, the drivers can accommodate either parallel or series terminated transmission lines. Point-to-point distribution of signals is the preferred method in today's high-performance clock networks . Series-terminated or parallel-terminated lines can be used in a point-to-point scheme . The parallel configuration terminates the signal at the end of the line with a 50 tl resistance to VDD/2 . Only one terminated line can be driven by each output of the LCK4972A due to the high level of do current drawn . In a series-terminated case, there is no do current draw, and the outputs can drive multiple seriesterminated lines. Figure 10 shows these scenarios . 11 AdLib OCR Evaluation LCK4972A Low-Voltage PLL Clock Driver Functional Description (continued) 3.0 Driving Transmission Lines (continued) . ' IN 2 .5 LCK4972A ; OUTPUT BUFFER ' 2.0 w C7 Rs = 43 S2 -VA- Zo = 50 S2 OUTA Z LCK4972A ; OUTPUT ' BUFFER ' ' IN >n O 1 .5 1 .0 0.5 Rs = 43 S2 Zo = 50 n OUTBO 2 , 4 Zo = 50 S2 " ------- " Preliminary Data Sheet December 2002 Rs=43 n OUTB1 Z 6 8 TIME (ns) 10 12 14 2341 (F) Figure 11 . Single vs. Dual Waveforms 2340 (F) r.1 Figure 10. Dual Transmission Lines The waveform plots of Figure 11 show the simulated results of a single output versus a two-line output. A 43 ps delta exists between the two differently loaded outputs that can be seen in Figure 11 . This implies that dual-line driving need not be used in order to maintain tight output-to-output skew. The step in Figure 11 shows an impedance mismatch caused when looking into the driver. The parallel combination in Figure 10 plus the output resistance does not equal the parallel combination of the line impedances. The voltage wave down the lines will equal the following : LCK4972A ; OUTPUT ' BUFFER ' ' Rs = 36 S2 vv Zo = 50 S2 Z >n 7 Zo = 50 S2 " Rs=36n Z 7n+36n 1136n=50n 1150n 25 S2 = 25 n 2342 (F) r.1 Figure 12. Optimized Dual Transmission Lines VL = VS (Zo/RS + Ro + Zo) = 3.0 (25/53 .5) = 1 .4 V The voltage will double at the load-end to 2.8 V, due to the near-unity reflection coefficient . It then continues to increment towards 3.0 V in one-round trip delay steps (4 ps). This step will not cause any false clock triggering, but some may not want these reflections on the line. Figure 12 shows a possible configuration in order to eliminate these reflections . In this scenario, the series terminating resistors are reduced so the line impedance is matched when the parallel combination is added to the output buffer. 12 Agere Systems Inc. AdLib OCR Evaluation LCK4972A LowVoltage PLL Clock Driver Preliminary Data Sheet December 2002 Functional Description (continued) Output Freeze Circuitry The new green classification for computers requires unique power management. The LCK4972A's individual output enable control allows software to implement unique power management. A serial interface was created to eliminate individual output control at the cost of one pin per output. The freeze control logic provides a mechanism for the LCK4972A's clock inputs to be stopped in the logic 0 state. The freeze mechanism allows serial loading of the 12-bit serial input register. This register contains one programmable freeze enable bit for 12 of the 14 output clocks. The Qc0 and QFB outputs cannot be frozen with the serial port, which prevents possible lock-up situations if there is an error in the serial input register. The user can also program a freeze by writing 0 to the respective freeze bit . Likewise, it can be programmability unfrozen by writing a 1 to that same bit . Freeze logic cannot force a recently frozen clock to a logic 0 state before the time which it would normally transition to that state. The logic will only maintain the frozen clock in logic 0. Similarly, the logic will not force a recently frozen clock to logic 1 before the time it would normally transition there. When the clock would normally be in a logic 0 state, the logic re-enables the unfrozen clock, eliminating the possibility of runt clock pulses . The user may write to the serial input register by supplying a logic 0 start bit followed (serially) by 12 NRZ freeze bits through Frz_Data. The period of the Frz_Clk signal equals the period of each Frz_Data bit. The timing should be such that the LCK4972A is able to sample each Frz-Data bit with the rising edge of the Frz-Clk (free0running) signal . START BIT I DO I D1 I D2 I D3 I D4 I D5 I D6 I D7 I D8 I D9 I D10 I D11 2343 (F) Figure 13. Freeze Data Input Protocol Agere Systems Inc. 13 AdLib OCR Evaluation LCK4972A Low-Voltage PLL Clock Driver Preliminary Data Sheet December 2002 Absolute Maximum Ratings Stresses which exceed the absolute maximum ratings can cause permanent damage to the device . These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods of time can adversely affect device reliability. Table 8. Absolute Maximum Ratings Parameter Supply Voltage Input Voltage Input Current Storage Temperature Range Symbol VDD VI IIN Tst9 I I Min Max -0.3 -0.3 -40 4 .6 VDD + 0.3 20 125 I Unit V V mA C I Electrical Characteristics Table 9 . PILL Input Reference Characteristics (TA = -40 C to 85 C) Parameter TCLK Input Rise/Fall Reference Input Frequency Reference Input Duty Cycle Crystal Oscillator Frequency I Symbol Condition Min Max Unit tr, tf fret trefDC txtal ? -1 25 3.0 1 75 ns MHz I I 10 I 25 I % MHz 1 . Maximum input reference frequency is limited by VCO lock range and the feedback driver or 100 MHz . Minimum input reference frequency is limited by the VCO lock range and the feedback divider. 2. See On-Board Crystal Oscillator on page 11 section for more crystal information . do Characteristics Table 10. do Characteristics (TA = -40 C to 85 C, VDD = 3.3 V 5%) Parameter Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Current Maximum Supply Current Analog VDD Current Input Capacitance Power Dissipation Capacitance Symbol I VIH VIL VOH VOL Ilrv IDD IDDA CIN Cpd Condition IOH = -24 mAl IOL = 24 mAl 2 All VDD pins VDDA pin only3 I Per output Min I 2 .0 2.4 - I TO 130 60 25 I Max Unit 3.6 0.8 0.5 120 160 85 4 - V V V V pA mA mA pF I pF 1 . The LCK4972A inputs can drive a series of parallel terminated transmission lines on the incident edge . 2. Inputs have pull-up/pull-down resistors which affect input current. 3. Qa = Qb = Qc = 50 MHz, unoladed outputs . 14 Agere Systems Inc. AdLib OCR Evaluation LCK4972A LowVoltage PLL Clock Driver Preliminary Data Sheet December 2002 Electrical Characteristics (continued) ac Characteristics Table 11 . ac Characteristics (TA = -40 C to 85 C, VDD = 3.3 V 5%)1, 2 Parameter Input Reference Frequency: .4 feedback =6 feedback =8 feedback =10 feedback =12 feedback =16 feedback -24 feedback . 32 feedback Input Reference Frequency in PLL Bypass Mode3 VCO Frequency Range4 Crystal Internal Frequency Ranges Output Frequency: -2 feedback .4 feedback =6 feedback =8 feedback =10 feedback =12 feedback =16 feedback -20 feedback . 24 feedback Serial Interface Clock Frequency Reference Input Duty Cycle CCLKx Input Rise/Fall Time Propagation Delay (static phase offset) CCLKx or FB IN Output-to-Output Skew Output Duty Cycle Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-Cycle Jitter (RMS 1(7) Period Jitter (RMS 1(7) I/O Phase Jitter (RMS 1(y) PLL Closed Loop Bandwidth Maximum PLL Lock Time 1. 2. 3. 4. 5. Symbol Condition fREF PLL locked fREF PLL bypass PLL locked fvc0 fXTAL WAX fSTOP_CLK 20% to 80% PLL locked fREFDC tR, tF t(O) tSK(O) DC tR, tF tPLZ, HZ tPZL, LZ UIT(CC) UIT(PER) tJIT(O) I BW tLOCK I 20% to 80% I Min Typ Max 50.0 33.3 25.0 20.0 16.6 12.5 8.33 6.25 150 10 - 120.0 80.0 60.0 48.0 40.0 30.0 20.0 15.0 TBD 500 25 100 .0 50.0 33.3 25.0 20.0 16.6 12.5 10.0 8.33 25 - 150 240 .0 120.0 80.0 60.0 48.0 40.0 30.0 24.0 20.0 20 75 1 .0 - 47 0.1 - 250 50 53 1 .0 8 8 100 TBD TBD TBD I 10 I - I Unit MHz MHz MHz MHz MHz MHz % ns ps ps % ns ns ns ps ps ps kHz ms All ac characteristics are design targets and subject to change upon device characterization . ac characteristics apply for parallel output termination of 50 12 to VTT. In bypass mode, the LCK4972A divides the input reference clock. The input reference frequency must match the VCO lock range divided be the total feedback divider ratio : fREF = fVCO = (M x VCO SEL) . The crystal frequency range must both meet the interface frequency range and VCO lock range divided by the feedback divider ratio : fXTAL(min, max) = fvCO(min, max) = (M x VCO SEL) and 10 MHz < NTAL < 25 MHz. Agere Systems Inc. 15 AdLib OCR Evaluation Preliminary Data Sheet LCK4972A Low-Voltage PLL Clock Driver December 2002 Outline Diagram 52-pin TQFPT package outline . All dimensions are in millimeters . 1 .00 REF 0 .25 GAGE PLANE ~ 'P I 4TING PLANE I ~I 10 I~ 0 .45/0 .75 DETAIL A 13 14 26 DETAIL A L DETAIL B 0 .09/0 .20 1 .00 0 .05 0 .22/0 .38 jjj 11 0 65 TYP - 0 .08 0 1 .20 MAX 0.05/0 .15 SEATING PLANE 0 .08 DETAIL B PowerPC is a registered trademark of International Business Machines Corporation . Pentium is a registered trademark of Intel Corporation . For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http ://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc ., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA : Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN : (886) 2-2725-5858 (Taipei) EUROPE : Tel. (44) 1344 296 400 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice . No liability is assumed as a result of their use or application . Agere, Agere Systems, and the Agere logo are trademarks of Agere Systmes Inc . Copyright (c) 2002 Agere Systems Inc . All Rights Reserved December 2002 DS03-041 LCK ere s a 8 - y te ms s