a8e
re
systems
LCK4972A
Low-Voltage
PLL
Clock
Driver
Preliminary
Data
Sheet
December
2002
Features
.
Fully
integrated
PLL
.
. Output
frequency
up
to
240
MHz
.
. Compatible
with
PowerPC©
and
Pentiume
microprocessors
.
.
52-pin
TQFPT
.
. 3
.3
V
power
supply
.
.
Pin
compatible
with
972
type
devices
.
.
±100
ps
typical
cycle-to-cycle
jitter
.
. Output
skews
of
less
than
250
ps
.
Description
Agere
Systems'
LCK4972A
is
a 3
.3
V
PLL-based
clock
driver
for
high-performance
RISC
or
CISC
processor-based
systems
.
The
LCK4972A
has
output
frequencies
of
up
to
240
MHz
and
skews
of
less
than
250
ps,
making
it
ideal for
synchronous
systems
.
The
LCK4972A
contains
12 low-skew
outputs
and a
feedback/sync
output
for
flexibility
and
simple
implementation
.
There
is
a
robust
level
of
frequency
programmability
between
the
12 low-skew
outputs
in
addition
to
the
input/output
relationships
.
This allows
for
very
flexible
programming
of
the
input
reference
versus
the output
frequency
.
The
LCK4972A
contains
a
flexible
output
enable
and
disable
scheme
.
This
helps
execute
system
debug
as
well
as
offer
multiple
powerdown
schemes,
which
meet
green-class
machine
requirements
.
The
LCK4972A
features
a power-on
reset
function,
which
automatically
resets
the
device
on powerup,
providing
automatic
synchronization
between
QFB
and
other
outputs
.
The
LCK4972A
is
3
.3
V
compatible
and
requires
no
external
loop
filters
.
It
has
the
capability
of
driving
50
tl
transmission
lines
.
Series
terminated
lines
have
the
ability
of
driving
two
50
tl
lines
in
parallel,
effectively
doubling
the
fanout
.
AdLib OCR Evaluation
LCK4972A
Low-Voltage
PLL
Clock
Driver
Preliminary
Data
Sheet
December
2002
Pin
Information
Pin
Diagram
Vss
MROEB
Frz
Clk
Frz
Data
fselFB2
PLL
EN
Ref
Sel
TCLK
Sel
TCLKO
TCLK1
xtal1
xtal2
VDDA
75
I
o 0
00
o
°
cc
cc
cc
a)
a)
a) a)
> >
c~
>
c~
>
c~
>
c~
w w w
w
52
51
50
49
48 47
46
45
44
43 42
41
40
1
0
39
2
38
337
4 36
5 35
6 34
7
LCK4972A
33
8 32
9
31
10 30
11
29
12 28
13 27
14 15 16 17 18 19 20 21 22 23
24
25
26
~C
!A
CID
O
N O
O
O
!A
U
V >
°o
a)
0o
c~
>
>
>I
>
w
<n
>
75
c
'~ C7
Note
:
All
inputs
have
internal
pull-up
resistors
(50
kn)
except
for
xtal1
and
xtal2
.
Figure
1
.
52-Pin
TQFPT
Vss
Qb0
VDDO
Qb1
Vss
Qb2
VDDO
Qb3
Ext
FB
Vss
QFB
VDDI
fselFBO
2331
(F)
r .1
2
Agere
Systems
Inc
.
AdLib OCR Evaluation
Preliminary
Data
Sheet
December
2002
LCK4972A
Low
Voltage
PLL
Clock
Driver
Pin
Information
(continued)
Pin
Descriptions
Table
1
.
Pin
Descriptions
Pin
Symbol
Type
I/O
Description
1,
15,
Vss
Ground
-
Ground
.
24,
30,
35,
39,
47,51
2
MROEB
LVTTL
I
Master
Reset
and
Output
Enable
Input
.
Note
:
When
MR/OE
is
set
high,
the
PLL
will
have been
disturbed
and
the
outputs
will
be
at
an
indeterminate
frequency
until
MR/OE
is
relocked
.
3
Frz
Clk
LVTTL
I
Freeze
Mode
.
4
Frz
Data
LVTTL
I
Freeze
Mode
.
5
fselFB2
LVTTL
I
Feedback
Output
Divider
Function
Select
.
This
input,
along
with pins
fseIFB0
and
fselFB1,
controls
the
divider
function
of
the
feedback
bank
of
outputs
.
See
Table
3
for
more
details
.
6
PLL
EN
LVTTL
I
PLL
Bypass
Select
.
0
=
The
internal
PLL
is
bypassed
and
the
selected
reference
input
provides
the
clocks
to
operate
the
device
.
1
=
The
internal
PLL
provides
the
internal
clocks
to
operate
the device
.
7
Ref_Sel
LVTTL
I
Reference
Select Input
.
The
Ref_Sel
input
controls
the
reference
input
to
the
PLL
.
0
=
The
input
is
selected
by
the
TCLK_Sel
input
.
1
=
The
PCLK
is
selected
.
8
TCLK_Sel LVTTL
I
TTL
Clock
Select Input
.
The
TCLK_Sel
input
controls
which
TCLK
input
will
be
used
as
the reference
input
if
Ref
Sel
is
set
to
0
.
0
=
TCLKO
is
selected
.
1
=
TCLK1
is
selected
.
9,10
TCLK[0
:1]
LVTTL
I
LVTLL
Reference
Input
.
These
inputs
provide
the reference
frequency
for
the
internal
PLL
when
selected
by
Ref
Sel
and
TCLK
Sel
.
11
xtal1
LVTTL
I
Xtal
Reference
Input
.
This
input
provides
the reference
frequency
for
the
internal
PLL
when
selected
by Ref
Sel
.
12
xtal2
LVTTL
I
Xtal
Reference
Input
.
This
input
provides
the reference
frequency
for
the
internal
PLL
when
selected
by Ref
Sel
.
13
VDDA
Power
-
PLL
Power
.
14
Inv_Clk
LVTTL
I
Invert
Mode
.
This
input
only
affects
the
Qc
bank
.
0
=
All
outputs
of
the
Qc
bank
are
in
the
normal
phase
alignment
.
1
=
Qc2
and
Qc3
are
inverted
from
the
normal
phase
of
Qc0
and
Qc1
.
16, 18,
Qc[3
:0]
LVTTL
O
Clock
Output
.
These
outputs,
along
with
the
Qa[0
:3],
Qb[0
:3],
and
QFB
21,23
outputs,
provide
numerous
divide
functions
determined
by
the
fsela[0
:3],
fselb[0
:3],
and
the
fselFB[0
:2]
See
Table
2
and
Table
3
for
more
details
.
17,
22,
VDDO
Power
-
Output
Buffer
Power
.
33, 37,
45,49
19,20
fselc[1
:0]
LVTTL
I
Output
Divider
Function
Select
.
Each
pair
controls
the
divider function
of
the
respective
bank
of
outputs
.
See
Table
2
for
more
details
.
Agere
Systems
Inc
.
AdLib OCR Evaluation
LCK4972A
Low-Voltage
PLL
Clock
Driver
Preliminary
Data
Sheet
December
2002
Pin
Information
(continued)
Pin
Descriptions
(continued)
Table
1
.
Pin
Descriptions
(continued)
Pin
Symbol
Type
I/O
Description
25
QSync
LVTTL
O
PLL
Lock
Indicator
.
0 =
ThePLL
is
attempting
to
acquire
lock
.
1
=
This
output
indicates
that
the
internal
PLL
is
locked
to
the
reference
signal
.
Note
:
If
there
is
no
activity
on
the
selected
reference
input,
QSync
may
not
accurately
reflect
the
state
of
the
internal
PLL
.
This
pin
will
drive
logic,
but
not
Thevenin
terminated
transmission
lines
.
It
is
always
active
and
does
not
go
to
a high-impedance
state
.
QSync
provides
TEST
MODE
information
when
PLL
EN
is
set
to
0
.
26
fselFB1
LVTTL
I
Feedback
Output
Divider
Function
Select
.
This
input,
along
with
pins
fselFB1
and
fselFB2,
controls
the
divider
function
of
the
feedback
bank
of
outputs
.
See
Table
3
for
more
details
.
27
fselFBO
LVTTL
I
Feedback
Output
Divider
Function
Select
.
This
input,
along
with
pins
fselFBO
and
fselFB2,
controls
the
divider
function
of
the
feedback
bank
of
outputs
.
See
Table
3
for
more
details
.
28
VDDI
Power
-
PLL
Power
.
29
QFB
LVTTL
O
Clock
Output
.
This
output,
along
with
the
Qa[0
:3]
and
Qc[0
:3]
outputs,
provides
numerous
divide
functions
determined
by
the
fsela[0
:3],
fselb[0
:3],
and
the
fselFB[0
:2]
.
See
Table
2
and
Table
3
for
more
details
.
31
Ext
FB
LVTTL
I
PLL
Feedback
Input
.
This
input
is
used
to
connect
one
of
the
clock
outputs
(usually
QFB)
to
the
feedback
input
of
the
PLL
.
32, 34,
Qb[3
:0]
LVTTL
O
Clock
Output
.
These
outputs,
along
with
the
Qa[0
:3],
Qc[0
:3],
and
QFB
36,38
outputs,
provide
numerous
divide
functions
determined
by
the
fsela[0
:3],
fselb[0
:3],
and
the
fselFB[0
:2]
.
See
Table
2
and
Table
3
for
more
details
.
40,41
fselb[1
:0]
LVTTL
I
Output
Divider
Function
Select
.
Each
pair
controls
the
divider function
of
the
respective
bank
of
outputs
.
See
Table
2
for
more
details
.
42,43
fsela[1
:0]
LVTTL
I
Output
Divider
Function
Select
.
Each
pair
controls
the
divider function
of
the
respective
bank
of
outputs
.
See
Table
2
for
more
details
.
44, 46,
Qa[3
:0]
LVTTL
O
Clock
Output
.
These
outputs,
along
with
the
Qb[0
:3],
Qc[0
:3],
and
QFB
48,50
outputs,
provide
numerous
divide
functions
determined
by
the
fsela[0
:3],
fselb[0
:3],
and
the
fselFB[0
:2]
.
See
Table
2
and
Table
3
for
more
details
.
52
VCO
Sel
LVTTL
I
VCO
Frequency
Select
Input
.
This
input
selects
the
nominal
operating
range
of
the
VCO
used
in
the
PLL
.
0 =
The
VCO
range
is
100
MHz-240
MHz
.
1
=
The
VCO
range
is
200
MHz-480
MHz
.
Agere
Systems
Inc
.
AdLib OCR Evaluation
Preliminary
Data
Sheet
December
2002
LCK4972A
Low
Voltage
PLL
Clock
Driver
Functional Description
Using
the
select
lines
(fsela[1
:0],
fselb[1
:0],
fselc[1
:0],
fselFB[2
:0]),
the
following
output
frequency
ratios
between
outputs
can be
obtained
:
M
1
:1
2
:1
3
:1
3
:2
4
:1
4
:3
5
:1
5
:2
5
:3
6
:1
6
:5
These
ratios
can
be
achieved
by
pushing
the
control
signal
low
one
clock
edge
before
the
coincident
edges
of
outputs
Qa
and
Qc
.
The
synchronization
output
indicates
when
these
rising
edges
will
occur
.
Selectability
of
feedback
frequency
is
independent
of
the
output
frequencies
.
Output
frequencies
can be
odd
or
even
multiples
of
the
input
reference
clock,
as
well
as
being
less
than
the
input
frequency
.
The
power-on
reset
function
is
designed
to
reset
the
system
after
powerup
for
synchronization
between
QFB
and
other
outputs
.
This
solves the
problem
of
resetting
if
fselFB2
is
held high
on
powerup
.
All
other
conditions
of
the
fsel
pins
automatically
synchronize
during
PLL
clock
acquisition
.
All
outputs
are
initialized
active
on
power
on
.
The
LCK4972A
independently
enables
each
output
through
a
serial
input
port
.
When
disabled
(frozen),
the
outputs
will
lock
in
the
low
state,
but
internal
state
machines
are
unaffected
.
When
re-enabled,
the
outputs
initialize
in
phase
and
synchronous
with
those
not
reactivating
.
This
freezing
only
happens
when
the
outputs
are
in
the
low
state,
preventing
runt
pulse
generation
.
Table
2
.
Function
Table
for
Qa,
Qb, and
Qc
fsela1
fsela0
Qa
fselb1
fselb0
Qb
fselc1 fselc0
Qc
0
0
.4
0 0
.4
0
0
:2
0
1
:6
0
1
:6
0
1
:4
1
0
.8
1
0
.8
1
0
:6
1
I
1
I
:12
I
I
1
I
1
I
.10I
I
1
I
1
I
:8I
Table
3
.
Function
Table
for
QFB
fseIFB21 fselFB1
fselFBO
QFB
000
.4
0 0
1
.6
0
1
0
.8
0
1
1
=10
1
0 0
.8
1
0
1
=12
1 1
0
=16
1
I
1
I
1
I
-20
1
. If
fselFB2
is
set
to
1,
it
may
be necessary
to
apply
a
reset
pulse
after
powerup
in
order
to
ensure
synchronization
between
the
QFB
and
other
inputs
.
Table 4
.
Function
Table
for
Logic
Selection
Control
Pin
Logic
0
Logic
1
VCO
Sel
VCO/2
VCO
Ref
Sel
TCLK
Xtal
(PECL)
TCLK
Sel
TCLKO
TCLK1
PLL
EN
BypassPLL
Enable
PLL
MR/OE
Master
Reset/
Output
High-Z
Enable
Outputs
Inv_Clk Noninverted
Qc2,
Qc3
Inverted
Qc2,
Qc3
Agere
Systems
Inc
.
5
AdLib OCR Evaluation
LCK4972A
Low-Voltage
PLL
Clock
Driver
Preliminary
Data
Sheet
December
2002
Functional
Description
(continued)
F
RE
TC
fSi
Fr
Qa0
Qa1
Qa2
Qa3
Qb0
Qb1
Qb2
Qb3
Qc0
Qc1
Qc2
Qc3
QFB
QSync
2332
(F)
Figure 2
.
Logic
Diagram
6
Agere
Systems
Inc
.
AdLib OCR Evaluation
Preliminary
Data
Sheet
December
2002
LCK4972A
Low
Voltage
PLL
Clock
Driver
Functional
Description
(continued)
Device
Programming
The
LCK4972A
contains
three
independent
banks
of
four
outputs
as
well
as
an
independent
PLL
feedback
output
.
The
possible
configurations
make
Agere
Systems
Inc
.'s
LCK4972A
one
of
the
most
versatile
frequency
programming
devices
.
Table
5
shows
various
selection
possibilities
.
Table 5
.
Programmable
Output
Frequency
Relationships
for
Qa,
Qb, and
Qc
(VCO
Sel
=
1)
v
°v
Qa
M
°M
Qb
2
°,
Qc
4)
42
4)
42
Z
42
Z
42
4)
42
4)
42
0 0
VCO/4
0 0
VCO/4
0 0
VCO/2
0
1
VCO/6
0
1
VCO/6
0
1
VCO/4
1
0
VCO/8
1
1
1
0
VCO/8
1
1
1
0 VC01/6
1
I
1
1
VCO/12
1
1
1
1
1
1
VCO/101
1
1
1
1
1
VC8/8I
Table 6
.
Programmable
Output
Frequency
Relationships
for
QFB
(VCO
Sel
=
1)
fselFB2
fselFB1
fselFBO
QFB
000
VCO/4
0 0
1
VCO/6
0
1
0
VCO/8
0
1 1
VCO/10
1
0 0
VCO/8
1
0
1
VCO/12
1 1
0
VCO/16
1 1 1
VCO/20
To
determine
the
relationship
between
the
three
banks,
compare
their
divide
ratios
.
Forexample,
if
a
ratio
of
5
:3 :2
is
desired,
set
Qa
to
=10,
Qb
to
=6,
and
Qc
to
=4
.
These
selections
would
yield
a 5
:3 :2
ratio
.
For
low
frequency
circumstances,
the
VCO
Sel
pin
allows
the option
of
an
additional
-2
to
be
added
to
the
clock
path
.
This
pin
maintains the output
relationships,
but
provides
an extended
clock
range
for
the
PLL
.
The
feedback
output
is
matched
to
the
input
reference
frequency
after
the
output
frequency
relationship
is
set
and
VCO
is
in
a
stable
range
.
Only an
external
feedback
is
provided
to
the
PLL
in
the
LCK4972A
device
to
optimize
flexibility
.
If,
in
the
previous
example,
the
input
reference
frequency
were
equal
to
the
lowest output
frequency,
the output
would
be
set
to
=10
mode
.
The
fselFB2
input
could
be
asserted
to half
the
frequency
if
the
needed
feedback
frequency
is
half
of
the lowest
frequency
output
.
This
multiplies
the
output
frequencies
by a
factor
of two,
relative
to
the
input
reference
frequency
.
Assume
the
previously
mentioned
5
:3 :2
ratio
with
the
highest
output
frequency
of
100
MHz
.
If
the
only
available
reference
frequency
is
50
MHz,
the
setup
of
Figure
3
can
be
used
.
The
device
provides
100
MHz,
66
MHz,
and
40
MHz
outputs,
all
generated
from
the
50
MHz
source
.
Figure
4
and
Figure
5
also
show
possible
configurations
of
the
LCK4972A
.
LCK4972A
0
fsela0
0
fselal
Qa
4
100
MHz
1
fselb0
1
fselbl
Qb
4
40
MHz
0
fselc0
1
fselcl
Qc
4 66
.66
MHz
0
fse!FBO
1
fseIFB1
QFB
50
MHz
0
fselFB2
50
MHz
Input
Ref
Ext_FB
VCO
=
400
MHz
2334
(F)
r .1
Figure
3
.
100
MHz
from50
MHz
Example
LCK4972A
0
fsela0
Oa
4
60
MHz
(PROCESSOR)
0
fselb0
0
fselbl
Qb
4
60
MHz
(PROCESSOR)
1
fselc0
1
fselc1
QC
4
30
MHz
(PCI)
1
fseIFBO
1
fselFB1
QFB
24
MHz
(FLOPPY
DISK
CLK)
0
fselFB2
24
MHz
Input
Ref
Ext
FB
2335
(F)
r .1
Figure
4
.
Pentium
CompatibleClocks
Example
Agere
Systems
Inc
.
7
AdLib OCR Evaluation
LCK4972A
Low-Voltage
PLL
Clock
Driver
Preliminary
Data
Sheet
December
2002
Functional
Description
(continued)
Device
Programming
(continued)
LC
K4972A
1
fsela0
1
fsela1
0
fselb0
1
fselbl
1
fselc0
1
fselcl
1
fseIFBO
1
fselFB1
1
fselFB2
4
Qa
33
MHz
(PCI)
4
Qb
50
MHz
(PROCESSOR)
Qc
r~
50
MHz
(PROCESSOR)
QFB
r---l
20
MHz
(ETHERNET)
20
MHz
Input
Ref
Ext_FB
2336
(F)
r .1
Figure
5
.
20
MHz
Source
Example
The
Lnv_Clk
input
pin,
when
asserted,
will
invert
the
Qc2
and
Qc3
outputs
.
This
inversion
does
not
affect
the
output-output
skew
of
the
device
and
allows
for
the
development
of
180°
phase-shifted clocks
.
This
output
can
also
be used as a feedback
output
or
routed
to
a
second
PLL
to
generate
early/late
clocks
.
Figure
5 on
page
8
shows
a
180°
phase-shift
configuration
.
SYNC
Output
When
the
output
frequencies
are not
integer
multiples
of
each
other,
there
is
a
need
for
a
signal
for
synchronization
purposes
.
The
SYNC
output
is
designed
to
address
this
need
.
The
Qa
and
Qc
banks
of
outputs
are
monitored
by
the
device,
and
a
low-going
pulse
(one
period
in
duration,
one
period before
the
coincident
rising
edges
of
Qa
and
Qc)
is
provided
.
The
duration
and
placement
of
the
pulse
is
dependent
on
the
highest
of
Qa
and
Qc
output
frequencies
.
The
timing
diagram,
(Figure
8 on
page
10)
shows
the
various
waveforms
for
SYNC
.
Note
:
SYNC
is
defined
for
all
possible
combinations
of
Qa
and
Qc,
even
though
the
lower
frequency
clock
should
be used as a
synchronizing
signal
in
most
cases
.
8
Agere
Systems
Inc
.
AdLib OCR Evaluation
Preliminary
Data
Sheet
December
2002
LCK4972A
Low
Voltage
PLL
Clock
Driver
FunctionalDescription
(continued)
SYNC
Output
(continued)
0
0
0
0
1
0
0
0
0
1
LCK4972A
fsela0
fselal
fselb0
fselbl
fselc0
fselcl
fseIFB0
fseIFB1
fseIFB2
Inv
Clk
Input
Ref
Ext
FB
LCK4972A
0
fsela0
Qa
4 66
MHz
1
fsela1
0
fselb0
Qb
4 66
MHz
1
fselbl
1
fselc0
QC
2 66
MHz
1
fselcl
0 fseIFB0
Qc
2 66
MHz
0
fseIFB1
0 fseIFB2
QFB
0
Inv-Clk
Qa
4
33
MHz
SHIFTED
90°
Qb
4
33
MHz
SHIFTED
90-
QC
4
33
MHz
SHIFTED
90°
QFB
66
MHz
66
MHz
66
MHz
33
MHz
SHIFTED
90°
2337
(F)
r .1
66
MHz
100
75
50
25
a
0
-25
-50
-75
-100
Input
Ref
Ext
FB
Figure
6
.
Phase
Delay
Example
Using
Two
LCK4972As
Qc3 Qc2
Qc1
Qc0 Qb3
Qb2
Qb1 Qb0
Qa3 Qa2
Qal
Qa0
QFB
2338
.a
(F)
r .1
Figure 7
.
Typical
Skews
Relative
to
QA
Agere
Systems
Inc
.
9
AdLib OCR Evaluation
LCK4972A
Low-Voltage
PLL
Clock
Driver
Preliminary
Data
Sheet
December
2002
Functional
Description
(continued)
SYNC
Output
(continued)
rvcO
1
:1
MODE
Qa
Qc
Sync
2
:1
MODE
Qa
Qc
Sync
3
:1
MODE
Qc(-2)
Qa(-6)
Sync
3
:2
MODE
Qa(-4)
Qc(-6)
Sync
4
:1
MODE
Qc(-2)
Qa(-8)
Sync
4
:3
MODE
Qa(-6)
Qc(-8)
Sync
6
:1
MODE
Qa(-12)
Qc(-2)
Sync
2333
(F)
Figure 8
.
LCK4972A
Timing
10
Agere
Systems
Inc
.
AdLib OCR Evaluation
Preliminary
Data
Sheet
December
2002
LCK4972A
Low
Voltage
PLL
Clock
Driver
Functional
Description
(continued)
On-Board
Crystal
Oscillator
The
LCK4972A
features
an
on-board
crystal
oscillator
for
seed
clock
generation
.
The
oscillator
is
self-
contained
.
The
only
external
component
required
is
the
crystal
.
The
circuit
is
a
series
resonant
circuit,
eliminating
the
need
for
large
on-board
capacitors
.
This series
resonant
design
calls
for
a
series
resonant
crystal,
but
most
crystals
are
characterized
in
parallel
resonant
mode
.
Physically,
a
parallel
resonant
crystal
is
no
different
from
a
series
resonant
crystal
.
Overall,
a
parallel
crystal
can
be
used
with
this
device
with
a
small
frequency
error
due
to
the
actual
series
resonant
frequency
of
the
parallel
resonant
crystal
.
A
parallel
specified
crystal
will
exhibit
an
oscillatory
frequency
±100
ppm
lower
than
the specified
value
.
This
translates
to
ineffectual
kHz
inaccuracies,
which
effectually
will
not
effect
the
device
.
Table 7
.
Crystal
Recommendations
Parameter
Value
Crystal
Cut
Functional
AT
Cut
Resonance
Series
Resonance)
Frequency
Tolerance
±75
ppm
at
25°C
Frequency/Temperature
Stability
±150
ppm
at
0
°C-70
°C
Operating
Range
0
°C-70
°C
Shunt
Capacitance
5
pF-7
pF
Equivalent
Series
Resistance
(ESR)
50
t2-80
tl
max
Correlation
Drive
Level
100
pW
Aging
I
5
ppm/year
(first
3
years)
1
.
Consult
the
On-Board
Crystal Oscillator
section
for
details
on
par-
allel
versus
series
crystals
.
The
LCK4972A
is
not
designed
to
be a
synthesizer
with
a
fixed input
frequency,
but
a
clock
driver
capable
of
generating
outputs
with
programmable
frequency
relationships
.
Because
of
this
intent,
the
crystal
input
frequency
is
a
function
of
the
output
frequency
.
When
the
external
feedback
to
the
PLL
is
enabled,
choose
a
crystal
equal
in
frequency
to
the
fed-back
signal
.
Power
Supply
Filtering
The
LCK4972A
is
a
mixed-signal
product
which
is
susceptible
to
random
noise,
especially
when
this
noise
is
on
the
power
supply
pins
.
To
isolate
the
output
buffer
switching
from
the
internal
phase-locked
loop,
the
LCK4972A
provides
separate
power
supplies
for
the
internal
PLL
(VDDA)
and
for
the output
buffers
(VDDO)
.
In
a
digital
system
environment,
besides
this
isolation
technique,
it
is
highly
recommended
that
both
VDDA
and
VDD
power
supplies
be
filtered
to
reduce
the
random
noise
as
much
as
possible
.
Figure
9
illustrates
a
typical
power
supply
filter
scheme
.
Due
to
its
susceptibility
to
noise
with spectral
content
in
this
range,
a
filter
for
the
LCK4972A
should
be
designed
to
target
noise
in
the
100
kHz
to
10
MHz
range
.
The
RC
filter
in
Figure
9
will
provide
a
broad-
band
filter
with
approximately
100
:1
attenuation
for
noise
with spectral
content
above
20
kHz
.
More
elabo-
rate
power
supply
schemes
may
be
used
to
achieve
increased
power
supply
noise
filtering
.
3
.3
V
Rs
=
512-10
12
VDDA
0
.01
RF
1
22
RF
y
LCK4972A
VDD
Figure
9
.
Power
Supply
Filter
Driving
Transmission
Lines
0
.01
RF_t
2344
(F)
r .1
The
output
drivers
of
the
LCK4972A
were
designed
for
the
lowest
impedance
possible
for
maximum
flexibility
.
The
LCK4972A's
10
tl
impedance,
the
drivers
can
accommodate
either
parallel
or
series
terminated
transmission
lines
.
Point-to-point
distribution
of
signals
is
the
preferred
method
in
today's
high-performance
clock
networks
.
Series-terminated
or
parallel-terminated
lines
can be
used
in
a
point-to-point
scheme
.
The
parallel
configuration
terminates
the
signal
at
the
end
of
the
line
with
a
50
tl
resistance
to
VDD/2
.
Only
one
terminated
line
can
be
driven
by
each
output of
the
LCK4972A
due
to
the
high
level
of
do
current
drawn
.
In
a
series-terminated
case,
there
is
no
do
current
draw,
and
the
outputs
can
drive
multiple series-
terminated
lines
.
Figure
10
shows
these
scenarios
.
Agere
Systems
Inc
.
11
AdLib OCR Evaluation
LCK4972A
Low-Voltage
PLL
Clock
Driver
Preliminary
Data
Sheet
December
2002
Functional
Description
(continued)
Driving
Transmission
Lines
(continued)
LCK4972A
;
.
OUTPUT
'
BUFFER
'
Rs
=
43
S2
Zo=50
S2
IN
-V
A-
OUTA
Z
LCK4972A
;
OUTPUT
Zo
= 50
n
'
BUFFER
'
Rs
=
43
S2
'
OUTBO
,
IN
>n
Zo
=
50
S2
"
-------
"
OUTB1
Rs=43
n
Z
2340
(F)
r
.1
Figure
10
.
Dual
Transmission
Lines
The
waveform
plots of
Figure
11
show
the simulated
results
of
a
single
output
versus
a
two-line
output
.
A
43 ps
delta
exists
between
the
two
differently
loaded
outputs
that
can
be
seen
in
Figure
11
.
This
implies that
dual-line driving
need
not
be
used
in
order
to
maintain
tight
output-to-output
skew
.
The
step
in
Figure
11
shows
an
impedance
mismatch
caused
when
looking
into
the
driver
.
The
parallel
combination
in
Figure
10
plus
the
output
resistance
does
not
equal
the
parallel
combination
of
the
line
impedances
.
The
voltage
wave
down
the
lines
will
equal
the
following
:
VL
=
VS
(Zo/RS
+
Ro
+
Zo)
=
3
.0
(25/53
.5)
=
1
.4
V
The
voltage
will
double
at
the
load-end
to
2
.8 V,
due
to
the
near-unity
reflection
coefficient
.
It
then continues
to
increment
towards 3
.0
V
in
one-round
trip
delay steps
(4
ps)
.
This step
will
not
cause
any
false
clock
triggering,
but
some
may
not
want
these
reflections
on
the
line
.
Figure
12
shows
a
possible
configuration
in
order
to
eliminate
these
reflections
.
In
this
scenario,
the
series
terminating
resistors
are
reduced so
the
line
impedance
is
matched
when
the
parallel
combination
is
added
to
the output
buffer
.
3
.0
2
.5
2
.0
w
C7
1
.5
O
1
.0
0
.5
2341
(F)
Figure
11
.
Single
vs
.
Dual
Waveforms
LCK4972A
;
OUTPUT
'
BUFFER
'
'
Zo
=
50
S2
Rs
=
36
S2
vv
7
>n
Z
Zo=
50
S2
"
Rs=36n
Z
7n+36n
1136n=50n
1150n
25
S2
=
25
n
2342
(F)
r .1
Figure
12
.
Optimized
Dual
Transmission
Lines
12
Agere
Systems
Inc
.
2 4
6 8 10 12 14
TIME
(ns)
AdLib OCR Evaluation
Preliminary
Data
Sheet
LCK4972A
December
2002
Low
Voltage
PLL
Clock
Driver
Functional Description
(continued)
Output
Freeze
Circuitry
Thenew
green
classification for
computers
requires
unique
power
management
.
The
LCK4972A's
individual
output
enable
control
allows
software
to
implement
unique
power
management
.
A
serial
interface
was
created
to
eliminate
individual
output
control
at
the
cost of
one
pin
per output
.
The
freeze
control
logic
provides
a
mechanism
for
the
LCK4972A's
clock
inputs
to
be stopped
in
the
logic
0
state
.
The
freeze
mechanism
allows
serial
loading
of
the
12-bit
serial
input
register
.
This
register
contains
one
programmable
freeze
enable
bit
for
12
of
the
14
output clocks
.
TheQc0
and
QFB
outputs
cannot be
frozen
with
the
serial
port,
which
prevents
possible
lock-up
situations
if
there
is
an
error
in
the
serial
input
register
.
The
user
can
also
program
a
freeze
by
writing
0
to
the
respective freeze
bit
.
Likewise,
it
can
be
programmability
unfrozen
by
writing
a
1
to
that
same
bit
.
Freeze
logic
cannot
force
a
recently
frozen
clock
to
a
logic
0
state
before
the
time
which
it
would
normally
transition
to that
state
.
The
logic
will
only
maintain
the
frozen
clock
in
logic
0
.
Similarly,
the
logic
will
not
force
a
recently
frozen
clock
to logic
1
before
the
time
it
would
normally
transition
there
.
When
the
clock
would
normally
be
in
a
logic
0
state,
the
logic
re-enables
the
unfrozen
clock,
eliminating
the
possibility
of
runt
clock
pulses
.
The
user
may
write
to
the
serial
input
register
by
supplying
a
logic
0
start
bit
followed
(serially)
by 12
NRZ
freeze
bits
through
Frz_Data
.
The
period
of
the
Frz_Clk
signal
equals
the period
of
each
Frz_Data
bit
.
The
timing
should
be such
that
the
LCK4972A
is
able
to
sample
each
Frz-Data
bit
with
the
rising
edge
of
the
Frz-Clk
(free0running)
signal
.
START
BIT
I
DO
I
D1
I
D2
I
D3
I
D4
I
D5
I
D6
I
D7
I
D8
I
D9
I
D10
I
D11
Figure 13
.
Freeze Data
Input
Protocol
2343
(F)
Agere
Systems
Inc
.
13
AdLib OCR Evaluation
LCK4972A
Low-Voltage
PLL
Clock
Driver
Preliminary
Data
Sheet
December
2002
Absolute
Maximum
Ratings
Stresses
which
exceed
the
absolute
maximum
ratings
can
cause permanent
damage
to
the device
.
These
are
absolute
stress
ratings
only
.
Functional
operation
of
the device
is
not
implied
at
these
or
any
other
conditions
in
excess
of
those
given
in
the
operational
sections
of
the
data
sheet
.
Exposure
to
absolute
maximum
ratings
for
extended
periods
of time
can
adversely
affect
device
reliability
.
Table 8
.
Absolute
Maximum
Ratings
Parameter
Symbol
Min
Max
Unit
Supply
Voltage
VDD
-0
.3
4
.6
V
Input
Voltage
VI
-0
.3
VDD
+
0
.3
V
Input
Current
IIN
-
±20
mA
Storage
Temperature
Range
I
Tst9
I
-40
I
125
I
°C
Electrical
Characteristics
Table 9
.
PILL
Input
Reference
Characteristics
(TA
=
-40
°C
to
85
°C)
Parameter
Symbol
Condition
Min
Max
Unit
TCLK
Input
Rise/Fall
tr,
tf
- -
3
.0
ns
Reference
Input
Frequency
fret
-
-1
1
MHz
Reference
Input
Duty Cycle
trefDC
-
25 75
%
Crystal
Oscillator
Frequency
I
txtal
I
?
I
10
I
25
I
MHz
1
.
Maximum
input
reference
frequency
is
limited
by
VCO
lock
range and
the
feedback
driver
or
100
MHz
.
Minimum
input
reference
frequency
is
limited
by
the
VCO
lock
range and
the
feedback
divider
.
2
.
See
On-Board
Crystal
Oscillator
on
page
11
section
for
more
crystal
information
.
do
Characteristics
Table
10
.
do
Characteristics
(TA
=
-40
°C
to
85
°C,
VDD
=
3
.3
V
±
5%)
Parameter
Symbol
Condition
Min
TO
Max
Unit
Input
High
Voltage
VIH
-
2
.0
-
3
.6
V
Input
Low
Voltage
VIL
- - -
0
.8
V
Output
High
Voltage
VOH
IOH
=
-24
mAl
2
.4
- -
V
Output
Low
Voltage
VOL
IOL
=
24
mAl
- -
0
.5
V
Input
Current
Ilrv
2
- -
±120
pA
Maximum
Supply
Current
IDD
All
VDD
pins
-
130
160
mA
Analog
VDD
Current
IDDA
VDDA
pin
only3
-
60
85
mA
Input
Capacitance
CIN
- - -
4
pF
Power
Dissipation
Capacitance
I
Cpd
I
Per
output
I
-
I
25
I
-
I
pF
1
.
The
LCK4972A
inputs
can
drive
a
series of
parallel
terminated
transmission
lines
on
the
incident
edge
.
2
.
Inputs
have
pull-up/pull-down
resistors
which
affect
input
current
.
3
.
Qa
=
Qb
=
Qc=
50
MHz,
unoladed
outputs
.
14
Agere
Systems
Inc
.
AdLib OCR Evaluation
Preliminary
Data
Sheet
December
2002
LCK4972A
Low
Voltage
PLL
Clock
Driver
Electrical
Characteristics
(continued)
ac
Characteristics
Table
11
.
ac
Characteristics
(TA
=
-40
°C
to
85
°C,
VDD
=
3
.3
V
±
5%)1,
2
Parameter
Symbol
Condition
Min Typ
Max
Unit
Input
Reference
Frequency
:
fREF
PLL
locked
MHz
.4
feedback
50
.0
-
120
.0
=6 feedback
33
.3
-
80
.0
=8 feedback
25
.0
-
60
.0
=10
feedback
20
.0
-
48
.0
=12
feedback
16
.6
-
40
.0
=16
feedback
12
.5
-
30
.0
-24
feedback
8
.33
-
20
.0
.
32
feedback
6
.25
-
15
.0
Input
Reference
Frequency
in
PLL
Bypass
Mode3 fREF
PLL
bypass
- -
TBD MHz
VCO
Frequency
Range
4
fvc0
-
150
-
500
MHz
Crystal
Internal
Frequency
Ranges fXTAL
-
10
-
25
MHz
Output
Frequency
:
WAX
PLL
locked
MHz
-2 feedback 100
.0
-
240
.0
.4
feedback
50
.0
-
120
.0
=6
feedback
33
.3
-
80
.0
=8
feedback
25
.0
-
60
.0
=10
feedback
20
.0
-
48
.0
=12
feedback
16
.6
-
40
.0
=16
feedback
12
.5
-
30
.0
-20
feedback
10
.0
-
24
.0
.
24
feedback
8
.33
-
20
.0
Serial
Interface
Clock
Frequency
fSTOP_CLK
-
- -
20
MHz
Reference
Input
Duty
Cycle
fREFDC
-
25
-
75
%
CCLKx
Input
Rise/Fall
Time
tR,
tF
20%
to
80%
- -
1
.0
ns
Propagation
Delay
(static
phase
offset)
CCLKx
or t(O)
PLL
locked
-
±150
-
ps
FB
IN
Output-to-Output
Skew
tSK(O)
-
- -
250
ps
Output Duty
Cycle
DC
-
47
50 53
%
Output
Rise/Fall
Time
tR,
tF
20%
to
80%
0
.1
-
1
.0
ns
Output
Disable
Time
tPLZ,
HZ
-
- -
8 ns
Output Enable
Time
tPZL,
LZ
-
- -
8 ns
Cycle-to-Cycle
Jitter
(RMS
1(7)
UIT(CC)
-
- -
±100
ps
Period
Jitter
(RMS
1(7)
UIT(PER)
-
-
TBD
-
ps
I/O
Phase
Jitter
(RMS
1(y)
tJIT(O)
-
-
TBD
-
ps
PLL
Closed
Loop
Bandwidth
BW
-
- -
TBD
kHz
Maximum
PLL
Lock
Time
I
tLOCK
I
-
I
-
I
10
I
-
I
ms
1
.
All
ac
characteristics
are design
targets
and
subject
to
change
upon
device
characterization
.
2
.
ac
characteristics
apply
for
parallel
output
termination
of
50
12 to
VTT
.
3
.
In
bypass
mode,
the
LCK4972A
divides
the
input
reference
clock
.
4
.
The
input
reference
frequency
must
match
the
VCO
lock
range
divided
be
the
total
feedback
divider
ratio
:
fREF =
fVCO
=
(M x
VCO
SEL)
.
5
.
The
crystal
frequency
range
must
both
meet
the
interface
frequency range and
VCO
lock
range
divided
by
the
feedback
divider
ratio
:
fXTAL(min,
max)
=
fvCO(min,
max)
=
(M
x
VCO
SEL)
and
10
MHz
<
NTAL
<25
MHz
.
Agere
Systems
Inc
.
15
AdLib OCR Evaluation
LCK4972A
Low-Voltage
PLL
Clock
Driver
Outline
Diagram
52-pin
TQFPT
package
outline
.
All
dimensions
are
in
millimeters
.
13
10
Preliminary
Data
Sheet
December
2002
1
.00
REF
0
.25
GAGE
PLANE
~
'P
4TING
PLANE
I I
~I
I~
0
.45/0
.75
DETAIL
A
0
.09/0
.20
0
.22/0
.38
0
.08
0
DETAIL
A
L
DETAIL
B
1
.00
±
0
.05
jjj
1
.20
MAX
11
-
0
65
TYP
0
.05/0
.15
SEATING
PLANE
0
.08
PowerPC
is
a
registered
trademark
of
International
Business
Machines
Corporation
.
Pentium
is
a
registered
trademark
of
Intel
Corporation
.
DETAIL
B
For
additional
information,
contact
your
Agere
Systems
Account
Manager
or
the
following
:
INTERNET
:
http
://www
.agere
.com
E-MAIL
:
docmaster@agere
.com
N
.
AMERICA
:
Agere
Systems
Inc
.,
Lehigh
Valley Central
Campus,
Room
10A-301C,
1110American
Parkway
NE,
Allentown,
PA
18109-9138
1-800-372-2447,
FAX
610-712-4106
(In
CANADA
:
1-800-553-2448,
FAX
610-712-4106)
ASIA
:
Agere
Systems
HongKong
Ltd
.,
Suites
3201
&
3210-12,
32/F,
Tower
2,
The
Gateway,
Harbour
City,
Kowloon
Tel
.
(852)
3129-2000,
FAX
(852)
3129-2020
CHINA
:
(86)
21-5047-1212
(Shanghai),
(86)
755-25881122
(Shenzhen)
JAPAN
:
(81)
3-5421-1600
(Tokyo),
KOREA
:
(82)
2-767-1850
(Seoul),
SINGAPORE
:
(65)
778-8833,
TAIWAN
:
(886)
2-2725-5858
(Taipei)
EUROPE
:
Tel
.
(44)
1344
296400
Agere
Systems
Inc
.
reserves
the
right
to
make
changes
to
the
product(s)
or
information
contained
herein
without
notice
.
No
liability is
assumed
as a
result
of
their
use
or
application
.
Agere,
Agere
Systems, and the
Agere
logo
are
trademarks
of
Agere
Systmes
Inc
.
Copyright
©
2002
Agere
Systems
Inc
.
All
Rights
Reserved
s
y
s
te
ms
December
2002
a
-
ere
DS03-041
LCK
8
14 26
AdLib OCR Evaluation
