Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. I
11/09/99
IS61LV256 ISSI®
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.
FEATURES
• High-speed access times:
-- 8, 10, 12, 15, 20 ns
• Automatic power-down when chip is deselected
• CMOS low power operation
-- 345 mW (max.) operating
-- 7 mW (max.) CMOS standby
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three-state outputs
DESCRIPTION
The ISSI IS61LV256 is a very high-speed, low power,
32,768-word by 8-bit static RAM. It is fabricated using
ISSI's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields access times as fast as 8 ns maximum.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation is reduced to
50 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active
LOW Chip Enable (CE). The active LOW Write Enable
(WE) controls both writing and reading of the memory.
The IS61LV256 is available in the JEDEC standard 28-pin,
300-mil SOJ and the 450-mil TSOP (Type I) package.
32K x 8 LOW VOLTAGE
CMOS STATIC RAM OCTOBER 1999
FUNCTIONAL BLOCK DIAGRAM
A0-A14
CE
OE
WE
256 X 1024
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
IS61LV256 ISSI
®
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. I
11/09/99
PIN CONFIGURATION
28-Pin SOJ
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PIN CONFIGURATION
28-Pin TSOP (Type I)
PIN DESCRIPTIONS
A0-A14 Address Inputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Input/Output
Vcc Power
GND Ground
TRUTH TABLE
Mode WE CE OE I/O Operation Vcc Current
Not Selected X H X High-Z ISB1, ISB2
(Power-down)
Output Disabled H L H High-Z ICC
Read H L L DOUT ICC
Write L L X DIN ICC
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
VCC Power Supply Voltage Relative to GND –0.5 to +4.6 V
VTERM Terminal Voltage with Respect to GND –0.5 to +4.6 V
TBIAS Temperature Under Bias Com. –10 to +85 °C
Ind. –45 to +90
TSTG Storage Temperature –65 to +150 °C
PDPower Dissipation 1 W
IOUT DC Output Current ±20 mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
IS61LV256 ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
Rev. I
11/09/99
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Mi n. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –2.0 mA 2.4 —V
VOL Output LOW Voltage VCC = Min., IOL = 4.0 mA —0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.3 V
VIL Input LOW Voltage(1) –0.3 0.8 V
ILI Input Leakage GND ≤ VIN ≤ VCC Com. –11µA
Ind. –55
ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled Com. –11µA
Ind. –55
Notes:
1. VIL (min.) = –0.3V (DC); VIL (min.) = –2.0V (pulse width ≤ 2.0 ns).
VIH (max.) = VCC + 0.5V (DC); VIH (max.) = Vcc + 2.0V (pulse width ≤ 2.0 ns).
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 5 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
OPERATING RANGE
Range Ambient Temperature Speed VCC
Commercial 0°C to +70°C 8, 10, 12 3.3V, +10%, –5%
15, 20 3.3V ± 10%
Industrial –40°C to +85°C All 3.3V + 10%, –5%
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 ns
(2)
-10 ns
(2)
-12 ns -15 ns -20 ns
Sym. Parameter Test Conditions
Min.Max. Min.Max. Min. Max. Min. Max. Min.Max. Unit
ICC Vcc Dynamic Operating VCC = Max., CE = VIL Com. —120 —110 —100 —90 —80 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. —— —120 —110 —100 —90
ISB1TTL Standby Current VCC = Max., Com. —15 —10 —10 —10 —10 mA
(TTL Inputs) VIN = VIH or VIL Ind. —— —20 —20 —20 —20
CE ≥ VIH, f = 0
ISB2CMOS Standby VCC = Max., Com. —2—2—2—2—2mA
Current (CMOS Inputs) CE
≤
VCC – 0.2V, Ind. —— — 5—5—5—5
VIN > VCC – 0.2V, or
VIN
≤
0.2V, f = 0
Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Shaded area = PREPRODUCTION AVAILABILITY.
IS61LV256 ISSI
®
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. I
11/09/99
AC TEST LOADS
Figure 1. Figure 2.
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V
and Reference Levels
Output Load See Figures 1 and 2
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8 ns
(2)
-10 ns
(2)
-12 ns -15 ns -20 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tRC Read Cycle Time 8 —10 —12 —15 —20 —ns
tAA Address Access Time —8—10 —12 —15 —20 ns
tOHA Output Hold Time 2 —2—2—2—2—ns
tACE CE Access Time —8—10 —12 —15 —20 ns
tDOE OE Access Time —4—5—6—7—8ns
tLZOE
(3)
OE to Low-Z Output 0 —0—0—0—0—ns
tHZOE
(3)
OE to High-Z Output —4—5—5—6—6ns
tLZCE
(3)
CE to Low-Z Output 3 —3—3—3—3—ns
tHZCE
(3)
CE to High-Z Output —4—5—6—7—7ns
tPU
(4)
CE to Power-Up 0 —0—0—0—0—ns
tPD
(4)
CE to Power-Down —8—10 —12 —15 —20 ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3.0V and output loading specified in Figure 1.
2. Shaded area = PREPRODUCTION AVAILABILITY.
3. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100%
tested.
4. Not 100% tested.
319 Ω
30 pF
Including
jig and
scope
353 Ω
OUTPUT
3.3V
319 Ω
5 pF
Including
jig and
scope
353 Ω
OUTPUT
3.3V
IS61LV256 ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
Rev. I
11/09/99
DATA VALID
READ1.eps
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
DOUT
ADDRESS
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z DATA VALID
CE_RD2.eps
ADDRESS
OE
CE
DOUT
t
HZCE
READ CYCLE NO. 2(1,3)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
IS61LV256 ISSI
®
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. I
11/09/99
AC WAVEFORMS
WRITE CYCLE NO. 1
(CE Controlled, OE is HIGH or LOW)
(1 )
DATA UNDEFINED
t WC
VALID ADDRESS
t SCE
t PWE1
t PWE2
t AW
t HA
HIGH-Z
t HD
t SA
t HZWE
ADDRESS
CE
WE
DOUT
DIN DATAIN VALID
t LZWE
t SD
CE_WR1.eps
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
-8 ns
(3)
-10 ns
(3)
-12 ns -15 ns -20 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tWC Write Cycle Time 8 —10 —12 —15 —20 —ns
tSCE CE to Write End 6.5 —8—8—10 —12 —ns
tAW Address Setup Time 6.5 —8—8—10 —12 —ns
to Write End
tHA Address Hold 0 —0—0—0—0—ns
from Write End
tSA Address Setup Time 0 —0—0—0—0—ns
tPWE1WE Pulse Width (OE HIGH) 6 .5 —7—8—10 —12 —ns
tPWE2WE Pulse Width (OE LOW) 8 —10 —12 —15 —20 —ns
tSD Data Setup to Write End 5 —5—6—7—10 —ns
tHD Data Hold from Write End 0 —0—0—0—0—ns
tHZWE
(4)
WE LOW to High-Z Output —3.5 —4—6—7—7ns
tLZWE
(4)
WE HIGH to Low-Z Output 0 —0—0—0—0—ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3.0V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing
are referenced to the rising or falling edge of the signal that terminates the Write.
3. Shaded area = PREPRODUCTION AVAILABILITY.
4. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100%
tested.
IS61LV256 ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. I
11/09/99
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA t
HZWE
ADDRESS
CE
WE
D
OUT
DIN
OE
DATA
IN
VALID
t
LZWE
t
SD
CE_WR2.eps
WRITE CYCLE NO. 2
(WE Controlled, OE is HIGH During Write Cycle)
(1,2)
WRITE CYCLE NO. 3
(WE Controlled, OE is LOW During Write Cycle)
(1)
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
CE_WR3.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE • VIH.
IS61LV256 ISSI
®
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. I
11/09/99
ISSI
®
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No. Package
8 IS61LV256-8T TSOP - Type I
IS61LV256-8J 300-mil Plastic SOJ
10 IS61LV256-10T TSOP - Type I
IS61LV256-10J 300-mil Plastic SOJ
12 IS61LV256-12T TSOP - Type I
IS61LV256-12J 300-mil Plastic SOJ
15 IS61LV256-15T TSOP - Type I
IS61LV256-15J 300-mil Plastic SOJ
20 IS61LV256-15T TSOP - Type I
IS61LV256-20J 300-mil Plastic SOJ
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No. Package
10 IS61LV256-10TI TSOP - Type I
IS61LV256-10JI 300-mil Plastic SOJ
12 IS61LV256-12TI TSOP - Type I
IS61LV256-12JI 300-mil Plastic SOJ
15 IS61LV256-15TI TSOP - Type I
IS61LV256-15JI 300-mil Plastic SOJ
20 IS61LV256-20TI TSOP - Type I
IS61LV256-20JI 300-mil Plastic SOJ
