eGaN(R) FET DATASHEET EPC2016C EPC2016C - Enhancement Mode Power Transistor VDS , 100 V RDS(on) , 16 m ID , 18 A D EFFICIENT POWER CONVERSION G S Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment leveraging the infrastructure that has been developed over the last 60 years. GaN's exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. Maximum Ratings PARAMETER VALUE UNIT Drain-to-Source Voltage (Continuous) 100 V Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150C) 120 V Continuous (TA = 25C, RJA = 13.4C/W) 18 Pulsed (25C, TPULSE = 300 s) 75 Gate-to-Source Voltage 6 Gate-to-Source Voltage -4 TJ Operating Temperature -40 to 150 TSTG Storage Temperature -40 to 150 VDS ID VGS A V C HAL EPC2016C eGaN(R) FETs are supplied only in passivated die form with solder bars. Die size: 2.1 x 1.6 mm Applications * High Speed DC-DC conversion * Class-D Audio * High Frequency Hard-Switching and Soft-Switching Circuits Benefits * Ultra High Efficiency * Ultra Low RDS(on) * Ultra Low QG * Ultra Small Footprint www.epc-co.com/epc/Products/eGaNFETs/EPC2016C.aspx Thermal Characteristics PARAMETER TYP RJC Thermal Resistance, Junction to Case 2 RJB Thermal Resistance, Junction to Board 4 RJA Thermal Resistance, Junction to Ambient (Note 1) 69 UNIT C/W Note 1: RJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board. See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details. Static Characteristics (TJ = 25C unless otherwise stated) PARAMETER TEST CONDITIONS MIN 100 BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 300 A IDSS Drain-Source Leakage IGSS TYP MAX UNIT V VGS = 0 V, VDS = 80 V 25 150 A Gate-to-Source Forward Leakage VGS = 5 V 0.5 3 mA Gate-to-Source Reverse Leakage VGS = -4 V 0.15 0.25 mA VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 3 mA 1.4 2.5 V RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 11 A 12 16 m VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.8 0.8 V All measurements were done with substrate connected to source. EPC - THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 1 eGaN(R) FET DATASHEET EPC2016C Dynamic Characteristics (TJ = 25C unless otherwise stated) PARAMETER CISS Input Capacitance TEST CONDITIONS MIN VGS = 0 V, VDS = 50 V TYP MAX 360 420 COSS Output Capacitance 210 310 CRSS Reverse Transfer Capacitance 3.2 4.8 RG Gate Resistance 0.4 QG Total Gate Charge 3.4 QGS Gate-to-Source Charge QGD Gate-to-Drain Charge QG(TH) Gate Charge at Threshold QOSS Output Charge QRR Source-Drain Recovery Charge UNIT pF 4.5 1.1 VDS = 50 V, ID = 11 A 0.55 1 nC 0.7 VGS = 0 V, VDS = 50 V 16 24 0 All measurements were done with substrate connected to source. Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS. Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS. Figure 1: Typical Output Characteristics at 25C Figure 2: Transfer Characteristics 75 75 30 VGS = 5 V VGS = 4 V VGS = 3 V VGS = 2 V 15 0 50 RDS(on) - Drain-to-Source Resistance (m) ID - Drain Current (A) 45 0 25C 125C 60 0.5 1.0 1.5 2.0 VDS - Drain-to-Source Voltage (V) 2.5 ID = 8 A ID = 12 A ID = 20 A ID = 40 A 20 10 2.0 2.5 3.0 3.5 4.0 VGS - Gate-to-Source Voltage (V) 30 0.5 4.5 5.0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VGS - Gate-to-Source Voltage (V) 5.0 Figure 4: RDS(on) vs. VGS for Various Temperatures 50 30 0 45 0 3.0 Figure 3: RDS(on) vs. VGS for Various Drain Currents 40 VDS = 3 V 15 RDS(on) - Drain-to-Source Resistance (m) ID - Drain Current (A) 60 25C 125C 40 ID = 11 A 30 20 10 0 EPC - THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VGS - Gate-to-Source Voltage (V) | 2 eGaN(R) FET DATASHEET EPC2016C Figure 5a: Capacitance (Linear Scale) 600 Figure 5b: Capacitance (Log Scale) 400 Capacitance (pF) Capacitance (pF) 1000 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 500 300 200 100 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 10 100 0 0 20 40 60 80 1 100 0 20 40 VDS - Drain-to-Source Voltage (V) Figure 6: Gate Charge 36 5 ID = 11 A VDS = 50 V 4 3.5 3 2.5 2 1.5 1 0.5 0 0 0.5 1.0 1.5 2.0 QG - Gate Charge (nC) 2.5 3.0 12 6 0.5 1.5 2.0 2.5 3.0 3.5 VSD - Source-to-Drain Voltage (V) 4.0 4.5 5.0 Figure 9: Normalized Threshold Voltage vs. Temperature ID = 11 A VGS = 5 V 1.3 Normalized Threshold Voltage Normalized On-State Resistance - RDS(on) 1.0 1.4 1.5 1.4 1.3 1.2 1.1 1 ID = 3 mA 1.2 1.1 1 0.9 0.8 0.7 0.9 0.8 25C 125C 18 Figure 8: Normalized On-State Resistance vs. Temperature 1.6 100 24 3.5 1.8 1.7 80 Figure 7: Reverse Drain-Source Characteristics 30 ISD - Source to Drain Current (A) VGS - Gate to Source Voltage (V) 4.5 60 VDS - Drain-to-Source Voltage (V) 0 25 50 75 100 125 TJ - Junction Temperature ( C ) 150 0.6 0 25 50 75 100 125 150 TJ - Junction Temperature ( C ) All measurements were done with substrate shortened to source. EPC - THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 3 eGaN(R) FET DATASHEET EPC2016C 12 Figure 10: Gate Current 25C 125C IG - Gate Current (mA) 10 8 6 4 2 0 0 1 2 3 4 5 6 VGS - Gate-to-Source Voltage (V) Figure 11: Transient Thermal Response Curves Junction-to-Board ZJB, Normalized Thermal Impedance 1 Duty Factors: 0.5 0.2 0.1 0.1 0.05 T PDM 0.02 0.01 0.01 Notes: Duty Factor = tp/T Peak TJ = PDM x ZJB x RJB + TB Single Pulse 0.001 10-5 tp 10-4 10-3 10-2 tp - Rectangular Pulse Duration [s] 10-1 1 10 Junction-to-Case ZC, Normalized Thermal Impedance 1 Duty Factors: 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 0.001 T PDM Notes: Duty Factor = tp/T Peak TJ = PDM x ZJC x RJC + TC Single Pulse 0.0001 10-5 tp 10-4 10-3 10-2 tp - Rectangular Pulse Duration [s] EPC - THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | 10-1 1 10 | 4 eGaN(R) FET DATASHEET EPC2016C Figure 12: Safe Operating Area I D- Drain Current (A) 100 10 limited by RDS(on) Pulse Width 100 ms 10 ms 1 ms 100 s 1 0.1 0.1 1 10 100 VDS - Drain-Source Voltage (V) TJ = Max Rated, TC = +25C, Single Pulse TAPE AND REEL CONFIGURATION 4 mm pitch, 8 mm wide tape on 7" reel 7" reel d e f Loaded Tape Feed Direction g Die orientation dot b ZZZZ c Gate solder bar is under this corner YYYY a 2016 Die is placed into pocket solder bar side down (face side down) EPC2016C (note 1) Dimension (mm) target min a b c (see note) d e f (see note) g 8.00 1.75 3.50 4.00 4.00 2.00 1.5 7.90 1.65 3.45 3.90 3.90 1.95 1.5 max 8.30 1.85 3.55 4.10 4.10 2.05 1.6 Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard. Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. DIE MARKINGS 2016 Die orientation dot Gate Pad bump is under this corner YYYY ZZZZ Part Number EPC2016C EPC - THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | Laser Markings Part # Marking Line 1 Lot_Date Code Marking line 2 Lot_Date Code Marking Line 3 2016 YYYY ZZZZ | 5 eGaN(R) FET DATASHEET EPC2016C A DIE OUTLINE f f Solder Bar View d X2 X4 3 4 5 6 c B 2 DIM 1 g g X3 100 +/- 20 (685) Side View Seating Plane RECOMMENDED LAND PATTERN 815 Max e A B c d e f g MICROMETERS MIN Nominal MAX 2076 1602 1379 577 235 195 400 2106 1632 1382 580 250 200 400 2136 1662 1385 583 265 205 400 Pad no. 1 is Gate; Pads no. 3, 5 are Drain; Pads no. 4, 6 are Source; Pad no. 2 is Substrate.* *Substrate pin should be connected to Source 2106 The land pattern is solder mask defined. X3 3 4 5 6 802 1632 1 1362 560 X2 (units in m) Pad no. 1 is Gate; Pads no. 3, 5 are Drain; Pads no. 4, 6 are Source; Pad no. 2 is Substrate. * 2 *Substrate pin should be connected to Source X4 180 180 RECOMMENDED STENCIL DRAWING 2106 Recommended stencil should be 4mil (100 m) thick, must be laser cut , opening per drawing. The corner has a radius of R60 4 5 802 3 6 1632 1 1362 560 X2 (measurements in m) Intended for use with SAC305 Type 3 solder, reference 88.5% metals content. 2 Additional assembly resources available at http://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx 180 180 Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. eGaN(R) is a registered trademark of Efficient Power Conversion Corporation. EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx EPC - THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | Information subject to change without notice. Revised May, 2019 | 6