W83194BR-740 STEPLESS CLOCK FOR SIS735/740 CHIPSET Table of Content1. GENERAL DESCRIPTION ......................................................................................................... 2 2. PRODUCT FEATURES .............................................................................................................. 2 3. PIN CONFIGURATION ............................................................................................................... 3 4. PIN DESCRIPTION..................................................................................................................... 4 4.1 Crystal I/O ....................................................................................................................... 4 4.2 CPU, SDRAM, AGP, PCI Clock Outputs....................................................................... 4 4.3 I2C Control Interface....................................................................................................... 5 4.4 4.4 Fixed Frequency Outputs ......................................................................................... 5 4.5 Power Management Pins................................................................................................ 5 4.6 Power Pins...................................................................................................................... 6 5. FREQUENCY SELECTION BY HARDWARE TABLE................................................................ 6 6. FUNCTION DESCRIPTION........................................................................................................ 7 6.1 2-WIRE I2C CONTROL INTERFACE ............................................................................ 7 6.2 SERIAL CONTROL REGISTERS .................................................................................. 7 6.2.1 Register 4: CPU Frequency Select Register (default = 0) ................................................8 6.2.2 Register 5 : CPU Clock Register (1 = Active, 0 = Inactive) ............................................11 6.2.3 Register 6: PCI Clock Register (1 = Active, 0 = Inactive) .............................................11 6.2.4 Register 7: Control Register (1 = Active, 0 = Inactive)...................................................11 6.2.5 Register 8: Control Register (1 = Active, 0 = Inactive)....................................................12 6.2.6 Register 9: Control Register(1 = Active, 0 = Inactive).....................................................12 6.2.7 Register 10: Watchdog Timer Register...........................................................................12 6.2.8 Register 11: M/N Program Register and Divisor.............................................................13 6.2.9 Register 12: M/N Program Register................................................................................13 6.2.10 Register 13: Spread spectrum control Register ............................................................13 6.2.11 Register 14: Divisor Register ........................................................................................13 6.2.12 Register 15: Winbond Chip ID Register (Read Only)...................................................14 6.2.13 Register 16: Winbond Chip ID Register (Read Only)...................................................14 7. ORDERING INFORMATION .................................................................................................... 15 8. HOW TO READ THE TOP MARKING...................................................................................... 15 9. PACKAGE DRAWING AND DIMENSIONS.............................................................................. 16 10. REVISION HISTORY ................................................................................................................ 17 -1- Publication Release Date:May 19, 2005 Revision 2.0 W83194BR-740 1. GENERAL DESCRIPTION The W83194BR-740 is a Clock Synthesizer for SiS 735/740 chipset. W83194BR-740 provides all clocks required for high-speed RISC or CISC microprocessor such as AMD K7, and also provides 16 different frequencies of CPU clocks frequency setting. All clocks are externally selectable with smooth transitions. The W83194BR-740 makes SDRAM in synchronous or asynchronous frequency with CPU clocks. The W83194BR-740 provides step-less frequency programming by controlling the VCO freq. and the programmable AGP, PCI clock output divisor ratio. A watch dog timer is quipped and when time out, the RESET# pin will output 4ms pulse signal. Spread spectrum built in at 0.5% or 0.25% to reduce EMI. Programmable stopping individual clock outputs and frequency selection through I2C interface The W83194BR-740 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns slew rate. 2. PRODUCT FEATURES y Supports AMD CPU with I2C. y 3 CPU clocks (one free-running CPU clock) y 2 AGP clocks y 1 SDRAM output clock for chipset y 1 IOAPIC clock y 6 PCI synchronous clocks. y Optional single or mixed supply: (Others Vdd = 3.3V, VddLCPU=2.5V) y Skew---CPU to CPU < 175ps, CPU to SDRAM < 250ps, PCI to PCI < 500ps, AGP to AGP < 175ps y Smooth frequency switch with selections from 66 to 200mhz y I2C 2-Wire serial interface and I2C read back y 0.5%, 0.25%center type, 0~0.5% down type spread spectrum to reduce EMI y Programmable registers to enable/stop each output and select modes (mode as Tri-state or Normal ) y 48 MHz for USB y 24 MHz for super I/O y Packaged in 48-pin SSOP -2- W83194BR-740 3. PIN CONFIGURATION VddR REF0^/&FS0 REF1^/&FS1 Vss Vssosc Xin Xout Vss PCICLK_F^/&FS2 PCICLK1^/&FS3 VddP PCICLK2^ PCICLK3^ Vss PCICLK4^ PCICLK5^ VddAGP AGPCLK0 AGPCLK1 VssAGP Vdd48 48MHz^ 24_48MHz#/&AGPSEL Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VddAPIC IOAPIC Vss VddC $CPUCLK0T $CPUCLK0C Vss VddC $CPUCLK1T Vss Reserved RESET# VddSD SDRAM_out VssD PCI_STOP# CPU_STOP# PD# SDRAM_STOP# AGP_STOP# SDATA* SDCLK* Vss Vdd *:pull-up 120K &:pull-down 120K ^:double strength #:input active low $:open drain ALL PCICLK outputs have X1.5~X2 drive strength -3- Publication Release Date:May 19, 2005 Revision2.0 W83194BR-740 4. PIN DESCRIPTION IN - Input OUT - Output I/O - Bi-directional OD - Open drain # - Active Low * - Internal 120k pull-up 4.1 Crystal I/O SYMBOL PIN I/O Xin 6 IN Xout 7 OUT 4.2 FUNCTION Crystal input with internal loading capacitors and feedback resistors. Crystal output at 14.318MHz nominally. CPU, SDRAM, AGP, PCI Clock Outputs SYMBOL PIN I/O 47 OUT $CPUCLK0T $CPUCLK0C 44,43 OD $CPUCLK1T 40 OD 35 OUT PCICLK_F^/ &FS2 9 I/O PCICLK1^/ &FS3 10 I/O 12,13,15,16 OUT 37 OD 18,19 OUT IOAPIC SDRAM_out PCICLK^ [ 2:5 ] RESET# AGPCLK0 AGPCLK1 FUNCTION 16.7/33MHz APIC clock for CPU and Chipset, selected by I2C. True CPU clock output and Complementary CPU clock output, open drain output type. This pin will be stopped by CPU_STOP# Low skew (< 250ps) clock outputs for host CPU clock output for chipset, open drain output type. This pin will not be stopped by CPU_STOP# SDRAM clock output which have syn. or asyn. Frequencies as CPU clocks. The clock phase is the same as CPUCLK0T and CPUCLK1T. Latched input for FS2 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. Interanl 120K pull-down. PCICLK_F outputs have 1.5X drive strength. Latched input for FS3 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. Internal 120K pull-down PCICLK1 outputs have 1.5X drive strength. Low skew (< 250ps) PCI clock outputs. y ALL PCICLK outputs have 1.5X drive strength. Open Drain output type, 4ms low active pulse, when Watch Dog time out the all clock output recover to hardware FS0~FS3 setting. Low skew (< 250ps) AGP clock outputs. -4- W83194BR-740 4.3 I2C Control Interface SYMBOL PIN I/O FUNCTION 2 *SDATA 28 I/O Serial data of I C 2-wire control interface *SDCLK 27 IN Serial clock of I2C 2-wire control interface 4.4 Fixed Frequency Outputs SYMBOL PIN I/O REF0^/&FS0 2 I/O REF1^/&FS1 3 I/O 24_48MHz#/&AGPSEL 23 I/O 48MHz ^ 22 O 4.5 FUNCTION 3.3V, 14.318MHz reference clock output. Internal 120k pull-down. Latched input for FS0 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. This pin has 1.5X drive strength. 3.3V , 14.318MHz reference clock output. Internal 120k pull-down. This pin has 1.5X drive strength. Latched input for FS1 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. Latched input for &AGPSEL at initial power up for H/W selecting the output frequency of AGP clocks. Internal 120K pull-down. 24MHz or 48MHz selected by I2C programming control bit (Byte7, bit4),and default be 24MHz 48MHz output for USB. This pin has 1.5X drive strength. Power Management Pins SYMBOL AGP_STOP# SDRAM_STOP# PD# CPU_STOP# PCI_STOP# PIN 29 30 31 32 33 FUNCTION AGP clock stop control pin. SDRAM clock stop control pin. Power Down pin, if PD#=0, all clocks are stopped. CPU clock stop control pin. PCI clock stop control pin. -5- Publication Release Date:May 19, 2005 Revision2.0 W83194BR-740 4.6 Power Pins SYMBOL PIN VddR VddAPIC Vdd FUNCTION 1 48 25 VddC Power supply for REF. 3.3V Power supply for IOAPIC,2.5V. Power supply for core logic. 3.3V Power supply for CPUCLK1T, CPUCLK0T, and CPUCLK0C, 2.5V. Power supply for AGP outputs. Power supply for PCI outputs. Power supply for SDRAM and 48/24MHz outputs. Power supply for 48/24MHz outputs. 41,45 VddAGP VddP VddSD Vdd48 17 11 36 21 4,5,8,14,20,26,46,39,4 Circuit Ground. 2 Vss 5. FREQUENCY SELECTION BY HARDWARE TABLE VCO VCO/ VCO/AGP CPU SDRAM FS[3:0] (MHZ) CPU:SDRAM:PCI AGPSEL=0 AGPSEL=1 (MHZ) (MHZ) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 399.6 400 498 399 399.6 400 400 399 336 372 414 300 399.6 498 300 480 6 4 3 3 6 4 4 3 3 3 3 2 6 4 2 3 6 4 3 3 4 6 3 4 3 3 3 2 3 3 3 4 2 3 5 4 2 3 3 4 3 4 4 5 2 4 5 5 6 6 8 6 6 6 6 6 5 6 6 5 6 8 5 8 8 8 10 8 8 8 8 8 6 8 8 6 8 10 6 10 -6- 66.6 100 166 133 66.6 100 100 133 112 124 138 150 66.6 124.5 150 160 66.6 100 166 133 100 66.6 133 100 112 124 138 150 133 166 100 120 PCI AGP (MHZ) AGPSEL=0 AGPSEL=1 33.3 33.3 33.2 33.3 33.3 33.3 33.3 33.3 37.3 31 34.5 30 33.3 31.13 30 32 66.6 66.6 62.5 66.6 66.6 66.6 66.6 66.6 67.2 62 69 60 66.6 62.5 60 60 50 50 50 50 50 50 50 50 56 46.5 51.8 50 50 50 50 48 W83194BR-740 6. FUNCTION DESCRIPTION 6.1 2-WIRE I2C CONTROL INTERFACE The clock generator is a slave I2C component which can be read back the data stored in the latches for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire control interface allows each clock output individually enabled or disabled. On power up, the W83194BR-740 initializes with default register settings, and then itptional to use the 2-wire control interface. The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high during normal data transfer. There are only two exceptions. One is a high-to-low transition on SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a low-tohigh transition on SDATA while SDCLK is high used to indicate the end of a data transfer cycle. Data is always sent as complete 8-bit bytes followed by an acknowledge generated. Byte writing starts with a start condition followed by 7-bit slave address [1101 0010], command code checking [0000 0000], and byte count checking. After successful reception of each byte, an acknowledge (low) on the SDATA wire will be generated by the clock chip. Controller can start to write to internal I2C registers after the string of data. The sequence order is as follows: Bytes sequence order for I2C controller : Clock Address A(6:0) & R/W Ack 8 bits dummy Command code Ack 8 bits dummy Byte count Ack Byte0,1,2... until Stop Set R/W to 1 when read back the data sequence is as follows, [1101 0011] : Clock Address A(6:0) & R/W 6.2 Ack Byte 0 Ack Byte 1 Ack Byte2, 3, 4... until Stop SERIAL CONTROL REGISTERS The Pin column lists the affected pin number and the @PowerUp column gives the state at true power up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and acknowledged. -7- Publication Release Date:May 19, 2005 Revision2.0 W83194BR-740 6.2.1 Register 4: CPU Frequency Select Register (default = 0) BIT @POWERUP PIN 7 6 5 4 0 0 0 0 - 3 0 - 2 1 0 0 - 0 0 - DESCRIPTION SEL3 (for frequency table selection by software via I2C) SEL2 (for frequency table selection by software via I2C) SEL1 (for frequency table selection by software via I2C) SEL0 (for frequency table selection by software via I2C) 0 = Selection by hardware 1 = Selection by software I2C - Bit 1,2, 7:4 SEL4 (for frequency table selection by software via I2C) SEL5 (for frequency table selection by software via I2C) 0 = Running 1 = Tristate all outputs -8- W83194BR-740 Frequency table by I2C VCO VCO/ SEL[5:0] (MHz) CPU:SDRAM:PCI VCO/AGP CPU SDRAM PCI AGPSEL=0 AGPSEL=1 (MHz) (MHz) (MHz) AGP AGPSEL=0 AGPSEL= 1 000000 000001 000010 000011 000100 000101 000110 000111 399.6 400 498 399 399.6 400 400 399 6 4 3 3 6 4 4 3 6 4 3 3 4 6 3 4 2 3 5 4 2 3 3 4 6 6 8 6 6 6 6 6 8 8 10 8 8 8 8 8 66.6 100 166 133 66.6 100 100 133 66.6 100 166 133 100 66.6 133 100 33.3 33.3 33.2 33.3 33.3 33.3 33.3 33.3 66.6 66.6 62.5 66.6 66.6 66.6 66.6 66.6 50 50 50 50 50 50 50 50 001000 336 3 3 3 5 6 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 011100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 372 414 300 399.6 498 300 480 420 432 333.2 388 408 416 420 428 412 420 424 428 412 420 424 432 3 3 2 6 4 2 3 6 6 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 2 3 3 3 4 4 4 3 3 3 3 3 3 6 6 4 4 4 4 4 4 4 4 5 2 4 5 5 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 6 6 5 6 8 5 8 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 8 8 6 8 10 6 10 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 112 124 138 150 66.6 124.5 150 160 70 72 83.3 97 102 104 105 107 103 105 106 107 103 105 106 108 112 124 138 150 133 166 100 120 105 108 111.07 129.33 136 138.67 140 142.67 68.67 70 106 107 103 105 106 108 37.3 31 34.5 30 33.3 31.13 30 32 35 36 27.77 32.33 34 34.67 35 35.67 34.33 35 35.33 35.67 34.33 35 35.33 36 67.2 62 69 60 66.6 62.5 60 60 70 72 55.53 64.67 68 69.33 70 71.33 68.67 70 70.67 71.33 68.67 70 70.67 72 56 46.5 51.8 50 50 50 50 48 52.5 54 41.65 48.5 51 52 52.5 53.5 51.5 52.5 53 53.5 51.5 52.5 53 54 -9- Publication Release Date:May 19, 2005 Revision2.0 W83194BR-740 Frequency table by I2C,Continued. VCO VCO/ SEL[5:0] (MHz) CPU:SDRAM:PCI 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 111100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 390 405 408 417 420 426 429 435 390 405 414 426 411 417 423 426 390 396 408 411 414 426 432 438 450 459 468 489 498 525 534 549 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 VCO/AGP CPU SDRAM PCI AGPSEL=0 AGPSEL=1 (MHz) (MHz) (MHz) 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 -10- 130 135 136 139 140 142 143 145 130 135 138 142 137 139 141 142 130 132 136 137 138 142 144 146 150 153 156 163 166 175 178 183 130 135 136 139 140 142 143 145 130 135 138 142 137 139 141 142 97.5 99 102 102.75 103.5 106.5 108 109.5 112.5 114.75 117 122.25 124.5 131.25 133.5 137.25 32.5 33.75 34 34.75 35 35.5 35.75 36.25 26 27 27.6 28.4 27.4 27.8 28.2 28.4 32.5 33 34 34.25 34.5 35.5 36 36.5 30 30.6 31.2 32.6 33.2 35 35.6 36.6 AGP AGPSEL=0 AGPSEL= 1 65 67.5 68 69.5 70 71 71.5 72.5 65 67.5 69 71 68.5 69.5 70.5 71 65 49.5 51 51.38 51.75 53.25 54 54.75 56.25 57.38 58.5 61.13 62.25 65.63 66.75 68.63 48.75 50.63 51 52.13 52.5 53.25 53.63 54.38 48.75 50.63 51.75 53.25 51.38 52.13 52.88 53.25 48.75 39.6 40.8 41.1 41.4 42.6 43.2 43.8 45 45.9 46.8 48.9 49.8 52.5 53.4 54.9 W83194BR-740 6.2.2 Register 5 : CPU Clock Register (1 = Active, 0 = Inactive) BIT @POWERUP PIN 7 1 - 6 1 - 5 0 - 4 0 - 3 2 1 0 1 1 1 1 43 44 40 - 6.2.3 DESCRIPTION Reserved 0 = 0.5% down type spread 1= Center type spread. 0 = Normal 1 = Spread Spectrum enabled 0 = 0.25% Center type Spread Spectrum Modulation 1 = 0.5% Center type Spread Spectrum Modulation $CPUCLK0C (Active / Inactive) $CPUCLK0T (Active / Inactive) $CPUCLK1T (Active / Inactive) Reserved Register 6: PCI Clock Register (1 = Active, 0 = Inactive) BIT @POWERUP PIN 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 19 18 16 15 13 12 10 9 6.2.4 DESCRIPTION AGPCLK1 (Active / Inactive) AGPCLK0 (Active / Inactive) PCICLK5 (Active / Inactive) PCICLK4 (Active / Inactive) PCICLK3 (Active / Inactive) PCICLK2 (Active / Inactive) PCICLK1 (Active / Inactive) PCICLK_F (Active / Inactive) Register 7: Control Register (1 = Active, 0 = Inactive) BIT @POWERUP PIN 7 6 5 1 1 1 23 22 47 4 1 - 3 1 - 2 1 0 1 1 1 3 2 DESCRIPTION 24_48MHz (Active / Inactive) 48MHz (Active / Inactive) IOAPIC(Active / Inactive) 1 = 24_48MHz(pin23) is 24MHz 0 = 24_48MHz(pin23) is 48Mhz 1 = IOAPIC(pin47) is the frequency of PCI/2 0 = IOAPIC(pin47) is the frequency of PCI Reserved REF1 (Active / Inactive) REF0 (Active / Inactive) - 11 - Publication Release Date:May 19, 2005 Revision2.0 W83194BR-740 6.2.5 Register 8: Control Register (1 = Active, 0 = Inactive) BIT @POWERUP PIN 7 6 5 4 3 2 1 0 X X X X X 1 0 0 23 10 9 3 2 - 6.2.6 @POWERUP PIN 7 1 - 6 1 - 5 4 3 2 1 0 1 X X X X X - BIT Latched AGPSEL# Latched FS3# Latched FS2# Latched FS1# Latched FS0# ACskew2 (AGP to CPU skew program bit) ACskew1 (AGP to CPU skew program bit) ACskew0 (AGP to CPU skew program bit) Register 9: Control Register(1 = Active, 0 = Inactive) BIT 6.2.7 DESCRIPTION DESCRIPTION Reserved 1 = $CPUCLK1T can be stopped by CPU_STOP# y 0 = $CPUCLK1T free running Reserved Latched AGP_STOP# Latched CPU_STOP# Latched PCI_STOP# Latched SDR_STOP# Latched PD# Register 10: Watchdog Timer Register @POWERUP PIN 7 0 - 6 5 4 3 2 1 0 X 0 0 0 0 0 0 - DESCRIPTION Enable Count 1 = start timer 0 = stop timer Second timeout status (READ ONLY) Second count 5 Second count 4 Second count 3 Second count 2 Second count 1 Second count 0 -12- W83194BR-740 6.2.8 Register 11: M/N Program Register and Divisor BIT @POWERUP PIN 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 - 6.2.9 DESCRIPTION N value bit 8 Test 1 (Internal test use) Test 0 (Internal test use) M value bit 4 M value bit 3 M value bit 2 M value bit 1 M value bit 0 Register 12: M/N Program Register BIT @POWERUP PIN 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 - DESCRIPTION N value bit 7 N value bit 6 N value bit 5 N value bit 4 N value bit 3 N value bit 2 N value bit 1 N value bit 0 6.2.10 Register 13: Spread spectrum control Register BIT @POWERUP PIN 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 - DESCRIPTION Spread spectrum up count 3 Spread spectrum up count 2 Spread spectrum up count 1 Spread spectrum up count 0 Spread spectrum down count 3 Spread spectrum down count 2 Spread spectrum down count 1 Spread spectrum down count 0 6.2.11 Register 14: Divisor Register BIT @POWERUP PIN 7 0 - 6 5 4 3 2 1 0 0 0 0 0 0 0 0 - DESCRIPTION 0: use frequency table 1: use M/N register to program frequency The equation is VCO freq. = 14.318MHz * (N+4)/ M Ratio SSEL3 (See CPU:SDRAM:PCI ratio selection table) Ratio SSEL2 (See CPU:SDRAM:PCI ratio selection table) Ratio SSEL1 (See CPU:SDRAM:PCI ratio selection table) Ratio SSEL0 (See CPU:SDRAM:PCI ratio selection table) AGP Ratio ASEL2 (See AGP ratio selection table) AGP Ratio ASEL1 (See AGP ratio selection table) AGP Ratio ASEL0 (See AGP ratio selection table) - 13 - Publication Release Date:May 19, 2005 Revision2.0 W83194BR-740 6.2.12 Register 15: Winbond Chip ID Register (Read Only) BIT @POWERUP PIN 7 6 5 4 3 2 1 0 0 1 1 0 0 0 1 0 - DESCRIPTION Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID 6.2.13 Register 16: Winbond Chip ID Register (Read Only) BIT @POWERUP PIN 7 6 5 4 3 2 1 0 1 0 1 0 0 0 1 0 - DESCRIPTION Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Version ID Version ID Version ID Version ID 1.CPU:SDRAM:PCI ratio selection table SSEL[3:0] 2.AGP ratio selection table VCO/ VCO/ CPU/ ASEL[2:0] VCO/AGP CPU SDRAM PCI 000 3 001 5 010 6 011 8 100 4 101 - 0000 2 2 5 0001 2 3 5 0010 3 3 3 0011 3 3 4 0100 3 3 5 0101 3 4 4 0110 3 4 5 0111 4 3 3 1000 4 3 4 1001 4 4 3 1010 4 6 3 1011 6 3 2 1100 6 4 2 1101 6 6 2 1110 6 6 3 1111 6 6 4 -14- 110 - 111 10 W83194BR-740 7. ORDERING INFORMATION PART NUMBER PACKAGE TYPE PRODUCTION FLOW W83194BR-740 48 PIN SSOP Commercial, 0C to +70C 8. HOW TO READ THE TOP MARKING W83194BR-740 28051234 942GED 1st line: Winbond logo and the type number: W83194BR-740 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 942 G E D 942: packages made in '99, week 42 G: assembly house ID; O means OSE, G means GR E: Internal use code D: IC revision All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 15 - Publication Release Date:May 19, 2005 Revision2.0 W83194BR-740 9. PACKAGE DRAWING AND DIMENSIONS -16- W83194BR-740 10. REVISION HISTORY VERSION DATE PAGE DESCRIPTION n.a All of the versions before 0.50 are for internal use. 1.0 02/Apr n.a Change version and version on web site to 1.0 2.0 May 19, 2005 17 ADD Important Notice Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd. No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd. 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 17 - Publication Release Date:May 19, 2005 Revision2.0