M4A5-192/96-12VNC - Lattice Semiconductor Corporation

Publication#

17466

Rev:

Amendment/

Issue Date:

May 1999

MACH 4 CPLD Family

High Performance EE CMOS

Programmable Logic

FEATURES

◆

High-performance, EE CMOS 3.3-V & 5-V CPLD families

◆

Flexible architecture for rapid logic designs

— Excellent First-Time-Fit

and reﬁt feature

— SpeedLocking

performance for guaranteed ﬁxed timing

— Central, input and output switch matrices for 100% routability and 100% pin-out retention

◆

High speed

— 5.0ns t

Commercial and 7.5ns t

Industrial

— 182MHz f

CNT

◆

32 to 512 macrocells; 32 to 768 registers

◆

44 to 352 pins in PLCC, PQFP, TQFP, BGA, or fpBGA packages

◆

Advanced capabilities for easy system integration

— 3.3-V & 5-V JEDEC-compliant operations

— JTAG (IEEE 1149.1) compliant for boundary scan testing

— 3.3-V & 5-V JTAG in-system programming

— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)

— Safe for mixed supply voltage system designs

— Programmable pull-up or Bus-Friendly

inputs and I/Os

— Hot-socketing

— Programmable security bit

— Individual output slew rate control

◆

Flexible architecture for a wide range of design styles

— D/T registers and latches

— Synchronous or asynchronous mode

— Dedicated input registers

— Programmable polarity

— Reset/ preset swapping

◆

Advanced EE CMOS process provides high-performance, cost-effective solutions

◆

Supported by Vantis DesignDirect

software for rapid logic development

— Supports HDL design methodologies with results optimized for Vantis

— Flexibility to adapt to user requirements

— Software partnerships that ensure customer success

◆

Lattice/Vantis and third-party hardware programming support

— Lattice/VantisPRO

(formerly known as MACHPRO

) software for in-system programmability

support on PCs and automated test equipment

— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,

and System General

Includes

MACH 4A Family

Advance Information

2 MACH 4 Family

Notes:

1. For information on the M4-96/96 device, please refer to the M4-96/96 datasheet at www.vantis.com.

2. “M4-xxx” is for 5-V devices. “M4LV-xxx” is for 3.3-V devices.

Table 1. MACH 4 Device Features

1,2

Feature M4-32/32

M4LV-32/32 M4-64/32

M4LV-64/32 M4-96/48

M4LV-96/48 M4-128/64

M4LV-128/64 M4-128N/64

M4LV-128N/64 M4-192/96

M4LV-192/96 M4-256/128

M4LV-256/128

Macrocells

32 64 96 128 128 192 256

Maximum User I/O Pins

32 32 48 64 64 96 128

(ns)

7.5 7.5 7.5 7.5 7.5 7.5 7.5

CNT

(MHz)

111 111 111 111 111 111 111

COS

(ns)

5.5 5.5 5.5 5.5 5.5 5.5 5.5

(ns)

5.5 5.5 5.5 5.5 5.5 5.5 5.5

Static Power (mA)

25 25 50 70 70 85 100

JTAG Compliant

Yes Yes Yes Yes No Yes Yes

PCI Compliant

Yes Yes Yes Yes Yes Yes Yes

MACH 4 Family 3

Notes:

1. All information on MACH 4A devices is Advance Information. Please contact a Lattice/Vantis sales representative for details on

availability.

Table 2. MACH 4A Device Features

3.3 V Devices

Feature M4A3-32 M4A3-64 M4A3-96 M4A3-128 M4A3-192 M4A3-256 M4A3-384 M4A3-512

Macrocells

32 64 96 128 192 256 384 512

User I/O options

32 32/64 48 64/96/128 68/96/128 128/192 132/160/192 132/160/192/

256

(ns)

5.0 5.0 5.0 5.0 5.0 5.0 6.5 6.5

CNT

(MHz)

182 182 182 182 182 182 154 154

COS

(ns)

4.0 4.0 4.0 4.0 4.0 4.0 4.5 4.5

(ns)

3.0 3.0 3.0 3.0 3.0 3.0 4.0 4.0

Static Power (mA)

TBD TBD TBD TBD TBD TBD TBD TBD

JTAG Compliant

Yes Yes Yes Yes Yes Yes Yes Yes

PCI Compliant

Yes Yes Yes Yes Yes Yes Yes Yes

5 V Devices

Feature M4A5-32 M4A5-64 M4A5-96 M4A5-128 M4A5-192 M4A5-256

Macrocells

32 64 96 128 192 256

User I/O options

32 32 48 64 96 128

(ns)

5.0 5.0 5.0 5.0 5.0 6.5

CNT

(MHz)

182 182 182 182 182 154

COS

(ns)

4.0 4.0 4.0 4.0 4.0 4.5

(ns)

3.0 3.0 3.0 3.0 3.0 4.0

Static Power (mA)

TBD TBD TBD TBD TBD TBD

JTAG Compliant

Yes Yes Yes Yes Yes Yes

PCI Compliant

Yes Yes Yes Yes Yes Yes

4 MACH 4 Family

GENERAL DESCRIPTION

The MACH

4 family from Lattice/V antis offers an exceptionally ﬂexible architecture and delivers

a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products

and software tools. The overall beneﬁts for users are a guaranteed and predictable CPLD

solution, faster time-to-market, greater ﬂexibility and lower cost. The MACH 4 devices offer

densities ranging from 32 to 512 macrocells with 100% utilization and 100% pin-out retention.

Both the MACH 4 and the MACH 4A families offer 5-V (M4-xxx and M4A5-xxx) and 3.3-V (M4L V-

xxx and M4A3-xxx) operation.

MACH 4 products are 5-V or 3.3-V in-system programmable through the JT AG (IEEE Std. 1149.1)

interface. JTAG boundary scan testing capability also allows product testability on automated test

equipment for device connectivity.

All MACH 4 family members deliver First-Time Fit and easy system integration with pin-out

retention after any design change and reﬁt. With multi-tiered central switch matrices, enhanced

logic arrays, intelligent logic allocators with an XOR gate and multi-clocking, the MACH 4 family

has D or T-type registers and latches as well as synchronous/asynchronous logic and ﬂexible

set/reset capabilities. For both 3.3-V and 5-V operations, MACH 4 products can deliver

guaranteed ﬁxed timing as fast as 5.0 ns t

and 182 MHz f

CNT

through the SpeedLocking feature

when using up to 20 product terms per output (Tables 3 and 4).

Note:

1. C = Commercial, I = Industrial

Table 3. MACH 4 Speed Grades

Device

Speed Grade

-7 -10 -12 -14 -15 -18

M4-32/32

M4LV-32/32

C C, I C, I I C I

M4-64/32

M4LV-64/32

C C, I C, I I C I

M4-96/48

M4LV-96/48

C C, I C, I I C I

M4-128/64

M4LV-128/64

C C, I C, I I C I

M4-128N/64

M4LV-128N/64

C C, I C, I I C I

M4-192/96

M4LV-192/96

C C, I C, I I C I

M4-256/128

M4LV-256/128

C C, I C, I I C I

MACH 4 Family 5

Notes:

1. C = Commercial, I = Industrial

2. All information on MACH 4A devices is Advance Information. Please contact a Lattice/Vantis sales representative for details on

availability.

The MACH 4 family offers 20 density-I/O combinations in Thin Quad Flat Pack (TQFP), Plastic

Quad Flat Pack (PQFP), Plastic Leaded Chip Carrier (PLCC), Ball Grid Array (BGA), and ﬁne-

pitch BGA (fpBGA) packages ranging from 44 to 352 pins (Tables 5 and 6). It also offers I/O

safety features for mixed-voltage designs so that the 3.3-V devices can accept 5-V inputs, and 5-

V devices do not overdrive 3.3-V inputs. Additional features include Bus-Friendly inputs and I/

Os, a programmable power-down mode for extra power savings and individual output slew rate

control for the highest speed transition or for the lowest noise transition.

Table 4. MACH 4A Speed Grades

Device

Speed Grade

1, 2

-5 -55 -6 -65 -7 -10 -12 -14

M4A3-32

M4A5-32

CCCCC, IC, IC, II

M4A3-64

M4A5-64

CCCCC, IC, IC, II

M4A3-96

M4A5-96

CCCCC, IC, IC, II

M4A3-128

M4A5-128

CCCCC, IC, IC, II

M4A3-192

M4A5-192

CCCCC, I C, I C, II

M4A3-256

CCCCC, IC, IC, II

M4A5-256

C C C, I C, I I

M4A3-384

C C C, I C, I I

M4A3-512

C C C, I C, I I

Table 5. MACH 4 Package and I/O Options (Number of I/Os and dedicated inputs in Table)

Package M4-32/32

M4LV-32/32 M4-64/32

M4LV-64/32 M4-96/48

M4LV-96/48 M4-128/64

M4LV-128/64 M4-128N/64

M4LV-128N/64 M4-192/96

M4LV-192/96 M4-256/128

M4LV-256/128

44-pin PLCC

32+2 32+2

44-pin TQFP

32+2 32+2

48-pin TQFP

32+2 32+2

84-pin PLCC

64+6

100-pin TQFP

48+8 64+6

100-pin PQFP

64+6

144-pin TQFP

96+16

208-pin PQFP

128+14

256-ball BGA

128+14

6 MACH 4 Family

Note:

1. All information on MACH 4A devices is Advance Information. Please contact a Lattice/Vantis sales representative for details on

availability.

Table 6. MACH 4A Package and I/O Options

(Number of I/Os and dedicated inputs in Table)

3.3 V Devices

Package M4A3-32 M4A3-64 M4A3-96 M4A3-128 M4A3-192 M4A3-256 M4A3-384 M4A3-512

44-pin PLCC

32+2 32+2

44-pin TQFP

32+2 32+2

48-pin TQFP

32+2 32+2

100-pin TQFP

64+6 48+8 64+6 68+2

100-pin PQFP

64+6

100-ball

fpBGA

64+6 64+6 68+2

144-pin TQFP

96+16 96+16

144-ball

fpBGA

96+16 96+16

176-pin TQFP

128+4 128+4 128+4 132 132

200-ball

fpBGA

128+4 128+4 128+4

208-pin PQFP

128+14, 160 160 160

320-ball

fpBGA

192

256-ball BGA

128+14 192 192

352-ball BGA

256

5 V Devices

Package M4A5-32 M4A5-64 M4A5-96 M4A5-128 M4A5-192 M4A5-256

44-pin PLCC

32+2 32+2

44-pin TQFP

32+2 32+2

48-pin TQFP

32+2 32+2

100-pin TQFP

48+8 64+6

100-pin PQFP

64+6

144-pin TQFP

96+16

208-pin PQFP

128+14

256-ball BGA

128+14

MACH 4 Family 7

Lattice/Vantis of fers software design support for MACH devices in both the MACHXL

and

DesignDirect development systems. The DesignDirect development system is Vantis’

implementation software that includes support for all V antis CPLD, FPGA and SPLD devices. This

system is supported under Windows ’95, ’98 and NT as well as Sun Solaris and HPUX.

DesignDirect software is designed for use with design entry, simulation and veriﬁcation software

from leading-edge tool vendors such as Cadence, Exemplar Logic, Mentor Graphics, Model

Technology , Synopsys, Synplicity, Viewlogic and others. It accepts EDIF 2 0 0 input netlists,

generates JEDEC ﬁles for Vantis PLDs and creates industry-standard EDIF, Verilog, VITAL-

compliant VHDL and SDF simulation netlist for design veriﬁcation.

DesignDirect software is also available in product conﬁgurations that include VHDL and Verilog

synthesis from Exemplar Logic and VHDL, Verilog R TL and gate level timing simulation from

Model T echnology. Schematic capture and ABEL entry, as well as functional simulation, are also

provided.

8 MACH 4 Family

FUNCTIONAL DESCRIPTION

The fundamental architecture of MACH 4 devices (Figure 1) consists of multiple optimized PAL

blocks interconnected by a central switch matrix. The central switch matrix allows

communication between PAL blocks and routes inputs to the PAL blocks. Together, the PAL

blocks and central switch matrix allow the logic designer to create large designs in a single

device instead of having to use multiple devices.

The key to being able to make effective use of these devices lies in the interconnect schemes.

In MACH 4 architecture, the macrocells have been decoupled from the product terms through

the logic allocator , and the I/O pins have been decoupled from the macrocells due to the output

switch matrix. In addition, more input routing options are provided by the input switch matrix.

These resources provide the ﬂexibility needed to ﬁt designs efﬁciently.

Notes:

1. 16 for MACH 4 and MACH 4A devices with 1:1 macrocell-I/O cell ratio (see next page).

2. Block clocks do not go to I/O cells in M4(LV)-32/32 or M4A(3,5)-32/32.

3. M4(LV)-192/96, M4(LV)-256/128, M4A(3,5)-192, M4A(3,5)-256, M4A3-384, and M4A3-512 have dedicated clock pins which

cannot be used as inputs and do not connect to the central switch matrix.

I/O

Pins

Clock/Input

Pins

Central Switch Matrix

I/O

Pins

I/O

Pins

Dedicated

Input Pins

PAL Block

Logic

Allocator

with XOR

Output/

Buried

Macrocells

33/

34/

36 1616

Clock

Generator

Logic

Array

Output Switch Matrix

Input

Switch

Matrix

I/O Cells

Note 1

Note 2

Note 3

PAL Block

17466G-001

Figure 1. MACH 4 Block Diagram and PAL Block Structure

MACH 4 Family 9

Table 7. Architectural Summary of MACH 4 devices

Table 8. Architectural Summary of MACH 4A devices

The Macrocell-I/O cell ratio is deﬁned as the number of macrocells versus the number of I/O

cells internally in a PAL block (Tables 7 and 8).

The central switch matrix takes all dedicated inputs and signals from the input switch matrices

and routes them as needed to the P AL blocks. Feedback signals that return to the same P AL block

still must go through the central switch matrix. This mechanism ensures that P AL blocks in MACH

4 devices communicate with each other with consistent, predictable delays.

The central switch matrix makes a MACH 4 device more advanced than simply several PAL

devices on a single chip. It allows the designer to think of the device not as a collection of

blocks, but as a single programmable device; the software partitions the design into PAL blocks

through the central switch matrix so that the designer does not have to be concerned with the

internal architecture of the device.

MACH 4A Devices

M4-64/32, M4LV-64/32

M4-96/48, M4LV-96/48

M4-128/64, M4LV-128/64

M4-128N/64, M4LV-128N/64

M4-192/96, M4LV-192/96

M4-256/128, M4LV-256/128

M4-32/32

M4LV-32/32

Macrocell-I/O Cell

Ratio 2:1 1:1

Input Switch Matrix Yes Yes

Input Registers Yes No

Central Switch Matrix Yes Yes

Output Switch Matrix Yes Yes

MACH 4A Devices

M4A3-64/32, M4A5-64/32

M4A3-96/48, M4A5-96/48

M4A3-128/64, M4A5-128/64

M4A3-192/96, M4A5-192/96

M4A3-256/128, M4A5-256/128

M4A3-384

M4A3-512

M4A3-32/32

M4A5-32/32

M4A3-64/64

M4A3-128/96, M4A3-128/128

M4A3-256/160

M4A3-256/192

M4A3-192/68, M4A3-192/128

Macrocell-I/O Cell

Ratio 2:1 1:1

Input Switch Matrix Yes Yes

Input Registers Yes No

Central Switch Matrix Yes Yes

Output Switch Matrix Yes Yes

10 MACH 4 Family

Each PAL block consists of:

◆

Product-term array

◆

Logic allocator

◆

Macrocells

◆

Output switch matrix

◆

I/O cells

◆

Input switch matrix

◆

Clock generator

Product-Term Array

The product-term array consists of a number of product ter ms that form the basis of the logic

being implemented. The inputs to the AND gates come from the central switch matrix (T able 9),

and are provided in both true and complement forms for ef ﬁcient logic implementation.

Because the number of product terms available for a given logic function is not ﬁxed, the full

sum of products is not realized in the array. The product terms drive the logic allocator, which

allocates the appropriate number of product terms to generate the function.

Logic Allocator

Within the logic allocator, product terms are allocated to macrocells in “product term clusters.”

The availability and distribution of product term clusters are automatically considered by the

software as it ﬁts functions within a PAL block. The size of a product term cluster has been

optimized to provide high utilization of product terms, making complex functions using many

product terms possible. Yet when few product terms are used, there will be a minimal number

Table 9. PAL Block Inputs

Device Number of Inputs to PAL Block

M4-32/32 and M4LV-32/32

M4-64/32 and M4LV-64/32

M4-96/48 and M4LV-96/48

M4-128/64 and M4LV-128/64

M4-128N/64 and M4LV-128N/64

M4-192/96 and M4LV-192/96

M4-256/128 and M4LV-256/128 34

M4A3-32/32 and M4A5-32/32

M4A3-64/32 and M4A5-64/32

M4A3-96/48 and M4A5-96/48

M4A3-128/64 and M4A5-128/64

M4A3-192/96 and M4A5-192/96

M4A3-256/128 and M4A5-256/128 34

M4A3-64/64

M4A3-128/96 and M4A3-128/128

M4A3-192/68 and M4A3-192/128

M4A3-256/160 and M4A3-256/192

M4A3-384

M4A3-512

MACH 4 Family 11

of unused—or wasted—product terms left over. The product term clusters available to each

macrocell within a PAL block are shown in Tables 10 and 11.

Each product term cluster is associated with a macrocell. The size of a cluster depends on the

conﬁguration of the associated macrocell. When the macrocell is used in synchronous mode

(Figure 2a), the basic cluster has 4 product terms. When the associated macrocell is used in

asynchronous mode (Figure 2b), the cluster has 2 product terms. Note that if the product ter m

cluster is routed to a different macrocell, the allocator conﬁguration is not deter mined by the

mode of the macrocell actually being driven. The conﬁguration is always set by the mode of the

macrocell that the cluster will drive if not routed away, regardless of the actual routing.

In addition, there is an extra product term that can either join the basic cluster to give an

extended cluster, or drive the second input of an exclusive-OR gate in the signal path. If included

with the basic cluster, this provides for up to 20 product ter ms on a synchronous function that

uses four extended 5-product-term clusters. A similar asynchronous function can have up to 18

product terms.

When the extra product term is used to extend the cluster, the value of the second XOR input

can be programmed as a 0 or a 1, giving polarity control. The possible conﬁgurations of the logic

allocator are shown in Figures 3 and 4.

12 MACH 4 Family

Table 10. Logic Allocator for All MACH 4 and MACH 4A Devices (except M4(LV)-32/32 and M4A(3,5)-32/32)

Output Macrocell Available Clusters Output Macrocell Available Clusters

M0C0, C1, C2M8C7, C8, C9, C10

M1C0, C1, C2, C3M9C8, C9, C10, C11

M2C1, C2, C3, C4M10 C9, C10, C11, C12

M3C2, C3, C4, C5M11 C10, C11, C12, C13

M4C3, C4, C5, C6M12 C11, C12, C13, C14

M5C4, C5, C6, C7M13 C12, C13, C14, C15

M6C5, C6, C7, C8M14 C13, C14, C15

M7C6, C7, C8, C9M15 C14, C15

Table 11. Logic Allocator for M4(LV)-32/32 and M4A(3,5)-32/32

Output Macrocell Available Clusters Output Macrocell Available Clusters

M0C0, C1, C2M8C8, C9, C10

M1C0, C1, C2, C3M9C8, C9, C10, C11

M2C1, C2, C3, C4M10 C9, C10, C11, C12

M3C2, C3, C4, C5M11 C10, C11, C12, C13

M4C3, C4, C5, C6M12 C11, C12, C13, C14

M5C4, C5, C6, C7M13 C12, C13, C14, C15

M6C5, C6, C7M14 C13, C14, C15

M7C6, C7M15 C14, C15

0 Default

Prog. Polarity

To n-1

To n-2

From n-1

To n+1

From n+1

From n+2

Basic Product

Term Cluster

Extra

Product

Term

Logic Allocator

To Macrocell

0 Default

Prog. Polarity

To n-1

To n-2

From n-1

To n+1

From n+1

From n+2

Basic Product

Term Cluster

Extra

Product

Term

Logic Allocator

To Macrocell

17466G-006

Figure 2. Logic Allocator: Conﬁguration of Cluster “n” Set by Mode of Macrocell “n”

17466G-005

a. Synchronous Mode

b. Asynchronous Mode

MACH 4 Family 13

Note that the conﬁguration of the logic allocator has absolutely no impact on the speed of the

signal. All conﬁgurations have the same delay. This means that designers do not have to decide

between optimizing resources or speed; both can be optimized.

If not used in the cluster, the extra product term can act in conjunction with the basic cluster to

provide XOR logic for such functions as data comparison, or it can work with the D-,T-type ﬂip-

ﬂop to provide for J-K, and S-R register operation. In addition, if the basic cluster is routed to

another macrocell, the extra product term is still available for logic. In this case, the ﬁrst XOR

input will be a logic 0. This circuit has the ﬂexibility to route product terms elsewhere without

giving up the use of the macrocell.

Product term clusters do not “wrap” around a PAL block. This means that the macrocells at the

ends of the block have fewer product terms available.

17466G-007

Figure 3. Logic Allocator Conﬁgurations: Synchronous Mode

a. Basic cluster with XOR b. Extended cluster, active high c. Extended cluster, active low

d. Basic cluster routed away;

single-product-term, active high e. Extended cluster routed away

17466G-008

Figure 4. Logic Allocator Conﬁgurations: Asynchronous Mode

b. Extended cluster, active high c. Extended cluster, active low

e. Extended cluster routed away

d. Basic cluster routed away;

single-product-term, active high

a. Basic cluster with XOR

14 MACH 4 Family

Macrocell

The macrocell consists of a storage element, routing resources, a clock multiplexer, and

initialization control. The macrocell has two fundamental modes: synchronous and

asynchronous (Figure 5). The mode chosen only affects clocking and initialization in the

macrocell.

In either mode, a combinatorial path can be used. For combinatorial logic, the synchronous

mode will generally be used, since it provides more product terms in the allocator.

SWAP

D/T/L Q

AP AR

Power-Up

Reset

PAL-Block

Initialization

Product Terms

From Logic Allocator

Block CLK0

Block CLK1

Block CLK2

Block CLK3

To Output and Input

Switch Matrices

Common PAL-block resource

Individual macrocell resources

From

PAL-Clock

Generator

D/T/L Q

AP AR

Power-Up

Reset

Individual

Initialization

Product Term

From Logic

Allocator

Block CLK0

Block CLK1

To Output and Input

Switch Matrices

Individual Clock

Product Term

From PAL-Block

Clock Generator

17466G-010

Figure 5. Macrocell

17466G-009

a. Synchronous mode

b. Asynchronous mode

MACH 4 Family 15

The ﬂip-ﬂop can be conﬁgured as a D-type or T-type latch. J-K or S-R registers can be

synthesized. The primary ﬂip-ﬂop conﬁgurations are shown in Figure 6, although others are

possible. Flip-ﬂop functionality is deﬁned in Table 12. Note that a J-K latch is inadvisable as it

will cause oscillation if both J and K inputs are HIGH.

AP AR DQ

AP AR

AP AR LQ

AP AR

17466G-011

Figure 6. Primary Macrocell Conﬁgurations

g. Combinatorial with programmable polarity

a. D-type with XOR b. D-type with programmable D polarity

c. Latch with XOR d. Latch with programmable D polarity

e. T-type with programmable T polarity

f. Combinatorial with XOR

16 MACH 4 Family

Note:

1. Polarity of CLK/LE can be programmed

Although the macrocell shows only one input to the register , the XOR gate in the logic allocator

allows the D-, T-type register to emulate J-K, and S-R behavior. In this case, the available product

terms are divided between J and K (or S and R). When conﬁgured as J-K, S-R, or T-type, the

extra product term must be used on the XOR gate input for ﬂip-ﬂop emulation. In any register

type, the polarity of the inputs can be programmed.

The clock input to the ﬂip-ﬂop can select any of the four P AL block clocks in synchronous mode,

with the additional choice of either polarity of an individual product term clock in the

asynchronous mode.

The initialization circuit depends on the mode. In synchronous mode (Figure 7), asynchronous

reset and preset are provided, each driven by a product term common to the entire PAL block.

Table 12. Register/Latch Operation

Conﬁguration Input(s) CLK/LE 1Q+

D-type Register D=X

D=0

D=1

0,1, ↓ (↑)

↑ (↓)

T-type Register T=X

T=0

T=1

0, 1, ↓ (↑)

↑ (↓)

D-type Latch D=X

D=0

D=1

1(0)

0(1)

Power-Up

Reset

D/T/L AR

PAL-Block

Initialization

Product Terms

a. Power-up reset

Power-Up

Preset

D/L

PAL-Block

Initialization

Product Terms

17466G-012 17466G-013

Figure 7. Synchronous Mode Initialization Conﬁgurations

b. Power-up preset

MACH 4 Family 17

A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged,

providing ﬂexibility. In asynchronous mode (Figure 8), a single individual product term is

provided for initialization. It can be selected to control reset or preset.

Note that the reset/preset swapping selection feature effects power-up reset as well. The

initialization functionality of the ﬂip-ﬂops is illustrated in T able 13. The macrocell sends its data

to the output switch matrix and the input switch matrix. The output switch matrix can route this

data to an output if so desired. The input switch matrix can send the signal back to the central

switch matrix as feedback.

Note:

1. Transparent latch is unaffected by AR, AP

Output Switch Matrix

The output switch matrix allows macrocells to be connected to any of several I/O cells within a

PAL block. This provides high ﬂexibility in determining pinout and allows design changes to

occur without effecting pinout.

In MACH 4 and MACH 4A devices with 2:1 Macrocell-I/O cell ratio, each PAL block has twice as

many macrocells as I/O cells. The MACH 4 output switch matrix allows for half of the macrocells

to drive I/O cells within a PAL block, in combinations according to Figure 9. Each I/O cell can

choose from eight macrocells; each macrocell has a choice of four I/O cells. The MACH 4 and

MACH 4A devices with 1:1 Macrocell-I/O cell ratio allow each macrocell to drive one of eight I/

O cells (Figure 9).

Table 13. Asynchronous Reset/Preset Operation

AR AP CLK/LE1Q+

0 0 X See Table 12

01X1

10X0

11X0

Power-Up

Reset

D/L/T AR

Individual

Reset

Product Term

a. Reset

Power-Up

Preset

D/L/T AR

Individual

Preset

Product Term

b. Preset

17466G-014 17466G-015

Figure 8. Asynchronous Mode Initialization Conﬁgurations

18 MACH 4 Family

Table 14. Output Switch Matrix Combinations for MACH 4 and MACH 4A

Devices with 2:1 Macrocell-I/O Cell Ratio

Macrocell Routable to I/O Cells

M0, M1 I/O0, I/O5, I/O6, I/O7

M2, M3 I/O0, I/O1, I/O6, I/O7

M4, M5 I/O0, I/O1, I/O2, I/O7

M6, M7 I/O0, I/O1, I/O2, I/O3

M8, M9 I/O1, I/O2, I/O3, I/O4

M10, M11 I/O2, I/O3, I/O4, I/O5

M12, M13 I/O3, I/O4, I/O5, I/O6

M14, M15 I/O4, I/O5, I/O6, I/O7

I/O Cell Available Macrocells

I/O0 M0, M1, M2, M3, M4, M5, M6, M7

I/O1 M2, M3, M4, M5, M6, M7, M8, M9

I/O2 M4, M5, M6, M7, M8, M9, M10, M11

I/O3 M6, M7, M8, M9, M10, M11, M12, M13

I/O4 M8, M9, M10, M11, M12, M13, M14, M15

I/O5 M0, M1, M10, M11, M12, M13, M14, M15

Figure 9. MACH 4 Output Switch Matrix

M10

M11

M12

M13

M14

M15

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

Each macrocell can drive

one of 4 I/O cells in MACH 4

and MACH 4A devices with

2:1 macrocell-I/O cell ratio.

Each I/O cell can

choose one of 8

macrocells in

all MACH 4 and

MACH 4A devices.

macrocells

MUX

I/O cell

M10

M11

M12

M13

M14

M15

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O8

I/O9

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

Each macrocell can drive

one of 8 I/O cells in MACH

4A devices with 1:1

macrocell-I/O cell ratio except

M4A(3, 5)-32/32 devices.

M10

M11

M12

M13

M14

M15

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O8

I/O9

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

Each macrocell can drive

one of 8 I/O cells in

M4(LV)-32/32 and

M4A(3, 5)-32/32 devices.

MACH 4 Family 19

I/O6 M0, M1, M2, M3, M12, M13, M14, M15

I/O7 M0, M1, M2, M3, M4, M5, M14, M15

Table 15. Output Switch Matrix Combinations for MACH 4 and MACH 4A Devices with 1:1 Macrocell-I/O Cell

Ratio except M4(LV)-32/32 and M4A(3,5)-32/32

Macrocell Routable to I/O Cells

M0 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

M1 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

M2 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

M3 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

M4 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

M5 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

M6 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

M7 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

M8 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15

M9 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15

M10 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15

M11 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15

M12 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15

M13 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15

M14 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15

M15 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15

I/O Cell Available Macrocells

I/O0 M0 M1 M2 M3 M4 M5 M6 M7

I/O1 M0 M1 M2 M3 M4 M5 M6 M7

I/O2 M0 M1 M2 M3 M4 M5 M6 M7

I/O3 M0 M1 M2 M3 M4 M5 M6 M7

I/O4 M0 M1 M2 M3 M4 M5 M6 M7

I/O5 M0 M1 M2 M3 M4 M5 M6 M7

I/O6 M0 M1 M2 M3 M4 M5 M6 M7

I/O7 M0 M1 M2 M3 M4 M5 M6 M7

I/O8 M8 M9 M10 M11 M12 M13 M14 M15

I/O9 M8 M9 M10 M11 M12 M13 M14 M15

I/O10 M8 M9 M10 M11 M12 M13 M14 M15

I/O11 M8 M9 M10 M11 M12 M13 M14 M15

I/O12 M8 M9 M10 M11 M12 M13 M14 M15

I/O13 M8 M9 M10 M11 M12 M13 M14 M15

I/O14 M8 M9 M10 M11 M12 M13 M14 M15

I/O15 M8 M9 M10 M11 M12 M13 M14 M15

Table 14. Output Switch Matrix Combinations for MACH 4 and MACH 4A

Devices with 2:1 Macrocell-I/O Cell Ratio

Macrocell Routable to I/O Cells

20 MACH 4 Family

Table 16. Output Switch Matrix Combinations for M4(LV)-32/32 and M4A(3,5)-32/32

Macrocell Routable to I/O Cells

M0, M1, M2, M3, M4, M5, M6, M7 I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7

M8, M9, M10, M11, M12, M13, M14, M15 I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15

I/O Cell Available Macrocells

I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7 M0, M1, M2, M3, M4, M5, M6, M7

I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15 M8, M9, M10, M11, M12, M13, M14, M15

MACH 4 Family 21

I/O Cell

The I/O cell (Figures 10 and 11) simply consists of a programmable output enable, a feedback

path, and ﬂip-ﬂop (except MACH 4 and MACH 4A devices with 1:1 macrocell-I/O cell ratio.) An

individual output enable product term is provided for each I/O cell. The feedback signal drives

the input switch matrix.

The I/O cell (Figure 10) contains a ﬂip-ﬂop, which provides the capability for storing the input

in a D-type register or latch. The clock can be any of the PAL block clocks. Both the direct and

registered versions of the input are sent to the input switch matrix. This allows for such functions

as “time-domain-multiplexed” data comparison, where the ﬁrst data value is stored, and then the

second data value is put on the I/O pin and compared with the previous stored value.

Note that the ﬂip-ﬂop used in the MACH 4 I/O cell is independent of the ﬂip-ﬂops in the

macrocells. It powers up to a logic low.

Zero-Hold-Time Input Register

The MACH 4 devices have a zero-hold-time (ZHT) fuse which controls the time delay associated

with loading data into all I/O cell registers and latches. When programmed, the ZHT fuse

increases the data path setup delays to input storage elements, matching equivalent delays in

the clock path. When the fuse is erased, the setup time to the input storage element is minimized.

This feature facilitates doing worst-case designs for which data is loaded from sources which

have low (or zero) minimum output propagation delays from clock edges.

Input Switch Matrix

The input switch matrix (Figures 12 and 13) optimizes routing of inputs to the central switch

matrix. Without the input switch matrix, each input and feedback signal has only one way to

enter the central switch matrix. The input switch matrix provides additional ways for these

signals to enter the central switch matrix.

D/L

Block CLK3

Block CLK2

Block CLK1

Block CLK0

Input

Switch

Matrix

Individual

Output Enable

Product Term

From Output

Switch Matrix

17466G-017 17466G-018

Figure 10. I/O Cell for MACH 4 and MACH 4A Devices

with 2:1 Macrocell-I/O Cell Ratio Figure 11. I/O Cell for MACH 4 and MACH 4A Devices

with 1:1 Macrocell-I/O Cell Ratio

Input

Switch

Matrix

Individual

Output Enable

Product Term

From Output

Switch Matrix

Power-up reset

22 MACH 4 Family

PAL Block Clock Generation

Each MACH 4 device has four clock pins that can also be used as inputs. These pins drive a

clock generator in each PAL block (Figure 14). The clock generator provides four clock signals

that can be used anywhere in the PAL block. These four PAL block clock signals can consist of

a large number of combinations of the true and complement edges of the global clock signals.

Table 17 lists the possible combinations.

Note:

1. M4(L V)-32/32, M4A(3,5)-32/32, M4(L V)-64/32 and M4A(3,5)-64/32 have only two clock pins, GCLK0 and GCLK1. GCLK2 is tied

to GCLK0, and GCLK3 is tied to GCLK1.

To Central Switch Matrix

From Macrocell 2

From Input Cell

Direct

From Macrocell 1

Registered/Latched

17466G-002 17466G-003

Figure 12. MACH 4 and MACH 4A with 2:1

Macrocell-I/O Cell Ratio - Input Switch Matrix Figure 13. MACH 4 and MACH 4A with 1:1

Macrocell-I/O Cell Ratio - Input Switch Matrix

To Central Switch Matrix

From Macrocell

From I/O Pin

GCLK0

GCLK1

GCLK2

GCLK3

Block CLK0

(GCLK0 or GCLK1)

Block CLK1

(GCLK1 or GCLK0)

Block CLK2

(GCLK2 or GCLK3)

Block CLK3

(GCLK3 or GCLK2)

17466G-004

Figure 14. PAL Block Clock Generator 1

MACH 4 Family 23

Note:

1. Values in parentheses are for the M4(LV)-32/32, M4A(3,5)-32/32, M4(LV)-64/32 and M4A(3,5)-64/32.

This feature provides high ﬂexibility for partitioning state machines and dual-phase clocks. It

also allows latches to be driven with either polarity of latch enable, and in a master-slave

conﬁguration.

Table 17. PAL Block Clock Combinations1

Block CLK0 Block CLK1 Block CLK2 Block CLK3

GCLK0

GCLK1

GCLK0

GCLK1

GCLK0

GCLK2 (GCLK0)

GCLK3 (GCLK1)

GCLK2 (GCLK0)

GCLK3 (GCLK1)

GCLK2 (GCLK0)

24 MACH 4 Family

MACH 4 TIMING MODEL

The primary focus of the MACH 4 timing model is to accurately represent the timing in a MACH

4 device, and at the same time, be easy to understand. This model accurately describes all

combinatorial and registered paths through the device, making a distinction between inter nal

feedback and external feedback. A signal uses internal feedback when it is fed back into the

switch matrix or block without having to go through the output buffer. The input register

speciﬁcations are also reported as internal feedback. When a signal is fed back into the switch

matrix after having gone through the output buffer, it is using external feedback.

The parameter , tBUF, is deﬁned as the time it takes to go from feedback through the output buffer

to the I/O pad. If a signal goes to the internal feedback rather than to the I/O pad, the parameter

designator is followed by an “i”. By adding tBUF to this internal parameter, the external parameter

is derived. For example, tPD = tPDi + tBUF. A diagram representing the modularized MACH 4

timing model is shown in Figure 15. Refer to the Technical Note entitled MACH 4 Timing and

High Speed Design for a more detailed discussion about the timing parameters.

SPEEDLOCKING FOR GUARANTEED FIXED TIMING

The MACH 4 architecture allows allocation of up to 20 product terms to an individual macrocell

with the assistance of an XOR gate without incurring additional timing delays.

The design of the switch matrix and PAL blocks guarantee a ﬁxed pin-to-pin delay that is

independent of the logic required by the design. Other non-Vantis CPLDs incur serious timing

delays as product terms expand beyond their typical 4 or 5 product ter m limits. Speed and

SpeedLocking combine to give designs easy access to the perfor mance required in today’s

designs.

(External Feedback)

(Internal Feedback)

INPUT REG/

INPUT LATCH

tSIRS

tHIRS

tSIL

tHIL

tSIRZ

tHIRZ

tSILZ

tHILZ

tPDILi

tICOSi

tIGOSi

tPDILZi

tSS(T)

tSA(T)

tH(S/A)

tS(S/A)L

tH(S/A)L

tSRR

tPDi

tPDLi

tCO(S/A)i

tGO(S/A)i

tSRi

COMB/DFF/TFF/

LATCH/SR*/JK*

S/R

BLK CLK

OUT

tPL

tBUF

tEA

tER

tSLW

Central

Switch

Matrix

*emulated

17466G-025

Figure 15. MACH 4 Timing Model

MACH 4 Family 25

IEEE 1149.1-COMPLIANT BOUNDARY SCAN TESTABILITY

All MACH 4 devices, except the M4(LV)-128N/64, have boundary scan cells and are compliant

to the IEEE 1149.1 standard. This allows functional testing of the circuit board on which the

device is mounted through a serial scan path that can access all critical logic nodes. Internal

registers are linked internally, allowing test data to be shifted in and loaded directly onto test

nodes, or test node data to be captured and shifted out for veriﬁcation. In addition, these devices

can be linked into a board-level serial scan path for more complete board-level testing.

IEEE 1149.1-COMPLIANT IN-SYSTEM PROGRAMMING

Programming devices in-system provides a number of signiﬁcant beneﬁts including: rapid

prototyping, lower inventory levels, higher quality, and the ability to make in-ﬁeld modiﬁcations.

All MACH 4 devices provide In-System Programming (ISP) capability through their Boundary

ScanTest Access Ports. This capability has been implemented in a manner that ensures that the

port remains compliant to the IEEE 1149.1 standard. By using IEEE 1149.1 as the communication

interface through which ISP is achieved, customers get the beneﬁt of a standard, well-deﬁned

interface.

MACH 4 devices can be programmed across the commercial temperature and voltage range.

V antis provides its free PC-based Lattice/V antisPRO software to facilitate in-system programming.

Lattice/VantisPRO takes the JEDEC ﬁle output produced by Vantis’ design implementation

software, along with information about the JT AG chain, and creates a set of vectors that are used

to drive the JTAG chain. Lattice/VantisPRO software can use these vectors to drive a JTAG chain

via the parallel port of a PC. Alternatively, Lattice/V antisPRO software can output ﬁles in formats

understood by common automated test equipment. This equpment can then be used to program

MACH 4 devices during the testing of a circuit board. For more information about in-system

programming, refer to the separate document entitled MACH ISP Manual.

PCI COMPLIANT

MACH 4(A) devices in the -5/-55/-6/-65/-7/-10/-12 speed grades are compliant with the PCI

Local Bus Speciﬁcation version 2.1, published by the PCI Special Interest Group (SIG). The 5-V

devices are fully PCI-compliant. The 3.3-V devices are mostly compliant but do not meet the PCI

condition to clamp the inputs as they rise above VCC because of their 5-V input tolerant feature.

SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS

Both the 3.3-V and 5-V VCC MACH 4 devices are safe for mixed supply voltage system designs.

The 5-V devices will not overdrive 3.3-V devices above the output voltage of 3.3 V, while they

accept inputs from other 3.3-V devices. The 3.3-V device will accept inputs up to 5.5 V . Both the

5-V and 3.3-V versions have the same high-speed perfor mance and provide easy-to-use mixed-

voltage design capability.

PULL UP OR BUS-FRIENDLY INPUTS AND I/OS

All MACH 4 devices have inputs and I/Os which feature the Bus-Friendly circuitry incorporating

two inverters in series which loop back to the input. This double inversion weakly holds the

input at its last driven logic state. While it is good design practice to tie unused pins to a known

state, the Bus-Friendly input structure pulls pins away from the input threshold voltage where

noise can cause high-frequency switching. At power-up, the Bus-Friendly latches are reset to a

26 MACH 4 Family

logic level “1.” For the circuit diagram, please refer to the Input/Output Equivalent Schematics

(page 393) in the General Information Section of the Vantis 1999 Data Book.

All MACH 4A devices have a programmable bit that conﬁgures all inputs and I/Os with either

pull-up or Bus-Friendly characteristics. If the device is conﬁgured in pull-up mode, all inputs

and I/O pins are weakly pulled up. For the circuit diagram, please refer to the Input/Output

Equivalent Schematics (page 393) in the General Information Section of the Vantis 1999 Data

Book.

POWER MANAGEMENT

Each individual PAL block in MACH 4 devices features a programmable low-power mode, which

results in power savings of up to 50%. The signal speed paths in the low-power PAL block will

be slower than those in the non-low-power PAL block. This feature allows speed critical paths

to run at maximum frequency while the rest of the signal paths operate in the low-power mode.

PROGRAMMABLE SLEW RATE

Each MACH 4 device I/O has an individually programmable output slew rate control bit. Each

output can be individually conﬁgured for the higher speed transition (3 V/ns) or for the lower

noise transition (1 V/ns). For high-speed designs with long, unterminated traces, the slow-slew

rate will introduce fewer reﬂections, less noise, and keep ground bounce to a minimum. For

designs with short traces or well terminated lines, the fast slew rate can be used to achieve the

highest speed. The slew rate is adjusted independent of power.

POWER-UP RESET/SET

All ﬂip-ﬂops power up to a known state for predictable system initialization. If a macrocell is

conﬁgured to SET on a signal from the control generator , then that macrocell will be SET during

device power-up. If a macrocell is conﬁgured to RESET on a signal from the control generator

or is not conﬁgured for set/reset, then that macrocell will RESET on power-up. To guarantee

initialization values, the VCC rise must be monotonic, and the clock must be inactive until the

reset delay time has elapsed.

SECURITY BIT

A programmable security bit is provided on the MACH 4 devices as a deterrent to unauthorized

copying of the array conﬁguration patterns. Once programmed, this bit defeats readback of the

programmed pattern by a device programmer, securing proprietary designs from competitors.

Programming and veriﬁcation are also defeated by the security bit. The bit can only be reset by

erasing the entire device.

HOT SOCKETING

MACH 4A devices are well-suited for those applications that require hot socketing capability.

Hot socketing a device requires that the device, when powered down, can tolerate active signals

on the I/Os and inputs without being damaged. Additionally, it requires that the effects of the

powered-down MACH devices be minimal on active signals.

MACH 4 Family 27

MACROCELL

M10

M11

M12

M13

M14

M15

M4(LV)-64/32, M4A(3, 5)-64/32

M4(LV)-96/48, M4A(3, 5)-96/48

M4(LV)-128/64, M4A(3, 5)-128/64

B16

17 17

M4(LV)-192/96, M4(3, 5)-192/96

M4(LV)-256/128, M4(3, 5)-256/128 M4A3-384

M4A3-512

M10

M11

M12

M13

M14

O7M15

CLK0

CLK1

CLK2

CLK3

I/O

CELL

I/O0

CLOCK

GENERATOR

MACROCELL

CENTRAL SWITCH MATRIX

MACROCELL

16 16

I/O

CELL

I/O1

I/O

CELL

I/O2

C6 I/O

CELL

I/O3

C8 I/O

CELL

I/O4

C10 I/O

CELL

I/O5

C11

C12 I/O

CELL

I/O6

C13

C14 I/O

CELL

INPUT SWITCH

MATRIX

I/O7

C15

LOGIC ALLOCA TOR

OUTPUT SWITCH MATRIX

Figure 16. PAL Block for MACH 4 and MACH 4A with 2:1 Macrocell - I/O Cell Ratio

17466H-40

28 MACH 4 Family

Figure 17. PAL Block for MACH 4A Devices with 1:1 Macrocell-I/O Cell Ratio (except M4A (3,5)-32/32)

17466H-41

MACH 4 Family 29

MACROCELL

M10

M11

M12

M13

M14

M15

M10

M11

M12

M13

M14

O10

O12

O14

M15

I/O

CELL I/O0

CLOCK

GENERATOR

MACROCELL

CENTRAL SWITCH MATRIX

MACROCELL

O1 I/O

CELL

I/O1

C2 I/O

CELL

I/O2

O3 I/O

CELL

I/O3

O5 I/O

CELL

I/O5

O7 I/O

CELL

I/O7

C4 I/O

CELL

I/O4

C6 I/O

CELL

I/O6

C8 I/O

CELL

I/O8

O9 I/O

CELL

I/O9

O11 I/O

CELL

I/O11

C0 I/O

CELL

I/O10

C0 I/O

CELL

I/O12

O13 I/O

CELL

I/O13

O15 I/O

CELL

I/O15

C0 I/O

CELL

INPUT

SWITCH

MATRIX

I/O14

LOGIC ALLOCATOR

OUTPUT SWITCH MATRIX

CLK0/I0 CLK0/I1

Figure 18. PAL Block for M4(LV)-32/32 and M4A (3,5)-32/32

17466H-042

30 MACH 4 Family

BLOCK DIAGRAM – M4(LV)-32/32 AND M4A(3,5)-32/32

Central Switch Matrix

CLK0/I0, CLK1/I1

I/O8–I/O15 I/O0–I/O7

I/O16–I/O23 I/O24–I/O31

I/O Cells

Output Switch

Matrix

Macrocells

4 4

I/O Cells

Output Switch

Matrix

Macrocells

66 X 98

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

I/O Cells

Output Switch

Matrix

Macrocells

I/O Cells

Output Switch

Matrix

Macrocells

66 X 98

AND Logic Array

and Logic Allocator

Input Switch

Matrix

Input Switch

Matrix

Input Switch

Matrix

Clock Generator

Block A

Block B

17466H-019

MACH 4 Family 31

BLOCK DIAGRAM – M4(LV)-64/32 AND M4A(3,5)-64/32

Central Switch Matrix

CLK0/I0, CLK1/I1

I/O0–I/O7 I/O24–I/O31

I/O16–I/O23I/O8–I/O15

I/O Cells

Output Switch

Matrix

Macrocells

66 X 90

AND Logic Array

and Logic Allocator

Clock Generator

I/O Cells

Output Switch

Matrix

Macrocells

66 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

I/O Cells

Output Switch

Matrix

Macrocells

66 X 90

AND Logic Array

and Logic Allocator

I/O Cells

Output Switch

Matrix

Macrocells

66 X 90

AND Logic Array

and Logic Allocator

Input Switch

Matrix

Input Switch

Matrix

Input Switch

Matrix

Clock Generator

Block A

Block B

Block D

Block C

17466H-020

MACH 4 Family 32

BLOCK DIAGRAM – M4(LV)-96/48 AND M4A(3,5)-96/48

444

CLK0/I0, CLK1/I1,

CLK2/I4, CLK3/I5

I2, I3, I6, I7

I/O16–I/O23 I/O8–I/O15 I/O0–I/O7

I/O40–I/O47I/O32–I/O39I/O24–I/O31

I/O Cells

Output Switch

Matrix

Macrocells

66 X 90

AND Logic Array

and Logic Allocator

Clock Generator

I/O Cells

Output Switch

Matrix

Macrocells

66 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

I/O Cells

Output Switch

Matrix

Macrocells

66 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

I/O Cells

Output Switch

Matrix

Macrocells

66 X 90

AND Logic Array

and Logic Allocator

I/O Cells

Output Switch

Matrix

Macrocells

66 X 90

AND Logic Array

and Logic Allocator

I/O Cells

Output Switch

Matrix

Macrocells

66 X 90

AND Logic Array

and Logic Allocator

Input Switch

Matrix Input Switch

Matrix

Input Switch

Matrix

Clock Generator

Input Switch

Matrix

CBl

BBl

Block D Block E Block F

Central Switch Matrix

17466G-021

33 MACH 4 Family

Central Switch Matrix

442

CLK0/I0, CLK1/I1,

CLK2/I3, CLK3/I4

I2, I5

I/O0–I/O7I/O8–I/O15I/O16–I/O23I/O24–I/031

I/O32–I/O39 I/O40–I/O47 I/O48–I/O55 I/O56–I/O63

I/O Cells

Output Switch

Matrix

Macrocells

66 X 90

AND Logic Array

and Logic Allocator

Clock Generator

I/O Cells

Output Switch

Matrix

Macrocells

66 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

I/O Cells

Output Switch

Matrix

Macrocells

66 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

I/O Cells

Output Switch

Matrix

Macrocells

66 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

I/O Cells

Output Switch

Matrix

Macrocells

66 X 90

AND Logic Array

and Logic Allocator

I/O Cells

Output Switch

Matrix

Macrocells

66 X 90

AND Logic Array

and Logic Allocator

I/O Cells

Output Switch

Matrix

Macrocells

66 X 90

AND Logic Array

and Logic Allocator

I/O Cells

Output Switch

Matrix

Macrocells

66 X 90

AND Logic Array

and Logic Allocator

Input Switch

Matrix Input Switch

Matrix

Input Switch

Matrix

Clock Generator

Input Switch

Matrix

Input Switch

Matrix

Clock Generator

Block ABlock BBlock CBlock D

Block HBlock GBlock FBlock E

BLOCK DIAGRAM – M4(LV)-128N/64, M4(LV)-128/64 AND M4A(3,5)-128/64

17466H-022

MACH 4 Family 34

BLOCK DIAGRAM – M4(LV)-192/96 AND M4A(3,5)-192/96

Central Switch Matrix

Block B

I/O8–I/O15 CLK0–CLK3

I/O32–I/O39

Block E I/O56–I/O63

Block H

I/O48–I/O55

Block G

I0–I15

I/O40–I/O47

Block F

Block A

I/O0–I/O7 Block K

I/O80–I/O87

Block L

I/O88–I/O95

Block C I/O16–I/O23

Block D I/O24–I/O31 I/O72–I/O79 Block J

I/O64–I/O71 Block I

I/O Cells

Macrocells

68 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

68 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

68 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

68 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

68 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

68 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

68 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

68 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

68 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

68 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

68 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

68 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

4 4

24 34

34 34 34 34

17466G-064

35 MACH 4 Family

BLOCK DIAGRAM – M4(LV)-256/128 AND M4A(3,5)-256/128

Central Switch Matrix

Block B

I/O8–I/O15 CLK0–CLK3

I/O48–I/O55

Block G I/O72–I/O79

Block J

I/O64–I/O71

Block I

I0–I13

I/O56–I/O63

Block H

Block A

I/O0–I/O7 Block O

I/O112–I/O119

Block P

I/O120–I/O127

Block C I/O16–I/O23

Block D I/O24–I/O31

Block E I/O32–I/O39

Block F I/O40–I/O47

I/O104–I/O111 Block N

I/O96–I/O103 Block M

I/O88–I/O95 Block L

I/O80–I/O87 Block K

I/O Cells

Macrocells

68 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

68 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

68 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

68 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

68 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

68 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

68 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

68 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

68 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

68 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

68 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

68 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

68 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

68 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

68 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

68 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

4 4

24 34

34 24

24 34

34 24

17466G-024

MACH 4 Family 36

BLOCK DIAGRAM – M4A3-384/192

Central Switch Matrix

Block B

I/O8–I/O15 CLK0–CLK3

Block A

I/O0–I/O7 Block GX

I/O176–I/O183

Block HX

I/O184–I/O191

Block C I/O16–I/O23

Block F I/O40–I/O47 Block D I/O24–I/O31

Block E I/O32–I/O39 I/O168–I/O175 Block FX

I/O144–I/O151 Block CX

I/O160–I/O167 Block EX

I/O152–I/O159 Block DX

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

4 4

24 36

36 24

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

24 36

36 24

Block G I/O48–I/O55

Block J I/O72–I/O79 Block H I/O56–I/O63

Block I I/O64–I/O71 I/O136–I/O143 Block BX

I/O112–I/O119 Block O

I/O128–I/O135 Block AX

I/O120–I/O127 Block P

Detail A

Repeat Detail A

I/O88–I/O95

Block L

I/O80–I/O87

Block K I/O196–I/O103

Block M I/O104–I/O111

Block N

17466G-067

37 MACH 4 Family

BLOCK DIAGRAM - M4A3-512/256

Central Switch Matrix

Block B

I/O8–I/O15 CLK0–CLK3

Block A

I/O0–I/O7 Block OX

I/O240–I/O247

Block PX

I/O248–I/O255

Block C I/O16–I/O23

Block F I/O40–I/O47 Block D I/O24–I/O31

Block E I/O32–I/O39 I/O232–I/O239 Block NX

I/O208–I/O215 Block KX

I/O224–I/O231 Block MX

I/O216–I/O223 Block LX

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

24 36

36 24

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

I/O Cells

Macrocells

72 X 90

AND Logic Array

and Logic Allocator

Clock Generator

Input Switch

Matrix

Output Switch

Matrix

24 36

36 24

Block G I/O48–I/O55

Block J I/O72–I/O79 Block H I/O56–I/O63

Block I I/O64–I/O71 I/O200–I/O207 Block JX

I/O176–I/O183 Block GX

I/O192–I/O199 Block IX

I/O184–I/O191 Block HX

Block K I/O80–I/O87

Block N I/O104–I/O111 Block L I/O88–I/O95

Block M I/O96–I/O103 I/O168–I/O175 Block FX

I/O144–I/O151 Block CX

I/O160–I/O167 Block EX

I/O152–I/O159 Block DX

Detail A

Repeat Detail A

I/O120–I/O127

Block P

I/O112–I/O119

Block O I/O128–I/O135

Block AX I/O136–I/O143

Block BX

4 4

17466G-068

MACH 4 Family 38

ABSOLUTE MAXIMUM RATINGS

M4 and M4A5

Storage Temperature. . . . . . . . . . . . . .-65°C to +150°C

Ambient Temperature

with Power Applied . . . . . . . . . . . . . . -55°C to +100°C

Device Junction Temperature . . . . . . . . . . . . . +130°C

Supply Voltage

with Respect to Ground . . . . . . . . . . .-0.5 V to +7.0 V

DC Input Voltage . . . . . . . . . . . . -0.5 V to VCC + 0.5 V

Static Discharge Voltage . . . . . . . . . . . . . . . . . 2000 V

Latchup Current (TA = -40°C to +85°C). . . . . . . 200 mA

Stresses above those listed under Absolute Maximum

Ratings may cause permanent device failur e. Functionality at

or above these limits is not implied. Exposure to Absolute

Maximum Ratings for extended periods may affect device

reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (TA)

Operating in Free Air. . . . . . . . . . . . . . . 0°C to +70°C

Supply Voltage (VCC)

with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V

Industrial (I) Devices

Ambient Temperature (TA)

Operating in Free Air. . . . . . . . . . . . . . -40°C to +85°C

Supply Voltage (VCC)

with Respect to Ground . . . . . . . . . . +4.50 V to +5.5 V

Operating ranges deﬁne those limits between which the func-

tionality of the device is guaranteed.

Notes:

1. Total IOL for one PAL block should not exceed 64 mA.

2. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.

3. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).

4. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.

VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.

5-V DC CHARACTERISTICS OVER OPERATING RANGES

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

VOH Output HIGH Voltage IOH = –3.2 mA, VCC = Min, VIN = VIH or VIL 2.4 V

IOH = 0 mA, VCC = Max, VIN = VIH or VIL 3.3 V

VOL Output LOW Voltage IOL = 24 mA, VCC = Min, VIN = VIH or VIL (Note 1) 0.5 V

VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs

(Note 2) 2.0 V

VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs

(Note 2) 0.8 V

IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 3) 10 µA

IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 3) –10 µA

IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max, VIN = VIH or VIL (Note 3) 10 µA

IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max , VIN = VIH or VIL (Note 3) –10 µA

ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 4) –30 –160 mA

39 MACH 4 Family

ABSOLUTE MAXIMUM RATINGS

M4LV and M4A3

Storage Temperature. . . . . . . . . . . . . .-65°C to +150°C

Ambient Temperature

with Power Applied . . . . . . . . . . . . . . -55°C to +100°C

Device Junction Temperature . . . . . . . . . . . . . +130°C

Supply Voltage

with Respect to Ground . . . . . . . . . . .-0.5 V to +4.5 V

DC Input Voltage . . . . . . . . . . . . . . . . .-0.5 V to 6.0 V

Static Discharge Voltage . . . . . . . . . . . . . . . . . 2000 V

Latchup Current (TA = -40°C to +85°C). . . . . . . 200 mA

Stresses above those listed under Absolute Maximum

Ratings may cause permanent device failur e. Functionality at

or above these limits is not implied. Exposure to Absolute

Maximum Ratings for extended periods may affect device

reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (TA)

Operating in Free Air. . . . . . . . . . . . . . . 0°C to +70°C

Supply Voltage (VCC)

with Respect to Ground . . . . . . . . . . . +3.0 V to +3.6 V

Industrial (I) Devices

Ambient Temperature (TA)

Operating in Free Air. . . . . . . . . . . . . . -40°C to +85°C

Supply Voltage (VCC)

with Respect to Ground . . . . . . . . . . . +3.0 V to +3.6 V

Operating ranges deﬁne those limits between which the func-

tionality of the device is guaranteed.

Notes:

1. Total IOL for one PAL block should not exceed 64 mA.

2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).

3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.

3.3-V DC CHARACTERISTICS OVER OPERATING RANGES

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

VOH Output HIGH Voltage VCC = Min

VIN = VIH or VIL

IOH = –100 µAV

CC – 0.2 V

IOH = –3.2 mA 2.4 V

VOL Output LOW Voltage VCC = Min

VIN = VIH or VIL

(Note 1)

IOL = 100 µA 0.2 V

IOL = 24 mA 0.5 V

VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all

Inputs 2.0 5.5 V

VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all

Inputs –0.3 0.8 V

IIH Input HIGH Leakage Current VIN = 3.6 V, VCC = Max (Note 2) 5 µA

IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) –5 µA

IOZH Off-State Output Leakage Current HIGH VOUT = 3.6 V, VCC = Max

VIN = VIH or VIL (Note 2) 5µA

IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max

VIN = VIH or VIL (Note 2) –5 µA

ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –15 –160 mA

MACH 4 Family 40

MACH 4 TIMING PARAMETERS OVER OPERATING RANGES1

-7 -10 -12 -14 -15 -18

UnitMin Max Min Max Min Max Min Max Min Max Min Max

Combinatorial Delay:

tPDi Internal combinatorial propagation delay 5.5 8.0 10.0 12.0 13.0 16.0 ns

tPD Combinatorial propagation delay 7.5 10.0 12.0 14.0 15.0 18.0 ns

Registered Delays:

tSS Synchronous clock setup time, D-type register 5.5 6.0 7.0 10.0 10.0 12.0 ns

tSST Synchronous clock setup time, T-type register 6.5 7.0 8.0 11.0 11.0 13.0 ns

tSA Asynchronous clock setup time, D-type register 3.5 4.0 5.0 8.0 8.0 10.0 ns

tSAT Asynchronous clock setup time, T-type register 4.5 5.0 6.0 9.0 9.0 11.0 ns

tHS Synchronous clock hold time 0.0 0.0 0.0 0.0 0.0 0.0 ns

tHA Asynchronous clock hold time 3.5 4.0 5.0 8.0 8.0 10.0 ns

tCOSi Synchronous clock to internal output 3.5 4.5 6.0 8.0 8.0 10.0 ns

tCOS Synchronous clock to output 5.5 6.5 8.0 10.0 10.0 12.0 ns

tCOAi Asynchronous clock to internal output 7.5 10.0 12.0 16.0 16.0 18.0 ns

tCOA Asynchronous clock to output 9.5 12.0 14.0 18.0 18.0 20.0 ns

Latched Delays:

tSSL Synchronous Latch setup time 6.0 7.0 8.0 10.0 10.0 12.0 ns

tSAL Asynchronous Latch setup time 4.0 4.0 5.0 8.0 8.0 10.0 ns

tHSL Synchronous Latch hold time 0.0 0.0 0.0 0.0 0.0 0.0 ns

tHAL Asynchronous Latch hold time 4.0 4.0 5.0 8.0 8.0 10.0 ns

tPDLi Transparent latch to internal output 8.0 10.0 12.0 15.0 15.0 18.0 ns

tPDL Propagation delay through transparent latch to output 10.0 12.0 14.0 17.0 17.0 20.0 ns

tGOSi Synchronous Gate to internal output 4.0 5.5 8.0 9.0 9.0 10.0 ns

tGOS Synchronous Gate to output 6.0 7.5 10.0 11.0 11.0 12.0 ns

tGOAi Asynchronous Gate to internal output 9.0 11.0 14.0 17.0 17.0 20.0 ns

tGOA Asynchronous Gate to output 11.0 13.0 16.0 19.0 19.0 22.0 ns

Input Register Delays:

tSIRS Input register setup time 2.0 2.0 2.0 2.0 2.0 2.0 ns

tHIRS Input register hold time 3.0 3.0 3.0 4.0 4.0 4.0 ns

tICOSi Input register clock to internal feedback 3.5 4.5 6.0 6.0 6.0 6.0 ns

Input Latch Delays:

tSIL Input latch setup time 2.0 2.0 2.0 2.0 2.0 2.0 ns

tHIL Input latch hold time 3.0 3.0 3.0 4.0 4.0 4.0 ns

tIGOSi Input latch gate to internal feedback 4.0 4.0 4.0 5.0 5.0 6.0 ns

tPDILi Transparent input latch to internal feedback 2.0 2.0 2.0 2.0 2.0 2.0 ns

Input Register Delays with ZHT Option:

tSIRZ Input register setup time - ZHT 6.0 6.0 6.0 6.0 6.0 6.0 ns

tHIRZ Input register hold time - ZHT 0.0 0.0 0.0 0.0 0.0 0.0 ns

41 MACH 4 Family

Input Latch Delays with ZHT Option:

tSILZ Input latch setup time - ZHT 6.0 6.0 6.0 6.0 6.0 6.0 ns

tHILZ Input latch hold time - ZHT 0.0 0.0 0.0 0.0 0.0 0.0 ns

tPDILZi Transparent input latch to internal feedback - ZHT 6.0 6.0 6.0 6.0 6.0 6.0 ns

Output Delays:

tBUF Output buffer delay 2.0 2.0 2.0 2.0 2.0 2.0 ns

tSLW Slow slew rate delay adder 2.5 2.5 2.5 2.5 2.5 2.5 ns

tEA Output enable time 9.5 10.0 12.0 15.0 15.0 17.0 ns

tER Output disable time 9.5 10.0 12.0 15.0 15.0 17.0 ns

Power Delay:

tPL Power-down mode delay adder 2.5 2.5 2.5 2.5 2.5 2.5 ns

Reset and Preset Delays:

tSRi Asynchronous reset or preset to internal register output 10.0 12.0 14.0 18.0 18.0 20.0 ns

tSR Asynchronous reset or preset to register output 12.0 14.0 16.0 20.0 20.0 22.0 ns

tSRR Asynchronous reset and preset register recovery time 8.0 8.0 10.0 15.0 15.0 17.0 ns

tSRW Asynchronous reset or preset width 10.0 10.0 12.0 15.0 15.0 17.0 ns

Clock/LE Width:

tWLS Global clock width low 3.0 5.0 6.0 6.0 6.0 7.0 ns

tWHS Global clock width high 3.0 5.0 6.0 6.0 6.0 7.0 ns

tWLA Product term clock width low 4.0 5.0 8.0 9.0 9.0 10.0 ns

tWHA Product term clock width high 4.0 5.0 8.0 9.0 9.0 10.0 ns

tGWS Global gate width low (for low transparent) or high

(for high transparent) 5.0 5.0 6.0 6.0 6.0 7.0 ns

tGWA Product term gate width low (for low transparent) or

high (for high transparent) 4.0 5.0 6.0 9.0 9.0 11.0 ns

tWIRL Input register clock width low 4.5 5.0 6.0 6.0 6.0 7.0 ns

tWIRH Input register clock width high 4.5 5.0 6.0 6.0 6.0 7.0 ns

tWIL Input latch gate width 5.0 5.0 6.0 6.0 6.0 7.0 ns

MACH 4 TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)

-7 -10 -12 -14 -15 -18

UnitMin Max Min Max Min Max Min Max Min Max Min Max

MACH 4 Family 42

Notes:

1. See “Switching Test Circuit” in the General Information Section of the Vantis 1999 Data Book.

2. This parameter does not apply to ﬂip-ﬂops in the emulated mode since the feedback path is required for emulation.

Frequency:

fMAXS

External feedback, D-type, Min of 1/(tWLS + tWHS) or

1/(tSS + tCOS)90.9 80.0 66.7 50.0 50.0 41.7 MHz

External feedback, T-type, Min of 1/(tWLS + tWHS) or

1/(tSST + tCOS)83.3 74.1 62.5 47.6 47.6 40.0 MHz

Internal feedback (fCNT), D-type,

Min of 1/(tWLS + tWHS) or 1/(tSS + tCOSi)111.1 95.2 76.9 55.6 55.6 45.5 MHz

Internal feedback (fCNT), T-type,

Min of 1/(tWLS + tWHS) or 1/(tSST + tCOSi)100.0 87.0 71.4 52.6 52.6 43.5 MHz

No feedback2, Min of 1/(tWLS + tWHS), 1/(tSS + tHS) or

1/(tSST + tHS)153.8 100.0 83.3 83.3 83.3 71.4 MHz

fMAXA

External feedback, D-type, Min of 1/(tWLA + tWHA) or

1/(tSA + tCOA)76.9 62.5 52.6 38.5 38.5 33.3 MHz

External feedback, T-type, Min of 1/(tWLA + tWHA) or

1/(tSAT + tCOA)71.4 58.8 50.0 37.0 37.0 32.3 MHz

Internal feedback (fCNTA), D-type,

Min of 1/(tWLA + tWHA) or 1/(tSA + tCOAi)90.9 71.4 58.8 41.7 41.7 35.7 MHz

Internal feedback (fCNTA), T-type,

Min of 1/(tWLA + tWHA) or 1/(tSAT + tCOAi)83.3 66.7 55.6 40.0 40.0 34.5 MHz

No feedback2, Min of 1/(tWLA + tWHA),

1/(tSA + tHA) or 1/(tSAT + tHA)125.0 100.0 62.5 55.6 55.6 50.0 MHz

fMAXI Maximum input register frequency,

Min of 1/(tWIRH + tWIRL) or 1/(tSIRS + tHIRS)111.0 100.0 83.3 83.3 83.3 71.4 MHz

MACH 4 TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)

-7 -10 -12 -14 -15 -18

UnitMin Max Min Max Min Max Min Max Min Max Min Max

MACH 4A TIMING PARAMETERS OVER OPERATING RANGES1

-5 -55 -6 -65 -7 -10 -12 -14

UnitMin Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max

Combinatorial Delay:

tPDi Internal combinatorial

propagation delay 3.5 4.0 4.0 4.5 5.0 7.0 9.0 11.0 ns

tPD Combinatorial propagation

delay 5.0 5.5 6.0 6.5 7.5 10.0 12.0 14.0 ns

Registered Delays:

tSS Synchronous clock setup

time, D-type register 3.0 3.5 4.0 4.0 5.5 6.0 7.0 10.0 ns

tSST Synchronous clock setup

time, T-type register 4.0 4.0 4.5 4.5 6.5 7.0 8.0 11.0 ns

tSA Asynchronous clock setup

time, D-type register 2.5 2.5 3.0 3.0 3.5 4.0 5.0 8.0 ns

tSAT Asynchronous clock setup

time, T-type register 3.0 3.0 3.5 3.5 4.5 5.0 6.0 9.0 ns

tHS Synchronous clock hold

time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns

MACH 4 Family 43

tHA Asynchronous clock hold

time 2.5 2.5 3.0 3.0 3.5 4.0 5.0 8.0 ns

tCOSi Synchronous clock to

internal output 2.5 2.5 2.5 2.5 2.5 2.5 3.5 3.5 ns

tCOS Synchronous clock to

output 4.0 4.0 4.5 4.5 5.0 5.5 6.5 6.5 ns

tCOAi Asynchronous clock to

internal output 5.0 5.0 5.0 5.0 6.0 8.0 10.0 12.0 ns

tCOA Asynchronous clock to

output 6.5 6.5 7.0 7.0 8.5 11.0 13.0 15.0 ns

Latched Delays:

tSSL Synchronous latch setup

time 4.0 4.0 4.5 4.5 6.0 7.0 8.0 10.0 ns

tSAL Asynchronous latch setup

time 3.0 3.0 3.5 3.5 4.0 4.0 5.0 8.0 ns

tHSL Synchronous latch hold

time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns

tHAL Asynchronous latch hold

time 3.0 3.0 3.5 3.5 4.0 4.0 5.0 8.0 ns

tPDLi Transparent latch to

internal output 5.5 5.5 6.0 6.0 7.5 9.0 11.0 12.0 ns

tPDL Propagation delay through

transparent latch to output 7.0 7.0 8.0 8.0 10.0 12.0 14.0 15.0 ns

tGOSi Synchronous gate to

internal output 3.0 3.0 3.0 3.0 3.5 4.5 7.0 8.0 ns

tGOS Synchronous gate to output 4.5 4.5 5.0 5.0 6.0 7.5 10.0 11.0 ns

tGOAi Asynchronous gate to

internal output 6.0 6.0 6.0 6.0 8.5 10.0 13.0 15.0 ns

tGOA Asynchronous gate to

output 7.5 7.5 8.0 8.0 11.0 13.0 16.0 18.0 ns

Input Register Delays:

tSIRS Input register setup time 1.5 1.5 2.0 2.0 2.0 2.0 2.0 2.0 ns

tHIRS Input register hold time 2.5 2.5 3.0 3.0 3.0 3.0 3.0 4.0 ns

tICOSi Input register clock to

internal feedback 3.0 3.0 3.0 3.0 3.5 4.5 6.0 6.0 ns

Input Latch Delays:

tSIL Input latch setup time 1.5 1.5 2.0 2.0 2.0 2.0 2.0 2.0 ns

tHIL Input latch hold time 2.5 2.5 3.0 3.0 3.0 3.0 3.0 4.0 ns

tIGOSi Input latch gate to internal

feedback 3.5 3.5 4.0 4.0 4.0 4.0 4.0 5.0 ns

tPDILi Transparent input latch to

internal feedback 1.5 1.5 1.5 1.5 2.0 2.0 2.0 2.0 ns

MACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)

-5 -55 -6 -65 -7 -10 -12 -14

UnitMin Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max

44 MACH 4 Family

Input Register Delays with ZHT Option:

tSIRZ Input register setup time -

ZHT 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 ns

tHIRZ Input register hold time -

ZHT 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns

Input Latch Delays with ZHT Option:

tSILZ Input latch setup time -

ZHT 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 ns

tHILZ Input latch hold time - ZHT 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns

tPDILZi Transparent input latch to

internal feedback - ZHT 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 ns

Output Delays:

tBUF Output buffer delay 1.5 1.5 2.0 2.0 2.5 3.0 3.0 3.0 ns

tSLW Slow slew rate delay adder 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns

tEA Output enable time 7.5 7.5 8.5 8.5 9.5 10.0 12.0 15.0 ns

tER Output disable time 7.5 7.5 8.5 8.5 9.5 10.0 12.0 15.0 ns

Power Delay:

tPL Power-down mode delay

adder 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns

Reset and Preset Delays:

tSRi

Asynchronous reset or

preset to internal register

output 7.5 7.7 8.0 8.0 9.5 11.0 13.0 16.0 ns

tSR Asynchronous reset or

preset to register output 9.0 9.2 10.0 10.0 12.0 14.0 16.0 19.0 ns

tSRR

Asynchronous reset and

preset register recovery

time 7.0 7.0 7.5 7.5 8.0 8.0 10.0 15.0 ns

tSRW Asynchronous reset or

preset width 7.0 7.0 8.0 8.0 10.0 10.0 12.0 15.0 ns

Clock/LE Width:

tWLS Global clock width low 2.0 2.0 2.5 2.5 3.0 5.0 6.0 6.0 ns

tWHS Global clock width high 2.0 2.0 2.5 2.5 3.0 5.0 6.0 6.0 ns

tWLA Product term clock width

low 3.0 3.0 3.5 3.5 4.0 5.0 8.0 9.0 ns

tWHA Product term clock width

high 3.0 3.0 3.5 3.5 4.0 5.0 8.0 9.0 ns

tGWS

Global gate width low (for

low transparent) or high

(for high transparent) 4.0 4.0 4.5 4.5 5.0 5.0 6.0 6.0 ns

tGWA

Product term gate width

low (for low transparent)

or high (for high

transparent)

4.0 4.0 4.5 4.5 5.0 5.0 6.0 9.0 ns

tWIRL Input register clock width

low 3.0 3.0 3.5 3.5 4.0 5.0 6.0 6.0 ns

MACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)

-5 -55 -6 -65 -7 -10 -12 -14

UnitMin Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max

MACH 4 Family 45

Notes:

1. See “Switching Test Circuit” in the General Information Section of the Vantis 1999 Data Book.

2. This parameter does not apply to ﬂip-ﬂops in the emulated mode since the feedback path is required for emulation.

tWIRH Input register clock width

high 3.0 3.0 3.5 3.5 4.0 5.0 6.0 6.0 ns

tWIL Input latch gate width 4.0 4.0 4.5 4.5 5.0 5.0 6.0 6.0 ns

Frequency:

fMAXS

External feedback, D-type,

Min of 1/(tWLS + tWHS) or

1/(tSS + tCOS)143 133 118 118 95.2 87.0 74.1 60.6 MHz

External feedback, T-type,

Min of 1/(tWLS + tWHS) or

1/(tSST + tCOS)125 125 111 111 87.0 80.0 69.0 57.1 MHz

Internal feedback (fCNT),

D-type, Min of 1/(tWLS +

tWHS) or 1/(tSS + tCOSi)182 167 154 154 125 100 83.3 74.1 MHz

Internal feedback (fCNT),

T-type, Min of 1/(tWLS +

tWHS) or 1/(tSST + tCOSi)154 154 143 143 111 105 87.0 69.0 MHz

No feedback2, Min of 1/

(tWLS + tWHS), 1/(tSS + tHS)

or 1/(tSST + tHS)250 250 200 200 154 125 100 83.3 MHz

fMAXA

External feedback, D-type,

Min of 1/(tWLA + tWHA) or

1/(tSA + tCOA)111 111 100 100 83.3 66.7 55.6 43.5 MHz

External feedback, T-type,

Min of 1/(tWLA + tWHA) or

1/(tSAT + tCOA)105 105 95.2 95.2 76.9 62.5 52.6 41.7 MHz

Internal feedback (fCNTA),

D-type, Min of 1/(tWLA +

tWHA) or 1/(tSA + tCOAi)133 133 125 125 105 83.3 66.7 50.0 MHz

Internal feedback (fCNTA),

T-type, Min of 1/(tWLA +

tWHA) or 1/(tSAT + tCOAi)125 125 118 118 95.2 76.9 62.5 47.6 MHz

No feedback2, Min of 1/

(tWLA + tWHA), 1/(tSA +

tHA) or 1/(tSAT + tHA)167 167 143 143 125 100 62.5 55.6 MHz

fMAXI

Maximum input register

frequency , Min of 1/(tWIRH

+ tWIRL) or 1/(tSIRS +

tHIRS)

167 167 143 143 125 100 83.3 83.3 MHz

MACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)

-5 -55 -6 -65 -7 -10 -12 -14

UnitMin Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max

46 MACH 4 Family

CAPACITANCE 1

Note:

1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modiﬁed

where this parameter may be affected.

ICC vs. FREQUENCY

These curves represent the typical power consumption for a particular device at system

frequency. The selected “typical” pattern is a 16-bit up-down counter. This pattern ﬁlls the

device and exercises every macrocell. Maximum frequency shown uses internal feedback and

a D-type register. Power/Speed are optimized to obtain the highest counter frequency and the

lowest power. The highest frequency (LSBs) is placed in common PAL blocks, which are set to

high power . The lowest frequency signals (MSBs) are placed in a common PAL block and set to

lowest power.

Parameter Symbol Parameter Description Test Conditions Typ Unit

CIN Input capacitance VIN=2.0 V 3.3 V or 5 V, 25°C, 1 MHz 6 pF

CI/O Output capacitance VOUT=2.0V 3.3 V or 5 V, 25°C, 1 MHz 8 pF

350

300

250

200

150

100

110

120

130

VCC = 5 V or 3.3 V, TA = 25 °C

ICC (mA)

Frequency (MHz) 17466G-066

M4(LV)-32/32

M4(LV)-64/32

M4(LV)-96/48

M4(LV)-128/64

M4(LV)-192/96

M4(LV)-256/128

Figure 19. ICC Curves at High Power Mode

17466G-044

MACH 4 Family 47

350

300

250

200

150

100

110

120

VCC = 5 V or 3.3 V, TA = 25 °C

M4(LV)-32/32

ICC (mA)

Frequency (MHz) 17466G-065

M4(LV)-64/32

M4(LV)-96/48

M4(LV)-128/64

M4(LV)-192/96

M4(LV)-256/128

Figure 20. ICC Curves at Low Power Mode

Figure 21. MACH 4A Device Dynamic Icc Curves at High and Low Power Modes

300

250

200

150

100

0 20 40 60 80 100 120 140 160 180 200

M4A3-256/128 (HP)

M4A3-256/128 (LP)

M4A3-128/64 (HP)

M4A3-128/64 (LP)

M4A3-32/32 (HP)

M4A3-32/32 (LP)

220 240 260

Frequency (MHz)

VCC = 3.3V, TA = 25°C

Icc (mA)

HP: High Power

LP: Low Power

17466H-066

48 MACH 4 Family

44-PIN PLCC CONNECTION DIAGRAM (M4(LV)-32/32, M4A(3,5)-32/32,

M4(LV)-64/32 AND M4A(3,5)-64/32)

Top View

44-Pin PLCC

PIN DESIGNATIONS

CLK/I = Clock or Input

GND = Ground

I/O = Input/Output

VCC = Supply Voltage

TDI = Test Data In

TCK = Test Clock

TMS = Test Mode Select

TDO = Test Data Out

144 43 42

5432

641

17 23 24 25 26

19 20 21 22

18 27 28

I/O5

I/O6

I/O7

TDI

CLK0/I0

GND

TCK

I/O8

I/O9

I/O10

I/O11

B10

A10

A11

I/O27

I/O26

I/O25

I/O24

TDO

GND

CLK1/I1

TMS

I/O23

I/O22

I/O21

I/O12

I/O13

I/O14

I/O15

VCC

GND

I/O16

I/O17

I/O18

I/O19

I/O20

A12

A13

A14

A15

B15

B14

B13

B12

B11

I/O4

I/O3

I/O2

I/O1

I/O0

GND

VCC

I/O31

I/O30

I/O29

I/O28

M4(LV)-32/32

M4A(3,5)-32/32

M4(LV)-32/32

M4A(3,5)-32/32

M4(LV)-64/32

M4A(3,5)-64/32

M4(LV)-64/32

M4A(3,5)-64/32

M4(LV)-64/32

M4A(3,5)-64/32

M4(LV)-64/32

M4A(3,5)-64/32

17466G-026

I/O Cell (0-7)

PAL Block (A-D)

MACH 4 Family 49

44-PIN TQFP CONNECTION DIAGRAM (M4(LV)-32/32, M4A(3,5)-32/32,

M4(LV)-64/32 AND M4A(3,5)-64/32)

Top View

44-Pin TQFP

PIN DESIGNATIONS

CLK/I = Clock or Input

GND = Ground

I/O = Input/Output

VCC = Supply Voltage

TDI = Test Data In

TCK = Test Clock

TMS = Test Mode Select

TDO = Test Data Out

I/O12

I/O13

I/O14

I/O15

VCC

GND

I/O16

I/O17

I/O18

I/O19

I/O20

A12

A13

A14

A15

B15

B14

B13

B12

B11

I/O4

I/O3

I/O2

I/O1

I/O0

GND

VCC

I/O31

I/O30

I/O29

I/O28

I/O27

I/O26

I/O25

I/O24

TDO

GND

CLK1/I1

TMS

I/O23

I/O22

I/O21

B10

I/O5

I/O6

I/O7

TDI

CLK0/I0

GND

TCK

I/O8

I/O9

I/O10

I/O11

A10

A11

M4(LV)-32/32

M4A(3,5)-32/32

M4(LV)-32/32

M4A(3,5)-32/32

M4(LV)-64/32

M4A(3,5)-64/32

M4(LV)-64/32

M4A(3,5)-64/32

M4(LV)-64/32

M4A(3,5)-64/32

M4(LV)-64/32

M4A(3,5)-64/32

I/O Cell (0-7)

PAL Block (A-D)

50 MACH 4 Family

48-PIN TQFP CONNECTION DIAGRAM (M4(LV)-32/32, M4A(3,5)-32/32,

M4(LV)-64/32 AND M4A(3,5)-64/32)

Top View

48-Pin TQFP

PIN DESIGNATIONS

CLK/I = Clock or Input

GND = Ground

I/O = Input/Output

VCC = Supply Voltage

NC = No Connect

TDI = Test Data In

TCK = Test Clock

TMS = Test Mode Select

TDO = Test Data Out

I/O12

I/O13

I/O14

I/O15

VCC

GND

I/O16

I/O17

I/O18

I/O19

I/O20

A12

A13

A14

A15

B15

B14

B13

B12

B11

I/O4

I/O3

I/O2

I/O1

I/O0

GND

VCC

I/O31

I/O30

I/O29

I/O28

I/O27

I/O26

I/O25

I/O24

TDO

GND

CLK1/I1

TMS

I/O23

I/O22

I/O21

B10

I/O5

I/O6

I/O7

TDI

CLK0/I0

GND

TCK

I/O8

I/O9

I/O10

I/O11

A10

A11

M4(LV)-32/32

M4A(3,5)-32/32

M4(LV)-32/32

M4A(3,5)-32/32

M4(LV)-64/32

M4A(3,5)-64/32

M4(LV)-64/32

M4A(3,5)-64/32

M4(LV)-64/32

M4A(3,5)-64/32

M4(LV)-64/32

M4A(3,5)-64/32

17466G-028

I/O Cell (0-7)

PAL Block (A-D)

MACH 4 Family 51

100-PIN TQFP CONNECTION DIAGRAM (M4(LV)-96/48 AND M4A(3,5)-96/48)

Top View

100-Pin TQFP

PIN DESIGNATIONS

CLK/I = Clock or Input

GND = Ground

I = Input

I/O = Input/Output

VCC = Supply Voltage

NC = No Connect

TDI = Test Data In

TCK = Test Clock

TMS = Test Mode Select

TDO = Test Data Out

TDI

I/O6

I/O7

I/O8

I/O9

I/O10

I/O11

I0/CLK0

GND

I1/CLK1

I/O12

I/O13

I/O14

I/O15

I/O16

I/O17

TMS

TCK

GND

I/O18

I/O19

I/O20

I/O21

I/O22

I/O23

GND

I/O24

I/O25

I/O26

I/O27

I/O28

I/O29

GND

100

GND

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

GND

I/O47

I/O46

I/O45

I/O44

I/O43

I/O42

GND

TDO

I/O41

I/O40

I/O39

I/O38

I/O37

I/O36

I5/CLK3

GND

I4/CLK2

I/O35

I/O34

I/O33

I/O32

I/O31

I/O30

17466G-029

I/O Cell (0-7)

PAL Block (A-F)

52 MACH 4 Family

84-PIN PLCC CONNECTION DIAGRAM (M4(LV)-128N/64)

Top View

84-Pin PLCC

Note:

Pin-compatible with the MACH131, MACH231, MACH435.

PIN DESIGNATIONS

CLK/I = Clock or Input

GND = Ground

I = Input

I/O = Input/Output

VCC = Supply Voltage

381

580 76

79 75

40 47

34 39

33 48 52

32 53

I/O9

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

CLK0/I0

VCC

GND

CLK1/I1

I/O16

I/O17

I/O18

I/O19

I/O20

I/O21

I/O22

I/O23

GND

I/O8 GND

I/O55

I/O54

I/O53

I/O52

I/O51

I/O50

I/O49

I/O48

CLK3/I4

VCC

CLK2/I3

I/O47

I/O46

I/O45

I/O44

I/O43

I/O42

I/O41

GND

I/O40

GND

VCC

I/O0

I/O62

I/O63

VCC

I/O3

I/O4

I/O5

I/O6

I/O1

I/O2

I/O61

I/O57

I/O58

I/O59

I/O60

I/O56

I/O7

GND

VCC

I/O34

I/O33

I/O32

VCC

I/O29

I/O28

I/O27

I/O26

I/O31

I/O30

I/O35

I/O39

I/O38

I/O37

I/O36

GND

I/O25

I/O24

17466G-030

I/O Cell (0-7)

PAL Block (A-H)

MACH 4 Family 53

100-PIN PQFP CONNECTION DIAGRAM (M4(LV)-128/64 AND M4A(3,5)-128/64)

Top View

100-Pin PQFP

Note:

The numbers in parentheses reﬂect compatible pin numbers for 84-pin PLCC.

PIN DESIGNATIONS

I/CLK = Input or Clock

GND = Ground

I = Input

I/O = Input/Output

VCC = Supply Voltage

TDI = Test Data In

TCK = Test Clock

TMS = Test Mode Select

TDO = Test Data Out

TRST = Test Reset

ENABLE = Program

I/O7 A7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

VCC

GND

VCC

I/O63

I/O62

I/O61

I/O60

I/O59

I/O58

I/O57

I/O56

GND

TDI

I/O8

I/O9

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

IO/CLK0

GND

I1/CLK1

I/O16

I/O17

I/O18

I/O19

I/O20

I/O21

I/O22

I/O23

C7 TMS

TCK

GND

100

I/O46

I/O45

I/O44

I/O43

I/O42

I/O41

I/O40

ENABLE

GND

TD0

TRST

I/O55

I/O54

I/O53

I/O52

I/O51

I/O50

I/O49

I/O48

I4/CLK3

GND

I3/CLK2

I/O47 F1

GND

I/O24

I/O25

I/O26

I/O27

I/O28

I/O29

I/O30

I/O31

GND

I/O32

I/O33

I/O34

I/O35

I/O36

I/O37

I/O38

I/O39

(83)

(12)

(13)

(14)

(15)

(16)

(17)

(18)

(19)

(20)

(23)

(24)

(25)

(26)

(27)

(28)

(29)

(30)

(31)

(33)

(34)

(35)

(36)

(37)

(38)

(39)

(40)

(45)

(46)

(47)

(48)

(49)

(50)

(51)

(52)

(62)

(61)

(60)

(59)

(58)

(57)

(56)

(55)

(54)

(41)

(73)

(72)

(71)

(70)

(69)

(68)

(67)

(66)

(65)

(10)

(9)

(8)

(7)

(6)

(5)

(4)

(3)

(82)

(81)

(80)

(79)

(78)

(77)

(76)

(75)

VCC

VCC VCC

VCC

17466G

031

I/O Cell (0-7)

PAL Block (A-H)

54 MACH 4 Family

100-PIN TQFP CONNECTION DIAGRAM (M4(LV)-128/64 AND M4A(3,5)-128/64)

Top View

100-Pin TQFP

PIN DESIGNATIONS

CLK/I = Clock or Input

GND = Ground

I = Input

I/O = Input/Output

VCC = Supply Voltage

TDI = Test Data In

TCK = Test Clock

TMS = Test Mode Select

TDO = Test Data Out

TRST = Test Reset

ENABLE = Program

GND

TDI

I/O8

I/O9

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

I0/CLK0

VCC

GND

I1/CLK1

I/O16

I/O17

I/O18

I/O19

I/O20

I/O21

I/O22

I/O23

TMS

TCK

GND

I/O24

I/O25

I/O26

I/O27

I/O28

I/O29

I/O30

I/O31

GND

I/O32

I/O33

I/O34

I/O35

I/O36

I/O37

I/O38

I/O39

GND

100

GND

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

VCC

GND

VCC

I/O63

I/O62

I/O61

I/O60

I/O59

I/O58

I/O57

I/O56

GND

TDO

TRST

I/O55

I/O54

I/O53

I/O52

I/O51

I/O50

I/O49

I/O48

I4/CLK3

GND

VCC

I3/CLK2

I/O47

I/O46

I/O45

I/O44

I/O43

I/O42

I/O41

I/O40

ENABLE

GND

17466G-032

I/O Cell (0-7)

PAL Block (A-H)

MACH 4 Family 55

144-PIN TQFP CONNECTION DIAGRAM (M4(LV)-192/96 AND M4A(3,5)-192/96)

Top View

144-Pin TQFP

PIN DESIGNATIONS

CLK = Clock

GND = Ground

I = Input

I/O = Input/Output

VCC = Supply Voltage

TDI = Test Data In

TCK = Test Clock

TMS = Test Mode Select

TDO = Test Data Out

17466G-033

GND

TDI

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

VCC

GND

I/O8

I/O9

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

GND

VCC

I/O16

I/O17

I/O18

I/O19

I/O20

I/O21

I/O22

I/O23

TMS

TCK

GND

I/O24

I/O25

I/O26

I/O27

I/O28

I/O29

I/O30

I/O31

CLK1

GND

VCC

CLK2

I/O32

I/O33

I/O34

I/O35

I/O36

I/O37

I/O38

I/O39

VCC

GND

I/O40

I/O41

I/O42

I/O43

I/O44

I/O45

I/O46

I/O47

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

I/O95

I/O94

I/O93

I/O92

I/O91

I/O90

I/O89

I/O88

GND

VCC

I/O87

I/O86

I/O85

I/O84

I/O83

I/O82

I/O81

I/O80

CLK0

GND

VCC

CLK3

I15

I14

I13

I/O79

I/O78

I/O77

I/O76

I/O75

I/O74

I/O73

I/O72

GND

108

107

106

105

104

103

102

101

100

GND

TDO

I/O71

I/O70

I/O69

I/O68

I/O67

I/O66

I/O65

I/O64

I12

VCC

GND

I11

I10

I/O63

I/O62

I/O61

I/O60

I/O59

I/O58

I/O57

I/O56

GND

VCC

I/O55

I/O54

I/O53

I/O52

I/O51

I/O50

I/O49

I/O48

GND

I/O Cell (0-7)

PAL Block (A-L)

56 MACH 4 Family

176-PIN TQFP CONNECTION DIAGRAM - M4A3-256/128, M4A3-192/128,

M4A3-128/128, AND M4A3-384/132

Top View

176-Pin TQFP

GND

TDI

I/O16

I/O17

I/O18

I/O19

I/O20

I/O21

I/O22

I/O23

VCC

GND

I/O24

I/O25

I/O26

I/O27

I/O28

I/O29

I/O30

I/O31

GND

VCC

I/O32

I/O33

I/O34

I/O35

I/O36

I/O37

I/O38

I/O39

I/O40

GND

VCC

I/O41

I/O42

I/O43

I/O44

I/O45

I/O46

I/O47

I/O48

TMS

TCK

GND

I/O49

I/O50

I/O51

I/O52

I/O53

I/O54

I/O55

I/O56

GND

VCC

I/O57

I/O58

I/O59

I/O60

I/O61

I/O62

I/O63

I/O64

I/O66

CLK1

GND

VCC

CLK2

I/O66

I/O67

I/O68

I/O69

I/O70

I/O71

I/O72

I/O73

VCC

GND

I/O74

I/O75

I/O76

I/O77

I/O78

I/O79

I/O80

I/O81

GND

TDI

I/O16

I/O17

I/O18

I/O19

I/O20

I/O21

I/O22

I/O23

VCC

GND

I/O24

I/O25

I/O26

I/O27

I/O28

I/O29

I/O30

I/O31

GND

VCC

I0*(I4)

I/O32

I/O33

I/O34

I/O35

I/O36

I/O37

I/O38

I/O39

GND

VCC

I/O40

I/O41

I/O42

I/O43

I/O44

I/O45

I/O46

I/O47

TMS

TCK

GND

TDI

I/O

VCC

GND

I/O

GND

VCC

I/O

GND

VCC

I/O

TMS

TCK

GND

I/O48

I/O49

I/O50

I/O51

I/O52

I/O53

I/O54

I/O55

GND

VCC

I/O56

I/O57

I/O58

I/O59

I/O60

I/O61

I/O62

I/O63

I1*(I6)

CLK1

GND

VCC

CLK2

I/O64

I/O65

I/O66

I/O67

I/O68

I/O69

I/O70

I/O71

VCC

GND

I/O72

I/O73

I/O74

I/O75

I/O76

I/O77

I/O78

I/O79

GND

I/O

GND

VCC

I/O

CLK1

GND

VCC

CLK2

I/O

VCC

GND

I/O

GND

FX7

FX6

FX5

FX4

FX3

FX2

FX1

FX0

CX7

CX6

CX5

CX4

CX3

CX2

CX1

CX0

DX5

BX0

BX1

BX2

BX3

BX4

BX5

BX6

BX7

HX6

EX0

EX1

EX2

EX3

EX4

EX5

EX6

EX7

GX0

GX1

GX2

GX3

GX4

GX5

GX6

GX7

GND

TDO

TRST

I/O111

I/O110

I/O109

I/O108

I/O107

I/O106

I/O105

I/O104

VCC

GND

I/O103

I/O102

I/O101

I/O100

I/O99

I/O98

I/O97

I/O96

I2*(I1)

VCC

GND

I/O95

I/O94

I/O93

I/O92

I/O91

I/O90

I/O89

I/O88

GND

VCC

I/O87

I/O86

I/O85

I/O84

I/O83

I/O82

I/O81

I/O80

ENABLE

GND

TDO

VCC

I/O

VCC

GND

I/O

VCC

GND

I/O

GND

VCC

I/O

GND

I/O15

I/O14

I/O13

I/O12

I/O11

I/O10

I/O9

I/O8

GND

VCC

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

CLK0

VCC

GND

CLK3

I3*(I3)

I/O127

I/O126

I/O125

I/O124

I/O123

I/O122

I/O121

I/O120

VCC

GND

I/O119

I/O118

I/O117

I/O116

I/O115

I/O114

I/O113

I/O112

GND

I/O

GND

VCC

I/O

CLK0

VCC

GND

CLK3

I/O

VCC

GND

I/O

GND

I/O15

I/O14

I/O13

I/O12

I/O11

I/O10

I/O9

I/O8

GND

VCC

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

CLK0

VCC

GND

CLK3

I/O131

I/O130

I/O129

I/O128

I/O127

I/O126

I/O125

I/O124

I/O123

VCC

GND

I/O122

I/O121

I/O120

I/O119

I/O118

I/O117

I/O116

I/O115

GND

TDO

VCC

I/O114

I/O113

I/O112

I/O111

I/O110

I/O109

I/O108

I/O107

VCC

GND

I/O106

I/O105

I/O104

I/O103

I/O102

I/O101

I/O100

I/O99

I/O98

VCC

GND

I/O97

I/O96

I/O95

I/O94

I/O93

I/O92

I/O91

I/O90

GND

VCC

I/O89

I/O88

I/O87

I/O86

I/O85

I/O84

I/O83

I/O82

GND

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

RECOMMEND TO TIE TO VCC

M4A3-256/128

M4A3-384/132

M4A3-128/128 &

M4A3-192/128

RECOMMEND TO TIE TO GND

PIN DESIGNATIONS

CLK

GND

I/O

N/C

VCC

TDI

TCK

TMS

TDO

TRST

ENABLE

=I/O Cell (0-7)

PAL Block (A-HX)

Clock

Ground

Input ( ) shows equivalent pin in M4A3-256/128 (208PQFP)

Input/Output

No Connect

Supply V oltage

Test Data In

Test Clock

Test Mode Select

Test Data Out

Test Reset

Program

17466G-042

MACH 4 Family 57

208-PIN PQFP CONNECTION DIAGRAM - M4A3-256/128, M4A5-256/128,

M4-256/128, M4LV-256/128, AND M4A3-384/160

Top View

208-Pin PQFP

PIN DESIGNATIONS

CLK

GND

I/O

N/C

VCC

TDI

TCK

TMS

TDO

TRST

ENABLE

=I/O Cell (0-7)

PAL Block (A-HX)

Clock

Ground

Input ( ) shows equivalent pin in M4A3-256/128 (208PQFP)

Input/Output

No Connect

Supply Voltage

Test Data In

Test Clock

Test Mode Select

Test Data Out

Test Reset

Program

17466G-044

58 MACH 4 Family

256-BALL BGA CONNECTION DIAGRAM (M4(LV)-256/128 AND

M4A(3,5)-256/128)

Bottom View

256-Ball BGA

PIN DESIGNATIONS

CLK

GND

I/O

N/C

VCC

TDI

TCK

TMS

TDO

TRST

ENABLE

=I/O Cell (0-7)

PAL Block (A-P)

Clock

Ground

Input

Input/Output

No Connect

Supply Voltage

Test Data In

Test Clock

Test Mode Select

Test Data Out

Test Reset

Program

17466G-045

MACH 4 Family 59

256-BALL BGA CONNECTION DIAGRAM - M4A3-384/192

Bottom View

256-Ball BGA

PIN DESIGNATIONS

CLK

GND

I/O

N/C

VCC

TDI

TCK

TMS

TDO

=I/O Cell (0-7)

PAL Block (A-HX)

Clock

Ground

Input

Input/Output

No Connect

Supply Voltage

Test Data In

Test Clock

Test Mode Select

Test Data Out

17466G-046

60 MACH 4 Family

MACH 4 PRODUCT ORDERING INFORMATION

MACH 4 Devices Commercial & Industrial - 3.3V and 5V

Lattice/Vantis programmable logic products are available with several ordering options. The order number (Valid Combination) is

formed by a combination of:

All MACH devices are dual-marked with both Commercial and

Industrial grades. The Industrial speed grade is slower, i.e.,

M4-256/128-7YC-10YI

Valid Combinations

Valid Combinations list conﬁgurations planned to be

supported in volume for this device. Consult the local

Lattice/Vantis sales ofﬁce to conﬁrm availability of

speciﬁc valid combinations and to check on newly

released combinations.

128

FAMILY TYPE

4- = MACH 4 Family (5-V VCC)

4LV- = MACH 4 Family Low Voltage (3.3-V VCC)

M4- 256 Y C

MACROCELL DENSITY

32 = 32 Macrocells 128N = 128 Macrocells, Non-ISP

64 = 64 Macrocells 192 = 192 Macrocells

96 = 96 Macrocells 256 = 256 Macrocells

128 = 128 Macrocells

I/Os

/32 = 32 I/Os in 44-pin PLCC, 44-pin TQFP or 48-pin TQFP

/48 = 48 I/Os in 100-pin TQFP

/64 = 64 I/Os in 84-pin PLCC, 100-pin PQFP or 100-pin TQFP

/96 = 96 I/Os in 144-pin TQFP

128 = 128 I/Os in 208-pin PQFP or 256-ball BGA

OPERATING CONDITIONS

C = Commercial (0°C to +70°C)

I = Industrial (-40 °C to +85 °C)

PACKAGE TYPE

A = Ball Grid Array (BGA)

J = Plastic Leaded Chip Carrier

(PLCC)

V = Thin Quad Flat Pack (TQFP)

Y = Plastic Quad Flat Pack (PQFP)

SPEED

-7 =7.5 ns tPD

-10 =10 ns tPD

-12 =12 ns tPD

-14 =14 ns tPD

-15 =15 ns tPD

-18 =18 ns tPD

-7

48 = 48-pin TQFP for M4(LV)-32/32

or M4(LV)-64/32

Valid Combinations

M4-32/32

-7, -10, -12, -15

JC, VC, VC48

M4LV-32/32 JC, VC, VC48

M4-64/32 JC, VC, VC48

M4LV-64/32 JC, VC, VC48

M4-96/48 VC

M4LV-96/48 VC

M4-128/64 YC, VC

M4LV-128/64 YC, VC

M4-128N/64 JC

M4LV-128N/64 JC

M4-192/96 VC

M4LV-192/96 VC

M4-256/128 YC, AC

M4LV-256/128 YC, AC

Valid Combinations

M4-32/32

-10, -12, -14, -18

JI, VI, VI48

M4LV-32/32 JI, VI, VI48

M4-64/32 JI, VI, VI48

M4LV-64/32 JI, VI, VI48

M4-96/48 VI

M4LV-96/48 VI

M4-128/64 YI, VI

M4LV-128/64 YI, VI

M4-128N/64 JI

M4LV-128N/64 JI

M4-192/96 VI

M4LV-192/96 VI

M4-256/128 YI, AI

M4LV-256/128 YI, AI

MACH 4 Family 61

MACH 4A PRODUCT ORDERING INFORMATION

MACH 4A Devices Commercial and Industrial - 3.3V and 5V

Lattice/Vantis programmable logic products are available with several ordering options. The order number (Valid Combination) is

formed by a combination of:

128

FAMILY TYPE

4A3- = MACH 4 Family Low Voltage Advanced Feature

(3.3-V VCC)

4A5- = MACH 4 Family Advanced Feature (5-V VCC)

M4A3- 256 Y C

MACROCELL DENSITY

32 = 32 Macrocells 192 = 192 Macrocells

64 = 64 Macrocells 256 = 256 Macrocells

96 = 96 Macrocells 384 = 384 Macrocells

128 = 128 Macrocells 512 = 512 Macrocells

I/Os

/32 = 32 I/Os in 44-pin PLCC, 44-pin TQFP or 48-pin TQFP

/48 = 48 I/Os in 100-pin TQFP

/64 = 64 I/Os in 100-pin TQFP, 100-pin PQFP, or 100-ball fpBGA

/68 = 68 I/Os in 100-pin TQFP or 100-ball fpBGA

/96 = 96 I/Os in 144-pin TQFP or 144-ball fpBGA

/128 = 128 I/Os in 176-pin TQFP , 200-ball fpBGA, 208-pin PQFP, or

256-ball BGA

/132 = 132 I/Os in 176-pin TQFP

/160 = 160 I/Os in 208-pin PQFP

/192 = 192 I/Os in 256-ball BGA or 320-ball fpBGA

/256 = 256 I/Os in 352-ball BGA

OPERATING CONDITIONS

C = Commercial (0°C to +70°C)

I = Industrial (-40 °C to +85 °C)

PACKAGE TYPE

A = Ball Grid Array (BGA)

J = Plastic Leaded Chip Carrier

(PLCC)

V = Thin Quad Flat Pack (TQFP)

Y = Plastic Quad Flat Pack (PQFP)

FA = Fine-pitch Ball Grid Array 0.8mm

(fpBGA)

SPEED

-5 = 5.0 ns tPD

-55 = 5.5 ns tPD

-6 = 6.0 ns tPD

-65 = 6.5 ns tPD

-7 = 7.5 ns tPD

-10 = 10 ns tPD

-12 = 12 ns tPD

-14 = 14 ns tPD

-7

48 = 48-pin TQFP for

M4A3-32/32 or M4A3-64/32

M4A5-32/32 or M4A5-64/32

3.3V Commercial Combinations

M4A3-32/32

-5, -55, -6, -65,

-7, -10, -12

JC, VC, VC48

M4A3-64/32 JC, VC, VC48

M4A3-64/64 VC, FAC

M4A3-96/48 VC

M4A3-128/64 YC, VC, FAC

M4A3-128/96 VC, FAC

M4A3-128/128 VC, FAC

M4A3-192/68 VC, FAC

M4A3-192/96 VC, FAC

M4A3-192/128 VC, FAC

M4A3-256/128 YC, VC, AC, FAC

M4A3-256/160 YC

M4A3-256/192 AC

M4A3-384/132

-65, -7, -10, -12

M4A3-384/160 YC

M4A3-384/192 AC

M4A3-512/132 VC

M4A3-512/160 YC

M4A3-512/192 AC

M4A3-512/256 AC

3.3V Industrial Combinations

M4A3-32/32

-7, -10, -12, -14

JI, VI, VI48

M4A3-64/32 JI, VI, VI48

M4A3-64/64 VI

M4A3-96/48 VI

M4A3-128/64 YI, VI

M4A3-128/96 VI

M4A3-128/128 VI

M4A3-192/68 VI

M4A3-192/96 VI

M4A3-192/128 VI

M4A3-256/128 YI, VI, AI

M4A3-256/160 YI

M4A3-256/192 AI

M4A3-384/132

-10, -12, -14

M4A3-384/160 YI

M4A3-384/192 AI

M4A3-512/132 VI

M4A3-512/160 YI

M4A3-512/192 AI

M4A3-512/256 AI

62 MACH 4 Family

Most MACH devices are dual-marked with both Commercial and Industrial grades. The Industrial speed grade is slower , i.e., M4A3-

256/128-7YC-10YI

Valid Combinations

V alid Combinations list conﬁgurations planned to be supported in volume for this device. Consult the local Lattice/V antis sales ofﬁce

to conﬁrm availability of speciﬁc valid combinations and to check on newly released combinations.

Trademarks

Vantis, the Vantis logo, and combinations thereof, First-Time-Fit, SpeedLocking, Bus-Friendly, DesignDirect, and Lattice/VantisPRO are trademarks,

and MACHPRO, MACHXL, and PAL are registered trademarks of Lattice Semiconductor Corporation.

Other product names used in this publication are for indentiﬁcation purposes only and may be trademarks of their respective companies.

5V Industrial Combinations

M4A5-32/32

-7, -10, -12, -14

JI, VI, VI48

M4A5-64/32 JI, VI, VI48

M4A5-96/48 VI

M4A5-128/64 YI, VI

M4A5-192/96 VI

M4A5-256/128 -10, -12, -14 YI, VI, AI

5V Commercial Combinations

M4A5-32/32

-5, -55, -6, -65,

-7, -10, -12

-65, -7, -10, -12

JC, VC, VC48

M4A5-64/32 JC, VC, VC48

M4A5-96/48 VC

M4A5-128/64 YC, VC

M4A5-192/96 VC

M4A5-256/128 YC, VC, AC