ADVANCE 128Mb MULTIBANK BURST FLASH 32Mb/64Mb ASYNC/PAGE CellularRAM COMBO FLASH AND CellularRAMTM COMBO MEMORY MT28C128532W18/W30D MT28C128564W18/W30D Low Voltage, Wireless Temperature Features Figure 1: 77-Ball FBGA * Stacked die Combo package Includes two 64Mb Flash devices Choice of either one 32Mb or one 64Mb CellularRAMO device * Basic configuration Flash Flexible multibank architecture 4 Meg x 16 Async/Page/Burst interface Support for true concurrent operations with no latency CellularRAM Low-power, high-density design 2 Meg x 16 or 4 Meg x 16 configurations Async/Page * F_VCC, VCCQ, F_VPP, PS_VCC voltages 1.70V (MIN)/1.95V (MAX) F_VCC, PS_VCC 1.70V (MIN)/2.24V (MAX) VCCQ (W18) 1.70V (MIN)/3.3V(MAX) VCCQ (W30) 1.80V (TYP) F_VPP (in-system PROGRAM/ERASE) 12V 5% (HV) F_VPP (in-house programming and accelerated programming algorithm [APA] activation) * Asynchronous access time Flash/CellularRAM access time: 60ns @ 1.70V VCC * Page Mode read access (W18/W30) Interpage read access: 60ns @ 1.70V F_VCC , PS_VCC (W18) Intrapage read access: 20ns @ 1.70V F_VCC, PS_VCC (W18) Interpage read access: 70ns @ 1.70V F_VCC , PS_VCC (W30) Intrapage read access: 22ns @ 1.70V F_VCC, PS_VCC (W30) * Enhanced suspend options ERASE-SUSPEND-to-READ within same bank PROGRAM-SUSPEND-to-READ within same bank ERASE-SUSPEND-to-PROGRAM within same bank * Read/Write CellularRAM during program/erase of Flash * Each Flash contains two 64-bit chip protection registers for security purposes * Flash PROGRAM/ERASE cycles 100,000 WRITE/ERASE cycles per block * Cross-compatible command set support Extended command set Common Flash interface (CFI) compliant * Manufacturer's ID (ManID) Micron(R) (0x2Ch) Intel(R) (0x89h) 1 2 3 4 5 6 7 8 A A4 A18 A19 PS_VSS F_VCC F_VCC A21 A11 B A5 PS_LB# PS_VSS NC CLK NC A12 C A3 A17 F_VPP PS_WE# PS_CE# A9 A13 D A2 A7 F_WP# ADV# A20 A10 A15 E A1 A6 PS_UB# F_RST# F_WE# A8 A14 A16 F A0 DQ8 DQ2 DQ10 DQ5 DQ13 WAIT# F_CE2# G PS_OE# DQ0 DQ1 DQ3 DQ12 DQ14 DQ7 F_OE2# H NC F_OE1# DQ9 DQ11 DQ4 DQ6 DQ15 VCCQ J F_CE1# NC NC NC PS_VCC F_VCC VCCQ PS_ZZ# K PS_VSS VSSQ VCCQ F_VCC PS_VSS VSSQ F_VSS PS_VSS Top View (Ball Down) Marking Options * Timing 60ns 70ns * Burst Frequency 66 MHz1 54 MHz * Boot Block Configuration Top/Top Top/Bottom Bottom/Top Bottom/Bottom * I/O Voltage Range VccQ 1.70V-1.95V VccQ 1.70V-3.3V * Manufacturer's ID (ManID) Micron (0x2Ch) Intel (0x89h) * Operating Temperature Range Wireless Temperature (-25C to +85C) * Package 77-ball FBGA (8 x 10 grid) NOTE: -60 -70 6 5 TT TB BT BB 18 30 None K WT FW 1. Contact factory for availability. Part Number Example: MT28C128564W18DFW-705 BBWT 09005aef80b10a55 MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN PRODUCTS 1 (c)2003 Micron Technology, Inc. AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS. ADVANCE 128Mb MULTIBANK BURST FLASH 32Mb/64Mb ASYNC/PAGE CellularRAM COMBO Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Flash Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Boot Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 MultiChip Packaging Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Unique IDs, State Machines, and Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Flash Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Flash Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Data Sheet Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 09005aef80b10a55 MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. ADVANCE 128Mb MULTIBANK BURST FLASH 32Mb/64Mb ASYNC/PAGE CellularRAM COMBO List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: 77-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 77-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 09005aef80b10a55 MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. ADVANCE 128Mb MULTIBANK BURST FLASH 32Mb/64Mb ASYNC/PAGE CellularRAM COMBO List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Cross-Reference for Abbreviated Device Marks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Valid Part Number Combinations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Possible Boot Configurations for Flash Die . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Truth Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 CFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 09005aef80b10a55 MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. ADVANCE 128Mb MULTIBANK BURST FLASH 32Mb/64Mb ASYNC/PAGE CellularRAM COMBO General Description The refresh configuration register (CR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up and can be updated any time during normal operation. Special attention has been focused on standby current consumption during self-refresh. CellularRAM products include three system-accessible mechanisms used to minimize standby current. Partial array refresh (PAR) limits refresh to the portion of the memory array being used. Temperature compensated refresh (TCR) is used to adjust the refresh rate according to the ambient temperature. The refresh rate can be decreased at lower temperatures to minimize current consumption during standby. Deep power down (DPD) halts the REFRESH operation altogether and is used when no vital information is stored in the device. These three refresh mechanisms are adjusted through the CR. Please refer to Micron's Web site www.micron.com/ flash for the latest MT28F644W18/W30 Flash data sheet and http://www.micron.com/cellularram for the latest MT45W2MW16PFA and MT45W4MW16PFA CellularRAM data sheet. The MT28C128532W18/W30D and MT28C128564W18/W30D combination Flash and CellularRAM are high-performance, high-density, memory solutions that can significantly improve system performance. The Flash architecture features a multipartition configuration that supports READ-whilePROGRAM/ERASE operations with no latency. A 4Mb partition size enables optimal design flexibility. Two Flash devices are stacked to achieve the 128Mb density. Each Flash die has a dedicated CE# and OE# control, enabling each Flash to be independently selectable. The MT28C128532W18/W30D and MT28C128564W18/W30D stacked Flash devices enable soft protection for blocks, as read only, by configuring soft protection registers with dedicated command sequences. For security purposes, two userprogrammable 64-bit chip protection registers are provided for each Flash device. The embedded WORD PROGRAM and BLOCK ERASE functions are fully automated by an on-chip write state machine (WSM). An on-chip device status register can be used to monitor the WSM status and determine the progress of the PROGRAM/ERASE tasks. Each Flash device has a read configuration register (RCR) that defines how the Flash interacts with the memory bus. For device specifications and additional documentation concerning Flash and CellularRAM features, please refer to the MT28F644W18/W30 data sheet at www.micron.com/flash and the MT45W2MW16PFA and MT45W4MW16PFA data sheets at http:// www.micron.com/cellularram. The CellularRAM architecture features high-speed CMOS, dynamic random-access memories developed for low-power portable applications The CellularRAM device is available in either 32Mb or 64Mb densities. To operate seamlessly on a burst Flash bus, CellularRAM products have incorporated a transparent selfrefresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance. 09005aef80b10a55 MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN Flash Configurations Each Flash memory implements a multibank architecture (16 banks of 4Mb each) to allow concurrent operations. Any address within a block address range selects that block for the required READ, PROGRAM, or ERASE operation. Each Flash memory features eight 4K-word sectors (8 x 65,536 bits), designated as parameter blocks, and the remaining part is organized in main blocks of 32K words each (524,288 bits). The parameter blocks are addressed either by the low order addresses (bottom boot) or by the higher order addresses (top boot). The two Flash devices can be supplied with any combination of top or bottom boot (e.g., top/top, bottom/bottom, top/bottom, or bottom/top). Please see Figures 2 and 3 for more information. 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. ADVANCE 128Mb MULTIBANK BURST FLASH 32Mb/64Mb ASYNC/PAGE CellularRAM COMBO Figure 2: Flash Memory Map Parameter Blocks - Top Boot Main Main Main Main Main Parameter Blocks - Bottom Boot Main F_CE1#/F_OE1# controlled lower address space (0Mb to 64Mb) F_CE2#/F_OE2# controlled upper address space (64Mb to 128Mb) NOTE: Figure 2 shows a BT (bottom/top) dual Flash configuration. 09005aef80b10a55 MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. ADVANCE 128Mb MULTIBANK BURST FLASH 32Mb/64Mb ASYNC/PAGE CellularRAM COMBO Figure 3: Block Diagram F_OE1# F_CE1# F_WE# FLASH #1 Bank 0 4,096K x 16 Bank 15 ADV# F_VPP FLASH #2 F_CE2# F_OE2# Bank 16 4,096K x 16 A0-A21 VCCQ VSSQ PS_CE# PS_ZZ# PS_OE# PS_WE# 09005aef80b10a55 MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN CLK F_WP# F_RST# F_VCC F_VSS DQ0-DQ15 WAIT# Bank 31 CellularRAM 2,048K x 16 4,096K x 16 7 PS_UB# PS_LB# PS_VSS PS_VCC Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. ADVANCE 128Mb MULTIBANK BURST FLASH 32Mb/64Mb ASYNC/PAGE CellularRAM COMBO Device Marking Due to the size of the package, the Microna standard part number is not printed on the top of each device. Instead, an abbreviated device mark com- Table 1: prised of a five-digit alphanumeric code is used. The abbreviated device marks are cross-referenced to the Micron part numbers in Table 1. Cross-Reference for Abbreviated Device Marks PRODUCT PART NUMBER MT28C128532W18DFW-606 BTWT MT28C128532W18DFW-606 BBWT MT28C128532W18DFW-705 BTWT MT28C128532W18DFW-705 TTWT MT28C128564W18DFW-606 BTWT MT28C128564W18DFW-705 BTWT MT28C128532W18DFW-606 TBWT MT28C128532W18DFW-606 BBWT MT28C128532W18DFW-705 BBWT MT28C128532W18DFW-705 TTWT MT28C128532W30DFW-606 BBWT MT28C128532W30DFW-705 TBWT MT28C128564W30DFW-606 BTWT MT28C128564W30DFW-705 BTWT 09005aef80b10a55 MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN 8 PRODUCT MARKING SAMPLE MARKING MECHANICAL MARKING FW625 FW631 FW632 FW626 FW627 FW637 FW639 FW642 FW638 FW643 FW649 FW651 FW650 FW640 FX625 FX631 FX632 FX626 FX627 FX637 FX639 FX642 FX638 FX643 FX649 FX651 FX650 FX640 FY625 FY631 FY632 FY626 FY627 FY637 FY639 FY642 FY638 FY643 FY649 FY651 FY650 FY640 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. ADVANCE 128Mb MULTIBANK BURST FLASH 32Mb/64Mb ASYNC/PAGE CellularRAM COMBO Part Numbering Information Micron's low-power devices are available with several different combinations of features (see Figure 4). Valid combinations of features and their corresponding part numbers are listed in Table 2. Figure 4: Part Number Chart MT 28C 1285 64 W18 D FW -70 5 BB WT ES Micron Technology Production Status Flash Family Blank = Production ES = Engineering Samples MS = Mechanical Samples 28C = Dual-Supply Flash/CellularRAM Combo Operating Temperature Range Density/Organization/Banks WT = Wireless (-25C to +85C) 128 = two 64Mb (4,096K x 16) bank x = 5 Multibank 32 Banks (all banks have the same dimensions) Boot Block Starting Address BB BT TT TB CellularRAM Density 64 = 64Mb CellularRAM (4 Meg x 16) 32 = 32Mb CellularRAM (2 Meg x 16) = Bottom boot/Bottom boot = Bottom boot/Top boot = Top boot/Top boot = Top boot/Bottom boot Burst Mode Frequency Flash Read Mode Operation 5 = 54 MHz 6 = 66 MHz W = Flash Async/Page/Burst Read Operating Voltage Range Manufacturer's ID 18 VCC = 1.70V-1.95V VCC VCCQ = 1.70V-2.24V VCC None = Micron [2Ch] K = Intel [89h] 30 VCC = 1.70V-1.95V VCC VCCQ = 1.70V-3.30V VCC Access Time CE Select/Special Mark Package Code D = Dual CE Flash with Aysnchronous PSRAM FW = 77-ball FBGA (8 x 10 grid) Table 2: -60 = 60ns -70 = 70ns Valid Part Number Combinations PART NUMBER ManID ACCESS TIME (ns) MT28C128532W18DFW-606 BTWT MT28C128532W18DFW-606 BBWT MT28C128532W18DFW-705 BTWT MT28C128532W18DFW-705 TTWT MT28C128564W18DFW-606 BTWT MT28C128564W18DFW-705 BTWT MT28C128532W18DFW-606 TBWT MT28C128532W18DFW-606 BBWT MT28C128532W18DFW-705 BBWT MT28C128532W18DFW-705 TTWT MT28C128532W30DFW-606 BBWT MT28C128532W30DFW-705 TBWT MT28C128564W30DFW-606 BTWT MT28C128564W30DFW-705 BTWT Micron Micron Micron Micron Micron Micron Micron Micron Micron Micron Micron Micron Micron Micron -60 -60 -70 -70 -60 -70 -60 -60 -70 -70 -60 -70 -60 -70 09005aef80b10a55 MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN 9 BOOT BLOCK STARTING ADDRESS BURST FREQUENCY (MHz) Bottom/Top Bottom/Bottom Bottom/Top Top/Top Bottom/Top Bottom/Top Top/Bottom Bottom/Bottom Bottom/Bottom Top/Top Bottom/Bottom Top/Bottom Bottom/Top Bottom/Top 66 66 54 54 66 54 66 66 54 54 66 54 66 54 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. ADVANCE 128Mb MULTIBANK BURST FLASH 32Mb/64Mb ASYNC/PAGE CellularRAM COMBO Table 3: Ball Descriptions 77-BALL FBGA NUMBERS F1, E1, D1, C1, A1, B1, E2, D2, E6, C7, D7, A8, B8, C8, E7, D8, E8, C2, A2, A3, D6, A7 J1 F8 H2 G8 E5 D4 B2 E3 C5 G1 C6 J8 D5 B6 E4 G2, G3, F3, G4, H5, F5, H6, G7, F2, H3, F4, H4, G5, F6, G6, H7 F7 K7 C4 J6 K5 J5 J7 K6 B5, B7, H1, J2, J3, J4 B3, C3, D3 SYMBOL TYPE A0-A21 Input F_CE1# F_CE2# F_OE1# F_OE2# F_WE# F_WP# PS_LB# PS_UB# PS_WE# PS_OE# PS_CE# PS_ZZ# ADV# CLK F_RST# DQ0-DQ15 Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input I/O WAIT# F_VSS F_VPP F_VCC PS_VSS PS_VCC VCCQ VSSQ Output Supply Supply Supply Supply Supply Supply Supply - NC 09005aef80b10a55 MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN - - DESCRIPTIONS Addresses: Flash: A0-A21 (128Mb "D") CellularRAM: A0-A20 (32Mb) CellularRAM: A0-A21 (64Mb) Flash Chip Enable #1 Flash Chip Enable #2 Flash Output Enable #1 Flash Output Enable #2 Flash Write Enable Flash Write Protect CellularRAM Lower Byte Control CellularRAM Upper Byte Control CellularRAM Write Enable CellularRAM Output Enable CellularRAM Chip Enable CellularRAM Deep Sleep Mode and Configuration Mode Flash Address Valid (Burst operation only) Flash Clock (Burst operation only) Flash Reset Flash/CellularRAM Data Input/Output Flash WAIT# Flash Core Ground Flash VPP Flash Core Power Supply CellularRAM Core Ground CellularRAM Core Power Supply Flash/CellularRAM I/O Supply Flash/CellularRAM I/O Ground No Connect Ball not Mounted 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. ADVANCE 128Mb MULTIBANK BURST FLASH 32Mb/64Mb ASYNC/PAGE CellularRAM COMBO Boot Configurations Both Flash devices will share the same ManID, either Micron (0x2Ch) or Intel (0x89h), which is defined by the part number. (Se Figure 4 on page 9.) The CellularRAM has a configuration register (CR) that defines how the device performs self refresh. The possible configurations for Flash die are shown in Table 4 below. This table shows the possible configurations of the two Flash devices for either top boot or bottom boot: F_CE1# and F_CE2# indicate to which Flash die the configuration is referred. Table 4: Command Codes Possible Boot Configurations for Flash Die CONFIGURATION F_CE1# F_CE2# ORDER CODE Top/Top Bottom/Top Top/Bottom Bottom/Bottom Top Bottom Top Bottom Top Top Bottom Bottom TT BT TB BB All Flash command codes are independent within each device. Care must be taken when crossing the array boundary between the upper and lower Flash and the CellularRAM to ensure that only one device is enabled at one time. In a two-cycle command sequence such as word program (0x40/data), it is required that both commands be issued to the same device. It is not recommended that READ and ERASE operations occur simultaneously on two devices. MultiChip Packaging Considerations READ Operation Multichip packaging presents unique challenges when controlling complex memory devices. The MT28C128532W18/W30D and MT28C128564W18/W30D devices combine two Micron Flash devices with a single CellularRAM device. Page and burst read modes are limited to the address boundaries of each device. A new page/ burst operation must be started when crossing a device boundary. Unique IDs, State Machines, and Registers The reset control is shared by both Flash die. Bringing RST# control LOW will reset both the upper and lower device. Flash Reset Each Flash device has a separate command state machine (CSM) and status register (SR) and read configuration register (RCR). The RCR settings are separate and can be different for the upper and lower device. Each Flash device has its own OTP, CFI, and device code. Depending on the boot configuration of each Flash device, the OTP, CFI, and device code information may differ. 09005aef80b10a55 MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN Power Consumption Multiple chip packaging requires that power calculations consider the active operation of the upper and lower Flash as well as that of the CellularRAM. Total power consumed will be the sum of the currents associated with the state of each device. Table 9 on page 14 shows the power consumption specifications. 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. Truth Table FLASH SIGNALS SHARED SIGNALS CellularRAM SIGNALS MEMORY OUTPUT FLASH F_CE1# MEMORY PS_ BUS MODES F_CE1# F_CE2# F_OE1# F_OE2# F_WE# F_RP# ADV# WAIT# PS_CE# PS_ZZ# PS_OE# UB/LB PS_WE# CONTROL L L H H H X L H X H H X H L X H H H L L X Valid Valid X L X H X H H X X X H H X X L L H X H H X X L H X X H L X L H H H X L L X X L X H H H X X X X X Flash must be in High-Z Flash Flash Other DOUT DIN High-Z CellularRAM any mode allowable Other High-Z X Valid Valid X CellularRAM must be in High-Z None Flash Flash Other High-Z DOUT DIN High-Z X X CellularRAM any mode allowable Other High-Z L X X X X L L X X Valid Valid X L L H H H H L H X L L X H L X None PSRAM PSRAM Other High-Z DOUT DIN High-Z X X X L H H X X Other High-Z X X X H L X X X Other High-Z CellularRAM must be in High-Z Flash any mode allowable ADVANCE Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003, Micron Technology, Inc. CellularRAM 12 Read Write Standby Output Disable Reset Read Write Standby Output Disable Reset Read Write Standby Output Disable Deep Sleep Mode DQ0- DQ15 128Mb MULTIBANK BURST FLASH 32Mb/64Mb ASYNC/PAGE CellularRAM COMBO FLASH F_CE2# 09005aef80b10a55 MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN Table 5: ADVANCE 128Mb MULTIBANK BURST FLASH 32Mb/64Mb ASYNC/PAGE CellularRAM COMBO Flash Electrical Specifications Table 6: Absolute Maximum Ratings Note 1 PARAMETERS/CONDITIONS W18 W30 Voltage to any ball except VCC, VCCQ, and VPP VPP Voltage W18 W30 W18 W30 VCC Supply Voltage VCCQ Supply Voltage Output Short Circuit Current Operating Temperature Range Storage Temperature Range Soldering Cycle MIN MAX -0.5 -0.5 -0.2 +2.45 +3.45 +14 +2.45 +2.5 +2.45 +3.3465 100 +85 +125 +260C for 10s -0.2 -0.2 -25 -55 UNITS NOTES V V 2 V V mA C C NOTE: 1. Stresses greater than those listed in Table 6 may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Maximum DC voltage on VPP may overshoot to +14V for periods <20ns. Table 7: Recommended Operating Conditions PARAMETER SYMBOL MIN TYP MAX UNITS TA -25 - +85 C VCC VccQ (W18) VccQ (W30) CIO VPP1 VPP2 1.70 - V 1.70 - - 0.9 11.4 - - - 4.0 - - - - - 1.95 2.24 3.3 6.5 1.95 12.6 100,000 1,000 100 pF V V Cycles Cycles Hours SYMBOL TYP MAX UNITS CIN COUT TBD TBD TBD TBD pF pF Operating Temperature VCC Supply Voltage I/O Supply Voltage Input/Output Capacitance: DQs VPP Voltage VPP In-factory Programming Voltage Block Erase Cycling (VPP = VPP1) Block Erase Cycling (VPP = VPP2) Time for VPP at VPP2 Table 8: t PPH V Capacitance TA = +25C; f = 1 MHz PARAMETER/CONDITION Input Capacitance Output Capacitance 09005aef80b10a55 MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. ADVANCE 128Mb MULTIBANK BURST FLASH 32Mb/64Mb ASYNC/PAGE CellularRAM COMBO Table 9: DC Characteristics Notes appear on following page; all currents are in RMS unless otherwise noted W18/W30 PARAMETER Input Low Voltage Input High Voltage Output Low Voltage IOL = 100A Output High Voltage IOH = -100A VPP Lockout Voltage VCC Lock VccQ Lock Input Load Current Output Leakage Current VCC Standby Current with 32Mb PSRAM with 64Mb PSRAM Asynchronous Read Current Page Read Current Vcc Burst Read Current 4-word Burst Read Current @ 54 MHz 4-word Burst Read Current @ 66 MHz Vcc Burst Read Current 8-word Burst Read Current @ 54 MHz 8-word Burst Read Current @ 66 MHz Vcc Continuous Burst Read Current Continous Burst Read Current @ 54 MHz Continous Burst Read Current @ 66 MHz F_VCC Program Current F_VPP = F_VPP1, Program in Progress F_VPP = F_VPP2, Program in Progress F_VCC Block Erase Current F_VPP = F_VPP1, Block Erase in Progress F_VPP = F_VPP2, Block Erase in Progress F_VCC Program Suspend Current F_VCC Erase Suspend Current F_VCC Automatic Power Save Current F_VPP Standby Current F_VPP Program Suspend Current F_VPP Erase Suspend Current F_VPP Read Current 09005aef80b10a55 MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN SYM MIN VIL VIH 0 VCCQ - 0.4 TYP VOL VOH F_VPPLK F_VLKO F_VILKOQ F_ILI F_ILO MAX UNITS NOTES 0.4 VCCQ 0.1 V V V 1 1 VCCQ - 0.1 V 0.4 1.0 TBD V V V A A 1 1 ICCS A F_ICCR F_ICCR 2 3 140 150 4 6 F_ICCR 3 3 5 5 mA 2, 3, 5 F_ICCR 3 3 5 5 mA 2, 3, 5 F_ICCR 7 8 10 12 mA 2, 3, 5 F_ICCW 18 8 25 15 F_ICCE 18 8 7 7 7 0.2 0.2 0.2 2 30 15 25 25 25 5 5 5 15 mA mA mA mA F_ICCWS F_ICCES F_ICCAPS F_IPPS F_IPPWS F_IPPES F_IPPR 14 A A A 4 4 A A Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. ADVANCE 128Mb MULTIBANK BURST FLASH 32Mb/64Mb ASYNC/PAGE CellularRAM COMBO Table 9: DC Characteristics (continued) Notes appear on following page; all currents are in RMS unless otherwise noted W18/W30 PARAMETER F_VPP Program Current F_VPP = F_VPP1, Program in Progress F_VPP = F_VPP2, Program in Progress F_VPP Erase Current F_VPP = F_VPP1, Erase in Progress F_VPP = F_VPP2, Erase in Progress Read Operating Current Asynchronous Random READ Asynchronous Page READ Initial Access, Burst READ Continuous Burst READ Write Operating Current SYM MIN TYP MAX F_IPPW 0.05 8 0.10 22 F_IPPE 0.05 8 0.10 22 (-60) (-70) 25 21 15 13 35 21 15 11 UNITS NOTES mA mA PS_ICC1 PS_ICC2 (-60) (-70) mA 6, 7, 8 mA 6, 7, 9 25 21 NOTE: 1. VIL may decrease to -0.4V and VIH may increase to VCCQ + 0.3V for durations not to exceed 20ns. 2. APS mode reduces ICC to approximately ICCS levels. 3. Test conditions: VCC = VCC (MAX), CE# = VIL, OE# = VIH. All other inputs = VIH or VIL. 4. ICCES and ICCWS values are valid when the device is deselected. Any READ operation performed while in suspend mode will have an additional current draw of suspend current (ICCES or ICCWS). 5. Synchronous clock = 54 MHz/burst length = continuous is worst case for VCC burst read current. 6. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive output capacitance expected in the actual system. 7. This device assumes a standby mode if the chip is disabled (CE# HIGH). It will also automatically go into a standby mode whenever all input signals are quiescent (not toggling), regardless of the state of CE#, UB#, and LB#. In order to achieve low standby current all inputs must be either VCC or VSS. 8. VIN = VCC or 0V Chip Enabled, IOUT = 0. 9. VIN = VCC or 0V Chip Enabled, IOUT = 0. 09005aef80b10a55 MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. ADVANCE 128Mb MULTIBANK BURST FLASH 32Mb/64Mb ASYNC/PAGE CellularRAM COMBO Table 10: CFI OFFSET 00 DATA DESCRIPTION Manufacturer's Identification Code (ManID) Micron Intel Device ID Code (DevID) 44C6h/8864h Top boot block device ID code (Micron / Intel) 44C7h/8865h Bottom boot block device ID code (Micron/Intel) reserved Reserved 0051, 0052 "QR" 0059 "Y" 0003, 0000 Primary OEM command set 0039, 0000 Address for primary extended table 0000, 0000 Alternate OEM command set 0000, 0000 Address for OEM extended table 0017 VCC MIN for Erase/Write; Bit 7-bit 4 volts in BCD; Bit 3-bit 0 100mV in BCD 0019 VCC MAX for Erase/Write; Bit 7-bit 4 volts in BCD; Bit 3-bit 0 100mV in BCD 00B4 VPP MIN for Erase/Write; Bit 7-bit 4 volts in hex; Bit 3-bit 0 100mV in BCD 00C6 VPP MAX for Erase/Write; Bit 7-bit 4 Volts in hex; Bit 3-bit 0 100mV in BCD 0004 Typical timeout for single byte/word program, 2ns, 0000 = not supported 2Ch 89h 01 02 - 0F 10, 11 12 13, 14 15, 16 17, 18 19, 1A 1B 1C 1D 1E 1F 20 0000 Typical timeout for maximum size multiple byte/word program, 2ns, 0000 = not supported 21 000A Typical timeout for individual block erase, 2ns, 0000 = not supported 22 0000 Typical timeout for full chip erase, 2ns, 0000 = not supported 23 0004 Maximum timeout for single byte/word program, 2ns, 0000 = not supported 24 0000 Maximum timeout for maximum size multiple byte/word program, 2ns, 0000 = not supported 25 0002 Maximum timeout for individual block erase, 2ns, 0000 = not supported 26 0000 Maximum timeout for full chip erase, 2ns, 0000 = not supported 27 0017 28 29 2A, 2B 0001 0000 0000, 0000 Device size, 2n bytes Bus interface x8 = 0, x16 = 1, x32 = 2, x64 = 3 Flash device interface description 0000 = async 2C 2D, 2E 0002 007E, 0000 0007, 0000 0000, 0001 0020, 0000 0007, 0000 007E, 0000 0020, 0000 0000, 0001 0000, 0000 0000, 0000 0050, 0052 0049 0031 2F, 30 31, 32 33, 34 35, 36 37, 38 39, 3A 3B 3C 09005aef80b10a55 MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN Maximum number of bytes in multibyte program or page, 2n Number of erase block regions within device (4K words and 32K words) Top boot block device erase block region information 1 Bottom boot block device erase block region information 1 Top boot block device erase block region information 1 Bottom boot block device erase block region information 1 Top boot block device erase block region information 2 Bottom boot block device erase block region information 2 Top boot block device erase block region information 2 Bottom boot block device erase block region information 2 Reserved for future erase block region information Reserved for future erase block region information "PR" "I" Major version number, ASCII 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. ADVANCE 128Mb MULTIBANK BURST FLASH 32Mb/64Mb ASYNC/PAGE CellularRAM COMBO Table 10: CFI (continued) OFFSET DATA 3D 3E 3F 40 41 0033 00E6 0003 0000 0000 42 43, 44 45 46 47 48, 49 4A, 4B 0001 0003, 0000 0018 00C0 0001 0080, 0000 0003, 0003 4C 4D 4E 4F 50 51 52 0004 0004 0001 0002 0007 0000 Top: 0002 Bot :0002 Top: 000F Bot: 0001 Top: 0000 Bot: 0000 Top: 0011 Bot: 0011 Top: 0000 Bot: 0000 Top: 0000 Bot: 0000 Top: 0001 Bot: 0002 Top: 0007 Bot: 0007 Top: 0000 Bot: 0000 Top: 0000 Bot: 0020 Top: 0001 Bot: 0000 53 54 55 56 57 58 59 5A 5B 5C 09005aef80b10a55 MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN DESCRIPTION Minor version number, ASCII Optional Feature and Command Support Bit 0 Chip erase supported no = 0 Bit 1 Suspend erase supported = yes = 1 Bit 2 Suspend program supported = yes = 1 Bit 3 Chip lock/unlock supported = no = 0 Bit 4 Queued erase supported = no = 0 Bit 5 Instant individual block locking supported = yes = 1 Bit 6 Protection bits supported = yes = 1 Bit 7 Page mode read supported = yes = 1 Bit 8 Synchronous read supported = no = 0 Bit 9 Simultaneous operation supported = yes = 1 Program supported after erase suspend = yes Bit 0 block lock status active = yes; Bit 1 block lock down active = yes VCC supply optimum, 00 = not supported, Bit 7-bit 4 volts in BCD; Bit 3-bit 0 100mV in BCD VPP supply optimum, 00 = not supported, Bit 7-bit 4 volts in BCD; Bit 3-bit 0 100mV in BCD Number of protection register fields in JEDEC ID space Lock bytes LOW address, lock bytes HIGH address 2n factory programmed bytes, 2n user programmable bytes Page mode read capability Number of synchronous mode read configuration fields that follow Synchronous mode read capability configuration 1 Synchronous mode read capability configuration 2 Synchronous mode read capability configuration 3 Synchronous mode read capability configuration 4 Number of device hardware partition regions within the device Number of identical partitions within the partition region Number of identical partitions within the partition region Number of identical partitions within the partition region Simultaneous PROGRAM/ERASE operations allowed in other partitions while a partition in this region is in program mode Simultaneous PROGRAM/ERASE operations allowed in other partitions while a partition in this region is in erase mode Types of erase block regions in this partition region Partition region 1 erase block type 1 information Partition region 1 erase block type 1 information Partition region 1 erase block type 1 information Partition region 1 erase block type 1 information 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. ADVANCE 128Mb MULTIBANK BURST FLASH 32Mb/64Mb ASYNC/PAGE CellularRAM COMBO Table 10: CFI (continued) OFFSET DATA 5D Top: 0064 Bot: 0064 Top: 0000 Bot: 0000 Top: 0001 Bot: 0001 Top: 0003 Bot: 0003 5E 5F 60 DESCRIPTION Partition 1 (erase block type 1) Partition 1 (erase block type 1) Partition 1 (erase block type 1) bits per cell; internal ECC Partition 1 (erase block type 1) page mode and synchronous mode capabilities Partition region 1 erase block type 2 information Bot: 61 Bot: 0006 Bot: 62 Bot: 0000 Bot: 63 Bot: 0000 Partition region 1 erase block type 2 information Partition region 1 erase block type 2 information Partition region 1 erase block type 2 information Bot: 64 Bot: 0001 Bot: 65 Bot: 0064 Bot: 66 Bot: 0000 Bot: 67 Bot: 0001 Bot: 68 Top: 61 Bot: 69 Top: 62 Bot: 6A Top: 63 Bot: 6B Top: 64 Bot: 6C Top: 65 Bot: 6D Top: 66 Bot: 6E Top: 67 Bot: 6F Top: 68 Bot: 70 Top: 69 Bot: 71 Top: 6A Bot: 72 Bot: 0003 Top: 0001 Bot: 000F Top: 0000 Bot: 0000 Top: 0011 Bot: 0011 Top: 0000 Bot: 0000 Top: 0000 Bot: 0000 Top: 0002 Bot: 0001 Top: 0006 Bot: 0007 Top: 0000 Bot: 0000 Top: 0000 Bot: 0000 Top: 0001 Bot: 0001 Partition region 1 (erase block type 2) Partition region 1 (erase block type 2) Partition region 1 (erase block type 2) bits per cell Partition region 1 (erase block type 2) page mode and synchronous mode capabilities 09005aef80b10a55 MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN Number of identical partitions within the partition region Number of identical partitions within the partition region Number of PROGRAM/ERASE operations allowed in a partition Simultaneous PROGRAM/ERASE operations allowed in other partitions while a partition in this region is in program mode Simultaneous PROGRAM/ERASE operations allowed in other partitions while a partition in this region is in erase mode Types of erase block regions in this partition region Partition region 2 erase block type 1 information Partition region 2 erase block type 1 information Partition region 2 erase block type 1 information Partition region 2 erase block type 1 information 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. ADVANCE 128Mb MULTIBANK BURST FLASH 32Mb/64Mb ASYNC/PAGE CellularRAM COMBO Table 10: CFI (continued) OFFSET DATA Top: 6B Bot: 73 Top: 6C Bot: 74 Top: 6D Bot: 75 Top: 6E Bot: 76 Top: 6F Top: 0064 Bot: 0064 Top: 0000 Bot: 0000 Top: 0001 Bot: 0001 Top: 0003 Bot: 0003 Top: 0007 Partition 2 (erase block type 1) Top: 70 Top: 0000 Partition region 2 erase block type 2 information Top: 71 Top: 0020 Partition region 2 erase block type 2 information Top: 72 Top: 0000 Partition region 2 erase block type 2 information Top: 73 Top: 0064 Partition 2 (erase block type 2) Top: 74 Top: 0000 Partition 2 (erase block type 2) Top: 75 Top: 0001 Partition 2 (erase block type 2) bits per cell Top: 76 Top: 0003 Partition 2 (erase block type 2) page mode and synchronous mode capabilities 77 78 79-7F DESCRIPTION Partition 2 (erase block type 1) Partition 2 (erase block type 1) bits per cell Partition 2 (erase block type 1) page mode and synchronous mode capabilities Partition region 2 erase block type 2 information Reserved 32Mb: 0020 PSRAM Density 64Mb: 0040 Reserved 09005aef80b10a55 MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. ADVANCE 128Mb MULTIBANK BURST FLASH 32Mb/64Mb ASYNC/PAGE CellularRAM COMBO Figure 5: 77-Ball FBGA 1.025 0.075 SEATING PLANE C SOLDER BALL MATERIAL: EUTECTIC 62% Sn, 36% Pb, 2% Ag SUBSTRATE: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC 0.10 C 77X 0.35 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS O 0.35mm ON A 0.30mm SMD BALL PAD. 5.60 BALL A1 ID BALL A1 0.80 TYP BALL A1 ID 5.00 0.05 BALL A8 7.20 10.00 0.10 CL 3.60 0.05 0.80 TYP CL 2.80 0.05 4.00 0.05 1.40 MAX 8.00 0.10 NOTE: 1. All dimensions in millimeters. Data Sheet Designation Advance: This data sheet contains initial descriptions of products still under development. For additional documentation concerning Flash and CellularRAM features, functional descriptions, programming, and timing, please refer to the MT28F644W18/W30 data sheet at www.micron.com/flash and the MT45W2MW16PFA and MT45W4MW16PFA data sheets at http://www.micron.com/cellularram. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. CellularRAM is a trademark of Micron Technology, Inc., inside the U.S. and a trademark of Infineon Technologies outside the U.S. All other trademarks are the property of their respective owners. 09005aef80b10a55 MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN 20 Micron Technology, Inc., reserves the right to change products or specifications without notice.. (c)2003 Micron Technology, Inc ADVANCE 128Mb MULTIBANK BURST FLASH 32Mb/64Mb ASYNC/PAGE CellularRAM COMBO Revision History Rev B, Advance.................................................................................................................................................................7/03 * Included W30 specification * Added Intel ManID varient * Updated mechanical information * Table 10 (CFI) clarification Original document, Rev. A ..............................................................................................................................................5/03 09005aef80b10a55 MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.