MT28C128532W18DFW-606BBWT - Micron

‡PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.

09005aef80b10a55

128Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE‡

FLASH AND CellularRAM™

COMBO MEMORY

MT28C128532W18/W30D

MT28C128564W18/W30D

Low Voltage, Wireless Temperature

Features

• Stacked die Combo package

Includes two 64Mb Flash devices

Choice of either one 32Mb or one 64Mb

CellularRAMÔ device

• Basic configuration

Flash

Flexible multibank architecture

4 Meg x 16 Async/Page/Burst interface

Support for true concurrent operations with

no latency

CellularRAM

Low-power, high-density design

2 Meg x 16 or 4 Meg x 16 configurations

Async/Page

•F_V

CC, VCCQ, F_VPP, PS_VCC voltages

1.70V (MIN)/1.95V (MAX) F_VCC, PS_VCC

1.70V (MIN)/2.24V (MAX) VCCQ (W18)

1.70V (MIN)/3.3V(MAX) VCCQ (W30)

1.80V (TYP) F_VPP (in-system PROGRAM/ERASE)

12V ±5% (HV) F_VPP (in-house programming and

accelerated programming algorithm [APA]

activation)

• Asynchronous access time

Flash/CellularRAM access time: 60ns @ 1.70V VCC

• Page Mode read access (W18/W30)

Interpage read access: 60ns @ 1.70V F_V

, PS_V

(W18)

Intrapage read access: 20ns @ 1.70V F_V

, PS_V

(W18)

Interpage read access: 70ns @ 1.70V F_VCC , PS_VCC (W30)

Intrapage read access: 22ns @ 1.70V F_VCC, PS_VCC (W30)

• Enhanced suspend options

ERASE-SUSPEND-to-READ within same bank

PROGRAM-SUSPEND-to-READ within same bank

ERASE-SUSPEND-to-PROGRAM within same bank

• Read/Write CellularRAM during program/erase of

Flash

• Each Flash contains two 64-bit chip protection

registers for security purposes

• Flash PROGRAM/ERASE cycles

100,000 WRITE/ERASE cycles per block

• Cross-compatible command set support

Extended command set

Common Flash interface (CFI) compliant

• Manufacturer’s ID (ManID)

Micron® (0x2Ch)

Intel® (0x89h)

NOTE: 1. Contact factory for availability.

Part Number Example:

MT28C128564W18DFW-705 BBWT

Options Marking

• Timing

60ns

70ns

-60

-70

• Burst Frequency

66 MHz1

54 MHz

• Boot Block Configuration

Top/Top

Top/Bottom

Bottom/Top

Bottom/Bottom

•I/O Voltage Range

VccQ 1.70V–1.95V

VccQ 1.70V–3.3V

• Manufacturer’s ID (ManID)

Micron (0x2Ch)

Intel (0x89h)

None

• Operating Temperature Range

Wireless Temperature (-25°C to +85°C) WT

•Package

77-ball FBGA (8 x 10 grid) FW

Figure 1: 77-Ball FBGA

1 2 3 4 5 6 7 8

Top View

(Ball Down)

PS_VSS

F_VPP

F_WP#

F_RST#

DQ10

DQ3

DQ11

F_VCC

A19

PS_UB#

DQ2

DQ1

DQ9

VCCQ

PS_OE#

F_CE1#

PS_VSS

F_VCC

CLK

PS_CE#

A20

DQ13

DQ14

DQ6

F_VCC

VSSQ

A10

A14

WAIT#

DQ7

DQ15

VCCQ

F_VSS

A11

A12

A13

A15

A16

F_CE2#

F_OE2#

VCCQ

PS_ZZ#

PS_VSS

F_VCC

PS_WE#

ADV#

F_WE#

DQ5

DQ12

DQ4

PS_VCC

PS_VSS

A18

PS_LB#

A17

DQ8

DQ0

F_OE1#

VSSQ

A21

128Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

09005aef80b10a55 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table of Contents

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Flash Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Boot Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

MultiChip Packaging Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Unique IDs, State Machines, and Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Flash Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Flash Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Data Sheet Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

128Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

09005aef80b10a55 Micron Technology, Inc., reserves the right to change products or specifications without notice.

List of Figures

Figure 1: 77-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Figure 2: Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Figure 3: Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Figure 4: Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 5: 77-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

128Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

09005aef80b10a55 Micron Technology, Inc., reserves the right to change products or specifications without notice.

List of Tables

Table 1: Cross-Reference for Abbreviated Device Marks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Table 2: Valid Part Number Combinations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Table 3: Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Table 4: Possible Boot Configurations for Flash Die . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Table 5: Truth Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Table 6: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 7: Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 8: Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 9: DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 10: CFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

128Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

09005aef80b10a55 Micron Technology, Inc., reserves the right to change products or specifications without notice.

General Description

The MT28C128532W18/W30D and

MT28C128564W18/W30D combination Flash and Cel-

lularRAM are high-performance, high-density, mem-

ory solutions that can significantly improve system

performance. The Flash architecture features a multi-

partition configuration that supports READ-while-

PROGRAM/ERASE operations with no latency. A 4Mb

partition size enables optimal design flexibility.

Two Flash devices are stacked to achieve the 128Mb

density. Each Flash die has a dedicated CE# and OE#

control, enabling each Flash to be independently select-

able.

The MT28C128532W18/W30D and

MT28C128564W18/W30D stacked Flash devices

enable soft protection for blocks, as read only, by con-

figuring soft protection registers with dedicated com-

mand sequences. For security purposes, two user-

programmable 64-bit chip protection registers are pro-

vided for each Flash device.

The embedded WORD PROGRAM and BLOCK

ERASE functions are fully automated by an on-chip

write state machine (WSM). An on-chip device status

determine the progress of the PROGRAM/ERASE tasks.

Each Flash device has a read configuration register

(RCR) that defines how the Flash interacts with the mem-

ory bus. For device specifications and additional docu-

mentation concerning Flash and CellularRAM features,

please refer to the MT28F644W18/W30 data sheet at

www.micron.com/flash and the MT45W2MW16PFA and

MT45W4MW16PFA data sheets at http://

www.micron.com/cellularram.

The CellularRAM architecture features high-speed

CMOS, dynamic random-access memories developed

for low-power portable applications The CellularRAM

device is available in either 32Mb or 64Mb densities.

To operate seamlessly on a burst Flash bus, Cellular-

RAM products have incorporated a transparent self-

refresh mechanism. The hidden refresh requires no

additional support from the system memory controller

and has no significant impact on device read/write per-

formance.

The refresh configuration register (CR) is used to con-

trol how refresh is performed on the DRAM array. These

registers are automatically loaded with default settings

during power-up and can be updated any time during

normal operation. Special attention has been focused

on standby current consumption during self-refresh.

CellularRAM products include three system-acces-

sible mechanisms used to minimize standby current.

Partial array refresh (PAR) limits refresh to the portion

of the memory array being used. Temperature com-

pensated refresh (TCR) is used to adjust the refresh

rate according to the ambient temperature. The

refresh rate can be decreased at lower temperatures to

minimize current consumption during standby. Deep

power down (DPD) halts the REFRESH operation alto-

gether and is used when no vital information is stored

in the device. These three refresh mechanisms are

adjusted through the CR.

Please refer to Micron’s Web site www.micron.com/

flash for the latest MT28F644W18/W30 Flash data

sheet and

http://www.micron.com/cellularram

for the

latest MT45W2MW16PFA and MT45W4MW16PFA Cel-

lularRAM data sheet.

Flash Configurations

Each Flash memory implements a multibank archi-

tecture (16 banks of 4Mb each) to allow concurrent

operations. Any address within a block address range

selects that block for the required READ, PROGRAM, or

ERASE operation.

Each Flash memory features eight 4K-word sectors

(8 x 65,536 bits), designated as parameter blocks, and

the remaining part is organized in main blocks of 32K

words each (524,288 bits). The parameter blocks are

addressed either by the low order addresses (bottom

boot) or by the higher order addresses (top boot).

The two Flash devices can be supplied with any

combination of top or bottom boot (e.g., top/top, bot-

tom/bottom, top/bottom, or bottom/top). Please see

Figures 2 and 3 for more information.

128Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

09005aef80b10a55 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 2: Flash Memory Map

NOTE:

Figure 2 shows a BT (bottom/top) dual Flash configuration.

Parameter

Blocks –

Top Boot

F_CE2#/F_OE2#

controlled upper address space

(64Mb to 128Mb)

Main

Parameter

Blocks –

Bottom Boot

F_CE1#/F_OE1#

controlled lower address space

(0Mb to 64Mb)

Main

128Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

09005aef80b10a55 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 3: Block Diagram

PS_OE#

PS_ZZ#

PS_CE#

PS_WE#

DQ0

–

DQ15

–

A21

F_WE#

F_OE2#

F_CE2#

CLK

WP#

WAIT

FLASH #1

CellularRAM

F_RST#

PS_UB#

PS_LB#

4,096K x 16

2,048K x 16

4,096K x 16

Bank 0

Bank 15

PS_VCC

F_OE1#

F_CE1#

ADV#

PS_VSS

FLASH #2

4,096K x 16

Bank 16

Bank 31

F_V

128Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

09005aef80b10a55 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Device Marking

Due to the size of the package, the Micronâ stan-

dard part number is not printed on the top of each

device. Instead, an abbreviated device mark com-

prised of a five-digit alphanumeric code is used. The

abbreviated device marks are cross-referenced to the

Micron part numbers in Table 1.

Table 1: Cross-Reference for Abbreviated Device Marks

PRODUCT PART NUMBER

PRODUCT

MARKING

SAMPLE

MARKING

MECHANICAL

MARKING

MT28C128532W18DFW-606 BTWT FW625 FX625 FY625

MT28C128532W18DFW-606 BBWT FW631 FX631 FY631

MT28C128532W18DFW-705 BTWT FW632 FX632 FY632

MT28C128532W18DFW-705 TTWT FW626 FX626 FY626

MT28C128564W18DFW-606 BTWT FW627 FX627 FY627

MT28C128564W18DFW-705 BTWT FW637 FX637 FY637

MT28C128532W18DFW-606 TBWT FW639 FX639 FY639

MT28C128532W18DFW-606 BBWT FW642 FX642 FY642

MT28C128532W18DFW-705 BBWT FW638 FX638 FY638

MT28C128532W18DFW-705 TTWT FW643 FX643 FY643

MT28C128532W30DFW-606 BBWT FW649 FX649 FY649

MT28C128532W30DFW-705 TBWT FW651 FX651 FY651

MT28C128564W30DFW-606 BTWT FW650 FX650 FY650

MT28C128564W30DFW-705 BTWT FW640 FX640 FY640

128Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

09005aef80b10a55 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Part Numbering Information

Micron’s low-power devices are available with sev-

eral different combinations of features (see Figure 4).

Valid combinations of features and their correspond-

ing part numbers are listed in Table 2.

Figure 4: Part Number Chart

MT 28C 1285 64 W18 D FW -70 5 BB WT ES

Micron Technology

Flash Family

28C = Dual-Supply Flash/CellularRAM Combo

Density/Organization/Banks

128 = two 64Mb (4,096K x 16)

bank x = 5 Multibank 32 Banks

(all banks have the same dimensions)

Access Time

-60 = 60ns

-70 = 70ns

CellularRAM Density

64 = 64Mb CellularRAM (4 Meg x 16)

32 = 32Mb CellularRAM (2 Meg x 16)

Flash Read Mode Operation

W = Flash Async/Page/Burst Read

Package Code

FW = 77-ball FBGA (8 x 10 grid)

Operating Temperature Range

WT = Wireless (-25ºC to +85ºC)

Burst Mode Frequency

5 = 54 MHz

6 = 66 MHz

Boot Block Starting Address

BB = Bottom boot/Bottom boot

BT = Bottom boot/Top boot

TT = Top boot/Top boot

TB = Top boot/Bottom boot

Operating Voltage Range

VCC = 1.70V–1.95V VCC

VCCQ = 1.70V–2.24V VCC

VCC = 1.70V–1.95V VCC

VCCQ = 1.70V–3.30V VCC

CE Select/Special Mark

D = Dual CE Flash with Aysnchronous PSRAM

Production Status

Blank = Production

ES = Engineering Samples

MS = Mechanical Samples

Manufacturer's ID

None = Micron [2Ch]

K = Intel [89h]

Table 2: Valid Part Number Combinations

PART NUMBER ManID

ACCESS

TIME (ns)

BOOT BLOCK STARTING

ADDRESS

BURST

FREQUENCY

(MHz)

MT28C128532W18DFW-606 BTWT Micron -60 Bottom/Top 66

MT28C128532W18DFW-606 BBWT Micron -60 Bottom/Bottom 66

MT28C128532W18DFW-705 BTWT Micron -70 Bottom/Top 54

MT28C128532W18DFW-705 TTWT Micron -70 Top/Top 54

MT28C128564W18DFW-606 BTWT Micron -60 Bottom/Top 66

MT28C128564W18DFW-705 BTWT Micron -70 Bottom/Top 54

MT28C128532W18DFW-606 TBWT Micron -60 Top/Bottom 66

MT28C128532W18DFW-606 BBWT Micron -60 Bottom/Bottom 66

MT28C128532W18DFW-705 BBWT Micron -70 Bottom/Bottom 54

MT28C128532W18DFW-705 TTWT Micron -70 Top/Top 54

MT28C128532W30DFW-606 BBWT Micron -60 Bottom/Bottom 66

MT28C128532W30DFW-705 TBWT Micron -70 Top/Bottom 54

MT28C128564W30DFW-606 BTWT Micron -60 Bottom/Top 66

MT28C128564W30DFW-705 BTWT Micron -70 Bottom/Top 54

128Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

09005aef80b10a55 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table 3: Ball Descriptions

77-BALL FBGA

NUMBERS SYMBOL TYPE DESCRIPTIONS

F1, E1, D1, C1, A1,

B1, E2, D2, E6, C7,

D7, A8, B8, C8, E7,

D8, E8, C2, A2, A3,

D6, A7

A0–A21 Input Addresses:

Flash: A0–A21 (128Mb “D”)

CellularRAM: A0–A20 (32Mb)

CellularRAM: A0–A21 (64Mb)

J1 F_CE1# Input Flash Chip Enable #1

F8 F_CE2# Input Flash Chip Enable #2

H2 F_OE1# Input Flash Output Enable #1

G8 F_OE2# Input Flash Output Enable #2

E5 F_WE# Input Flash Write Enable

D4 F_WP# Input Flash Write Protect

B2 PS_LB# Input CellularRAM Lower Byte Control

E3 PS_UB# Input CellularRAM Upper Byte Control

C5 PS_WE# Input CellularRAM Write Enable

G1 PS_OE# Input CellularRAM Output Enable

C6 PS_CE# Input CellularRAM Chip Enable

J8 PS_ZZ# Input CellularRAM Deep Sleep Mode and Configuration Mode

D5 ADV# Input Flash Address Valid (Burst operation only)

B6 CLK Input Flash Clock (Burst operation only)

E4 F_RST# Input Flash Reset

G2, G3, F3, G4, H5,

F5, H6, G7, F2, H3,

F4, H4, G5, F6, G6,

DQ0–DQ15 I/O Flash/CellularRAM Data Input/Output

F7 WAIT# Output Flash WAIT#

K7 F_VSS Supply Flash Core Ground

C4 F_VPP Supply Flash VPP

J6 F_VCC Supply Flash Core Power Supply

K5 PS_VSS Supply CellularRAM Core Ground

J5 PS_VCC Supply CellularRAM Core Power Supply

J7 VCCQ Supply Flash/CellularRAM I/O Supply

K6 VSSQ Supply Flash/CellularRAM I/O Ground

B5, B7, H1, J2, J3,

J4 NC –No Connect

B3, C3, D3 – – Ball not Mounted

128Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

09005aef80b10a55 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Boot Configurations

The possible configurations for Flash die are shown

in Table 4 below. This table shows the possible config-

urations of the two Flash devices for either top boot or

bottom boot: F_CE1# and F_CE2# indicate to which

Flash die the configuration is referred.

MultiChip Packaging Considerations

Multichip packaging presents unique chal-

lenges when controlling complex memory devices.

The MT28C128532W18/W30D and

MT28C128564W18/W30D devices combine two

Micron Flash devices with a single CellularRAM

device.

Unique IDs, State Machines, and

Registers

Each Flash device has a separate command state

machine (CSM) and status register (SR) and read con-

figuration register (RCR). The RCR settings are sepa-

rate and can be different for the upper and lower

device. Each Flash device has its own OTP, CFI, and

device code. Depending on the boot configuration of

each Flash device, the OTP, CFI, and device code infor-

mation may differ.

Both Flash devices will share the same ManID,

either Micron (0x2Ch) or Intel (0x89h), which is

defined by the part number. (Se Figure 4 on page 9.)

The CellularRAM has a configuration register (CR)

that defines how the device performs self refresh.

Command Codes

All Flash command codes are independent

within each device. Care must be taken when

crossing the array boundary between the upper

and lower Flash and the CellularRAM to ensure

that only one device is enabled at one time.

In a two-cycle command sequence such as word

program (0x40/data), it is required that both com-

mands be issued to the same device.

It is not recommended that READ and ERASE

operations occur simultaneously on two devices.

READ Operation

Page and burst read modes are limited to the

address boundaries of each device. A new page/ burst

operation must be started when crossing a device

boundary.

Flash Reset

The reset control is shared by both Flash die.

Bringing RST# control LOW will reset both the

upper and lower device.

Power Consumption

Multiple chip packaging requires that power

calculations consider the active operation of the

upper and lower Flash as well as that of the Cellu-

larRAM. Total power consumed will be the sum of

the currents associated with the state of each

device. Table 9 on page 14 shows the power con-

sumption specifications.

Table 4: Possible Boot Configurations

for Flash Die

CONFIGURATION F_CE1# F_CE2#

ORDER

CODE

Top/Top Top Top TT

Bottom/Top Bottom Top BT

Top/Bottom Top Bottom TB

Bottom/Bottom Bottom Bottom BB

128Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

09005aef80b10a55 Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN

Table 5: Truth Table

MODES

FLASH SIGNALS SHARED SIGNALS CellularRAM SIGNALS MEMORY OUTPUT

F_CE1# F_CE2# F_OE1# F_OE2# F_WE# F_RP# ADV# WAIT# PS_CE# PS_ZZ# PS_OE#

PS_

UB/LB PS_WE#

MEMORY

BUS

CONTROL

DQ0–

DQ15

FLASH F_CE1#

Read LHL HHHLValid CellularRAM must be in High-Z Flash DOUT

Write LHHHLHLValid FlashD

Standby HXX XXHXX

CellularRAM any mode allowable

Other High-Z

Output

Disable LXHXHHXX OtherHigh-Z

Reset X X X X X L X X None High-Z

FLASH F_CE2#

Read HLH LHHLValid CellularRAM must be in High-Z Flash DOUT

Write HLHHLHLValid FlashD

Standby XHX XXHXX

CellularRAM any mode allowable

Other High-Z

Output

Disable XLXHHHXX OtherHigh-Z

Reset X X X X X L X X None High-Z

CellularRAM

Read Flash must be in High-Z XLValidL H L L HPSRAMD

OUT

Write XLValidL H H L LPSRAMD

Standby

Flash any mode allowable

XXX H H X X X OtherHigh-Z

Output

Disable XXX L H H X X OtherHigh-Z

Deep

Sleep

Mode

XXX H L X X X OtherHigh-Z

128Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

09005aef80b10a55 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Flash Electrical Specifications

NOTE:

1. Stresses greater than those listed in Table 6 may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above those indicated in the operational sec-

tions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may

affect reliability.

2. Maximum DC voltage on VPP may overshoot to +14V for periods <20ns.

Table 6: Absolute Maximum Ratings

Note 1

PARAMETERS/CONDITIONS MIN MAX UNITS NOTES

Voltage to any ball except VCC, VCCQ, and VPP W18

W30

-0.5

+2.45

+3.45 V

VPP Voltage -0.2 +14 V 2

VCC Supply Voltage W18

W30 -0.2 +2.45

+2.5 V

VCCQ Supply Voltage W18

W30 -0.2 +2.45

+3.3465 V

Output Short Circuit Current 100 mA

Operating Temperature Range -25 +85 °C

Storage Temperature Range -55 +125 °C

Soldering Cycle +260°C for 10s

Table 7: Recommended Operating Conditions

PARAMETER SYMBOL MIN TYP MAX UNITS

Operating Temperature TA-25 – +85 °C

VCC Supply Voltage VCC 1.70 – 1.95 V

I/O Supply Voltage VccQ (W18) 1.70 – 2.24 V

VccQ (W30) 3.3

Input/Output Capacitance: DQs CIO –4.06.5pF

VPP Voltage VPP10.9 – 1.95 V

VPP In-factory Programming Voltage VPP211.4 – 12.6 V

Block Erase Cycling (VPP = VPP1)– – 100,000 Cycles

Block Erase Cycling (VPP = VPP2)––1,000Cycles

Time for VPP at VPP2tPPH – – 100 Hours

Table 8: Capacitance

TA = +25°C; f = 1 MHz

PARAMETER/CONDITION SYMBOL TY P MAX UNITS

Input Capacitance CIN TBD TBD pF

Output Capacitance COUT TBD TBD pF

128Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

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Table 9: DC Characteristics

Notes appear on following page; all currents are in RMS unless otherwise noted

PARAMETER SYM MIN

W18/W30

UNITS NOTESTYP MAX

Input Low Voltage VIL 00.4V1

Input High Voltage VIH VCCQ – 0.4 VCCQV 1

Output Low Voltage

IOL = 100µA VOL 0.1 V

Output High Voltage

IOH = -100µA VOH VCCQ – 0.1 V

VPP Lockout Voltage F_VPPLK 0.4 V

VCC Lock F_VLKO 1.0 V

VccQ Lock F_VILKOQ TBD V

Input Load Current F_ILI ±1 µA

Output Leakage Current F_ILO ±1 µA

VCC Standby Current

with 32Mb PSRAM

with 64Mb PSRAM

ICCS 140

150

µA

Asynchronous Read Current F_ICCR 24mA

Page Read Current F_ICCR 36mA

Vcc Burst Read Current

4-word Burst Read Current @ 54 MHz

4-word Burst Read Current @ 66 MHz

F_ICCR 3

mA 2, 3, 5

Vcc Burst Read Current

8-word Burst Read Current @ 54 MHz

8-word Burst Read Current @ 66 MHz

F_ICCR 3

mA 2, 3, 5

Vcc Continuous Burst Read Current

Continous Burst Read Current @ 54 MHz

Continous Burst Read Current @ 66 MHz

F_ICCR 7

mA 2, 3, 5

F_VCC Program Current

F_VPP = F_VPP1, Program in Progress

F_VPP = F_VPP2, Program in Progress

F_ICCW 18

F_VCC Block Erase Current

F_VPP = F_VPP1, Block Erase in Progress

F_VPP = F_VPP2, Block Erase in Progress

F_ICCE 18

F_VCC Program Suspend Current F_ICCWS 725

µA 4

F_VCC Erase Suspend Current F_ICCES 725

µA 4

F_VCC Automatic Power Save Current F_ICCAPS 725

µA

F_VPP Standby Current

F_VPP Program Suspend Current

F_IPPS

F_IPPWS

0.2

5µA

F_VPP Erase Suspend Current

F_VPP Read Current

F_IPPES

F_IPPR

0.2

15 µA

128Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

09005aef80b10a55 Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE:

1. VIL may decrease to -0.4V and VIH may increase to VCCQ + 0.3V for durations not to exceed 20ns.

2. APS mode reduces ICC to approximately ICCS levels.

3. Test conditions: VCC = VCC (MAX), CE# = VIL, OE# = VIH. All other inputs = VIH or VIL.

4. ICCES and ICCWS values are valid when the device is deselected. Any READ operation performed while in suspend

mode will have an additional current draw of suspend current (ICCES or ICCWS).

5. Synchronous clock = 54 MHz/burst length = continuous is worst case for VCC burst read current.

6. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current

required to drive output capacitance expected in the actual system.

7. This device assumes a standby mode if the chip is disabled (CE# HIGH). It will also automatically go into a standby

mode whenever all input signals are quiescent (not toggling), regardless of the state of CE#, UB#, and LB#. In order

to achieve low standby current all inputs must be either VCC or VSS.

8. VIN = VCC or 0V Chip Enabled, IOUT = 0.

9. VIN = VCC or 0V Chip Enabled, IOUT = 0.

F_VPP Program Current

F_VPP = F_VPP1, Program in Progress

F_VPP = F_VPP2, Program in Progress

F_IPPW 0.05

0.10

F_VPP Erase Current

F_VPP = F_VPP1, Erase in Progress

F_VPP = F_VPP2, Erase in Progress

F_IPPE 0.05

0.10

Read Operating Current

Asynchronous Random READ

Asynchronous Page READ

Initial Access, Burst READ

Continuous Burst READ

PS_ICC1

(-60)

(-70)

mA 6, 7, 8

Write Operating Current PS_ICC2

(-60)

(-70)

mA 6, 7, 9

Table 9: DC Characteristics (continued)

Notes appear on following page; all currents are in RMS unless otherwise noted

PARAMETER SYM MIN

W18/W30

UNITS NOTESTYP MAX

128Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

09005aef80b10a55 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table 10: CFI

OFFSET DATA DESCRIPTION

2Ch

Manufacturer’s Identification Code (ManID)

Micron

89h Intel

44C6h/8864h

Device ID Code (DevID)

Top boot block device ID code (Micron / Intel)

44C7h/8865h Bottom boot block device ID code (Micron/Intel)

02 – 0F reserved Reserved

10, 11 0051, 0052 “QR”

12 0059 “Y”

13, 14 0003, 0000 Primary OEM command set

15, 16 0039, 0000 Address for primary extended table

17, 18 0000, 0000 Alternate OEM command set

19, 1A 0000, 0000 Address for OEM extended table

1B 0017 VCC MIN for Erase/Write; Bit 7–bit 4 volts in BCD; Bit 3–bit 0 100mV in BCD

1C 0019 VCC MAX for Erase/Write; Bit 7–bit 4 volts in BCD; Bit 3–bit 0 100mV in BCD

1D 00B4 VPP MIN for Erase/Write; Bit 7–bit 4 volts in hex; Bit 3–bit 0 100mV in BCD

1E 00C6 VPP MAX for Erase/Write; Bit 7–bit 4 Volts in hex; Bit 3–bit 0 100mV in BCD

1F 0004 Typical timeout for single byte/word program, 2nµs, 0000 = not supported

20 0000 Typical timeout for maximum size multiple byte/word program, 2nµs, 0000 = not supported

21 000A Typical timeout for individual block erase, 2ns, 0000 = not supported

22 0000 Typical timeout for full chip erase, 2ns, 0000 = not supported

23 0004 Maximum timeout for single byte/word program, 2nµs, 0000 = not supported

24 0000 Maximum timeout for maximum size multiple byte/word program, 2nµs, 0000 = not

supported

25 0002 Maximum timeout for individual block erase, 2ns, 0000 = not supported

26 0000 Maximum timeout for full chip erase, 2ns, 0000 = not supported

27 0017 Device size, 2n bytes

28 0001 Bus interface x8 = 0, x16 = 1, x32 = 2, x64 = 3

29 0000 Flash device interface description 0000 = async

2A, 2B 0000, 0000 Maximum number of bytes in multibyte program or page, 2n

2C 0002 Number of erase block regions within device (4K words and 32K words)

2D, 2E 007E, 0000 Top boot block device erase block region information 1

0007, 0000 Bottom boot block device erase block region information 1

2F, 30 0000, 0001 Top boot block device erase block region information 1

0020, 0000 Bottom boot block device erase block region information 1

31, 32 0007, 0000 Top boot block device erase block region information 2

007E, 0000 Bottom boot block device erase block region information 2

33, 34 0020, 0000 Top boot block device erase block region information 2

0000, 0001 Bottom boot block device erase block region information 2

35, 36 0000, 0000 Reserved for future erase block region information

37, 38 0000, 0000 Reserved for future erase block region information

39, 3A 0050, 0052 “PR”

3B 0049 “I”

3C 0031 Major version number, ASCII

128Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

09005aef80b10a55 Micron Technology, Inc., reserves the right to change products or specifications without notice.

3D 0033 Minor version number, ASCII

00E6

0003

0000

Optional Feature and Command Support

Bit 0 Chip erase supported no = 0

Bit 1 Suspend erase supported = yes = 1

Bit 2 Suspend program supported = yes = 1

Bit 3 Chip lock/unlock supported = no = 0

Bit 4 Queued erase supported = no = 0

Bit 5 Instant individual block locking supported = yes = 1

Bit 6 Protection bits supported = yes = 1

Bit 7 Page mode read supported = yes = 1

Bit 8 Synchronous read supported = no = 0

Bit 9 Simultaneous operation supported = yes = 1

42 0001 Program supported after erase suspend = yes

43, 44 0003, 0000 Bit 0 block lock status active = yes; Bit 1 block lock down active = yes

45 0018 VCC supply optimum, 00 = not supported, Bit 7–bit 4 volts in BCD; Bit 3–bit 0 100mV in BCD

46 00C0 VPP supply optimum, 00 = not supported, Bit 7–bit 4 volts in BCD; Bit 3–bit 0 100mV in BCD

47 0001 Number of protection register fields in JEDEC ID space

48, 49 0080, 0000 Lock bytes LOW address, lock bytes HIGH address

4A, 4B 0003, 0003 2n factory programmed bytes, 2n user programmable bytes

4C 0004 Page mode read capability

4D 0004 Number of synchronous mode read configuration fields that follow

4E 0001 Synchronous mode read capability configuration 1

4F 0002 Synchronous mode read capability configuration 2

50 0007 Synchronous mode read capability configuration 3

51 0000 Synchronous mode read capability configuration 4

52 Top: 0002 Number of device hardware partition regions within the device

Bot :0002

53 Top: 000F Number of identical partitions within the partition region

Bot: 0001

54 Top: 0000 Number of identical partitions within the partition region

Bot: 0000

55 Top: 0011 Number of identical partitions within the partition region

Bot: 0011

56 Top: 0000 Simultaneous PROGRAM/ERASE operations allowed in other partitions while a partition in

this region is in program mode

Bot: 0000

57 Top: 0000 Simultaneous PROGRAM/ERASE operations allowed in other partitions while a partition in

this region is in erase mode

Bot: 0000

58 Top: 0001 Types of erase block regions in this partition region

Bot: 0002

59 Top: 0007 Partition region 1 erase block type 1 information

Bot: 0007

5A Top: 0000 Partition region 1 erase block type 1 information

Bot: 0000

5B Top: 0000 Partition region 1 erase block type 1 information

Bot: 0020

5C Top: 0001 Partition region 1 erase block type 1 information

Bot: 0000

Table 10: CFI (continued)

OFFSET DATA DESCRIPTION

128Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

09005aef80b10a55 Micron Technology, Inc., reserves the right to change products or specifications without notice.

5D Top: 0064 Partition 1 (erase block type 1)

Bot: 0064

5E Top: 0000 Partition 1 (erase block type 1)

Bot: 0000

5F Top: 0001 Partition 1 (erase block type 1) bits per cell; internal ECC

Bot: 0001

60 Top: 0003 Partition 1 (erase block type 1) page mode and synchronous mode capabilities

Bot: 0003

Bot: 61

Partition region 1 erase block type 2 information

Bot: 0006

Bot: 62

Partition region 1 erase block type 2 information

Bot: 0000

Bot: 63

Partition region 1 erase block type 2 information

Bot: 0000

Bot: 64

Partition region 1 erase block type 2 information

Bot: 0001

Bot: 65

Partition region 1 (erase block type 2)

Bot: 0064

Bot: 66

Partition region 1 (erase block type 2)

Bot: 0000

Bot: 67

Partition region 1 (erase block type 2) bits per cell

Bot: 0001

Bot: 68

Partition region 1 (erase block type 2) page mode and synchronous mode capabilities

Bot: 0003

Top: 61 Top: 0001 Number of identical partitions within the partition region

Bot: 69 Bot: 000F

Top: 62 Top: 0000 Number of identical partitions within the partition region

Bot: 6A Bot: 0000

Top: 63 Top: 0011 Number of PROGRAM/ERASE operations allowed in a partition

Bot: 6B Bot: 0011

Top: 64 Top: 0000 Simultaneous PROGRAM/ERASE operations allowed in other partitions while a partition in

this region is in program mode

Bot: 6C Bot: 0000

Top: 65 Top: 0000 Simultaneous PROGRAM/ERASE operations allowed in other partitions while a partition in

this region is in erase mode

Bot: 6D Bot: 0000

Top: 66 Top: 0002 Types of erase block regions in this partition region

Bot: 6E Bot: 0001

Top: 67 Top: 0006 Partition region 2 erase block type 1 information

Bot: 6F Bot: 0007

Top: 68 Top: 0000 Partition region 2 erase block type 1 information

Bot: 70 Bot: 0000

Top: 69 Top: 0000 Partition region 2 erase block type 1 information

Bot: 71 Bot: 0000

Top: 6A Top: 0001 Partition region 2 erase block type 1 information

Bot: 72 Bot: 0001

Table 10: CFI (continued)

OFFSET DATA DESCRIPTION

128Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

09005aef80b10a55 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Top: 6B Top: 0064 Partition 2 (erase block type 1)

Bot: 73 Bot: 0064

Top: 6C Top: 0000 Partition 2 (erase block type 1)

Bot: 74 Bot: 0000

Top: 6D Top: 0001 Partition 2 (erase block type 1) bits per cell

Bot: 75 Bot: 0001

Top: 6E Top: 0003 Partition 2 (erase block type 1) page mode and synchronous mode capabilities

Bot: 76 Bot: 0003

Top: 6F Top: 0007 Partition region 2 erase block type 2 information

Top: 70 Top: 0000 Partition region 2 erase block type 2 information

Top: 71 Top: 0020 Partition region 2 erase block type 2 information

Top: 72 Top: 0000 Partition region 2 erase block type 2 information

Top: 73 Top: 0064 Partition 2 (erase block type 2)

Top: 74 Top: 0000 Partition 2 (erase block type 2)

Top: 75 Top: 0001 Partition 2 (erase block type 2) bits per cell

Top: 76 Top: 0003 Partition 2 (erase block type 2) page mode and synchronous mode capabilities

77 Reserved

78 32Mb: 0020 PSRAM Density

64Mb: 0040

79–7F Reserved

Table 10: CFI (continued)

OFFSET DATA DESCRIPTION

128Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

09005aef80b10a55 Micron Technology, Inc., reserves the right to change products or specifications without notice..

MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.

CellularRAM is a trademark of Micron Technology, Inc., inside the U.S. and a trademark of Infineon Technologies outside the U.S.

All other trademarks are the property of their respective owners.

Figure 5: 77-Ball FBGA

NOTE:

1. All dimensions in millimeters.

Data Sheet Designation

Advance: This data sheet contains initial descriptions of products still under development.

For additional documentation concerning Flash and CellularRAM features, functional descriptions, program-

ming, and timing, please refer to the MT28F644W18/W30 data sheet at www.micron.com/flash and the

MT45W2MW16PFA and MT45W4MW16PFA data sheets at

http://www.micron.com/cellularram.

BALL A1 ID

1.025 ±0.075

SEATING PLANE

0.10 C

1.40 MAX

BALL A8

BALL A1 ID

0.80

TYP

0.80 TYP

2.80 ±0.05

5.60

BALL A1

8.00 ±0.10

4.00 ±0.05

SOLDER BALL DIAMETER

REFERS TO POST REFLOW

CONDITION. THE PRE-REFLOW

DIAMETER IS Ø 0.35mm ON A

0.30mm SMD BALL PAD.

77X ∅0.35

SOLDER BALL MATERIAL:

EUTECTIC 62% Sn, 36% Pb, 2% Ag

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

7.20

3.60 ±0.05

5.00 ±0.05

10.00 ±0.10

128Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

09005aef80b10a55 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Revision History

Rev B, Advance.................................................................................................................................................................7/03

• Included W30 specification

• Added Intel ManID varient

• Updated mechanical information

• Table 10 (CFI) clarification

Original document, Rev. A ..............................................................................................................................................5/03