www.DataSheet4U.com MICROCOMPUTER MN101C00 MN101C115/117 LSI User's Manual Pub. No. 21411-011E www.DataSheet4U.com PanaXSeries is a trademark of Matsushita Electric Industrial Co., Ltd. The other corporation names,logotype and product names written in this book are trademarks or registered trademarks of their corresponding corporations. Request for your special attention and precautions in using the technical information and semiconductors described in this book www.DataSheet4U.com (1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this book and controlled under the "Foreign Exchange and Foreign Trade Control Law" is to be exported or taken out of Japan. (2) The contents of this book are subject to change without notice in matters of improved function. When finalizing your design,therefore,ask for the most up-to-date version in advance in order to check for any changes. (3) We are not liable for any damage arising out of the use of the contents of this book, or for any infringement of patents or any other rights owned by a third party. (4) No part of this book may be reprinted or reproduced by any means without written permission from our company. (5) This book deals with standard specifications. Ask for the latest individual Product Standards or Specifications in advance for more detailed information required for your design,purchasing and applications. If you have any inquiries or questions about this book or our semiconductors, please contact one of our sales offices listed at the back of this book or Matsushita Electronics Corporation's Sales Department. How to Read This Manual The MN101C11x incorporates more than one ROM/RAM to meet a variety of applications. An EPROM version as well as a Mask ROM version is available so users can write a program by themselves. ROM 8K RAM MN101C115*1 256 16K MN101C117 512 16K MN101CP117 512 Under plannin *1 : Unit Byte ?@@?e ?@@?e ?@@?e ?@@?e ?? ?? ?? ?? ?? ?? ? ?? ?? ?? ?? ?? ?? ?? ? ?? ?? ?? ?? ?? ?? ?? ? ?? ?? ?? ?? ?? ?? ?? ? ?? ?? ?? ?? ?? ?? ?? ? ?? ?? ?? ?? ?? ?? ?? ? ?? ?? ?? ? ??? ?? ?? ?W2@@6T2@??? W&(?'@@<e? 7@H?N@@?e? @@e?@@?e? 3@L?J@5?e? N@)?&(Y?e? J@@@0Yf? 7@h? 3@h? S@@@@@6Xe? ?W.R4@@@@1e? ?7H?f@@e? ?@L?f@5e? ?@)Ke?C(Ye? ?3@@@@@(Y?e? ?V4@@@0Yf? ? ?? ?? ?? ?? ?? ?? ? ?? ?? ?? ?? ?? ?? ?? ? ?? www.DataSheet4U.com Organization In this LSI manual, the MN101C117 functions are presented in the following order: overview, CPU basic functions, port functions, timer functions, serial functions, and other peripheral hardware functions. How to Read This Manual-1 Manual Configuration Each section of this manual consists of a title, summary, main text, supplemental information, precautions and warnings. The layout and definition of each section are shown below. Chapter 4 Timer Functions Subtitle Sub-subtitle The smallest block in this manual. 4-3 16-bit Timer Operation (timer 4) Summary Introduction to the section. 4-3-1 Overview Timer 4 is a 16-bit programmable counter that can be used as an event counter. A signal with frequency of 1/2 of the timer 4 overflow signal can be output from the TM4IO pin. An input capture function and added pulse PWM output function can also be used. Main text Timer Operation Settings for timer operation are listed below. (1) (2) (3) Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" so that the count operation of timer 4 is stopped. Set the TM4CK2~0 flags of the TM4MD register to select fosc, fs/4, or fs/16 as the clock source. Set the TM4PWM flag of the TM4MD register to "0" so that 16-bit timer operation is selected. www.DataSheet4U.com Clock When servicing an interrupt, reset the timer 4 interrupt request flag before operating timer 4. During a count operation, be careful if the value set in TM4OCH and TM4OCL is smaller than the value of binary counter 4, since the count-up operation will continue until overflow occurs. Supplementary information Supplementary information for the main text. An explanation of terminology is also included. TM4EN Write to registers TM4OCH, TM4OCL Binary counter 4 Key information Important information from the text. 04 05 06 07 08 09 00 Precautions and warnings Figure 4-3-1 Binary Counter 4 (TM4BC) Count Timing If the TM4EN flag of the TM4MD register is changed simultaneously with other bits, the switching operation may cause binary counter 4 to be incremented. Precautions are listed in case of lost functionality or damage. Be sure to read. If the value of TM4OCH and TM4OCL registers is overwritten while timer 4 has stopped counting, binary counter 4 will be reset to X'0000'. 16-bit Timer Operation (timer 4) 83 How to Read This Manual-2 www.DataSheet4U.com Finding Desired Information This manual provides four methods for finding desired information quickly and easily. (1) (2) (3) (4) Consult the index at the front of the manual to locate the beginning of each section. Consult the table of contents at the front of the manual to locate desired titles. Consult the list of figures at the front of the manual to locate illustrations and charts by title name. Chapter names are located at the top outer corner of each page, and section titles are located at the bottom outer corner of each page. Related Manuals The following manuals are also available from Panasonic as part of the MN101C00 series. MN101C00 Series LSI Manual <Device Hardware Description> MN101C00 Series Command Manual <Command Descriptions> MN101C00 Series Cross Assembler User's Manual <Assembler Syntax and Entry Methods> MN101C00 Series C Compiler User's Manual Operation <C Compiler Installation, Startup, Option Descriptions> MN101C00 Series C Compiler User's Manual Language <C Language Syntax Description> MN101C00 Series C Compiler User's Manual Library <C Compiler Standard Library Description> MN101C00 Series C Source Code Debugger User's Manual <C Source Code Debugger Usage Methods> MN101C00 Series PanaX Series Installation Manual <Installation of C Compiler, Cross Assembler, C Source Code Debugger; In-circuit Emulator> Where to Send Inquires Please send any inquires or questions concerning the contents of this manual to the Panasonic semiconductor design center closest to you. A list of addresses is provided at the end of this manual for your convenience. How to Read This Manual-3 ?? @@@?he O26Xe @@Y?e?O26X?e @@@@@@@@@@@@@@@@@@@@@)e ?@@@@@@@@@@@@@@@@@@@)?e ?I'Xg@Xh @Khf?O26X?e N)X?e?J@@h @@@@@@@@@@@@@@@@@@)?e ?@)KeO&Y?eO26Xe @@ @@H?e @@@@@@@@@@@@@@@@@@@@@)e @@ @@f @@@@@@@@@@@@@@@@@@f @@@@@@@@@@@@@@g @@ @@he@@g @@f?@@@e@@@?g @@he@@g @@f?@@He@@Y?O)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @@he@@g @@f?@@?e@@h @@he@@g @@f?@@?e@@eO)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @0M?e@@e?I4@g ?J@5f?@@?e@@h @@gO26Xe ?7@Hf?@5?e@@h @@@@@@@@@@@@@@@@@@@@@)e ?@5?'@@@@@H?e@@eO26Xe @@hf ?@H?V+MW@5f@@@@@@@)e @@hf J5fW&(Yf@@h @@hf .Ye?O&0Y?f@@h @@hf @0M?g@@h W&g O2@@6Kf O2@@6Kf O2@@6Kf ?O2@@@e ?W&@g ?@@(MI'@@?e ?@@(MI'@@?e ?@@(MI'@@?e ?W2@0Mf W&@@g J@(YeV'@Le J@(YeV'@Le J@(YeV'@Le W&(Mg .Y@@g 7@H?e?N@1e 7@H?e?N@1e 7@H?e?N@1e ?W&(Y?g @@g @@g@@e @@g@@e @@g@@e ?7@Hh @@g @@g@@e @@g@@e @@g@@e J@@=h @@g 7@S@@@6Kf @@g 3@L?e?J@@e N@)XeW&@@e 3@L?e?J@@e N@)XeW&@@e 3@L?e?J@@e N@)XeW&@@e @@(M?I'@@?e @@g @@H?eV'@Le @@g ?@@)KO&@@@e I4@@0Y@5e ?@@)KO&@@@e I4@@0Y@5e ?@@)KO&@@@e I4@@0Y@5e @@f?N@1e @@g ?J@He ?J@He ?J@He @@g@@e @@g W&5?e W&5?e W&5?e @@g@@e @@g ?W&(Y?e ?W&(Y?e ?W&(Y?e 3@L?e?J@5e @@g O&(Yf O&(Yf O&(Yf N@)XeW&@He ?@@?e @@g O2@0Y?f O2@0Y?f O2@0Y?f ?@@?e ?@@)KO&@@?e ?@@?e @@@@@@f ?@@0M?g ?@@0M?g ?@@0M?g ?@@?e I4@@0Mf W&g W2@@6Xf ?W&@g ?W&(MI')X?e W&@@g ?7@HeN@1?e .Y@@g J@5?e?3@Le @@g 7@H?e?N@1e @@g @@g@@e @@g @@g @@g@@e @@g@@e @@g @@g @@g@@e @@g@@e @@g @@g@@e @@g @@g 3@L?e?J@5e N@1?e?7@He @@g ?3@LeJ@5?e @@g ?V')KO&(Y?e @@@@@@f V4@@0Yf ?? ? ?? ? W&g ?O2@@@e W&f ? W2@@@@@(e ?W&@g ?W2@0Mf ?W&@f ? 7@@@@@0Ye W&@@g W&(Mg ?J@?h W&@@f ? .Y@@g ?W&(Y?g ?75?h ?W&@@@f ? @@g ?7@Hh J@Y?h W&(Y@@f ? @@g J@@=h ?@@?e? @@@@@6K?f ?W&(Y?@@f @@g W&(Ye@@f @@g 7@S@@@6Kf @@(M?I'@@?e ?@@?e?? I4@@@@f I'@@L?e?W&(Y?e@@f @@g ? ?V'@1?e @@g @@H?eV'@Le @@f?N@1e N@@?e?7@Yf@@f ?@@@@@@@@@@@e ?? @@g @@g@@e ?@@?e?@@@@@@@@@@@e @@g ?@5?e @@f ?? @@g @@g@@e 3@L?e?J@5e J@H?e @@f @@g N@)XeW&@He ?@6Xe?W&5f @@f ? @@g ?@@)KO&@@?e ?@@?e? ?3@)K?O&0Yf @@f @@@@@@f I4@@0Mf ?@@?e? ?V4@@@0Mg @@f ? ? ? ? ? ? ? W26Xf @@6Khe'6X?e 7<B1f ?I'@@?f?'6XV'1?e 3=C5f V4@?f?V'1?V'?e W2@@6XfV40Yf V'g ?W&(MI')X?he W&(YeV')Xhe ?@@6K? ?W&(Y?e?V')X?h I'@@hfW.f W&(YgV')Xh ?@K?f?O2@@@@@@@@@1?e ?O26X?e ?V4@he?W&Hf @?&@H?g?V')X?g W&5?f 3@@5heV')Xg ?W&(Y?f V40Yhe?V')K?f ?3@@@@@@@@0Mg?I@?e ?V40M? W&(Yg V'@6X?e ?W&(Y?g ?V'@)Xe O&(Yh V'@1e W2@(Y?h ?V4@e ?O&@0Yhe ?O2@(Mhf ?@KO2@@0Y?hf ?3@@@0M?hg ?V40M? W&g ?W&@g W&@@g .Y@@g @@g @@g @@g @@g @@g @@g @@g @@g @@g @@g @@g @@@@@@f Contents www.DataSheet4U.com Chapter 1 Overview Chapter 2 Basic CPU Functions Chapter 3 Port Functions Chapter 4 Timer Functions Chapter 5 Serial Functions Chapter 6 A/D Conversion Functions Chapter 7 AC Zero-Cross Circuit/Noise Filter Appendices 0 1 2 3 4 5 6 7 8 www.DataSheet4U.com ?? @@@?he O26Xe @@Y?e?O26X?e @@@@@@@@@@@@@@@@@@@@@)e ?@@@@@@@@@@@@@@@@@@@)?e ?I'Xg@Xh @Khf?O26X?e N)X?e?J@@h @@@@@@@@@@@@@@@@@@)?e ?@)KeO&Y?eO26Xe @@ @@H?e @@@@@@@@@@@@@@@@@@@@@)e @@ @@f @@@@@@@@@@@@@@@@@@f @@@@@@@@@@@@@@g @@ @@he@@g @@f?@@@e@@@?g @@he@@g @@f?@@He@@Y?O)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @@he@@g @@f?@@?e@@h @@he@@g @@f?@@?e@@eO)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @0M?e@@e?I4@g ?J@5f?@@?e@@h @@gO26Xe ?7@Hf?@5?e@@h @@@@@@@@@@@@@@@@@@@@@)e ?@5?'@@@@@H?e@@eO26Xe @@hf ?@H?V+MW@5f@@@@@@@)e @@hf J5fW&(Yf@@h @@hf .Ye?O&0Y?f@@h @@hf @0M?g@@h W&g O2@@6Kf O2@@6Kf O2@@6Kf ?O2@@@e ?W&@g ?@@(MI'@@?e ?@@(MI'@@?e ?@@(MI'@@?e ?W2@0Mf W&@@g J@(YeV'@Le J@(YeV'@Le J@(YeV'@Le W&(Mg .Y@@g 7@H?e?N@1e 7@H?e?N@1e 7@H?e?N@1e ?W&(Y?g @@g @@g@@e @@g@@e @@g@@e ?7@Hh @@g @@g@@e @@g@@e @@g@@e J@@=h @@g 7@S@@@6Kf @@g 3@L?e?J@@e N@)XeW&@@e 3@L?e?J@@e N@)XeW&@@e 3@L?e?J@@e N@)XeW&@@e @@(M?I'@@?e @@g @@H?eV'@Le @@g ?@@)KO&@@@e I4@@0Y@5e ?@@)KO&@@@e I4@@0Y@5e ?@@)KO&@@@e I4@@0Y@5e @@f?N@1e @@g ?J@He ?J@He ?J@He @@g@@e @@g W&5?e W&5?e W&5?e @@g@@e @@g ?W&(Y?e ?W&(Y?e ?W&(Y?e 3@L?e?J@5e @@g O&(Yf O&(Yf O&(Yf N@)XeW&@He ?@@?e @@g O2@0Y?f O2@0Y?f O2@0Y?f ?@@?e ?@@)KO&@@?e ?@@?e @@@@@@f ?@@0M?g ?@@0M?g ?@@0M?g ?@@?e I4@@0Mf W&g W2@@6Xf ?W&@g ?W&(MI')X?e W&@@g ?7@HeN@1?e .Y@@g J@5?e?3@Le @@g 7@H?e?N@1e @@g @@g@@e @@g @@g @@g@@e @@g@@e @@g @@g @@g@@e @@g@@e @@g @@g@@e @@g @@g 3@L?e?J@5e N@1?e?7@He @@g ?3@LeJ@5?e @@g ?V')KO&(Y?e @@@@@@f V4@@0Yf ?? ? ?? ? W&g ?O2@@@e W&f ? W2@@@@@(e ?W&@g ?W2@0Mf ?W&@f ? 7@@@@@0Ye W&@@g W&(Mg ?J@?h W&@@f ? .Y@@g ?W&(Y?g ?75?h ?W&@@@f ? @@g ?7@Hh J@Y?h W&(Y@@f ? @@g J@@=h ?@@?e? @@@@@6K?f ?W&(Y?@@f @@g W&(Ye@@f @@g 7@S@@@6Kf @@(M?I'@@?e ?@@?e?? I4@@@@f I'@@L?e?W&(Y?e@@f @@g ? ?V'@1?e @@g @@H?eV'@Le @@f?N@1e N@@?e?7@Yf@@f ?@@@@@@@@@@@e ?? @@g @@g@@e ?@@?e?@@@@@@@@@@@e @@g ?@5?e @@f ?? @@g @@g@@e 3@L?e?J@5e J@H?e @@f @@g N@)XeW&@He ?@6Xe?W&5f @@f ? @@g ?@@)KO&@@?e ?@@?e? ?3@)K?O&0Yf @@f @@@@@@f I4@@0Mf ?@@?e? ?V4@@@0Mg @@f ? ? ? ? ? ? ? W26Xf @@6Khe'6X?e 7<B1f ?I'@@?f?'6XV'1?e 3=C5f V4@?f?V'1?V'?e W2@@6XfV40Yf V'g ?W&(MI')X?he W&(YeV')Xhe ?@@6K? ?W&(Y?e?V')X?h I'@@hfW.f W&(YgV')Xh ?@K?f?O2@@@@@@@@@1?e ?O26X?e ?V4@he?W&Hf @?&@H?g?V')X?g W&5?f 3@@5heV')Xg ?W&(Y?f V40Yhe?V')K?f ?3@@@@@@@@0Mg?I@?e ?V40M? W&(Yg V'@6X?e ?W&(Y?g ?V'@)Xe O&(Yh V'@1e W2@(Y?h ?V4@e ?O&@0Yhe ?O2@(Mhf ?@KO2@@0Y?hf ?3@@@0M?hg ?V40M? ?O2@@6X?f @@@@@@)Xf ?J(MeI'@1f ?.Y?e?N@@f @@f @@f ?J@5f ?7@Hf J@5?f 7(Y?f ?J(Yg W.Y?g ?W.Yh W&Y?fO.e ?W&@@@@@@@(Ye ?&@@@@@@@0Y?e Contents www.DataSheet4U.com 0 Contents Chapter 1 Overview 1-1 Product Overview...........................................................................................................2 1-1-1 Overview ..........................................................................................................2 1-1-2 Product Summary .............................................................................................2 1-2 Hardware Functions .......................................................................................................3 1-3 Pins .................................................................................................................................5 1-3-1 Pin Diagram......................................................................................................5 1-3-2 Pin Function Summary .....................................................................................8 1-4 Overview of Functions .................................................................................................12 1-4-1 Block Diagram................................................................................................12 1-5 Electrical Characteristics..............................................................................................13 www.DataSheet4U.com 1-5-1 Absolute Maximum Ratings...........................................................................13 1-5-2 Operating Conditions......................................................................................14 1-5-3 DC Characteristics .........................................................................................17 1-5-4 A/D Converter Characteristics........................................................................21 1-6 Option...........................................................................................................................22 1-6-1 ROM Option ...................................................................................................22 1-6-2 Option Check List...........................................................................................23 1-7 Outline Drawings .........................................................................................................24 Chapter 2 Basic CPU Functions 2-1 Overview ......................................................................................................................28 2-2 Address Space 2-2-1 Memory Configuration ...................................................................................28 2-2-2 Special Function Registers .............................................................................28 2-3 Bus Interface ................................................................................................................29 2-3-1 Overview .......................................................................................................30 2-3-2 Control Register..............................................................................................30 2-4 Interrupts ......................................................................................................................31 2-4-1 Accepting and Returning from Interrupts.......................................................31 2-4-2 Interrupt Sources and Vector Addresses .........................................................33 2-4-3 Interrupt Control Registers .............................................................................34 2-5 Reset .............................................................................................................................36 <Contents 1> www.DataSheet4U.com Chapter 3 Port Functions 3-1 Overview ......................................................................................................................38 3-2 Port Control Registers ..................................................................................................41 3-2-1 Overview ........................................................................................................41 3-2-2 I/O Port Control Registers ..............................................................................45 3-3 I/O Port Configuration and Functions..........................................................................47 Chapter 4 Timer Functions 4-1 Overview ......................................................................................................................56 4-2 8-bit Timer Operation (timers 2, 3) ..............................................................................62 4-2-1 Overview ........................................................................................................62 4-2-2 Operation ........................................................................................................63 4-3 16-bit Timer Operation (timer 4)..................................................................................69 4-3-1 Overview ........................................................................................................69 4-3-2 Operation ........................................................................................................69 4-4 8-bit Timer Operation (timer 5)....................................................................................76 4-4-1 Overview ........................................................................................................76 4-4-2 Operation ........................................................................................................76 4-5 Time Base Operation....................................................................................................77 4-5-1 Overview ........................................................................................................77 4-5-2 Operation ........................................................................................................77 4-6 Watchdog Timer Operation ..........................................................................................78 4-6-1 Overview ........................................................................................................78 4-6-2 Setup and Operation .......................................................................................78 4-7 Remote Control Output Operation ...............................................................................79 4-7-1 Overview ........................................................................................................79 4-7-2 Setup and Operation .......................................................................................79 4-8 Buzzer Output ..............................................................................................................80 4-8-1 Buzzer Output Setup and Operation ...............................................................80 4-9 Timer Function Control Registers................................................................................81 4-9-1 Overview ........................................................................................................81 4-9-2 Programmable Timer/Counters ......................................................................82 4-9-3 Timer Mode Registers ....................................................................................85 4-9-4 Timer Control Registers .................................................................................89 <Contents 2> Chapter 5 Serial Functions 5-1 Overview ......................................................................................................................92 5-2 Synchronous Serial Interface .......................................................................................94 5-2-1 Overview ........................................................................................................94 5-2-2 Setup and Operation .......................................................................................94 5-2-3 Serial Interface Transfer Timing.....................................................................99 5-3 Half-duplex UART Serial Interface ...........................................................................101 5-3-1 Overview ......................................................................................................101 5-3-2 Setup and Operation .....................................................................................101 5-3-3 How to Use the Baud Rate Timer.................................................................105 5-4 Serial Interface Control Registers ..............................................................................106 5-4-1 Overview ......................................................................................................106 5-4-2 Transmit/Receive Shift Registers, Receive Data Buffer ..............................107 5-4-3 Serial Interface Mode Registers ...................................................................108 5-4-4 Serial Interface Control Register ..................................................................112 Chapter 6 A/D Conversion Functions www.DataSheet4U.com 6-1 Overview ....................................................................................................................114 6-2 A/D Conversion..........................................................................................................115 6-3 A/D Converter Control Registers ...............................................................................117 6-3-1 Overview.......................................................................................................117 6-3-2 A/D Control Register (ANCTR)...................................................................118 6-3-3 A/D Buffers (ANBUF) .................................................................................120 Chapter 7 AC Zero-Cross Circuit/Noise Filter 7-1 Overview ....................................................................................................................122 7-2 AC Zero-Cross Circuit Operation ..............................................................................123 7-2-1 Setup and Operation .....................................................................................123 7-3 Noise Filter.................................................................................................................124 7-3-1 Overview ......................................................................................................124 7-3-2 Example Input and Output Waveforms for Noise Filter...............................125 7-4 AC Zero-Cross Control Register................................................................................126 <Contents 3> 7-4-1 Overview ......................................................................................................126 7-4-2 Noise Filter Control Register (NFCTR) .......................................................127 www.DataSheet4U.com Appendices 8-1 EPROM Versions .......................................................................................................130 8-1-1 Overview ......................................................................................................130 8-1-2 Cautions on Use............................................................................................131 8-1-3 Erasing Written Data in Windowed Packages ..............................................132 (PX-AP101C11-SDC, PX-AP101C11-FBC) 8-1-4 Characteristics of EPROM Versions.............................................................133 8-1-5 Writing to Internal EPROM..........................................................................134 8-1-6 Cautions on Handling the ROM Writer........................................................136 8-1-7 Option Bit .....................................................................................................137 8-1-8 Writing Adapter Connection.........................................................................138 8-2 Instruction Sets...........................................................................................................141 8-3 Instruction Maps.........................................................................................................147 8-4 Special Function Registers .........................................................................................149 <Contents 4> www.DataSheet4U.com ?? @@@?he O26Xe @@Y?e?O26X?e @@@@@@@@@@@@@@@@@@@@@)e ?@@@@@@@@@@@@@@@@@@@)?e ?I'Xg@Xh @Khf?O26X?e N)X?e?J@@h @@@@@@@@@@@@@@@@@@)?e ?@)KeO&Y?eO26Xe @@ @@H?e @@@@@@@@@@@@@@@@@@@@@)e @@ @@f @@@@@@@@@@@@@@@@@@f @@@@@@@@@@@@@@g @@ @@he@@g @@f?@@@e@@@?g @@he@@g @@f?@@He@@Y?O)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @@he@@g @@f?@@?e@@h @@he@@g @@f?@@?e@@eO)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @0M?e@@e?I4@g ?J@5f?@@?e@@h @@gO26Xe ?7@Hf?@5?e@@h @@@@@@@@@@@@@@@@@@@@@)e ?@5?'@@@@@H?e@@eO26Xe @@hf ?@H?V+MW@5f@@@@@@@)e @@hf J5fW&(Yf@@h @@hf .Ye?O&0Y?f@@h @@hf @0M?g@@h W&g O2@@6Kf O2@@6Kf O2@@6Kf ?O2@@@e ?W&@g ?@@(MI'@@?e ?@@(MI'@@?e ?@@(MI'@@?e ?W2@0Mf W&@@g J@(YeV'@Le J@(YeV'@Le J@(YeV'@Le W&(Mg .Y@@g 7@H?e?N@1e 7@H?e?N@1e 7@H?e?N@1e ?W&(Y?g @@g @@g@@e @@g@@e @@g@@e ?7@Hh @@g @@g@@e @@g@@e @@g@@e J@@=h @@g 7@S@@@6Kf @@g 3@L?e?J@@e N@)XeW&@@e 3@L?e?J@@e N@)XeW&@@e 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W&g ?W&@g W&@@g .Y@@g @@g @@g @@g @@g @@g @@g @@g @@g @@g @@g @@g @@@@@@f Chapter 1 1 Overview www.DataSheet4U.com 1 Chapter 1 Overview 1-1 Product Overview 1-1-1 Overview The MN101C00 series of 8-bit single-chip microcomputers incorporate several types of peripheral functions. This chip series is well suited for VCR, MD, TV, CD, LD, printer, telephone, home automation, pager, air conditioner, PPC, remote control, fax machine, musical instrument, and other applications. The MN101C117 has an internal 16 KB of ROM and 512 bytes of RAM. Peripheral functions include four sets of timers, one set of serial interfaces, an A/D converter, and remote control output. The configuration of this microcomputer is well suited for applications as a system controller in a VCR selection timer, CD player, MD, or portable terminal. With two oscillation systems (max. 20 MHz/32 kHz) contained on the chip of 48-pin QFP package, the system clock can be switched between high and low speed. When the oscillation source (fosc) is 8 MHz, a machine cycle lasts for 250 ns. When fosc is 20 MHz, a machine cycle is 100 ns. The package are available with three types of 42-pin SDIP, 44-pin QFP and 48-pin QFH. www.DataSheet4U.com 1-1-2 Product Summary This manual describes the following models of the MN101C11 series. These products have identical functions. Table 1-1-1 Product Summary Model MN101C115*1 MN101C117 MN101CP117 1 Under development 2 Product Overview ROM Size 8 KB 16 KB 16 KB RAM Size 256 bytes 512 bytes 512 bytes Classification Mask ROM version Mask ROM version EPROM version www.DataSheet4U.com Chapter 1 Overview 1-2 Hardware Functions ROM/RAM Size: <Single chip mode> Internal ROM2 16,384x8-bit*3 Internal RAM2 512x8-bit Machine Cycles: High speed mode 0.10s/20MHz (4.5V to 5.5V) 0.25s/8MHz(2.7V to 5.5V) 1.00s/2MHz(2.0V to 5.5V) Low speed mode 125s/32KHz(2.0V to 5.5V)*4 Interrupts: 12 interrupts(11 interrupts except for 48-pin QFH package) <External interrupts> The active edge can be selected for all external interrupts IRQ0 External interrupt (can be connected to noise filter) 2 Differs depending upon the model. [ 1-1-2 "Product Summary"] *3 Bit 8 of the last address for the built-in ROM of MN101C11X is an optional bit; therefore, this cannot be used as an ordinary ROM. *4 Exclusive for a 48-pin QFH product. IRQ1 External interrupt (can determine zero crossings, can be connected to noise filter) IRQ2 External interrupt IRQ3 External interrupt *4 <Timer interrupts> TM2IRQ Timer 2 (8-bit timer) TM3IRQ Timer 3 (8-bit timer) TM4IRQ Timer 4 (16-bit timer) TM5IRQ Timer 5 (8-bit timer) TBIRQ Clock timer interrupts <Serial communication interrupt> SC0IRQ Serial 0 (synchronous + simple UART <A/D conversion complete interrupt> ADIRQ A/D conversion complete <Watchdog timer interrupt> NMI Overflow of watchdog timer Timer/Counters:five timers, all can generate interrupts Timer 2 8-bit timer Square wave output, 8-bit PWM output are possible, Clock source: fs, fs/4, fx*4, TM2IO pin input Timer 3 8-bit timer Square wave output, synchronous serial/UART baud rate timer Clock source: fosc, fs/4, fs/16, TM3IO pin input Remote control carrier can be generated. Hardware Functions 3 Chapter 1 Overview Timers 2 and 3 can be cascaded. Timer 4 16-bit timer Square wave output, 16-bit PWM output are possible. Clock source: fosc, fs/4, fs/16, TM4IO pin input Input capture function Time base timer Clock source: fosc, fs/4, fx*4, fx/213*4 or fosc/213 XIOat 32kHz, can be set to measure one minute intervals*4 Can operate independently as timer 5 (8-bit timer). Watchdog timer Selected by the mask option as fs/216, fs/218, or fs/220 Remote control Based on the timer output, a remote control carrier with duty ratio carrier output: of 1/2, 1/3 can be output. Buzzer output: Output frequency can be selected from fs/29, fs/210, fs/211 or fs/212. Serial interface: Synchronous/ Simple UART (half-duplex) Transfer clock: fs/2, fs/4, fs/16, 1/2 of timer 3 output When using timer 3, the transfer rates for a 12MHz oscillation are 19200/9600/4800/2400/1200/300 bps. MSB or LSB can be selected as the first bit for transfer. An arbitrary transfer size of 1 to 8 bits can be selected. www.DataSheet4U.com A/D converter: 10 bits x 8 channels LED driver function:8 pins Ports: 5 26 ports for 44-QFP 27 ports for 48-QFH 6 12 ports for 48-QFH 7 4 ports for 48-QFH I/O ports 25 ports (8 have dual functions)*5 LED (large current) driver ports: 8 ports (push-pull configuration) Input ports 11 ports (all have dual functions) *6 Number of pins with dual function for external interrupts: 3*7 (One of which can also be used for zero-cross input.) Number of pins with dual function for A/D input: 8 Operation mode input pin: 1 Reset input pin: 1 Operation modes: NORMAL mode SLOW mode*4 HALT mode STOP mode and switches operating clock*4 Package: 4 Hardware Functions 42-SDIP, 44-QFP, 48-QFH 1-3 Pins 1-3-1 Pin Diagram 1 42 2 41 3 40 4 39 5 38 6 7 8 9 10 11 12 13 14 15 16 17 MN101C117/115 TXD,SBO0,P00 RXD,SBI0,P01 SBT0,P02 BUZZER, P06 RMOUT,P10 P11 TM2IO,P12 TM3IO,P13 TM4IO,P14 IRQ0,P20 IRQ1,P21 IRQ2,P22 P60 P61 P62 P63 P64 P65 P66 P67 NRST, P27 - www.DataSheet4U.com Chapter 1 Overview 37 36 35 34 33 32 31 30 29 28 27 26 18 25 19 24 20 23 21 22 VSS OSC1 OSC2 VDD PA7,AN7 PA6,AN6 PA5,AN5 PA4,AN4 PA3,AN3 PA2,AN2 PA1,AN1 PA0,AN0 P80,LED0 P81,LED1 P82,LED2 P83,LED3 P84,LED4 P85,LED5 P86,LED6 P87,LED7 MMOD Figure 1-3-1 Pin Diagram (42-SDIP: TOP VIEW) Pins 5 P84,LED4 P85,LED5 P86,LED6 P87,LED7 MMOD P27,NRST P70 P67 P66 P65 P64 Chapter 1 Overview LED3,P83 LED2,P82 LED1,P81 LED0,P80 AN0,PA0 AN1,PA1 AN2,PA2 AN3,PA3 AN4,PA4 AN5,PA5 AN6,PA6 MN101C117/115 P63 P62 P61 P60 P22,IRQ2 P21,IRQ1,SENS P20,IRQ0 P14,TM4IO P13,TM3IO P12,TM2IO P11 AN7,PA7 VDD OSC2 OSC1 VSS NC TXD,SBO0,P00 RXD,SBI0,P01 SBT0,P02 BUZZER, P06 RMOUT,P10 www.DataSheet4U.com 44 43 42 41 40 39 38 37 36 35 34 1 33 2 32 3 31 4 30 5 29 6 28 7 - 27 8 26 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 Figure 1-3-2 Pin Diagram (44-QFP: TOP VIEW) 6 Pins P84,LED4 P85,LED5 P86,LED6 P87,LED7 MMOD P27,NRST P71 P70 P67 P66 P65 P64 LED3,P83 LED2,P82 LED1,P81 LED0,P80 NC AN0,PA0 AN1,PA1 AN2,PA2 AN3,PA3 AN4,PA4 AN5,PA5 AN6,PA6 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 30 7 - 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 MN101C117/115 P63 P62 P61 P60 P23,IRQ3 P22,IRQ2 P21,IRQ1,SENS P20,IRQ0 P14,TM4IO P13,TM3IO P12,TM2IO P11 AN7,PA7 VDD OSC2 OSC1 VSS XI XO TXD,SBO0,P00 RXD,SBI0,P01 SBT0,P02 BUZZER,P06 RMOUT,P10 www.DataSheet4U.com Chapter 1 Overview Figure 1-3-3 Pin Diagram (48-QFH: TOP VIEW) Pins 7 Chapter 1 Overview 1-3-2 Pin Function Summary *The pin numbers in the list correspond to the QFH package(Refer to Figure 1-3-3 Pin connection.) Be careful when using SDIP and QFP packages. Table 1-3-1 Pin Function Summary (1/4) Pin No. Name Type Dual Function Function Description 17 14 VSS VDD - Power supply pins Apply 2.0V to 5.5V to VDD and 0V to VSS. 16 15 OSC1 OSC2 Input Output Clock input pin Clock output pin Connect these oscillation pins to ceramic or crystal oscillators for highspeed clock operation. If the clock is an external input, connect it to OSC1 and leave OSC2 open. The chip will not operate with an external clock when using either the STOP or SLOW modes. 18 XI Input Clock input pin 19 XO Output Clock output pin 43 RST I/O Connect these oscillation pins to ceramic or crystal oscillators for lowspeed clock operation. If the clock is an external input, connect it to XI and leave XO open. The chip will not operate with an external clock when using the STOP mode. If these pins are not used, connect XI to VSS and leave XO open. *42-SDIP and 44-QFP packages have no pins of this kind. This pin resets the chip when power is turned on, is allocated as P27 and contains an internal pull-up resistor (Typ. 35 k). Setting this pin low initializes, the internal state of the device is initialized. Thereafter, setting the input to an"H"level release the reset The hardware waits for the system clock to stabilize, and then processes the reset interrupt. Also, if "0" is written to P27 and the reset is initiated by software, a low level will be output. The output has an n-channel open-drain configuration. If a capacitor is to be inserted between RST and VDD, it is recommended that a discharge diode be placed between RST and VDD. 20 to 23 P00 to P02 I/O P06 www.DataSheet4U.com 8 Pins P27 Reset pin SBO0(TXD), I/O port 0 SBI0(RXD), SBT0, DK (BUZZER) 4-bit CMOS tri-state I/O port. Each bit can be set individually as either an input or output by the P0DIR register. A pull-up resistor for each bit can be selected individually by the P0PLU register. At reset, the input mode is selected and pull-up resistors are disabled (high impedance output). www.DataSheet4U.com Chapter 1 Overview Table 1-3-1 Pin Function Summary (2/4) Pin No. Name Type Dual Function Function I/O port 1 Description 24 to 28 P10 to P14 I/O RMOUT, TM2IO to TM4IO 29 to 32 P20 to P23 Input IRQ0, Input port 2 IRQ1(SENS), IRQ2 to 3 43 P27 Input RST 33 to 40 P60 to P67 I/O I/O port 6 8-bit CMOS tri-state I/O port. Each bit can be set individually as either an input or output by the P6DIR register. A pull-up resistor for each bit can be selected individually by the P6PLU register. At reset, the input mode is selected and pull-up resistors for P60 to P67 are disabled (high impedance output). 41 to 42 P70 to P71 I/O I/O port 7 2-bit CMOS tri-state I/O port. Each individual bit can be switched to an input or output by the P7DIR register. A pull-up or pull-down resistor for each bit can be selected individually by the P7PLUD register. However, pull-up and pull-down resistors cannot be mixed. At reset, the input mode is selected and pull-up resistors are disabled (high impedance output). P70 and P71 pins do not exist for 42-SDIP package. P71 pin does not exist for 44-QFP package, either. 1 to 4 45 to 48 P80 to P87 I/O LED0 to 7 I/O port 8 8-bit CMOS tri-state I/O port. Each individual bit can be switched to an input or output by the P8DIR register. A pull-up resistor for each bit can be selected individually by the P8PLU register. When configured as outputs, these pins can drive LED segments, directly. At reset, the input mode is selected and pull-up resistors for P80 to P87 are disabled (high impedance output). 6 to 13 PA0 to PA7 Input AN0 to AN7 Input port 2 Input port A 5-bit CMOS tri-state I/O port. Each bit can be set individually as either an input or output by theP1DIR register. A pull-up resistor for each bit can be selected individually by the P1PLU register. At reset, the input mode is selected and pull-up resistors are disabled (high impedance output). 4-bit input port. A pull-up resistor for each bit can be selected individually by the P2PLU register. At reset, the input mode is selected and pull-up resistors are disabled (high impedance output). P23 pin does not exist for 42-SDIP, 44-QFP packages. Port P27 has an n-channel open-drain configuration. When "0" is written and the reset is initiated by software, a low level will be output. 8-bit input port. A pull-up or pull-down resistor for each bit can be selected individually by the PAPLUD register. However, pull-up and pulldown resistors cannot be mixed. At reset, the PA0 to PA7 input mode is selected and pull-up resistors are disabled. Pins 9 Chapter 1 Overview Table 1-3-1 Pin Function Summary (3/4) Pin No. Name Type Dual Function 20 TXD Output SBO0(P00) 21 RXD Input SBI0(P01) 20 SBO0 Output 21 SBI0 Input 22 SBT0 I/O 22 Buzzer In the serial interface in UART mode, these pins are configured as the receive data input pin and transmit data output pin. A push-pull or n-channel open-drain configuration can be selected for TXD by the SC0MD1 register. Pull-up resistors can be selected by the P0PLU register. The TXD and RXD pins are also allocated as P00 and P01 respectively. When not used as serial/UART pins, these can be used as normal I/O pins. TXD(P00) Serial interface transmit data output pin Transmit data output pin for serial interfaces 0. The output configuration, either CMOS push-pull or n-channel open-drain, and pull-up resistors can be selected by the software. Set these pins to the output mode by the P0DIR register. SBO0 is allocated as P00. This may be used as normal I/O pin when the serial interface is not used. RXD(P01) Serial interface receive data input pin Receive data input pin for serial interfaces 0. Pull-up resistor can be selected by the P0PLU register. Set these pins to the input mode by the P0DIR register. SBI0 is allocated as P01. This can be used as normal I/O pin when the serial interface is not used. P02 Serial interface clock I/O pin Clock I/O pin for serial interface 0. The output configuration, either CMOS push-pull or n-channel open-drain output, can be selected by the software. The direction of SBT0 is selected by the P0DIR register in accordance with the communication mode. Pull-up resistors can be selected by the P0PLU register. SBT0 is allocated as P02. This can be used as normal I/O pin when the serial interface is not used. P06 24 RMOUT I/O P10 26 to 28 TM2IO to TM4IO I/O P12 to P14 10 Pins Description UART transmit data output pin UART receive data input pin www.DataSheet4U.com I/O Function Buzzer output Piezoelectric buzzer driver pin. The driving frequency can be selected in the range of fs/2 to fs/2 by the DLYCTR register. Select output mode by the P0DIR register and select buzzer output by the DLYCTR register. When not used for buzzer output, this pin can be used as a normal I/O pin. Remote control transmit signal output pin Output pin for remote control transmit signal with a carrier signal. Can be used as a normal I/O pin when remote control is not used. Timer I/O pins Event counter clock input pins, overflow pulse output pins and PWM signal output pins for timer 2 to 4. To use these pins as event clock inputs, configure them as inputs by the P1DIR register. For overflow pulse and PWM output, configure these pins as outputs by the P1DIR register. When the pins are used as inputs, pull-up resistors can be specified by the P1PLU register. When not used for timer I/O, these can be used as normal I/O pins. Chapter 1 Overview Table 1-3-1 Pin Function Summary (4/4) Pin No. Name Type Dual Function Function Description Test mode switch input pin This pin sets the test mode. Must be set to L. P20, P21(SENS), P22,P23 External interrupt input pins The valid edge for these external interrupt input pins can be selected with the IRQnICR registers. IRQ1 is an external interrupt pin that is able to determine AC zero crossings. It can also be used as a normal external interrupt. When IRQ0 to 3 are not used for interrupts, these can be used as normal I/O pins. AN0 to AN7 Input PA0 to PA7 Analog input pins Analog input pins for an 8-channel, 10-bit A/D converter. When not used for analog input, these pins can be used as normal I/O pins. SENS IRQ1(P21) SENS is an input pin for an AC zero-cross detection circuit. The AC zeroAC zero-cross detection input pin cross circuit outputs a high level when the input is at an intermediate level. It outputs a low level at all other times. SENS is connected to the P21 input circuit and the IRQ1 interrupt circuit. When the AC zero-cross detection circuit is not used, this pin can be used as a normal P21 input. The P21IM flag of the FLOAT1 register sets which input is selected. 44 MMOD Input 29 to 32 IRQ0 to IRQ3 Input 6 to 13 30 Input www.DataSheet4U.com Pins 11 Chapter 1 Overview 1-4 Overview of Functions RAM 512 bytes 8-bit timer 2 External interrupt 8-bit timer 3 Serial interface 0 16-bit timer 4 Time base timer 5 A/D conversion Watchdog timer Port 6 RST MMOD VSS VDD OSC2 OSC1 XO ROM 16 KB Port 7 Port 1 Port 2 CPU MN101C00 Port 8 www.DataSheet4U.com System clock oscillator Sub-clock oscillator Port A TXD,SBO0,P00 RXD,SBI0,P01 SBT0,P02 P06 RMOUT,P10 P11 TM2IO,P12 TM3IO,P13 TM4IO,P14 IRQ0,P20 SENS,IRQ1,P21 IRQ2,P22 IRQ3,P23 RST,P27 AN7,PA7 AN6,PA6 AN5,PA5 AN4,PA4 AN3,PA3 AN2,PA2 AN1,PA1 AN0,PA0 Port 0 XI 1-4-1 Block Diagram Figure 1-4-1 Block Diagram of Functions) 12 Overview of Function P60 P61 P62 P63 P64 P65 P66 P67 P70 P71 P80,LED0 P81,LED1 P82,LED2 P83,LED3 P84,LED4 P85,LED6 P86,LED6 P87,LED7 Chapter 1 Overview 1-5 Electrical Characteristics Contents Model MN101C117/115 Classification CMOS integrated circuit Use General purpose Function CMOS, 8-bit, single-chip microcomputer This LSI manual describes standard specifications. Before using the LSI, please obtain product specifications from the sales office. 1-5-1 Absolute Maximum Ratings Parameter Symbol 2 3 Rating Unit 1 Supply voltage VDD -0.3 to +7.0 V 2 Input clamp current (SENS) IC -500 to 500 A 3 Input pin voltage VI -0.3 to VDD+0.3 V 4 Output pin voltage VO -0.3 to VDD+0.3 V 5 I/O pin voltage VIO1 -0.3 to VDD+0.3 V www.DataSheet4U.com P8 I OL1 (peak) 30 Except P8 I OL2 (peak) 20 All pins I OH (peak) -10 I OL1 (avg) 20 Average output Other than P8 I OL2 (avg) current*1 15 I OH (avg) -5 6 7 Peak output current 8 9 10 P8 11 All pins mA 12 Tolerable loss PD 400 mW 13 Ambient operating temperature Topr -40 to 85 C 14 Storage temperature Tstg -55 to +125 C Note: 1 Applicable even for an interval of 100ms. Insert at least one bypass capacitor of 0.1 F or more between a power source pin and GND to prevent from latchup. *3 Absolute maximum ratings indicate the allowable limit to which applied voltage does not damage a chip, not guarantee the operation. *2 Electrical Characteristics 13 Chapter 1 Overview 1-5-2 Operating Conditions Ta=-40 to +85C VDD=2.0 to 5.5V VSS=0V Parameter Symbol Rating Conditions MIN TYP Unit MAX Supply voltage 1 VDD1 fosc 20.0MHz 4.5 5.5 2 VDD2 fosc 8.39MHz 2.7 5.5 VDD3 fosc 2.00MHz 2.0 5.5 fx = 32.768kHz 2.0 5.5 STOP mode 1.8 5.5 Supply voltage 3 during operation 4 VDD4 5 Voltage to maintain RAM data VDD5 Operating speed *1 V 2 6 7 tc1 VDD=4.5 to 5.5V 0.100 tc2 VDD=2.7 to 5.5V 0.238 VDD=2.0 to 5.5V 1.00 VDD=2.0 to 5.5V 40 125 VDD=4.5 to 5.5V 1.0 20.0 Instruction execution time 8 tc3 9 tc4 * 1 s Crystal oscillator 1 Fig. 1-5-1 10 Crystal frequency fxtal 1 11 C11 20 C12 20 www.DataSheet4U.com External capacitors 12 pF 13 Internal feedback resistor RF10 Crystal oscillator 2 Fig. 1-5-2* k 32.768 kHz fxtal 2 15 C21 20 C22 20 16 17 Internal feedback resistor RF20 Note: 700k Typ MN101C pF 4.0 M *1. Only for 48-QFH package 2 t c1, t c2, t c3: OSC1 is the CPU clock t c4: XI is the CPU clock OSC1 XI 4.0M Typ fxtal1 MN101C OSC2 C12 14 700 1 14 Crystal frequency External capacitors MHz C11 fxtal2 XO C22 C21 The instruction cycle is twice the clock cycle. The feedback resistor is built-in. The instruction cycle is four times the clock cycle. The feedback resistor is built-in. Figure 1-5-1 Crystal Oscillator 1 Figure 1-5-2 Crystal Oscillator 2 *1 Electrical Characteristics Chapter 1 Overview Parameter Symbol Rating Conditions MIN TYP Unit MAX External clock input 1 OSC1 (OSC2 is unconnected) 18 Clock frequency fOSC 19 High level pulse width twh 1 1 20 Low level pulse width twl 1 21 Rise time twr 1 1.0 20.0 20.0 30.0 20.0 30.0 Fig. 1-5-3 ns 5.0 Fig. 1-5-3 22 Fall time MHz ns twf 1 5.0 External clock input 2 XI (XO is unconnected)*2 23 Clock frequency 24 High level pulse width fx 32.768 twh 2 twl 2 26 Rise time twr 2 Fig. 1-5-4 s 3.5 20 Fig. 1-5-4 27 Fall time twf 2 kHz 3.5 1 25 Low level pulse width 100 ns 20 1 Set the clock duty ratio to 45 to 55%. *2 Applicable only for 48-pin QFH package www.DataSheet4U.com Electrical Characteristics 15 Chapter 1 Overview 0.9VDD 0.1VDD twh1 twr1 twl1 twf1 Figure 1-5-3 OSC1 Timing Chart www.DataSheet4U.com 0.9VDD 0.1VDD twh2 twr2 Figure 1-5-4 XI Timing Chart 16 Electrical Characteristics twl2 twf2 Chapter 1 Overview 1-5-3 DC Characteristics Ta=-40 to +85C VDD=2.0 to 5.5V VSS=0V Parameter Symbol Rating Conditions MIN Supply current (no load at output) 1 Supply current 2 during operation 3 4 Supply current during HALT mode 5 6 Supply current during STOP mode 7 Notes: 1 MAX 25 60 mA IDD2 IDD3 TYP 1 fosc=20.0MHz,VDD=5V IDD1 Unit fosc=8.39MHz,VDD=5V *2 IDD5 *2 10 25 fx =32.768kHz,VDD=3V 100 fx =32.768kHz,VDD=3V 8 Ta=25 ?W2@6X ?7<?B1 ?@e?@f?O2@@6T2@?f ?3=?C5e?W2(M??I4@@Lf ?V4@0YeW&(Yf?I'1f 7@H?gV'f ?J@5hg ?7@Hhg ?@@?hg ?@@?hg ?@@?hg ?@@?hg ?@@?hg ?@@?hg ?3@Lhg ?N@1h?@f 3@L?gJ5f V')Xf?W.Yf ?V4)K?eO.Y?f ?I4@@@0Yg IDD6*2 Ta=-40 to 85C IDD7 VDD=5V, Ta=25C 0 2 IDD8 VDD=5V, Ta=-40 to 85C 0 20 18 A Measured under conditions of Ta=25C and no load. The supply current during operation, I DD1 (I DD2 ), is measured under the following conditions: After all I/O pins are set to input mode and the oscillation is set to <NORMAL mode>, the MMOD pin is fixed at VSS, the input pins are www.DataSheet4U.com fixed at VDD, and a 20MHz (8.39MHz) square wave of amplitude VDD,VSS is input to the OSC1 pin. The supply current during operation, IDD3, is measured under the following conditions: After all I/O pins are set to input mode and the oscillation is set to <SLOW mode>, the MMOD pin is fixed at VSS, the input pins are fixed at VDD, and a 32.768kHz square wave of amplitude VDD,VSS is input to the XI pin. The supply current during HALT mode, IDD5(IDD6), is measured under the following conditions: After all I/O pins are set to input mode and the oscillation is set to <HALT mode>, the MMOD pin is fixed at VSS, the input pins are fixed at VDD, and an 32.768kHz square wave of amplitude VDD,VSS is input to the XI pin. The supply current during STOP mode IDD7(IDD8) is measured under the following conditions: After the oscillation mode is set to <STOP mode>, the MMOD pin is fixed at VSS, the input pins are fixed at VDD, and the OSC1 and XI pins are *2 unconnected. The items IDD5(IDD6) and IDD7(IDD8) are applicable only for 48-pin QFH package. Electrical Characteristics 17 Chapter 1 Overview Ta=-40 to +85C VDD=2.0 to 5.5V VSS=0V Parameter Symbol Rating Conditions MIN TYP Unit MAX Input pin 1 MMOD 8 Input high voltage 1 VIH1 9 Input high voltage 2 VIH2 10 Input low voltage 1 VIL1 11 Input low voltage 2 VIL2 VDD=4.5 to 5.5V 12 Input leakage current ILK1 VIN = 0 to VDD VDD=4.5 to 5.5V 0.8VDD VDD V 0.7VDD VDD V 0 0.2VDD V 0 0.3VDD V 10 A Input pin 2 P20, P22~P23 (Schmitt trigger input) 13 Input high voltage VIH3 0.8VDD VDD V 14 Input low voltage VIL3 0 0.2VDD V 15 Input leakage current ILK3 VIN=0 to VDD 10 A IIH3 VDD=5V, VIN=1.5V Pull-up resistor ON -300 A 16 Input high current -30 -100 Input pin 3--1 P21 (Schmitt trigger input) 17 Input high voltage VIH4 0.8VDD VDD V 18 Input low voltage VIL4 0 0.2VDD V 19 Input leakage current ILK4 VIN=0 to VDD 10 A IIH4 VDD=5V, VIN=1.5V Pull-up resistor ON -300 A 20 Input high current www.DataSheet4U.com -30 -100 Input pin 3--2 P21 (when used as SENS) 21 Input high voltage 1 VDHH 22 Input low voltage 1 VDLH 23 Input high voltage 2 4.5 VDD VSS 3.5 VDHL 1.5 VDD 24 Input low voltage 2 VDLL VSS 0.5 25 Input leakage current ILK10 VIN=0V to VDD IC10 VDD=5.0V VIN>VDD, VIN<0V 26 Input clamp current 18 Electrical Characteristics VDD=5.0V Fig. 1-5-5 V V 10 A 400 Chapter 1 Overview SENS pin 27 trs Rise time 30 Fig. 1-5-5 28 tfs Fall time s 30 trs tfs VDD VDHH VDLH Input voltage level 1 (Input) VDHL VDLL VSS Input voltage level 2 (Output) www.DataSheet4U.com Figure 1-5-5 Operation of AC Zero-Cross Detection Circuit Ta=-40 to +85C VDD=2.0 to 5.5V VSS=0V Parameter Symbol Rating Conditions MIN TYP Unit MAX Input pin 4 PA0~PA7 29 Input high voltage 1 VIH5 30 Input high voltage 2 VIH6 31 Input low voltage 1 VIL5 32 Input low voltage 2 VIL6 VDD=4.5 to 5.5V 33 Input leakage current ILK5 VIN=0 to VDD 34 Input high current IIH5 VDD=5V, VIN=1.5V Pull-up resistor ON IIL5 VDD=5V, VIN=3.5V Pull-down resistor ON 35 Input low current VDD=4.5 to 5.5V 0.8VDD VDD V 0.7VDD VDD V 0 0.2VDD V 0 0.3VDD V 2 A -30 -100 -300 A 80 180 400 A Electrical Characteristics 19 Chapter 1 Overview Ta=-40 to +85C VDD=2.0 to 5.5V VSS=0V Parameter Symbol Rating Conditions MIN TYP Unit MAX I/O pin 5 P27 (RST) 36 Input high voltage VIH7 0.9VDD VDD V 37 Input low voltage VIL7 0 0.2VDD V 38 Input leakage current ILK7 VIN = 0 to VDD 10 A Iih VDD=5V, VIN=1.5V Pull-up resistor built in -300 A 39 Input high current -30 -100 I/O pin 6 P00 to P06, P10 to P14 (Schmitt trigger input) 40 Input high voltage VIH8 0.8VDD VDD V 41 Input low voltage VIL8 0 0.2VDD V 42 Input leakage current ILK8 VIN=0 to VDD 10 A 43 Input high current IIH8 VDD=5V, VIN=1.5V Pull-up resistor ON -300 A 44 Output high voltage VOH8 VDD = 5V, IOH = -0.5mA 45 Output low voltage VOL8 VDD = 5V, IOL = 1.0mA -30 -100 4.5 V 0.5 V 0.8VDD VDD V 0.7VDD VDD V 0 0.2VDD V 0 0.3VDD V 10 A -300 A I/O pin 7 , P60 to P67 46 Input high voltage 1 VIH9 47 Input high voltage 2 VIH10 48 Input low voltage 1 VIL9 49 Input low voltage 2 VIL10 50 Input leakage current ILK9 VIN=0 to VDD 51 Input high current IIH9 VDD=5V, VIN=1.5V Pull-up resistor ON 52 Output high voltage VOH9 VDD = 5V, IOH = -0.5mA 53 Output low voltage VOL9 VDD = 5V, IOL = 1.0mA www.DataSheet4U.com VDD=4.5 to 5.5V VDD=4.5 to 5.5V -30 -100 4.5 V 0.5 V 0.8VDD VDD V 0.7VDD VDD V 0 0.2VDD V 0 0.3VDD V 10 A I/O pin 8 P70 to P71 54 Input high voltage 1 VIH11 55 Input high voltage 2 VIH12 56 Input low voltage 1 VIL11 57 Input low voltage 2 VIL12 VDD=4.5 to 5.5V 58 Input leakage current ILK11 VIN = 0 to VDD 59 Input high current IIH11 VDD=5V, VIN=1.5V Pull-up resistor ON 60 Input low current IIL11 61 Output high voltage 62 Output low voltage 20 VDD=4.5 to 5.5V -30 -100 -300 A VDD=5V, VIN=3.5V Pull-down resistor ON 30 100 300 A VOH11 VDD = 5V, IOH = -0.5mA 4.5 VOL11 VDD = 5V, IOL = 1.0mA Electrical Characteristics V 0.5 V www.DataSheet4U.com Chapter 1 Overview Ta=-40 to +85C VDD=2.0 to 5.5V VSS=0V Parameter Symbol Rating Conditions MIN TYP Unit MAX I/O pin 9 P80~P87 63 Input high voltage 1 VIH13 64 Input high voltage 2 VIH14 65 Input low voltage 1 VIL113 66 Input low voltage 2 VIL14 VDD=4.5 to 5.5V 67 Input leakage current ILK13 VIN=0 to VDD 68 Input high current IIH13 VDD=5V, VIN=1.5V Pull-up resistor ON -30 69 Output high voltage VOH13 VDD = 5V, IOH = -0.5mA 4.5 70 Output low voltage VOL13 VDD = 5V, IOL = 15mA VDD=4.5 to 5.5V 0.8VDD VDD V 0.7VDD VDD V 0 0.2VDD V 0 0.3VDD V 10 A -300 A -100 V 1.0 V 1-5-4 A/D Converter Characteristics Ta=-40 to+85C VDD=2.0 to 5.5V VSS=0V Rating Parameter Symbol Conditions Unit MIN 1 Resolution 2 Nonlinear error 1 3 Differential linear error 1 4 Nonlinear error 2 5 Differential linear error 2 6 Zero traction voltage 7 Full-scale transition voltage 8 9 11 Bits VDD = 5.0V, VSS = 0V VREF+=5.0V, VREF-=0V TAD = 800ns 3 LSB 3 LSB VDD = 5.0V, VSS = 0V VREF-=5.0V, VREF-=0V fx = 32.768kHz 5 LSB 5 LSB 30 100 mV 30 100 mV VDD = 5.0V, VSS = 0V VREF+=5.0V, VREF-=0V TAD = 800ns Sampling time 12 Analog input leakage current 9.6 s fx = 32.768kHz fOSC = 8MHz 10 MAX 10 TAD = 800ns A/D conversion time TYP fx = 32.768kHz When VDAIN = 0 to 5V is off 1.0 183 s 36 s 30.5 s 2 A Electrical Characteristics 21 Chapter 1 Overview 1-6 Option 1-6-1 ROM Option The product equipped with this LSI or an EPROM with this LSI controls the oscillation mode after resetting as well as the runaway-detection watchdog timer, using bits 2 to 0 of the last address of the built-in ROM. Option bits 7 - 6 - 5 4 - PKG SEL2 3 2 1 0 PKG WDSEL2 WDSEL1 NSSTRT SEL1 Selection of oscillation mode after resetting NSSTRT 0 SLOW mode 1 NORMAL mode www.DataSheet4U.com WDSEL2 WDSEL1 Watchdog timer cycle setting 0 1 0 fs/2 16 1 fs/2 18 fs/2 20 PKGSEL2 PKGSEL1 0 1 SDIP042-P-0600 0 QFP044-P-1010 QFH048-P-0707 1 Figure 1-6 ROM Option ( Address:X'7FFF' ) 22 Option Packages www.DataSheet4U.com Chapter 1 Overview 1-6-2 Option Form Date: SE No. Model Name MN101C Customer Approval 1. Oscillation mode Type A Type B Note: Type A: Operation begins from the reset cycle in the NORMAL mode. Type B: Operation begins from the reset cycle in the SLOW mode. 2. Watchdog timer period setting Detection Period 16 Selection 3. Package selection Package fs/2 SDIP042-P-0600 fs/218 QFP044-P-1010 20 fs/2 Selection QFH048-P-0707 Not used Contents of mask option are subject to change. When placing an order for masks, please request the most recent option list from the sales office. Option of this product is used a part of the built-in ROM. When placing an order for programme, please sed data on the address of the option. Chapter 1 Overview 23 Chapter 1 Overview 1-7 Outline Drawings Package code: SDIP042-P-0600 Unit: mm www.DataSheet4U.com Body Material: Epoxy Resin Lead Material:Fe Ni Lead Finish Method:Soldering dip Figure 1-7-1 42-SDIP The external dimensions of the package are subject to change. Before using this product, please obtain product specifications from the sales office. 24 External Dimensions Chapter 1 Overview Package code: QFP044-P-1010 Unit: mm www.DataSheet4U.com Body Material: Epoxy Resin Lead Material:Fe Ni Lead Finish Method:Soldering dip Figure 1-7-2 44-QFP The external dimensions of the package are subject to change. Before using this product, please obtain product specifications from the sales office. External Dimensions) 25 Chapter 1 Overview Package code: QFH048-P-0707 Unit: mm www.DataSheet4U.com Material: Epoxy Resin Lead Material:Fe Ni-42 Alloy Lead Finish Method:Soldering dip Figure 1-7-3 48-QFH The external dimensions of the package are subject to change. Before using this product, please obtain product specifications from the sales office. 26 External Dimensions ?? @@@?he O26Xe @@Y?e?O26X?e @@@@@@@@@@@@@@@@@@@@@)e ?@@@@@@@@@@@@@@@@@@@)?e ?I'Xg@Xh @Khf?O26X?e N)X?e?J@@h @@@@@@@@@@@@@@@@@@)?e ?@)KeO&Y?eO26Xe @@ @@H?e @@@@@@@@@@@@@@@@@@@@@)e @@ @@f @@@@@@@@@@@@@@@@@@f @@@@@@@@@@@@@@g @@ @@he@@g @@f?@@@e@@@?g @@he@@g @@f?@@He@@Y?O)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @@he@@g @@f?@@?e@@h @@he@@g @@f?@@?e@@eO)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @0M?e@@e?I4@g ?J@5f?@@?e@@h @@gO26Xe ?7@Hf?@5?e@@h @@@@@@@@@@@@@@@@@@@@@)e ?@5?'@@@@@H?e@@eO26Xe @@hf ?@H?V+MW@5f@@@@@@@)e @@hf J5fW&(Yf@@h @@hf .Ye?O&0Y?f@@h @@hf @0M?g@@h W&g O2@@6Kf O2@@6Kf O2@@6Kf ?O2@@@e ?W&@g ?@@(MI'@@?e ?@@(MI'@@?e ?@@(MI'@@?e ?W2@0Mf W&@@g J@(YeV'@Le J@(YeV'@Le J@(YeV'@Le W&(Mg .Y@@g 7@H?e?N@1e 7@H?e?N@1e 7@H?e?N@1e ?W&(Y?g @@g @@g@@e @@g@@e @@g@@e ?7@Hh @@g @@g@@e @@g@@e @@g@@e J@@=h @@g 7@S@@@6Kf @@g 3@L?e?J@@e N@)XeW&@@e 3@L?e?J@@e N@)XeW&@@e 3@L?e?J@@e N@)XeW&@@e @@(M?I'@@?e @@g @@H?eV'@Le @@g ?@@)KO&@@@e I4@@0Y@5e ?@@)KO&@@@e I4@@0Y@5e ?@@)KO&@@@e I4@@0Y@5e @@f?N@1e @@g ?J@He ?J@He ?J@He @@g@@e @@g W&5?e W&5?e W&5?e @@g@@e @@g ?W&(Y?e ?W&(Y?e ?W&(Y?e 3@L?e?J@5e @@g O&(Yf O&(Yf O&(Yf N@)XeW&@He ?@@?e @@g O2@0Y?f O2@0Y?f O2@0Y?f ?@@?e ?@@)KO&@@?e ?@@?e @@@@@@f ?@@0M?g ?@@0M?g ?@@0M?g ?@@?e I4@@0Mf W&g W2@@6Xf ?W&@g ?W&(MI')X?e W&@@g ?7@HeN@1?e .Y@@g J@5?e?3@Le @@g 7@H?e?N@1e @@g @@g@@e @@g @@g @@g@@e @@g@@e @@g @@g @@g@@e @@g@@e @@g @@g@@e @@g @@g 3@L?e?J@5e N@1?e?7@He @@g ?3@LeJ@5?e @@g ?V')KO&(Y?e @@@@@@f V4@@0Yf ?? ? ?? ? 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W&(Yg V'@6X?e ?W&(Y?g ?V'@)Xe O&(Yh V'@1e W2@(Y?h ?V4@e ?O&@0Yhe ?O2@(Mhf ?@KO2@@0Y?hf ?3@@@0M?hg ?V40M? ?O2@@6X?f ?W2@@@@@@@e @@@@@@)Xf W&@@@@@@@@e ?J(MeI'@1f .Mg@@e ?.Y?e?N@@f ?J@5e @@f ?7@He @@f J@5?e ?J@5f 7@H?e ?7@Hf ?J@5f J@5?f ?7@Hf 7(Y?f J@5?f ?J(Yg 7@H?f W.Y?g @@g ?W.Yh ?J@5g W&Y?fO.e ?7@Hg ?W&@@@@@@@(Ye ?@@?g ?&@@@@@@@0Y?e ?@@?g Chapter 2 2 Basic CPU Functions www.DataSheet4U.com 27 Chapter 2 Basic CPU Functions 2-1 Overview Basic CPU functions are in conformance with the MN101C00 series manual (architecture manual). This chapter describes specifications unique to the MN101C117/115. 2-2 Address Space 2-2-1 Memory Configuration X'00000' Abs 8 addressing access area 256 bytes 512 bytes X'00100' Internal RAM space Data www.DataSheet4U.com X'00200' X'03F00' 256 bytes X'04000' 128 bytes X'04080' 64 bytes Special function registers Interrupt vector table Subroutine vector table 16 KB X'040C0' Internal ROM space Instruction code/ table data X'07FFF' Figure 2-2-1 Memory Map Differs depending upon the model. MN101C115 Internal RAM X'00000' to X'000FF' Internal ROM X'04000' to X'05FFF' MN101CP117 Internal RAM X'00000' to X'001FF' EP ROM 28 Overview/Address Space X'04000' to X'01FFF' 256 bytes 8 KB 512 bytes 16 KB www.DataSheet4U.com Chapter 2 Basic CPU Functions 2-2-2 Special Function Registers Memory control register(MEMCTR) is a 4-bit register which set up the base Table 2-2-1 Register Map 1 2 3 4 5 6 7 8 9 A B C D E F CPU mode, memory control Port output 03F1X P0OUT P1OUT P2OUT P6OUT P7OUT P8OUT 03F2X P0IN P1IN P2IN P6IN P7IN P8IN 03F3X P0DIR P1DIR P6DIR P7DIR P8DIR P1OMD PAIMD 03F4X P0PLU P1PLU P2PLU P6PLU P7PLUD P8PLU Port input PAIN I/O mode control I/O ports 0 03F0X CPUM MEMCTR WDCTR DLYCTR Resistor control PAPLUD FLOAT1 03F5X SC0MD0 SC0MD1 SC0MD2 SC0MD3 SC0CTR SC0TRB SC0RXB Serial interface control 03F6X TM2BC TM3BC TM4BCL TM4BCH TM4ICL TM4ICH TM5BC 03F7X TM2OC TM3OC TM4OCL TM4OCH TM5OC 03F8X TM2MD TM3MD TM4MD TM5MD RMCTR NFCTR Timer control A/D control 03F9X ANCTR0 ANCTR1 ANBUF0 ANBUF1 03FAX 03FBX Reserved 03FCX 03FDX 03FEX NMICR IRQ0ICR IRQ1ICR TM2ICR TBICR SC0ICR ADICR IRQ2ICR TM3ICR TM4ICR Interrupt control 03FFX TM5ICR Address Space 29 Chapter 2 Basic CPU Functions 2-3 Bus Interface 2-3-1 Overview The MN101C117, unlike other MN101C series microcomputers, does not support memory expansion mode and processor mode. 2-3-2 Control Registers The memory control register is a four-bit register that sets up wait-count at a time of access to a base address of interrupt vector table and a special register zone. (1) Memory control register(MEMCTR) 7 MEMCTR 6 5 IOW1 IOW0 IVBA 4 3 2 1 0 (at reset: 11001011) IRWE Must be set to 11. www.DataSheet4U.com IRWE Set software write for interrupt request flag 0 Software write disable Even if data is written to each interrupt control register (xxxICR), the state of the interrupt request flag (xxxIR) will not change. 1 Software write enable Must be set to 1. Must be set to 0 IVBA Base address setting for interrupt vector table 0 Interrupt vector base = X'04000' 1 Interrupt vector base = X'00100' IOW1 to 0 Bus cycle at Number of wait cycles set when accessing special register area 20MHz oscillation 00 No wait cycles 100ns 01 1 wait cycle 150ns 10 2 wait cycles 200ns 11 3 wait cycles 250ns Figure 2-3-1 Memory Control Register MEMCTR:X'03F01'R/W 30 Bus Interface www.DataSheet4U.com Chapter 2 Basic CPU Functions 2-4 Interrupts 2-4-1 Accepting and Returning from Interrupts In the MN101C00 series, when an interrupt is accepted, the hardware pushes the program's return address and the PSW, on to the stack, and branches to the beginning address of the interrupt program specified by the interrupt vector table. Operation when Interrupt is Accepted 1. 2. The stack pointer (SP) contents are update. (SP-6 SP) The handy address register (HA) is pushed on to the stack. 3. HA upper byte (SP+5) HA lower byte (SP+4) The program counter (PC = return address) contents are pushed on to the stack. 4. PC (bit 18 to bit 17, bit 0) (SP+3) PC (bit 16 to bit 9) (SP+2) PC (bit 8 to bit 1) (SP+1) The PSW is pushed on to the stack. 5. PSW (SP) xxxLVn of the accepted interrupt is copied to IM of the PSW. 6. Interrupt level IM Execution branches to vector table. 7 0 7 New SP (after interrupt accepted) NewisSP 0 Low PSW Low PSW PC8 to 1 (after interrupt is accepted) PC8toto91 PC16 PC0 PC0 PC16 to 9PC18,17 HA7 to 0 PC18,17 Address Address HA7toto80 HA15 Old SP (before interrupt is accepted) Old SP HA15 to 8 High High (before interrupt is accepted) Figure 2-4-1 Stack Status during an Interrupt Since the contents of data and address registers are not saved, use PUSH instructions in the program to save these values as necessary on the stack. Interrupts 31 Chapter 2 Basic CPU Functions Operation when Returning from Interrupt After the program POPs the register and other values saved by the interrupt service routine, an RTI instruction is implemented to return to the program that was being executed when the interrupt was received. The processing sequence for the return from interrupt instruction, RTI, is listed below. www.DataSheet4U.com 32 Interrupts 1. 2. 3. The processor status word (PSW) is pulled from the stack. (SP) The program counter(PC = return address) is pulled from the stack. (SP+1 to 3) The handy address register (HA) is pulled from the stack. (SP+4, 5) 4. 5. The SP is pulled. (SP+6 SP) Execution branches to the address indicated by the PC. www.DataSheet4U.com Chapter 2 Basic CPU Functions 2-4-2 Interrupt Sources and Vector Addresses In addition to reset, there are 20 interrupt vectors that indicate the starting addresses of interrupt programs. These vectors are located in the 80-byte ROM address area X'04004' to X'04053'. Table 2-4-1 Interrupt Control Registers Interrupt Source Vector Number Control Register (address) Vector Address 0 Reset 1 Non-maskable interrupt (NMI) NMICR (X'03FE1') X'04004' 2 External interrupt 0 (IRQ0) IRQ0ICR (X'03FE2') X'04008' 3 External interrupt 1 (IRQ1) IRQ1ICR (X'03FE3') X'0400C' 4 Reserved (X'03FE4') X'04010' 5 Reserved (X'03FE5') X'04014' 6 Timer 2 compare-match (TM2IRQ) TM2ICR (X'03FE6') X'04018' 7 Time base period (TBIRQ) TBICR (X'03FE7') X'0401C' 8 SC0 transfer complete (SC0IRQ) SC0ICR (X'03FE8') X'04020' 9 Reserved (X'03FE9') X'04024' (X'03FEA') X'04028' 10 X'04000' A/D conversion complete (ADIRQ) ADICR 11 External interrupt 2 (IRQ2) IRQ2ICR (X'03FEB') X'0402C' 12 External interrupt 3 (IRQ3)* IRQ3ICR (X'03FEC') X'04030' 13 Reserved (X'03FED') X'04034' 14 Timer 3 compare-match (TM3IRQ) TM3ICR (X'03FEE') X'04038' 15 Timer 4 compare-match (TM4IRQ) TM4ICR (X'03FEF') X'0403C' 16 Timer 5 compare-match (TM5IRQ) TM5ICR (X'03FF0') X'04040' 17 Reserved (X'03FF1') X'04044' 18 Reserved (X'03FF2') X'04048' 19 Reserved (X'03FF3') X'0404C' 20 Reserved (X'03FF4') X'04050' *IRQ31CR cannot be used except for 48-pin QFH package. Set the vector addresses for reserved and unused interrupts to an address containing an RTI instruction. Interrupts 33 Chapter 2 Basic CPU Functions 2-4-3 Interrupt Control Registers Interrupt control registers consist of the following: a non-maskable interrupt control register (NMICR), external interrupt control registers (IRQnICR), and internal interrupt control registers (TMnICR, TBICR, SCnICR, ATCICR, ADICR). Be sure to use the MIE flag of the PSW register to write to all interrupt control registers. Non-maskable Interrupt Control Register (NMICR) Non-maskable interrupt factors are stored in the non-maskable interrupt control register (NMICR), and are used when a non-maskable interrupt is generated. 7 6 5 4 3 2 1 0 (at reset: ------0-) WDIR NMICR WDIR Watchdog interrupt request flag 0 No interrupt request 1 Happens interrupt request Figure 2-4-2 Non-maskable Interrupt Control Register (NMICR: X'03FE1', R/W) External Interrupt Control Registers (IRQnICR) The external interrupt control registers (IRQnICR) control the interrupt level, valid edge, and request/enable. www.DataSheet4U.com 7 By setting xxxLVn to '11' (level 3), the corresponding interrupt vector will be disabled, regardless of the state of the interrupt enable and interrupt request flags. IRQnICR 6 5 xxxLV1 xxxLV0 REDGn 4 3 2 -- -- -- 1 0 xxxIE xxxIR (at reset: 000---00) xxxIR External interrupt request flag 0 No interrupt request 1 Happens interrupt request xxxIE External interrupt enable flag 0 Disable interrupt 1 Enable interrupt REDGn External interrupt valid edge flag 0 Falling edge 1 Rising edge xxxLV1 xxxLV0 Interrupt level flag for external interrupt The CPU has interrupt levels from 0 to 3. This flag sets the interrupt level for interrupt requests. n=0,1,2,3,4 Figure 2-4-3 External Interrupt Control Register (IRQnICR: X'03FE2' to X'03FE3', X'03FEB' to X'03FED', R/W) 34 Interrupts Chapter 2 Basic CPU Functions Internal Interrupt Control Registers (TMnICR, TBICR, SCOICR, ATCICR, ADICR) The internal interrupt control registers (TMnICR, TBICR, SCnICR, ATCICR, ADICR) control the interrupt levels of internal interrupts, timer interrupts, serial interrupts, A/D conversion complete interrupts, and interrupt request/enable. Be sure to disable all interrupts before writing to these registors. 7 6 TMnICR, TBICR, SCnICR, xxxLV1 xxxLV0 ATCICR, ADICR 5 4 3 2 - - - - 1 0 xxxIE xxxIR (at reset: 00----00) xxxIR Interrupt request flag 0 No interrupt request 1 Happens interrupt request xxxIE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt xxxLV1 xxxLV0 By setting xxxLVn to '11' (level 3), the corresponding interrupt vector will be disabled, regardless of the state of the interrupt enable and interrupt request flags. Interrupt level flag This 2-bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests. www.DataSheet4U.com Figure 2-4-4 Internal Interrupt Control Registers (TMnICR, TBICR, SC0ICR,ADICR: X'03FE6' to X'03FEA', X'03FEA' to X'03FF0', R/W) Interrupts 35 Chapter 2 Basic CPU Functions 2-5 Reset The CPU contents are reset and registers are initialized when the RST pin is pulled to low. Initiating a Reset There are two methods to initiate a reset. For the reset to be stable, the low pulse must be maintained for at least four clock cycles. However, it is important to minimize noise, since a reset may occur in a smaller number of clock cycles. (1) Drive the RST pin low for at least four clock cycles. RST pin 4 clock cycles (200ns for a 20MHz oscillation) Figure 2-5-1 Minimum Reset Pulse Width (2) Set bit 7 (P2OUT7 flags) of the P2OUT register to "0." After reset is released, the P2OUT flag will be "1." Releasing the Reset www.DataSheet4U.com When the RST pin changes from low to high, an internal 15-bit counter begins counting at the oscillation clock frequency. The interval from when this counter begins counting until it overflows is known as the stabilization wait time. After waiting for this amount of time, the internal reset is released and the CPU begins operation. RST pin Peripheral register CPU internal reset Oscillation stabilization wait time 215/fosc Figure 2-5-2 Reset Release Sequence When returning from the STOP mode is terminating, the software can use the DLYCTR register to select an oscillation stabilization wait time of 0, 27/fosc, 211/fosc, or 215/fosc. 36 Reset ?? @@@?he O26Xe @@Y?e?O26X?e @@@@@@@@@@@@@@@@@@@@@)e ?@@@@@@@@@@@@@@@@@@@)?e ?I'Xg@Xh @Khf?O26X?e N)X?e?J@@h @@@@@@@@@@@@@@@@@@)?e ?@)KeO&Y?eO26Xe @@ @@H?e @@@@@@@@@@@@@@@@@@@@@)e @@ @@f @@@@@@@@@@@@@@@@@@f @@@@@@@@@@@@@@g @@ @@he@@g @@f?@@@e@@@?g @@he@@g @@f?@@He@@Y?O)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @@he@@g @@f?@@?e@@h @@he@@g @@f?@@?e@@eO)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @0M?e@@e?I4@g ?J@5f?@@?e@@h @@gO26Xe ?7@Hf?@5?e@@h @@@@@@@@@@@@@@@@@@@@@)e ?@5?'@@@@@H?e@@eO26Xe @@hf ?@H?V+MW@5f@@@@@@@)e @@hf J5fW&(Yf@@h @@hf .Ye?O&0Y?f@@h @@hf @0M?g@@h W&g O2@@6Kf O2@@6Kf O2@@6Kf ?O2@@@e ?W&@g ?@@(MI'@@?e ?@@(MI'@@?e ?@@(MI'@@?e ?W2@0Mf W&@@g J@(YeV'@Le J@(YeV'@Le J@(YeV'@Le W&(Mg .Y@@g 7@H?e?N@1e 7@H?e?N@1e 7@H?e?N@1e ?W&(Y?g @@g @@g@@e @@g@@e @@g@@e ?7@Hh @@g @@g@@e @@g@@e @@g@@e J@@=h @@g 7@S@@@6Kf @@g 3@L?e?J@@e N@)XeW&@@e 3@L?e?J@@e N@)XeW&@@e 3@L?e?J@@e N@)XeW&@@e @@(M?I'@@?e @@g @@H?eV'@Le @@g ?@@)KO&@@@e I4@@0Y@5e ?@@)KO&@@@e I4@@0Y@5e ?@@)KO&@@@e I4@@0Y@5e @@f?N@1e @@g ?J@He ?J@He ?J@He @@g@@e @@g W&5?e W&5?e W&5?e @@g@@e @@g ?W&(Y?e ?W&(Y?e ?W&(Y?e 3@L?e?J@5e @@g O&(Yf O&(Yf O&(Yf N@)XeW&@He ?@@?e @@g O2@0Y?f O2@0Y?f O2@0Y?f ?@@?e ?@@)KO&@@?e ?@@?e @@@@@@f ?@@0M?g ?@@0M?g ?@@0M?g ?@@?e I4@@0Mf W&g ?O2@@@e ?W&@g ?W2@0Mf W&@@g W&(Mg .Y@@g ?W&(Y?g @@g ?7@Hh @@g J@@=h @@g @@g 7@S@@@6Kf @@(M?I'@@?e @@g @@g @@H?eV'@Le @@f?N@1e @@g @@g@@e @@g @@g @@g@@e 3@L?e?J@5e @@g N@)XeW&@He @@g ?@@)KO&@@?e @@@@@@f I4@@0Mf ?? ? ?? ? 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O2@6X?f ?W2@@@@@@@e W2@@@@)Xf W&@@@@@@@@e 7(M?I'@1f .Mg@@e (Ye?N@@f ?J@5e ?J@5f ?7@He W&(Yf J@5?e ?W&@g 7@H?e ?&@@)Xf ?J@5f ?I')X?e ?7@Hf N@1?e J@5?f ?@@?e 7@H?f ?@@?e @@g ?@5?e ?J@5g @6X?eJ@H?e ?7@Hg 3@)K?O&@f ?@@?g V4@@@0M?f ?@@?g Chapter 3 3 Port Functions www.DataSheet4U.com 37 Chapter 3 Port Functions 3-1 Overview A total of 39 pins on the MN101C117, including those shared with special function pins, are allocated for the 7 ports of P0 to P2, P6 to P8, and PA. Each I/O port is assigned according to the special function register area in memory. I/O ports are operated in byte or bit units in the same way as RAM. For each I/O port, the PnOUT register (port n output register) that sets the output value is assigned to memory address X'3F1n', and the PnIN register (port n input register) from which the input value is monitored is assigned to memory address X'3F2n'. * This I/O control is valid even when special functions are selected for the dual function pins. *Table 3-1-1 Status When Port Is Reset (single-chip mode) Port I/O Mode Pull-up/Pull-down Resistor I/O Port or Special Function Port 0 Input mode No pull-up resistor I/O port Port 1 Input mode No pull-up resistor I/O port Port 2 Input mode No pull-up resistor I/O port Port 6 Input mode No pull-up resistor I/O port Port 7 Input mode No pull-up/pull-down resistors I/O port Port 8 Input mode No pull-up/pull-down resistors I/O port Port A Input mode No pull-up/pull-down resistors I/O port www.DataSheet4U.com Port 0 (P0) 4-bit CMOS tri-state I/O port. Table 3-1-2 Port 0 Functions Pin Name Type P00 to P02 I/O P06 38 Overview Dual Function SBO0(TXD), SBI0(RXD), SBT0 BUZZER Description Each bit can be set individually as either an input or output by the P0DIR register. A pull-up resistor for each bit can be selected individually by the P0PLU register. At reset, the input mode is selected and pull-up resistors are disabled (high impedance output). Chapter 3 Port Functions Port 1 (P1) 5-bit CMOS tri-state I/O port. Table 3-1-3 Port 1 Functions Pin Name Type P10 to P14 I/O Dual Function Description RMOUT, Each bit can be set individually as either an input or TM2IO to TM4IO output by the P1DIR register. A pull-up resistor for each bit can be selected individually by the P1PLU register. At reset, the input mode is selected and pull-up resistors are disabled (high impedance output). Port 2 (P2) 4-bit CMOS tri-state input port. Table 3-1-4 Port 2 Functions Pin Name P20 to P23 Type Input www.DataSheet4U.com Dual Function IRQ0, IRQ1(SENS), IRQ2 to 3 Description A pull-up resistor for each bit can be selected individually by the P2PLU register. At reset, the input mode pull-up resisters are disabled (high impedance output). Only 48-QFH has P23. Port 6 (P6) 8-bit CMOS tri-state I/O port. Table 3-1-5 Port 6 Functions Pin Name Type P60 to P67 I/O Dual Function Description Each bit can be set individually as either an input or output by the P6DIR register. A pull-up resistor for each bit can be selected individually by the P6PLU register. At reset, the input mode pull-up resisters are disabled (high impedance output). Overview 39 Chapter 3 Port Functions Port 7 (P7) 8-bit CMOS tri-state I/O port. Table 3-1-6 Port 7 Functions Pin Name Type P70 to P71 I/O Dual Function Description Each individual bit can be switched to an input or output by the P7DIR register. A pull-up or pull-down resistor for each bit can be selected individually by the P7PLU register. However, pull-up and pull-down resistors cannot be mixed. At reset, the input mode pull-up resisters are disabled . 42-SDIP has no pins of P70,P71. 44-QFP has no pin of p71. Port 8 (P8) 8-bit CMOS tri-state I/O port. Table 3-1-7 Port 8 Functions Pin Name Type Dual Function www.DataSheet4U.com P80 to P87 I/O LED0 to 7 Description Each individual bit can be switched to an input or output by the P8DIR register. A pull-up resistor for each bit can be selected individually by the P8PLU register. When configured as outputs, it is possible to LED. At reset, when single chip mode is selected, the input mode pull-up resisters for P80 to P87 are disabled (high impedance output). Port A (PA) 8-bit CMOS tri-state input port. Table 3-1-8 Port A Functions Pin Name Type PA0 to PA7 Input 40 Overview Dual Function Description AN0 to AN7 A pull-up or pull-down resistor for each bit can be selected individually by the PAPLUD register. However, pull-up and pull-down resistors cannot be mixed. At reset, the input mode pull-up resisters for PA0 to PA7 are disabled. www.DataSheet4U.com Chapter 3 Port Functions 3-2 Port Control Registers 3-2-1 Overview 28 registers control the I/O ports. See table 3-2-1. Table 3-2-1 I/O Port Control Registers (1/2) Name Address R/W P0OUT X'03F10' R/W Port 0 output register P1OUT X'03F11' R/W Port 1 output register P2OUT X'03F12' R/W Port 2 output register P6OUT X'03F16' R/W Port 6 output register P7OUT X'03F17' R/W Port 7 output register P8OUT X'03F18' R/W Port 8 output register P0IN X'03F20' R Port 0 input register P1IN X'03F21' R Port 1 input register P2IN X'03F22' R Port 2 input register P6IN X'03F26' R Port 6 input register P7IN X'03F27' R Port 7 input register P8IN X'03F28' R Port 8 input register PAIN X'03F2A' R Port A input register P0DIR X'03F30' R/W Port 0 direction control register P1DIR X'03F31' R/W Port 1 direction control register Function Port Control Registers 41 Chapter 3 Port Functions Table 3-2-1 I/O Port Control Registers (2/2) Name www.DataSheet4U.com 42 Port Control Registers Address R/W P6DIR X'03F36' R/W Port 6 direction control register P7DIR X'03F37' R/W Port 7 direction control register P8DIR X'03F38' R/W Port 8 direction control register P1OMD X'03F39' R/W Port 1 output mode register PAIMD X'03F3A' R/W Port A input mode register P0PLU X'03F40' R/W Port 0 pull-up control register P1PLU X'03F41' R/W Port 1 pull-up control register P2PLU X'03F42' R/W Port 2 pull-up control register P6PLU X'03F46' R/W Port 6 pull-up control register P7PLUD X'03F47' R/W Port 7 pull-up/pull-down control register P8PLU X'03F48' R/W Port 8 pull-up control register PAPLUD X'03F4A' R/W Port A pull-up/pull-down control register FLOAT1 X'03F4B' R/W Pin control register 1 Function Chapter 3 Port Functions 7 6 P0OUT6 P0OUT P1OUT P2OUT P0IN 5 4 3 2 1 0 P0OUT2 P0OUT1 P0OUT0 (at reset: -0---000) P1OUT4 P1OUT3 P1OUT2 P1OUT1 P1OUT0 (at reset: ---00000) (at reset: 1-------) P2OUT7 P0IN6 P0IN2 P0IN1 P0IN0 (at reset: -X---XXX) P1IN P1IN4 P1IN3 P1IN2 P1IN1 P1IN0 P2IN P2IN2 P2IN1 P2IN0 (at reset: ----XXX) P0DIR2 P0DIR1 P0DIR0 (at reset: -0---000) P1DIR P1DIR4 P1DIR3 P1DIR2 P1DIR1 P1DIR0 (at reset: ---00000) P1OMD P14TCO P13TCO P12TCO P10TCO (at reset: ---00000) P0PLU2 P0PLU1 P0PLU0 (at reset: -0---000) P1PLU P1PLU4 P1PLU3 P1PLU2 P1PLU1 P1PLU0 (at reset: ---00000) P2PLU P2PLU2 P2PLU1 P2PLU0 P6OUT P6OUT7 P6OUT6 P6OUT5 P6OUT4 P6OUT3 P6OUT2 P6OUT1 P6OUT0 (at reset: 00000000) P6IN P6IN7 P6IN6 P6IN5 P6IN4 P6IN3 P6IN2 P6IN1 P6IN0 (at reset: XXXXXXXX) P6DIR P6DIR7 P6DIR6 P6DIR5 P6DIR4 P6DIR3 P6DIR2 P6DIR1 P6DIR0 (at reset: 00000000) P6PLU P6PLU7 P6PLU6 P6PLU5 P6PLU4 P6PLU3 P6PLU2 P6PLU1 P6PLU0 (at reset: 00000000) P0DIR P0DIR6 (at reset: ---XXXXX) www.DataSheet4U.com P0PLU P0PLU6 (at reset: -----000) Figure 3-2-1 Port Control Registers (1/2) Port Control Registers 43 Chapter 3 Port Functions 7 6 5 4 3 2 1 0 P7OUT P7OUT1 P7OUT0 (at reset: - - - - - - 00) P8OUT P8OUT7 P8OUT6 P8OUT5 P8OUT4 P8OUT3 P8OUT2 P8OUT1 P8OUT0 (at reset: 00000000) P7IN P7IN1 P7IN0 (at reset: - - - - - - XX) P8IN P8IN7 P8IN6 P8IN5 P8IN4 P8IN3 P8IN2 P8IN1 P8IN0 (at reset: XXXXXXXX) PAIN PAIN7 PAIN6 PAIN5 PAIN4 PAIN3 PAIN2 PAIN1 PAIN0 (at reset: XXXXXXXX) P7DIR P7DIR1 P7DIR0 P8DIR P8DIR7 P8DIR6 P8DIR5 P8DIR4 P8DIR3 P8DIR2 P8DIR1 P8DIR0 (at reset: 00000000) PAIMD PAAIN7 PAAIN6 PAAIN5 PAAIN4 PAAIN3 PAAIN2 PAAIN1 PAAIN0 (at reset: 00000000) P7PLUD P7PLUD1 P7PLUD0 (at reset: - - - - - - 00) (at reset: - - - - - - 00) www.DataSheet4U.com P8PLU P8PLU7 P8PLU6 P8PLU5 P8PLU4 P8PLU3 P8PLU2 P8PLU1 P8PLU0 (at reset: 00000000) PAPLUD PAPLUD7 PAPLUD6 PAPLUD5 PAPLUD4 PAPLUD3 PAPLUD2 PAPLUD1 PAPLUD0 (at reset: 00000000) Figure 3-2-1 Port Control Registers (2/2) 44 Port Control Registers www.DataSheet4U.com Chapter 3 Port Functions 3-2-2 I/O Port Control Registers This section describes the special function registers that control the MN101C117's I/O ports. Data Registers * PnOUT registers Data registers to output to the ports. Data written to these registers is output from the ports. 0 Low (Vss level) is output. 1 High (Vdd level) is output. * PnIN registers Data registers to input data from the ports. The value of data at the pins can be input by reading these registers. These are read-only registers. 0 Pin is low. 1 Pin is high. Input and output registers are mapped to separate addresses. To use these ports for I/O, configure them as I/O ports in the PnOMD/PnIMD registers, described in this section. Direction Control Registers * PnDIR registers 0 Input mode 1 Output mode These registers set the port for use as an input or output. Pull-up/Pull-down Resistor Control Registers * PnPLU registers These register settings determine whether internal pull-up resistors are added to the ports. 0 No pull-up / pull-down resistor 1 Pull-up / Pull down resistor * PnPLUD registers These register settings determine whether internal pull-up or pull-down resistors are added to the ports. 0 No pull-up / pull-down resistor 1 Pull-up / Pull down resistor Port Control Registers 45 Chapter 3 Port Functions Port Output/Input Mode Registers * PnOMD/PnIMD registers These register settings determine whether the port pins(P10 to P14, PA0 to PA5) are used as I/O ports or as special function pins (dual function). If the special (dual) functions used, the PnDIR, PnPLU, PnPLUD, and other registers must be set. Setting the PAIMD register prevents unnecessary current from flowing in a pin when an intermediate voltage (analog voltage) is applied to the pin. 0 I/O port 1 Special function pin Pin Control Registers * FLOAT1 registers This register specifies whether the resistors-attached to pins P7 and PA are pull-up resistors or pull-down resistors. In addition, this register selects either zero cross input or Schmitt trigger input for pin P21. 7 FLOAT1 6 5 4 3 2 P21IM 1 0 PARDWN P7RDWN (at reset: -----000) P7RDWN www.DataSheet4U.com P7 pull-up/pull-down resistor selection 0 pull-up resistor 1 pull-down resistor PARDWN PA pull-up/pull-down resistor selection 0 pull-up resistor 1 pull-down resistor P21IM P21 input mode selection 0 Schmitt trigger input 1 SENS input Figure 3-2-2 Pin Control Register 1(FLOAT1: X'03F4B',R/W) 46 Port Control Registers Chapter 3 Port Functions 3-3 I/O Port Configuration and Functions P00,P02,P10 to P14 Reset R D Q Pull-up resistor control Write L Read Reset R D Q Data bus I/O direction control Write L Read Reset R D Q Port output data Write L Read Schmidt trigger input Port input data Read Special function input data Special function output control Special function output data www.DataSheet4U.com Pull-up resistor control I/O direction control Control bit Register (address) Control bit Register (address) Port output Control bit Register (address) Port input Control bit Register (address) Output format control Control bit Register (address) Special function input Special function Special function output control (1) Special function output control (2) Special function P00 P02 P0PLU0 P0PLU2 P0PLU (X'03F40') P0DIR0 P0DIR2 P0DIR (X'03F30') P0OUT0 P0OUT2 P0OUT (X'03F10') P0IN0 P0IN2 P0IN (X'03F20') SC0SBOM SC0SBTM SC0MD3 (X'03F53') SBT0 SBO0(TXD) Control bit SC0SBOS SBT0 SC0SBTS P10 P1PLU0 P11 P1PLU1 P1DIR0 P1DIR1 P1OUT0 P1OUT1 P1IN0 P1IN1 P12 P1PLU2 P1PLU (X'03F41') P1DIR2 P1DIR (X'03F31') P1OUT2 P1OUT (X'03F11') P1IN2 P1IN (X'03F21') P13 P1PLU3 P14 P1PLU4 P1DIR3 P1DIR4 P1OUT3 P1OUT4 P1IN3 P1IN4 TM2I TM3I TM4I RMOUT TM2O TM3O TM4O P10TCO P12TCO P13TCO P14TCO P1OMD (X'03F39') SC0MD3 (X'03F53') Register (address) Special function SBO0/TXD RMOUT Control bit SC0CMD RMOEN Register (address) SC0CTR (X'03F54') RMCTR (X'3F89) Both The TM0RM flag of the RMCTR register and the P10TCO flag of the P10MD register are used to switch between remote control output and timer output. I/O Port Configuration and Functions 47 Chapter 3 Port Functions P01 Reset R D Q Pull-up resistor control Write L Read Reset R D Q I/O direction control Data bus Write L Read Reset R D Q Port output data Write L Read Schmitt trigger input Port input data Read Special function input data Control bit Pull-up resistor Register control (address) Control bit I/O direction Register control (address) Control bit Port output Register (address) Control bit Port input Register (address) Special function input Special function www.DataSheet4U.com P01 P0PLU1 P0PLU (X'03F40') P0DIR1 P0DIR (X'03F30') P0OUT1 P0OUT (X'03F10') P0IN1 P0IN (X'03F20') SBI0/RXD Figure 3-3-2 Configuration and Functions of P01 48 I/O Port Configuration and Functions Chapter 3 Port Functions PA0 to PA7 Reset R D Q Pull-up/pull-down resistor control Write L Read R D Q Write L Read Data bus Pull-up/pull-down resistor selection Data bus Reset Read Port input data Reset R D Q Input mode control Write L Read Analog input www.DataSheet4U.com PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 Control bit PAPLUD0 PAPLUD1 PAPLUD2 PAPLUD3 PAPLUD4 PAPLUD5 PAPLUD6 PAPLUD7 Pull-up resistor Register PAPLUD control (address) (X'03F4A') Pull-up/ PARDWN Control bit pull-down Register FLOAT1 resistor (address) (X'03F4B') control Control bit PAAIN0 PAAIN1 PAAIN2 PAAIN3 PAAIN4 PAAIN5 PAAIN6 PAAIN7 Input mode Register PAIMD control (address) (X'03F3A') Control bit PAIN0 PAIN1 PAIN2 PAIN3 PAIN4 PAIN5 PAIN6 PAIN7 Port input Register PAIN (address) (X'03F2A') Special function Special function AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 input Figure 3-3-3 Configuration and Functions of PA0 to PA7 I/O Port Configuration and Functions 49 Chapter 3 Port Functions Pin Configuration for P20, P22 to P23 Reset R D Q Pull-up resistor control L Read Data bus Write Schmitt trigger input Port input data Read Special function input data *P23 is only for 48-pin package. P23 P20 P22 Control bit P2PLU0 P2PLU2 P2PLU3 Pull-up resistor P2PLU Register control (X'03F42') (address) P2IN3 P2IN2 Control bit P2IN0 Port input P2IN Register (X'03F22') (address) Special function IRQ3 IRQ0 IRQ2 Interrupt input input Figure 3-3-4 Configuration and Functions of P20, P22, P23 www.DataSheet4U.com 50 I/O Port Configuration and Functions www.DataSheet4U.com Chapter 3 Port Functions P21 Reset R D Q Pull-up resistor control Special function input data Data bus Read L Read Reset R D Q Read L Read Port input data Read AC zero-cross detection circuit Special function input data Schmitt trigger input Pull-up resistor control Port input Special function input selection Control bit Register (address) Control bit Register (address) Special function Control bit Register (address) P21 P2PLU1 P2PLU (x'03F42') P2IN1 P2IN (x'03F22') SENS P21IM FLOAT1 (x'03F4B') Figure 3-3-5 Configuration and Functions of P21 I/O Port Configuration and Functions 51 Chapter 3 Port Functions P27 Schmitt trigger input Data bus Reset signal input Reset S D Q Port output data Write L Special input Special function output www.DataSheet4U.com Special function Control bit Register (address) P27 RST Soft reset output P2OUT7 P2OUT (x'03F12') Figure 3-3-6 Configuration and Functions of P27 52 I/O Port Configuration and Functions Chapter 3 Port Functions P70 to P71 Reset R D Q Pull-up/pull-down resistor control Write L Read Reset R D Q Pull-up/pull-down resistor selection Write L Read I/O direction control Data bus Reset R D Q Write L Read Reset R D Q Port output data Write L Read Port input data Read www.DataSheet4U.com P70 Pull-up/ Control bit pull-down Register resistor control (address) P7PLUD0 Port input Port output Control bit Register (address) Control bit Register (address) Control bit Register (address) P7PLUD1 P7PLUD (X'03F47') P7RDWN FLOAT1 (X'03F4B') Control bit Pull-up/ pull-down Register resistor control (address) I/O direction control P71 P7DIR1 P7DIR0 P7DIR (X'03F37') P7IN0 P7IN1 P7IN (X'03F27') P7OUT0 P7OUT1 P7OUT (X'03F17') Figure 3-3-7 Configuration and Functions of P70 I/O Port Configuration and Functions 53 Chapter 3 Port Functions P60 to P67,P80 to P87 Reset R D Q Pull-up resistor control Write L Read Reset R D Q Data bus I/O direction control Write L Read Reset R D Q Port output data Write L Read Schmidt trigger input Port input data Read www.DataSheet4U.com Pull-up resistor control Control bit Register (address) I/O direction control Control bit Register (address) Port output Control bit Register (address) Port input Control bit Register (address) P65 P66 P67 P60 P61 P62 P63 P64 P6PLU0 P6PLU1 P6PLU2 P6PLU3 P6PLU4 P6PLU5 P6PLU6 P6PLU7 P6PLU (x'03F46') P6DIR0 P6DIR1 P6DIR2 P6DIR3 P6DIR4 P6DIR5 P6DIR6 P6DIR7 P6DIR (x'03F36') P6OUT0 P6OUT1 P6OUT2 P6OUT3 P6OUT4 P6OUT5 P6OUT6 P6OUT7 P6OUT (x'03F16') P6IN0 P6IN1 P6IN2 P6IN3 P6IN4 P6IN5 P6IN6 P6IN7 P6IN (x'03F26') Figure 3-3-8 Configuration and Functions of P60 to P67 Pull-up resistor control Control bit Register (address) I/O direction control Control bit Register (address) Port output Control bit Register (address) Port input Control bit Register (address) P85 P86 P87 P80 P81 P82 P83 P84 P8PLU0 P8PLU1 P8PLU2 P8PLU3 P8PLU4 P8PLU5 P8PLU6 P8PLU7 P8PLU (x'03F48') P8DIR0 P8DIR1 P8DIR2 P8DIR3 P8DIR4 P8DIR5 P8DIR6 P8DIR7 P8DIR (x'03F38') P8OUT0 P8OUT1 P8OUT2 P8OUT3 P8OUT4 P8OUT5 P8OUT6 P8OUT7 P8OUT (x'03F18') P8IN0 P8IN1 P8IN2 P8IN3 P8IN4 P8IN5 P8IN6 P8IN7 P8IN (x'03F28') Figure 3-3-9 Configuration and Functions of P80 to P87 54 I/O Port Configuration and Functions ?? @@@?he O26Xe @@Y?e?O26X?e @@@@@@@@@@@@@@@@@@@@@)e ?@@@@@@@@@@@@@@@@@@@)?e ?I'Xg@Xh @Khf?O26X?e N)X?e?J@@h @@@@@@@@@@@@@@@@@@)?e ?@)KeO&Y?eO26Xe @@ @@H?e @@@@@@@@@@@@@@@@@@@@@)e @@ @@f @@@@@@@@@@@@@@@@@@f @@@@@@@@@@@@@@g @@ @@he@@g @@f?@@@e@@@?g @@he@@g @@f?@@He@@Y?O)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @@he@@g @@f?@@?e@@h @@he@@g @@f?@@?e@@eO)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @0M?e@@e?I4@g ?J@5f?@@?e@@h @@gO26Xe ?7@Hf?@5?e@@h @@@@@@@@@@@@@@@@@@@@@)e ?@5?'@@@@@H?e@@eO26Xe @@hf ?@H?V+MW@5f@@@@@@@)e @@hf J5fW&(Yf@@h @@hf .Ye?O&0Y?f@@h @@hf @0M?g@@h W&g O2@@6Kf O2@@6Kf O2@@6Kf ?O2@@@e ?W&@g ?@@(MI'@@?e ?@@(MI'@@?e ?@@(MI'@@?e ?W2@0Mf W&@@g J@(YeV'@Le J@(YeV'@Le J@(YeV'@Le W&(Mg .Y@@g 7@H?e?N@1e 7@H?e?N@1e 7@H?e?N@1e ?W&(Y?g @@g @@g@@e @@g@@e @@g@@e ?7@Hh @@g @@g@@e @@g@@e @@g@@e J@@=h @@g 7@S@@@6Kf @@g 3@L?e?J@@e N@)XeW&@@e 3@L?e?J@@e N@)XeW&@@e 3@L?e?J@@e N@)XeW&@@e @@(M?I'@@?e @@g @@H?eV'@Le @@g ?@@)KO&@@@e I4@@0Y@5e ?@@)KO&@@@e I4@@0Y@5e ?@@)KO&@@@e I4@@0Y@5e @@f?N@1e @@g ?J@He ?J@He ?J@He @@g@@e @@g W&5?e W&5?e W&5?e @@g@@e @@g ?W&(Y?e ?W&(Y?e ?W&(Y?e 3@L?e?J@5e @@g O&(Yf O&(Yf O&(Yf N@)XeW&@He ?@@?e @@g O2@0Y?f O2@0Y?f O2@0Y?f ?@@?e ?@@)KO&@@?e ?@@?e @@@@@@f ?@@0M?g ?@@0M?g ?@@0M?g ?@@?e I4@@0Mf W&g ?O2@@@e ?W&@g ?W2@0Mf W&@@g W&(Mg .Y@@g ?W&(Y?g @@g ?7@Hh @@g J@@=h @@g @@g 7@S@@@6Kf @@(M?I'@@?e @@g @@g @@H?eV'@Le @@f?N@1e @@g @@g@@e @@g @@g @@g@@e 3@L?e?J@5e @@g N@)XeW&@He @@g ?@@)KO&@@?e @@@@@@f I4@@0Mf ?? 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W&g O2@6X?f ? O2@6X?f ?W&@g W2@@@@)Xf W2@@@@)Xf ? W&@@g 7(M?I'@1f 7(M?I'@1f ? .Y@@g (Ye?N@@f (Ye?N@@f ? ?J@5f @@g ?J@5f @@g W&(Yf ?@@?e?? W&(Yf @@g ?W&@g @@g ?&@@)Xf ?@@?e?? ?W&@g ?&@@)Xf @@g ?I')X?e ? ?I')X?e @@g N@1?e N@1?e ?? @@g ?@@?e ?@@?e @@g ?@@?e ?@@?e ?? @@g ?@5?e ?@5?e @@g @6X?eJ@H?e @6X?eJ@H?e ? @@g 3@)K?O&@f ?@@?e? 3@)K?O&@f @@@@@@f V4@@@0M?f ?@@?e? V4@@@0M?f ? ? ? ? ? ? ? W&g ?W&@g W&@@g .Y@@g @@g @@g @@g @@g @@g @@g @@g @@g @@g @@g @@g @@@@@@f W26Xf @@6Khe'6X?e 7<B1f ?I'@@?f?'6XV'1?e 3=C5f V4@?f?V'1?V'?e W2@@6XfV40Yf V'g ?W&(MI')X?he W&(YeV')Xhe ?@@6K? ?W&(Y?e?V')X?h I'@@hfW.f W&(YgV')Xh ?@K?f?O2@@@@@@@@@1?e ?O26X?e ?V4@he?W&Hf @?&@H?g?V')X?g W&5?f 3@@5heV')Xg ?W&(Y?f V40Yhe?V')K?f ?3@@@@@@@@0Mg?I@?e ?V40M? W&(Yg V'@6X?e ?W&(Y?g ?V'@)Xe O&(Yh V'@1e W2@(Y?h ?V4@e ?O&@0Yhe ?O2@(Mhf ?@KO2@@0Y?hf ?3@@@0M?hg ?V40M? W2@@@@@(e W2@@@@@(e 7@@@@@0Ye 7@@@@@0Ye ?J@?h ?J@?h ?75?h ?75?h J@Y?h J@Y?h @@@@@6K?f @@@@@6K?f I4@@@@f I4@@@@f I'@@L?e I'@@L?e ?V'@1?e ?V'@1?e N@@?e N@@?e ?@@?e ?@@?e ?@5?e ?@5?e J@H?e J@H?e ?@6Xe?W&5f?@6Xe?W&5f ?3@)K?O&0Yf?3@)K?O&0Yf ?V4@@@0Mg?V4@@@0Mg Chapter 4 4 Timer Functions www.DataSheet4U.com 55 Chapter 4 Timer Functions 4-1 Overview The MN101C117 contains three 8-bit timers, one 16-bit timer, a watchdog timer, a time base timer, and circuits for remote control output and buzzer output. Table 4-1-1 Summary of Timer Functions Timer 2 (8-bit) Timer 3 (8-bit) Timer 4 (16-bit) Timer 5 (8-bit) Time Base TM2IRQ TM3IRQ TM4IRQ TM5IRQ TBIRQ Event counter x x Timer pulse output x x x x x x x x x x Interrupt Timer operation Serial transmission clock x x www.DataSheet4U.com x PWM output Cascade connection x Capture function x x 0 fs fosc fosc fosc fosc Clock 1 fs/4 fs/4 fs/4 fs/4 fx source 2 fx fs/16 fs/16 fx 3 Other 56 Overview TM2IO input TM3IO input TM4IO input fosc,fx/213 Remote control carrier pulse generation Pulse added type PWM Not possible to temporarily halt BC TM2IO input fx fs/4 fs MUX MUX TM2CK0 TM2CK1 TM2CK2 TM2PWM TM2EN - - - TM2MD Synchronization 7 0 MUX MUX fosc f s/4 f s/16 TM3IO input MUX Synchronization Read TM2BC R 8-bit counter Match TM2OC Compare register Read/Write MUX MUX TM3CK0 TM3CK1 TM3CK2 TM3PWM TM3EN - - - TM3MD www.DataSheet4U.com 7 0 MUX RST input Read TM3BC R 8-bit counter Match TM3OC Compare register Read/Write S RQ 1/2 MUX MUX MUX TM3IO output/ PWM2/ Remote control carrier output/ Serial transfer clock output TM2IO output/PWM2 TM2IRQ 1/2 TM3IRQ Chapter 4 Timer Functions Figure 4-1-1 Timers 2, 3 Block Diagram Overview 57 58 Overview IRQ0 IRQ1 IRQ2 MUX Synchronization MUX MUX Synchronization Read Read Read TM4ICH 16-bit capture register TM4ICL MUX RSTIO Pulse-added timing generation TM4BCH R Overflow of lower 8 bits Match TM4OCH 16-bit counter Match TM4BCL R Read TM4OCL www.DataSheet4U.com TM4IO input fosc fs/4 fs/16 Read/Write 16-bit compare register Read/Write Q TM4CK0 TM4CK1 TM4CK2 T4ICT0 T4ICT1 TM4PWM TM4EN - TM4MD S R Figure 4-1-2 Timer 4 Block Diagram 7 0 1/2 Pulse added MUX TM4PWM MUX TCIO4Ioutput/ PWM output TM4IRQ Chapter 4 Timer Functions MUX 1/2 13 1/2 1/2 1/2 1/2 7 8 9 10 MUX fx MUX MUX Synchronization MUX 3.9ms, 7.8ms, 15.6ms, 31.2ms (32kHz) 250ms (32kHz) 0.977ms (8MHz) f osc f s/4 www.DataSheet4U.com fx f osc TM5MD 0 TM5CK0 TM5CK1 TM5CK2 TM5CK3 TM5IR0 TM5IR1 TM5IR2 TM5CLRS 7 MUX Read MUX TM5BC R TM5IRQ TBIRQ 1min (32kHz),250ms (8.38MHz) 8-bit counter Match TM5OC Compare register Read/Write Chapter 4 Timer Functions Figure 4-1-3 Timer 5/Time Base Block Diagram Overview 59 60 Overview Reset input fs R 1/212 1/211 1/210 1/29 Overflow MUX MUX 1/4 1/4 S ROM option Refer to the aragraph [1-6-1 ROM option] 1/214 1/2 14 fosc 1/2 10 fosc 1/2 6 fosc R 7 0 DLYS0 DLYS1 - - - BUZS0 BUZS1 BUZOE DLYCTR WDEN - - - - - - - WDCTR 7 0 R 1/4 Overflow Buzzer WDIRQ Internal reset release Chapter 4 Timer Functions www.DataSheet4U.com Figure 4-1-4 Watchdog Timer, Buzzer Block Diagram 7 0 - RMDTY0 - RMOEN - - - - MUX RMCTR Synchronization circuit Remote control output Chapter 4 Timer Functions Timer 3 output 1/3 duty 1/2 duty www.DataSheet4U.com Figure 4-1-5 Remote Control Transmission Block Diagram Overview 61 Chapter 4 Timer Functions 4-2 8-bit Timer Operation (timers 2, 3) 4-2-1 Overview Functions for timers 2 and 3 are listed below. Table 4-2-1 Summary of 8-bit Timer Functions Timer 2 (8-bit) Interrupt Timer 3 (8-bit) TM2IRQ TM3IRQ Timer operation Event counter Timer pulse output Serial transmission clock www.DataSheet4U.com x x PWM output Cascade connection Remote control carrier pulse generation 62 8-bit Timer Operation (timers 2, 3) (SIF0) x Chapter 4 Timer Functions When servicing an interrupt, reset the timer 2 interrupt request flag before starting timer 2. 4-2-2 Operation During a count operation, be careful if the value set in TM2OC is smaller than the value of binary counter 2, since the count-up operation will continue until overflow occurs. Timer Operation (timers 2, 3) Settings for timer operation are listed below. Timer 2 is used as an example. (1) Set the TM2EN flag of the timer 2 mode register (TM2MD) to "0" to stop the count operation of timer 2. (2) Set the TM2CK2 0 flags of the TM2MD register to select fs, fs/4, fx, or synchronized fx as the clock source. Set the TM2PWM flag of the TM2MD register to "0" so that normal timer operation is selected. Set a value in compare register 2 (TM2OC). Set the TM2EN flag of the TM2MD register to "1" to start the timer. When timer 2 begins operation, binary counter 2 (TM2BC) will count upward from X'00'. When the value of binary counter 2 matches that of the TM2OC register, the timer 2 interrupt request flag is set, and the binary counter 2 is reset to X'00' and begins to count upward again. (3) (4) (5) (6) (7) If fx is to be selected as the clock source and the value of binary counter 2 is to be read during operation, select synchronized fx in order to avoid reading data that may be incomplete during countup transitions. However, with synchronized fx, it is not possible to return from STOP/HALT modes. ? ?? ?? ?? ? ?? ?? ? W&f ?W&@f ?W2@@6X?e?? ?*@@@@e ?N@@f ?7(MI'1?e? J@H??N@Le? @@f 7@f@1e? @@f @@f @@f@@e? @@f @@f@@e? 3@f@5e? @@f N@L??J@He? @@?O.? 3@@(Y? ?3)KO&5?e? V40Ye ?V4@@0Y?e?? ?? ?? ? Clock www.DataSheet4U.com TM4EN Write to registers TM4OCH, TM4OCL Binary counter 4 04 05 06 07 08 09 00 Figure 4-2-1 Binary Counter 2 (TM2BC) Count Timing If the TM2EN flag of TM2MD register is changed simultaneously with other bits, the switching operation may cause binary counter 2 to be incremented. If the value of TM2OC register is overwritten while timer 2 has stopped counting, binary counter 2 will be reset to X'00' at the edge of next count clock. The value of TM3CK0~2 of T3MD register is unsettled. If timer2/ timer 3 is independently used, any mode except cascade connection should be set. 8-bit Timer Operation (timers 2, 3) 63 Chapter 4 Timer Functions Event Count Function (timers 2, 3) If TM2IO input is selected as the clock source and the value of binary counter 2 is to be read during operation, select synchronized TM2IO input to avoid reading data that may be incomplete during count-up transitions. However, with synchronized TM2IO input, it is not possible to return from STOP/HALT modes. Settings for the event count function are listed below. Timer 2 is used as an example. (1) (2) (3) (4) (5) (6) (7) Set the TM2EN flag of the timer 2 mode register (TM2MD) to "0" to stop the count operation of timer 2. Use the TM2CK2 to 0 flags of the TM2MD register to select TM2IO input or synchronous TM2IO input as the clock source. Set the TM2PWM flag of the TM2MD register to "0" so that normal timer operation is selected. Set a value in compare register 2 (TM2OC). Set the TM2EN flag of the TM2MD register to "1" to start the timer. When timer 2 begins operation, binary counter 2 will count upward from X'00'. When the value of binary counter 2 matches that of the TM2OC register, the timer 2 interrupt request flag is set, and the binary counter 2 is reset to X'00' and begins to count upward again. When synchronized TM2IO is selected, the timer 2 clock source is synchronized with the system clock after a transition of the TM2IO input signal. Binary counter 2 counts upward based on a signal synchronized to the system clock. Therefore, correct values can be read from binary counter 2. www.DataSheet4U.com CPU system clock (fs) TM4IO input Synchronous circuit output Binary counter n n+1 Figure 4-2-2 Timer 2 Event Counter Timing (when synchronous TM2IO input is selected) 64 8-bit Timer Operation (timers 2, 3) Chapter 4 Timer Functions Timer Pulse Output Function (timers 2, 3) Settings for the timer pulse output function are listed below. Timer 2 is used as an example. (1) (2) (3) (4) (5) (6) (7) (8) Set the TM2EN flag of the timer 2 mode register (TM2MD) to "0" to stop the count operation of timer 2. Set bit 2 of the port 1 output/input mode register (P1OMD) to "1" to set the special function pin. Bit 2 of port 1 will be specified as the pulse output pin. Set the TM2CK2 to 0 flags of the TM2MD register to select fs, fs/4, fx, or synchronized fx as the clock source. Set the TM2PWM flag of the TM2MD register to "0" so that normal timer operation is selected. Set a value in compare register 2 (TM2OC). Set the TM2EN flag of the TM2MD register to "1" to start the timer. When timer 2 begins operation, binary counter 2 will count upward from X'00'. When the value of binary counter 2 matches that of the TM2OC register, the timer 2 interrupt request flag is set, and the binary counter 2 is reset to X'00' and begins to count upward again. The period of a signal output to the port is 1/2 of the period set in the TM2OC register. If port 1 is to be used as a pulse output pin, it is necessary to set the port 1 output direction control register (P1DIR) and the port 1 pull-up/pull-down resistor control register (P1PLU). Matches compare register www.DataSheet4U.com Binary counter TM2OUT Figure 4-2-3 Timer Pulse Output Timing 8-bit Timer Operation (timers 2, 3) 65 Chapter 4 Timer Functions If the TM3PWM flag of the TM3MD register is set to "1" and timer 2 PWM output is selected, the PWM output of timer 2 will also be output from the TM3IO pin. If port 1 is to be used as a PWM output pin, the P1DIR and P1PLU registers must be set. PWM Output Function (Timer 2) Settings for the PWM output function are listed below. (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) www.DataSheet4U.com Set the TM2EN flag of the timer 2 mode register (TM2MD) to "0" to stop the count operation of timer 2. Set bit 2 of the port 1 output/input mode register (P1OMD) to the special function pin setting. Bit 2 of port 1 will be specified as the PWM output pin. Set the TM2CK2 to 0 flags of the TM2MD register to select fs, fs/4, fx, or synchronous fx as the clock source. The period of the output waveform is determined based on the clock source. Set the TM2PWM flag of the TM2MD register to "1" so that PWM operation is selected. Set a value in compare register 2 (TM2OC). The high interval of the output waveform is determined based on the value of the TM2OC compare register. Set the TM2EN flag of the TM2MD register to "1" to start the timer. When timer 2 begins operation, binary counter 2 will count upward from X'00'. A high-level signal is output from the port beginning when binary counter 2 starts counting at X'00' and ending when the value of binary counter 2 matches the value set in the TM2OC register. When the value of binary counter 2 matches that of the TM2OC register, a low-level signal is output from the port. Binary counter 2 continues to count upward until X'FF' is reached. At the next countup cycle, the value of binary counter 2 is reset to X'00', a high-level signal is output from the port, and counting begins again. Overflow Matches TM2OC register Binary counter 2 PWM output Time specified by TM2OC register Time until binary counter 2 reaches X'FF' Figure 4-2-4 PWM Output Timing 66 8-bit Timer Operation (timers 2, 3) Chapter 4 Timer Functions Clock PWM output Figure 4-2-5 PWM Output Timing (when TM2OC register is X'00') Matches TM2OC register Overflow www.DataSheet4U.com Binary counter 2 PWM output Figure 4-2-6 PWM Output Timing (when TM2OC register is X'FF') 8-bit Timer Operation (timers 2, 3) 67 Chapter 4 Timer Functions The clock source for the serial interface has a frequency that is 1/2 of the overflow output of timer 3. For serial interface settings, refer to the chapter on serial functions. Serial Transfer Clock Function(timer 3) Settings for the serial transfer clock function are listed below. (1) (2) (3) (4) (5) (6) (7) (8) Set the TM3EN flag of the timer 3 mode register (TM3MD) to "0" to stop the count operation of timer 3. Set the SC0CK1 and SC0CK0 flags of the serial interface 0 mode register 1 (SC0MD1) to select 1/2 of the timer 3 overflow frequency as the clock source. Set the TM3CK2 to 0 flags of the TM3MD register to select fosc, fs, fs/4, or fs/16 as the clock source. Set the TM3PWM flag of the TM3MD register to "0" to select timer 3 output. Set a value in compare register 3 (TM3OC). Set the TM3EN flag of the TM3MD register to "1" to start the timer. When timer 3 begins operation, binary counter 3 counts upward from X'00'. When the value of binary counter 3 matches that of the TM3OC register, the timer 3 interrupt request flag is set, the value of binary counter 3 is reset to X'00', and counting begins again. Cascade Connection Function (timer 2 + timer 3) Settings for the cascade connection function are listed below. Timer 2 and timer 3 are connected to operate as a 16-bit timer. www.DataSheet4U.com (1) (2) (3) (4) (5) (6) (7) (8) (9) Disable the timer 2 interrupt. (10) Set the TM2EN flag of the timer 2 mode register (TM2MD) to "0" to stop the count operation of timer 2. Set the TM3EN flag of the timer 3 mode register (TM3MD) to "0" to stop the count operation of timer 3. Set the TM2CK2 to 0 flags of the TM2MD register to select fs, fs/4, fx, or synchronized fx as the clock source. Use the TM3CK2 to 0 flags of the TM3MD register to set the clock source as a cascade connection with timer 2. Set the TM2PWM flag of the TM2MD register to "0" to select normal timer operation. Set values in compare register 2 (TM2OC) and compare register 3 (TM3OC). Set the TM2EN flag of the TM2MD register to "1" to start the timer. Set the TM3EN flag of the TM3MD register to "1" to start the timer. When timers 2 and 3 begin operation, the binary counters begin counting upward from X'0000' as a 16-bit counter. When the value of the 16-bit binary counter matches that of the 16-bit register (TM3OC+TM2OC), the timer 3 interrupt request flag is set, the value of the 16-bit binary counter is reset to X'0000', and counting begins again. Use a 16-bit access instruction to set the (TM3OC+TM2OC) register. 68 8-bit Timer Operation (timers 2, 3) www.DataSheet4U.com Chapter 4 Timer Functions 4-3 16-bit Timer Operation (timer 4) 4-3-1 Overview Timer 4 is a 16-bit programmable counter that can be used as an event counter. A signal with a frequency of 1/2 of the timer 4 overflow signal can be output from the TM4IO pin. An input capture function and pulse added type PWM output function can also be used. 4-3-2 Operation Timer Operation Settings for timer operation are listed below. (1) (2) (3) (4) (5) (6) (7) Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" to stop the count operation of timer 4. Set the TM4CK2 to 0 flags of the TM4MD register to select fosc, fs/4, or fs/16 as the clock source. Set the TM4PWM flag of the TM4MD register to "0" to select 16-bit timer operation. Set a value in compare register 4 (TM4OCH, TM4OCL). Set the TM4EN flag of the TM4MD register to "1" to start the timer. When timer 4 begins operation, binary counter 4 counts upward from X'0000'. When the value of binary counter 4 matches that of the TM4OCH and TM4OCL registers, the timer 4 interrupt request flag is set, the value of binary counter 4 is reset to X'0000', and counting begins again. When servicing an interrupt, reset the timer 4 interrupt request flag before operating timer 4. During a count operation, be careful if the value set in TM4OCH and TM4OCL is smaller than the value of binary counter 4, since the count-up operation will continue until overflow occurs. 16-bit Timer Operation (timer 4) 69 Chapter 4 Timer Functions Clock TM4EN Write to registers TM4OCH, TM4OCL Binary counter 4 04 05 06 07 08 09 00 Figure 4-3-1 Binary Counter 4 (TM4BC) Count Timing www.DataSheet4U.com If the TM4EN flag of the TM4MD register is changed simultaneously with other bits, the switching operation may cause binary counter 4 to be incremented. If the value of the TM4OCH, TM4OCL register is overwritten while timer 4 has stopped counting, binary counter 4 will be reset to X'0000'. 70 16-bit Timer Operation (timer 4) www.DataSheet4U.com Chapter 4 Timer Functions Event Count Function Settings for the event count function are listed below. (1) (2) (3) (4) (5) (6) (7) Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" to stop the count operation of timer 4. Use the TM4CK2 to 0 flags of the TM4MD register to select TM4IO input or synchronized TM4IO input as the clock source. Set the TM4PWM flag of the TM4MD register to "0" so that 16-bit timer operation is selected. Set a value in compare register 4 (TM4OCH, TM4OCL). Set the TM4EN flag of the TM4MD register to "1" to start the timer. When timer 4 begins operation, binary counter 4 will count upward from X'0000'. When the value of binary counter 4 matches that of the TM4OCH and TM4OCL registers, the timer 4 interrupt request flag is set, and the binary counter 4 is reset to X'0000' and begins to count upward again. If TM4IO input is selected as the clock source and the value of binary counter 4 is to be read during operation, select synchronized TM4IO input to avoid reading data that may be incomplete during count-up transitions. However, with synchronized TM4IO input, it is not possible to return from STOP/HALT modes. When synchronized TM4IO is selected, the timer 4 clock source is synchronized with the system clock after a transition of the TM4IO input signal. Timer 4 counts upward based on a signal synchronized to the system clock. Therefore, correct values can be read from binary counter 4. Figure 4-3-2 Timer 4 Event Counter Timing (when synchronous TM4IO CPU system clock (fs) TM4IO input Synchronous circuit output Binary counter n n+1 input is selected) 16-bit Timer Operation (timer 4) 71 Chapter 4 Timer Functions Timer Pulse Output Function The period of the output signal from the port is 1/2 of the period set in the TM4OCH, TM4OCL register. Settings for the timer pulse output function are listed below. (1) (2) (3) (4) (5) (6) (7) (8) Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" so that the count operation of timer 4 is stopped. Set bit 4 of the port 1 output/input mode register (P1OMD) to the special function pin setting. Bit 4 of port 1 will be specified as the pulse output pin. Use the TM4CK2 to 0 flags of the TM4MD register to select fosc, fs/4, or fs/16 as the clock source. Set the TM4PWM flag of the TM4MD register to "0" so that 16-bit timer operation is selected. Set a value in compare register 4 (TM4OCH, TM4OCL). Set the TM4EN flag of the TM4MD register to "1" to start the timer. When timer 4 begins operation, binary counter 4 will count upward from X'0000'. When the value of binary counter 4 matches that of the TM4OCH and TM4OCL registers, the timer 4 interrupt request flag is set, and the binary counter 4 is reset to X'0000' and begins to count upward again. Matches TM4OCH, TM4OCL register www.DataSheet4U.com Binary counter 4 TM4OUT Figure 4-3-3 Timer Pulse Output Timing 72 16-bit Timer Operation (timer 4) www.DataSheet4U.com Chapter 4 Timer Functions Pulse Added Type PWM Output Function If bit 4 of port 1 is to be used as a PWM output pin, set the P1DIR and P1PLU registers. In the pulse added method, a 1-bit output is appended to the basic component of the 8-bit PWM output. Precise control is possible based on the number of PWM repetitions (256 times) to which this bit is appended. Settings for the pulse added type PWM output function are listed below. (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" to stop the count operation of timer 4. Set bit 4 of the port 1 output/input mode register (P1OMD) to the special function pin setting. Bit 4 of port 1 will be specified as the PWM output pin. Use the TM4CK2 to 0 flags of the TM4MD register to select fosc, fs/4, or fs/16 as the clock source. The period of the output waveform is determined based on the clock source. Set the TM4PWM flag of the TM4MD register to "1" so that PWM operation is selected. Set a value in the lower 8 bits of compare register 4 (TM4OCL). The high interval of the output waveform is determined based on the value of the lower 8 bits of compare register 4 (TM4OCL). Set the position of the added pulse in the upper 8 bits of compare register 4 (TM4OCH). Set the TM4EN flag of the TM4MD register to "1" to start the timer. When timer 4 begins operation, binary counter 4 will count upward from X'00'. A high-level signal is output from the port beginning when binary counter 4 starts counting from X'00' and ending when the value of binary counter 4 matches the value set in the TM4OCL register. When the value of binary counter 4 matches that of the TM4OCL register, a lowlevel signal is output from the port. Binary counter 4 continues to count upward until X'FF' is reached. At the next countup cycle, the value of binary counter 4 is reset to X'00', and counting begins again. A high-level signal is output from the port. PWM4 output is fixed at L with X'FF' set at the lower 8 bits(TM40CL) of compare register. Use of timer 4 at PWM mode disables setting of X'FF' att TM4OCL register. Use a 16-bit access instruction to set the TM4OCH, TM4OCL register. ,, ,, ,, Basic PWM components Added pulse Tn=X'00' Tn=X'01' Tn=X'02' , Tn=X'03' Repeated 256 times ,, ,, , : Added pulse Tn=X'04' Tn=X'FF' Figure 4-3-4 Pulse Added Type PWM Output 16-bit Timer Operation (timer 4) 73 Chapter 4 Timer Functions [ 5-2-3 "Serial Interface Setting the Added Pulse Position Transfer Timing"] The upper 8 bits of compare register 4 (TM4OCH) set the position of the added pulse. If the TM4OCH register is set to X'00', an additional bit is not appended to the basic PWM component. If the TM4OCH register is set to X'FF', an additional bit is repeatedly appended to the 255 basic PWM components during the period. The relation between the value set in the TM4OCH register and the added pulse is shown in the table below. If X'03' is set in the TM4OCH register, bits are appended to pulse positions for X'01' and X'02', shown in table 4-3-1. The relation between the value set in the TM4OCH register and the position of the added bit is shown in figure 4-3-5. Table 4-3-1 Pulse-Added PWM OutputFigure Value Set in TM4OCH Register Added Pulse Position (value of Tn) 00000000 X'80' X'40',X'C0' X'20',X'60',X'A0',X'E0' X'10',X'30',X'50',X'70',X'90',X'B0',X'D0',X'F0' X'08',X'18',X'28',X'38',X'48',X'58' . . . . .,X'E8',X'F8' X'04',X'0C',X'14',X'1C',X'24',X'2C' . . . . .,X'F4',X'FC' X'02',X'06',X'0A',X'0E',X'12',X'16' . . . . .,X'FA',X'FE' X'01',X'03',X'05',X'07',X'09',X'0B' . . . . .,X'FD',X'FF' 00000001 00000010 00000100 00001000 00010000 00100000 01000000 10000000 (MSB) www.DataSheet4U.com (LSB) Repeated 256 times TM4OCH Register setting 0 value X '00' X '40' X '80' X 'C0' X '01' X '02' X '04' X '08' X '10' PWM basic component Position of added pulse X'87' Position of added pulse X'88' Figure 4-3-5 Pulse Added Type PWM Output 74 16-bit Timer Operation (timer 4) X 'FF' Position of added pulse Chapter 4 Timer Functions Capture Function Settings for the capture function are listed below. (1) (2) (3) (4) (5) (6) (7) (8) (9) www.DataSheet4U.com (10) Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" to stop the count operation of timer 4. Use the TM4CK2 to 0 flags of the TM4MD register to select fosc, fs/4, or fs/16 as the clock source. Use the T4ICTS1 and T4ICTS0 flags of the TM4MD register to select IRQ2, IRQ1, or IRQ0 as the input capture trigger. Set the REDGn flag of the external interrupt control register to specify the valid edge for the interrupt selected as the TM4 input capture trigger. Set the TM4PWM flag of the TM4MD register to "1" to select 16-bit timer operation. Set a value in compare register 4 (TM4OCH, TM4OCL). Set the TM4EN flag of the TM4MD register to "1" to start the timer. When timer 4 begins operation, binary counter 4 will count upward from X'0000' until it reaches the value set in compare register 4. If the binary counter is to be used as a free-running counter that counts from X'0000' to X'FFFF', set the compare register 4 to X'FFFF'. When the value of binary counter 4 matches that of the TM4OCH, TM4OCL register, the timer 4 interrupt request flag is set, binary counter 4 is reset to X'0000', and counting begins again. If the external interrupt selected as the TM4 input capture trigger is received during timer 4 operation, the value of binary counter 4 will be written into the input capture register (TM4ICH, TM4ICL). Setting a value in compare register 4, clears binary counter 4. If the event occurs before a read, that data will be overwritten. 16-bit Timer Operation (timer 4) 75 Chapter 4 Timer Functions 4-4 8-bit Timer Operation (timer 5) 4-4-1 Overview Timer 5 is an 8-bit timer that can have fosc, fs/4, fx, or time base output as its clock source. 4-4-2 Operation Timer Operation When servicing an interrupt, reset the timer 5 interrupt request flag before starting timer 5. www.DataSheet4U.com When choosing either time base timer output or time base timer synchronized output for the timer 5 clock source, the time base must be set up. During a count operation, be careful if the value set in TM5OC is smaller than the value of binary counter 5, since the count-up operation will continue until overflow occurs. If fx input is selected as the clock source and the value of binary counter 5 is to be read during operation, select synchronized fx input to avoid reading data that may be incomplete during countup transitions. However, with synchronized fx input, it is not possible to return from STOP/HALT modes. Settings for timer operation are listed below. (1) Set the TM5CLRS flag of the timer 5 mode register (TM5MD) to "0." (2) Use the TM5CK3 to 1 flags of the TM5MD register to select fosc, fs/4, fx, synchronized fx, time base timer output, or time base timer synchronized output as the clock source. (3) Set a value in compare register 5 (TM5OC). At this time, if the TM5CLRS flag is "0," binary counter 5 will be initialized to X'00'. (4) Binary counter 5 (TM5OC) counts upward from X'00'. (5) When the value of binary counter 5 matches that of the TM5OC register, the timer 5 interrupt request flag is set, the binary counter is reset to X'00', and counting begins again. If the TM5CLRS flag of the TM5MD register is set to "0," binary counter 5 will be initialized every time data in the TM5OC register is overwritten. Timer 5 interrupts are disabled in this mode. If timer 5 interrupts are to be used, the TM5CLRS flag must be reset to "1" after writing to the TM5OC register. Timer 5 operation cannot be halted. 76 8-bit Timer Operation (timers 2, 3) Chapter 4 Timer Functions 4-5 Time Base Operation 4-5-1 Overview The clock source for the time base timer can be set to fosc or fx. Also, the interrupt period for time base timer (TBIRQ) can be set to 1/27, 1/28, 1/29, 1/210, or 1/213 of the clock source. 4-5-2 Operation Time Base Function Settings for the time base function are listed below. (1) Use the TM5CK0 flag of the timer 5 mode register (TM5MD) to select fosc or fx as the clock source. Use the TM5IR2 to 0 flags of the TM5MD register to select the time base timer interrupt source. When the selected time interval passes, the interrupt request flag of the time base interrupt control register (TBICR) is set. www.DataSheet4U.com (2) (3) Time base operation cannot be halted. Table 4-5-1 Base Time Settings 000 001 010 011 1XX 1 27 1 28 1 29 1 210 1 213 20MHz 6.4s 12.8s 25.6s 51.2s 409.6s 8.38MHz 15.2s 30.5s 61.0s 122.0s 976.4s 32.768kHz 3.9ms 7.8ms 15.6ms 31.2ms 250ms TM5IR2 to 0 Clock Source fosc fx Time Base Operation 77 www.DataSheet4U.com Chapter 4 Timer Functions 4-6 Watchdog Timer Operation 4-6-1 Overview The watchdog timer is controlled by the watchdog control register (WDCTR) and can be used for runaway program detection. 4-6-2 Setup and Operation (1) The upper 2 bits of the watchdog timer are cleared when the WDEN flag is set to "0." Therefore, if WDEN flag is set to 0 when an uppermost bit of a watchdog timer is 1, WDT interrupt occurs depending on the timing of this clear the watchdog timer may be reset at 1/4TWD. If the WDEN bit is to be repeatedly cleared and set at regular intervals, those operations should be performed within 1/4 of the TWD period. (2) (3) Set the WDEN flag of the watchdog timer control register (WDCTR) to "1" to start the watchdog timer. Operate the watchdog timer by clearing the WDEN flag to "0" within the fixed amount of time (TWD), and then resetting the WDEN flag to "1." If the WDEN flag is not cleared, a WDT interrupt will be generated after the fixed amount of time passes. When an illegal operation is detected, the program encoded at the location of the WDT interrupt routine is executed. TWD is set by the ROM option as fs/216, fs/218, or fs/220. Illegal operation detection period vs. WDEN clear period is shown by the following formula: Illegal operation detection period > [WDEN clear period] x 4 When software resetting is not triggered by WDT interrupt, hardware resetting (low level output at the reset terminal) takes place at the next WDT interrupt. 78 Watchdog Timer Operation www.DataSheet4U.com Chapter 4 Timer Functions 4-7 Remote Control Output Operation 4-7-1 Overview A remote control carrier pulse can be generated using the overflow of timer 3. Two duty ratios of 1/2 or 1/3 can be selected. 4-7-2 Setup and Operation (1) (2) (3) (4) (5) Set the RMOEN flag of the remote control carrier output control register (RMCTR)to "0" so that the remote control carrier output is switched off. Set timer 3 to select the base period of the remote control carrier (the width that the remote control carrier output pulse is held at a high level). Set the RMDTY0 flag of the RMCTR register to select the carrier duty. Set the P10 output data to "0" and set P10 to the output mode. And select the remote control carrier output by setting the TMORM flag of the RMCTR register to "0". The RMOEN flag of the RMCTR register controls whether the remote control carrier output is on or off. Even if the carrier output is at a high level, and the RMOEN flag is set to "0" (off), the carrier waveform will be maintained by the synchronous circuit Set bit 0 of the P1OMD register to "1" at the same time the remote control output is switched on, and to "0" at the same time the remote control output is switched off. Base period set by TM3 RMOEN Output on Output off RMOUT (1/3 duty) Figure 4-7-1 Remote Control Carrier Output Waveform Remote Control Output Operation 79 Chapter 4 Timer Functions 4-8 Buzzer Output 4-8-1 Buzzer Output Setup and Operation The square wave having a frequency 1/29 to 1/212 of the system clock can be output from the P06/BUZZER pin. (1) (2) (3) (4) www.DataSheet4U.com 80 Buzzer Output Set the BUZOE flag of the oscillation stabilization wait control register (DLYCTR) to "0" so that the buzzer output is turned off. Set the buzzer output frequency with the BUZCK1 and BUZCK0 flags of the DLYCTR. Set the BUZOE flag of the DLYCTR register to "1" and set P06 to the buzzer output mode. The BUZOE flag of the DLYCTR register controls whether the buzzer output is ON or OFF. www.DataSheet4U.com Chapter 4 Timer Functions 4-9 Timer Function Control Registers 4-9-1 Overview 19 registers control the timers. See table 4-9-1. Table 4-9-1 Timer Control Registers Name Address R/W Function TM2OC X'03F72' R/W TM2BC X'03F62' R TM2MD X'03F82' R/W Timer 2 mode register TM3OC X'03F73' R/W Compare register 3 Compare register 2 Binary counter 2 TM3BC X'03F63' R TM3MD X'03F83' R/W Binary counter 3 Timer 3 mode register TM4OCL X'03F74' R/W Compare register 4 (lower 8 bits) TM4OCH X'03F75' R/W Compare register 4 (upper 8 bits) TM4BCL X'03F64' R Binary counter 4 (lower 8 bits) TM4BCH X'03F65' R Binary counter 4 (upper 8 bits) TM4ICL X'03F66' R Input capture register (lower 8 bits) TM4ICH X'03F67' R Input capture register (upper 8 bits) TM4MD X'03F84' R/W Timer 4 mode register TM5OC X'03F78' R/W Compare register 5 TM5BC X'03F68' R Binary counter 5 TM5MD X'03F88' R/W Timer 5 mode register WDCTR X'03F02' R/W Watchdog timer control register DLYCTR X'03F03' R/W Oscillation stabilization wait control register RMCTR X'03F89' R/W Remote control carrier output control register R/W: Readable and writable R: Read only Overview 81 Chapter 4 Timer Functions 4-9-2 Programmable Timer/Counters Timers 2~5 all contain a programmable 8-bit timer/counter (16-bit in timer 4). Programmable timer/counters consist of a compare register and a binary counter. (1) Compare register 2 (TM2OC) 7 6 5 4 3 2 1 0 TM2OC7 TM2OC6 TM2OC5 TM2OC4 TM2OC3 TM2OC2 TM2OC1 TM2OC0 (at reset: undefined) Figure 4-9-1 Compare Register 2 (TM2OC: X'03F72', R/W) (2) Binary counter 2 (TM2BC) 7 6 5 4 3 2 1 0 TM2BC7 TM2BC6 TM2BC5 TM2BC4 TM2BC3 TM2BC2 TM2BC1 TM2BC0 (at reset: 00000000) www.DataSheet4U.com Figure 4-9-2 Binary Counter 2 (TM2BC: X'03F62', R) (3) Compare register 3 (TM3OC) 7 6 5 4 3 2 1 0 TM3OC7 TM3OC6 TM3OC5 TM3OC4 TM3OC3 TM3OC2 TM3OC1 TM3OC0 (at reset: undefined) Figure 4-9-3 Compare Register 3 (TM3OC: X'03F73', R/W) (4) Binary counter 3 (TM3BC) 7 6 5 4 3 2 1 0 TM3BC7 TM3BC6 TM3BC5 TM3BC4 TM3BC3 TM3BC2 TM3BC1 TM3BC0 (at reset: 00000000) Figure 4-9-4 Binary Counter 3 (TM3BC: X'03F63', R) 82 Timer Function Control Registers Chapter 4 Timer Functions (5) Compare register 4 (TM4OCL) (lower 8 bits) 7 6 5 4 3 2 1 0 TM4OCL7 TM4OCL6 TM4OCL5 TM4OCL4 TM4OCL3 TM4OCL2 TM4OCL1 TM4OCL0 (at reset: undefined) Figure 4-9-5 Compare Register 4 (TM4OCL: X'03F74', R/W) (6) Compare register 4 (TM4OCH) (upper 8 bits) 7 6 5 4 3 2 1 0 TM4OCH7 TM4OCH6 TM4OCH5 TM4OCH4 TM4OCH3 TM4OCH2TM4OCH1 TM4OCH0 (at reset: undefined) Figure 4-9-6 Compare Register 4 (TM4OCH: X'03F75', R/W) (7) Binary counter 4 (TM4BCL) (lower 8 bits) 7 6 5 4 3 2 1 0 TM4BCL7 TM4BCL6 TM4BCL5 TM4BCL4 TM4BCL3 TM4BCL2 TM4BCL1 TM4BCL0 (at reset: 00000000) www.DataSheet4U.com Figure 4-9-7 Binary Counter 4 (TM4BCL: X'03F64', R) (8) Binary counter 4 (TM4BCH) (upper 8 bits) 7 6 5 4 3 2 1 0 TM4BCH7 TM4BCH6 TM4BCH5 TM4BCH4 TM4BCH3 TM4BCH2 TM4BCH1 TM4BCH0 (at reset: 00000000) Figure 4-9-8 Binary Counter 4 (TM4BCH: X'03F65', R) Timer Function Control Registers 83 Chapter 4 Timer Functions (9) Input capture register (TM4ICL) (lower 8 bits) 7 6 5 4 3 2 1 0 TM4ICL7 TM4ICL6 TM4ICL5 TM4ICL4 TM4ICL3 TM4ICL2 TM4ICL1 TM4ICL0 (at reset: undefined) Figure 4-9-9 Input Capture Register (TM4ICL: X'03F66', R) (10) Input capture register (TM4ICH) (upper 8 bits) 7 6 5 4 3 2 1 0 TM4ICH7 TM4ICH6 TM4ICH5 TM4ICH4 TM4ICH3 TM4ICH2 TM4ICH1 TM4ICH0 (at reset: undefined) Figure 4-9-10 Input Capture Register (TM4ICH: X'03F67', R) (11) Compare register 5 (TM5OC) 7 6 5 4 3 2 1 0 TM5OC7 TM5OC6 TM5OC5 TM5OC4 TM5OC3 TM5OC2 TM5OC1 TM5OC0 (at reset: undefined) www.DataSheet4U.com Figure 4-9-11 Compare Register 5 (TM5OC: X'03F78', R/W) (12) Binary counter 5 (TM5BC) 7 6 5 4 3 2 1 0 TM5BC7 TM5BC6 TM5BC5 TM5BC4 TM5BC3 TM5BC2 TM5BC1 TM5BC0 (at reset: 00000000) Figure 4-9-12 Binary Counter 5 (TM5BC: X'03F68', R) 84 Timer Function Control Registers www.DataSheet4U.com Chapter 4 Timer Functions 4-9-3 Timer Mode Registers Four readable and writable 6-byte timer mode registers. Control timers 2, 3, 4, 5, and the time base. (1) Timer 2 mode register (TM2MD) TM2MD 7 6 5 4 - - - TM2EN 3 2 1 0 (at reset: ---00XXX) TM2PWM TM2CK2 TM2CK1 TM2CK0 TM2CK2 TM2CK1 TM2CK0 X 0 0 1 1 1 Clock source selection 0 fs 1 fs/4 0 fx * 1 TM2IO input 0 Synchronous fx * 1 Synchronous TM2IO input * 48QFH package only TM2PWM TM2 operation mode selection 0 Normal timer operation 1 PWM operation TM2EN TM2 count control 0 Halt the count 1 Operate the count Figure 4-9-13 Timer 2 Mode Register (TM2MD: X'03F82', R/W) Timer Function Control Registers 85 Chapter 4 Timer Functions (2) Timer 3 mode register (TM3MD) TM3MD 7 6 5 - - - 4 3 2 TM3EN TM3PWM TM3CK2 1 0 TM3CK1 TM3CK0 (at reset: ---00XXX) TM3CK2 TM3CK1 fosc 1 fs/4 0 fs/16 1 TM3IO input 0 x Cascade connection with timer 2 1 1 Synchronous TM3IO input 0 1 TM3PWM P13 output selection during TM2 PWM operation 0 Timer 3 output 1 Timer 2 PWM output TM3EN www.DataSheet4U.com Clock source selection 0 0 1 TM3CK0 TM3 count control 0 Halt the count 1 Operate the count Figure 4-9-14 Timer 3 Mode Register (TM3MD: X'03F83', R/W) 86 Timer Function Control Registers Chapter 4 Timer Functions (3) Timer 4 mode register (TM4MD) TM4MD 7 6 - TM4EN 5 4 TM4PWM T4ICTS1 3 2 1 0 T4ICTS0 TM4CK2 TM4CK1 TM4CK0 (at reset: -0000XXX) TM4CK2 TM4CK1 0 0 1 TM4CK0 Clock source selection 0 fosc 1 fs/4 0 fs/16 1 1 TM4IO input Synchronous TM4IO input 1 1 T4ICTS1 T4ICTS0 TM4 input capture trigger selection 0 Disable input capture operation 1 IRQ0 0 IRQ1 1 IRQ2 0 1 TM4PWM TM4 operation mode selection www.DataSheet4U.com 0 16-bit timer operation 1 PWM operation TM4EN TM4 count control 0 Halt the count 1 Operate the count Figure 4-9-15 Timer 4 Mode Register (TM4MD: X'03F84', R/W) Timer Function Control Registers 87 Chapter 4 Timer Functions (4) Timer 5 mode register (TM5MD) 7 TM5MD 6 TM5CLRS TM5IR2 5 4 3 2 1 0 TM5IR1 TM5IR0 TM5CK3 TM5CK2 TM5CK1 TM5CK0 (at reset: 0XXXXXX0) TM5CK0 Time base timer clock source selection 0 fosc 1 (Use Prohibited) fx * * 48QFH package only TM5CK3 TM5CK2 X 0 0 1 1 TM5IR2 TM5IR1 www.DataSheet4U.com 0 0 1 1 x TM5CK1 Timer 5 clock source selection 0 fosc 1 fs/4 0 (Use Prohibited) 1 0 Output of time base timer (Use Prohibited) 1 Synchronous time base timer output Time base timer TM5IR0 interrupt period selection 0 1/27 of the clock source 1 1/28 of the clock source 0 1 1/29 of the clock source 1/210 of the clock source x 1/213 of the clock source TM5CLRS Binary counter 5 clear selection flag 0 Enable initialization of TM5BC during a write to TM5OC 1 Disable initialization of TM5BC during a write to TM5OC If TM5CLRS=0, TM5IRQ is disabled. Figure 4-9-16 Timer 5 Mode Register (TM5MD: X'03F88', R/W) 88 Timer Function Control Registers www.DataSheet4U.com Chapter 4 Timer Functions 4-9-4 Timer Control Registers (1) Watchdog timer control register (WDCTR) WDCTR 7 6 5 4 3 2 1 0 - - - - - - - WDEN (at reset: -------0) WDEN Watchdog timer enable 0 Clear watchdog timer/disable operation 1 Enable WDT timer Figure 4-9-17 Watchdog Timer Control Register (WDCTR: X'03F02', R/W) (2) Oscillation stabilization wait control register (DLYCTR) 7 DLYCTR 6 5 BUZOE BUZCK1 BUZCK0 4 3 2 - - - 1 0 DLYS1 DLYS0 (at reset: 0XX---00) DLYS1 DLYS0 Oscillation stabilization wait period setting 0 1/214 of the system clock (fs) 1 1/210 of the system clock (fs) 1 0 1/26 of the system clock (fs) 1 1 Disable use 0 After reset is released, the oscillation stabilization wait period is fixed at 1/215. BUZCK1 BUZCK0 0 1 Buzzer output frequency selection 0 1/212 of the system clock (fs) 1 1/211 of the system clock (fs) 0 1/210 of the system clock (fs) 1 1/29 of the system clock (fs) BUZOE P06 output selection 0 P06 port output 1 P06 buzzer output Figure 4-9-18 Oscillation Stabilization Wait Counter Control Register (DLYCTR: X'03F03', R/W) Timer Function Control Registers 89 Chapter 4 Timer Functions (3) Remote control carrier output control register (RMCTR) RMCTR 7 6 5 4 3 2 1 0 - - - - RMOEN - RMDTY0 - (at reset: ---00XX0) Must be set to "0." Remote control carrier output duty selection RMDTY0 0 1/2 duty 1 1/3 duty Must be set to "0." RMOEN Enable remote control carrier output 0 Output low level 1 Output remote control carrier Must be set to "0." Figure 4-9-19 Remote Control Carrier Control Register (RMCTR: X'03F89', R/W) www.DataSheet4U.com 90 Timer Function Control Registers ?? @@@?he O26Xe @@Y?e?O26X?e @@@@@@@@@@@@@@@@@@@@@)e ?@@@@@@@@@@@@@@@@@@@)?e ?I'Xg@Xh @Khf?O26X?e N)X?e?J@@h @@@@@@@@@@@@@@@@@@)?e ?@)KeO&Y?eO26Xe @@ @@H?e @@@@@@@@@@@@@@@@@@@@@)e @@ @@f @@@@@@@@@@@@@@@@@@f @@@@@@@@@@@@@@g @@ @@he@@g @@f?@@@e@@@?g @@he@@g @@f?@@He@@Y?O)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @@he@@g @@f?@@?e@@h @@he@@g @@f?@@?e@@eO)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @0M?e@@e?I4@g ?J@5f?@@?e@@h @@gO26Xe ?7@Hf?@5?e@@h @@@@@@@@@@@@@@@@@@@@@)e ?@5?'@@@@@H?e@@eO26Xe @@hf ?@H?V+MW@5f@@@@@@@)e @@hf J5fW&(Yf@@h @@hf .Ye?O&0Y?f@@h @@hf @0M?g@@h W&g O2@@6Kf O2@@6Kf O2@@6Kf ?O2@@@e ?W&@g ?@@(MI'@@?e ?@@(MI'@@?e ?@@(MI'@@?e ?W2@0Mf W&@@g J@(YeV'@Le J@(YeV'@Le J@(YeV'@Le W&(Mg .Y@@g 7@H?e?N@1e 7@H?e?N@1e 7@H?e?N@1e ?W&(Y?g @@g @@g@@e @@g@@e @@g@@e ?7@Hh @@g @@g@@e @@g@@e @@g@@e J@@=h @@g 7@S@@@6Kf @@g 3@L?e?J@@e N@)XeW&@@e 3@L?e?J@@e N@)XeW&@@e 3@L?e?J@@e N@)XeW&@@e @@(M?I'@@?e @@g @@H?eV'@Le @@g ?@@)KO&@@@e I4@@0Y@5e ?@@)KO&@@@e I4@@0Y@5e ?@@)KO&@@@e I4@@0Y@5e @@f?N@1e @@g ?J@He ?J@He ?J@He @@g@@e @@g W&5?e W&5?e W&5?e @@g@@e @@g ?W&(Y?e ?W&(Y?e ?W&(Y?e 3@L?e?J@5e @@g O&(Yf O&(Yf O&(Yf N@)XeW&@He ?@@?e @@g O2@0Y?f O2@0Y?f O2@0Y?f ?@@?e ?@@)KO&@@?e ?@@?e @@@@@@f ?@@0M?g ?@@0M?g ?@@0M?g ?@@?e I4@@0Mf W&g ?O2@@@e ?W&@g ?W2@0Mf W&@@g W&(Mg .Y@@g ?W&(Y?g @@g ?7@Hh @@g J@@=h @@g @@g 7@S@@@6Kf @@(M?I'@@?e @@g @@g @@H?eV'@Le @@f?N@1e @@g @@g@@e @@g @@g @@g@@e 3@L?e?J@5e @@g N@)XeW&@He @@g ?@@)KO&@@?e @@@@@@f I4@@0Mf www.DataSheet4U.com ?? ? ?? ? W&g O2@6X?f ? O2@6X?f ?W&@g W2@@@@)Xf W2@@@@)Xf ? W&@@g 7(M?I'@1f 7(M?I'@1f ? .Y@@g (Ye?N@@f (Ye?N@@f ? ?J@5f @@g ?J@5f @@g W&(Yf ?@@?e?? W&(Yf @@g ?W&@g @@g ?&@@)Xf ?@@?e?? ?W&@g ?&@@)Xf @@g ?I')X?e ? ?I')X?e @@g N@1?e N@1?e ?? @@g ?@@?e ?@@?e @@g ?@@?e ?@@?e ?? @@g ?@5?e ?@5?e @@g @6X?eJ@H?e @6X?eJ@H?e ? @@g 3@)K?O&@f ?@@?e? 3@)K?O&@f @@@@@@f V4@@@0M?f ?@@?e? V4@@@0M?f ? ? ? ? ? ? ? W&g ?W&@g W&@@g .Y@@g @@g @@g @@g @@g @@g @@g @@g @@g @@g @@g @@g @@@@@@f W26Xf @@6Khe'6X?e 7<B1f ?I'@@?f?'6XV'1?e 3=C5f V4@?f?V'1?V'?e W2@@6XfV40Yf V'g ?W&(MI')X?he W&(YeV')Xhe ?@@6K? ?W&(Y?e?V')X?h I'@@hfW.f W&(YgV')Xh ?@K?f?O2@@@@@@@@@1?e ?O26X?e ?V4@he?W&Hf @?&@H?g?V')X?g W&5?f 3@@5heV')Xg ?W&(Y?f V40Yhe?V')K?f ?3@@@@@@@@0Mg?I@?e ?V40M? W&(Yg V'@6X?e ?W&(Y?g ?V'@)Xe O&(Yh V'@1e W2@(Y?h ?V4@e ?O&@0Yhe ?O2@(Mhf ?@KO2@@0Y?hf ?3@@@0M?hg ?V40M? O2@@6Kf ?@@(MI'@@?e J@(YeV'@Le 7@H?e?N@1e @@g@@e @@g@@e 3@L?e?J@@e N@)XeW&@@e ?@@)KO&@@@e I4@@0Y@5e ?J@He W&5?e ?W&(Y?e O&(Yf O2@0Y?f ?@@0M?g W&g ?W&@g W&@@g .Y@@g @@g @@g @@g @@g @@g @@g @@g @@g @@g @@g @@g @@@@@@f Chapter 5 5 Serial Functions 91 Chapter 5 Serial Functions 5-1 Overview The MN101C117 contains a serial interface that can operate in synchronous and simple UART modes. An overview of serial functions is shown below. Table 5-1-1 Overview of Serial Functions Serial 0 Interrupt SC0ICR Synchronous Simple UART Clock selection www.DataSheet4U.com 1/8 period of clock 92 Overview fs/2 fs/4 fs/16 BC3X1/2 External fs/2 fs/4 fs/16 BC3x1/2 1/2 of timer 3 overflow SBT0/P02 SBI0/RXD/P01 2 M U X SC0TRI SC0ERE SC0BRKF SC0CK0 SC0CK1 SC0CKM - - SC0MD1 1/8 M U X 7 0 M U X M U X SC0LNG0 SC0LNG1 SC0LNG2 SC0STE SC0DIR SC0CE0 SC0CE1 - 8 7 SWAP 8 8 3 Bit counter Receive Append control transmit parity check control parity Shift register 8 SC0TRB Receive buffer SC0RXB 8 SC0MD0 0 Break receive control Stop bit detection Start condition detection 7 0 www.DataSheet4U.com SBO0/P00 SC0SBTS SC0SBIS SC0SBOS SC0SBTM SC0SBOM SC0IOM - - SC0MD3 - SC0ORE SC0PEK SC0FEF - - SC0CMD SC0BSY SC0CTR ORE detection control 7 0 Start condition transmission SC0NPE SC0PM0 SC0PM1 SC0FM0 SC0FM1 SC0BRKE - - SC0MD2 7 0 SC0IRQ SBO0/TXD1/P00 Chapter 5 Serial Functions Figure 5-1-1 Serial 0 Block Diagram Overview 93 Chapter 5 Serial Functions 5-2 Synchronous Serial Interface 5-2-1 Overview A serial interface begins operation when data is written to the shift buffer. A bit counter is incremented at each 1-bit transfer. The transfer is complete when the counter overflows. Bit transfers of an arbitrary 1 to 8 bits can be performed. The transfer bit count must be set before performing the transfer. 5-2-2 Setup and Operation Transmission www.DataSheet4U.com (1) (2) (3) (4) [ Section 5-2-3, "Serial (5) Interface Transfer Timing"] (6) Select the synchronous serial interface by setting the SC0CMD flag of the serial interface 0 control register (SC0CTR) to "0." Select the transfer bit count with the SC0LNG2 to 0 flags of the serial interface 0 mode register 0 (SC0MD0). The transfer bit count can be set as 1 to 8 bits. Specify whether the start condition is enabled or disabled with the SC0STE flag of the SC0MD0 register. Specify the first bit to be transferred (MSB first or LSB first) with the SC0DIR flag of the SC0MD0 register. Select the valid edge of the clock signal with the SC0CE1 to 0 flags of the SC0MD0 register. When the clock source is an internal clock: * Select the clock source with the SC0CK1 to 0 flags of serial interface 0 mode register 1 (SC0MD1). * Set the SC0CKM flag of the SC0MD1 register specify whether or not the clock source frequency will be divided by 8. * Select serial clock operation by setting the SC0SBTS flag of the serial interface 0 mode register 3 (SC0MD3) to "1." * Set the SC0SBTM flag of the SC0MD3 register. * Set bit 0 of the port 0 direction control register (P0DIR) to the output mode. * Set bit 0 of the port 0 pull-up resistor control register (P0PLU). 94 Synchronous Serial Interface www.DataSheet4U.com Chapter 5 Serial Functions When the clock source is an external clock (SBT0 pin input): (7) (8) (9) (10) (11) (12) * Set the SC0SBTM flag of the SC0MD3 register. * Set bit 2 of the P0DIR register to input mode. * Set the P0PLU register, if necessary. Select the SC0SBOM flag of the SC0MD3 register. Select the SC0IOM flag of the SC0MD3 register. Select serial communication by setting the SC0SBOS flag of the SC0MD3 register to "1." Set transmit data to serial interface 0 transmit/receive shift register (SC0TRB). This will start the serial transmission. When serial transmission begins, the SC0BSY flag of the SC0CTR register is set to "1," indicating that a serial transfer is in progress. When the serial transmission has completed, the SC0BSY flag of the SC0CTR register is cleared to "0" and the SC0 transfer complete interrupt request flag is set to "1." The SC0TRI flag of SC0MD1 register 1 is cleared to "0." After the transfer is complete, the transfer bit count in the SC0LNG2 to 0 flags of the SC0MD0 register will be changed. Except in an 8-bit transfer, reset the transfer bit count at the time of the next transmission. When switching from transmission to reception, set the SC0SBOS flag of the SC0MD3 register to "0" and then set the SC0SBIS flag to "1." Do not change both of these flags at the same time. The SC0SBTS flag of the SC0MD3 register must be set to "1" before the SC0SBOS flag of the SC0MD3 register is set to "1." When the serial port is enabled and the SC0CE1 to 0 flags of the SC0MD0 register are changed, the transfer bit count in the SC0LNG2 to 0 flags of the SC0MD0 register may be incremented. Enabling the start condition drives the SBO0 pin high for a fixed time interval (1/2 the clock source cycle) after the transmission is completed. If the start condition is disabled, the SBO0 pin will remain at the value of the of the last data bit. If the SC0IOM flag of the SC0MD3 register is set for a pin connection, the SBI0 pin can be used as a port. The SBO0 pin receives data during the input mode and transmits data during the output mode. The SC0LNG2 to 0 flags change at the opposite edge of the transmit data output edge. Serial interface 0 begins operation when the SC0SBOS flag or the SC0SBIS flag is set to "1." Set the SC0SBOS flag or the SC0SBIS flag after all conditions have been set. Synchronous Serial Interface 95 Chapter 5 Serial Functions SBT Clock SBO ts Start condition enabled SBO Start condition disabled Interrupt SC0BSY SC0LNG2 to 0 0 1 2 3 4 5 6 7 0 Figure 5-2-1 Synchronous Serial Interface Transmission Timing (falling edge) www.DataSheet4U.com Clock SBT SBO Start condition enabled SBO Start condition disabled Interrupt SC0BSY SC0LNG2 to 0 0 1 2 3 4 5 6 7 0 Figure 5-2-2 Synchronous Serial Interface Transmission Timing (rising edge) 96 Synchronous Serial Interface Chapter 5 Serial Functions Reception (1) (2) (3) (4) (5) (6) www.DataSheet4U.com (7) (8) (9) (10) Select the synchronous serial interface by setting the SC0CMD flag of the serial interface 0 control register (SC0CTR) to "0." Select the transfer bit count with the SC0LNG2 to 0 flags of the serial interface 0 mode register 0 (SC0MD0). The transfer bit count can be set as 1 to 8 bits. Specify whether the start condition is enabled or disabled with the SC0STE flag of the SC0MD0 register. Specify the first bit to be transferred (MSB first or LSB first) with the SC0DIR flag of the SC0MD0 register. Select the valid edge of the clock signal with the SC0CE1 to 0 flags of the SC0MD0 register. When the clock source is an internal clock: * Select the clock source with the SC0CK1 to 0 flags of serial interface 0 mode register 1 (SC0MD1). * Set the SC0CKM flag of the SC0MD1 register to specify whether or not the clock source frequency will be divided by 8. * Select serial clock pin operation by setting the SC0SBTS flag of the serial interface 0 mode register 3 (SC0MD3) to "1." * Set the SC0SBTM flag of the SC0MD3 register. * Set bit 2 of the port 0 direction control register (P0DIR) to the output mode (P02/SBT0 output mode). * If necessary, set bit 2 of the port 0 pull-up resistor control register (P0PLU) to add the pull-up resistor. When the clock source is an external clock (SBT0 pin input): * Set bit 2 of the P0DIR register to the input mode. * If necessary, set bit 2 of the P0PLU register. Select the SC0IOM flag of the SC0MD3 register. Select serial communication by setting the SC0SBIS flag of the SC0MD3 register to "1." (Reception data wait.) When the serial reception begins, the SC0BSY flag of the serial interface 0 control register (SC0CTR) is set to "1," indicating that a serial transfer is in progress. When the serial reception is complete, the SC0BSY flag of the SC0CTR register is cleared to "0" and the SC0 transfer complete interrupt request flag is set to "1." The SC0TRI flag of the SC0MD1 register is set to "1." After the transfer is complete, the transfer bit count in the SC0LNG2 to 0 flags of the SC0MD0 register will be changed. Except in an 8-bit transfer count, reset the transfer bit count at the time of the next reception. When switching from reception to transmission, set the SC0SBIS flag of the SC0MD3 register to "0" and then set the SC0SBOS flag to "1." Do not change both of these flags at the same time. When the serial port is enabled and the SC0CE1 to 0 flags of the SC0MD0 register are changed, the transfer bit count in the SC0LNG2 to 0 flags of the SC0MD0 register may by incremented. [ Section 5-2-3, "Serial Interface Transfer Timing"] If the start condition is enabled, the SC0LNG2 to 0 flags of the SC0MD0 register will be cleared when the start condition is received. In this case, the receive bit count is fixed at 8 bits. The SC0SBTS flag of the SC0MD3 register must be set to "1" before setting the SC0SBIS flag of the SC0MD3 register to "1." If the internal clock is selected as the clock source, after setting the SC0SBIS flag of the SC0MD3 register to "1," write dummy data to the SC0TRB register. If there is to be another reception, write dummy data again to the SC0TRB register. The SC0LNG2 to 0 flags change at the opposite edge of the transmit data output edge. Serial interface 0 begins operation when the SC0SBOS flag or the SC0SBIS flag is set to "1." Set the SC0SBOS flag or the SC0SBIS flag after all conditions have been set. Synchronous Serial Interface 97 Chapter 5 Serial Functions Clock Start condition enabled Start condition disabled Interrupt SC0BSY start condition enabled SC0BSY start condition disabled SC0LNG2 to 0 0 1 2 3 4 5 6 7 0 Figure 5-2-3 Synchronous Serial Interface Reception Timing (reception at rising edge) www.DataSheet4U.com Clock Start condition enabled Start condition disabled Interrupt SC0BSY start condition enabled SC0BSY start condition disabled SC0LNG2 to 0 0 1 2 3 4 5 6 7 0 Figure 5-2-4 Synchronous Serial Interface Reception Timing (reception at falling edge) 98 Synchronous Serial Interface www.DataSheet4U.com Chapter 5 Serial Functions 5-2-3 Serial Interface Transfer Timing Serial interface 0 uses the SC0CE0 and SC0CE1 flags of serial interface 0 mode register 0 (SC0MD0), to control the edge at which transmission data is output and the edge at which reception data is input. During transmission, when the SCnCE1 flag is "0," data output is synchronized to the falling edge of the clock. During reception, when the SCnCE0 flag is "0," data reception is synchronized to the opposite polarity edge of the transmit data edge. When the SCnCE0 flag is "1," data reception is synchronized to the same polarity edge as the transmit data edge. Table 5-2-1 Serial Data Input Edge and Output Edge (serial interface 0) SC0CE0 SC0CE1 0 0 0 1 1 0 1 1 Receive Data Input Edge Transmit Data Output Edge Synchronous Serial Interface 99 Chapter 5 Serial Functions When serial interface 0 is used for simultaneous transmission and reception, set the SCnCE0 and SCnCE1 flags of the SCnMD0 register to "00" or "01", so that the reception data input edge is opposite in polarity to the transmit data output edge. Also, the polarity of the reception data input edge is opposite polarity of the transmit data output edge of the other device. SBT0 Data is input in synchronization with the rising edge of the clock. SBI0 Data is output in synchronization with the falling edge of the clock. SBO0 Figure 5-2-5 Synchronous Serial Transmit/Receive Timing (data is received at the rising edge and transmitted at the falling edge) www.DataSheet4U.com SBT0 Data is input in synchronization with the falling edge of the clock. SBI0 Data is output in synchronization with the rising edge of the clock. SBO0 Figure 5-2-6 Synchronous Serial Transmit/Receive Timing (data is received at the falling edge and transmitted at the rising edge) 100 Synchronous Serial Interface Chapter 5 Serial Functions 5-3 Half-duplex UART Serial Interface 5-3-1 Overview Setup and operation of UART transmission and reception are described below. 5-3-2 Setup and Operation Transmission (1) (2) www.DataSheet4U.com (3) (4) (5) (6) Select UART by setting the SC0CMD flag of the serial interface 0 control register (SC0CTR) to "1." Specify the first bit to be transferred (MSB first or LSB first) with the SC0DIR flag of the serial interface 0 mode register 0 (SC0MD0). Select the valid edge of the clock signal with the SC0CE1 to 0 flags of the SC0MD0 register. Select the clock source with the SC0CK1 to 0 flags of serial interface 0 mode register 1 (SC0MD1). Set the SC0CKM flags of the SC0MD1 register to "1" to divide the clock source frequency by 8. Set the SC0NPE flag of the serial interface 0 mode register 2 (SC0MD2) to enable or disable parity. When the serial port is enabled and the SC0CE1 to 0 flags of the SC0MD0 register are toggled, the transfer bit count may change. The TXD pin goes to a high level after transmission is complete. Setting the SC0FM flag of the SC0MD2 register to frame mode automatically sets the SC0LNG2 to 0 flags of the SC0MD0 register. After the transfer is complete, the SC0LNG2 to 0 flags of the SC0MD0 register are automatically set with the transfer bit count. Set the SC0CKM flag of the SC0MD1 register to "1" to divide the clock source frequency by 8. Half-duplex UART Serial Interface 101 Chapter 5 Serial Functions (7) (8) (9) Serial interface 0 begins operation when the SC0SBOS flag or the SC0SBIS flag is set to "1." Set the SC0SBOS flag or the SC0SBIS flag after all conditions have been set. (10) (11) (12) (13) (14) (15) (16) If parity is enabled by the SC0NPE flag of the SC0MD2 register, set the SC0PM1~0 flags of the SC0MD2 register to specify the added parity bit. Set the SC0FM1 to 0 flags of the SC0MD2 register to specify the frame mode. Set the SC0BRKE flag of the SC0MD2 register to control break status transmission. Select the SC0SBOM flag of the SC0MD3 register. Select the SC0IOM flag of the SC0MD3 register. Set bit 0 of the port 0 direction control register (P0DIR) to the output mode. Select serial communication by setting the SC0SBOS flag of the SC0MD3 register to "1." Set transmit data to serial interface 0 transmit/receive shift register (SC0TRB). This will start the serial transmission. When the serial transmission begins, the SC0BSY flag of the SC0CTR register is set to "1," indicating that a serial transfer is in progress. When the serial transmission is complete, the SC0BSY flag of the SC0CTR register is cleared to "0" and the SC0 transfer complete interrupt request flag is set to "1." The SC0TRI flag of the SC0MD1 register is cleared to "0." www.DataSheet4U.com TXD Parity enabled Parity bit Stop bit Stop bit Stop bit TXD Parity disabled Interrupt Parity enabled Interrupt Parity disabled SC0BSY Parity enabled SC0BSY Parity disabled Figure 5-3-1 UART Transmission Timing 102 Half-duplex UART Serial Interface Stop bit Chapter 5 Serial Functions Reception (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) www.DataSheet4U.com (11) (12) (13) (14) Select UART by setting the SC0CMD flag of the serial interface 0 control register (SC0CTR) to "1." Specify the first bit to be transferred (MSB first or LSB first) with the SC0DIR flag of the serial interface 0 mode register 0 (SC0MD0). Select the valid edge of the clock signal with the SC0CE1 to 0 flags of the SC0MD0 register. Select the clock source with the SC0CK1~0 flags of serial interface 0 mode register 1 (SC0MD1). Set the SC0CKM flags of the SC0MD1 register to "1" to divide the clock source frequency by 8. Set the SC0NPE flag of the serial interface 0 mode register 2 (SC0MD2) to enable or disable parity. If parity is enabled by the SC0NPE flag of the SC0MD2 register, set the SC0PM1 to 0 flags of the SC0MD2 register to specify the added parity bit. Set the SC0FM1 to 0 flags of the SC0MD2 register to specify the frame mode. Select the SC0IOM flag of the SC0MD3 register. When the SC0IOM flag of the SC0MD3 register is specified that the pin is independent, set bit 1 of the port 0 direction control register (P0DIR) to the input mode. Set bit 0 of the port 0 pull-up resistor control register (P0PLU). Select serial communication by setting the SC0SBIS flag of the SC0MD3 register to "1." When the serial transmission begins, the SC0BSY flag of the SC0CTR register is set to "1," indicating that a serial transfer is in progress. When the serial transmission is complete, the SC0BSY flag of the SC0CTR register is cleared to "0" and the SC0 transfer complete interrupt request flag is set to "1." The SC0TRI flag of the SC0MD1 register is cleared to "1." Setting the SC0FM flag of the SC0MD2 register to frame mode automatically sets the SC0LNG2 to 0 flags of the SC0MD0 register. When the serial port is enabled and the SC0CE1 to 0 flags of the SC0MD0 register are toggled, the transfer bit count may change. The TXD pin goes to a high level after reception is complete. Serial interface 0 begins operation when the SC0SBOS or SC0SBIS flag is set to "1." Set the SC0SBOS or SC0SBIS flag after all conditions have been set. One machine cycle after the stop bit has been received, the start condition will no longer be accepted. Therefore, consecutive reception must be performed carefully. After the transfer is complete, the SC0LNG2 to 0 flags of the SC0MD0 register are automatically set with the transfer bit count. Half-duplex UART Serial Interface 103 Chapter 5 Serial Functions RXD Parity enabled Parity bit Stop bit Stop bit Stop bit RXD Parity disabled Interrupt Parity enabled Interrupt Parity disabled SC0BSY Parity enabled SC0BSY Parity disabled Figure 5-3-2 UART Reception Timing www.DataSheet4U.com 104 Half-duplex UART Serial Interface Stop bit Chapter 5 Serial Functions 5-3-3 How to Use the Baud Rate Timer Refer to the following when using the baud rate timer to set the UART transfer speed. (1) Specifying the timer clock source The clock source is specified by the TM3CKS3 to 1 flags of the timer 3 mode register (TM3MD). (2) Setting the compare register The compare register value is set in the timer 3 compare register (TM3OC). This set value is computed according to the following formula: overflow period = (compare register set value + 1) x timer clock period baud rate = 1/(overflow period x 2 x 8) SC0MD1(SC0CKM) compare register set value = timer clock frequency/(baud rate x 2 x 8) - 1 Table 5-3-1 UART Transfer Rate Transfer Speed (bps) fosc (MHz) 4.0 www.DataSheet4U.com 4.19 8.0 8.38 12.0 16.0 16.76 20.0 fosc fs/4 fs/16 fosc fs/4 fs/16 fosc fs/4 fs/16 fosc fs/4 fs/16 fosc fs/4 fs/16 fosc fs/4 fs/16 fosc fs/4 fs/16 fosc fs/4 fs/16 300 1200 Set Calculated Set Calculated Value Value Value Value -- 104 -- -- 109 -- -- 208 -- -- 218 -- -- -- 78 -- -- 104 -- -- 109 -- -- 130 -- 300 -- -- 300 -- -- 300 -- -- 300 -- -- -- 300 -- -- 300 -- -- 300 -- -- 300 208 -- -- 218 -- -- -- 52 -- -- 55 -- -- 78 -- -- 104 -- -- 109 -- -- 130 -- 1202 -- -- 1201 -- -- -- 1201 -- -- 1190 -- -- 1202 -- -- 1202 -- -- 1201 -- -- 1202 -- 2400 Set Calculated Value Value 104 -- -- 109 -- -- 208 -- -- 218 -- -- -- 39 -- -- 52 -- -- 55 -- -- 65 -- 2403 -- -- 2402 -- -- 2404 -- -- 2403 -- -- -- 2403 -- -- 2404 -- -- 2381 -- -- 2404 -- 4800 Set Calculated Value Value 52 -- -- 55 -- -- 104 -- -- 109 -- -- 156 -- -- 208 -- -- 218 -- -- -- 33 -- 9600 19200 Set Calculated Set Calculated Value Value Value Value 4807 26 9615 -- -- -- -- -- -- 4761 27 9699 -- -- -- -- -- -- 4807 52 9615 -- -- -- -- -- -- 4805 55 9523 -- -- -- -- -- -- 4808 78 9615 -- -- -- -- -- -- 4808 104 9615 -- -- -- -- -- -- 4805 109 9610 -- -- -- -- -- -- 130 9615 -- -- 4735 -- -- -- -- 13 -- -- -- -- -- 26 -- -- 27 -- -- 39 -- -- 52 -- -- 55 -- -- 65 -- -- Set the values from this table (minus 1) in the compare register. 19230 -- -- -- -- -- 19230 -- -- 19398 -- -- 19230 -- -- 19230 -- -- 19045 -- -- 19231 -- -- Example: The timer 3 clock source is fs/4 (fosc = 8MHz) and a baud rate of 300 bps is desired. Since fs=fosc/2, compare register set value = (8 x 106/2/4)/(300 x 2 x 8) - 1 =207 = X'CF' Half-duplex UART Serial Interface 105 Chapter 5 Serial Functions 5-4 Serial Interface Control Registers 5-4-1 Overview 7 registers control the serial interface. See table 5-4-1. Table 5-4-1 Serial Interface Registers Name www.DataSheet4U.com 106 Serial Interface Control Registers Address R/W Function SC0MD0 X'03F50' R/W Serial interface 0 mode register 0 SC0MD1 X'03F51' R/W Serial interface 0 mode register 1 SC0MD2 X'03F52' R/W Serial interface 0 mode register 2 SC0MD3 X'03F53' R/W Serial interface 0 mode register 3 SC0CTR X'03F54' R/W Serial interface 0 control register SC0TRB X'03F55' W Serial interface 0 transmit/receive shift register SC0RXB X'03F56' R Serial interface 0 receive data buffer www.DataSheet4U.com Chapter 5 Serial Functions 5-4-2 Transmit/Receive Shift Registers, Receive Data Buffer (1) Serial interface 0 transmit/receive shift register (SC0TRB) This 8-bit, writable register shifts the transmission data and the reception data. The direction of transfer can be specified as LSB first or MSB first. 7 SC0TRB 6 5 4 3 2 1 0 SC0TRB7 SC0TRB6 SC0TRB5 SC0TRB4 SC0TRB3 SC0TRB2 SC0TRB1 SC0TRB0 (at reset: undefined) Figure 5-4-1 Serial Interface 0 Transmit/Receive Shift Register (SC0TRB: X'03F55', W) (2) Serial interface 0 receive data buffer (SC0RXB) 7 SC0RXB 6 5 4 3 2 1 0 SC0RXB7 SC0RXB6 SC0RXB5 SC0RXB4 SC0RXB3 SC0RXB2 SC0RXB1 SC0RXB0 (at reset: undefined) Figure 5-4-2 Serial Interface 0 Receive Data Buffer (SC0RXB: X'03F56', R) Serial Interface Control Registers 107 Chapter 5 Serial Functions 5-4-3 Serial Interface Mode Registers (1) Serial interface 0 mode register (SC0MD0) 7 SC0MD0 - 6 5 4 3 2 1 0 (at reset: -00XX000) SC0CE0 SC0CE1 SC0DIR SC0STE SC0LNG2 SC0LNG1 SC0LNG0 SC0LNG2 SC0LNG1 SC0LNG0 Transfer bit count 0 0 1 0 1 1 SC0STE 0 8 bit 1 7 bit 0 1 6 bit 5 bit 0 4 bit 1 3 bit 0 2 bit 1 bit 1 Selection of synchronous serial start condition 0 Disable start condition 1 Enable start condition www.DataSheet4U.com SC0DIR First bit to be transferred 0 MSB first 1 LSB first SC0CE0 SC0CE1 Receive data Transmit data input edge output edge 0 0 Rising Falling 0 1 1 Falling Rising 0 Falling Falling 1 1 Rising Rising Figure 5-4-3 Serial Interface 0 Mode Register 0 (SC0MD0: X'03F50', R/W) 108 Serial Interface Control Registers www.DataSheet4U.com Chapter 5 Serial Functions (2) Serial interface 0 mode register 1 (SC0MD1) SC0MD1 7 6 - - 5 4 3 2 1 0 SC0CKM SC0CK1 SC0CK0 SC0BRKF SC0ERE SC0TRI (at reset: --X00000) Transmit/receive interrupt request flag SC0TRI 0 Transmit interrupt request 1 Receive interrupt request Error monitor SC0ERE 0 No error 1 Error Break status receive monitor SC0BRKF 0 Data 1 Break Clock source SC0CK1 SC0CK0 0 0 fs/2 0 1 fs/4 1 0 fs/16 1 1 BC3x1/2(1/2 of timer 3 overflow) SC0CKM Divide clock frequency by 8 0 Do not divide by 8 1 Divide by 8 An external clock can be selected as the clock source by setting the SBT0 pin to the input mode. Figure 5-4-4 Serial Interface 0 Mode Register 1 (SC0MD1: X'03F51', R/W) Serial Interface Control Registers 109 Chapter 5 Serial Functions (3) Serial interface 0 mode register 2 (SC0MD2) SC0MD2 7 6 - - 5 4 3 2 1 0 (at reset: --000XXX) SC0BRKE SC0FM1 SC0FM0 SC0PM1 SC0PM0 SC0NPE SC0NPE Parity enable 0 Parity enabled 1 Parity disabled Added bit specification SC0PM1 SC0PM0 Transmission 0 1 Normally add 0 1 Normally add 1 Check for 1 0 Add odd parity Check for odd parity 1 Add even parity Check for even parity SC0FM1 SC0FM0 0 www.DataSheet4U.com 1 Reception 0 Check for 0 Frame mode specification 0 7 data bits + 1 stop bit 1 7 data bits + 2 stop bits 0 8 data bits + 1 stop bits 1 8 data bits + 2 stop bits SC0BRKE Break status transmit control 0 Data 1 Break Figure 5-4-5 Serial Interface 0 Mode Register 2 (SC0MD2: X'03F52', R/W) 110 Serial Interface Control Registers Chapter 5 Serial Functions (4) Serial interface 0 mode register 3 (SC0MD3) SC0MD3 7 6 - - 5 4 3 2 1 0 SC0IOM SC0SBOM SC0SBTM SC0SBOS SC0SBIS SC0SBTS (at reset: --000000) SC0SBTS SBT0 pin function selection 0 Port 1 Serial clock pin SC0SBIS SBI0 input control 0 "1" input 1 Serial input SC0SBOS SBO0 pin function selection 0 Port 1 Serial communication SC0SBTM SBT0 pin configuration selection 0 Push-pull output 1 N-channel open-drain output www.DataSheet4U.com SC0SBOM SBO0 pin configuration selection 0 Push-pull output 1 N-channel open-drain output SC0IOM SBI0/SBO0 pin connection 0 Unconnected 1 Connected Figure 5-4-6 Serial Interface 0 Mode Register 3 (SC0MD3: X'03F53', R/W) Serial Interface Control Registers 111 Chapter 5 Serial Functions 5-4-4 Serial Interface Control Register (1) Serial interface 0 control register (SC0CTR) 7 SC0CTR 6 SC0BSY SC0CMD 5 4 - - 3 2 1 SC0FEF SC0PEK SC0ORE 0 - (at reset: 00XX000X) SC0ORE 0 No Error 1 Error SC0PEK Parity error detection 0 No Error 1 Error SC0FEF Framing error detection 0 No Error 1 Error SC0CMD www.DataSheet4U.com Overrun error detection Synchronous serial/ UART selection 0 Synchronous serial 1 UART SC0BSY Serial bus status 0 Other use 1 Serial transmission in progress Figure 5-4-7 Serial Interface 0 Control Register (SC0CTR: X'03F54', R) (R/W available with SC0CMD only) 112 Serial Interface Control Registers ?? @@@?he O26Xe @@Y?e?O26X?e @@@@@@@@@@@@@@@@@@@@@)e ?@@@@@@@@@@@@@@@@@@@)?e ?I'Xg@Xh @Khf?O26X?e N)X?e?J@@h @@@@@@@@@@@@@@@@@@)?e ?@)KeO&Y?eO26Xe @@ @@H?e @@@@@@@@@@@@@@@@@@@@@)e @@ @@f @@@@@@@@@@@@@@@@@@f @@@@@@@@@@@@@@g @@ @@he@@g @@f?@@@e@@@?g @@he@@g @@f?@@He@@Y?O)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @@he@@g @@f?@@?e@@h @@he@@g @@f?@@?e@@eO)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @0M?e@@e?I4@g ?J@5f?@@?e@@h @@gO26Xe ?7@Hf?@5?e@@h @@@@@@@@@@@@@@@@@@@@@)e ?@5?'@@@@@H?e@@eO26Xe @@hf ?@H?V+MW@5f@@@@@@@)e @@hf J5fW&(Yf@@h @@hf .Ye?O&0Y?f@@h @@hf @0M?g@@h W&g O2@@6Kf O2@@6Kf O2@@6Kf ?O2@@@e ?W&@g ?@@(MI'@@?e ?@@(MI'@@?e ?@@(MI'@@?e ?W2@0Mf W&@@g J@(YeV'@Le J@(YeV'@Le J@(YeV'@Le W&(Mg .Y@@g 7@H?e?N@1e 7@H?e?N@1e 7@H?e?N@1e ?W&(Y?g @@g @@g@@e @@g@@e @@g@@e ?7@Hh @@g @@g@@e @@g@@e @@g@@e J@@=h @@g 7@S@@@6Kf @@g 3@L?e?J@@e N@)XeW&@@e 3@L?e?J@@e N@)XeW&@@e 3@L?e?J@@e N@)XeW&@@e @@(M?I'@@?e @@g @@H?eV'@Le @@g ?@@)KO&@@@e I4@@0Y@5e ?@@)KO&@@@e I4@@0Y@5e ?@@)KO&@@@e I4@@0Y@5e @@f?N@1e @@g ?J@He ?J@He ?J@He @@g@@e @@g W&5?e W&5?e W&5?e @@g@@e @@g ?W&(Y?e ?W&(Y?e ?W&(Y?e 3@L?e?J@5e @@g O&(Yf O&(Yf O&(Yf N@)XeW&@He ?@@?e @@g O2@0Y?f O2@0Y?f O2@0Y?f ?@@?e ?@@)KO&@@?e ?@@?e @@@@@@f ?@@0M?g ?@@0M?g ?@@0M?g ?@@?e I4@@0Mf W&g ?O2@@@e ?W&@g ?W2@0Mf W&@@g W&(Mg .Y@@g ?W&(Y?g @@g ?7@Hh @@g J@@=h @@g @@g 7@S@@@6Kf @@(M?I'@@?e @@g @@g @@H?eV'@Le @@f?N@1e @@g @@g@@e @@g @@g @@g@@e 3@L?e?J@5e @@g N@)XeW&@He @@g ?@@)KO&@@?e @@@@@@f I4@@0Mf ?? ? ?? ? W&g O2@6X?f ? O2@6X?f ?W&@g W2@@@@)Xf W2@@@@)Xf ? W&@@g 7(M?I'@1f 7(M?I'@1f ? .Y@@g (Ye?N@@f (Ye?N@@f ? ?J@5f @@g ?J@5f @@g W&(Yf ?@@?e?? W&(Yf @@g ?W&@g @@g ?&@@)Xf ?@@?e?? ?W&@g ?&@@)Xf @@g ?I')X?e ? ?I')X?e @@g N@1?e N@1?e ?? @@g ?@@?e ?@@?e @@g ?@@?e ?@@?e ?? @@g ?@5?e ?@5?e @@g @6X?eJ@H?e @6X?eJ@H?e ? @@g 3@)K?O&@f ?@@?e? 3@)K?O&@f @@@@@@f V4@@@0M?f ?@@?e? V4@@@0M?f ? ? ? ? ? ? ? W&g ?W&@g W&@@g .Y@@g @@g @@g @@g @@g @@g @@g @@g @@g @@g @@g @@g @@@@@@f W26Xf @@6Khe'6X?e 7<B1f ?I'@@?f?'6XV'1?e 3=C5f V4@?f?V'1?V'?e W2@@6XfV40Yf V'g ?W&(MI')X?he W&(YeV')Xhe ?@@6K? ?W&(Y?e?V')X?h I'@@hfW.f W&(YgV')Xh ?@K?f?O2@@@@@@@@@1?e ?O26X?e ?V4@he?W&Hf @?&@H?g?V')X?g W&5?f 3@@5heV')Xg ?W&(Y?f V40Yhe?V')K?f ?3@@@@@@@@0Mg?I@?e ?V40M? W&(Yg V'@6X?e ?W&(Y?g ?V'@)Xe O&(Yh V'@1e W2@(Y?h ?V4@e ?O&@0Yhe ?O2@(Mhf ?@KO2@@0Y?hf ?3@@@0M?hg ?V40M? W&g ?W&@g W&@@g .Y@@g @@g @@g @@g @@g @@g @@g @@g @@g @@g @@g @@g @@@@@@f W&g O2@6X?f ?W&@g W2@@@@)Xf W&@@g 7(M?I'@1f .Y@@g (Ye?N@@f @@g ?J@5f @@g W&(Yf @@g ?W&@g @@g ?&@@)Xf @@g ?I')X?e @@g N@1?e @@g ?@@?e @@g ?@@?e @@g ?@5?e @@g @6X?eJ@H?e @@g 3@)K?O&@f @@@@@@f V4@@@0M?f www.DataSheet4U.com Chapter 6 6 A/D Conversion Functions 113 Chapter 6 A/D Conversion Functions 6-1 Overview The MN101C117 has an internal A/D converter with 10-bit resolution. A sample-and-hold circuit is contained on-chip and software can switch the analog input between channels 0 to 7 (AN0 to AN7). When the A/D converter is stopped, power consumption can be reduced by turning off the internal ladder resistors. ANCTR1 ANCTR0 ANCHS0 ANCHS1 ANCHS2 ANLADE ANCK0 ANCK1 ANSH0 ANSH1 - - - - - - - ANST 0 7 0 ANBUF1 ANBUF10 ANBUF11 ANBUF12 ANBUF13 ANBUF14 ANBUF15 ANBUF16 ANBUF17 A/D conversion control 7 0 7 ANBUF0 - - - - - - ANBUF06 ANBUF07 3 VDD www.DataSheet4U.com AN0 AN1 AN2 AN3 AN4 AN5 AN6 2 MUX 2 Upper 8 bits of A/D conversion data 10-bit A/D comparator Sample & hold Lower 2 bits of A/D conversion data AN7 VSS fs/2 fs/4 fs/8 fx x 2 MUX 1/2 1/6 1/18 Figure 6-1-1 A/D Converter Block Diagram 114 Overview MUX 0 7 www.DataSheet4U.com Chapter 6 A/D Conversion Functions 6-2 A/D Conversion The procedures for operating the A/D conversion circuit are listed below. (1) Set the ANCHS2 to ANCHS0 flags of A/D control register 0 (ANCTR0) to specify one of pins AN7 to AN0 (PA7 to PA0) as the analog input. (2) Set the ANCK1 and ANCK0 flags of A/D control register 0 to select the A/D conversion clock. Make this setting such that the period of the conversion clock (TAD), which is based on the oscillator, is greater than 800ns. (3) With the ANSH1 and ANSH0 flags of A/D control register 0, set the sample-and-hold time. Select a value for the sample and hold time that is suitable for the analog input impedance. (4) Set the ANLADE flag of A/D control register 0 to "1" so that current flows through the ladder resistors and the A/D converter is on standby. Note: Steps 1 to 4 above may performed all at the same time. (5) Set the ANST flag of A/D control register 1 (ANCTR1) to "1" to start the A/D conversion. (6) After the sample-and-hold time set in step 3, the sampled A/D conversion data is sequentially compared to determine its value beginning with the MSB. (7) When the A/D conversion is complete, the ANST bit is cleared to "0" and conversion results are stored in A/D buffers (ANBUF0, 1). At the same time, an A/D complete interrupt request (ADIRQ) is generated. Start the A/D conversion after the current flowing through the ladder resistors stabilizes. The time constant calculated time from the ladder resistance (max. 80 k ) and the external bypass capacitor connected between Vdd and Vss should be used as the criteria for the wait time. TAD 1~2 3 4 12 ANST A/D conversion start A/D conversion complete TS Sampling Hold Bit 9 Bit 8 comparison comparison Bit 0 comparison Determine bit 9 value Determine Determine bit 1 value bit 0 value Determine bit 8 value A/D interrupt Figure 6-2-1 A/D Conversion Timing A/D Conversion 115 Chapter 6 A/D Conversion Functions The following items must be implemented to maintain the accuracy of the A/D converter: 1. Use a maximum input pin impedance, R, of 500k1 with an external capacitor, C, that is minimum 1,000pF and maximum 1F1. 2. Take the RC time into consideration when setting the A/D conversion interval. 3. Changing the output level of the microcomputer or switching peripheral circuitry on or off when the A/D converter is in use may cause the analog input pin or current pin to fluctuate resulting in a loss of precision. During setup and evaluation, verify the waveform of the analog input pin. Equivalent circuit of analog signal output Microcomputer R A/D input pin C www.DataSheet4U.com 1 FC1000pF where R500k 1 Vss 1 These values are reference values. Figure 6-2-2 Recommended Circuit When Using A/D Conversion 116 A/D Converter Control Registers Chapter 6 A/D Conversion Functions 6-3 A/D Converter Control Registers 6-3-1 Overview Four registers control the A/D converter. See table 6-3-1. Table 6-3-1 A/D Converter Control Registers Name Address R/W Function ANCTR0 X'03F90' R/W A/D control register 0 ANCTR1 X'03F91' R/W A/D control register 1 ANBUF0 X'03F92' R A/D buffer 0 ANBUF1 X'03F93' R A/D buffer 1 www.DataSheet4U.com A/D Converter Control Registers 117 Chapter 6 A/D Conversion Functions 6-3-2 A/D Control Register (ANCTR) This readable and writable 8-bit register controls the operation of the A/D converter. 7 ANCTR0 6 5 4 3 2 1 0 ANSH1 ANSH0 ANCK1 ANCK0 ANLADE ANCHS2 ANCHS1 ANCHS0 (at reset: XXXX0XXX) ANCHS2 ANCHS1 ANCHS0 Analog input selection 0 0 1 0 1 1 ANLADE www.DataSheet4U.com 0 AN0 1 AN1 0 AN2 1 0 AN3 AN4 1 AN5 0 AN6 AN7 1 A/D ladder resistor control 0 A/D ladder resistors off 1 A/D ladder resistors on ANCK1 0 1 ANSH1 0 1 A/D conversion clock selection1 ANCK0 0 fs/2 1 fs/4 0 fs/8 1 Use prohibited ANSH0 Sample and hold time setting2 0 TAD x 2 1 TAD x 6 0 TAD x 18 1 Use prohibited (1) A/D control register 0 (ANCTR0) 1:Specify that where the period of the A/D conversion clock is greater than 800ns. 2:Sample-and-hold time is determined by the analog input impedance. TAD indicates the period of the A/D conversion clock. Figure 6-3-1 A/D Control Register 0 (ANCTR0: X'03F90', R/W) 118 A/D Converter Control Registers Chapter 6 A/D Conversion Functions (2) A/D conversion control register 1 (ANCTR1) 7 ANCTR1 6 5 4 3 2 1 0 ANST (at reset: 0-------) ANST A/D conversion status 0 A/D conversion completed or stopped 1 A/D conversion started or in progress Figure 6-3-2 A/D Control Register 1 (ANCTR1: X'03F91', R/W) www.DataSheet4U.com A/D Converter Control Registers 119 Chapter 6 A/D Conversion Functions 6-3-3 A/D Buffers (ANBUF) These read-only registers store the A/D conversion results. (1) A/D buffer 0 (ANBUF0) This register stores the lower 2 bits of the A/D conversion results. 7 ANBUF0 6 5 4 3 2 1 0 (at reset: XX------) ANBUF07 ANBUF06 Figure 6-3-3 A/D Buffer 0 (ANBUF0: X'03F92', R) (2) A/D buffer 1 (ANBUF1) This register stores the upper 8 bits of the A/D conversion results. 7 6 5 4 3 2 1 0 www.DataSheet4U.com ANBUF1 ANBUF17 ANBUF16 ANBUF15 ANBUF14 ANBUF13 ANBUF12 ANBUF11 ANBUF10 Figure 6-3-4 A/D Buffer 1 (ANBUF1: X'03F93', R) 120 A/D Converter Control Registers (at reset: XXXXXXXX) ?? @@@?he O26Xe @@Y?e?O26X?e @@@@@@@@@@@@@@@@@@@@@)e ?@@@@@@@@@@@@@@@@@@@)?e ?I'Xg@Xh @Khf?O26X?e N)X?e?J@@h @@@@@@@@@@@@@@@@@@)?e ?@)KeO&Y?eO26Xe @@ @@H?e @@@@@@@@@@@@@@@@@@@@@)e @@ @@f @@@@@@@@@@@@@@@@@@f @@@@@@@@@@@@@@g @@ @@he@@g @@f?@@@e@@@?g @@he@@g @@f?@@He@@Y?O)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @@he@@g @@f?@@?e@@h @@he@@g @@f?@@?e@@eO)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @0M?e@@e?I4@g ?J@5f?@@?e@@h @@gO26Xe ?7@Hf?@5?e@@h @@@@@@@@@@@@@@@@@@@@@)e ?@5?'@@@@@H?e@@eO26Xe @@hf ?@H?V+MW@5f@@@@@@@)e @@hf J5fW&(Yf@@h @@hf .Ye?O&0Y?f@@h @@hf @0M?g@@h W&g O2@@6Kf O2@@6Kf O2@@6Kf ?O2@@@e ?W&@g ?@@(MI'@@?e ?@@(MI'@@?e ?@@(MI'@@?e ?W2@0Mf W&@@g J@(YeV'@Le J@(YeV'@Le J@(YeV'@Le W&(Mg .Y@@g 7@H?e?N@1e 7@H?e?N@1e 7@H?e?N@1e ?W&(Y?g @@g @@g@@e @@g@@e @@g@@e ?7@Hh @@g @@g@@e @@g@@e @@g@@e J@@=h @@g 7@S@@@6Kf @@g 3@L?e?J@@e N@)XeW&@@e 3@L?e?J@@e N@)XeW&@@e 3@L?e?J@@e N@)XeW&@@e @@(M?I'@@?e @@g @@H?eV'@Le @@g ?@@)KO&@@@e I4@@0Y@5e ?@@)KO&@@@e I4@@0Y@5e ?@@)KO&@@@e I4@@0Y@5e @@f?N@1e @@g ?J@He ?J@He ?J@He @@g@@e @@g W&5?e W&5?e W&5?e @@g@@e @@g ?W&(Y?e ?W&(Y?e ?W&(Y?e 3@L?e?J@5e @@g O&(Yf O&(Yf O&(Yf N@)XeW&@He ?@@?e @@g O2@0Y?f O2@0Y?f O2@0Y?f ?@@?e ?@@)KO&@@?e ?@@?e @@@@@@f ?@@0M?g ?@@0M?g ?@@0M?g ?@@?e I4@@0Mf W&g ?O2@@@e ?W&@g ?W2@0Mf W&@@g W&(Mg .Y@@g ?W&(Y?g @@g ?7@Hh @@g J@@=h @@g @@g 7@S@@@6Kf @@(M?I'@@?e @@g @@g @@H?eV'@Le @@f?N@1e @@g @@g@@e @@g @@g @@g@@e 3@L?e?J@5e @@g N@)XeW&@He @@g ?@@)KO&@@?e @@@@@@f I4@@0Mf ?? ? ?? ? W&g O2@6X?f ? O2@6X?f ?W&@g W2@@@@)Xf W2@@@@)Xf ? W&@@g 7(M?I'@1f 7(M?I'@1f ? .Y@@g (Ye?N@@f (Ye?N@@f ? ?J@5f @@g ?J@5f @@g W&(Yf ?@@?e?? W&(Yf @@g ?W&@g @@g ?&@@)Xf ?@@?e?? ?W&@g ?&@@)Xf @@g ?I')X?e ? ?I')X?e @@g N@1?e N@1?e ?? @@g ?@@?e ?@@?e @@g ?@@?e ?@@?e ?? @@g ?@5?e ?@5?e @@g @6X?eJ@H?e @6X?eJ@H?e ? @@g 3@)K?O&@f ?@@?e? 3@)K?O&@f @@@@@@f V4@@@0M?f ?@@?e? V4@@@0M?f ? ? ? ? ? ? ? W&g ?W&@g W&@@g .Y@@g @@g @@g @@g @@g @@g @@g @@g @@g @@g @@g @@g @@@@@@f W26Xf @@6Khe'6X?e 7<B1f ?I'@@?f?'6XV'1?e 3=C5f V4@?f?V'1?V'?e W2@@6XfV40Yf V'g ?W&(MI')X?he W&(YeV')Xhe ?@@6K? ?W&(Y?e?V')X?h I'@@hfW.f W&(YgV')Xh ?@K?f?O2@@@@@@@@@1?e ?O26X?e ?V4@he?W&Hf @?&@H?g?V')X?g W&5?f 3@@5heV')Xg ?W&(Y?f V40Yhe?V')K?f ?3@@@@@@@@0Mg?I@?e ?V40M? W&(Yg V'@6X?e ?W&(Y?g ?V'@)Xe O&(Yh V'@1e W2@(Y?h ?V4@e ?O&@0Yhe ?O2@(Mhf ?@KO2@@0Y?hf ?3@@@0M?hg ?V40M? W&g ?O2@@6X?f ?W&@g @@@@@@)Xf W&@@g?J(MeI'@1f .Y@@g?.Y?e?N@@f @@g @@f @@g @@f @@g ?J@5f @@g ?7@Hf @@g J@5?f @@g 7(Y?f @@g ?J(Yg @@g W.Y?g @@g ?W.Yh @@g W&Y?fO.e @@g?W&@@@@@@@(Ye @@@@@@f?&@@@@@@@0Y?e W&g ?W&@g W&@@g .Y@@g @@g @@g @@g @@g @@g @@g @@g @@g @@g @@g @@g @@@@@@f www.DataSheet4U.com Chapter 7 7 AC Zero-Cross Circuit/Noise Filter 121 Chapter 7 AC Zero-Cross Circuit/Noise Filter 7-1 Overview The P21/SENS pin is the input pin for the AC zero-cross detection circuit. The AC zero-cross detection circuit outputs a high level when the input is at an intermediate level, and a low level at all other times. FLOAT1 P7RDWN PARDWN P21IM - - - - - www.DataSheet4U.com P21/IRQ1/SENS AC zero-cross detection circuit 0 7 MUX P21 input/IRQ1 to noise filter (See figure 7-3-1.) Figure 7-1-1 P21 Input Circuit Block Diagram 122 Overview Chapter 7 AC Zero-Cross Circuit/Noise Filter 7-2 AC Zero-Cross Circuit Operation 7-2-1 Setup and Operation Settings for zero-cross circuit operation are listed below. (1) (2) (3) (4) Set the REDG1 flag of the IRQ1ICR register to select the valid edge for IRQ1. Set the NF1EN and NF1CK1 to 0 flags of the NFCTR register to set the noise filter and its sampling clock. With the P21IM flag of the FLOAT1 register, set the P21 pin to zero-cross detection. An IRQ1 interrupt is generated by the falling edge or the rising edge of AC zero-cross detection output. AC line waveform 10 ms at 50Hz 8.3 ms at 60Hz VDD www.DataSheet4U.com VSS Ideal IRQ1 Actual IRQ1 Point A Figure 7-2-1 AC Line Waveform and IRQ Generation Timing Actual IRQ interrupt requests will be generated multiple times. Therefore, the software must filter this signal before making any evaluations. When noise filtering is selected for use, the amount of evaluation processing by the software will be reduced. However, if the OSC stops, a return from the backup mode will not be possible. AC Zero-Cross Circuit Operation 123 Chapter 7 AC Zero-Cross Circuit/Noise Filter 7-3 Noise Filter 7-3-1 Overview External interrupt pins IRQ0 and IRQ1 contain noise filtering circuit. This circuitry can be used for remote control signal reception. Data bus NFCTR IRQ0: External interrupt 0 NF0EN NF0CKS0 NF0CKS1 NF1EN NF1CKS0 NF1CKS1 2 IRQ1: External interrupt 1 2 0 fs/22 7 fs/28 MUX fs/29 fs/210 Noise filter P20/IRQ0 www.DataSheet4U.com To IRQ0 interrupt MUX fs/22 fs/28 fs/29 MUX 10 fs/2 P21/IRQ1/SENS AC zero-cross circuit (Fig.7-1-1) Noise filter MUX Figure 7-3-1 Noise Filtering Circuit Block Diagram 124 Noise Filter To IRQ1 interrupt Chapter 7 AC Zero-Cross Circuit/Noise Filter 7-3-2 Example Input and Output Waveforms for Noise Filter When the noise filter is used, the waveform input to the IRQ0 pin is sampled based on the clock specified by the NF0CKS0 and NF0CKS1 flags of the noise filter control register (NFCTR). The waveform input to the IRQ1 pin is also sampled based on the clock specified by the NF1CKS0 and NF1CKS1 flags. If the sampled level remains the same for 3 consecutive samples, it is sent the CPU; otherwise, the previous level is maintained. Noise filtering cannot be used in the STOP or HALT modes. Sampling Input 0 0 1 1 1 1 1 0 0 Waveform after noise filtering www.DataSheet4U.com Figure 7-3-2 Noise Filter Input and Output Waveform Example Noise Filter 125 Chapter 7 AC Zero-Cross Circuit/Noise Filter 7-4 AC Zero-Cross Control Register 7-4-1 Overview Four registers control the AC zero-cross circuit. Table 7-4-1 AC Zero-Cross Control Register [ 2-4-3 "Interrupt Control Registers External Interrupt Control Registers"] [ 3-2-2 "I/O Port Control Registers Pin Control Registers"] www.DataSheet4U.com 126 AC Zero-Cross Control Register Name Address R/W Function IRQOICR X'03FE2' R/W External interrupt control register 0 IRQ1ICR X'03FE3' R/W External interrupt control register 1 FLOAT1 X'03F4B' R/W Pin control register 1 NFCTR X'03F8A' R/W Noise filter control register Chapter 7 AC Zero-Cross Circuit/Noise Filter 7-4-2 Noise Filter Control Register (NFCTR) This 6-bit readable and writable register controls the noise filter. NFCTR www.DataSheet4U.com 7 6 - - 5 4 3 NF1CKS1 NF1CKS0 NF1EN 2 1 0 NF0CKS1 NF0CKS0 NF0EN (at reset: --000000) NF0EN IRQ0 noise filter setup and operation 0 IRQ0 noise filter off 1 IRQ0 noise filter on NF0CKS1 NF0CKS0 0 0 1 NF1EN IRQ0 noise filter sampling period selection 2 1 fs/2 fs/28 0 fs/2 1 fs/2 9 10 IRQ1 noise filter setup and operation 0 IRQ1 noise filter off 1 IRQ1 noise filter on NF1CKS1 NF1CKS0 0 1 0 IRQ1 noise filter sampling period selection 2 1 fs/2 fs/28 0 fs/2 1 fs/2 9 10 Figure 7-4-1 Noise Filter Control Register (NFCTR: X'03F8A', R/W) AC Zero-Cross Control Register 127 Chapter 7 AC Zero-Cross Circuit/Noise Filter www.DataSheet4U.com 128 ?? @@@?he O26Xe @@Y?e?O26X?e @@@@@@@@@@@@@@@@@@@@@)e ?@@@@@@@@@@@@@@@@@@@)?e ?I'Xg@Xh @Khf?O26X?e N)X?e?J@@h @@@@@@@@@@@@@@@@@@)?e ?@)KeO&Y?eO26Xe @@ @@H?e @@@@@@@@@@@@@@@@@@@@@)e @@ @@f @@@@@@@@@@@@@@@@@@f @@@@@@@@@@@@@@g @@ @@he@@g @@f?@@@e@@@?g @@he@@g @@f?@@He@@Y?O)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @@he@@g @@f?@@?e@@h @@he@@g @@f?@@?e@@eO)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @0M?e@@e?I4@g ?J@5f?@@?e@@h @@gO26Xe ?7@Hf?@5?e@@h @@@@@@@@@@@@@@@@@@@@@)e ?@5?'@@@@@H?e@@eO26Xe @@hf ?@H?V+MW@5f@@@@@@@)e @@hf J5fW&(Yf@@h @@hf .Ye?O&0Y?f@@h @@hf @0M?g@@h W&g O2@@6Kf O2@@6Kf O2@@6Kf ?O2@@@e ?W&@g ?@@(MI'@@?e ?@@(MI'@@?e ?@@(MI'@@?e ?W2@0Mf W&@@g J@(YeV'@Le J@(YeV'@Le J@(YeV'@Le W&(Mg .Y@@g 7@H?e?N@1e 7@H?e?N@1e 7@H?e?N@1e ?W&(Y?g @@g @@g@@e @@g@@e @@g@@e ?7@Hh @@g @@g@@e @@g@@e @@g@@e J@@=h @@g 7@S@@@6Kf @@g 3@L?e?J@@e N@)XeW&@@e 3@L?e?J@@e N@)XeW&@@e 3@L?e?J@@e N@)XeW&@@e @@(M?I'@@?e @@g @@H?eV'@Le @@g ?@@)KO&@@@e I4@@0Y@5e ?@@)KO&@@@e I4@@0Y@5e ?@@)KO&@@@e I4@@0Y@5e @@f?N@1e @@g ?J@He ?J@He ?J@He @@g@@e @@g W&5?e W&5?e W&5?e @@g@@e @@g ?W&(Y?e ?W&(Y?e ?W&(Y?e 3@L?e?J@5e @@g O&(Yf O&(Yf O&(Yf N@)XeW&@He ?@@?e @@g O2@0Y?f O2@0Y?f O2@0Y?f ?@@?e ?@@)KO&@@?e ?@@?e @@@@@@f ?@@0M?g ?@@0M?g ?@@0M?g ?@@?e I4@@0Mf W&g ?O2@@@e ?W&@g ?W2@0Mf W&@@g W&(Mg .Y@@g ?W&(Y?g @@g ?7@Hh @@g J@@=h @@g @@g 7@S@@@6Kf @@(M?I'@@?e @@g @@g @@H?eV'@Le @@f?N@1e @@g @@g@@e @@g @@g @@g@@e 3@L?e?J@5e @@g N@)XeW&@He @@g ?@@)KO&@@?e @@@@@@f I4@@0Mf ?? ? ?? ? W&g O2@6X?f ? O2@6X?f ?W&@g W2@@@@)Xf W2@@@@)Xf ? W&@@g 7(M?I'@1f 7(M?I'@1f ? .Y@@g (Ye?N@@f (Ye?N@@f ? ?J@5f @@g ?J@5f @@g W&(Yf ?@@?e?? W&(Yf @@g ?W&@g @@g ?&@@)Xf ?@@?e?? ?W&@g ?&@@)Xf @@g ?I')X?e ? ?I')X?e @@g N@1?e N@1?e ?? @@g ?@@?e ?@@?e @@g ?@@?e ?@@?e ?? @@g ?@5?e ?@5?e @@g @6X?eJ@H?e @6X?eJ@H?e ? @@g 3@)K?O&@f ?@@?e? 3@)K?O&@f @@@@@@f V4@@@0M?f ?@@?e? V4@@@0M?f ? ? ? ? ? ? ? W&g ?W&@g W&@@g .Y@@g @@g @@g @@g @@g @@g @@g @@g @@g @@g @@g @@g @@@@@@f W26Xf @@6Khe'6X?e 7<B1f ?I'@@?f?'6XV'1?e 3=C5f V4@?f?V'1?V'?e W2@@6XfV40Yf V'g ?W&(MI')X?he W&(YeV')Xhe ?@@6K? ?W&(Y?e?V')X?h I'@@hfW.f W&(YgV')Xh ?@K?f?O2@@@@@@@@@1?e ?O26X?e ?V4@he?W&Hf @?&@H?g?V')X?g W&5?f 3@@5heV')Xg ?W&(Y?f V40Yhe?V')K?f ?3@@@@@@@@0Mg?I@?e ?V40M? W&(Yg V'@6X?e ?W&(Y?g ?V'@)Xe O&(Yh V'@1e W2@(Y?h ?V4@e ?O&@0Yhe ?O2@(Mhf ?@KO2@@0Y?hf ?3@@@0M?hg ?V40M? W&g ?O2@@6X?f O2@@6Kf ?W&@g @@@@@@)Xf ?@@(MI'@@?e W&@@g?J(MeI'@1f J@(YeV'@Le .Y@@g?.Y?e?N@@f 7@H?e?N@1e @@g @@f @@g@@e @@g @@f @@g@@e @@g ?J@5f @@g ?7@Hf 3@L?e?J@@e N@)XeW&@@e @@g J@5?f @@g 7(Y?f ?@@)KO&@@@e I4@@0Y@5e @@g ?J(Yg ?J@He @@g W.Y?g W&5?e @@g ?W.Yh ?W&(Y?e @@g W&Y?fO.e O&(Yf @@g?W&@@@@@@@(Ye O2@0Y?f @@@@@@f?&@@@@@@@0Y?e ?@@0M?g www.DataSheet4U.com 8 Appendices 129 Chapter 8 Appendices 8-1 EPROM Versions 8-1-1 Overview EPROM version is microcomputer which was replaced with the mask ROM of the MN101C11 with an electronically programmable 16-KB EPROM. Because the MN101CP117**(**=DP,BF,HP) is sealed in plastic, once data is written to the internal PROM it cannot be erased. Because the PX-AP101C11-SDC and PX-AP101C11-FBC are sealed in a ceramic package that has a window, written data can beerased by illumination with ultraviolet light. Plastic package uses a 42-pin shrink DIL package, 44-pin flat package, and 48-pin flat package. Ceramic packages uses a 42-pin shrink DIL package and 44-pin flat package. Setting the EPROM version to EPROM mode, halts microcomputer functions, and the internal EPROM can be programmed. Refer to the EPROM mode pin diagram in figure 9-4-3 to 5. www.DataSheet4U.com The specification for writing to the internal EPROM are the same as for a general-purpose 256Kbit EPROM(Vpp=12.5V, tpw=0.2ms). Therefore, by replacing theEPROM Version's 42-pin socket with a special 28-pin socket adapter(supplied by Panasonic) having the same configuration as a normal EPROM, a general-purpose EPROM writer can be used to perform read and write operations. The EPROM Version is described on the following items: - Cautions on use of the internal EPROM - Erasing written Data in Windowed Package(PX-AP101C11-SDC, PXAP101C11-FBC) - Characteristics of EPROM Versions - Writing to the Microcomputer with Internal EPROM - Cautions on operating a ROM writer - Option bit - Connections of a writing adaptor. 130 EPROM Versions www.DataSheet4U.com Chapter 8 Appendices 8-1-2 Cautions on Use EPROM Versions differs from the MN101C11* in some of its electrical characteristics. The user should be aware of these differences. (1) To prevent data from being erased by ultraviolet light after a program is written, affix seals impermeable to UV rays to the glass sections at the top and side sections of the CPU. (PX-AP101C11-SDC, PX-AP101C11-FBC) (2) Due to device characteristics of the MN101CP11XXX, a writing test cannot be performed on all bits. Therefore, storage of the written data cannot be guaranteed in some cases. (3) When a program is written, verify that Vc power supply(6V) is connected before applying the Vpp power supply(12.5V). Disconnect the Vpp supply before disconnecting the Vcc supply. (4) Vpp should never exceed 13.5V including overshoot. (5) If a device is removed while a Vpp of +12.5V is applied, device reliability may be damaged. (6) At CE=VIL, do not change Vpp from VIL to +12.5V or from +12.5V to VIL. (7) From the time after a program is written until just before mounting, storage at a high temperature is recommended. Program/Read High temperature storage 125C - 48H Read Mounting EPROM Versions 131 Chapter 8 Appendices 8-1-3 Erasing Written Data in Windowed Packages (PX-AP101C11-SDC, PX-AP101C11-FBC) In an internal EPROM with windowed packaging, data is erased("0" "1") when UV light at 253.7nm permeates the window to irradiate the chip. The recommended exposure is 10W * s/cm2. This coverage can be achieved by using a commercial UV lamp positioned 2 to 3cm above the package for 15-20 minutes(when the illumination intensity of the package surface is12000 W/cm2). Remove any filters attached to the lamp. By installing a mirrored reflector plate in the lamp, illumination intensity will increase by afactor of 1.4 to 1.8, decreasing the erasure time. If the window becomes dirty with oil, adhesive, etc., UV light permeability will decrease, causing the erasure time to increase considerably. If this happens, clean with alcohol or another solvent that will not harm the package. The recommended above provides sufficient leeway, with several times the amount of time it takes to erase all the bits. However, this value will reliably erase data over all temperature and voltage ranges, and should not be altered. The level of illumination should be regularly checked and the lamp operation verified. www.DataSheet4U.com Erasure begins when EPROM is exposed to light with a wavelength shorter than 400nm. Since fluorescent light and sunlight have wavelengths in this range, exposure to these light sources for extended periods of time could cause inadvertant erasure. To prevent this, cover the window with an opaque label. Data is not erased at wavelengths longer than 400 to 500nm. However, because of typical semiconductor characteristics, the circuit may malfunction if the chip is exposed to an extremely high illumination intensity. The chip will operate normally if this exposure is stopped. However, for areas where it is continuous, take necessary precautions. 132 EPROM Versions www.DataSheet4U.com Chapter 8 Appendices 8-1-4 Characteristics of EPROM Version The MN101C11*(mask ROM version) and the Microcomputer with internal EPROM version have the following differences. Table 8-1-1 Difference between MN101C*(Mask ROM version) and Internal EPROM version) Operating temperature MN101C11ROM ver. -40 to 85 Internal EPROM version -20 to 85 Operating voltage 4.5 to 5.5V0.1s/20MHz 2.7 to 5.5v0.25s/8MHz 2.0 to 5.5v1.00s/2MHz Pin DC characteristics Output current,input current and input judge level are the same. Hi-speed,low-speed oscillation start control,runaway detection period settup Package selection 4.5 to 5.5V0.1s/20MHz 2.7 to 5.5v0.25s/8MHz 2.7 to 5.5v1.00s/2MHz ROM option EPROM option Internal ROM final address data be used as option data. (Final address =X'07FFF) EPROM final address data be used as option data. (Final address=X'07FFF) There are no other functional differences. EPROM Versions 133 Chapter 8 Appendices 8-1-5 Writing to Microcomputer with Internal EPROM Fit in the writing adapter and position the No.1 pin. No.1 pin must be matched to this position. *The socket of an adapter varies according to the package types. Product name 42-SDIP OTP42SD-101CP11 44-QFP OTP44QF14-101CP11 48-QFH OTP48FH7-101CP11 1 2 Package type 39 40 www.DataSheet4U.com No.1 Pin No.1 Pin No.1 Pin (MN101CP117DP) (MN101CP117BF) (MN101CP117HP) (top view) No.1 Pin 2.297 0.127 (PX-AP101C11-SDC) (top view) (PX-AP101C11-FBC) (side view) Figure 8-1-1 Mount on the writing adapter and position of No.1 pin. 134 EPROM Versions www.DataSheet4U.com Chapter 8 Appendices ROM writer Selection The device names should be set up as listed below. Table 8-1-2 Device selection Equip. name Vendor Pecker 30 Avarl Data Hitachi 27C256 1890A Minato Electronics Hitachi 27C256 Lab Site Data I/O Device name Hitachi 27C256 Remarks Do not run ID check and pin connection inspection. The above settings are based on the standard samples. When you use the other equipment than the ones listed, contact the nearest semiconductor design center.(Refer to the sales office table attached at the end of the manual.) EPROM Versions 135 Chapter 8 Appendices 8-1-6 Cautions on Operating the ROM Writer Cautions on operating the ROM writer (1)The Vpp programming voltage for the EPROM versions is 12.5V. Programming with a 21-volt ROM writer can lead to damage. The ROM writer specifications must match those for standard 1-megabit EPROMS:Vpp=12.5V V;tpw=0.2ms. (2)Make sure that the socket adapter matches the ROM writer socket and that the chip is correctly mounted in the socket adapter. Faulty connections can lead to damage. (3)After clearing all memory of the ROM writer, load the program. (Write the data X'FF' on the address X'0000' to X'7FFF'.) (4)After confirming the device name, write the addresses from the start to the final address. (5)The option bits for supporting the mask option are prepared at the final ROM address. This writer has no internal ID codes of Silicon Signature and Intelligent Identifier of the auto-device selection command of ROM writer. If the auto-device selection command is to be executed for this writer, the device is likely damaged. Therefore, never use this command. www.DataSheet4U.com When disabling the writing When disabling the writing, check the following points. (1)Check that the device is mounted correctly on the socket.(pin bending, connecting failure). (2)Check that the erase check result is no problem. (3)Check that the adapter type is identical to the device name. (4)Check that the writing mode is set correctly. (5)Check that the data is correctly transferred to the ROM writer. (6)Recheck the check points (1),(2) and (3) provided on the above paragraph of iCautions on Handling the ROM writeri. When the writing is disabled even after the above check points are confirmed and the device is replaced with another one, contact the nearest semiconductor design center. (See the attached sales office table.) 136 EPROM Versions Chapter 8 Appendices 8-1-7 Option Bit The MN101C117 and the MN101CP117 control the oscillation mode after resetting as well as the runaway-detection watch dog timer, using bit 2 to 0 of the last address (X'7FFF) of the built-in ROM. Option bit 7 6 5 4 3 2 1 0 PKGSEL2 PKGSEL1 WDSEL2 WDSEL1 NSSTRT NSSTRT Selection of oscillation mode after resetting 0 Slow mode 1 NORMAL mode WDSEL2 WDSEL1 Watchdog timer cycle setting 0 www.DataSheet4U.com 1 0 1 X fs/2 PKGSEL2 PKGSEL1 0 1 16 fs/2 18 fs/2 20 Package X SDIP042-P-0600 0 QFP044-P-1010 1 QFH048-P-0707 Fig. 8-1-2 Option bit(Address: X'07FFF') EPROM Versions 137 Chapter 8 Appendices 8-1-8 Writing Adapter Connection VSS 42 OSC1 41 3 P02 4 P06 OSC2 40 5 P10 6 P11 PA7 38 VDD 39 PA6 37 7 P12 8 P13 9 P14 10 P20 11 P21 12 P22 13 P60 14 P61 15 P62 16 P63 MN101CP117 www.DataSheet4U.com 1 P00 2 P01 - VSS VSS NOE VSS A14 VSS VSS VSS VSS VPP VSS NCE A0 A1 A2 A3 A4 A5 A6 A7 VSS PA5 36 PA4 35 PA3 34 PA2 33 PA1 32 PA0 31 P80 30 P81 29 P82 28 P83 27 17 P64 18 P65 P84 26 19 P66 20 P67 P86 24 21 NRST P85 25 P87 23 MMOD 22 VSS VSS VSS VCC VSS VSS A13 A12 A11 A10 A9 A8 D0 D1 D2 D3 D4 D5 D6 D7 VCC Package Code SDIP042-P-0600 Fig. 8-1-3 MN1-1CP117-DP(DC)EPROM Writing Adapter Connections Refer to the pin connection drawing of the 256-bit EPROM(27C256). 138 EPROM Versions D4 D5 D6 D7 VDD VSS VSS A7 A6 A5 A4 P70 P67 P66 P65 P64 20 P02 19 P01 17 NC 18 P00 - P63 P62 P61 P60 P22 P21 P20 P14 P13 P12 P11 33 32 31 30 29 28 27 26 25 24 23 A3 A2 A1 A0 NCE VSS VPP VSS VSS VSS VSS 21 P06 22 P10 MN101CP117 14 OSC2 15 OSC1 16 VSS P83 P82 P81 P80 PA0 PA1 PA2 PA3 PA4 PA5 PA6 MMOD NRST 44 43 42 41 40 39 38 37 36 35 34 P84 P85 P86 P87 1 2 3 4 5 6 7 8 9 10 11 12 PA7 13 VDD D3 D2 D1 D0 A8 A9 A10 A11 A12 A13 VSS VSS VDD VSS VSS VSS VSS VSS VSS NOE VSS A14 www.DataSheet4U.com Chapter 8 Appendices Package code: QFP044-P-1010 Pin pitch: 0.8mm Fig. 8-1-4 MN101CP117-BL(BC)EPROM Writing Adapter Connections Refer to the pin connection drawing of the 256-bit EPROM(27C256). EPROM Versions 139 MN101CP117 36 35 34 33 32 31 30 29 28 27 26 25 A3 A2 A1 A0 VSS NCE VSS VPP VSS VSS VSS VSS 23 P06 24 P10 21 P01 22 P02 20 P00 P63 P62 P61 P60 P23 P22 P21 P20 P14 P13 P12 P11 VSS VSS NOE VSS A14 VSS VDD VSS VSS VSS VSS 19 XO - 13 PA7 14 VDD www.DataSheet4U.com 7 8 9 10 11 12 P83 P82 P81 P80 NC PA0 PA1 PA2 PA3 PA4 PA5 PA6 17 VSS 18 XI A8 A9 A10 A11 A12 A13 VSS 1 2 3 4 5 6 15 OSC2 16 OSC1 D3 D2 D1 D0 P84 P85 P86 P87 MMOD NRST P71 P70 P67 P66 P65 P64 48 47 46 45 44 43 42 41 40 39 38 37 D4 D5 D6 D7 VDD VSS VSS VSS A7 A6 A5 A4 Chapter 8 Appendices Package code: QFH048-P-0707 Pin pitch: 0.5mm Fig. 8-1-5 MN101CP117-HP EPROM Writing Adapter connections Refer to the pin connection drawing of the 256-bit EPROM(27C256). 140 EPROM Versions Chapter 10 Appendices 8-2 Instruction Set MN101C00 SERIES INSTRUCTION SET Group Mnemonic Operation Affected Flag Code Cycle Repeat Expand 1 VF NF CF ZF Size Machine Code 2 3 4 5 6 7 Notes Page 8 9 10 11 Data move instructions MOV www.DataSheet4U.com MOVW MOV Dn,Dm DnDm - - - - 2 1 1010 DnDm MOV imm8,Dm imm8Dm - - - - 4 2 1010 DmDm <#8. 25 MOV Dn,PSW DnPSW 3 3 0010 1001 01Dn 26 MOV PSW,Dm PSWDm - - - - 3 2 0010 0001 01Dm 26 MOV (An),Dm mem8(An)Dm - - - - 2 2 0100 1ADm MOV (d8,An),Dm mem8(d8+An)Dm - - - - 4 2 0110 1ADm <d8. ...> MOV (d16,An),Dm mem8(d16+An)Dm - - - - 7 4 0010 0110 1ADm <d16 .... MOV (d4,SP),Dm mem8(d4+SP)Dm - - - - 3 2 0110 01Dm <d4> MOV (d8,SP),Dm mem8(d8+SP)Dm - - - - 5 3 0010 0110 01Dm <d8. ...> MOV (d16,SP),Dm mem8(d16+SP)Dm - - - - 7 4 0010 0110 00Dm <d16 .... MOV (io8),Dm mem8(IOTOP+io8)Dm - - - - 4 2 0110 00Dm <io8 ...> MOV (abs8),Dm mem8(abs8)Dm - - - - 4 2 0100 01Dm <abs 8..> MOV (abs12),Dm mem8(abs12)Dm - - - - 5 2 0100 00Dm <abs 12.. ...> MOV (abs16),Dm mem8(abs16)Dm - - - - 7 4 0010 1100 00Dm <abs 16.. .... MOV Dn,(Am) Dnmem8(Am) - - - - 2 2 0101 1aDn MOV Dn,(d8,Am) Dnmem8(d8+Am) - - - - 4 2 0111 1aDn <d8. ...> MOV Dn,(d16,Am) Dnmem8(d16+Am) - - - - 7 4 0010 0111 1aDn <d16 .... MOV Dn,(d4,SP) Dnmem8(d4+SP) - - - - 3 2 0111 01Dn <d4> MOV Dn,(d8,SP) Dnmem8(d8+SP) - - - - 5 3 0010 0111 01Dn <d8. ...> MOV Dn,(d16,SP) Dnmem8(d16+SP) - - - - 7 4 0010 0111 00Dn <d16 .... MOV Dn,(io8) Dnmem8(IOTOP+io8) - - - - 4 2 0111 00Dn <io8 ...> MOV Dn,(abs8) Dnmem8(abs8) - - - - 4 2 0101 01Dn <abs 8..> MOV Dn,(abs12) Dnmem8(abs12) - - - - 5 2 0101 00Dn <abs 12.. ...> MOV Dn,(abs16) Dnmem8(abs16) - - - - 7 4 0010 1101 00Dn <abs 16.. .... ...> 36 MOV imm8,(io8) imm8mem8(IOTOP+io8) - - - - 6 3 0000 0010 <io8 <#8. ...> 37 MOV imm8,(abs8) imm8mem8(abs8) - - - - 6 3 0001 0100 <abs 8..> <#8. ...> MOV imm8,(abs12) imm8mem8(abs12) - - - - 7 3 0001 0101 <abs 12.. ...> <#8. ...> MOV imm8,(abs16) imm8mem8(abs16) - - - - 9 5 0011 1101 1001 <abs 16.. .... ...> <#8. MOV Dn,(HA) Dnmem8(HA) - - - - 2 2 1101 00Dn MOVW (An),DWm mem16(An)DWm - - - - 2 3 1110 00Ad MOVW (An),Am mem16(An)Am - - - - 3 4 0010 1110 10Aa MOVW (d4,SP),DWm mem16(d4+SP)DWm - - - - 3 3 MOVW (d4,SP),Am mem16(d4+SP)Am - - - - 3 MOVW (d8,SP),DWm mem16(d8+SP)DWm - - - - MOVW (d8,SP),Am mem16(d8+SP)Am - - - MOVW (d16,SP),DWm mem16(d16+SP)DWm - - MOVW (d16,SP),Am mem16(d16+SP)Am - MOVW (abs8),DWm mem16(abs8)DWm MOVW (abs8),Am 25 ...> 27 1 .... .... 27 28 ...> 2 28 3 29 29 ...> 30 30 31 31 ...> 32 ...> 1 .... .... 32 33 ...> 2 33 3 34 34 ...> 35 35 36 37 38 38 ...> 39 40 4 40 1110 011d <d4> 2 41 3 1110 010a <d4> 2 41 5 4 0010 1110 011d <d8. ...> 3 42 - 5 4 0010 1110 010a <d8. ...> 3 42 - - 7 5 0010 1110 001d <d16 .... .... ...> 43 - - - 7 5 0010 1110 000a <d16 .... .... ...> 43 - - - - 4 3 1100 011d <abs 8..> mem16(abs8)Am - - - - 4 3 1100 010a <abs 8..> MOVW (abs16),DWm mem16(abs16)DWm - - - - 7 5 0010 1100 011d <abs 16.. .... ...> 45 MOVW (abs16),Am mem16(abs16)Am - - - - 7 5 0010 1100 010a <abs 16.. .... ...> 45 MOVW DWn,(Am) DWnmem16(Am) - - - - 2 3 1111 00aD MOVW An,(Am) Anmem16(Am) - - - - 3 4 0010 1111 10aA MOVW DWn,(d4,SP) DWnmem16(d4+SP) - - - - 3 3 MOVW An,(d4,SP) Anmem16(d4+SP) - - - - 3 MOVW DWn,(d8,SP) DWnmem16(d8+SP) - - - - MOVW An,(d8,SP) Anmem16(d8+SP) - - - MOVW DWn,(d16,SP) DWnmem16(d16+SP) - - MOVW An,(d16,SP) Anmem16(d16+SP) - MOVW DWn,(abs8) DWnmem16(abs8) MOVW An,(abs8) 44 44 46 4 46 1111 011D <d4> 2 47 3 1111 010A <d4> 2 47 5 4 0010 1111 011D <d8. ...> 3 48 - 5 4 0010 1111 010A <d8. ...> 3 48 - - 7 5 0010 1111 001D <d16 .... .... ...> 49 - - - 7 5 0010 1111 000A <d16 .... .... ...> 49 - - - - 4 3 1101 011D <abs 8..> Anmem16(abs8) - - - - 4 3 1101 010A <abs 8..> MOVW DWn,(abs16) DWnmem16(abs16) - - - - 7 5 0010 1101 011D <abs 16.. .... ...> 51 MOVW An,(abs16) Anmem16(abs16) - - - - 7 5 0010 1101 010A <abs 16.. .... ...> 51 MOVW DWn,(HA) DWnmem16(HA) - - - - 2 3 1001 010D MOVW An,(HA) Anmem16(HA) - - - - 2 3 1001 011A MOVW imm8,DWm sign(imm8)DWm - - - - 4 2 0000 110d <#8. ...> 5 53 MOVW imm8,Am zero(imm8)Am - - - - 4 2 0000 111a <#8. ...> 6 53 MOVW imm16,DWm imm16DWm - - - - 6 3 1100 111d <#16 .... Note: "Page" refers to the corresponding page in the Instruction Manual. 50 50 52 52 .... 54 ...> 1 d8 sign extended 2 d4 zero extended 3 d8 zero extended 4 A=An, a=Am 5 #8 sign extended 6 #8 zero extended Instruction Set 141 Chapter 10 Appendices MN101C00 SERIES INSTRUCTION SET Group PUSH POP EXT Mnemonic Operation Affected Flag CodeCycle Repeat Expand 1 VF NF CF ZF Size Machine Code 2 3 4 5 6 .... .... ...> 7 Notes Page 8 9 10 11 MOVW imm16,Am imm16Am - - - - 6 3 MOVW SP,Am SPAm - - - - 3 3 0010 0000 100a MOVW An,SP AnSP - - - - 3 3 0010 0000 101A MOVW DWn,DWm DWnDWm - - - - 3 3 0010 1000 00Dd MOVW DWn,Am DWnAm - - - - 3 3 0010 0100 11Da MOVW An,DWm AnDWm - - - - 3 3 0010 1100 11Ad MOVW An,Am AnAm - - - - 3 3 0010 0000 00Aa PUSH Dn SP-1SP,Dnmem8(SP) - - - - 2 3 1111 10Dn 58 PUSH An SP-2SP,Anmem16(SP) - - - - 2 5 0001 011A 58 POP Dn mem8(SP)Dn,SP+1SP - - - - 2 3 1110 10Dn 59 POP An mem16(SP)An,SP+2SP - - - - 2 4 0000 011A EXT Dn,DWm sign(Dn)DWm - - - - 3 3 0010 1001 000d 0011 0011 DnDm 1101 111a <#16 54 55 55 1 56 56 57 2 57 59 3 60 Arithmetic instructions ADD www.DataSheet4U.com ADD Dn,Dm Dm+DnDm 3 2 ADD imm4,Dm Dm+sign(imm4)Dm 3 2 61 6 61 1000 00Dm <#4> ADD imm8,Dm Dm+imm8Dm 4 2 ADDC ADDC Dn,Dm Dm+Dn+CFDm 3 2 0011 1011 DnDm ADDW ADDW DWn,DWm DWm+DWnDWm 3 3 0010 0101 00Dd ADDW DWn,Am Am+DWnAm 3 3 0010 0101 10Da ADDW imm4,Am Am+sign(imm4)Am 3 2 1110 110a <#4> ADDW imm8,Am Am+sign(imm8)Am 5 3 0010 1110 110a <#8. ...> ADDW imm16,Am Am+imm16Am 7 4 0010 0101 011a <#16 .... ADDW imm4,SP SP+sign(imm4)SP - - - - 3 2 1111 1101 <#4> ADDW imm8,SP SP+sign(imm8)SP - - - - 4 2 1111 1100 <#8. ADDW imm16,SP SP+imm16SP - - - - 7 4 0010 1111 1100 <#16 .... .... ...> ADDW imm16,DWm DWm+imm16DWm 7 4 0010 0101 010d <#16 .... .... ...> ADDUW ADDUW Dn,Am Am+zero(Dn)Am 3 3 0010 1000 1aDn ADDSW ADDSW Dn,Am Am+sign(Dn)Am 3 3 0010 1001 1aDn 70 SUB SUB Dn,Dm(when DnDm) Dm-DnDm 3 2 0010 1010 DnDm 71 SUB Dn,Dn Dn-DnDn 2 1 1000 01Dn SUB imm8,Dm Dm-imm8Dm 5 3 0010 1010 DmDm <#8. SUBC SUBC Dn,Dm Dm-Dn-CFDm 3 2 SUBW SUBW DWn,DWm DWm-DWnDWm 3 3 0010 0100 00Dd SUBW DWn,Am Am-DWnAm 3 3 0010 0100 10Da SUBW imm16,DWm DWm-imm16DWm 7 4 0010 0100 010d <#16 .... .... ...> SUBW imm16,Am Am-imm16Am 7 4 0010 0100 011a <#16 .... .... ...> MULU MULU Dn,Dm DmDnDWk 3 8 0010 1111 111D DIVU DIVU Dn,DWm DWm/DnDWm-I...DWm-h 3 9 0010 1110 111d CMP CMP Dn,Dm Dm-Dn...PSW 3 2 0011 0010 DnDm CMP imm8,Dm Dm-imm8...PSW 4 2 1100 00Dm <#8. CMP imm8,(abs8) mem8(abs8)-imm8...PSW 6 3 0000 0100 <abs 8..> CMP imm8,(abs12) mem8(abs12)-imm8...PSW 7 3 0000 0101 <abs 12.. CMP imm8,(abs16) mem8(abs16)-imm8...PSW 9 5 0011 1101 1000 <abs 16.. CMPW DWn,DWm DWm-DWn...PSW 3 3 0010 1000 01Dd CMPW DWn,Am Am-DWn...PSW 3 3 0010 0101 11Da CMPW An,Am Am-An...PSW 3 3 0010 0000 01Aa CMPW imm16,DWm DWm-imm16...PSW 6 3 1100 110d <#16 .... .... ...> 82 CMPW imm16,Am Am-imm16...PSW 6 3 1101 110a <#16 .... .... ...> 83 CMPW 0 0 0 0 1 0000 10Dm <#8. 62 ...> 63 1 64 64 .... 6 65 7 65 66 ...> ...> 6 66 7 67 67 68 8 69 71 ...> 72 73 0010 1011 DnDm 1 74 74 75 75 4 5 76 77 78 78 ...> <#8. 79 ...> ...> <#8. ...> .... <#8. ...> 79 80 ...> 1 81 81 2 82 Logical instructions AND OR XOR Dm&DnDm 0 0 3 2 Dm&imm8Dm 0 0 4 2 0001 11Dm <#8. ...> 84 AND imm8,PSW PSW&imm8PSW 5 3 0010 1001 0010 <#8. ...> 85 OR Dn,Dm DmIDnDm 0 0 3 2 0011 0110 DnDm OR imm8,Dm DmIimm8Dm 0 0 4 2 0001 10Dm <#8. ...> OR imm8,PSW PSWIimm8PSW 5 3 0010 1001 0011 <#8. ...> XOR Dn,Dm Dm^DnDm 0 0 3 2 0011 1010 DnDm XOR imm8,Dm Dm^imm8Dm 0 0 5 3 0011 1010 DmDm <#8. Note: "Page" refers to the corresponding page in the Instruction Manual. 142 84 AND Dn,Dm AND imm8,Dm Instruction Set 0011 0111 DnDm 86 86 87 9 1 D=DWn, d=DWm 2 A=An, a=Am 3 d=DWm 4 D=DWk 88 88 ...> 5 D=DWm 6 #4 sign extended 7 #8 sign extended 8 Dn zero extended 9 mn www.DataSheet4U.com Chapter 10 Appendices MN101C00 SERIES INSTRUCTION SET Group Mnemonic Operation Affected Flag CodeCycle Repeat Expand 1 VF NF CF ZF Size Machine Code 2 3 4 5 6 7 Notes Page 8 9 10 11 NOT NOT Dn _ DnDn 0 3 2 0010 0010 10Dn 89 ASR ASR Dn Dn.msbtemp,Dn.lsbCF 0 - 3 2 0010 0011 10Dn 90 0 0 3 2 0010 0011 11Dn 91 3 2 0010 0010 11Dn 92 5 5 0011 1000 0bp. <io8 0 0 4 0 0 mem8(IOTOP+io8)&bpdata...PSW 0 0 0 Dn>>1Dn,tempDn.msb LSR LSR Dn Dn.lsbCF,Dn>>1Dn 0Dn.msb ROR ROR Dn Dn.Isbtemp,Dn>>1Dn 0 CFDn.msb,tempCF Bit manipulation instructions BSET BSET (io8)bp ...> 93 4 1011 0bp. <abs 8..> 93 7 6 0011 1100 0bp. <abs 16.. 5 5 0011 1000 1bp. <io8 0 0 4 0 0 mem8(IOTOP+io8)&bpdata...PSW 0 0 1mem8(IOTOP+io8)bp BSET (abs8)bp mem8(abs8)&bpdata...PSW 1mem8(abs8)bp BSET (abs16)bp mem8(abs16)&bpdata...PSW .... 94 ...> 1mem8(abs16)bp BCLR BCLR (io8)bp ...> 95 4 1011 1bp. <abs 8..> 95 7 6 0011 1100 1bp. <abs 16.. 0mem8(IOTOP+io8)bp BCLR (abs8)bp mem8(abs8)&bpdata...PSW 0mem8(abs8)bp BCLR (abs16)bp mem8(abs16)&bpdata...PSW .... ...> .... ...> 96 0mem8(abs16)bp BTST BTST imm8,Dm Dm&imm8...PSW 0 0 5 3 0010 0000 11Dm <#8. BTST (abs16)bp mem8(abs16)&bpdata...PSW 0 0 7 5 0011 1101 0bp. <abs 16.. if(ZF=1), PC+3+d4(label)+HPC - - - - 3 2/3 1001 000H <d4> - - - - 4 2/3 1000 1010 <d7. ...H if(ZF=1), PC+5+d11(label)+HPC - - - - 5 2/3 1001 1010 <d11 .... - - - 3 2/3 1001 001H <d4> - - - 4 2/3 1000 1011 <d7. ...H - - - 5 2/3 1001 1011 <d11 .... - - - 4 2/3 1000 1000 <d7. ...H - - - 5 2/3 1001 1000 <d11 .... - - - 4 2/3 1000 1100 <d7. ...H - - - 5 2/3 1001 1100 <d11 .... - - - 4 2/3 1000 1101 <d7. ...H - - - 5 2/3 1001 1101 <d11 .... - - - 4 2/3 1000 1110 <d7. ...H - - - 5 2/3 1001 1110 <d11 .... - - - 4 2/3 1000 1111 <d7. ...H - - - 5 2/3 1001 1111 <d11 .... - - - 5 3/4 0010 0010 0001 <d7. ...H 97 ...> 97 Branch instructions Bcc BEQ label 1 98 2 98 3 99 if(ZF=0), PC+3PC BEQ label if(ZF=1), PC+4+d7(label)+HPC if(ZF=0), PC+4PC BEQ label ...H if(ZF=0), PC+5PC BNE label if(ZF=0), PC+3+d4(label)+HPC - 1 100 if(ZF=1), PC+3PC BNE label if(ZF=0), PC+4+d7(label)+HPC - 2 100 if(ZF=1), PC+4PC BNE label if(ZF=0), PC+5+d11(label)+HPC - ...H 3 101 if(ZF=1), PC+5PC BGE label if((VF^NF)=0),PC+4+d7(label)+HPC - 2 102 if((VF^NF)=1),PC+4PC BGE label if((VF^NF)=0),PC+5+d11(label)+HPC - ...H 3 102 if((VF^NF)=1),PC+5PC BCC label if(CF=0),PC+4+d7(label)+HPC - 2 103 if(CF=1), PC+4PC BCC label if(CF=0), PC+5+d11(label)+HPC - ...H 3 103 if(CF=1), PC+5PC BCS label if(CF=1),PC+4+d7(label)+HPC - 2 104 if(CF=0), PC+4PC BCS label if(CF=1), PC+5+d11(label)+HPC - ...H 3 104 if(CF=0), PC+5PC BLT label if((VF^NF)=1),PC+4+d7(label)+HPC - 2 105 if((VF^NF)=0),PC+4PC BLT label if((VF^NF)=1),PC+5+d11(label)+HPC - ...H 3 105 if((VF^NF)=0),PC+5PC BLE label if((VF^NF)|ZF=1),PC+4+d7(label)+HPC - 2 106 if((VF^NF)|ZF=0),PC+4PC BLE label if((VF^NF)|ZF=1),PC+5+d11(label)+HPC - ...H 3 106 if((VF^NF)|ZF=0),PC+5PC BGT label if((VF^NF)|ZF=0),PC+5+d7(label)+HPC - 2 107 if((VF^NF)|ZF=1),PC+5PC Note: "Page" refers to the corresponding page in the Instruction Manual. 1 d4 sign extended 2 d7 sign extended 3 d11 sign extended Instruction Set 143 www.DataSheet4U.com Chapter 10 Appendices MN101C00 SERIES INSTRUCTION SET Group Bcc Mnemonic BGT label Operation Affected Flag CodeCycle Repeat Expand 1 VF NF CF ZF Size Machine Code 2 3 4 5 ...H - - - 6 3/4 0010 0011 0001 <d11 .... - - - 5 3/4 0010 0010 0010 <d7. ...H - - - 6 3/4 0010 0011 0010 <d11 .... - - - 5 3/4 0010 0010 0011 <d7. ...H - - - 6 3/4 0010 0011 0011 <d11 .... if(NF=0),PC+5+d7(label)+HPC - - - - 5 3/4 0010 0010 0100 <d7. ...H if((VF^NF)|ZF=0),PC+6+d11(label)+HPC - 6 7 Notes Page 8 9 10 11 3 107 if((VF^NF)|ZF=1),PC+6PC BHI label if(CFIZF=0),PC+5+d7(label)+HPC - 2 108 if(CFIZF=1), PC+5PC BHI label if(CFIZF=0),PC+6+d11(label)+HPC - 3 108 ...H if(CFIZF=1), PC+6PC BLS label if(CFIZF=1),PC+5+d7(label)+HPC - 2 109 if(CFIZF=0), PC+5PC BLS label if(CFIZF=1),PC+6+d11(label)+HPC - 3 109 ...H if(CFIZF=0), PC+6PC BNC label 2 110 if(NF=1),PC+5PC BNC label if(NF=0),PC+6+d11(label)+HPC - - - - 6 3/4 0010 0011 0100 <d11 .... - - - 5 3/4 0010 0010 0101 <d7. ...H - - - 6 3/4 0010 0011 0101 <d11 .... - - - 5 3/4 0010 0010 0110 <d7. ...H - - - 6 3/4 0010 0011 0110 <d11 .... - - - 5 3/4 0010 0010 0111 <d7. ...H - - - 6 3/4 0010 0011 0111 <d11 .... 3 110 ...H if(NF=1),PC+6PC BNS label if(NF=1),PC+5+d7(label)+HPC - 2 111 if(NF=0),PC+5PC BNS label if(NF=1),PC+6+d11(label)+HPC - 3 111 ...H if(NF=0),PC+6PC BVC label if(VF=0),PC+5+d7(label)+HPC - 2 112 if(VF=1),PC+5PC BVC label if(VF=0),PC+6+d11(label)+HPC - 3 112 ...H if(VF=1),PC+6PC BVS label if(VF=1),PC+5+d7(label)+HPC - 2 113 if(VF=0),PC+5PC BVS label if(VF=1),PC+6+d11(label)+HPC - 3 113 ...H if(VF=0),PC+6PC CBEQ 1 114 BRA label PC+3+d4(label)+HPC - - - - 3 3 1110 111H <d4> BRA label PC+4+d7(label)+HPC - - - - 4 3 1000 1001 <d7. ...H BRA label PC+5+d11(label)+HPC - - - - 5 3 1001 1001 <d11 .... ...H CBEQ imm8,Dm,label if(Dm=imm8),PC+6+d7(label)+HPC 6 3/4 1100 10Dm <#8. ...> <d7. ...H 8 4/5 0010 1100 10Dm <#8. ...> <d11 .... ...H 9 6/7 0010 1101 1100 <abs 8..> <#8. ...> <d7. ...H 10 6/7 0010 1101 1101 <abs 8..> <#8. ...> <d11 .... ...H 11 7/8 0011 1101 1100 <abs 16.. .... ...> <#8. ...> <d7. ...H 12 7/8 0011 1101 1101 <abs 16.. .... ...> <#8. ...> <d11 .... 2 114 3 115 2 116 / if(Dm=imm8),PC+6PC CBEQ imm8,Dm,label if(Dm=imm8),PC+8+d11(label)+HPC 3 116 if(Dm=imm8),PC+8PC / CBEQ imm8,(abs8),label if(mem8(abs8)=imm8),PC+9+d7(label)+HPC 2 117 if(mem8(abs8)=imm8),PC+9PC / CBEQ imm8,(abs8),label if(mem8(abs8)=imm8),PC+10+d11(label)+HPC 3 117 if(mem8(abs8)=imm8),PC+10PC / CBEQ imm8,(abs16),label if(mem8(abs16)=imm8),PC+11+d7(label)+HPC 2 118 / if(mem8(abs16)=imm8),PC+11PC CBEQ imm8,(abs16),label if(mem8(abs16)=imm8),PC+12+d11(label)+HPC ...H 3 118 if(mem8(abs16)=imm8),PC+12PC / CBNE CBNE imm8,Dm,label 2 119 6 3/4 1101 10Dm <#8. 8 4/5 0010 1101 10Dm <#8. ...> <d11 .... ...H 9 6/7 0010 1101 1110 <abs 8..> <#8. ...> <d7. ...H 10 6/7 0010 1101 1111 <abs 8..> <#8. ...> <d11 .... ...H 11 7/8 0011 1101 1110 <abs 16.. .... ...> <#8. ...> <d7. ...H 12 7/8 0011 1101 1111 <abs 16.. .... ...> <#8. ...> <d11 .... 0 7 6/7 0011 0000 0bp. <abs 8..> <d7. ...H 0 8 6/7 0011 0000 1bp. <abs 8..> <d11 .... if(Dm=imm8),PC+6+d7(label)+HPC / ...> <d7. ..H> if(Dm=imm8),PC+6PC CBNE imm8,Dm,label if(Dm=imm8),PC+8+d11(label)+HPC / 3 119 if(Dm=imm8),PC+8PC CBNE imm8,(abs8),label if(mem8(abs8)=imm8),PC+9+d7(label)+HPC / 2 120 if(mem8(abs8)=imm8),PC+9PC CBNE imm8,(abs8),label if(mem8(abs8)=imm8),PC+10+d11(label)+HPC / 3 120 if(mem8(abs8)=imm8),PC+10PC CBNE imm8,(abs16),label if(mem8(abs16)=imm8),PC+11+d7(label)+HPC / 2 121 if(mem8(abs16)=imm8),PC+11PC CBNE imm8,(abs16),label if(mem8(abs16)=imm8),PC+12+d11(label)+HPC / ...H 3 121 if(mem8(abs16)=imm8),PC+12PC TBZ TBZ (abs8)bp,label if(mem8(abs8)bp=0),PC+7+d7(label)+HPC 0 2 122 if(mem8(abs8)bp=1),PC+7PC TBZ (abs8)bp,label if(mem8(abs8)bp=0),PC+8+d11(label)+HPC 0 ...H 3 122 if(mem8(abs8)bp=1),PC+8PC Note: "Page" refers to the corresponding page in the Instruction Manual. 144 Instruction Set 1 d4 sign extended 2 d7 sign extended 3 d11 sign extended Chapter 10 Appendices MN101C00 SERIES INSTRUCTION SET Group TBZ Mnemonic TBZ (io8)bp,label Affected Flag CodeCycle Repeat Expand 1 VF NF CF ZF Size Operation if(mem8(IOTOP+io8)bp=0),PC+7+d7(label)+HPC 0 Machine Code 2 3 4 5 6 7 Notes Page 8 9 10 11 1 123 0 7 6/7 0011 0100 0bp. <io8 ...> <d7. ...H 0 8 6/7 0011 0100 1bp. <io8 ...> <d11 .... ...H 0 9 7/8 0011 1110 0bp. <abs 16.. .... ...> <d7. 0 10 7/8 0011 1110 1bp. <abs 16.. .... ...> <d11 0 7 6/7 0011 0001 0bp. <abs 8..> <d7. ...H 0 8 6/7 0011 0001 1bp. <abs 8..> <d11 .... 0 7 6/7 0011 0101 0bp. <io8 ...> <d7. ...H 0 8 6/7 0011 0101 1bp. <io8 ...> <d11 .... ...H 0 9 7/8 0011 1111 0bp. <abs 16.. .... ...> <d7. ...H 0 10 7/8 0011 1111 1bp. <abs 16.. .... ...> <d11 .... if(mem8(IOTOP+io8)bp=1),PC+7PC TBZ (io8)bp,label if(mem8(IOTOP+io8)bp=0),PC+8+d11(label)+HPC 0 2 123 if(mem8(IOTOP+io8)bp=1),PC+8PC TBZ (abs16)bp,label if(mem8(abs16)bp=0),PC+9+d7(label)+HPC 0 1 124 ...H if(mem8(abs16)bp=1),PC+9PC TBZ (abs16)bp,label if(mem8(abs16)bp=0),PC+10+d11(label)+HPC 0 .... ...H 2 124 if(mem8(abs16)bp=1),PC+10PC TBNZ TBNZ (abs8)bp,label if(mem8(abs8)bp=1),PC+7+d7(label)+HPC 0 1 125 if(mem8(abs8)bp=0),PC+7PC TBNZ (abs8)bp,label if(mem8(abs8)bp=1),PC+8+d11(label)+HPC 0 2 125 ...H if(mem8(abs8)bp=0),PC+8PC TBNZ (io8)bp,label if(mem8(io)bp=1),PC+7+d7(label)+HPC 0 1 126 if(mem8(io)bp=0),PC+7PC TBNZ (io8)bp,label if(mem8(io)bp=1),PC+8+d11(label)+HPC 0 2 126 if(mem8(io)bp=0),PC+8PC TBNZ (abs16)bp,label if(mem8(abs16)bp=1),PC+9+d7(label)+HPC 0 1 127 if(mem8(abs16)bp=0),PC+9PC TBNZ (abs16)bp,label if(mem8(abs16)bp=1),PC+10+d11(label)+HPC 0 ...H 2 127 if(mem8(abs16)bp=0),PC+10PC JMP JSR JMP (An) 0PC.17~16,AnPC.15~0,0PC.H - - - - 3 4 0010 0001 00A0 JMP label abs18(label)+HPC - - - - 7 5 JSR (An) SP-3SP,(PC+3).bp7~0mem8(SP) - - - - 3 7 0011 1001 0aaH <abs 18.b p15 0..> 0010 0001 00A1 - - - - 5 6 0001 000H <d12 .... ...> - - - - 6 7 0001 001H <d16 .... .... - - - - 7 8 - - - - 3 9 1111 1110 <t4> 131 - - - - 2 1 0000 0000 132 128 5 128 129 (PC+3).bp15~8mem8(SP+1) (PC+3).Hmem8(SP+2).bp7, 0mem8(SP+2).bp6~2, (PC+3).bp17~16mem8(SP+2).bp1~0 0PC.bp17~16 AnPC.bp15~0,0PC.H www.DataSheet4U.com JSR label SP-3SP,(PC+5).bp7~0mem8(SP) 3 129 (PC+5).bp15~8mem8(SP+1) (PC+5).Hmem8(SP+2).bp7, 0mem8(SP+2).bp6~2, (PC+5).bp17~16mem8(SP+2).bp1~0 PC+5+d12(label)+HPC JSR label SP-3SP,(PC+6).bp7~0mem8(SP) ...> 4 130 0011 1001 1aaH <abs 18.b p15 0..> 5 130 (PC+6).bp15~8mem8(SP+1) (PC+6).Hmem8(SP+2).bp7, 0mem8(SP+2).bp6~2, (PC+6).bp17~16mem8(SP+2).bp1~0 PC+6+d16(label)+HPC JSR label SP-3SP,(PC+7).bp7~0mem8(SP) (PC+7).bp15~8mem8(SP+1) (PC+7).Hmem8(SP+2).bp7, 0mem8(SP+2).bp6~2, (PC+7).bp17~16mem8(SP+2).bp1~0 abs18(label)+HPC JSRV (tbl4) SP-3SP,(PC+3).bp7~0mem8(SP) (PC+3).bp15~8mem8(SP+1) (PC+3).Hmem8(SP+2).bp7 0mem8(SP+2).bp6~2, (PC+3).bp17~16mem8(SP+2).bp1~0 mem8(x'004080+tbl4<<2)PC.bp7~0 mem8(x'004080+tbl4<<2+1)PC.bp15~8 mem8(x'004080+tbl4<<2+2).bp7PC.H mem8(x'004080+tbl4<<2+2).bp1~0 PC.bp17~16 NOP NOP PC+2PC Note: "Page" refers to the corresponding page in the Instruction Manual. 1 d7 sign extended 2 d11 sign extended 3 d12 sign extended 4 d16 sign extended 5 aa=abs18.1716 Instruction Set 145 Chapter 10 Appendices MN101C00 SERIES INSTRUCTION SET Group RTS Mnemonic RTS Operation mem8(SP)(PC).bp70 Flag CodeCycle Repeat Expand 1 VF NF CF ZF Size Machine Code 2 3 4 5 6 7 Notes Page 8 9 10 11 - - - - 2 7 0000 0001 133 2 11 0000 0011 134 - - - - 3 2 0010 0001 1rep mem8(SP+1)(PC).bp158 mem8(SP+2).bp7(PC).H mem8(SP+2).bp10(PC).bp1716 SP+3SP RTI RTI mem8(SP)PSW mem8(SP+1)(PC).bp70 mem8(SP+2)(PC).bp158 mem8(SP+3).bp7(PC).H mem8(SP+3).bp10(PC).bp1716 mem8(SP+4)HA-l mem8(SP+5)HA-h SP+6SP Control instruction REP REP imm3 imm3RPC Note: "Page" refers to the corresponding page in the Instruction Manual. 1 135 1 Number of repeats is 0 when imm3=0. www.DataSheet4U.com Ver2.0(1997.9.26) 146 Instruction Set Chapter 10 Appendices 8-3 Instruction Map MN101C00 SERIES INSTRUCTION MAP 1st nibble\2nd nibble 0 1 RTS 2 3 4 5 6 7 8 9 A B C D E F 0 NOP 1 JSR d12(label) JSR d16(label) MOV #8,(abs8)/(abs12) PUSH An 2 When the extension code is b'0010' 3 When the extension code is b'0011' 4 MOV (abs12),Dm MOV (abs8),Dm MOV (An),Dm 5 MOV Dn,(abs12) MOV Dn,(abs8) MOV Dn,(Am) 6 MOV (io8),Dm MOV (d4,SP),Dm MOV (d8,An),Dm 7 MOV Dn,(io8) MOV Dn,(d4,SP) MOV Dn,(d8,Am) 8 ADD #4,Dm SUB Dn,Dn BGE d7 BRA d7 BEQ d7 BNE d7 BCC d7 BCS d7 BLT d7 BLE d7 9 BEQ d4 A MOV Dn,Dm / MOV #8,Dm B BSET (abs8)bp MOV #8,(io8) RTI BNE d4 CMP #8,(abs8)/(abs12) POP An ADD #8,Dm MOVW #8,DWm MOVW #8,Am OR #8,Dm AND #8,Dm MOVW DWn,(HA) MOVW An,(HA) BGE d11 BRA d11 BEQ d11 BNE d11 BCC d11 BCS d11 BLT d11 BLE d11 BCLR (abs8)bp C CMP #8,Dm MOVW (abs8),Am MOVW (abs8),DWm CBEQ #8,Dm,d7 CMPW #16,DWm MOVW #16,DWm D MOV Dn,(HA) MOVW An,(abs8) MOVW DWn,(abs8) CBNE #8,Dm,d7 CMPW #16,Am MOVW #16,Am E MOVW (An),DWm MOVW (d4,SP),Am MOVW (d4,SP),DWm POP Dn ADDW #4,Am F MOVW DWn,(Am) MOVW An,(d4,SP) MOVW DWn,(d4,SP) PUSH Dn ADDW #8,SP ADDW #4,SP JSRV (tbl4) BRA d4 www.DataSheet4U.com Extension code: b'0010' 2nd nibble\3rd nibble 1 0 2 3 4 5 0 MOVW An,Am CMPW An,Am 1 JMP (A0) JSR (A0) JMP (A1) JSR (A1) MOV PSW,Dm 6 7 8 9 A B C D E MOVW SP,Am MOVW An,SP BTST #8,Dm REP #3 2 BGT d7 BHI d7 BLS d7 BNC d7 BNS d7 BVC d7 BVS d7 NOT Dn ROR Dn 3 BGT d11 BHI d11 BLS d11 BNC d11 BNS d11 BVC d11 BVS d11 ASR Dn LSR Dn 4 SUBW DWn,DWm SUBW #16,DWm SUBW #16,Am SUBW DWn,Am MOVW DWn,Am 5 ADDW DWn,DWm ADDW #16,DWm ADDW #16,Am ADDW DWn,Am CMPW DWn,Am 6 MOV (d16,SP),Dm MOV (d8,SP),Dm MOV (d16,An),Dm 7 MOV Dn,(d16,SP) MOV Dn,(d8,SP) MOV Dn,(d16,Am) 8 MOVW DWn,DWm (NOPL @n=m) CMPW DWn,DWm 9 EXT Dn,DWm A SUB Dn,Dm / SUB #8,Dm B SUBC Dn,Dm AND #8,PSW OR #8,PSW MOV Dn,PSW F ADDUW Dn,Am ADDSW Dn,Am C MOV (abs16),Dm MOVW (abs16),Am MOVW (abs16),DWm CBEQ #8,Dm,d12 MOVW An,DWm D MOV Dn,(abs16) MOVW An,(abs16) MOVW DWn,(abs16) CBNE #8,Dm,d12 CBEQ #8,(abs8),d7/d11 CBNE #8,(abs8),d7/d11 E MOVW (d16,SP),Am MOVW (d16,SP),DWm MOVW (d8,SP),Am MOVW (d8,SP),DWm MOVW (An),Am ADDW #8,Am DIVU F MOVW An,(d16,SP) MOVW DWn,(d16,SP) MOVW An,(d8,SP) MOVW DWn,(d8,SP) MOVW An,(Am) ADDW #16,SP MULU Instruction Map 147 Chapter 10 Appendices Extension code: b'0011' 2nd nibble\3rd nibble 0 www.DataSheet4U.com 1 2 3 4 5 6 7 8 9 A 0 TBZ (abs8)bp,d7 TBZ (abs8)bp,d11 1 TBNZ (abs8)bp,d7 TBNZ (abs8)bp,d11 2 CMP Dn,Dm 3 ADD Dn,Dm 4 TBZ (io8)bp,d7 TBZ (io8)bp,d11 5 TBNZ (io8)bp,d7 TBNZ (io8)bp,d11 6 OR Dn,Dm 7 AND Dn,Dm 8 BSET (io8)bp BCLR (io8)bp 9 JMP abs18(label) JSR abs18(label) A XOR Dn,Dm / XOR #8,Dm B ADDC Dn,Dm C BSET (abs16)bp BCLR (abs16)bp D BTST (abs16)bp cmp #8,(abs16) mov #8,(abs16) E TBZ (abs16)bp,d7 TBZ (abs16)bp,d11 F TBNZ (abs16)bp,d7 TBNZ (abs16)bp,d11 B C D E F CBEQ #8,(abs16),d7/11 CBNE #8,(abs16),d7/11 Ver2.0(1997.9.26) 148 Instruction Map www.DataSheet4U.com Chapter 10 Appendices 8-4 Summary of Special Function Registers Bit Symbol Address Register X 3F00 CPUM X 3F01 MEMCTR X 3F02 WDCTR X 3F03 DLYCTR X 3F0E EXADV X 3F10 P0OUT X 3F11 P1OUT X 3F12 P2OUT X 3F13 Disables to use X 3F14 Disables to use X 3F15 Disables to use X 3F16 P6OUT X 3F17 P7OUT X 3F18 P8OUT X 3F1F Disables to use X 3F20 P0IN X 3F21 P1IN X 3F22 P2IN X 3F23 Disables to use Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STOP HALT OSC1 OSC0 Must be set STOP HALT transfer request transfer request to "0" IOW1 IOW0 II/0 bus wait value set Oscillation control IRWE IVBA Reference page MN101C00 series LSI Manual 30 Specifies base address of interrupt vector table WDEN Watchdog timer table DLYS1 DLYS0 Sets oscillation stabilization wait period P0OUT6 P0OUT2 P0OUT1 89 89 P0OUT0 4145 Port 0 output P1OUT4 P1OUT3 P1OUT2 P1OUT1 P1OUT0 4145 Port 1 output P2OUT7 4145 Port 2 output P6OUT7 P6OUT6 P6OUT5 P6OUT4 P6OUT3 P6OUT2 P6OUT1 P6OUT0 4145 Port 6 output P8OUT7 P8OUT6 P8OUT5 P8OUT4 P8OUT3 P8OUT2 P8OUT1 P7OUT0 Port 7 output P8OUT0 4145 Port 8 output P0IN2 P0IN6 P0IN1 P0IN0 Port 0 input P1IN4 P1IN3 4145 P1IN2 P1IN1 P1IN0 P2IN1 P2IN0 Port 1 input P2IN2 Port 2input 4145 4145 4145 Summary of Special Function Registers 149 Chapter 10 Appendices Bit Symbol Address Register X 3F24 Disables to use X 3F25 Disables to use X 3F26 P6IN X 3F27 P7IN X 3F28 P8IN X 3F2A PAIN X 3F30 P0DIR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P6IN7 P6IN6 P6IN5 P6IN4 P6IN3 P6IN2 P6IN1 P6IN0 P8IN6 P8IN5 P8IN4 P8IN3 PAIN6 PAIN5 PAIN4 PAIN3 Disables to use X 3F34 Disables to use X 3F35 Disables to use X 3F36 P6DIR X 3F37 P7DIR X 3F38 P8DIR X 3F39 P1OMD X 3F3A PAIMD X 3F3C Disables to use X 3F40 P0PLU X 3F41 P1PLU PAIN2 PAIN1 PAIN0 4145 P0DIR1 P0DIR0 Port 0 I/O direction control P1DIR3 4145 4145 P0DIR2 P1DIR4 X 3F33 P8IN1 Port A input P0DIR6 P1DIR P8IN2 P7IN0 Port 7 input P8IN0 Port 8 input PAIN7 X 3F31 4145 Port 6 input P8IN7 Reference Page P1DIR2 P1DIR1 4145 P1DIR0 4145 Port 1 I/O direction control www.DataSheet4U.com P6DIR7 P6DIR6 P6DIR5 P6DIR4 P6DIR3 P8DIR7 P8DIR6 P8DIR5 P8DIR4 P8DIR3 P6DIR1 P6DIR0 4145 PAAIN4 PAAIN3 P12TCO PAAIN2 P10TCO 4146 PAAIN1 PAAIN0 4146 I/O port/Special function pin control P0PLU6 P0PLU2 P0PLU1 P0PLU0 Port 0 pull-up resistor ON/OFF control P1PLU4 P1PLU3 P1PLU2 4145 4145 I/O port/Special function pin control PAAIN5 Summary of Special Function Registers P8DIR2 P7DIR0 Port 7 I/O direction control P8DIR1 P8DIR0 Port 8 I/O direction control P14TCO P13TCO 150 P6DIR2 Port 6 I/O direction control P1PLU1 4145 P1PLU0 Port 1 pull-up resistor ON/OFF control 4245 Chapter 10 Appendices Bit Symbol Address Register X 3F42 P2PLU X 3F43 Disables to use X 3F44 Disables to use X 3F45 Disables to use Bit 7 P6PLU X 3F47 P7PLUD X 3F48 P8PLU X 3F4A PAPLUD X 3F4B FLOAT1 X 3F4C Disables to use Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P2PLU2 P2PLU1 P2PLU0 Port 2 pull-up resistor ON/OFF control P6PLU7 X 3F46 Bit 6 P6PLU6 P6PLU5 P6PLU4 P6PLU3 P6PLU2 P6PLU1 P6PLU0 Port 6 pull-up resistor ON/OFF control Reference Page 4245 4245 P7PLUD0 Port pull-up pull down resistor ON/OFF control P8PLU7 P8PLU6 P8PLU5 P8PLU4 P8PLU3 P8PLU2 P8PLU1 4245 P8PLU0 4245 Port 8 pull-up resistor ON/OFF control PAPLUD7 PAPLUD6 PAPLUD5 PAPLUD4 PAPLUD3 PAPLUD2 PAPLUD1 PAPLUD0 P21M www.DataSheet4U.com SC0MD0 X 3F51 SC0MD1 X 3F52 SC0MD2 X 3F53 SC0MD3 X 3F54 SC0CTR X 3F55 SC0TRB X 3F56 SC0RXB X 3F57 Disables to use X 3F58 Disables to use PARDWN P7RDWN P21input Port A pullp Port 7 pullup mode selection pulldown sel. pulldown sel. SC0CE0 X 3F50 4245 Port A pull-up pull-down resistor ON/OFF control SC0CE1 P21M SC0DIR SC0STE SC0LNG2 SC0LNG1 SC0LNG0 Receive data input edge Start bit set up Synchrounou serial Transmit data output edge for transmit start edition select SC0CKM SC0CK1 Transfer bit count SC0CK0 SC0BRKF SC0ERE Select 1/8 period Clock source selection of freq. SC0BRKE SC0FM1 SC0FM0 SC0PM1 SC0PM0 SC0NPE Control break Specifies added bit status trans. Specifies frame mode Enables parity SC0IOM SC0SBOM SC0SBTM SC0SBOS SC0SBIS SC0SBTS SBI0/SBO0 SBO0pin pin connection selection SelectSBT SelectSBO ControlSBI SelectSBT0 pin format pin function input pin function SC0BSY SC0CMD SC0RXB5 SC0RXB4 SC0FEF SC0PEK SC0ORE Status of serial bus Detect parity error Detect framing error 108 SC0TRI Break status Error monitor Trans/rec interrup rec. monitor request flag Select sync. seroal UART 4246 Detect overrun error 109 110 111 112 SC0TRB7 SC0TRB6 SC0TRB5 SC0TRB4 SC0TRB3 SC0TRB2 SC0TRB1 SC0TRB0 Serial interface 0 transmit/receive shift register 107 SC0RXB7 SC0RXB6 SC0RXB5 SC0RXB4 SC0RXB3 SC0RXB2 SC0RXB1 SC0RXB0 Serial interface 0 receive data buffer 107 Summary of Special Function Registers 151 Chapter 10 Appendices Bit Symbol Address Register X 3F59 Disables to use X 3F5A Disables to use X 3F5B Disables to use X 3F5C Disables to use X 3F5D Disables to use X 3F60 Disables to use X 3F61 Bit 7 Bit 6 Bit 3 Bit 2 Bit 1 Bit 0 Reference Page - TM2BC5 TM2BC TM2BC4 TM2BC3 TM2BC2 TM2BC1 TM2BC0 82 Binary counter2 TM3BC7 TM3BC6 X 3F63 Bit 4 Disables to use TM2BC7 TM2BC6 X 3F62 Bit 5 TM3BC5 TM3BC4 TM3BC3 TM3BC TM3BC2 TM3BC1 TM3BC0 Binary counter3 www.DataSheet4U.com 82 TM4BCL7 TM4BCL6 TM4BCL5 TM4BCL4 TM4BCL3 TM4BCL2 TM4BCL1 TM4BCL0 X 3F64 X 3F65 Binary counter 4Lower 8 bits TM4BCL TM4BCH TM4BCH7 TM4BCH6 TM4BCH5 TM4BCH4 TM4BCH3 TM4BCH2 TM4BCH1 TM4BCH0 Binary counter4 (Upper 8 bits X 3F66 TM4ICL 83 TM4ICL7 TM4ICL6 TM4ICL5 TM4ICL4 TM4ICL3 TM4ICL2 TM4ICL1 TM4ICL0 Input capture registerLower 8 bits 83 84 TM4ICH7 TM4ICH6 TM4ICH5 TM4ICH4 TM4ICH3 TM4ICH2 TM4ICH1 TM4ICH0 X 3F67 TM4ICH X 3F68 TM5BC X 3F70 Disables to use - X 3F71 Disables to use - X 3F72 TM2OC X 3F73 TM3OC X 3F74 TM4OCL Input capture reigster(Upper 8 bits) TM5BC7 TM5BC6 TM5BC5 TM5BC4 TM5BC3 TM5BC2 TM5BC1 TM5BC0 Binary counter 5 84 84 TM2OC7 TM2OC6 TM2OC5 TM2OC4 TM2OC3 TM2OC2 TM2OC1 TM2OC0 Compare register 2 82 TM3OC7 TM3OC6 TM3OC5 TM3OC4 TM3OC3 TM3OC2 TM3OC1 TM3OC0 Compare register 3 82 TM4OCL7 TM4OCL6 TM4OCL5 TM4OCL4 TM4OCL3 TM4OCL2 TM4OCL1 TM4OCL0 152 Summary of Special Function Registers Compare register 4Lower 8 bits 83 Chapter 10 Appendices Bit Symbol Address Register X 3FE0 Disables to use X 3FE1 NMICR X 3FE2 IRQ0ICR X 3FE3 IRQ1ICR X 3FE4 Disables to use X 3FE5 Disables to use X 3FE6 TM2ICR X 3FE7 TBICR X 3FE8 SC0ICR X 3FE9 Disables to use X 3FEA ADICR X 3FEB IRQ2ICR X 3FEC IRQ3ICR X 3FED Disables to use X 3FEE TM3ICR Interrupt level flag for timer 3 interrupt Interrupt enable flag X 3FEF TM4ICR Interrupt level flag for timer 4 interrupt Interrupt enable flag X 3FF0 TM5ICR Interrupt level flag for timer 5 interrupt Interrupt enable flag X 3FF1 Disables to use X 3FF2 Disables to use Bit 7 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reference Page WDIR 34 Watchdog interrupt request flag IRQ0LV1 IRQ0LV0 REDG0 IRQ0IE IRQ0IR Interrup level flag for external interrupt External interrupt valid edge flag Interrupt enable flag Interrupt request flag IRQ1LV1 IRQ1LV0 REDG1 IRQ1IE IRQ1IR Interrupt level flag for external interrupt External interrupt valud edge flag Interrupt enable flag Interrupt request flag TM2LV1 TM2LV0 Interrupt level flag for timer 2 interrupt TBLV1 www.DataSheet4U.com Bit 6 TBLV0 Interrupt level flag for time base interrupt SC0LV1 SC0LV0 Interrupt level flag for serial 0 interrupt ADLV1 TM2IE TM2IR Interrupt enable flag Interrupt request flag TBIE TBIR Interrupt enable flag Interrupt request flag SC0IE SC0IR Interrup enable flag Interrupt request flag ADIE ADLV0 Interrup level flag for A/D interrupt IRQ2LV1 IRQ2LV0 REDG2 Interrupt level flag for external interrupt External interrupt valid edge flag 34 34 35 35 35 ADIR 35 Interrupt enable flag Interrupt request flag IRQ2IE IRQ2IR Interrup enable flag Interrupt request flag 34 Interrupt request flag 35 Interrupt request flag 35 Interrupt request flag 35 TM3IE TM4IE TM5IE Summary of Special Function Registers 153 Chapter 10 Appendices Bit Symbol Address Register X 3FE0 Disables to use X 3FE1 NMICR X 3FE2 IRQ0ICR X 3FE3 IRQ1ICR X 3FE4 Disables to use X 3FE5 Disables to use X 3FE6 TM2ICR X 3FE7 TBICR X 3FE8 SC0ICR X 3FE9 Disables to use X 3FEA ADICR X 3FEB IRQ2ICR X 3FEC IRQ3ICR X 3FED Disables to use X 3FEE TM3ICR Interrupt level flag for timer 3 interrupt Interrupt enable flag X 3FEF TM4ICR Interrupt level flag for timer 4 interrupt Interrupt enable flag X 3FF0 TM5ICR Interrupt level flag for timer 5 interrupt Interrupt enable flag X 3FF1 Disables to use X 3FF2 Disables to use Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reference Page WDIR 34 Watchdog interrupt request flag IRQ0LV1 IRQ0LV0 REDG0 IRQ0IE IRQ0IR Interrup level flag for external interrupt External interrupt valid edge flag Interrupt enable flag Interrupt request flag IRQ1LV1 IRQ1LV0 REDG1 IRQ1IE IRQ1IR Interrupt level flag for external interrupt External interrupt valud edge flag Interrupt enable flag Interrupt request flag TM2LV1 TM2LV0 Interrupt level flag for timer 2 interrupt TBLV1 TBLV0 Interrupt level flag for time base interrupt SC0LV1 SC0LV0 Interrupt level flag for serial 0 interrupt TM2IE TM2IR Interrupt enable flag Interrupt request flag TBIE TBIR Interrupt enable flag Interrupt request flag SC0IE SC0IR Interrup enable flag Interrupt request flag 34 34 35 35 35 www.DataSheet4U.com ADLV1 ADIE ADLV0 Interrup level flag for A/D interrupt IRQ2LV1 IRQ2LV0 REDG2 Interrupt level flag for external interrupt External interrupt valid edge flag ADIR 35 Interrupt enable flag Interrupt request flag IRQ2IE IRQ2IR Interrup enable flag Interrupt request flag 34 Interrupt request flag 35 Interrupt request flag 35 Interrupt request flag 35 TM3IE TM4IE 154 TM5IE Summary of Special Function Registers www.DataSheet4U.com MN101C115 / 117 LSI User's Manual August,1999 1st Edition 1st Printing Issued by Matsushita Electric Industrial Co., Ltd. Matsushita Electronics Corporation (c) Matsushita Electric Industrial Co., Ltd. (c) Matsushita Electronics Corporation www.DataSheet4U.com Semiconductor Company Matsushita Electronics Corporation Nagaokakyo, Kyoto, 617-8520 Japan Tel: (075) 951-8151 http://www.mec.panasonic.co.jp SALES OFFICES HONG KONG SALES OFFICE U.S.A. SALES OFFICE Panasonic Industrial Company [PIC] New Jersey Office: 2 Panasonic Way, Secaucus, New Jersey 07094 Tel: 201-392-6173 Fax: 201-392-4652 Milpitas Office: 1600 McCandless Drive, Milpitas, California 95035 Tel: 408-945-5630 Fax: 408-946-9063 Chicago Office: 1707 N. Randall Road, Elgin, Illinois 60123-7847 Tel: 847-468-5829 Fax: 847-468-5725 Atlanta Office: 1225 Northbrook Parkway, Suite 1-151, Suwanee, Georgia 30174 Tel: 770-338-6940 Fax: 770-338-6849 San Diego Office: 9444 Balboa Avenue, Suite 185 San Diego, California 92123 Tel: 619-503-2940 Fax: 619-715-5545 CANADA SALES OFFICE Panasonic Canada Inc. [PCI] 5700 Ambler Drive Mississauga, Ontario, L4W 2T3 Tel: 905-624-5010 Fax: 905-624-9880 GERMANY SALES OFFICE Panasonic Industrial Europe G.m.b.H. Munich Office: Hans-Pinsel-Strasse 2 85540 Haar Tel: 89-46159-156 Fax: 89-46159-195 [PIEG] U.K. SALES OFFICE Panasonic Industrial Europe Ltd. [PIEL] Electric component Group: Willoughby Road, Bracknell, Berkshire RG12 8FP Tel: 1344-85-3773 Fax: 1344-85-3853 FRANCE SALES OFFICE Panasonic Industrial Europe G.m.b.H. Paris Office: 270, Avenue de President Wilson 93218 La Plaine Saint-Denis Cedex Tel: 14946-4413 Fax: 14946-0007 [PIEG] ITALY SALES OFFICE Panasonic Industrial Europe G.m.b.H. Milano Office: Via Lucini N19, 20125 Milano Tel: 2678-8266 Fax: 2668-8207 [PIEG] Panasonic Shun Hing Industrial Sales (Hong Kong) Co., Ltd. [PSI(HK)] 11/F, Great Eagle Centre, 23 Harbour Road, Wanchai, Hong Kong. Tel: 2529-7322 Fax: 2865-3697 TAIWAN SALES OFFICE Panasonic Industrial Sales Taiwan Co.,Ltd. [PIST] Head Office: 6th Floor, Tai Ping & First Building No.550. Sec.4, Chung Hsiao E. Rd. Taipei 10516 Tel: 2-2757-1900 Fax: 2-2757-1906 Kaohsiung Office: 6th Floor, Hsien 1st Road Kaohsiung Tel: 7-223-5815 Fax: 7-224-8362 SINGAPORE SALES OFFICE Panasonic Semiconductor of South Asia 300 Beach Road # 16-01 The Concourse Singapore 199555 Tel: 390-3688 Fax: 390-3689 [PSSA] MALAYSIA SALES OFFICE Panasonic Industrial Company (Malaysia) Sdn. Bhd. Head Office: [PICM] Tingkat 16B Menara PKNS PJ No.17,Jalan Yong Shook Lin 46050 Petaling Jaya Selangor Darul Ehsan Malaysia Tel: 03-7516606 Fax: 03-7516666 Penang Office: Suite 20-17,MWE PLAZA No.8,Lebuh Farquhar,10200 Penang Malaysia Tel: 04-2625550 Fax: 04-2619989 Johore Sales Office: 39-01 Jaran Sri Perkasa 2/1,Taman Tampoi Utama,Tampoi 81200 Johor Bahru,Johor Malaysia Tel: 07-241-3822 Fax: 07-241-3996 CHINA SALES OFFICE Panasonic SH Industrial Sales (Shenzhen) Co., Ltd. [PSI(SZ)] 7A-107, International Business & Exhibition Centre, Futian Free Trade Zone, Shenzhen 518048 Tel: 755-359-8500 Fax: 755-359-8516 Panasonic Industrial (Shanghai) Co., Ltd. [PICS] 1F, Block A, Development Mansion, 51 Ri Jing Street, Wai Gao Qiao Free Trade Zone, Shanghai 200137 Tel: 21-5866-6114 Fax: 21-5866-8000 THAILAND SALES OFFICE Panasonic Industrial (Thailand) Ltd. [PICT] 252/133 Muang Thai-Phatra Complex Building,31st Fl.Rachadaphisek Rd.,Huaykwang,Bangkok 10320 Tel: 02-6933407 Fax: 02-6933423 080499