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MICROCOMPUTER
MN101C00
MN101C115/117
LSI User’s Manual
Pub. No. 21411-011E
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If you have any inquiries or questions about this book or our semiconductors, please contact one of
our sales offices listed at the back of this book or Matsushita Electronics Corporation's Sales
Department.
Request for your special attention and precautions in using the technical
information and semiconductors described in this book
(1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any
of the products or technologies described in this book and controlled under the "Foreign Exchange and
Foreign Trade Control Law" is to be exported or taken out of Japan.
(2) The contents of this book are subject to change without notice in matters of improved function. When
finalizing your design,therefore,ask for the most up-to-date version in advance in order to check for any
changes.
(3) We are not liable for any damage arising out of the use of the contents of this book, or for any
infringement of patents or any other rights owned by a third party.
(4) No part of this book may be reprinted or reproduced by any means without written permission from our
company.
(5)
This book deals with standard specifications. Ask for the latest individual Product Standards or Specifications
in advance for more detailed information required for your design,purchasing and applications.
PanaXSeries is a trademark of Matsushita Electric Industrial Co., Ltd.
The other corporation names,logotype and product names written in this book are trademarks or registered trademarks of their
corresponding corporations.
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How to Read This Manual–1
The MN101C11x incorporates more than one ROM/RAM to meet a variety of applications. An EPROM version as
well as a Mask ROM version is available so users can write a program by themselves.
■Organization
In this LSI manual, the MN101C117 functions are presented in the following order: overview, CPU basic functions,
port functions, timer functions, serial functions, and other peripheral hardware functions.
How to Read This Manual
ROM RAM
8K MN101C115*1 256
16K MN101C117 512
16K MN101CP117 512
*1 : Under plannin
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How to Read This Manual–2
■Manual Configuration
Each section of this manual consists of a title, summary, main text, supplemental information, precautions and
warnings. The layout and definition of each section are shown below.
Subtitle
Sub-subtitle
The smallest block
in this manual.
Main text
Summary
Introduction to the
section.
Key information
Important
information from
the text.
Supplementary
information
Supplementary
information for the
main text. An
explanation of
terminology is also
included.
Precautions and
warnings
Precautions are
listed in case of lost
functionality or
damage.
Be sure to read.
Chapter 4 Timer Functions
83
4-3 16-bit Timer Operation (timer 4)
4-3-1 Overview
Timer 4 is a 16-bit programmable counter that can be used as an event counter.
A signal with frequency of 1/2 of the timer 4 overflow signal can be output from the
TM4IO pin. An input capture function and added pulse PWM output function can
also be used.
■Timer Operation
Settings for timer operation are listed below.
(1) Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" so that the count
operation of timer 4 is stopped.
(2) Set the TM4CK2~0 flags of the TM4MD register to select fosc, fs/4, or fs/16 as the
clock source.
(3) Set the TM4PWM flag of the TM4MD register to "0" so that 16-bit timer operation is
selected.
Figure 4-3-1 Binary Counter 4 (TM4BC) Count Timing
16-bit Timer Operation (timer 4)
When servicing an interrupt, reset
the timer 4 interrupt request flag
before operating timer 4.
During a count operation, be
careful if the value set in TM4OCH
and TM4OCL is smaller than the
value of binary counter 4, since
the count-up operation will
continue until overflow occurs.
Clock
TM4EN
Binary
counter 4
Write to registers
TM4OCH, TM4OCL
0504 06 07 08 09 00
If the TM4EN flag of the TM4MD register is changed
simultaneously with other bits, the switching operation may cause
binary counter 4 to be incremented.
If the value of TM4OCH and TM4OCL registers is overwritten while
timer 4 has stopped counting, binary counter 4 will be reset to
X'0000'.
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■Finding Desired Information
This manual provides four methods for finding desired information quickly and easily.
(1) Consult the index at the front of the manual to locate the beginning of each section.
(2) Consult the table of contents at the front of the manual to locate desired titles.
(3) Consult the list of figures at the front of the manual to locate illustrations and charts by title name.
(4) Chapter names are located at the top outer corner of each page, and section titles are located at the bottom
outer corner of each page.
■Related Manuals
The following manuals are also available from Panasonic as part of the MN101C00 series.
MN101C00 Series LSI Manual
<Device Hardware Description>
MN101C00 Series Command Manual
<Command Descriptions>
MN101C00 Series Cross Assembler User's Manual
<Assembler Syntax and Entry Methods>
MN101C00 Series C Compiler User's Manual Operation
<C Compiler Installation, Startup, Option Descriptions>
MN101C00 Series C Compiler User's Manual Language
<C Language Syntax Description>
MN101C00 Series C Compiler User's Manual Library
<C Compiler Standard Library Description>
MN101C00 Series C Source Code Debugger User's Manual
<C Source Code Debugger Usage Methods>
MN101C00 Series PanaX Series Installation Manual
<Installation of C Compiler, Cross Assembler, C Source Code Debugger; In-circuit
Emulator>
■Where to Send Inquires
Please send any inquires or questions concerning the contents of this manual to the Panasonic semiconductor design
center closest to you. A list of addresses is provided at the end of this manual for your convenience.
How to Read This Manual–3
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Contents
Chapter 1 Overview
1-1 Product Overview...........................................................................................................2
1-1-1 Overview ..........................................................................................................2
1-1-2 Product Summary.............................................................................................2
1-2 Hardware Functions .......................................................................................................3
1-3 Pins.................................................................................................................................5
1-3-1 Pin Diagram......................................................................................................5
1-3-2 Pin Function Summary.....................................................................................8
1-4 Overview of Functions.................................................................................................12
1-4-1 Block Diagram................................................................................................12
1-5 Electrical Characteristics..............................................................................................13
1-5-1 Absolute Maximum Ratings...........................................................................13
1-5-2 Operating Conditions......................................................................................14
1-5-3 DC Characteristics.........................................................................................17
1-5-4 A/D Converter Characteristics........................................................................21
1-6 Option...........................................................................................................................22
1-6-1 ROM Option...................................................................................................22
1-6-2 Option Check List...........................................................................................23
1-7 Outline Drawings .........................................................................................................24
Chapter 2 Basic CPU Functions
2-1 Overview......................................................................................................................28
2-2 Address Space
2-2-1 Memory Configuration...................................................................................28
2-2-2 Special Function Registers .............................................................................28
2-3 Bus Interface ................................................................................................................29
2-3-1 Overview .......................................................................................................30
2-3-2 Control Register..............................................................................................30
2-4 Interrupts ......................................................................................................................31
2-4-1 Accepting and Returning from Interrupts.......................................................31
2-4-2 Interrupt Sources and Vector Addresses.........................................................33
2-4-3 Interrupt Control Registers.............................................................................34
2-5 Reset.............................................................................................................................36
<Contents 1>
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Chapter 3 Port Functions
3-1 Overview......................................................................................................................38
3-2 Port Control Registers..................................................................................................41
3-2-1 Overview ........................................................................................................41
3-2-2 I/O Port Control Registers..............................................................................45
3-3 I/O Port Configuration and Functions..........................................................................47
Chapter 4 Timer Functions
4-1 Overview......................................................................................................................56
4-2 8-bit Timer Operation (timers 2, 3)..............................................................................62
4-2-1 Overview ........................................................................................................62
4-2-2 Operation ........................................................................................................63
4-3 16-bit Timer Operation (timer 4)..................................................................................69
4-3-1 Overview ........................................................................................................69
4-3-2 Operation ........................................................................................................69
4-4 8-bit Timer Operation (timer 5)....................................................................................76
4-4-1 Overview ........................................................................................................76
4-4-2 Operation ........................................................................................................76
4-5 Time Base Operation....................................................................................................77
4-5-1 Overview ........................................................................................................77
4-5-2 Operation ........................................................................................................77
4-6 Watchdog Timer Operation..........................................................................................78
4-6-1 Overview ........................................................................................................78
4-6-2 Setup and Operation .......................................................................................78
4-7 Remote Control Output Operation...............................................................................79
4-7-1 Overview ........................................................................................................79
4-7-2 Setup and Operation .......................................................................................79
4-8 Buzzer Output ..............................................................................................................80
4-8-1 Buzzer Output Setup and Operation...............................................................80
4-9 Timer Function Control Registers................................................................................81
4-9-1 Overview ........................................................................................................81
4-9-2 Programmable Timer/Counters ......................................................................82
4-9-3 Timer Mode Registers ....................................................................................85
4-9-4 Timer Control Registers .................................................................................89
<Contents 2>
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Chapter 5 Serial Functions
5-1 Overview......................................................................................................................92
5-2 Synchronous Serial Interface .......................................................................................94
5-2-1 Overview ........................................................................................................94
5-2-2 Setup and Operation .......................................................................................94
5-2-3 Serial Interface Transfer Timing.....................................................................99
5-3 Half-duplex UART Serial Interface ...........................................................................101
5-3-1 Overview ......................................................................................................101
5-3-2 Setup and Operation .....................................................................................101
5-3-3 How to Use the Baud Rate Timer.................................................................105
5-4 Serial Interface Control Registers..............................................................................106
5-4-1 Overview ......................................................................................................106
5-4-2 Transmit/Receive Shift Registers, Receive Data Buffer ..............................107
5-4-3 Serial Interface Mode Registers ...................................................................108
5-4-4 Serial Interface Control Register ..................................................................112
Chapter 6 A/D Conversion Functions
6-1 Overview....................................................................................................................114
6-2 A/D Conversion..........................................................................................................115
6-3 A/D Converter Control Registers...............................................................................117
6-3-1 Overview.......................................................................................................117
6-3-2 A/D Control Register (ANCTR)...................................................................118
6-3-3 A/D Buffers (ANBUF).................................................................................120
Chapter 7 AC Zero-Cross Circuit/Noise Filter
7-1 Overview....................................................................................................................122
7-2 AC Zero-Cross Circuit Operation..............................................................................123
7-2-1 Setup and Operation .....................................................................................123
7-3 Noise Filter.................................................................................................................124
7-3-1 Overview ......................................................................................................124
7-3-2 Example Input and Output Waveforms for Noise Filter...............................125
7-4 AC Zero-Cross Control Register................................................................................126
7-4-1 Overview ......................................................................................................126
7-4-2 Noise Filter Control Register (NFCTR).......................................................127
<Contents 3>
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Appendices
8-1 EPROM Versions.......................................................................................................130
8-1-1 Overview ......................................................................................................130
8-1-2 Cautions on Use............................................................................................131
8-1-3 Erasing Written Data in Windowed Packages..............................................132
(PX-AP101C11-SDC, PX-AP101C11-FBC)
8-1-4 Characteristics of EPROM Versions.............................................................133
8-1-5 Writing to Internal EPROM..........................................................................134
8-1-6 Cautions on Handling the ROM Writer........................................................136
8-1-7 Option Bit .....................................................................................................137
8-1-8 Writing Adapter Connection.........................................................................138
8-2 Instruction Sets...........................................................................................................141
8-3 Instruction Maps.........................................................................................................147
8-4 Special Function Registers.........................................................................................149
<Contents 4>
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Chapter 1 Overview
2
1-1 Product Overview
1-1-1 Overview
The MN101C00 series of 8-bit single-chip microcomputers incorporate several types of
peripheral functions. This chip series is well suited for VCR, MD, TV, CD, LD, printer,
telephone, home automation, pager, air conditioner, PPC, remote control, fax machine,
musical instrument, and other applications.
The MN101C117 has an internal 16 KB of ROM and 512 bytes of RAM. Peripheral
functions include four sets of timers, one set of serial interfaces, an A/D converter, and
remote control output. The configuration of this microcomputer is well suited for applications
as a system controller in a VCR selection timer, CD player, MD, or portable terminal.
With two oscillation systems (max. 20 MHz/32 kHz) contained on the chip of 48-pin QFP
package, the system clock can be switched between high and low speed.
When the oscillation source (fosc) is 8 MHz, a machine cycle lasts for 250 ns. When fosc is
20 MHz, a machine cycle is 100 ns. The package are available with three types of 42-pin
SDIP, 44-pin QFP and 48-pin QFH.
1-1-2 Product Summary
This manual describes the following models of the MN101C11 series. These products have
identical functions.
Table 1-1-1 Product Summary
∗1
Under development
Product Overview
Model ROM Size RAM Size Classification
MN101C115*18 KB 256 bytes Mask ROM version
MN101C117 16 KB 512 bytes Mask ROM version
MN101CP117 16 KB 512 bytes EPROM version
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Chapter 1 Overview
3
Hardware Functions
1-2 Hardware Functions
ROM/RAM Size: <Single chip mode>
Internal ROM∗216,384×8-bit*3
Internal RAM∗2512×8-bit
Machine Cycles: High speed mode 0.10µs/20MHz (4.5V to 5.5V)
0.25µs/8MHz(2.7V to 5.5V)
1.00µs/2MHz(2.0V to 5.5V)
Low speed mode 125µs/32KHz(2.0V to 5.5V)*4
Interrupts: 12 interrupts(11 interrupts except for 48-pin QFH package)
<External interrupts>
The active edge can be selected for all external interrupts
IRQ0 External interrupt (can be connected to noise filter)
IRQ1 External interrupt (can determine zero crossings, can be
connected to noise filter)
IRQ2 External interrupt
IRQ3 External interrupt *4
<Timer interrupts>
TM2IRQ Timer 2 (8-bit timer)
TM3IRQ Timer 3 (8-bit timer)
TM4IRQ Timer 4 (16-bit timer)
TM5IRQ Timer 5 (8-bit timer)
TBIRQ Clock timer interrupts
<Serial communication interrupt>
SC0IRQ Serial 0 (synchronous + simple UART
<A/D conversion complete interrupt>
ADIRQ A/D conversion complete
<Watchdog timer interrupt>
NMI Overflow of watchdog timer
Timer/Counters:five timers, all can generate interrupts
Timer 2 8-bit timer
Square wave output, 8-bit PWM output are possible,
Clock source: fs, fs/4, fx*4, TM2IO pin input
Timer 3 8-bit timer
Square wave output, synchronous serial/UART baud rate
timer
Clock source: fosc, fs/4, fs/16, TM3IO pin input
Remote control carrier can be generated.
∗2 Differs depending upon the
model.
[☞1-1-2 "Product Summary"]
*3 Bit 8 of the last address for
the built-in ROM of
MN101C11X
is an optional bit; therefore, this
cannot be used as an ordinary
ROM.
*4 Exclusive for a 48-pin QFH
product.
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Chapter 1 Overview
4
Timers 2 and 3 can be cascaded.
Timer 4 16-bit timer
Square wave output, 16-bit PWM output are possible.
Clock source: fosc, fs/4, fs/16, TM4IO pin input
Input capture function
Time base timer
Clock source: fosc, fs/4, fx*4, fx/2
13
*4or fosc/213
XIOat 32kHz, can be set to measure one minute intervals*4
Can operate independently as timer 5 (8-bit timer).
Watchdog timer
Selected by the mask option as fs/216, fs/218, or fs/220
Remote control Based on the timer output, a remote control carrier with duty ratio
carrier output: of 1/2, 1/3 can be output.
Buzzer output: Output frequency can be selected from fs/29, fs/210, fs/211 or fs/212.
Serial interface: Synchronous/ Simple UART (half-duplex)
Transfer clock: fs/2, fs/4, fs/16, 1/2 of timer 3 output
When using timer 3, the transfer rates for a 12MHz
oscillation are 19200/9600/4800/2400/1200/300 bps.
MSB or LSB can be selected as the first bit for transfer. An
arbitrary transfer size of 1 to 8 bits can be selected.
A/D converter: 10 bits x 8 channels
LED driver function:8 pins
Ports: I/O ports 25 ports (8 have dual functions)*5
LED (large current) driver ports:
8 ports (push-pull configuration)
Input ports 11 ports (all have dual functions) *6
Number of pins with dual function for external interrupts: 3*7
(One of which can also be used for zero-cross input.)
Number of pins with dual function for A/D input: 8
Operation mode input pin: 1
Reset input pin: 1
Operation modes: NORMAL mode
SLOW mode*4
HALT mode
STOP mode
and switches operating clock*4
Package: 42-SDIP, 44-QFP, 48-QFH
Hardware Functions
∗
5 26 ports for 44-QFP
27 ports for 48-QFH
∗
6 12 ports for 48-QFH
∗
7 4 ports for 48-QFH
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Chapter 1 Overview
5
Pins
1-3 Pins
1-3-1 Pin Diagram
Figure 1-3-1 Pin Diagram (42-SDIP: TOP VIEW)
TXD,SBO0,P00
RXD,SBI0,P01
SBT0,P02
BUZZER,P06
RMOUT,P10
P11
TM2IO,P12
TM3IO,P13
TM4IO,P14
IRQ0,P20
IRQ1,P21
IRQ2,P22
P60
P61
P62
P63
P64
P65
P66
P67
NRST,P27
VSS
OSC1
OSC2
VDD
PA7,AN7
PA6,AN6
PA5,AN5
PA4,AN4
PA3,AN3
PA2,AN2
PA1,AN1
PA0,AN0
P80,LED0
P81,LED1
P82,LED2
P83,LED3
P84,LED4
P85,LED5
P86,LED6
P87,LED7
MMOD
MN101C117/115
４２-ＳＤＩＰ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
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Chapter 1 Overview
6
Figure 1-3-2 Pin Diagram (44-QFP: TOP VIEW)
MN101C117/115
LED3,P83
LED2,P82
LED1,P81
LED0,P80
AN6,PA6
AN0,PA0
AN1,PA1
AN2,PA2
AN3,PA3
AN4,PA4
AN5,PA5
P63
P62
P61
P60
P11
P22,IRQ2
P21,IRQ1,SENS
P20,IRQ0
P14,TM4IO
P13,TM3IO
P12,TM2IO
P66
P65
P67
P70
MMOD
P87,LED7
P86,LED6
P85,LED5
P27,NRST
P64
P84,LED4
TXD,SBO0,P00
RXD,SBI0,P01
SBT0,P02
NC
VSS
OSC2
VDD
OSC1
AN7,PA7
BUZZER,P06
RMOUT,P10
４４-ＱＦＰ
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20 21 22
23
24
25
26
27
28
29
30
31
32
33
3435363738394041424344
Pins
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Chapter 1 Overview
7
Pins
Figure 1-3-3 Pin Diagram (48-QFH: TOP VIEW)
LED3,P83
LED2,P82
LED1,P81
LED0,P80
NC
AN6,PA6
AN0,PA0
AN1,PA1
AN2,PA2
AN3,PA3
AN4,PA4
AN5,PA5
P63
P62
P61
P60
P11
P23,IRQ3
P22,IRQ2
P21,IRQ1,SENS
P20,IRQ0
P14,TM4IO
P13,TM3IO
P12,TM2IO
MN101C117/115
P66
P65
P67
P70
P27,NRST
MMOD
P87,LED7
P86,LED6
P85,LED5
P71
P64
TXD,SBO0,P00
RXD,SBI0,P01
SBT0,P02
XO
VSS
XI
OSC2
VDD
OSC1
AN7,PA7 P84,LED4
RMOUT,P10
BUZZER,P06
４８-ＱＦＨ
1
2
3
4
5
6
7
8
9
10
11
1213 14 15 16 17 18 19 20 21 22 23 24
25
26
27
28
29
30
31
32
33
34
35
36
3738394041424344454648 47
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Chapter 1 Overview
8
1-3-2 Pin Function Summary
*The pin numbers in the list correspond to the QFH package(Refer
to Figure 1-3-3 Pin connection.) Be careful when using SDIP and
QFP packages.
Table 1-3-1 Pin Function Summary (1/4)
Pins
Pin No. Name Type Dual Function Function Description
17 VSS – Power supply pins Apply 2.0V to 5.5V to VDD and 0V to VSS.
14 VDD
16 OSC1 Input Clock input pin
Connect these oscillation pins to ceramic or crystal oscillators for high-
15 OSC2 Output Clock output pin
speed clock operation.
If the clock is an external input, connect it to OSC1 and leave OSC2
open. The chip will not operate with an external clock when using either
the STOP or SLOW modes.
18 XI Input Clock input pin
Connect these oscillation pins to ceramic or crystal oscillators for low-
19 XO Output Clock output pin
speed clock operation.
If the clock is an external input, connect it to XI and leave XO open.
The chip will not operate with an external clock when using the STOP
mode. If these pins are not used, connect XI to VSS and leave XO open.
*42-SDIP and 44-QFP packages have no pins of this kind.
43 RST I/O P27 Reset pin This pin resets the chip when power is turned on, is allocated as P27 and
contains an internal pull-up resistor (Typ. 35 kΩ).
Setting this pin low initializes, the internal state of the device
is initialized. Thereafter, setting the input to an"H"level release the reset
The hardware waits for the system clock to stabilize, and then
processes the reset interrupt.
Also, if "0" is written to P27 and the reset is initiated by software, a low
level will be output. The output has an n-channel open-drain configuration.
If a capacitor is to be inserted between RST and VDD, it is
recommended that a discharge diode be placed between RST and VDD.
20 to 23 P00 to P02 I/O SBO0(TXD), I/O port 0 4-bit CMOS tri-state I/O port.
P06 SBI0(RXD), Each bit can be set individually as either an input or output by the
SBT0, P0DIR register. A pull-up resistor for each bit can be selected
DK individually by the P0PLU register.
(BUZZER) At reset, the input mode is selected and pull-up resistors are disabled
(high impedance output).
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Chapter 1 Overview
9
Table 1-3-1 Pin Function Summary (2/4)
41 to 42 P70 to P71 I/O I/O port 7 2-bit CMOS tri-state I/O port.
Each individual bit can be switched to an input or output by the P7DIR
register. A pull-up or pull-down resistor for each bit can be selected
individually by the P7PLUD register.
However, pull-up and pull-down resistors cannot be mixed.
At reset, the input mode is selected and pull-up resistors are disabled (high
impedance output).
P70 and P71 pins do not exist for 42-SDIP package. P71 pin does not exist
for 44-QFP package, either.
1 to 4 P80 to P87 I/O LED0 to 7 I/O port 8
45 to 48
8-bit CMOS tri-state I/O port.
Each individual bit can be switched to an input or output by the P8DIR
register. A pull-up resistor for each bit can be selected individually by
the P8PLU register. When configured as outputs, these pins can drive
LED segments, directly.
At reset, the input mode is selected and pull-up resistors for P80 to P87
are disabled (high impedance output).
Pins
33 to 40 P60 to P67 I/O I/O port 6 8-bit CMOS tri-state I/O port.
Each bit can be set individually as either an input or output by the P6DIR
register. A pull-up resistor for each bit can be selected individually by the
P6PLU register. At reset, the input mode is selected and pull-up resistors
for P60 to P67 are disabled (high impedance output).
Pin No. Name Type Dual Function Function Description
24 to 28 P10 to P14 I/O RMOUT, I/O port 1
TM2IO to
TM4IO
29 to 32
P20
to
P23
Input IRQ0, Input port 2
IRQ1(SENS),
IRQ2 to 3
43 P27 Input RST Input port 2
5-bit CMOS tri-state I/O port.
Each bit can be set individually as either an input or output by
theP1DIR register. A pull-up resistor for each bit can be selected
individually by the P1PLU register. At reset, the input mode is
selected and pull-up resistors are disabled (high impedance output).
4-bit input port. A pull-up resistor for each bit can be selected
individually by the P2PLU register. At reset, the input mode is
selected and pull-up resistors are disabled (high impedance output).
P23 pin does not exist for 42-SDIP, 44-QFP packages.
Port P27 has an n-channel open-drain configuration. When "0" is
written and the reset is initiated by software, a low level will be
output.
8-bit input port.
A pull-up or pull-down resistor for each bit can be selected
individually by the PAPLUD register. However, pull-up and pull-
down resistors cannot be mixed.
At reset, the PA0 to PA7 input mode is selected and pull-up resistors
are disabled.
6 to 13 PA0 to PA7 Input
AN0
to
AN7
Input port A
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Table 1-3-1 Pin Function Summary (3/4)
22 Buzzer I/O P06 Buzzer output
Chapter 1 Overview
10 Pins
Pin No. Name Type Dual Function Function Description
20 TXD Output SBO0(P00) UART transmit
data output pin
21 RXD Input SBI0(P01) UART receive
data input pin
20 SBO0 Output TXD(P00) Transmit data output pin for serial interfaces 0. The output
configuration, either CMOS push-pull or n-channel open-drain, and
pull-up resistors can be selected by the software. Set these pins to the
output mode by the P0DIR register.
SBO0 is allocated as P00. This may be used as normal I/O pin when
the serial interface is not used.
Clock I/O pin for serial interface 0. The output configuration, either
CMOS push-pull or n-channel open-drain output, can be selected by
the software. The direction of SBT0 is selected by the P0DIR register
in accordance with the communication mode. Pull-up resistors can be
selected by the P0PLU register. SBT0 is allocated as P02. This can be
used as normal I/O pin when the serial interface is not used.
22 SBT0 I/O P02 Serial interface
clock I/O pin
Receive data input pin for serial interfaces 0. Pull-up resistor can be
selected by the P0PLU register.
Set these pins to the input mode by the P0DIR register.
SBI0 is allocated as P01. This can be used as normal I/O pin when the
serial interface is not used.
21 SBI0 Input RXD(P01)
Serial interface
transmit data
output pin
Serial interface
receive data input
pin
24
RMOUT
I/O P10
Remote control transmit
signal output pin
Output pin for remote control transmit signal with a carrier signal.
Can be used as a normal I/O pin when remote control is not used.
In the serial interface in UART mode, these pins are configured as
the receive data input pin and transmit data output pin.
A push-pull or n-channel open-drain configuration can be selected for
TXD by the SC0MD1 register.
Pull-up resistors can be selected by the P0PLU register. The TXD
and RXD pins are also allocated as P00 and P01 respectively. When
not used as serial/UART pins, these can be used as normal I/O pins.
Event counter clock input pins, overflow pulse output pins and PWM
signal output pins for timer 2 to 4.
To use these pins as event clock inputs, configure them as inputs by
the P1DIR register. For overflow pulse and PWM output, configure
these pins as outputs by the P1DIR register. When the pins are used as
inputs, pull-up resistors can be specified by the P1PLU register. When
not used for timer I/O, these can be used as normal I/O pins.
Piezoelectric buzzer driver pin. The driving frequency can be
selected in the range of fs/2 to fs/2 by the DLYCTR register. Select
output mode by the P0DIR register and select buzzer output by the
DLYCTR register. When not used for buzzer output, this pin can be
used as a normal I/O pin.
26 to 28
TM2IO
to I/O P12 to P14 Timer I/O pins
TM4IO
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Chapter 1 Overview
Pins
Table 1-3-1 Pin Function Summary (4/4)
11
Pin No. Name Type Dual Function Function Description
The valid edge for these external interrupt input pins can be selected
with the IRQnICR registers.
IRQ1 is an external interrupt pin that is able to determine AC zero
crossings. It can also be used as a normal external interrupt.
When IRQ0 to 3 are not used for interrupts, these can be used as normal
I/O pins.
29 to 32 IRQ0 to Input P20,
External interrupt
IRQ3 P21(SENS),
input pins
P22,P23
6 to 13 AN0 to AN7 Input PA0 to PA7
Analog input pins
Analog input pins for an 8-channel, 10-bit A/D converter.
When not used for analog input, these pins can be used as normal I/O
pins.
44 MMOD Input Test mode
switch input pin
This pin sets the test mode.
Must be set to L.
30 SENS Input IRQ1(P21) AC zero-cross
detection input pin
SENS is an input pin for an AC zero-cross detection circuit. The AC zero-
cross circuit outputs a high level when the input is at an intermediate level. It
outputs a low level at all other times. SENS is connected to the P21 input
circuit and the IRQ1 interrupt circuit. When the AC zero-cross detection
circuit is not used, this pin can be used as a normal P21 input. The P21IM flag
of the FLOAT1 register sets which input is selected.
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Chapter 1 Overview
12 Overview of Function
1-4 Overview of Functions
1-4-1 Block Diagram
Figure 1-4-1 Block Diagram of Functions)
CPU
MN101C00
System
clock
oscillator
Sub-clock
oscillator
ROM
16 KB RAM
512 bytes
8-bit timer 2
8-bit timer 3
16-bit timer 4 Time base timer 5
Serial interface 0
Watchdog timer
External interrupt
A/D conversion
OSC1
OSC2
XI
XO
VSS
VDD
RST
MMOD
TXD,SBO0,P00
RXD,SBI0,P01
SBT0,P02
P06
AN7,PA7
Port 0
RMOUT,P10
P11
TM2IO,P12
TM3IO,P13
TM4IO,P14
IRQ0,P20
SENS,IRQ1,P21
IRQ2,P22
IRQ3,P23
P60
P61
P62
P63
P64
P65
P66
P67
P80,LED0
RST,P27
Port 1
Port A
Port 6
Port 7
AN6,PA6
AN5,PA5
AN4,PA4
AN3,PA3
AN2,PA2
AN1,PA1
AN0,PA0
Port 2
P81,LED1
P82,LED2
P83,LED3
P84,LED4
P85,LED6
P86,LED6
P87,LED7
P70
P71
Port 8
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Chapter 1 Overview
13
Electrical Characteristics
1-5 Electrical Characteristics
1-5-1 Absolute Maximum Ratings
∗2∗3
Note: ∗1Applicable even for an interval of 100ms.
*2 Insert at least one bypass capacitor of 0.1
µ
F or more between a power source pin
and GND to prevent from latchup.
*3 Absolute maximum ratings indicate the allowable limit to which applied voltage
does not damage a chip, not guarantee the operation.
This LSI manual describes
standard specifications.
Before using the LSI, please
obtain product specifications
from the sales office.
Contents Model MN101C117/115
Classification CMOS integrated circuit
Use General purpose
Function CMOS, 8-bit, single-chip microcomputer
Parameter Symbol Rating Unit
1 Supply voltage VDD –0.3
to
+7.0 V
2 Input clamp current (SENS) IC –500
to
500 µA
3 Input pin voltage VI–0.3
to
VDD+0.3 V
4 Output pin voltage VO–0.3
to
VDD+0.3 V
5 I/O pin voltage VIO1 –0.3
to
VDD+0.3 V
6
Peak output
I OL1 (peak)
7current I OL2 (peak)
8I
OH (peak) mA
9
Average output
I OL1 (avg)
10 current*1 I OL2 (avg)
11 I OH (avg)
12 Tolerable loss PD mW
13
Ambient operating temperature
Topr °C
14 Storage temperature Tstg °C
30
20
–10
20
15
–5
400
–40
to
85
–55
to
+125
P8
Except P8
All pins
P8
Other than P8
All pins
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Chapter 1 Overview
14 Electrical Characteristics
1-5-2 Operating Conditions
Ta=–40 to +85°C VDD=2.0 to 5.5V VSS=0V
Note: *1. Only for 48-QFH package
∗2t c1, t c2, t c3: OSC1 is the CPU clock
t c4: XI is the CPU clock
Parameter Symbol Conditions Rating Unit
MIN TYP MAX
Supply voltage
1V
DD1 fosc ≤20.0MHz 4.5 5.5
2Supply voltage VDD2 fosc ≤8.39MHz 2.7 5.5 V
3during operation VDD3 fosc ≤2.00MHz 2.0 5.5
4V
DD4 *1fx = 32.768kHz 2.0 5.5
5
Voltage to maintain RAM data
VDD5 STOP mode 1.8 5.5
Operating speed ∗2
6 tc1 VDD=4.5
to
5.5V 0.100
7
Instruction execution time
tc2 VDD=2.7
to
5.5V 0.238 µs
8 tc3 VDD=2.0
to
5.5V 1.00
9 tc4 *1VDD=2.0
to
5.5V 40 125
Crystal oscillator 1 Fig. 1-5-1
10 Crystal frequency fxtal 1 VDD=4.5
to
5.5V 1.0 20.0 MHz
11 External capacitors C11 20 pF
12 C12 20
13
Internal feedback resistor
RF10 700 kΩ
Crystal oscillator 2 Fig. 1-5-2*1
14 Crystal frequency fxtal 2 32.768 kHz
15 External capacitors C21 20 pF
16 C22 20
17
Internal feedback resistor
RF20 4.0 MΩ
OSC1
700kΩ
Typ
OSC2
MN101C
fxtal1
C12 C11
XI
4.0MΩ
Typ
XO
MN101C
fxtal2
C22 C21
The instruction cycle is twice the clock cycle.
The feedback resistor is built-in.
Figure 1-5-1 Crystal Oscillator 1
The instruction cycle is four times the clock cycle.
The feedback resistor is built-in.
Figure 1-5-2 Crystal Oscillator 2 *1
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Chapter 1 Overview
15
Electrical Characteristics
∗1Set the clock duty ratio to 45 to 55%.
*2 Applicable only for 48-pin QFH package
Parameter Symbol Conditions Rating Unit
MIN TYP MAX
External clock input 1 OSC1 (OSC2 is unconnected)
18 Clock frequency fOSC 1.0 20.0 MHz
19 High level pulse width∗twh 1 ∗120.0 30.0 ns
20 Low level pulse width∗twl 1 20.0 30.0
21 Rise time twr 1 5.0 ns
22 Fall time twf 1 5.0
External clock input 2 XI (XO is unconnected)*2
23 Clock frequency fx 32.768 100 kHz
24 High level pulse width∗twh 2 ∗13.5 µs
25 Low level pulse width∗twl 2 3.5
26 Rise time twr 2 20 ns
27 Fall time twf 2 20
Fig. 1-5-3
Fig. 1-5-3
Fig. 1-5-4
Fig. 1-5-4
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Chapter 1 Overview
16 Electrical Characteristics
Figure 1-5-3 OSC1 Timing Chart
Figure 1-5-4 XI Timing Chart
twh1 twl1
0.9VDD
0.1VDD
twf1twr1
twh2 twl2
0.9VDD
0.1VDD
twf2twr2
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1-5-3 DC Characteristics
Ta=–40 to +85°C VDD=2.0 to 5.5V VSS=0V
Notes: ∗1Measured under conditions of Ta=25°C and no load.
The supply current during operation, IDD1 (IDD2), is measured under the
following conditions: After all I/O pins are set to input mode and the oscillation
is set to <NORMAL mode>, the MMOD pin is fixed at VSS, the input pins are
fixed at VDD, and a 20MHz (8.39MHz) square wave of amplitude VDD,VSS is input
to the OSC1 pin.
The supply current during operation, IDD3, is measured under the following
conditions: After all I/O pins are set to input mode and the oscillation is set to
<SLOW mode>, the MMOD pin is fixed at VSS, the input pins are fixed at VDD,
and a 32.768kHz square wave of amplitude VDD,VSS is input to the XI pin.
The supply current during HALT mode, IDD5(IDD6), is measured under the
following conditions: After all I/O pins are set to input mode and the oscillation
is set to <HALT mode>, the MMOD pin is fixed at VSS, the input pins are fixed
at VDD, and an 32.768kHz square wave of amplitude VDD,VSS is input to the XI
pin.
The supply current during STOP mode IDD7(IDD8) is measured under the following
conditions: After the oscillation mode is set to <STOP mode>, the MMOD pin is
fixed at VSS, the input pins are fixed at VDD, and the OSC1 and XI pins are
unconnected.
*2 The items IDD5(IDD6) and IDD7(IDD8) are applicable only for 48-pin QFH package.
Parameter Symbol Conditions Rating Unit
MIN TYP MAX
Supply current (no load at output)∗1
1 Supply current IDD1
fosc=20.0MHz,VDD=5V 25 60 mA
2 during operation IDD2 fosc=8.39MHz,VDD=5V 10 25
3I
DD3 *2 fx =32.768kHz,VDD=3V 100
4
Supply current during HALT mode
IDD5 *2 fx =32.768kHz,VDD=3V 8
Ta=25
?W2@6X
?7<?B1
?@e?@f?O2@@6T2@?f
?3=?C5e?W2(M??I4@@Lf
?V4@0YeW&(Yf?I'1f
7@H?gV'f
?J@5hg
?7@Hhg
?@@?hg
?@@?hg
?@@?hg
?@@?hg
?@@?hg
?@@?hg
?3@Lhg
?N@1h?@f
3@L?gJ5f
V')Xf?W.Yf
?V4)K?eO.Y?f
?I4@@@0Yg
5I
DD6*2 Ta=-40
to
85˚C µA
6
Supply current during STOP mode
IDD7 VDD=5V, Ta=25˚C 0 2
7I
DD8 VDD=5V, Ta=-40
to
85˚C 0 20
Chapter 1 Overview
17
Electrical Characteristics
18
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Chapter 1 Overview
18 Electrical Characteristics
Ta=–40 to +85°C VDD=2.0 to 5.5V VSS=0V
Parameter Symbol Conditions Rating Unit
MIN TYP MAX
Input pin 1 MMOD
8 Input high voltage 1 VIH1 0.8VDD VDD V
9 Input high voltage 2 VIH2 VDD=4.5
to
5.5V 0.7VDD VDD V
10 Input low voltage 1 VIL1 0 0.2VDD V
11 Input low voltage 2 VIL2 VDD=4.5
to
5.5V 0 0.3VDD V
12 Input leakage current ILK1 VIN = 0
to
VDD ±10 µA
Input pin 2 P20, P22~P23 (Schmitt trigger input)
13 Input high voltage VIH3 0.8VDD VDD V
14 Input low voltage VIL3 0 0.2VDD V
15 Input leakage current ILK3 VIN=0
to
VDD ±10 µA
16 Input high current IIH3 –30 –100 –300 µA
Input pin 3—1 P21 (Schmitt trigger input)
17 Input high voltage VIH4 0.8VDD VDD V
18 Input low voltage VIL4 0 0.2VDD V
19 Input leakage current ILK4 VIN=0
to
VDD ±10 µA
20 Input high current IIH4 –30 –100 –300 µA
Input pin 3—2 P21 (when used as SENS)
21 Input high voltage 1 VDHH VDD=5.0V 4.5 VDD V
22 Input low voltage 1 VDLH Fig. 1-5-5 VSS 3.5
23 Input high voltage 2 VDHL 1.5 VDD V
24 Input low voltage 2 VDLL VSS 0.5
25 Input leakage current ILK10 VIN=0V
to
VDD ±10 µA
26 Input clamp current IC10 ±400
VDD=5V, VIN=1.5V
Pull-up resistor ON
VDD=5V, VIN=1.5V
Pull-up resistor ON
VDD=5.0V
VIN>VDD, VIN<0V
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Chapter 1 Overview
19
Electrical Characteristics
SENS pin
Figure 1-5-5 Operation of AC Zero-Cross Detection Circuit
Ta=–40 to +85°C VDD=2.0 to 5.5V VSS=0V
← trs→
Input voltage level 1→
Input voltage level 2→
(Input)
(Output)
VDD
VDHL
VDHH
VDLL
VDLH
VSS
← tfs →
27 Rise time trs Fig. 1-5-5 30 µs
28 Fall time tfs 30
Parameter Symbol Conditions Rating Unit
MIN TYP MAX
Input pin 4 PA0~PA7
29 Input high voltage 1 VIH5 0.8VDD VDD V
30 Input high voltage 2 VIH6 VDD=4.5
to
5.5V 0.7VDD VDD V
31
Input low voltage 1
VIL5 0 0.2VDD V
32
Input low voltage 2
VIL6 VDD=4.5
to
5.5V 0 0.3VDD V
33 Input leakage current ILK5 VIN=0
to
VDD ±2 µA
34 Input high current IIH5 –30 –100 –300 µA
35 Input low current IIL5 80 180 400 µA
VDD=5V, VIN=1.5V
Pull-up resistor ON
VDD=5V, VIN=3.5V
Pull-down resistor ON
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Chapter 1 Overview
20 Electrical Characteristics
Ta=–40 to +85°C VDD=2.0 to 5.5V VSS=0V
Parameter Symbol Conditions Rating Unit
MIN TYP MAX
I/O pin 5 P27 (RST)
36 Input high voltage VIH7 0.9VDD VDD V
37 Input low voltage VIL7 0 0.2VDD V
38 Input leakage current ILK7 VIN = 0
to
VDD ±10 µA
39 Input high current Iih -30 -100 -300 µA
I/O pin 6 P00 to P06, P10 to P14 (Schmitt trigger input)
40 Input high voltage VIH8 0.8VDD VDD V
41 Input low voltage VIL8 0 0.2VDD V
42 Input leakage current ILK8 VIN=0
to
VDD ±10 µA
43 Input high current IIH8 –30 –100 –300 µA
44 Output high voltage VOH8 VDD = 5V, IOH = –0.5mA 4.5 V
45 Output low voltage VOL8 VDD = 5V, IOL = 1.0mA 0.5 V
I/O pin 7 , P60 to P67
46 Input high voltage 1 VIH9 0.8VDD VDD V
47 Input high voltage 2 VIH10 VDD=4.5
to
5.5V 0.7VDD VDD V
48 Input low voltage 1 VIL9 0 0.2VDD V
49 Input low voltage 2 VIL10 VDD=4.5
to
5.5V 0 0.3VDD V
50 Input leakage current ILK9 VIN=0
to
VDD ±10 µA
51 Input high current IIH9 –30 –100 –300 µA
52 Output high voltage VOH9 VDD = 5V, IOH = -0.5mA 4.5 V
53 Output low voltage VOL9 VDD = 5V, IOL = 1.0mA 0.5 V
I/O pin 8 P70 to P71
54 Input high voltage 1 VIH11 0.8VDD VDD V
55 Input high voltage 2 VIH12 VDD=4.5
to
5.5V 0.7VDD VDD V
56 Input low voltage 1 VIL11 0 0.2VDD V
57 Input low voltage 2 VIL12 VDD=4.5
to
5.5V 0 0.3VDD V
58 Input leakage current ILK11 VIN = 0
to
VDD ±10 µA
59 Input high current IIH11 –30 –100 –300 µA
60 Input low current IIL11 30 100 300 µA
61 Output high voltage VOH11 VDD = 5V, IOH = –0.5mA 4.5 V
62 Output low voltage VOL11 VDD = 5V, IOL = 1.0mA 0.5 V
VDD=5V, VIN=1.5V
Pull-up resistor ON
VDD=5V, VIN=1.5V
Pull-up resistor ON
VDD=5V, VIN=3.5V
Pull-down resistor ON
VDD=5V, VIN=1.5V
Pull-up resistor ON
VDD=5V, VIN=1.5V
Pull-up resistor built in
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Chapter 1 Overview
Ta=–40 to +85°C VDD=2.0 to 5.5V VSS=0V
1-5-4 A/D Converter Characteristics
Ta=–40 to+85°C VDD=2.0 to 5.5V VSS=0V
Parameter Symbol Conditions Rating
Unit
MIN TYP MAX
1 Resolution 10 Bits
2 Nonlinear error 1 ±3 LSB
3 Differential linear error 1 ±3 LSB
4 Nonlinear error 2 ±5 LSB
5 Differential linear error 2 ±5 LSB
6 Zero traction voltage 30 100 mV
7
Full-scale transition voltage
30 100 mV
8A/D conversion time TAD = 800ns 9.6 µs
9 fx = 32.768kHz 183 µs
10 Sampling time fOSC = 8MHz 1.0 36 µs
11 fx = 32.768kHz 30.5 µs
12
Analog input leakage current
When VDAIN = 0
to
5V is off ±2 µA
21
Electrical Characteristics
Parameter Symbol Conditions Rating
Unit
MIN TYP MAX
I/O pin 9 P80~P87
63 Input high voltage 1 VIH13 0.8VDD VDD V
64 Input high voltage 2 VIH14 VDD=4.5
to
5.5V 0.7VDD VDD V
65 Input low voltage 1 VIL113 0 0.2VDD V
66 Input low voltage 2 VIL14 VDD=4.5
to
5.5V 0 0.3VDD V
67 Input leakage current ILK13 VIN=0
to
VDD ±10 µA
68 Input high current IIH13 –30 –100 –300 µA
69 Output high voltage VOH13 VDD = 5V, IOH = –0.5mA 4.5 V
70 Output low voltage VOL13 VDD = 5V, IOL = 15mA 1.0 V
VDD=5V, VIN=1.5V
Pull-up resistor ON
VDD = 5.0V, VSS = 0V
VREF+=5.0V, VREF–=0V
TAD = 800ns
VDD = 5.0V, VSS = 0V
VREF–=5.0V, VREF–=0V
fx = 32.768kHz
VDD = 5.0V, VSS = 0V
VREF+=5.0V, VREF–=0V
TAD = 800ns
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Chapter 1 Overview
1-6 Option
1-6-1 ROM Option
The product equipped with this LSI or an EPROM with this LSI controls the oscillation
mode after resetting as well as the runaway-detection watchdog timer, using bits 2 to
0 of the last address of the built-in ROM.
■ Option bits
Figure 1-6 ROM Option ( Address:X'7FFF' )
22 Option
01243
NSSTRT
Watchdog timer cycle setting
WDSEL2
WDSEL1WDSEL2
PKG
SEL1
PKG
SEL2
−−−
567
Selection of oscillation mode
after resetting
SLOW mode
NORMAL mode
NSSTRT
0
1
fs/2
01
WDSEL1
0
1Ｘ
fs/2
fs/2
16
18
20
Packages
SDIP042-P-0600
QFP044-P-1010
PKGSEL2
0
1
QFH048-P-0707
PKGSEL1
Ｘ
0
1
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Chapter 1 Overview
23
Chapter 1 Overview
1-6-2 Option Form
1. Oscillation mode
MN101C
Model
Name Customer
Approval
Date:
SE No.
Type A Type B
2. Watchdog timer period setting
Detection Period
fs/216
fs/218
fs/220
Not used
Selection
Note: Type A: Operation begins from the reset cycle in the NORMAL mode.
Type B: Operation begins from the reset cycle in the SLOW mode.
3. Package selection
Package
SDIP042-P-0600
QFP044-P-1010
QFH048-P-0707
Selection
Contents of mask option are subject to change.
When placing an order for masks, please request the most recent option
list from the sales office.
Option of this product is used a part of the built-in ROM.
When placing an order for programme, please sed data on the address
of the option.
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Chapter 1 Overview
24 External Dimensions
1-7 Outline Drawings
Body Material: Epoxy Resin Lead Material:Fe Ni Lead Finish Method:Soldering dip
Figure 1-7-1 42-SDIP
The external dimensions of the package are subject to change. Before
using this product, please obtain product specifications from the sales
office.
Package code: SDIP042-P-0600
Unit: mm
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Chapter 1 Overview
Body Material: Epoxy Resin Lead Material:Fe Ni Lead Finish Method:Soldering dip
Figure 1-7-2 44-QFP
Package code: QFP044-P-1010
Unit: mm
The external dimensions of the package are subject to change. Before
using this product, please obtain product specifications from the sales
office.
External Dimensions) 25
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Chapter 1 Overview
Material: Epoxy Resin Lead Material:Fe Ni-42 Alloy
Lead Finish Method:Soldering dip
Figure 1-7-3 48-QFH
Package code: QFH048-P-0707
Unit: mm
The external dimensions of the package are subject to change. Before
using this product, please obtain product specifications from the sales
office.
26 External Dimensions
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Chapter 2 Basic CPU Functions
28 Overview/Address Space
2-1 Overview
Basic CPU functions are in conformance with the MN101C00 series manual
(architecture manual). This chapter describes specifications unique to the
MN101C117/115.
2-2 Address Space
2-2-1 Memory Configuration
Figure 2-2-1 Memory Map
∗Differs depending upon the model.
MN101C115 Internal RAM X'00000'
to
X'000FF' 256 bytes
Internal ROM X'04000'
to
X'05FFF' 8 KB
MN101CP117 Internal RAM X'00000'
to
X'001FF' 512 bytes
EP ROM X'04000'
to
X'01FFF' 16 KB
Internal
RAM space
Special function registers
X'00000'
X'00100'
512 bytes
256 bytes
256 bytes
128 bytes
64 bytes
16 KB
X'03F00'
X'00200'
X'04000'
X'04080'
X'040C0'
X'07FFF'
Internal
ROM space
∗
∗
Abs 8 addressing
access area
Data
Interrupt
vector table
Subroutine
vector table
Instruction code/
table data
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Chapter 2 Basic CPU Functions
29
Address Space
2-2-2 Special Function Registers
Memory control register(MEMCTR) is a 4-bit register which set up the base
Table 2-2-1 Register Map
0123456789ABCDEF
03F0X
03F1X
03F2X
03F3X
03F4X
03F5X
03F6X
03F7X
03F8X
03F9X
03FAX
03FBX
03FCX
03FDX
03FEX
03FFX
CPUM
MEMCTR
WDCTR DLYCTR
SC0MD0 SC0MD1 SC0CTR SC0TRB SC0RXB
TM2BC TM3BC
TM4BCL TM4BCH TM4ICL TM4ICH
TM5BC
TM2OC TM3OC
TM4OCL TM4OCH
TM5OC
TM2MD TM3MD TM4MD
ANCTR0 ANCTR1 ANBUF0 ANBUF1
TM5MD
P0OUT P1OUT P2OUT P6OUT P7OUT P8OUT
P0IN P1IN P2IN P6IN P7IN P8IN PAIN
P0DIR P1DIR P6DIR P7DIR P8DIR
P1OMD
PAIMD
P0PLU P1PLU P2PLU P6PLU
P7PLUD PAPLUD
P8PLU
FLOAT1
NMICR IRQ0ICRIRQ1ICR
TM2ICR TBICR SC0ICR
ADICR
IRQ2ICR
TM3ICRTM4ICR
TM5ICR
SC0MD2 SC0MD3
RMCTR NFCTR
CPU mode, memory control
Interrupt control
Serial interface control
Timer control
A/D control
Reserved
Port output
Port input
I/O mode control
Resistor control
I/O ports
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2-3 Bus Interface
2-3-1 Overview
The MN101C117, unlike other MN101C series microcomputers, does not
support memory expansion mode and processor mode.
2-3-2 Control Registers
The memory control register is a four-bit register that sets up wait-count at a
time of access to a base address of interrupt vector table and a special
register zone.
(1) Memory control register(MEMCTR)
Figure 2-3-1 Memory Control Register MEMCTR:X'03F01'R/W
Chapter 2 Basic CPU Functions
30 Bus Interface
76543210
MEMCTR IOW1 IOW0 IRWE
IRWE Set software write for interrupt request flag
0
1
Software write disable
Even if data is written to each interrupt control
register (xxxICR), the state of the interrupt
request flag (xxxIR) will not change.
Software write enable
IOW1 to 0
Number of wait cycles set when
accessing special register area
00
01
10
11
No wait cycles
1 wait cycle
2 wait cycles
3 wait cycles
Bus cycle at
20MHz oscillation
100ns
150ns
200ns
250ns
IVBA
IVBA Base address setting for interrupt vector table
0Interrupt vector base = X'04000'
Interrupt vector base = X'00100'
1
(at reset: 11001011)
Must be set to 11.
Must be set to 1.
Must be set to 0
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Chapter 2 Basic CPU Functions
31
Interrupts
PSW
New SP
(after interrupt is accepted)
70
PC8 to 1
PC16 to 9
PC18,17
HA7 to 0
HA15 to 8
PC0
Old SP
(before interrupt is accepted)
Low
Address
High
2-4 Interrupts
2-4-1 Accepting and Returning from Interrupts
In the MN101C00 series, when an interrupt is accepted, the hardware
pushes the program's return address and the PSW, on to the stack, and
branches to the beginning address of the interrupt program specified by the
interrupt vector table.
■Operation when Interrupt is Accepted
1. The stack pointer (SP) contents are update. (SP–6 →SP)
2. The handy address register (HA) is pushed on to the stack.
HA upper byte →(SP+5)
HA lower byte →(SP+4)
3. The program counter (PC = return address) contents are pushed on to the stack.
PC (bit 18
to
bit 17, bit 0) →(SP+3)
PC (bit 16
to
bit 9) →(SP+2)
PC (bit 8
to
bit 1) →(SP+1)
4. The PSW is pushed on to the stack.
PSW →(SP)
5. xxxLVn of the accepted interrupt is copied to IM of the PSW.
Interrupt level →IM
6. Execution branches to vector table.
Figure 2-4-1 Stack Status during an Interrupt
PSW
New SP
(after interrupt is accepted)
70
PC8 to 1
PC16 to 9
PC18,17
HA7 to 0
HA15 to 8
PC0
Old SP
(before interrupt is accepted)
Low
Address
High
Since the contents of data and address registers are not saved, use PUSH
instructions in the program to save these values as necessary on the
stack.
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Chapter 2 Basic CPU Functions
32 Interrupts
■Operation when Returning from Interrupt
After the program POPs the register and other values saved by the interrupt service
routine, an RTI instruction is implemented to return to the program that was being
executed when the interrupt was received.
The processing sequence for the return from interrupt instruction, RTI, is listed
below.
1. The processor status word (PSW) is pulled from the stack. (SP)
2. The program counter(PC = return address) is pulled from the stack. (SP+1
to
3)
3. The handy address register (HA) is pulled from the stack. (SP+4, 5)
4. The SP is pulled. (SP+6 →SP)
5. Execution branches to the address indicated by the PC.
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2-4-2 Interrupt Sources and Vector Addresses
In addition to reset, there are 20 interrupt vectors that indicate the starting
addresses of interrupt programs. These vectors are located in the 80-byte
ROM address area X'04004'
to
X'04053'.
Table 2-4-1 Interrupt Control Registers
Chapter 2 Basic CPU Functions
33
Interrupts
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Vector Number
Control Register
(address)
NMICR
IRQ0ICR
IRQ1ICR
TM2ICR
TBICR
SC0ICR
ADICR
IRQ2ICR
IRQ3ICR
TM3ICR
TM4ICR
TM5ICR
20
X'04000'
X'04004'
X'04008'
X'0400C'
X'04010'
X'04014'
X'04018'
X'0401C'
X'04020'
X'04024'
X'04028'
X'0402C'
X'04030'
X'04034'
X'04038'
X'0403C'
X'04040'
X'04044'
X'04048'
X'0404C'
Vector Address
X'04050'
Interrupt Source
Non-maskable interrupt (NMI)
External interrupt 0 (IRQ0)
External interrupt 1 (IRQ1)
Reserved
Reserved
Timer 2 compare-match (TM2IRQ)
Time base period (TBIRQ)
SC0 transfer complete (SC0IRQ)
Reserved
External interrupt 2 (IRQ2)
External interrupt 3 (IRQ3)*
Reserved
Timer 3 compare-match (TM3IRQ)
Timer 4 compare-match (TM4IRQ)
Timer 5 compare-match (TM5IRQ)
Reserved
Reserved
Reserved
Reserved
Reset
(X'03FE1')
(X'03FE2')
(X'03FE3')
(X'03FE4')
(X'03FE5')
(X'03FE6')
(X'03FE7')
(X'03FE8')
(X'03FE9')
(X'03FEA')
(X'03FEB')
(X'03FEC')
(X'03FED')
(X'03FEE')
(X'03FEF')
(X'03FF0')
(X'03FF1')
(X'03FF2')
(X'03FF3')
(X'03FF4')
A/D conversion complete (ADIRQ)
Set the vector addresses for reserved and unused interrupts to
an address containing an RTI instruction.
*
IRQ31CR cannot be used
except for 48-pin QFH
package.
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2-4-3 Interrupt Control Registers
Interrupt control registers consist of the following: a non-maskable interrupt control
register (NMICR), external interrupt control registers (IRQnICR), and internal
interrupt control registers (TMnICR, TBICR, SCnICR, ATCICR, ADICR).
■Non-maskable Interrupt Control Register (NMICR)
Non-maskable interrupt factors are stored in the non-maskable interrupt control
register (NMICR), and are used when a non-maskable interrupt is generated.
Figure 2-4-2 Non-maskable Interrupt Control Register (NMICR: X'03FE1', R/W)
■External Interrupt Control Registers (IRQnICR)
The external interrupt control registers (IRQnICR) control the interrupt level, valid
edge, and request/enable.
Figure 2-4-3 External Interrupt Control Register
(IRQnICR: X'03FE2' to X'03FE3', X'03FEB' to X'03FED', R/W)
Chapter 2 Basic CPU Functions
34 Interrupts
01245673
(at reset: ------0-)
NMICR
0
1No interrupt request
Watchdog interrupt request flag
Happens interrupt request
WDIR
WDIR
xxxLV1
Interrupt level flag for external interrupt
xxxLV0
01245673
(at reset: 000---00)
IRQnICR
0
1No interrupt request
External interrupt request flag
Happens interrupt request
xxxIE
xxxIR
0
1Disable interrupt
External interrupt enable flag
Enable interrupt
xxxIE
0
1 Rising edge
External interrupt valid edge flag
Falling edge
The CPU has interrupt levels from 0 to 3.
This flag sets the interrupt level for interrupt requests.
REDGn∗
xxxIRxxxLV1xxxLV0
REDGn
———
∗ n=0,1,2,3,4
By setting xxxLVn to '11' (level
3), the corresponding interrupt
vector will be disabled,
regardless of the state of the
interrupt enable and interrupt
request flags.
Be sure to use the MIE flag of
the PSW register to write to all
interrupt control registers.
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■Internal Interrupt Control Registers (TMnICR, TBICR, SCOICR, ATCICR, ADICR)
The internal interrupt control registers (TMnICR, TBICR, SCnICR, ATCICR,
ADICR) control the interrupt levels of internal interrupts, timer interrupts, serial
interrupts, A/D conversion complete interrupts, and interrupt request/enable.
Be sure to disable all interrupts before writing to these registors.
Figure 2-4-4 Internal Interrupt Control Registers (TMnICR, TBICR,
SC0ICR,ADICR: X'03FE6' to X'03FEA', X'03FEA' to X'03FF0', R/W)
Chapter 2 Basic CPU Functions
35
Interrupts
xxxLV1 Interrupt level flag
xxxLV0
01245673
(at reset: 00----00)
TMnICR, TBICR, SCnICR,
ATCICR, ADICR
0
1No interrupt request
Interrupt request flag
Happens interrupt request
xxxIE
xxxIR
0
1Disable interrupt
Interrupt enable flag
Enable interrupt
xxxIE
xxxIRxxxLV1xxxLV0 ––––
This 2-bit flag sets the interrupt level by
assigning an interrupt level of 0 to 3 to
interrupt requests.
By setting xxxLVn to '11' (level
3), the corresponding interrupt
vector will be disabled,
regardless of the state of the
interrupt enable and interrupt
request flags.
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Chapter 2 Basic CPU Functions
36 Reset
2-5 Reset
The CPU contents are reset and registers are initialized when the RST pin is
pulled to low.
■Initiating a Reset
There are two methods to initiate a reset.
(1) Drive the RST pin low for at least four clock cycles.
Figure 2-5-1 Minimum Reset Pulse Width
(2) Set bit 7 (P2OUT7 flags) of the P2OUT register to "0." After reset is released,
the P2OUT flag will be "1."
■Releasing the Reset
When the RST pin changes from low to high, an internal 15-bit counter begins
counting at the oscillation clock frequency. The interval from when this counter
begins counting until it overflows is known as the stabilization wait time. After
waiting for this amount of time, the internal reset is released and the CPU begins
operation.
Figure 2-5-2 Reset Release Sequence
RST pin
4 clock cycles
(200ns for a 20MHz oscillation)
For the reset to be stable, the
low pulse must be maintained
for at least four clock cycles.
However, it is important to
minimize noise, since a reset
may occur in a smaller number
of clock cycles.
Oscillation
stabilization wait time
2 /fosc
RST pin
Peripheral
register
CPU
internal reset
15
When returning from the STOP mode is terminating, the
software can use the DLYCTR register to select an
oscillation stabilization wait time of 0, 27/fosc, 211/fosc, or
215/fosc.
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Chapter 3 Port Functions
38 Overview
3-1 Overview
A total of 39 pins on the MN101C117, including those shared with special
function pins, are allocated for the 7 ports of P0 to P2, P6 to P8, and PA.
Each I/O port is assigned according to the special function register area in
memory. I/O ports are operated in byte or bit units in the same way as RAM.
• This I/O control is valid even when special functions are selected for the dual function pins.
•
Table 3-1-1 Status When Port Is Reset (single-chip mode)
For each I/O port, the PnOUT register (port n output
register) that sets the output value is assigned to memory
address X'3F1n', and the PnIN register (port n input
register) from which the input value is monitored is
assigned to memory address X'3F2n'.
Port I/O Mode Pull-up/Pull-down Resistor I/O Port or Special Function
Port 0
Port 1
Port 2
Port 6
Port 7
Port 8
Port A
Input mode
Input mode
Input mode
Input mode
Input mode
Input mode
Input mode
No pull-up resistor
No pull-up resistor
No pull-up resistor
No pull-up resistor
No pull-up/pull-down resistors
No pull-up/pull-down resistors
No pull-up/pull-down resistors
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
■Port 0 (P0)
4-bit CMOS tri-state I/O port.
Table 3-1-2 Port 0 Functions
P00 to P02 I/O SBO0(TXD),
P06 SBI0(RXD),
SBT0
BUZZER
Each bit can be set individually as either an input or
output by the P0DIR register. A pull-up resistor for each
bit can be selected individually by the P0PLU register.
At reset, the input mode is selected and pull-up resistors
are disabled (high impedance output).
Pin Name Type Dual Function Description
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Chapter 3 Port Functions
39
Overview
■Port 1 (P1)
5-bit CMOS tri-state I/O port.
Table 3-1-3 Port 1 Functions
■Port 2 (P2)
4-bit CMOS tri-state input port.
Table 3-1-4 Port 2 Functions
■Port 6 (P6)
8-bit CMOS tri-state I/O port.
Table 3-1-5 Port 6 Functions
P10 to P14 I/O RMOUT,
TM2IO to
TM4IO Each bit can be set individually as either an input or
output by the P1DIR register. A pull-up resistor for each
bit can be selected individually by the P1PLU register.
At reset, the input mode is selected and pull-up resistors
are disabled (high impedance output).
Pin Name Type Dual Function Description
Pin Name Type Dual Function Description
P20 to P23
Input IRQ0,
IRQ1(SENS),
IRQ2 to 3
A pull-up resistor for each bit can be selected individually
by the P2PLU register. At reset, the input mode pull-up
resisters are disabled (high impedance output).
Only 48-QFH has P23.
Pin Name Type Dual Function Description
Each bit can be set individually as either an input or
output by the P6DIR register. A pull-up resistor for each
bit can be selected individually by the P6PLU register. At
reset, the input mode pull-up resisters are disabled (high
impedance output).
P60 to P67 I/O
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■Port 7 (P7)
8-bit CMOS tri-state I/O port.
Table 3-1-6 Port 7 Functions
■Port 8 (P8)
8-bit CMOS tri-state I/O port.
Table 3-1-7 Port 8 Functions
■Port A (PA)
8-bit CMOS tri-state input port.
Table 3-1-8 Port A Functions
Pin Name Type Dual Function Description
P70 to P71 I/O
Each individual bit can be switched to an input or output
by the P7DIR register. A pull-up or pull-down resistor for
each bit can be selected individually by the P7PLU
register.
However, pull-up and pull-down resistors cannot be
mixed. At reset, the input mode pull-up resisters are
disabled
. 42-SDIP has no pins of P70,P71. 44-QFP has no pin of
p71.
Pin Name Type Dual Function Description
P80 to P87 I/O LED0 to 7 Each individual bit can be switched to an input or output
by the P8DIR register. A pull-up resistor for each bit can
be selected individually by the P8PLU register. When
configured as outputs, it is possible to LED.
At reset, when single chip mode is selected, the input
mode pull-up resisters for P80 to P87 are disabled (high
impedance output).
Pin Name Type Dual Function Description
PA0 to PA7 Input
AN0 to AN7
A pull-up or pull-down resistor for each bit can be
selected individually by the PAPLUD register. However,
pull-up and pull-down resistors cannot be mixed.
At reset, the input mode pull-up resisters for PA0 to PA7
are disabled.
Chapter 3 Port Functions
40 Overview
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Chapter 3 Port Functions
41
Port Control Registers
3-2 Port Control Registers
3-2-1 Overview
28 registers control the I/O ports. See table 3-2-1.
Table 3-2-1 I/O Port Control Registers (1/2)
Name Address R/W Function
P0OUT
P1OUT
P2OUT
P6OUT
P7OUT
P8OUT
P0IN
P1IN
P2IN
P6IN
P7IN
P8IN
PAIN
P0DIR
P1DIR
X'03F10'
X'03F11'
X'03F12'
X'03F16'
X'03F17'
X'03F18'
X'03F20'
X'03F21'
X'03F22'
X'03F26'
X'03F27'
X'03F28'
X'03F2A'
X'03F30'
X'03F31'
Port 0 output register
Port 1 output register
Port 2 output register
Port 6 output register
Port 7 output register
Port 8 output register
Port 0 input register
Port 1 input register
Port 2 input register
Port 6 input register
Port 7 input register
Port 8 input register
Port A input register
Port 0 direction control register
Port 1 direction control register
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R/W
R/W
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Table 3-2-1 I/O Port Control Registers (2/2)
Chapter 3 Port Functions
42 Port Control Registers
Name Address R/W Function
P6DIR
P7DIR
P8DIR
P1OMD
PAIMD
P0PLU
P1PLU
P2PLU
P6PLU
P7PLUD
P8PLU
PAPLUD
FLOAT1
X'03F36'
X'03F37'
X'03F38'
X'03F39'
X'03F3A'
X'03F40'
X'03F41'
X'03F42'
X'03F46'
X'03F47'
X'03F48'
X'03F4A'
X'03F4B'
Port 6 direction control register
Port 7 direction control register
Port 8 direction control register
Port 1 output mode register
Port A input mode register
Port 0 pull-up control register
Port 1 pull-up control register
Port 2 pull-up control register
Port 6 pull-up control register
Port 7 pull-up/pull-down control register
Port 8 pull-up control register
Port A pull-up/pull-down control register
Pin control register 1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Chapter 3 Port Functions
43
Port Control Registers
Figure 3-2-1 Port Control Registers (1/2)
01245673
P0OUT (at reset: -0---000)
P1OUT (at reset: ---00000)
P0IN (at reset: -X---XXX)
P1IN (at reset: ---XXXXX)
P2IN (at reset: ----XXX)
P0DIR (at reset: -0---000)
P1DIR (at reset: ---00000)
P1OMD (at reset: ---00000)
P0PLU (at reset: -0---000)
P1PLU (at reset: ---00000)
P2PLU (at reset: -----000)
P0OUT6 P0OUT2 P0OUT1 P0OUT0
P1OUT4 P1OUT3 P1OUT2 P1OUT1 P1OUT0
P2OUT (at reset: 1-------)
P2OUT7
P0IN6 P0IN2 P0IN1 P0IN0
P2IN2 P2IN1 P2IN0
P1IN4 P1IN3 P1IN2 P1IN1 P1IN0
P0DIR6 P0DIR2 P0DIR1 P0DIR0
P0PLU6 P0PLU2 P0PLU1 P0PLU0
P1PLU4 P1PLU3 P1PLU2 P1PLU1 P1PLU0
P1DIR4 P1DIR3 P1DIR2 P1DIR1 P1DIR0
P14TCO P13TCO P12TCO P10TCO
P2PLU2 P2PLU1 P2PLU0
P6OUT (at reset: 00000000)
P6IN (at reset: XXXXXXXX)
P6DIR (at reset: 00000000)
P6OUT6P6OUT7 P6OUT5 P6OUT4 P6OUT3 P6OUT2 P6OUT1 P6OUT0
P6IN6P6IN7 P6IN5 P6IN4 P6IN3 P6IN2 P6IN1 P6IN0
P6DIR6P6DIR7 P6DIR5 P6DIR4 P6DIR3 P6DIR2 P6DIR1 P6DIR0
P6PLU (at reset: 00000000)
P6PLU7 P6PLU6 P6PLU5 P6PLU4 P6PLU3 P6PLU2 P6PLU1 P6PLU0
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Figure 3-2-1 Port Control Registers (2/2)
Chapter 3 Port Functions
44 Port Control Registers
01245673
P7OUT (at reset: - - - - - - 00)
P8OUT (at reset: 00000000)
P7IN (at reset: - - - - - - XX)
P8IN (at reset: XXXXXXXX)
PAIN (at reset: XXXXXXXX)
P7DIR (at reset: - - - - - - 00)
P8DIR (at reset: 00000000)
PAIMD (at reset: 00000000)
P7PLUD (at reset: - - - - - - 00)
P8PLU (at reset: 00000000)
PAPLUD (at reset: 00000000)
P7OUT1 P7OUT0
P8OUT6P8OUT7 P8OUT5 P8OUT4 P8OUT3 P8OUT2 P8OUT1 P8OUT0
P7DIR1 P7DIR0
P8DIR6P8DIR7 P8DIR5 P8DIR4 P8DIR3 P8DIR2 P8DIR1 P8DIR0
PAAIN6PAAIN7 PAAIN5 PAAIN4 PAAIN3 PAAIN2 PAAIN1 PAAIN0
P8IN6P8IN7 P8IN5 P8IN4 P8IN3 P8IN2 P8IN1 P8IN0
P7IN1 P7IN0
PAIN6PAIN7 PAIN5 PAIN4 PAIN3 PAIN2 PAIN1 PAIN0
P7PLUD0
PAPLUD6PAPLUD7 PAPLUD5 PAPLUD4 PAPLUD3 PAPLUD2 PAPLUD1 PAPLUD0
P8PLU6P8PLU7 P8PLU5 P8PLU4 P8PLU3 P8PLU2 P8PLU1 P8PLU0
P7PLUD1
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Chapter 3 Port Functions
45
Port Control Registers
3-2-2 I/O Port Control Registers
This section describes the special function registers that control the
MN101C117's I/O ports.
■Data Registers
• PnOUT registers
Data registers to output to the ports.
Data written to these registers is output from the ports.
• PnIN registers
Data registers to input data from the ports.
The value of data at the pins can be input by reading these registers.
These are read-only registers.
Input and output registers are mapped to separate addresses.
To use these ports for I/O, configure them as I/O ports in the PnOMD/PnIMD registers,
described in this section.
■Direction Control Registers
• PnDIR registers
These registers set the port for use as an input or output.
■Pull-up/Pull-down Resistor Control Registers
• PnPLU registers
These register settings determine whether internal pull-up resistors are added to the ports.
• PnPLUD registers
These register settings determine whether internal pull-up or pull-down resistors are
added to the ports.
0
1
Low (Vss level) is output.
High (Vdd level) is output.
0
1
Pin is low.
Pin is high.
0
1
Input mode
Output mode
0
1
No pull-up / pull-down resistor
Pull-up / Pull down resistor
0
1
No pull-up / pull-down resistor
Pull-up / Pull down resistor
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Chapter 3 Port Functions
46 Port Control Registers
■Port Output/Input Mode Registers
• PnOMD/PnIMD registers
These register settings determine whether the port pins(P10 to P14, PA0 to PA5) are used
as I/O ports or as special function pins (dual function).
If the special (dual) functions used, the PnDIR, PnPLU, PnPLUD, and other registers
must be set.
■Pin Control Registers
• FLOAT1 registers
This register specifies whether the resistors-attached to pins P7 and PA are pull-up
resistors or pull-down resistors.
In addition, this register selects either zero cross input or Schmitt trigger input for pin
P21.
Figure 3-2-2 Pin Control Register 1(FLOAT1: X'03F4B',R/W)
0
1
I/O port
Special function pin
Setting the PAIMD register
prevents unnecessary current
from flowing in a pin when an
intermediate voltage (analog
voltage) is applied to the pin.
0
1Schmitt trigger input
P21 input mode selection
SENS input
P21IM
0
1pull-up resistor
PA pull-up/pull-down
resistor selection
pull-down resistor
PARDWN
01245673
(at reset: -----000)
FLOAT1
P7RDWNPARDWNP21IM
0
1pull-up resistor
P7 pull-up/pull-down
resistor selection
pull-down resistor
P7RDWN
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Chapter 3 Port Functions
47
I/O Port Configuration and Functions
3-3 I/O Port Configuration and Functions
■P00,P02,P10 to P14
R
D
L
Q
Reset
Write Read
Read
R
D
L
Q
Reset
Write Read
R
D
L
Q
Reset
Write Read
Pull-up resistor control
I/O direction control
Port output data
Special function input data
Port input data
Data bus
Schmidt trigger input
Special function output control
Special function output data
SBO0(TXD)
P0PLU0
P00 P0PLU2
P02
P0PLU
(X'03F40')
P0DIR
(X'03F30')
P0OUT
(X'03F10')
P0IN
(X'03F20')
SC0MD3
(X'03F53')
SC0MD3
(X'03F53')
P0DIR0 P0DIR2
P0OUT0 P0OUT2
P0IN0 P0IN2
SC0SBOM
SBO0/TXD
SC0CMD
SC0CTR
(X'03F54')
SC0SBTM
SBT0
SC0SBOS SC0SBTS
P1PLU0 P1PLU
(X'03F41')
P1DIR
(X'03F31')
P1OUT
(X'03F11')
P1IN
(X'03F21')
P1OMD
(X'03F39')
P1PLU1 P1PLU3 P1PLU4
P1DIR0 P1DIR1 P1DIR3 P1DIR4
P1OUT0 P1OUT1 P1OUT3 P1OUT4
P1IN0 P1IN1 P1IN3 P1IN4
RMOUT
TM3I TM4I
P13TCO P14TCO
P1PLU2
P1DIR2
P1OUT2
P1IN2
TM2I
P12TCO
P10 P11 P12 P13 P14
RMOEN
RMCTR
(X'3F89)
∗ Both The TM0RM flag of the RMCTR register and the P10TCO flag of the P10MD register
are used to switch between remote control output and timer output.
Pull-up
resistor
control
I/O
direction
control
Port
output
Port
input
Output
format
control
Special
function
output
control (1)
Control bit
Register
(address)
Control bit
Register
(address)
Control bit
Register
(address)
Control bit
Register
(address)
Control bit
Register
(address)
Control bit
Special
function
Special
function
Register
(address)
Special
function
output
control (2) Control bit
Special function
Register
(address)
Special function input SBT0
RMOUT
P10TCO
TM2O TM3O TM4O
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Chapter 3 Port Functions
48 I/O Port Configuration and Functions
■P01
Figure 3-3-2 Configuration and Functions of P01
R
D
L
Q
Write Read
Read
R
D
L
Q
Reset
Write Read
R
D
L
Q
Reset
Write Read
Pull-up resistor control
I/O direction control
Port output data
Special function input data
Port input data
Data bus
Reset
Schmitt trigger input
P0PLU1
P0PLU
(X'03F40')
P0DIR
(X'03F30')
P0OUT
(X'03F10')
P0IN
(X'03F20')
P0DIR1
P0OUT1
P0IN1
SBI0/RXD
P01
Special function input
Pull-up
resistor
control
I/O direction
control
Port output
Port input
Control bit
Register
(address)
Control bit
Register
(address)
Control bit
Register
(address)
Control bit
Register
(address)
Special function
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Chapter 3 Port Functions
49
■PA0 to PA7
Figure 3-3-3 Configuration and Functions of PA0 to PA7
R
D
L
Q
Reset
Write Read
R
D
L
Q
Reset
Write Read
Read
R
D
L
Q
Reset
Write Read
Pull-up/pull-down resistor control
Pull-up/pull-down resistor selection
Input mode control
Analog input
Port input data
Data bus
Data bus
PAPLUD0
PAPLUD
(X'03F4A')
FLOAT1
(X'03F4B')
PAIMD
(X'03F3A')
PAIN
(X'03F2A')
PAAIN0 PAAIN1 PAAIN2 PAAIN3
PARDWN
PAAIN4 PAAIN5 PAAIN6 PAAIN7
PAIN0 PAIN1 PAIN2 PAIN3 PAIN4 PAIN5 PAIN6 PAIN7
PAPLUD1 PAPLUD2 PAPLUD3 PAPLUD4 PAPLUD5 PAPLUD6 PAPLUD7
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
Pull-up
resistor
control
Pull-up/
pull-down
resistor
control
Input mode
control
Port input
Control bit
Register
(address)
Control bit
Register
(address)
Control bit
Register
(address)
Control bit
Register
(address)
Special function
Special function
input
I/O Port Configuration and Functions
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Chapter 3 Port Functions
50 I/O Port Configuration and Functions
■Pin Configuration for P20, P22 to P23
Figure 3-3-4 Configuration and Functions of P20, P22, P23
R
D
L
Q
Reset
Write Read
Read
Schmitt trigger input
Pull-up resistor control
Port input data
Special function input data
Data bus
P2PLU0 P2PLU2
P2IN0 P2IN2
P2PLU
(X'03F42')
P2IN
(X'03F22')
IRQ0 IRQ2
Pull-up
resistor
control
Port input
Special function
input
Control bit
Register
(address)
Control bit
Register
(address)
Interrupt input
P20 P22 P23
P2PLU3
P2IN3
IRQ3
*
P23 is only for
48-pin package.
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Chapter 3 Port Functions
51
■P21
Figure 3-3-5 Configuration and Functions of P21
Data bus
R
D
L
Q
Reset
Read Read
Read
Schmitt trigger input
R
D
L
Q
Reset
Read Read
Pull-up resistor control
Port input data
Special function input data
Special function input data
AC zero-cross detection circuit
P2PLU1
P2IN1
P21IM
P2PLU
(x'03F42')
P2IN
(x'03F22')
FLOAT1
(x'03F4B')
SENS
Pull-up
resistor
control
Port input
Control bit
Register
(address)
Control bit
Register
(address)
Register
(address)
Special
function
input
selection
Special function
Control bit
P21
I/O Port Configuration and Functions
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Chapter 3 Port Functions
52 I/O Port Configuration and Functions
■P27
Figure 3-3-6 Configuration and Functions of P27
Schmitt trigger input
S
D
L
Q
Reset
Write
Port output data
Reset signal input
Data bus
RST
P2OUT7
P2OUT
(x'03F12')
Soft reset output
Special input
Register
(address)
Special
function
output
Special function
Control bit
P27
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Chapter 3 Port Functions
53
■P70 to P71
Figure 3-3-7 Configuration and Functions of P70
Read
R
D
L
Q
Reset
Write Read
R
D
L
Q
Reset
Write Read
R
D
L
Q
Reset
Write Read
Read
R
D
L
Q
Reset
Write
Pull-up/pull-down resistor control
Pull-up/pull-down resistor selection
I/O direction control
Port output data
Port input data
Data bus
I/O Port Configuration and Functions
P7PLUD0
P7PLUD
(X'03F47')
FLOAT1
(X'03F4B')
P7DIR
(X'03F37')
P7IN
(X'03F27')
P7DIR0
P7RDWN
P7IN0
P7OUT
(X'03F17')
P7OUT0
P70
Pull-up/
pull-down
resistor control
Pull-up/
pull-down
resistor control
I/O direction
control
Port input
Control bit
Register
(address)
Control bit
Register
(address)
Control bit
Register
(address)
Control bit
Register
(address)
Port output
Control bit
Register
(address)
P71
P7PLUD1
P7DIR1
P7IN1
P7OUT1
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Chapter 3 Port Functions
54 I/O Port Configuration and Functions
■P60 to P67,P80 to P87
Figure 3-3-8 Configuration and Functions of P60 to P67
Figure 3-3-9 Configuration and Functions of P80 to P87
R
D
L
Q
Reset
Write Read
Read
R
D
L
Q
Reset
Write Read
R
D
L
Q
Reset
Write Read
Pull-up resistor control
I/O direction control
Port output data
Port input data
Data bus
Schmidt trigger input
P6PLU0 P6PLU1 P6PLU2 P6PLU3 P6PLU4
P6OUT0 P6OUT1 P6OUT2 P6OUT3 P6OUT4
P6DIR0 P6DIR1 P6DIR2 P6DIR3 P6DIR4
P6IN0 P6IN1 P6IN2 P6IN3 P6IN4
P60 P61 P62 P63 P64
Pull-up
resistor
control
I/O
direction
control
Port input
Port output
Control bit
Register
(address)
Control bit
Register
(address)
Control bit
Register
(address)
Control bit
Register
(address)
P6PLU5 P6PLU6 P6PLU7
P6PLU
(x'03F46')
P6DIR
(x'03F36')
P6OUT
(x'03F16')
P6IN
(x'03F26')
P6OUT5 P6OUT6 P6OUT7
P6DIR5 P6DIR6 P6DIR7
P6IN5 P6IN6 P6IN7
P65 P66 P67
P8PLU0 P8PLU1 P8PLU2 P8PLU3 P8PLU4
P8OUT0 P8OUT1 P8OUT2 P8OUT3 P8OUT4
P8DIR0 P8DIR1 P8DIR2 P8DIR3 P8DIR4
P8IN0 P8IN1 P8IN2 P8IN3 P8IN4
P80 P81 P82 P83 P84
Pull-up
resistor
control
I/O
direction
control
Port input
Port output
Control bit
Register
(address)
Control bit
Register
(address)
Control bit
Register
(address)
Control bit
Register
(address)
P8PLU5 P8PLU6 P8PLU7
P8PLU
(x'03F48')
P8DIR
(x'03F38')
P8OUT
(x'03F18')
P8IN
(x'03F28')
P8OUT5 P8OUT6 P8OUT7
P8DIR5 P8DIR6 P8DIR7
P8IN5 P8IN6 P8IN7
P85 P86 P87
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Chapter 4 Timer Functions
56 Overview
4-1 Overview
The MN101C117 contains three 8-bit timers, one 16-bit timer, a watchdog
timer, a time base timer, and circuits for remote control output and buzzer
output.
Table 4-1-1 Summary of Timer Functions
Timer 2
(8-bit) Timer 3
(8-bit) Timer 4
(16-bit) Timer 5
(8-bit) Time Base
Interrupt TM2IRQ TM3IRQ TM4IRQ TM5IRQ TBIRQ
0
1
2
3
fs
fs/4
fx
TM2IO input
fosc
fs/4
fs/16
TM3IO input
fosc
fs/4
fs/16
TM4IO input
fosc
fs/4
fx
fosc,fx/213
fosc
fx
Remote
control
carrier pulse
generation
Pulse
added
type
PWM
××
××
××××
×××
×××
×× ××
Not
possible to
temporarily
halt BC
Event counter
Timer pulse output
Serial
transmission clock
PWM output
Cascade
connection
Capture function
Other
Clock
source
Timer operation
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Chapter 4 Timer Functions
57
Overview
fs
fs/4
fx
TM2IO
input
MUX
MUX MUX
MUX
Synchro-
nization
MUX
MUX
MUX
MUX
MUX
MUX
Synchro-
nization
MUX
fosc
f s/4
f s/16
TM3IO input
TM2OC
TM3CK0
TM3CK1
TM3CK2
TM2CK0
TM2CK1
TM2CK2
TM2PWM
TM2EN
TM3PWM
TM3EN TM3OC
TM3MD
TM2MD
TM3IRQ
TM3IO output/
PWM2/
Remote control
carrier output/
Serial transfer
clock output
TM2IRQ
TM2IO output/PWM2
RST input
TM2BC TM3BC
1/2
1/2
Read/Write
Read
Read/Write
Read
R R
RQ
S
Compare register
8-bit counter
Compare register
8-bit counter
Match Match
0
7
0
7
–
–
–
–
–
–
Figure 4-1-1 Timers 2, 3 Block Diagram
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Chapter 4 Timer Functions
58 Overview
Figure 4-1-2 Timer 4 Block Diagram
fosc
fs/4
fs/16
TM4IO
input
MUX
MUX
Synchro-
nization
Synchro-
nization
MUX
MUX
MUX
MUX
IRQ0
IRQ1
IRQ2
TM4OCL
TM4CK0
T4ICT0
TM4CK2
T4ICT1
TM4EN
TM4PWM
TM4CK1
RSTIO
TM4MD
1/2
Read/Write Read/Write
TM4PWM
Read Read
Read Read
R
RR SQ
TM4OCH
Pulse-added timing
generation
Pulse added
TM4IRQ
TCIO4Ioutput/
PWM output
Match
Match
TM4BCL TM4BCH
TM4ICL TM4ICH
Overflow of lower 8 bits
16-bit compare register
16-bit counter
16-bit capture register
–
0
7
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Chapter 4 Timer Functions
59
Overview
Figure 4-1-3 Timer 5/Time Base Block Diagram
MUX
MUX
MUX MUX
MUX MUX
MUX
f osc
f s/4
f osc
f x
250ms (32kHz) 0.977ms (8MHz)
1min (32kHz),250ms (8.38MHz)
3.9ms, 7.8ms, 15.6ms, 31.2ms (32kHz)
1/2
f x
TM5CK0
TM5MD
TM5CK1
TM5CK2
TM5CK3
TM5IR0
TM5IR1
TM5IR2
TM5CLRS
1/2
TM5IRQ
TBIRQ
TM5BC
Read/Write
Read
8-bit counter
TM5OC
Compare register
Match
13
10
1/29
1/28
1/27
R
Synchro-
nization
0
7
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Chapter 4 Timer Functions
60 Overview
Figure 4-1-4 Watchdog Timer, Buzzer Block Diagram
1/2
1/4
WDCTR
DLYCTR
MUX
MUX
14
12
1/2
11
1/2
10
1/2
9
1/2
fs
1/2
1/2
R
S
R
R
1/4 1/4
DLYS0
WDEN
–
–
–
–
–
–
–
0
7
DLYS1
BUZS0
–
0
7
–
–
BUZS1
BUZOE
10
1/2
fosc
fosc
fosc
6
14
Internal reset release
WDIRQ
Buzzer
Overflow
ROM option
Overflow
Reset input
Refer to the aragraph
[1-6-1 ROM option]
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Chapter 4 Timer Functions
61
Overview
Figure 4-1-5 Remote Control Transmission Block Diagram
Synchronization
circuit
MUX
RMCTR
Remote control output
1/3
duty
1/2
duty
RMDTY0
–
RMOEN
–
–
–
–
–
0
7
Timer 3 output
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Chapter 4 Timer Functions
62
4-2 8-bit Timer Operation (timers 2, 3)
4-2-1 Overview
Functions for timers 2 and 3 are listed below.
Table 4-2-1 Summary of 8-bit Timer Functions
Timer 2
(8-bit) Timer 3
(8-bit)
TM2IRQ TM3IRQ
Remote control
carrier pulse
generation
×
×
×
Interrupt
Event counter
Timer pulse output
Serial
transmission clock
PWM output
Cascade
connection
Timer operation
(SIF0)
8-bit Timer Operation (timers 2, 3)
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Chapter 4 Timer Functions
63
8-bit Timer Operation (timers 2, 3)
4-2-2 Operation
■Timer Operation (timers 2, 3)
Settings for timer operation are listed below. Timer 2 is used as an example.
(1) Set the TM2EN flag of the timer 2 mode register (TM2MD) to "0" to stop the count
operation of timer 2.
(2) Set the TM2CK2
W&f
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0 flags of the TM2MD register to select fs, fs/4, fx, or
synchronized fx as the clock source.
(3) Set the TM2PWM flag of the TM2MD register to "0" so that normal timer operation
is selected.
(4) Set a value in compare register 2 (TM2OC).
(5) Set the TM2EN flag of the TM2MD register to "1" to start the timer.
(6) When timer 2 begins operation, binary counter 2 (TM2BC) will count upward from
X'00'.
(7) When the value of binary counter 2 matches that of the TM2OC register, the timer 2
interrupt request flag is set, and the binary counter 2 is reset to X'00' and begins to
count upward again.
Figure 4-2-1 Binary Counter 2 (TM2BC) Count Timing
When servicing an interrupt, reset
the timer 2 interrupt request flag
before starting timer 2.
During a count operation, be
careful if the value set in TM2OC
is smaller than the value of binary
counter 2, since the count-up
operation will continue until
overflow occurs.
If fx is to be selected as the clock
source and the value of binary
counter 2 is to be read during
operation, select synchronized fx
in order to avoid reading data that
may be incomplete during count-
up transitions. However, with
synchronized fx, it is not possible
to return from STOP/HALT modes.
Clock
TM4EN
Binary
counter 4
Write to registers
TM4OCH, TM4OCL
0504 06 07 08 09 00
If the TM2EN flag of TM2MD register is changed simultaneously with
other bits, the switching operation may cause binary counter 2 to be
incremented.
If the value of TM2OC register is overwritten while timer 2 has
stopped counting, binary counter 2 will be reset to X'00' at the edge
of next count clock.
The value of TM3CK0~2 of T3MD register is unsettled. If timer2/
timer 3 is independently used, any mode except cascade
connection should be set.
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Chapter 4 Timer Functions
64 8-bit Timer Operation (timers 2, 3)
If TM2IO input is selected as the
clock source and the value of
binary counter 2 is to be read
during operation, select
synchronized TM2IO input to avoid
reading data that may be
incomplete during count-up
transitions. However, with
synchronized TM2IO input, it is not
possible to return from
STOP/HALT modes.
■Event Count Function (timers 2, 3)
Settings for the event count function are listed below. Timer 2 is used as an example.
(1) Set the TM2EN flag of the timer 2 mode register (TM2MD) to "0" to stop the count
operation of timer 2.
(2) Use the TM2CK2 to 0 flags of the TM2MD register to select TM2IO input or
synchronous TM2IO input as the clock source.
(3) Set the TM2PWM flag of the TM2MD register to "0" so that normal timer operation is
selected.
(4) Set a value in compare register 2 (TM2OC).
(5) Set the TM2EN flag of the TM2MD register to "1" to start the timer.
(6) When timer 2 begins operation, binary counter 2 will count upward from X'00'.
(7) When the value of binary counter 2 matches that of the TM2OC register, the timer 2
interrupt request flag is set, and the binary counter 2 is reset to X'00' and begins to count
upward again.
When synchronized TM2IO is selected, the timer 2 clock source is synchronized with the system
clock after a transition of the TM2IO input signal. Binary counter 2 counts upward based on a
signal synchronized to the system clock. Therefore, correct values can be read from binary counter
2.
Figure 4-2-2 Timer 2 Event Counter Timing
(when synchronous TM2IO input is selected)
CPU system clock
(fs)
TM4IO input
Synchronous
circuit output
Binary counter n n+1
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Chapter 4 Timer Functions
65
The period of a signal output to the
port is 1/2 of the period set in the
TM2OC register.
If port 1 is to be used as a pulse
output pin, it is necessary to set
the port 1 output direction control
register (P1DIR) and the port 1
pull-up/pull-down resistor control
register (P1PLU).
■Timer Pulse Output Function (timers 2, 3)
Settings for the timer pulse output function are listed below. Timer 2 is used as an
example.
(1) Set the TM2EN flag of the timer 2 mode register (TM2MD) to "0" to stop the count
operation of timer 2.
(2) Set bit 2 of the port 1 output/input mode register (P1OMD) to "1" to set the special
function pin. Bit 2 of port 1 will be specified as the pulse output pin.
(3) Set the TM2CK2 to 0 flags of the TM2MD register to select fs, fs/4, fx, or
synchronized fx as the clock source.
(4) Set the TM2PWM flag of the TM2MD register to "0" so that normal timer operation
is selected.
(5) Set a value in compare register 2 (TM2OC).
(6) Set the TM2EN flag of the TM2MD register to "1" to start the timer.
(7) When timer 2 begins operation, binary counter 2 will count upward from X'00'.
(8) When the value of binary counter 2 matches that of the TM2OC register, the timer 2
interrupt request flag is set, and the binary counter 2 is reset to X'00' and begins to
count upward again.
Figure 4-2-3 Timer Pulse Output Timing
Binary counter
Matches compare register
TM2OUT
8-bit Timer Operation (timers 2, 3)
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Chapter 4 Timer Functions
66
If the TM3PWM flag of the TM3MD
register is set to "1" and timer 2
PWM output is selected, the PWM
output of timer 2 will also be output
from the TM3IO pin.
If port 1 is to be used as a PWM
output pin, the P1DIR and P1PLU
registers must be set.
■PWM Output Function (Timer 2)
Settings for the PWM output function are listed below.
(1) Set the TM2EN flag of the timer 2 mode register (TM2MD) to "0" to stop the count
operation of timer 2.
(2) Set bit 2 of the port 1 output/input mode register (P1OMD) to the special function
pin setting. Bit 2 of port 1 will be specified as the PWM output pin.
(3) Set the TM2CK2 to 0 flags of the TM2MD register to select fs, fs/4, fx, or
synchronous fx as the clock source. The period of the output waveform is determined
based on the clock source.
(4) Set the TM2PWM flag of the TM2MD register to "1" so that PWM operation is
selected.
(5) Set a value in compare register 2 (TM2OC). The high interval of the output
waveform is determined based on the value of the TM2OC compare register.
(6) Set the TM2EN flag of the TM2MD register to "1" to start the timer.
(7) When timer 2 begins operation, binary counter 2 will count upward from X'00'.
(8) A high-level signal is output from the port beginning when binary counter 2 starts
counting at X'00' and ending when the value of binary counter 2 matches the value
set in the TM2OC register.
(9) When the value of binary counter 2 matches that of the TM2OC register, a low-level
signal is output from the port.
(10) Binary counter 2 continues to count upward until X'FF' is reached. At the next count-
up cycle, the value of binary counter 2 is reset to X'00', a high-level signal is output
from the port, and counting begins again.
Figure 4-2-4 PWM Output Timing
Binary
counter 2
Overflow
Matches TM2OC
register
PWM output
Time specified by TM2OC register
Time until binary counter 2 reaches X'FF'
8-bit Timer Operation (timers 2, 3)
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Figure 4-2-5 PWM Output Timing (when TM2OC register is X'00')
Figure 4-2-6 PWM Output Timing (when TM2OC register is X'FF')
Chapter 4 Timer Functions
67
8-bit Timer Operation (timers 2, 3)
Clock
PWM output
Binary
counter 2
PWM output
Matches TM2OC register
Overflow
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Chapter 4 Timer Functions
68
The clock source for the serial
interface has a frequency that is
1/2 of the overflow output of timer
3.
For serial interface settings, refer
to the chapter on serial functions.
Disable the timer 2 interrupt.
■ Serial Transfer Clock Function(timer 3)
Settings for the serial transfer clock function are listed below.
(1) Set the TM3EN flag of the timer 3 mode register (TM3MD) to "0" to stop the count
operation of timer 3.
(2) Set the SC0CK1 and SC0CK0 flags of the serial interface 0 mode register 1
(SC0MD1) to select 1/2 of the timer 3 overflow frequency as the clock source.
(3) Set the TM3CK2 to 0 flags of the TM3MD register to select fosc, fs, fs/4, or fs/16 as
the clock source.
(4) Set the TM3PWM flag of the TM3MD register to "0" to select timer 3 output.
(5) Set a value in compare register 3 (TM3OC).
(6) Set the TM3EN flag of the TM3MD register to "1" to start the timer.
(7) When timer 3 begins operation, binary counter 3 counts upward from X'00'.
(8) When the value of binary counter 3 matches that of the TM3OC register, the timer 3
interrupt request flag is set, the value of binary counter 3 is reset to X'00', and
counting begins again.
■Cascade Connection Function (timer 2 + timer 3)
Settings for the cascade connection function are listed below. Timer 2 and timer 3
are connected to operate as a 16-bit timer.
(1) Set the TM2EN flag of the timer 2 mode register (TM2MD) to "0" to stop the count
operation of timer 2.
(2) Set the TM3EN flag of the timer 3 mode register (TM3MD) to "0" to stop the count
operation of timer 3.
(3) Set the TM2CK2 to 0 flags of the TM2MD register to select fs, fs/4, fx, or
synchronized fx as the clock source.
(4) Use the TM3CK2 to 0 flags of the TM3MD register to set the clock source as a
cascade connection with timer 2.
(5) Set the TM2PWM flag of the TM2MD register to "0" to select normal timer
operation.
(6) Set values in compare register 2 (TM2OC) and compare register 3 (TM3OC).
(7) Set the TM2EN flag of the TM2MD register to "1" to start the timer.
(8) Set the TM3EN flag of the TM3MD register to "1" to start the timer.
(9) When timers 2 and 3 begin operation, the binary counters begin counting upward
from X'0000' as a 16-bit counter.
(10) When the value of the 16-bit binary counter matches that of the 16-bit register
(TM3OC+TM2OC), the timer 3 interrupt request flag is set, the value of the 16-bit
binary counter is reset to X'0000', and counting begins again.
Use a 16-bit access instruction to set the (TM3OC+TM2OC) register.
8-bit Timer Operation (timers 2, 3)
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Chapter 4 Timer Functions
69
16-bit Timer Operation (timer 4)
4-3 16-bit Timer Operation (timer 4)
4-3-1 Overview
Timer 4 is a 16-bit programmable counter that can be used as an event counter.
A signal with a frequency of 1/2 of the timer 4 overflow signal can be output from the
TM4IO pin. An input capture function and pulse added type PWM output function can
also be used.
4-3-2 Operation
■Timer Operation
Settings for timer operation are listed below.
(1) Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" to stop the count
operation of timer 4.
(2) Set the TM4CK2 to 0 flags of the TM4MD register to select fosc, fs/4, or fs/16 as the
clock source.
(3) Set the TM4PWM flag of the TM4MD register to "0" to select 16-bit timer operation.
(4) Set a value in compare register 4 (TM4OCH, TM4OCL).
(5) Set the TM4EN flag of the TM4MD register to "1" to start the timer.
(6) When timer 4 begins operation, binary counter 4 counts upward from X'0000'.
(7) When the value of binary counter 4 matches that of the TM4OCH and TM4OCL
registers, the timer 4 interrupt request flag is set, the value of binary counter 4 is reset
to X'0000', and counting begins again.
When servicing an interrupt, reset
the timer 4 interrupt request flag
before operating timer 4.
During a count operation, be
careful if the value set in TM4OCH
and TM4OCL is smaller than the
value of binary counter 4, since
the count-up operation will
continue until overflow occurs.
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Figure 4-3-1 Binary Counter 4 (TM4BC) Count Timing
Chapter 4 Timer Functions
70
Clock
TM4EN
Binary
counter 4
Write to registers
TM4OCH, TM4OCL
0504 06 07 08 09 00
If the TM4EN flag of the TM4MD register is changed simultaneously
with other bits, the switching operation may cause binary counter 4
to be incremented.
If the value of the TM4OCH, TM4OCL register is overwritten while
timer 4 has stopped counting, binary counter 4 will be reset to
X'0000'.
16-bit Timer Operation (timer 4)
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Chapter 4 Timer Functions
71
16-bit Timer Operation (timer 4)
If TM4IO input is selected as the
clock source and the value of
binary counter 4 is to be read
during operation, select
synchronized TM4IO input to avoid
reading data that may be
incomplete during count-up
transitions. However, with
synchronized TM4IO input, it is not
possible to return from
STOP/HALT modes.
■Event Count Function
Settings for the event count function are listed below.
(1) Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" to stop the count
operation of timer 4.
(2) Use the TM4CK2 to 0 flags of the TM4MD register to select TM4IO input or
synchronized TM4IO input as the clock source.
(3) Set the TM4PWM flag of the TM4MD register to "0" so that 16-bit timer operation
is selected.
(4) Set a value in compare register 4 (TM4OCH, TM4OCL).
(5) Set the TM4EN flag of the TM4MD register to "1" to start the timer.
(6) When timer 4 begins operation, binary counter 4 will count upward from X'0000'.
(7) When the value of binary counter 4 matches that of the TM4OCH and TM4OCL
registers, the timer 4 interrupt request flag is set, and the binary counter 4 is reset to
X'0000' and begins to count upward again.
When synchronized TM4IO is selected, the timer 4 clock source is synchronized with the system
clock after a transition of the TM4IO input signal. Timer 4 counts upward based on a signal
synchronized to the system clock. Therefore, correct values can be read from binary counter 4.
Figure 4-3-2 Timer 4 Event Counter Timing (when synchronous TM4IO
input is selected)
CPU system clock
(fs)
TM4IO input
Synchronous
circuit output
Binary counter n n+1
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Chapter 4 Timer Functions
72
■Timer Pulse Output Function
Settings for the timer pulse output function are listed below.
(1) Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" so that the count
operation of timer 4 is stopped.
(2) Set bit 4 of the port 1 output/input mode register (P1OMD) to the special
function pin setting. Bit 4 of port 1 will be specified as the pulse output pin.
(3) Use the TM4CK2 to 0 flags of the TM4MD register to select fosc, fs/4, or fs/16 as the
clock source.
(4) Set the TM4PWM flag of the TM4MD register to "0" so that 16-bit timer operation
is selected.
(5) Set a value in compare register 4 (TM4OCH, TM4OCL).
(6) Set the TM4EN flag of the TM4MD register to "1" to start the timer.
(7) When timer 4 begins operation, binary counter 4 will count upward from X'0000'.
(8) When the value of binary counter 4 matches that of the TM4OCH and TM4OCL
registers, the timer 4 interrupt request flag is set, and the binary counter 4 is reset to
X'0000' and begins to count upward again.
Figure 4-3-3 Timer Pulse Output Timing
The period of the output signal
from the port is 1/2 of the period
set in the TM4OCH, TM4OCL
register.
Binary
counter 4
Matches TM4OCH, TM4OCL register
TM4OUT
16-bit Timer Operation (timer 4)
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■Pulse Added Type PWM Output Function
In the pulse added method, a 1-bit output is appended to the basic component of the 8-bit
PWM output. Precise control is possible based on the number of PWM repetitions (256
times) to which this bit is appended. Settings for the pulse added type PWM output function
are listed below.
(1) Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" to stop the count
operation of timer 4.
(2) Set bit 4 of the port 1 output/input mode register (P1OMD) to the special function
pin setting. Bit 4 of port 1 will be specified as the PWM output pin.
(3) Use the TM4CK2 to 0 flags of the TM4MD register to select fosc, fs/4, or fs/16 as the
clock source. The period of the output waveform is determined based on the clock source.
(4) Set the TM4PWM flag of the TM4MD register to "1" so that PWM operation is
selected.
(5) Set a value in the lower 8 bits of compare register 4 (TM4OCL). The high interval of
the output waveform is determined based on the value of the lower 8 bits of compare
register 4 (TM4OCL).
(6) Set the position of the added pulse in the upper 8 bits of compare register 4
(TM4OCH).
(7) Set the TM4EN flag of the TM4MD register to "1" to start the timer.
(8) When timer 4 begins operation, binary counter 4 will count upward from X'00'.
(9) A high-level signal is output from the port beginning when binary counter 4 starts
counting from X'00' and ending when the value of binary counter 4 matches the
value set in the TM4OCL register.
(10) When the value of binary counter 4 matches that of the TM4OCL register, a low-
level signal is output from the port.
(11) Binary counter 4 continues to count upward until X'FF' is reached. At the next count-
up cycle, the value of binary counter 4 is reset to X'00', and counting begins again.
A high-level signal is output from the port.
Figure 4-3-4 Pulse Added Type PWM Output
Chapter 4 Timer Functions
73
If bit 4 of port 1 is to be used as a
PWM output pin, set the P1DIR
and P1PLU registers.
PWM4 output is fixed at L with
X'FF' set at the lower 8
bits(TM40CL) of compare register.
Use of timer 4 at PWM mode
disables setting of X'FF' att
TM4OCL register.
,,
,
,,
,,
,,
,,
Added pulse
: Added pulse
Basic PWM components
Repeated 256 times
Tn=X'00' Tn=X'01' Tn=X'02' Tn=X'03' Tn=X'04' Tn=X'FF'
,
Use a 16-bit access instruction to set the TM4OCH, TM4OCL
register.
16-bit Timer Operation (timer 4)
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Chapter 4 Timer Functions
74 16-bit Timer Operation (timer 4)
[☞5-2-3 "Serial Interface
Transfer Timing"]
■Setting the Added Pulse Position
The upper 8 bits of compare register 4 (TM4OCH) set the position of the added pulse. If the
TM4OCH register is set to X'00', an additional bit is not appended to the basic PWM
component. If the TM4OCH register is set to X'FF', an additional bit is repeatedly appended
to the 255 basic PWM components during the period. The relation between the value set in
the TM4OCH register and the added pulse is shown in the table below. If X'03' is set in the
TM4OCH register, bits are appended to pulse positions for X'01' and X'02', shown in table
4-3-1. The relation between the value set in the TM4OCH register and the position of the
added bit is shown in figure 4-3-5.
Table 4-3-1 Pulse-Added PWM OutputFigure
Figure 4-3-5 Pulse Added Type PWM Output
TM4OCH
Register setting
value
X '00'
X '01'
X '02'
X '10'
X '08'
X '04'
0 X '40' X '80' X 'C0' X 'FF'
PWM basic component
Repeated 256 times
Position of
added pulse
Position of added pulse X'87' Position of added pulse X'88'
Value Set in TM4OCH Register
Added Pulse Position (value of Tn)
00000000
00000001
10000000
01000000
00100000
00010000
00001000
00000100
00000010
(MSB) (LSB)
X'80'
X'40',X'C0'
X'20',X'60',X'A0',X'E0'
X'10',X'30',X'50',X'70',X'90',X'B0',X'D0',X'F0'
X'08',X'18',X'28',X'38',X'48',X'58' . . . . .,X'E8',X'F8'
X'04',X'0C',X'14',X'1C',X'24',X'2C' . . . . .,X'F4',X'FC'
X'02',X'06',X'0A',X'0E',X'12',X'16' . . . . .,X'FA',X'FE'
X'01',X'03',X'05',X'07',X'09',X'0B' . . . . .,X'FD',X'FF'
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Chapter 4 Timer Functions
75
16-bit Timer Operation (timer 4)
■Capture Function
Settings for the capture function are listed below.
(1) Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" to stop the count
operation of timer 4.
(2) Use the TM4CK2 to 0 flags of the TM4MD register to select fosc, fs/4, or fs/16 as the
clock source.
(3) Use the T4ICTS1 and T4ICTS0 flags of the TM4MD register to select IRQ2,
IRQ1, or IRQ0 as the input capture trigger.
(4) Set the REDGn flag of the external interrupt control register to specify the valid edge
for the interrupt selected as the TM4 input capture trigger.
(5) Set the TM4PWM flag of the TM4MD register to "1" to select 16-bit timer
operation.
(6) Set a value in compare register 4 (TM4OCH, TM4OCL).
(7) Set the TM4EN flag of the TM4MD register to "1" to start the timer.
(8) When timer 4 begins operation, binary counter 4 will count upward from X'0000'
until it reaches the value set in compare register 4.
(9) If the binary counter is to be used as a free-running counter that counts from
X'0000' to X'FFFF', set the compare register 4 to X'FFFF'.
When the value of binary counter 4 matches that of the TM4OCH, TM4OCL
register, the timer 4 interrupt request flag is set, binary counter 4 is reset to X'0000',
and counting begins again.
(10) If the external interrupt selected as the TM4 input capture trigger is received during
timer 4 operation, the value of binary counter 4 will be written into the input capture
register (TM4ICH, TM4ICL).
Setting a value in compare register
4, clears binary counter 4.
If the event occurs before a read,
that data will be overwritten.
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Chapter 4 Timer Functions
76 8-bit Timer Operation (timers 2, 3)
4-4 8-bit Timer Operation (timer 5)
4-4-1 Overview
Timer 5 is an 8-bit timer that can have fosc, fs/4, fx, or time base output as
its clock source.
4-4-2 Operation
■Timer Operation
Settings for timer operation are listed below.
(1) Set the TM5CLRS flag of the timer 5 mode register (TM5MD) to "0."
(2) Use the TM5CK3 to 1 flags of the TM5MD register to select fosc, fs/4, fx,
synchronized fx, time base timer output, or time base timer synchronized output as
the clock source.
(3) Set a value in compare register 5 (TM5OC). At this time, if the TM5CLRS flag is
"0," binary counter 5 will be initialized to X'00'.
(4) Binary counter 5 (TM5OC) counts upward from X'00'.
(5) When the value of binary counter 5 matches that of the TM5OC register, the timer 5
interrupt request flag is set, the binary counter is reset to X'00', and counting begins
again.
If the TM5CLRS flag of the TM5MD register is set to "0," binary
counter 5 will be initialized every time data in the TM5OC register is
overwritten. Timer 5 interrupts are disabled in this mode. If timer 5
interrupts are to be used, the TM5CLRS flag must be reset to "1"
after writing to the TM5OC register.
Timer 5 operation cannot be halted.
When servicing an interrupt, reset
the timer 5 interrupt request flag
before starting timer 5.
When choosing either time base
timer output or time base timer
synchronized output for the timer 5
clock source, the time base must
be set up.
During a count operation, be
careful if the value set in TM5OC
is smaller than the value of binary
counter 5, since the count-up
operation will continue until
overflow occurs.
If fx input is selected as the clock
source and the value of binary
counter 5 is to be read during
operation, select synchronized fx
input to avoid reading data that
may be incomplete during count-
up transitions. However, with
synchronized fx input, it is not
possible to return from
STOP/HALT modes.
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4-5 Time Base Operation
4-5-1 Overview
The clock source for the time base timer can be set to fosc or fx. Also, the interrupt
period for time base timer (TBIRQ) can be set to 1/27, 1/28, 1/29, 1/210, or 1/213 of the
clock source.
4-5-2 Operation
■Time Base Function
Settings for the time base function are listed below.
(1) Use the TM5CK0 flag of the timer 5 mode register (TM5MD) to select fosc or fx as
the clock source.
(2) Use the TM5IR2 to 0 flags of the TM5MD register to select the time base timer
interrupt source.
(3) When the selected time interval passes, the interrupt request flag of the time base
interrupt control register (TBICR) is set.
Table 4-5-1 Base Time Settings
Chapter 4 Timer Functions
77
TM5IR2 to 0
Clock Source
fosc 20MHz
8.38MHz
32.768kHz
6.4µs
15.2µs
3.9ms
12.8µs
30.5µs
7.8ms
25.6µs
61.0µs
15.6ms
51.2µs
122.0µs
31.2ms
409.6µs
000 001 010 011 1XX
1
271
281
291
210 1
213
976.4µs
250ms
fx
Time base operation cannot be halted.
Time Base Operation
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Chapter 4 Timer Functions
78
4-6 Watchdog Timer Operation
4-6-1 Overview
The watchdog timer is controlled by the watchdog control register (WDCTR) and can
be used for runaway program detection.
4-6-2 Setup and Operation
(1) Set the WDEN flag of the watchdog timer control register (WDCTR) to "1" to start
the watchdog timer.
(2) Operate the watchdog timer by clearing the WDEN flag to "0" within the fixed
amount of time (TWD), and then resetting the WDEN flag to "1."
If the WDEN flag is not cleared, a WDT interrupt will be generated after the fixed
amount of time passes.
(3) When an illegal operation is detected, the program encoded at the location of the
WDT interrupt routine is executed.
TWD is set by the ROM option as fs/216, fs/218, or fs/220.
Illegal operation detection period vs. WDEN clear period is shown by the following formula:
Illegal operation detection period > [WDEN clear period] x 4
The upper 2 bits of the watchdog
timer are cleared when the WDEN
flag is set to "0." Therefore, if
WDEN flag is set to 0 when an
uppermost bit of a watchdog timer
is 1, WDT interrupt occurs
depending on the timing of this
clear the watchdog timer may be
reset at 1/4T WD. If the WDEN bit is
to be repeatedly cleared and set at
regular intervals, those operations
should be performed within 1/4 of
the TWD period.
When software resetting is not triggered by WDT interrupt,
hardware resetting (low level output at the reset terminal) takes
place at the next WDT interrupt.
Watchdog Timer Operation
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4-7 Remote Control Output Operation
4-7-1 Overview
A remote control carrier pulse can be generated using the overflow of timer 3. Two
duty ratios of 1/2 or 1/3 can be selected.
4-7-2 Setup and Operation
(1) Set the RMOEN flag of the remote control carrier output control register (RMCTR)to
"0" so that the remote control carrier output is switched off.
(2) Set timer 3 to select the base period of the remote control carrier (the
width that the remote control carrier output pulse is held at a high level).
(3) Set the RMDTY0 flag of the RMCTR register to select the carrier duty.
(4) Set the P10 output data to "0" and set P10 to the output mode. And select the remote
control carrier output by setting the TMORM flag of the RMCTR register to "0".
(5) The RMOEN flag of the RMCTR register controls whether the remote control carrier
output is on or off.
Even if the carrier output is at a high level, and the RMOEN flag is set to "0"
(off), the carrier waveform will be maintained by the synchronous circuit
Figure 4-7-1 Remote Control Carrier Output Waveform
Chapter 4 Timer Functions
79
Base period
set by TM3
RMOUT
(1/3 duty)
RMOEN Output on
Output off
Set bit 0 of the P1OMD register to
"1" at the same time the remote
control output is switched on, and
to "0" at the same time the remote
control output is switched off.
Remote Control Output Operation
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Chapter 4 Timer Functions
80
4-8 Buzzer Output
4-8-1 Buzzer Output Setup and Operation
The square wave having a frequency 1/29to 1/212 of the system clock can be
output from the P06/BUZZER pin.
(1) Set the BUZOE flag of the oscillation stabilization wait control register (DLYCTR)
to "0" so that the buzzer output is turned off.
(2) Set the buzzer output frequency with the BUZCK1 and BUZCK0 flags of the
DLYCTR.
(3) Set the BUZOE flag of the DLYCTR register to "1" and set P06 to the buzzer output
mode.
(4) The BUZOE flag of the DLYCTR register controls whether the buzzer output is ON
or OFF.
Buzzer Output
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Chapter 4 Timer Functions
81
Overview
4-9 Timer Function Control Registers
4-9-1 Overview
19 registers control the timers. See table 4-9-1.
Table 4-9-1 Timer Control Registers
R/W: Readable and writable
R: Read only
Name Address R/W
X’03F72’
X’03F62’
X’03F82’
X’03F73’
X’03F63’
X’03F83’
X’03F64’
X’03F74’
X’03F75’
X’03F65’
X’03F66’
X’03F67’
X’03F84’
X’03F78’
X’03F68’
X’03F88’
X’03F02’
X’03F03’
X’03F89’
TM2OC R/W
TM2BC R
TM2MD R/W
TM3OC R/W
TM3BC R
TM3MD R/W
TM4BCL
R/W
TM4OCL R/W
TM4OCH R
TM4BCH R
TM4ICL R
TM4ICH R
TM4MD R/W
TM5OC R/W
TM5BC R
TM5MD R/W
WDCTR R/W
DLYCTR R/W
RMCTR R/W
Compare register 2
Binary counter 2
Timer 2 mode register
Compare register 3
Binary counter 3
Timer 3 mode register
Compare register 4 (lower 8 bits)
Compare register 4 (upper 8 bits)
Binary counter 4 (lower 8 bits)
Binary counter 4 (upper 8 bits)
Input capture register (lower 8 bits)
Input capture register (upper 8 bits)
Timer 4 mode register
Compare register 5
Binary counter 5
Timer 5 mode register
Watchdog timer control register
Oscillation stabilization wait control register
Remote control carrier output control register
Function
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Chapter 4 Timer Functions
82 Timer Function Control Registers
4-9-2 Programmable Timer/Counters
Timers 2~5 all contain a programmable 8-bit timer/counter (16-bit in timer 4).
Programmable timer/counters consist of a compare register and a binary
counter.
(1) Compare register 2 (TM2OC)
Figure 4-9-1 Compare Register 2 (TM2OC: X'03F72', R/W)
(2) Binary counter 2 (TM2BC)
Figure 4-9-2 Binary Counter 2 (TM2BC: X'03F62', R)
(3) Compare register 3 (TM3OC)
Figure 4-9-3 Compare Register 3 (TM3OC: X'03F73', R/W)
(4) Binary counter 3 (TM3BC)
Figure 4-9-4 Binary Counter 3 (TM3BC: X'03F63', R)
01245673
TM2OC0
(at reset: undefined)
TM2OC1TM2OC2TM2OC4TM2OC5TM2OC6TM2OC7 TM2OC3
01245673
TM2BC0
(at reset: 00000000)
TM2BC1TM2BC2TM2BC4TM2BC5TM2BC6TM2BC7 TM2BC3
01245673
TM3OC0
(at reset: undefined)
TM3OC1TM3OC2TM3OC4TM3OC5TM3OC6TM3OC7 TM3OC3
01245673
TM3BC0
(at reset: 00000000)
TM3BC1TM3BC2TM3BC4TM3BC5TM3BC6TM3BC7 TM3BC3
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(5) Compare register 4 (TM4OCL) (lower 8 bits)
Figure 4-9-5 Compare Register 4 (TM4OCL: X'03F74', R/W)
(6) Compare register 4 (TM4OCH) (upper 8 bits)
Figure 4-9-6 Compare Register 4 (TM4OCH: X'03F75', R/W)
(7) Binary counter 4 (TM4BCL) (lower 8 bits)
Figure 4-9-7 Binary Counter 4 (TM4BCL: X'03F64', R)
(8) Binary counter 4 (TM4BCH) (upper 8 bits)
Figure 4-9-8 Binary Counter 4 (TM4BCH: X'03F65', R)
Chapter 4 Timer Functions
83
Timer Function Control Registers
01245673
TM4BCH0
(at reset: 00000000)
TM4BCH1TM4BCH2TM4BCH4TM4BCH5TM4BCH6TM4BCH7 TM4BCH3
01245673
TM4BCL0
(at reset: 00000000)
TM4BCL1TM4BCL2TM4BCL4TM4BCL5TM4BCL6TM4BCL7 TM4BCL3
01245673
TM4OCL0
(at reset: undefined)
TM4OCL1TM4OCL2TM4OCL4TM4OCL5TM4OCL6TM4OCL7 TM4OCL3
01245673
TM4OCH0
(at reset: undefined)
TM4OCH1TM4OCH2TM4OCH4TM4OCH5TM4OCH6TM4OCH7 TM4OCH3
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Chapter 4 Timer Functions
84 Timer Function Control Registers
(9) Input capture register (TM4ICL) (lower 8 bits)
Figure 4-9-9 Input Capture Register (TM4ICL: X'03F66', R)
(10) Input capture register (TM4ICH) (upper 8 bits)
Figure 4-9-10 Input Capture Register (TM4ICH: X'03F67', R)
(11) Compare register 5 (TM5OC)
Figure 4-9-11 Compare Register 5 (TM5OC: X'03F78', R/W)
(12) Binary counter 5 (TM5BC)
Figure 4-9-12 Binary Counter 5 (TM5BC: X'03F68', R)
01245673
TM5OC0
(at reset: undefined)
TM5OC1TM5OC2TM5OC4TM5OC5TM5OC6TM5OC7 TM5OC3
01245673
TM5BC0
(at reset: 00000000)
TM5BC1TM5BC2TM5BC4TM5BC5TM5BC6TM5BC7 TM5BC3
01245673
TM4ICL0
(at reset: undefined)
TM4ICL1TM4ICL2TM4ICL4TM4ICL5TM4ICL6TM4ICL7 TM4ICL3
01245673
TM4ICH0
(at reset: undefined)
TM4ICH1TM4ICH2TM4ICH4TM4ICH5TM4ICH6TM4ICH7 TM4ICH3
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Chapter 4 Timer Functions
85
Timer Function Control Registers
4-9-3 Timer Mode Registers
Four readable and writable 6-byte timer mode registers. Control timers 2, 3, 4, 5, and
the time base.
(1) Timer 2 mode register (TM2MD)
Figure 4-9-13 Timer 2 Mode Register (TM2MD: X'03F82', R/W)
01245673
(at reset: ---00XXX)–––
TM2MD
TM2CK0
TM2CK1TM2CK2
0
1
1
X
1
0
0
0
0
1
1
0
1
1Normal timer operation
TM2 operation mode selection
TM2 count control
PWM operation
TM2CK0
TM2CK1TM2CK2
TM2PWMTM2EN
fs
fs/4
fx *
TM2IO input
Synchronous fx *
Synchronous TM2IO input
Clock source selection
TM2PWM
0
1Halt the count
Operate the count
TM2EN
* 48QFH package only
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(2) Timer 3 mode register (TM3MD)
Figure 4-9-14 Timer 3 Mode Register (TM3MD: X'03F83', R/W)
Chapter 4 Timer Functions
86 Timer Function Control Registers
TM3CK1
0
0
1
1
0
0
1fosc
fs/4
fs/16
TM3IO input
Cascade connection with timer 2
Synchronous TM3IO input
1
1
x0
1
Clock source selection
TM3CK0
0
1Halt the count
P13 output selection
during TM2 PWM operation
Operate the count
TM3PWM
0
1Timer 3 output
TM3 count control
Timer 2 PWM output
TM3EN
0124567
–––
3
(at reset: ---00XXX)
TM3MD
TM3CK0
TM3CK2
TM3CK1TM3CK2TM3PWMTM3EN
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(3) Timer 4 mode register (TM4MD)
Figure 4-9-15 Timer 4 Mode Register (TM4MD: X'03F84', R/W)
Chapter 4 Timer Functions
87
Timer Function Control Registers
0124567
–
3
(at reset: -0000XXX)
TM4MD
TM4CK0
TM4CK1TM4CK2
0
1
0
1
1
0
0
0
1fosc
fs/4
fs/16
TM4IO input
Synchronous TM4IO input
1
1
1Halt the count
TM4 count control
TM4 operation mode selection
Clock source selection
Operate the count
TM4CK0
TM4CK1TM4CK2T4ICTS0TM4PWM T4ICTS1TM4EN
T4ICTS1
0
1
0
0
1 IRQ0
IRQ1
IRQ2
1
TM4 input capture trigger selection
Disable input capture operation
T4ICTS0
TM4EN
0
116-bit timer operation
PWM operation
TM4PWM
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(4) Timer 5 mode register (TM5MD)
Figure 4-9-16 Timer 5 Mode Register (TM5MD: X'03F88', R/W)
Chapter 4 Timer Functions
88 Timer Function Control Registers
TM5CK3
X
0
TM5CK2
0
1
1
fs/4
(Use Prohibited)
Output of time base timer
Timer 5 clock source selection
fosc
0
0
1
1(Use Prohibited)
Synchronous time base timer output
0
1
TM5CK1
TM5IR1
0
0
1
0
0
11/27 of the clock source
1/28 of the clock source
1/29 of the clock source
1/210 of the clock source
1/213 of the clock source
1
xx1
Time base timer
interrupt period selection
TM5IR0
01245673
(at reset: 0XXXXXX0)
TM5MD
TM5CK0
TM5IR2
0
TM5CLRS
TM5CK1TM5CK2TM5CK3TM5IR0TM5IR1TM5IR2
TM5CLRS
0
1fosc
Time base timer
clock source selection
TM5CK0
Binary counter 5
clear selection flag
Disable initialization of
TM5BC during a write to TM5OC
1
∗If TM5CLRS=0, TM5IRQ is disabled.
Enable initialization of
TM5BC during a write to TM5OC
(Use Prohibited) fx *
* 48QFH package only
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4-9-4 Timer Control Registers
(1) Watchdog timer control register (WDCTR)
Figure 4-9-17 Watchdog Timer Control Register (WDCTR: X'03F02', R/W)
(2) Oscillation stabilization wait control register (DLYCTR)
Figure 4-9-18 Oscillation Stabilization Wait Counter Control Register
(DLYCTR: X'03F03', R/W)
Chapter 4 Timer Functions
89
Timer Function Control Registers
BUZCK1
0
1
0
0
1
1
Buzzer output
frequency selection
BUZCK0
01245673
–––
DLYCTR DLYS0DLYS1
BUZOE
DLYS1
0
1
0
0
11/214 of the system clock (fs)
1/210 of the system clock (fs)
1/26 of the system clock (fs)
1/212 of the system clock (fs)
1/211 of the system clock (fs)
1/210 of the system clock (fs)
1/29 of the system clock (fs)
Oscillation stabilization
wait period setting
DLYS0
11
Disable use
BUZOE
0
1P06 port output
P06 buzzer output
P06 output selection
BUZCK1BUZCK0
(at reset: 0XX---00)
∗After reset is released, the oscillation
stabilization wait period is fixed at 1/215.
01245673
–––––––
WDCTR
WDEN
Watchdog timer enable
0
1
Clear watchdog timer/disable operation
Enable WDT timer
WDEN
(at reset: -------0)
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(3) Remote control carrier output control register (RMCTR)
Figure 4-9-19 Remote Control Carrier Control Register
(RMCTR: X'03F89', R/W)
Chapter 4 Timer Functions
90 Timer Function Control Registers
01245673
RMCTR ––– –––
RMDTY0
RMOEN
Enable remote control
carrier output
0
1Output low level
Output remote control carrier
RMOEN
0
11/2 duty
1/3 duty
Remote control carrier
output duty selection
RMDTY0
Must be set to "0."
Must be set to "0."
Must be set to "0."
(at reset: ---00XX0)
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Chapter 5 Serial Functions
92 Overview
5-1 Overview
The MN101C117 contains a serial interface that can operate in synchronous
and simple UART modes.
An overview of serial functions is shown below.
Table 5-1-1 Overview of Serial Functions
Interrupt
Serial 0
Synchronous
Simple UART
Clock selection
1/8 period of clock
SC0ICR
fs/2
fs/4
fs/16
BC3X1/2
External
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Chapter 5 Serial Functions
93
Overview
Figure 5-1-1 Serial 0 Block Diagram
fs/2
fs/4
fs/16
BC3×1/2
SBI0/RXD/P01 SBO0/TXD1/P00
SC0RXB
SC0TRB
SBT0/P02 SC0IRQ
Shift register
SWAP
Start condition
transmission
Receive buffer
SC0PEK
SC0FEF
–
SC0BSY
SC0CMD
–
SC0ORE
0
7
0
7
–
SC0SBTS 0
7
0
7
SC0SBIS
SC0SBOS
SC0SBTM
SC0SBOM
SC0IOM
–
–
SC0TRI
SC0BRKF
SC0CK0
SC0CKM
–
–
SC0CK1
SC0ERE
SC0LNG0
SC0MD0
SC0MD1
SC0MD3
SC0NPE
SC0PM0
SC0PM1
SC0FM0
SC0FM1
SC0BRKE
–
–
SC0MD2
SC0CTR
SC0LNG1
SC0LNG2
SC0STE
SC0DIR
SC0CE0
SC0CE1
–
M
U
X
M
U
X
M
U
XBit counter
3
2
Start condition
detection
Break
receive control
Stop bit
detection
Receive
control
parity check Append
transmit
control parity
88
8
8
8
0
7
SBO0/P00
ORE detection
control
1/2 of timer 3
overflow
M
U
X
1/8
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Chapter 5 Serial Functions
94
5-2 Synchronous Serial Interface
5-2-1 Overview
A serial interface begins operation when data is written to the shift buffer. A bit
counter is incremented at each 1-bit transfer. The transfer is complete when the
counter overflows.
Bit transfers of an arbitrary 1 to 8 bits can be performed. The transfer bit count must
be set before performing the transfer.
5-2-2 Setup and Operation
■Transmission
(1) Select the synchronous serial interface by setting the SC0CMD flag of the
serial interface 0 control register (SC0CTR) to "0."
(2) Select the transfer bit count with the SC0LNG2 to 0 flags of the serial
interface 0 mode register 0 (SC0MD0). The transfer bit count can be
set as 1 to 8 bits.
(3) Specify whether the start condition is enabled or disabled with the SC0STE
flag of the SC0MD0 register.
(4) Specify the first bit to be transferred (MSB first or LSB first) with the
SC0DIR flag of the SC0MD0 register.
(5) Select the valid edge of the clock signal with the SC0CE1 to 0 flags of the
SC0MD0 register.
(6) When the clock source is an internal clock:
•Select the clock source with the SC0CK1 to 0 flags of serial interface 0
mode register 1 (SC0MD1).
•Set the SC0CKM flag of the SC0MD1 register specify whether or not the
clock source frequency will be divided by 8.
•Select serial clock operation by setting the SC0SBTS flag of the serial
interface 0 mode register 3 (SC0MD3) to "1."
•Set the SC0SBTM flag of the SC0MD3 register.
•Set bit 0 of the port 0 direction control register (P0DIR) to the output
mode.
•Set bit 0 of the port 0 pull-up resistor control register (P0PLU).
Synchronous Serial Interface
[☞ Section 5-2-3, "Serial
Interface Transfer Timing"]
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Chapter 5 Serial Functions
95
Synchronous Serial Interface
When the clock source is an external clock (SBT0 pin input):
•Set the SC0SBTM flag of the SC0MD3 register.
•Set bit 2 of the P0DIR register to input mode.
•Set the P0PLU register, if necessary.
(7) Select the SC0SBOM flag of the SC0MD3 register.
(8) Select the SC0IOM flag of the SC0MD3 register.
(9) Select serial communication by setting the SC0SBOS flag of the
SC0MD3 register to "1."
(10) Set transmit data to serial interface 0 transmit/receive shift register
(SC0TRB). This will start the serial transmission.
(11) When serial transmission begins, the SC0BSY flag of the SC0CTR register
is set to "1," indicating that a serial transfer is in progress.
(12) When the serial transmission has completed, the SC0BSY flag of the
SC0CTR register is cleared to "0" and the SC0 transfer complete interrupt
request flag is set to "1." The SC0TRI flag of SC0MD1 register 1 is cleared
to "0."
When the serial port is enabled
and the SC0CE1 to 0 flags of
the SC0MD0 register are
changed, the transfer bit count
in the SC0LNG2 to 0 flags of
the SC0MD0 register may be
incremented.
Enabling the start condition
drives the SBO0 pin high for a
fixed time interval (1/2 the
clock source cycle) after the
transmission is completed. If
the start condition is disabled,
the SBO0 pin will remain at the
value of the of the last data bit.
If the SC0IOM flag of the
SC0MD3 register is set for a
pin connection, the SBI0 pin
can be used as a port. The
SBO0 pin receives data during
the input mode and transmits
data during the output mode.
The SC0LNG2 to 0 flags
change at the opposite edge of
the transmit data output edge.
Serial interface 0 begins
operation when the SC0SBOS
flag or the SC0SBIS flag is set
to "1." Set the SC0SBOS flag
or the SC0SBIS flag after all
conditions have been set.
After the transfer is complete, the transfer bit count in the
SC0LNG2 to 0 flags of the SC0MD0 register will be changed.
Except in an 8-bit transfer, reset the transfer bit count at the
time of the next transmission.
The SC0SBTS flag of the SC0MD3 register must be set to "1"
before the SC0SBOS flag of the SC0MD3 register is set to
"1."
When switching from transmission to reception, set the
SC0SBOS flag of the SC0MD3 register to "0" and then set
the SC0SBIS flag to "1." Do not change both of these flags at
the same time.
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Chapter 5 Serial Functions
96
Figure 5-2-1 Synchronous Serial Interface Transmission Timing (falling edge)
Figure 5-2-2 Synchronous Serial Interface Transmission Timing (rising edge)
Clock
Start condition
enabled
Start condition
disabled
SC0BSY
Interrupt
SC0LNG2 to 0
SBT
SBO
SBO
ts
012345670
Synchronous Serial Interface
SBT
SBO
SBO
Clock
Start condition
enabled
Start condition
disabled
SC0BSY
Interrupt
SC0LNG2 to 0 012345670
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Chapter 5 Serial Functions
97
■Reception
(1) Select the synchronous serial interface by setting the SC0CMD flag of the
serial interface 0 control register (SC0CTR) to "0."
(2) Select the transfer bit count with the SC0LNG2 to 0 flags of the serial
interface 0 mode register 0 (SC0MD0). The transfer bit count can be set as
1 to 8 bits.
(3) Specify whether the start condition is enabled or disabled with the SC0STE
flag of the SC0MD0 register.
(4) Specify the first bit to be transferred (MSB first or LSB first) with the
SC0DIR flag of the SC0MD0 register.
(5) Select the valid edge of the clock signal with the SC0CE1 to 0 flags of the
SC0MD0 register.
(6) When the clock source is an internal clock:
•Select the clock source with the SC0CK1 to 0 flags of serial interface 0
mode register 1 (SC0MD1).
•Set the SC0CKM flag of the SC0MD1 register to specify whether or not
the clock source frequency will be divided by 8.
•Select serial clock pin operation by setting the SC0SBTS flag of the
serial interface 0 mode register 3 (SC0MD3) to "1."
•Set the SC0SBTM flag of the SC0MD3 register.
•Set bit 2 of the port 0 direction control register (P0DIR) to the output
mode (P02/SBT0 output mode).
•If necessary, set bit 2 of the port 0 pull-up resistor control register
(P0PLU) to add the pull-up resistor.
When the clock source is an external clock (SBT0 pin input):
•Set bit 2 of the P0DIR register to the input mode.
•If necessary, set bit 2 of the P0PLU register.
(7) Select the SC0IOM flag of the SC0MD3 register.
(8) Select serial communication by setting the SC0SBIS flag of the SC0MD3
register to "1." (Reception data wait.)
(9) When the serial reception begins, the SC0BSY flag of the serial interface 0
control register (SC0CTR) is set to "1," indicating that a serial transfer is in
progress.
(10) When the serial reception is complete, the SC0BSY flag of the SC0CTR
register is cleared to "0" and the SC0 transfer complete interrupt request flag
is set to "1." The SC0TRI flag of the SC0MD1 register is set to "1."
Synchronous Serial Interface
When the serial port is enabled
and the SC0CE1 to 0 flags of
the SC0MD0 register are
changed, the transfer bit count
in the SC0LNG2 to 0 flags of
the SC0MD0 register may by
incremented.
[☞Section 5-2-3, "Serial
Interface Transfer Timing"]
If the start condition is enabled,
the SC0LNG2 to 0 flags of the
SC0MD0 register will be
cleared when the start
condition is received. In this
case, the receive bit count is
fixed at 8 bits.
The SC0SBTS flag of the
SC0MD3 register must be set
to "1" before setting the
SC0SBIS flag of the SC0MD3
register to "1."
If the internal clock is selected
as the clock source, after
setting the SC0SBIS flag of the
SC0MD3 register to "1," write
dummy data to the SC0TRB
register. If there is to be
another reception, write
dummy data again to the
SC0TRB register.
The SC0LNG2 to 0 flags
change at the opposite edge of
the transmit data output edge.
Serial interface 0 begins
operation when the SC0SBOS
flag or the SC0SBIS flag is set
to "1." Set the SC0SBOS flag
or the SC0SBIS flag after all
conditions have been set.
After the transfer is complete, the transfer bit count in the
SC0LNG2 to 0 flags of the SC0MD0 register will be
changed. Except in an 8-bit transfer count, reset the
transfer bit count at the time of the next reception.
When switching from reception to transmission, set the
SC0SBIS flag of the SC0MD3 register to "0" and then set
the SC0SBOS flag to "1." Do not change both of these
flags at the same time.
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Chapter 5 Serial Functions
98
Figure 5-2-3 Synchronous Serial Interface Reception Timing
(reception at rising edge)
Figure 5-2-4 Synchronous Serial Interface Reception Timing
(reception at falling edge)
Synchronous Serial Interface
Clock
Start condition
disabled
Start condition
enabled
SC0BSY start
condition
enabled
SC0BSY start
condition
disabled
Interrupt
SC0LNG2 to 0 012345670
Clock
Start condition
enabled
Start condition
disabled
SC0BSY start
condition
disabled
SC0BSY start
condition
enabled
Interrupt
SC0LNG2 to 0 012345670
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Chapter 5 Serial Functions
99
Synchronous Serial Interface
5-2-3 Serial Interface Transfer Timing
Serial interface 0 uses the SC0CE0 and SC0CE1 flags of serial interface 0 mode
register 0 (SC0MD0), to control the edge at which transmission data is output and
the edge at which reception data is input.
During transmission, when the SCnCE1 flag is "0," data output is synchronized to
the falling edge of the clock.
During reception, when the SCnCE0 flag is "0," data reception is synchronized to
the opposite polarity edge of the transmit data edge. When the SCnCE0 flag is "1,"
data reception is synchronized to the same polarity edge as the transmit data edge.
Table 5-2-1 Serial Data Input Edge and Output Edge (serial interface 0)
SC0CE0 SC0CE1
Receive Data Input Edge Transmit Data Output Edge
0
1
0
0
0
1
11
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Chapter 5 Serial Functions
100
When serial interface 0 is used for simultaneous transmission and reception, set the
SCnCE0 and SCnCE1 flags of the SCnMD0 register to "00" or "01", so that the
reception data input edge is opposite in polarity to the transmit data output edge.
Also, the polarity of the reception data input edge is opposite polarity of the
transmit data output edge of the other device.
Figure 5-2-5 Synchronous Serial Transmit/Receive Timing
(data is received at the rising edge and transmitted at the falling edge)
Figure 5-2-6 Synchronous Serial Transmit/Receive Timing
(data is received at the falling edge and transmitted at the rising edge)
Synchronous Serial Interface
SBT0
SBI0
SBO0
Data is input in synchronization with the rising edge of the clock.
Data is output in synchronization with the falling edge of the clock.
SBT0
SBI0
SBO0
Data is input in synchronization with the falling edge of the clock.
Data is output in synchronization with the rising edge of the clock.
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Chapter 5 Serial Functions
101
5-3 Half-duplex UART Serial Interface
5-3-1 Overview
Setup and operation of UART transmission and reception are described
below.
5-3-2 Setup and Operation
■Transmission
(1) Select UART by setting the SC0CMD flag of the serial interface 0 control
register (SC0CTR) to "1."
(2) Specify the first bit to be transferred (MSB first or LSB first) with the
SC0DIR flag of the serial interface 0 mode register 0 (SC0MD0).
(3) Select the valid edge of the clock signal with the SC0CE1 to 0 flags of the
SC0MD0 register.
(4) Select the clock source with the SC0CK1 to 0 flags of serial interface 0
mode register 1 (SC0MD1).
(5) Set the SC0CKM flags of the SC0MD1 register to "1" to divide the clock
source frequency by 8.
(6) Set the SC0NPE flag of the serial interface 0 mode register 2 (SC0MD2) to
enable or disable parity.
Half-duplex UART Serial Interface
When the serial port is enabled
and the SC0CE1 to 0 flags of
the SC0MD0 register are
toggled, the transfer bit count
may change.
The TXD pin goes to a high
level after transmission is
complete.
Setting the SC0FM flag of the SC0MD2 register to frame
mode automatically sets the SC0LNG2 to 0 flags of the
SC0MD0 register.
After the transfer is complete, the SC0LNG2 to 0 flags of the
SC0MD0 register are automatically set with the transfer bit
count.
Set the SC0CKM flag of the SC0MD1 register to "1" to divide
the clock source frequency by 8.
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Chapter 5 Serial Functions
102
(7) If parity is enabled by the SC0NPE flag of the SC0MD2 register, set the
SC0PM1~0 flags of the SC0MD2 register to specify the added parity bit.
(8) Set the SC0FM1 to 0 flags of the SC0MD2 register to specify the frame
mode.
(9) Set the SC0BRKE flag of the SC0MD2 register to control break status
transmission.
(10) Select the SC0SBOM flag of the SC0MD3 register.
(11) Select the SC0IOM flag of the SC0MD3 register.
(12) Set bit 0 of the port 0 direction control register (P0DIR) to the output mode.
(13) Select serial communication by setting the SC0SBOS flag of the SC0MD3
register to "1."
(14) Set transmit data to serial interface 0 transmit/receive shift register
(SC0TRB). This will start the serial transmission.
(15) When the serial transmission begins, the SC0BSY flag of the SC0CTR
register is set to "1," indicating that a serial transfer is in progress.
(16) When the serial transmission is complete, the SC0BSY flag of the SC0CTR
register is cleared to "0" and the SC0 transfer complete interrupt request flag
is set to "1." The SC0TRI flag of the SC0MD1 register is cleared to "0."
Figure 5-3-1 UART Transmission Timing
Half-duplex UART Serial Interface
Serial interface 0 begins
operation when the SC0SBOS
flag or the SC0SBIS flag is set
to "1." Set the SC0SBOS flag
or the SC0SBIS flag after all
conditions have been set.
TXD
Parity enabled
Parity disabled
Parity
bit Stop
bit
Stop
bit
Stop
bit
Stop
bit
SC0BSY
Parity disabled
SC0BSY
Parity enabled
Interrupt
Parity disabled
Interrupt
Parity enabled
TXD
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Chapter 5 Serial Functions
103
When the serial port is enabled
and the SC0CE1 to 0 flags of
the SC0MD0 register are
toggled, the transfer bit count
may change.
The TXD pin goes to a high
level after reception is
complete.
Serial interface 0 begins
operation when the SC0SBOS
or SC0SBIS flag is set to "1."
Set the SC0SBOS or SC0SBIS
flag after all conditions have
been set.
One machine cycle after the
stop bit has been received, the
start condition will no longer be
accepted. Therefore,
consecutive reception must be
performed carefully.
Half-duplex UART Serial Interface
■Reception
(1) Select UART by setting the SC0CMD flag of the serial interface 0 control
register (SC0CTR) to "1."
(2) Specify the first bit to be transferred (MSB first or LSB first) with the
SC0DIR flag of the serial interface 0 mode register 0 (SC0MD0).
(3) Select the valid edge of the clock signal with the SC0CE1 to 0 flags of the
SC0MD0 register.
(4) Select the clock source with the SC0CK1~0 flags of serial interface 0 mode
register 1 (SC0MD1).
(5) Set the SC0CKM flags of the SC0MD1 register to "1" to divide the clock
source frequency by 8.
(6) Set the SC0NPE flag of the serial interface 0 mode register 2 (SC0MD2) to
enable or disable parity.
(7) If parity is enabled by the SC0NPE flag of the SC0MD2 register, set the
SC0PM1 to 0 flags of the SC0MD2 register to specify the added parity bit.
(8) Set the SC0FM1 to 0 flags of the SC0MD2 register to specify the frame
mode.
(9) Select the SC0IOM flag of the SC0MD3 register.
(10) When the SC0IOM flag of the SC0MD3 register is specified that the pin is
independent, set bit 1 of the port 0 direction control register (P0DIR) to the
input mode.
(11) Set bit 0 of the port 0 pull-up resistor control register (P0PLU).
(12) Select serial communication by setting the SC0SBIS flag of the SC0MD3
register to "1."
(13) When the serial transmission begins, the SC0BSY flag of the SC0CTR
register is set to "1," indicating that a serial transfer is in progress.
(14) When the serial transmission is complete, the SC0BSY flag of the SC0CTR
register is cleared to "0" and the SC0 transfer complete interrupt request flag
is set to "1." The SC0TRI flag of the SC0MD1 register is cleared to "1."
Setting the SC0FM flag of the SC0MD2 register to frame
mode automatically sets the SC0LNG2 to 0 flags of the
SC0MD0 register.
After the transfer is complete, the SC0LNG2 to 0 flags of the
SC0MD0 register are automatically set with the transfer bit
count.
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Chapter 5 Serial Functions
104
Figure 5-3-2 UART Reception Timing
Half-duplex UART Serial Interface
RXD
RXD
Parity enabled
Parity disabled
Parity
bit Stop
bit
Stop
bit
Stop
bit
Stop
bit
SC0BSY
Parity disabled
SC0BSY
Parity enabled
Interrupt
Parity disabled
Interrupt
Parity enabled
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5-3-3 How to Use the Baud Rate Timer
Refer to the following when using the baud rate timer to set the UART transfer
speed.
(1) Specifying the timer clock source
The clock source is specified by the TM3CKS3 to 1 flags of the timer 3
mode register (TM3MD).
(2) Setting the compare register
The compare register value is set in the timer 3 compare register (TM3OC).
This set value is computed according to the following formula:
overflow period = (compare register set value + 1) ×timer clock period
baud rate = 1/(overflow period ×2 × 8)
↑SC0MD1(SC0CKM)
compare register set value = timer clock frequency/(baud rate ×2 ×8) – 1
Table 5-3-1 UART Transfer Rate
Example:
The timer 3 clock source is fs/4 (fosc = 8MHz) and a baud rate of 300 bps is
desired.
Since fs=fosc/2,
compare register set value = (8 ×106/2/4)/(300 ×2 ×8) – 1
=207
= X'CF'
Chapter 5 Serial Functions
105
Half-duplex UART Serial Interface
4.0
fosc
(MHz)
Transfer Speed
(bps)
fosc
fs/4
fs/16
—
104
—
—
Set
Value Calculated
Value Set
Value Calculated
Value Set
Value Calculated
Value Set
Value Calculated
Value Set
Value Calculated
Value Set
Value Calculated
Value
300
—
208
—
—
1202
—
—
104
—
—
2403
—
—
52
—
—
4807
—
—
26
—
—
9615
—
—
13
—
—
19230
—
—
—
109
—
—
300
—
218
—
—
1201
—
—
109
—
—
2402
—
—
55
—
—
4761
—
—
27
—
—
9699
—
—
—
—
—
—
—
—
—
208
—
—
300
—
—
52
—
—
1201
—
208
—
—
2404
—
—
104
—
—
4807
—
—
52
—
—
9615
—
—
26
—
—
19230
—
—
—
218
—
—
300
—
—
55
—
—
1190
—
218
—
—
2403
—
—
109
—
—
4805
—
—
55
—
—
9523
—
—
27
—
—
19398
—
—
—
—
78
—
—
300
—
78
—
—
1202
—
—
39
—
—
2403
—
156
—
—
4808
—
—
78
—
—
9615
—
—
39
—
—
19230
—
—
—
—
104
—
—
300
—
104
—
—
1202
—
—
52
—
—
2404
—
208
—
—
4808
—
—
104
—
—
9615
—
—
52
—
—
19230
—
—
—
—
109
—
—
300
—
109
—
—
1201
—
—
55
—
—
2381
—
218
—
—
4805
—
—
109
—
—
9610
—
—
55
—
—
19045
—
—
—
—
130
—
—
300
—
130
—
—
1202
—
—
65
—
—
2404
—
—
33
—
—
4735
—
130
—
—
9615
—
—
65
—
—
19231
—
—
fosc
fs/4
fs/16
fosc
fs/4
fs/16
fosc
fs/4
fs/16
fosc
fs/4
fs/16
fosc
fs/4
fs/16
fosc
fs/4
fs/16
fosc
fs/4
fs/16
300 1200 2400 4800 9600 19200
4.19
8.0
8.38
12.0
16.0
16.76
20.0
Set the values from this table
(minus 1) in the compare
register.
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Chapter 5 Serial Functions
106 Serial Interface Control Registers
5-4 Serial Interface Control Registers
5-4-1 Overview
7 registers control the serial interface. See table 5-4-1.
Table 5-4-1 Serial Interface Registers
Name Address R/W Function
SC0MD0 X'03F50' R/W Serial interface 0 mode register 0
SC0MD1 X'03F51' R/W Serial interface 0 mode register 1
SC0MD2 X'03F52' R/W Serial interface 0 mode register 2
SC0MD3 X'03F53' R/W Serial interface 0 mode register 3
SC0CTR X'03F54' R/W Serial interface 0 control register
SC0TRB X'03F55' W Serial interface 0 transmit/receive shift register
SC0RXB X'03F56' R Serial interface 0 receive data buffer
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Chapter 5 Serial Functions
107
Serial Interface Control Registers
5-4-2 Transmit/Receive Shift Registers, Receive Data Buffer
(1) Serial interface 0 transmit/receive shift register (SC0TRB)
This 8-bit, writable register shifts the transmission data and the reception data. The
direction of transfer can be specified as LSB first or MSB first.
Figure 5-4-1 Serial Interface 0 Transmit/Receive Shift Register
(SC0TRB: X'03F55', W)
(2) Serial interface 0 receive data buffer (SC0RXB)
Figure 5-4-2 Serial Interface 0 Receive Data Buffer
(SC0RXB: X'03F56', R)
(at reset: undefined)
01243
SC0TRB
SC0TRB5SC0TRB6SC0TRB7 SC0TRB2SC0TRB3 SC0TRB0SC0TRB1
SC0TRB4
567
(at reset: undefined)
01243
SC0RXB
SC0RXB5SC0RXB6SC0RXB7 SC0RXB2SC0RXB3 SC0RXB0SC0RXB1
SC0RXB4
567
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Chapter 5 Serial Functions
108
5-4-3 Serial Interface Mode Registers
(1) Serial interface 0 mode register (SC0MD0)
Figure 5-4-3 Serial Interface 0 Mode Register 0 (SC0MD0: X'03F50', R/W)
Serial Interface Control Registers
(at reset: -00XX000)
01243
SC0MD0
SC0LNG0SC0LNG1SC0LNG2
SC0LNG0SC0LNG1SC0LNG2
SC0STE
SC0CE1
SC0DIR
SC0CE0
–
567
0
0
1
0
0
18 bit
7 bit
6 bit
5 bit
1
Transfer bit count
0
1
1
0
0
14 bit
3 bit
2 bit
1 bit
1
Receive data
input edge
SC0CE1SC0CE
0
0
1Falling
Rising
Rising Falling
Falling
Rising
Transmit data
output edge
0
1
0
1
0
1Disable start condition
Selection of synchronous
serial start condition
Enable start condition
SC0STE
0
1MSB first
First bit to be transferred
LSB first
SC0DIR
0
1
Rising
Falling
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Chapter 5 Serial Functions
109
Serial Interface Control Registers
(2) Serial interface 0 mode register 1 (SC0MD1)
Figure 5-4-4 Serial Interface 0 Mode Register 1 (SC0MD1: X'03F51', R/W)
01243
(at reset: --X00000)
SC0MD1
SC0ERE
SC0TRI
SC0BRKF
SC0CK0
SC0CKM
SC0CK1
–
–
567
0
1Transmit interrupt request
Transmit/receive
interrupt request flag
Receive interrupt request
SC0TRI
0
1No error
Error monitor
Error
SC0ERE
0
1Data
Break status
receive monitor
Break
SC0BRKF
0
0fs/2
Clock source
fs/4
SC0CK1
0
1
1
1fs/16
BC3×1/2(1/2 of timer 3 overflow)
0
1
SC0CK0
0
1Do not divide by 8
Divide clock frequency by 8
Divide by 8
SC0CKM
An external clock can be selected as the clock
source by setting the SBT0 pin to the input mode.
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Chapter 5 Serial Functions
110 Serial Interface Control Registers
(3) Serial interface 0 mode register 2 (SC0MD2)
Figure 5-4-5 Serial Interface 0 Mode Register 2 (SC0MD2: X'03F52', R/W)
01243
(at reset: --000XXX)
SC0MD2
SC0NPE
Break status transmit control
Data
Break
SC0BRKE
Added bit specification
SC0PM1
SC0PM0SC0PM1SC0FM0SC0FM1
SC0BRKE
––
567
0
1
Parity enable
Parity enabled
Parity disabled
SC0NPE
0
1
Normally add 0
Add even parity
Normally add 1
Add odd parity
0
1
0
0
1
SC0PM0
1
Frame mode specification
SC0FM1
7 data bits + 1 stop bit
8 data bits + 2 stop bits
7 data bits + 2 stop bits
8 data bits + 1 stop bits
0
1
0
0
1
SC0FM0
1
Transmission Reception
Check for 0
Check for 1
Check for odd parity
Check for even parity
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Chapter 5 Serial Functions
111
Serial Interface Control Registers
(4) Serial interface 0 mode register 3 (SC0MD3)
Figure 5-4-6 Serial Interface 0 Mode Register 3 (SC0MD3: X'03F53', R/W)
SBI0 input control
"1" input
Serial input
SC0SBIS
0
1
SBO0 pin function selection
Port
Serial communication
SC0SBOS
0
1
SBT0 pin configuration selection
Push-pull output
N-channel open-drain output
SC0SBTM
0
1
SBT0 pin function selection
Port
Serial clock pin
SC0SBTS
0
1
SBO0 pin configuration selection
Push-pull output
N-channel open-drain output
SC0SBOM
0
1
SBI0/SBO0 pin connection
Unconnected
Connected
SC0IOM
0
1
01243
(at reset: --000000)
SC0MD3
SC0SBTSSC0SBIS
SC0SBOS
SC0SBTMSC0SBOM
SC0IOM
––
567
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Chapter 5 Serial Functions
112
5-4-4 Serial Interface Control Register
(1) Serial interface 0 control register (SC0CTR)
Figure 5-4-7 Serial Interface 0 Control Register (SC0CTR: X'03F54', R)
(R/W available with SC0CMD only)
Serial Interface Control Registers
01243
(at reset: 00XX000X)
SC0CTR
SC0ORE
–
SC0PEKSC0FEF
––
SC0CMD
SC0BSY
567
0
1No Error
Overrun error detection
Error
SC0ORE
0
1No Error
Parity error detection
Error
SC0PEK
0
1No Error
Framing error detection
Error
SC0FEF
0
1Synchronous serial
Synchronous serial/
UART selection
UART
SC0CMD
0
1Other use
Serial bus status
Serial transmission in progress
SC0BSY
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Chapter 6 A/D Conversion Functions
114 Overview
6-1 Overview
The MN101C117 has an internal A/D converter with 10-bit resolution. A
sample-and-hold circuit is contained on-chip and software can switch the
analog input between channels 0 to 7 (AN0 to AN7).
When the A/D converter is stopped, power consumption can be reduced by
turning off the internal ladder resistors.
Figure 6-1-1 A/D Converter Block Diagram
MUX
MUX
Upper 8 bits of A/D
conversion data
Lower 2 bits of A/D conversion data
Sample & hold
A/D conversion
control
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
VSS
fs/2
fs/4
fs/8
VDD
ANCHS0
ANCHS1
ANCHS2
ANLADE
ANCK0
ANCK1
ANSH0
ANSH1
ANBUF10
ANBUF11
ANBUF12
ANBUF13
ANBUF14
ANBUF15
ANBUF16
ANBUF17 ANBUF06
ANBUF07
ANST
MUX
1/18
3
22
10-bit
A/D comparator
ANCTR0
ANCTR1
ANBUF1 ANBUF0
0
7
0
7
0
7
0
7
–
–
–
–
–
–
–
–
–
–
–
–
–
1/6
1/2
fx x 2
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Chapter 6 A/D Conversion Functions
115
A/D Conversion
6-2 A/D Conversion
The procedures for operating the A/D conversion circuit are listed below.
(1) Set the ANCHS2 to ANCHS0 flags of A/D control register 0 (ANCTR0) to specify one
of pins AN7 to AN0 (PA7 to PA0) as the analog input.
(2) Set the ANCK1 and ANCK0 flags of A/D control register 0 to select the A/D
conversion clock. Make this setting such that the period of the conversion clock
(TAD), which is based on the oscillator, is greater than 800ns.
(3) With the ANSH1 and ANSH0 flags of A/D control register 0, set the sample-and-hold
time. Select a value for the sample and hold time that is suitable for the analog input
impedance.
(4) Set the ANLADE flag of A/D control register 0 to "1" so that current flows through
the ladder resistors and the A/D converter is on standby.
Note: Steps 1 to 4 above may performed all at the same time.
(5) Set the ANST flag of A/D control register 1 (ANCTR1) to "1" to start the A/D
conversion.
(6) After the sample-and-hold time set in step 3, the sampled A/D conversion data is
sequentially compared to determine its value beginning with the MSB.
(7) When the A/D conversion is complete, the ANST bit is cleared to "0" and conversion
results are stored in A/D buffers (ANBUF0, 1). At the same time, an A/D complete
interrupt request (ADIRQ) is generated.
Figure 6-2-1 A/D Conversion Timing
Start the A/D conversion after the
current flowing through the ladder
resistors stabilizes. The time
constant calculated time from the
ladder resistance (max. 80 k
Ω
)
and the external bypass capacitor
connected between V
dd
and V
ss
should be used as the criteria for
the wait time.
TAD 1~2 3 4 12
ANST A/D conversion start
TS
Hold
Sampling
Bit 9
comparison Bit 8
comparison Bit 0
comparison
Determine
bit 1 value
Determine
bit 8 value
Determine
bit 9 value
A/D interrupt
Determine
bit 0 value
A/D conversion complete
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Chapter 6 A/D Conversion Functions
116 A/D Converter Control Registers
The following items must be implemented to maintain the accuracy of the
A/D converter:
1. Use a maximum input pin impedance, R, of 500kΩ∗1with an external
capacitor, C, that is minimum 1,000pF and maximum 1µF∗1.
2. Take the RC time into consideration when setting the A/D conversion
interval.
3. Changing the output level of the microcomputer or switching peripheral
circuitry on or off when the A/D converter is in use may cause the
analog input pin or current pin to fluctuate resulting in a loss of
precision. During setup and evaluation, verify the waveform of the
analog input pin.
∗1 These values are reference values.
Figure 6-2-2 Recommended Circuit When Using A/D Conversion
Equivalent circuit of
analog signal output
R
1 µF≥C≥1000pF
where R≤500kΩ
Vss
C
A/D input pin
Microcomputer
∗1
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117
Chapter 6 A/D Conversion Functions
A/D Converter Control Registers
6-3 A/D Converter Control Registers
6-3-1 Overview
Four registers control the A/D converter. See table 6-3-1.
Table 6-3-1 A/D Converter Control Registers
Name Address R/W Function
ANCTR0 X'03F90' R/W A/D control register 0
ANCTR1 X'03F91' R/W A/D control register 1
ANBUF0 X'03F92' R A/D buffer 0
ANBUF1 X'03F93' R A/D buffer 1
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Chapter 6 A/D Conversion Functions
118 A/D Converter Control Registers
6-3-2 A/D Control Register (ANCTR)
This readable and writable 8-bit register controls the operation of the A/D
converter.
(1) A/D control register 0 (ANCTR0)
∗1:Specify that where the period of the A/D conversion clock
is greater than 800ns.
∗2:Sample-and-hold time is determined by the analog input
impedance. TAD indicates the period of the A/D conversion
clock.
Figure 6-3-1 A/D Control Register 0 (ANCTR0: X'03F90', R/W)
0
1
0
1
0
1
A/D conversion
clock selection∗1
0
0
1
0
0
1
1
Analog input selection
01245673
ANCTR0
ANCHS0ANCHS1ANCHS2
ANCHS0ANCHS1ANCHS2
ANLADE
ANLADE
ANCK0
ANCK1
ANCK0ANCK1
ANSH1 ANSH0
ANSH0ANSH1
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
0
1
1
0
0
1
1
0
1
A/D ladder resistor control
A/D ladder resistors off
A/D ladder resistors on
fs/2
fs/4
fs/8
Use prohibited
0
1
0
1
0
1
Sample and
hold time setting∗2
TAD × 2
TAD × 6
TAD × 18
Use prohibited
(at reset: XXXX0XXX)
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Chapter 6 A/D Conversion Functions
119
A/D Converter Control Registers
(2) A/D conversion control register 1 (ANCTR1)
Figure 6-3-2 A/D Control Register 1 (ANCTR1: X'03F91', R/W)
A/D conversion status
01243
ANST
ANCTR1
567
(at reset: 0-------)
0
1
A/D conversion completed or stopped
A/D conversion started or in progress
ANST
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Chapter 6 A/D Conversion Functions
120 A/D Converter Control Registers
6-3-3 A/D Buffers (ANBUF)
These read-only registers store the A/D conversion results.
(1) A/D buffer 0 (ANBUF0)
This register stores the lower 2 bits of the A/D conversion results.
Figure 6-3-3 A/D Buffer 0 (ANBUF0: X'03F92', R)
(2) A/D buffer 1 (ANBUF1)
This register stores the upper 8 bits of the A/D conversion results.
Figure 6-3-4 A/D Buffer 1 (ANBUF1: X'03F93', R)
01245673
ANBUF0
ANBUF07 ANBUF06
(at reset: XX------)
01245673
ANBUF1
ANBUF17 ANBUF16 ANBUF15 ANBUF14 ANBUF13 ANBUF12 ANBUF11 ANBUF10
(at reset: XXXXXXXX)
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Chapter 7 AC Zero-Cross Circuit/Noise Filter
122 Overview
7-1 Overview
The P21/SENS pin is the input pin for the AC zero-cross detection circuit.
The AC zero-cross detection circuit outputs a high level when the input is at
an intermediate level, and a low level at all other times.
AC zero-cross
detection circuit P21 input/IRQ1
to noise filter
(See figure 7-3-1.)
MUX
P21/IRQ1/SENS
FLOAT1
0
7
P7RDWN
PARDWN
–
–
–
–
–
P21IM
Figure 7-1-1 P21 Input Circuit Block Diagram
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Chapter 7 AC Zero-Cross Circuit/Noise Filter
123
AC Zero-Cross Circuit Operation
7-2 AC Zero-Cross Circuit Operation
7-2-1 Setup and Operation
Settings for zero-cross circuit operation are listed below.
(1) Set the REDG1 flag of the IRQ1ICR register to select the valid edge for IRQ1.
(2) Set the NF1EN and NF1CK1 to 0 flags of the NFCTR register to set the noise filter
and its sampling clock.
(3) With the P21IM flag of the FLOAT1 register, set the P21 pin to zero-cross
detection.
(4) An IRQ1 interrupt is generated by the falling edge or the rising edge of AC
zero-cross detection output.
Actual IRQ interrupt requests will be generated multiple times. Therefore, the software must
filter this signal before making any evaluations.
When noise filtering is selected for use, the amount of evaluation processing by the software
will be reduced. However, if the OSC stops, a return from the backup mode will not be
possible.
VDD
VSS
AC line waveform
Point A
Ideal
IRQ1
Actual
IRQ1
10 ms at 50Hz
8.3 ms at 60Hz
Figure 7-2-1 AC Line Waveform and IRQ Generation Timing
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Chapter 7 AC Zero-Cross Circuit/Noise Filter
124
7-3 Noise Filter
7-3-1 Overview
External interrupt pins IRQ0 and IRQ1 contain noise filtering circuit. This
circuitry can be used for remote control signal reception.
Figure 7-3-1 Noise Filtering Circuit Block Diagram
Noise Filter
Data bus
NFCTR
NF1EN
NF1CKS0
fs/28
fs/22
fs/29
fs/210
MUX
Noise filter
To IRQ0
interrupt
P20/IRQ0
MUX
NF0CKS1
NF0CKS0
NF0EN
NF1CKS1
2
2
MUX
Noise filter
To IRQ1
interrupt
P21/IRQ1/SENS
MUX
0
7
fs/28
fs/22
fs/29
fs/210
AC zero-cross
circuit
(Fig.7-1-1)
IRQ0: External interrupt 0
IRQ1: External interrupt 1
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Chapter 7 AC Zero-Cross Circuit/Noise Filter
125
Noise Filter
7-3-2 Example Input and Output W aveforms for Noise Filter
When the noise filter is used, the waveform input to the IRQ0 pin is sampled based on the
clock specified by the NF0CKS0 and NF0CKS1 flags of the noise filter control register
(NFCTR). The waveform input to the IRQ1 pin is also sampled based on the clock specified
by the NF1CKS0 and NF1CKS1 flags. If the sampled level remains the same for 3
consecutive samples, it is sent the CPU; otherwise, the previous level is maintained.
Figure 7-3-2 Noise Filter Input and Output Waveform Example
Noise filtering cannot be
used in the STOP or HALT
modes.
Sampling
Input
Waveform after
noise filtering
001111100
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Chapter 7 AC Zero-Cross Circuit/Noise Filter
126
[☞2-4-3 "Interrupt Control
Registers ■External Interrupt
Control Registers"]
[☞3-2-2 "I/O Port Control
Registers ■Pin Control
Registers"]
7-4 AC Zero-Cross Control Register
7-4-1 Overview
Four registers control the AC zero-cross circuit.
Table 7-4-1 AC Zero-Cross Control Register
AC Zero-Cross Control Register
Name Address R/W Function
IRQOICR X'03FE2' R/W External interrupt control register 0
IRQ1ICR X'03FE3' R/W External interrupt control register 1
FLOAT1 X'03F4B' R/W Pin control register 1
NFCTR X'03F8A' R/W Noise filter control register
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Chapter 7 AC Zero-Cross Circuit/Noise Filter
127
AC Zero-Cross Control Register
7-4-2 Noise Filter Control Register (NFCTR)
This 6-bit readable and writable register controls the noise filter.
Figure 7-4-1 Noise Filter Control Register (NFCTR: X'03F8A', R/W)
0
1
0
1
0
1
IRQ1 noise filter
sampling period selection
01245673
NFCTR
NF0ENNF0CKS0NF0CKS1
NF1EN
NF1EN
NF1CKS0NF1CKS1
NF1CKS0NF1CKS1
––
0
1
IRQ1 noise filter setup and operation
IRQ1 noise filter off
IRQ1 noise filter on
(at reset: --000000)
NF0EN
0
1
IRQ0 noise filter setup and operation
IRQ0 noise filter off
IRQ0 noise filter on
0
1
0
1
0
1
IRQ0 noise filter
sampling period selection
NF0CKS0NF0CKS1
fs/2
fs/2
fs/2
fs/2
2
8
9
10
fs/2
fs/2
fs/2
fs/2
2
8
9
10
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Chapter 7 AC Zero-Cross Circuit/Noise Filter
128
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Chapter 8 Appendices
130
EPROM Versions
8-1 EPROM Versions
8-1-1 Overview
EPROM version is microcomputer which was replaced with the mask ROM
of the MN101C11 with an electronically programmable 16-KB EPROM.
Because the MN101CP117**(**=DP,BF,HP) is sealed in plastic, once data
is written to the internal PROM it cannot be erased.
Because the PX-AP101C11-SDC and PX-AP101C11-FBC are sealed in a
ceramic package that has a window, written data can beerased by
illumination with ultraviolet light. Plastic package uses a 42-pin shrink DIL
package, 44-pin flat package, and 48-pin flat package. Ceramic packages
uses a 42-pin shrink DIL package and 44-pin flat package.
Setting the EPROM version to EPROM mode, halts microcomputer
functions, and the internal EPROM can be programmed. Refer to the
EPROM mode pin diagram in figure 9-4-3 to 5.
The specification for writing to the internal EPROM are the same as for a
general-purpose 256Kbit EPROM(Vpp=12.5V, tpw=0.2ms). Therefore,
by replacing theEPROM Version's 42-pin socket with a special 28-pin
socket adapter(supplied by Panasonic) having the same configuration as a
normal EPROM, a general-purpose EPROM writer can be
used to perform read and write operations.
The EPROM Version is described on the following items:
- Cautions on use of the internal EPROM
- Erasing written Data in Windowed Package(PX-AP101C11-SDC, PX-
AP101C11-FBC)
- Characteristics of EPROM Versions
- Writing to the Microcomputer with Internal EPROM
- Cautions on operating a ROM writer
- Option bit
- Connections of a writing adaptor.
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8-1-2 Cautions on Use
EPROM Versions differs from the MN101C11* in some of its electrical
characteristics. The user should be aware of these differences.
(1) To prevent data from being erased by ultraviolet light after a program is
written, affix seals impermeable to UV rays to the glass sections at the
top and side sections of the CPU.
(PX-AP101C11-SDC, PX-AP101C11-FBC)
(2) Due to device characteristics of the MN101CP11XXX, a writing test
cannot be performed on all bits. Therefore, storage of the written data
cannot be guaranteed in some cases.
(3) When a program is written, verify that Vc power supply(6V) is connected
before applying the Vpp power supply(12.5V). Disconnect the Vpp
supply before disconnecting the Vcc supply.
(4) Vpp should never exceed 13.5V including overshoot.
(5) If a device is removed while a Vpp of +12.5V is applied, device reliability
may be damaged.
(6) At CE=VIL, do not change Vpp from VIL to +12.5V or from +12.5V to
VIL.
(7) From the time after a program is written until just before mounting,
storage at a high temperature is recommended.
Program/Read
High temperature storage
125°C - 48H
Read
Mounting
Chapter 8 Appendices
131
EPROM Versions
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Chapter 8 Appendices
132
EPROM Versions
8-1-3 Erasing Written Data in Windowed Packages
In an internal EPROM with windowed packaging, data is erased("0" →"1")
when UV light at 253.7nm permeates the window to irradiate the chip.
The recommended exposure is 10W · s/cm2. This coverage can be achieved
by using a commercial UV lamp positioned 2 to 3cm above the package for
15-20 minutes(when the illumination intensity of the package surface
is12000µW/cm2). Remove any filters attached to the lamp. By installing a
mirrored reflector plate in the lamp, illumination intensity will increase by
afactor of 1.4 to 1.8, decreasing the erasure time.
If the window becomes dirty with oil, adhesive, etc., UV light permeability will
decrease, causing the erasure time to increase considerably. If this
happens, clean with alcohol or another solvent that will not harm the
package. The recommended above provides sufficient leeway, with several
times the amount of time it takes to erase all the bits. However, this value
will reliably erase data over all temperature and voltage ranges, and should
not be altered. The level of illumination should be regularly checked and the
lamp operation verified.
Erasure begins when EPROM is exposed to light with a wavelength shorter
than 400nm. Since fluorescent light and sunlight have wavelengths in this
range, exposure to these light sources for extended periods of time could
cause inadvertant erasure. To prevent this, cover the window with an
opaque label.
Data is not erased at wavelengths longer than 400 to 500nm. However,
because of typical semiconductor characteristics, the circuit may
malfunction if the chip is exposed to an extremely high illumination intensity.
The chip will operate normally if this exposure is stopped. However, for
areas where it is continuous, take necessary precautions.
(PX-AP101C11-SDC, PX-AP101C11-FBC)
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Chapter 8 Appendices
133
EPROM Versions
8-1-4 Characteristics of EPROM Version
The MN101C11*(mask ROM version) and the Microcomputer with internal
EPROM version have the following differences.
Table 8-1-1 Difference between MN101C*(Mask ROM version) and
Internal EPROM version)
There are no other functional differences.
MN101C11＊（ROM ver.）
-40 to 85℃ Internal EPROM version
-20 to 85℃
Operating voltage 4.5 to 5.5V（0.1μs/20MHz）
2.7 to 5.5v（0.25μs/8MHz）    
2.0 to 5.5v（1.00μs/2MHz）
4.5 to 5.5V（0.1μs/20MHz）
2.7 to 5.5v（0.25μs/8MHz）
2.7 to 5.5v（1.00μs/2MHz）
Pin DC characteristics Output current,input current and input judge level are the same.
ROM option EPROM option
Hi-speed,low-speed oscilla-
tion start control,runaway
detection period settup
Package selection
Internal ROM final address data
be used as option data.
(Final address =X'07FFF)
EPROM final address data be
used as option data.
(Final address=X'07FFF)
Operating temperature
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8-1-5 Writing to Microcomputer with Internal EPROM
■ Fit in the writing adapter and position the No.1 pin.
Figure 8-1-1 Mount on the writing adapter and position of No.1 pin.
Chapter 8 Appendices
134
EPROM Versions
1
2
39
40
No.1 pin must be matched to
this position.
*The socket of an adapter
varies according to the
package types.
Package type Product name
OTP42SD-101CP11
OTP44QF14-101CP11
OTP48FH7-101CP11
42-SDIP
44-QFP
48-QFH
No.1Pin
2.297
0.127
No.1 Pin
No.1 Pin
No.1 Pin
(MN101CP117BF) (MN101CP117HP)
(MN101CP117DP)
(PX-AP101C11-SDC) (top view) (PX-AP101C11-FBC) (side view)
(top view)
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Chapter 8 Appendices
135
EPROM Versions
■ ROM writer Selection
The device names should be set up as listed below.
Table 8-1-2 Device selection
The above settings are based on the standard samples.
When you use the other equipment than the ones listed, contact the
nearest semiconductor design center.(Refer to the sales office table
attached at the end of the manual.)
Pecker 30 Avarl Data
1890A Minato Electronics
Equip. name
Lab Site Data I/O
Vendor Device name Remarks
Hitachi 27C256
Hitachi 27C256
Hitachi 27C256 Do not run ID check and
pin connection inspection.
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Chapter 8 Appendices
136
EPROM Versions
8-1-6
Cautions on Operating the ROM Writer
■ Cautions on operating the ROM writer
(1)The Vpp programming voltage for the EPROM versions is 12.5V.
Programming with a 21-volt ROM writer can lead to damage. The ROM
writer specifications must match those for standard 1-megabit
EPROMS:Vpp=12.5V V;tpw=0.2ms.
(2)Make sure that the socket adapter matches the ROM writer socket and
that the chip is correctly mounted in the socket adapter. Faulty
connections can lead to damage.
(3)After clearing all memory of the ROM writer, load the program.
(Write the data X'FF' on the address X'0000' to X'7FFF'.)
(4)After confirming the device name, write the addresses from the start to
the final address.
(5)The option bits for supporting the mask option are prepared at the final
ROM address.
This writer has no internal ID codes of Silicon Signature and Intelligent
Identifier of the auto-device selection command of ROM writer. If the
auto-device selection command is to be executed for this writer, the
device is likely damaged. Therefore, never use this command.
■ When disabling the writing
When disabling the writing, check the following points.
(1)Check that the device is mounted correctly on the socket.(pin bending,
connecting failure).
(2)Check that the erase check result is no problem.
(3)Check that the adapter type is identical to the device name.
(4)Check that the writing mode is set correctly.
(5)Check that the data is correctly transferred to the ROM writer.
(6)Recheck the check points (1),(2) and (3) provided on the above
paragraph of ìCautions on Handling the ROM writerî.
When the writing is disabled even after the above check points are
confirmed and the device is replaced with another one, contact the
nearest semiconductor design center.
(See the attached sales office table.)
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Chapter 8 Appendices
137
EPROM Versions
8-1-7 Option Bit
The MN101C117 and the MN101CP117 control the oscillation mode after resetting
as well as the runaway-detection watch dog timer, using bit 2 to 0 of the last address
(X'7FFF) of the built-in ROM.
■
Option bit
Fig. 8-1-2 Option bit(Address: X'07FFF')
01245673
0
1Slowmode
Selectionofoscillationmode
afterresetting
NORMALmode
NSSTRT
WDSEL2 WDSEL1
PKGSEL2 PKGSEL1
NSSTRT
0
1
fs/2
Watchdogtimercyclesetting
fs/2
WDSEL2WDSEL1
0
1
Xfs/2
16
18
20
0
1
SDIP042-P-0600
QFP044-P-1010
QFH048-P-0707
Package
PKGSEL2PKGSEL1
X
0
1
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Chapter 8 Appendices
138
EPROM Versions
8-1-8 Writing Adapter Connection
Package Code SDIP042-P-0600
Fig. 8-1-3 MN1-1CP117-DP(DC)EPROM Writing Adapter Connections
VSS
VSS
NOE
VSS
A14
VSS
VSS
VSS
VSS
VPP
VSS
NCE
A0
A1
A2
A3
A4
A5
A6
A7
VSS
VSS
VSS
VSS
VCC
VSS
VSS
A13
A12
A11
A10
A9
A8
D0
D1
D2
D3
D4
D5
D6
D7
VCC
MN101CP117
４２-ＳＤＩＰ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P00
P01
P02
P06
P10
P11
P12
P13
P14
P20
P21
P22
P60
P61
P62
P63
P64
P65
P66
P67
NRST
VSS
OSC1
OSC2
VDD
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
P80
P81
P82
P83
P84
P85
P86
P87
MMOD
Refer to the pin connection drawing of the 256-bit
EPROM(27C256).
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Chapter 8 Appendices
139
EPROM Versions
Package code: QFP044-P-1010
Pin pitch: 0.8mm
Fig. 8-1-4 MN101CP117-BL(BC)EPROM Writing Adapter Connections
MN101CP117
４４-ＱＦＰ
D3
D2
D1
D0
A8
A9
A10
A11
A12
A13
VSS
A3
A2
A1
A0
NCE
VSS
VPP
VSS
VSS
VSS
VSS
D4
D5
D6
D7
VDD
VSS
VSS
A7
A6
A5
A4
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
NOE
VSS
A14
1
2
3
4
5
6
7
8
9
10
11 23
24
25
26
27
28
29
30
31
32
33
P83
P82
P81
P80
PA6
PA0
PA1
PA2
PA3
PA4
PA5
P63
P62
P61
P60
P11
P22
P21
P20
P14
P13
P12
P66
P65
P67
P70
MMOD
P87
P86
P85
NRST
P64
P84
P00
P01
P02
NC
VSS
OSC2
VDD
OSC1
PA7
P06
P10
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
Refer to the pin connection drawing of the 256-bit
EPROM(27C256).
www.DataSheet4U.com
Chapter 8 Appendices
140
EPROM Versions
Package code: QFH048-P-0707
Pin pitch: 0.5mm
Fig. 8-1-5 MN101CP117-HP EPROM Writing Adapter connections
P83
P82
P81
P80
NC
PA6
PA0
PA1
PA2
PA3
PA4
PA5
P63
P62
P61
P60
P11
P23
P22
P21
P20
P14
P13
P12
MN101CP117
P66
P65
P67
P70
NRST
MMOD
P87
P86
P85
P71
P64
P00
P01
P02
XO
VSS
XI
OSC2
VDD
OSC1
PA7 P84
P10
P06
４８-ＱＦＨ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
25
26
27
28
29
30
31
32
33
34
35
36
D3
D2
D1
D0
A8
A9
A10
A11
A12
A13
VSS
A3
A2
A1
A0
VSS
NCE
VSS
VPP
VSS
VSS
VSS
VSS
D4
D5
D6
D7
VDD
VSS
VSS
VSS
A7
A6
A5
A4
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
NOE
VSS
A14
Refer to the pin connection drawing of the 256-bit
EPROM(27C256).
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Chapter 10 Appendices
141
Instruction Set
8-2 Instruction Set
MN101C00 SERIES INSTRUCTION SET
Group
Data move instructions
Mnemonic Operation Affected Flag
VF NF CF ZF
Code
Size
Cycle
Re-
peat Machine Code
Notes
Page
1234567891011Expand
MOV
––––21 25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
47
47
48
48
49
49
50
50
51
51
52
52
53
53
54
1010 DnDm
MOV
imm8,Dm
imm8→Dm ––––42 1010DmDm <#8. ...>
MOV
Dn,PSW
Dn→PSW 33 1001 01Dn0010
MOV
PSW,Dm
PSW→Dm ––––32 0001 01Dm0010
MOV
(An),Dm
mem8(An)→Dm ––––22 0100 1ADm
MOV
(d8,An),Dm
mem8(d8+An)→Dm ––––42 0110 1ADm <d8. ...>
MOV
(d16,An),Dm
mem8(d16+An)→Dm ––––74 0110 1ADm <d16 .... .... ...>0010
MOV
(d4,SP),Dm
mem8(d4+SP)→Dm ––––32 0110 01Dm <d4>
MOV
(d8,SP),Dm
∗1
∗2
∗3
mem8(d8+SP)→Dm ––––53 0110 01Dm <d8. ...>0010
MOV
(d16,SP),Dm
mem8(d16+SP)→Dm ––––74 0110 00Dm <d16 .... .... ...>0010
MOV
Dn,(io8)
Dn→mem8(IOTOP+io8) ––––42 0111 00Dn <io8 ...>
MOV
Dn,(abs8)
Dn→mem8(abs8) ––––42 0101 01Dn <abs 8..>
MOV
Dn,(abs12)
Dn→mem8(abs12) ––––52 0101 00Dn <abs 12.. ...>
MOV
Dn,(abs16)
Dn→mem8(abs16) ––––74 1101 00Dn <abs 16.. .... ...>0010
MOV
imm8,(io8) imm
8→mem8(IOTOP+io8) ––––63 0000 0010 <io8 ...> <#8. ...>
MOV
imm8,(abs8) imm
8→mem8(abs8) ––––63 0001 0100 <abs 8..> <#8. ...>
MOV
imm8,(abs12) imm
8→mem8(abs12) ––––73 0001 0101 <abs 12.. ...> <#8. ...>
MOV
imm8,(abs16) imm
8→mem8(abs16) ––––95 1101 1001 <abs 16.. .... ...> <#8. ...>0011
MOV
Dn,(HA)
Dn→mem8(HA) ––––22 1101 00Dn
MOV
W
(abs16),DWm
mem16(abs16)→DWm ––––75 1100 011d <abs 16.. .... ...>0010
MOV
W
(abs16),Am
mem16(abs16)→Am ––––75 1100 010a <abs 16.. .... ...>0010
MOV
W
DWn,(Am)
DWn→mem16(Am) ––––23 1111 00aD
MOV
W
An,(Am) ∗4
An→mem16(Am) ––––34 1111 10aA0010
MOV
W
DWn,(d4,SP)
DWn→mem16(d4+SP) ––––33 1111 011D <d4>
MOV
W
An,(d4,SP)
An→mem16(d4+SP) ––––33 1111 010A <d4>
MOV
W
DWn,(d8,SP)
DWn→mem16(d8+SP) ––––54 1111 011D <d8. ...>0010
MOV
W
An,(d8,SP)
∗2
∗2
∗3
∗3
An→mem16(d8+SP) ––––54 1111 010A <d8. ...>0010
MOV
W
DWn,(d16,SP)
DWn→mem16(d16+SP) ––––75 1111 001D <d16 .... .... ...>0010
MOV
W
An,(d16,SP)
An→mem16(d16+SP) ––––75 1111 000A <d16 .... .... ...>0010
MOV
W
DWn,(abs8)
DWn→mem16(abs8) ––––43 1101 011D <abs 8..>
MOV
W
An,(abs8)
An→mem16(abs8) ––––43 1101 010A <abs 8..>
MOV
W
DWn,(abs16)
DWn→mem16(abs16) ––––75 1101 011D <abs 16.. .... ...>0010
MOV
W
An,(abs16)
An→mem16(abs16) ––––75 1101 010A <abs 16.. .... ...>0010
MOV
W
DWn,(HA)
DWn→mem16(HA) ––––23 1001 010D
MOV
W
An,(HA)
An→mem16(HA) ––––23 1001 011A
MOVW
imm8,DWm
sign(imm8)→DWm ––––42 0000 110d <#8. ...>
MOVW
imm8,Am
∗5
∗6
∗1 d8 sign extended
∗2 d4 zero extended
∗3 d8 zero extended
∗4 A=An, a=Am
∗5 #8 sign extended
∗6 #8 zero extended
zero(imm8)→Am ––––42 0000 111a <#8. ...>
MOVW
imm16,DWm
imm16→DWm ––––63 1100 111d <#16 .... .... ...>
MOV
W
(An),DWmMOV
W mem16(An)→DWm ––––23 1110 00Ad
MOV
W
(An),Am
mem16(An)→Am ––––34 1110 10Aa0010
MOV
W
(d4,SP),DWm
mem16(d4+SP)→DWm ––––33 1110 011d <d4>
MOV
W
(d4,SP),Am
mem16(d4+SP)→Am ––––33 1110 010a <d4>
MOV
W
(d8,SP),DWm
mem16(d8+SP)→DWm ––––54 1110 011d <d8. ...>0010
MOV
W
(d8,SP),Am
∗4
∗2
∗2
∗3
∗3
mem16(d8+SP)→Am ––––54 1110 010a <d8. ...>0010
MOV
W
(d16,SP),DWm
mem16(d16+SP)→DWm ––––75 1110 001d <d16 .... .... ...>0010
MOV
W
(d16,SP),Am
mem16(d16+SP)→Am ––––75 1110 000a <d16 .... .... ...>0010
MOV
W
(abs8),DWm
mem16(abs8)→DWm ––––43 1100 011d <abs 8..>
MOV
W
(abs8),Am
mem16(abs8)→Am ––––43 1100 010a <abs 8..>
MOV
(io8),Dm
mem8(IOTOP+io8)→Dm ––––42 0110 00Dm <io8 ...>
MOV
(abs8),Dm
mem8(abs8)→Dm ––––42 0100 01Dm <abs 8..>
MOV
(abs12),Dm
mem8(abs12)→Dm ––––52 0100 00Dm <abs 12.. ...>
MOV
(abs16),Dm
mem8(abs16)→Dm ––––74 1100 00Dm <abs 16.. .... ...>0010
MOV
Dn,(Am)
Dn→mem8(Am) ––––22 0101 1aDn
MOV
Dn,(d8,Am)
Dn→mem8(d8+Am) ––––42 0111 1aDn <d8. ...>
MOV
Dn,(d16,Am)
Dn→mem8(d16+Am) ––––74 0111 1aDn <d16 .... .... ...>0010
MOV
Dn,(d4,SP)
Dn→mem8(d4+SP) ––––32 0111 01Dn <d4>
MOV
Dn,(d8,SP)
∗1
∗2
∗3
Dn→mem8(d8+SP) ––––53 0111 01Dn <d8. ...>0010
MOV
Dn,(d16,SP)
Dn→mem8(d16+SP) ––––74 0111 00Dn <d16 .... .... ...>0010
MOV
Dn,Dm
Dn→Dm
Note: "Page" refers to the corresponding page in the Instruction Manual.
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Chapter 10 Appendices
142 Instruction Set
MN101C00 SERIES INSTRUCTION SET
Group Mnemonic Operation Affected Flag
VF NF CF ZF
Code
Size Cycle
Re-
peat Machine Code
Notes
Page
1234567891011Expand
PUSH
Dn
PUSH SP-1→SP,Dn→mem8(SP) ––––23 1111 10Dn
PUSH
An
SP-2→SP,An→mem16(SP) ––––25 0001 011A
POP
Dn
POP mem8(SP)→Dn,SP+1→SP ––––23 1110 10Dn
POP
An
mem16(SP)→An,SP+2→SP ––––24 0000 011A
EXT
Dn,DWm
EXT sign(Dn)→DWm ––––33 1001 000d0010
Arithmetic instructions
ADD
Dn,Dm
ADD Dm+Dn→Dm 32 0011 DnDm0011
ADD
imm4,Dm
Dm+sign(imm4)→Dm 32 1000 00Dm <#4>
ADD
imm8,Dm
Dm+imm8→Dm 42 0000 10Dm <#8. ...>
ADDC
Dn,Dm
ADDC Dm+Dn+CF→Dm 32 1011 DnDm0011
ADDW
DWn,DWm
ADDW DWm+DWn→DWm 33 0101 00Dd0010
ADDW
DWn,Am
Am+DWn→Am 33 0101 10Da0010
ADDW
imm4,Am
Am+sign(imm4)→Am 32 1110 110a <#4>
ADDW
imm8,Am
Am+sign(imm8)→Am 53 1110 110a <#8. ...>0010
ADDW
imm16,Am
Am+imm16→Am 74 0101 011a <#16 .... .... ...>0010
ADDW
imm4,SP
SP+sign(imm4)→SP ––––32 1111 1101 <#4>
ADDW
imm8,SP
SP+sign(imm8)→SP ––––42 1111 1100 <#8. ...>
ADDW
imm16,SP
SP+imm16→SP ––––74 1111 1100 <#16 .... .... ...>0010
ADDW
imm16,DWm
DWm+imm16→DWm 74 0101 010d <#16 .... .... ...>0010
ADDUW
Dn,Am
ADDUW Am+zero(Dn)→Am 33 1000 1aDn0010
ADDSW
Dn,Am
ADDSW Am+sign(Dn)→Am 33 1001 1aDn0010
SUB
Dn,Dm(when Dn≠Dm)
SUB Dm-Dn→Dm 32 1010 DnDm0010
SUB
Dn,Dn
Dn-Dn→Dn 000121 1000 01Dn
SUB
imm8,Dm
Dm-imm8→Dm 53 1010DmDm <#8.0010
SUBC
Dn,Dm
SUBC Dm-Dn-CF→Dm 32 1011 DnDm0010
SUBW
DWn,DWm
SUBW DWm-DWn→DWm 33 0100 00Dd0010
SUBW
DWn,Am
Am-DWn→Am 33 0100 10Da0010
SUBW
imm16,DWm
DWm-imm16→DWm 74 0100 010d <#16 .... .... ...>0010
SUBW
imm16,Am
Am-imm16→Am 74 0100 011a <#16 .... .... ...>0010
MULU
Dn,Dm
MULU Dm∗Dn→DWk 038 1111 111D0010
DIVU
Dn,DWm
DIVU DWm/Dn→DWm-I...DWm-h 39 1110 111d0010
MOVW
imm16,Am
imm16→Am ––––63 54
55
55
56
56
57
57
58
58
59
59
60
61
61
62
63
64
64
65
65
66
66
67
67
68
69
70
71
71
72
73
74
74
75
75
76
77
1101 111a <#16 .... .... ...>
MOVW
SP,Am
SP→Am ––––33 0000 100a0010
MOVW
An,SP
An→SP ––––33 0000 101A0010
MOVW
DWn,DWm
DWn→DWm ––––33 1000 00Dd0010
MOVW
DWn,Am
DWn→Am ––––33 0100 11Da0010
MOVW
An,DWm
An→DWm ––––33 1100 11Ad0010
MOVW
An,Am
An→Am ––––33 0000 00Aa0010
○
∗3
∗6
∗1
∗6
∗7
∗6
∗7
∗8
∗1
∗4
∗5 
∗1
∗1 D=DWn, d=DWm
∗2 A=An, a=Am
∗3 d=DWm
∗4 D=DWk
∗5 D=DWm
∗6 #4 sign extended
∗7 #8 sign extended
∗8 Dn zero extended
CMP
Dn,Dm
CMP Dm-Dn...PSW 32 0010 DnDm0011
CMP
imm8,Dm
Dm-imm8...PSW 42 1100 00Dm <#8. ...>
CMP
imm8,(abs8)
mem8(abs8)-imm8...PSW 63 0000 0100 <abs 8..>
78
78
79
CMP
imm8,(abs12)
mem8(abs12)-imm8...PSW 73 79
80
81
81
82
82
83
0000 0101 <abs 12.. ...> <#8. ...>
CMP
imm8,(abs16)
mem8(abs16)-imm8...PSW 95 1101 1000 <abs 16.. .... ...> <#8. ...>0011
CMPW
DWn,DWm
CMPW DWm-DWn...PSW 33 1000 01Dd0010
CMPW
DWn,Am
Am-DWn...PSW 33 0101 11Da0010
CMPW
An,Am
∗1
∗2
Am-An...PSW 33 0000 01Aa0010
CMPW
imm16,DWm
DWm-imm16...PSW 63 1100 110d <#16 .... .... ...>
CMPW
imm16,Am
Am-imm16...PSW 63 1101 110a <#16 .... .... ...>
Logical instructions
AND
Dn,Dm
AND Dm&Dn→Dm 0032 0111 DnDm0011
AND
imm8,Dm
Dm&imm8→Dm 0042 0001 11Dm <#8. ...>
AND
imm8,PSW
PSW&imm8→PSW 53 1001 0010 <#8. ...>0010
OR
Dn,Dm
OR DmIDn→Dm 0032 0110 DnDm0011
OR
imm8,Dm
DmIimm8→Dm 0042 0001 10Dm <#8. ...>
OR
imm8,PSW
PSWIimm8→PSW 53 1001 0011 <#8. ...>0010
XOR
Dn,Dm
XOR Dm^Dn→Dm 0032 1010 DnDm0011
XOR
imm8,Dm
Dm^imm8→Dm 0053 1010DmDm <#8. ...>0011
84
84
85
86
86
87
88
88
...>
<#8. ...>
∗2
∗9 m≠n
∗9
Note: "Page" refers to the corresponding page in the Instruction Manual.
www.DataSheet4U.com
Chapter 10 Appendices
143
Instruction Set
MN101C00 SERIES INSTRUCTION SET
Group Mnemonic Operation Affected Flag
VF NF CF ZF
Code
Size Cycle
Re-
peat Machine Code
Notes
Page
1234567891011Expand
∗1 d4 sign extended
∗2 d7 sign extended
∗3 d11 sign extended
NOT 
Dn
NOT _Dn→Dn 0032 0010 10Dn0010 89
92
ASR 
Dn
ASR Dn.msb→temp,Dn.lsb→CF 0– 32 0011 10Dn0010
Dn>>1→Dn,temp→Dn.msb
LSR 
Dn
LSR Dn.lsb→CF,Dn>>1→Dn 00 32 0011 11Dn0010
0→Dn.msb
90
91
ROR 
Dn
ROR Dn.Isb→temp,Dn>>1→Dn 032 0010 11Dn0010
CF→Dn.msb,temp→CF
93
93
94
95
95
96
97
Bit manipulation instructions
BSET (io8)bp
BSET
mem8(IOTOP+io8)&bpdata...PSW
0●0●55 1000 0bp. <io8 ...>0011
1→mem8(
IOTOP+
io8)bp
BSET (abs8)bp
mem8(abs8)&bpdata...PSW 0●0●44 1011 0bp. <abs 8..>
1→mem8(abs8)bp
BSET (abs16)bp
mem8(abs16)&bpdata...PSW 0●0●76 1100 0bp. <abs 16.. .... ...>0011
1→mem8(abs16)bp
BCLR (io8)bp
BCLR
mem8(IOTOP+io8)&bpdata...PSW
0●0●55 1000 1bp. <io8 ...>0011
0→mem8(
IOTOP+
io8)bp
BCLR (abs8)bp
mem8(abs8)&bpdata...PSW 0●0●44 1011 1bp. <abs 8..>
0→mem8(abs8)bp
BCLR (abs16)bp
mem8(abs16)&bpdata...PSW 0●0●76 1100 1bp. <abs 16.. .... ...>0011
0→mem8(abs16)bp
BTST imm8,Dm
BTST Dm&imm8...PSW 0●0●53 0000 11Dm <#8. ...>0010
BTST (abs16)bp
mem8(abs16)&bpdata...PSW 0●0●75 1101 0bp. <abs 16.. .... ...> 970011
98
98
99
100
100
101
102
Branch instructions
BEQ label
Bcc
if(ZF=1), PC+3+d4(label)+H
→
PC
––––32/3 1001 000H <d4>
if(ZF=0), PC+3→PC
BEQ label ∗2if(ZF=1), PC+4+d7(label)+H
→
PC
––––42/3 1000 1010 <d7. ...H
if(ZF=0), PC+4→PC
BEQ label ∗3if(ZF=1), PC+5+d11(label)+H
→
PC
––––52/3 1001 1010 <d11 .... ...H
if(ZF=0), PC+5→PC
BNE label
∗1
∗1
if(ZF=0), PC+3+d4(label)+H
→
PC
––––32/3 1001 001H <d4>
if(ZF=1), PC+3→PC
BNE label
if(ZF=0), PC+4+d7(label)+H
→
PC
––––42/3 1000 1011 <d7. ...H
if(ZF=1), PC+4→PC
BNE label if(ZF=0), PC+5+d11(label)+H
→
PC
––––52/3 1001 1011 <d11 .... ...H
if(ZF=1), PC+5→PC
BGE label
if((VF^NF)=0),PC+4+d7(label)+H→PC
––––42/3 1000 1000 <d7. ...H
if((VF^NF)=1),PC+4→PC
∗2
∗3
∗2
102
103
103
104
104
105
BGE label
if((VF^NF)=0),PC+5+d11(label)+H→PC
––––52/3 1001 1000 <d11 .... ...H
if((VF^NF)=1),PC+5→PC
BCC label
if(CF=0),PC+4+d7(label)+H
→
PC
––––42/3 1000 1100 <d7. ...H
if(CF=1), PC+4→PC
BCC label
∗3
∗2
∗3if(CF=0), PC+5+d11(label)+H
→
PC
––––52/3 1001 1100 <d11 .... ...H
if(CF=1), PC+5→PC
BCS label
if(CF=1),PC+4+d7(label)+H
→
PC
––––42/3 1000 1101 <d7. ...H
if(CF=0), PC+4→PC
BCS label if(CF=1), PC+5+d11(label)+H
→
PC
––––52/3 1001 1101 <d11 .... ...H
if(CF=0), PC+5→PC
BLT label
if((VF^NF)=1),PC+4+d7(label)+H→PC
––––42/3 1000 1110 <d7. ...H
∗2
∗3
∗2
105
106
106
107
BLT label
if((VF^NF)=1),PC+5+d11(label)+H→PC
––––52/3 1001 1110 <d11 .... ...H
if((VF^NF)=0),PC+5→PC
BLE label
if((VF^NF)|ZF=1),PC+4+d7(label)+H→PC
––––42/3 1000 1111 <d7. ...H
if((VF^NF)|ZF=0),PC+4→PC
BLE label
if((VF^NF)|ZF=1),PC+5+d11(label)+H→PC
––––52/3 1001 1111 <d11 .... ...H
if((VF^NF)|ZF=0),PC+5→PC
BGT label
if((VF^NF)|ZF=0),PC+5+d7(label)+H→PC
––––53/4 0010 0001 <d7. ...H0010
if((VF^NF)|ZF=1),PC+5→PC
∗3
∗2
∗3
∗2
if((VF^NF)=0),PC+4→PC
Note: "Page" refers to the corresponding page in the Instruction Manual.
www.DataSheet4U.com
Chapter 10 Appendices
144 Instruction Set
MN101C00 SERIES INSTRUCTION SET
Group Mnemonic Operation Affected Flag
VF NF CF ZF
Code
SizeCycle
Re-
peat Machine Code
Notes
Page
1234567891011Expand
∗1 d4 sign extended
∗2 d7 sign extended
107
108
108
109
109
BGT label
Bcc
if((VF^NF)|ZF=0),PC+6+d11(label)+H→PC
––––63/4 0011 0001 <d11 .... ...H0010
if((VF^NF)|ZF=1),PC+6→PC
BHI label
if(CF
I
ZF=0),PC+5+d7(label)+H→PC
––––53/4 0010 0010 <d7. ...H0010
if(CFIZF=1), PC+5
→
PC
BHI label
if(CF
I
ZF=0),PC+6+d11(label)+H
→
PC
–––−63/4 0011 0010 <d11 .... ...H0010
if(CFIZF=1), PC+6
→
PC
BLS label
if(CF
I
ZF=1),PC+5+d7(label)+H
→
PC
––––53/4 0010 0011 <d7. ...H0010
if(CFIZF=0), PC+5
→
PC
BLS label
∗3
∗2
∗3
∗2
∗3
if(CF
I
ZF=1),PC+6+d11(label)+H
→
PC
––––63/4 0011 0011 <d11 .... ...H0010
if(CFIZF=0), PC+6
→
PC
BNC label
if(NF=0),PC+5+d7(label)+H
→
PC
–−−− 5110
110
111
111
112
112
113
113
3/4 0010 0100 <d7. ...H0010
if(NF=1),PC+5
→
PC
BNC label
if(NF=0),PC+6+d11(label)+H
→
PC
––––63/4 0011 0100 <d11 .... ...H0010
if(NF=1),PC+6
→
PC
BNS label
if(NF=1),PC+5+d7(label)+H
→
PC
––––53/4 0010 0101 <d7. ...H0010
if(NF=0),PC+5
→
PC
BNS label
if(NF=1),PC+6+d11(label)+H
→
PC
––––63/4 0011 0101 <d11 .... ...H0010
if(NF=0),PC+6
→
PC
BVC label
if(VF=0),PC+5+d7(label)+H
→
PC
––––53/4 0010 0110 <d7. ...H0010
if(VF=1),PC+5
→
PC
BVC label
if(VF=0),PC+6+d11(label)+H
→
PC
––––63/4 0011 0110 <d11 .... ...H0010
if(VF=1),PC+6
→
PC
BVS label
if(VF=1),PC+5+d7(label)+H
→
PC
––––53/4 0010 0111 <d7. ...H0010
if(VF=0),PC+5
→
PC
BVS label
if(VF=1),PC+6+d11(label)+H
→
PC
––––63/4 0011 0111 <d11 .... ...H0010
if(VF=0),PC+6
→
PC
∗2
∗3
∗2
∗3
∗2
∗3
∗2
∗3
114
114
115
BRA label
PC+3+d4(label)
+H
→PC ––––33 1110 111H <d4>
BRA label
PC+4+d7(label)
+H
→PC ––––43 1000 1001 <d7. ...H
BRA label
PC+5+d11(label)
+H
→PC ––––53 1001 1001 <d11 .... ...H
∗2
∗3
∗1
116
116
117
117
118
118
119
119
120
120
121
121
122
122
CBEQ imm8,Dm,label
CBEQ
if(Dm=imm8),PC+6+d7(label)+H
→
PC
63/4 1100 10Dm <#8. ...> <d7. ...H
if(Dm=imm8),PC+6
→
PC
/
if(Dm=imm8),PC+8+d11(label)+H→PC
if(Dm=imm8),PC+8
→
PC
/
CBEQ imm8,Dm,label
84/5 1100 10Dm <#8. ...> <d11 .... ...H0010
CBEQ imm8,(abs8),label
if(mem8(abs8)=imm8),PC+9+d7(label)+H
→
PC
96/7 1101 1100 <abs 8..> <#8. ...> <d7. ...H0010
if(mem8(abs8)=imm8),PC+9→PC
/
CBEQ imm8,(abs8),
label
if(mem8(abs8)=imm8),PC+10+d11(label)+H→PC
10 6/7 1101 1101 <abs 8..> <#8. ...> <d11 .... ...H0010
if(mem8(abs8)=imm8),PC+10→PC
/
CBEQ imm8,(abs16),
label
if(mem8(abs16)=imm8),PC+11+d7(label)+H→PC
11 7/8 1101 1100 <abs 16.. .... ...> <#8. ...> <d7. ...H0011
if(mem8(abs16)=imm8),PC+11→PC
/
CBEQ imm8,(abs16),
label
if(mem8(abs16)=imm8),PC+12+d11(label)+H
→
PC
12 7/8 1101 1101 <abs 16.. .... ...> <#8. ...> <d11 .... ...H0011
if(mem8(abs16)=imm8),PC+12→PC
/
CBNE imm8,Dm,label
if(Dm=imm8),PC+6+d7(label)+H→PC
/63/4 1101 10Dm <#8. ...> <d7. ..H>
if(Dm=imm8),PC+6→PC
CBNE imm8,Dm,label
if(Dm=imm8),PC+8+d11(label)+H→PC
/84/5 1101 10Dm <#8. ...> <d11 .... ...H0010
if(Dm=imm8),PC+8→PC
CBNE imm8,(abs8),label
if(mem8(abs8)=imm8),PC+9+d7(label)+H→PC
/96/7 1101 1110 <abs 8..> <#8. ...> <d7. ...H0010
if(mem8(abs8)=imm8),PC+9→PC
CBNE imm8,(abs8),label
if(mem8(abs8)=imm8),PC+10+d11(label)+H→PC
/10 6/7 1101 1111 <abs 8..> <#8. ...> <d11 .... ...H0010
if(mem8(abs8)=imm8),PC+10→PC
CBNE imm8,(abs16),label
if(mem8(abs16)=imm8),PC+11+d7(label)+H→PC
/11 7/8 1101 1110 <abs 16.. .... ...> <#8. ...> <d7. ...H0011
if(mem8(abs16)=imm8),PC+11→PC
CBNE imm8,(abs16),label
if(mem8(abs16)=imm8),PC+12+d11(label)+H→PC
/12 7/8 1101 1111 <abs 16.. .... ...> <#8. ...> <d11 .... ...H0011
if(mem8(abs16)=imm8),PC+12→PC
TBZ (abs8)bp,label
TBZ
if(mem8(abs8)bp=0),PC+7+d7(label)+H→PC
0076/7 0000 0bp. <abs 8..> <d7. ...H0011
if(mem8(abs8)bp=1),PC+7→PC
∗2
∗3
∗2
∗3
∗2
∗3
∗2
∗3
∗2
∗3
∗2
∗3
∗2
∗3
CBNE
∗3 d11 sign extended
TBZ (abs8)bp,label
if(mem8(abs8)bp=0),PC+8+d11(label)+H→PC
0086/7 0000 1bp. <abs 8..> <d11 .... ...H0011
if(mem8(abs8)bp=1),PC+8→PC
Note: "Page" refers to the corresponding page in the Instruction Manual.
www.DataSheet4U.com
Chapter 10 Appendices
145
Instruction Set
MN101C00 SERIES INSTRUCTION SET
Group Mnemonic Operation Affected Flag
VF NF CF ZF
Code
Size Cycle
Re-
peat Machine Code
Notes
Page
1234567891011Expand
TBNZ (abs8)bp,label
if(mem8(abs8)bp=1),PC+8+d11(label)+H→PC
008
126
127
127
129
129
130
130
131
6/7 0001 1bp. <abs 8..> <d11 .... ...H0011
if(mem8(abs8)bp=0),PC+8→PC
TBNZ (io8)bp,label
if(mem8(io)bp=1),PC+8+d11(label)+H→PC
0086/7 0101 1bp. <io8 ...> <d11 .... ...H0011
if(mem8(io)bp=0),PC+8→PC
TBNZ (abs16)bp,
label
∗2
∗2
∗2
if(mem8(abs16)bp=1),PC+10+d11(label)+H→PC
0010 7/8 1111 1bp. <abs 16.. .... ...> <d11 .... ...H0011
if(mem8(abs16)bp=0),PC+10→PC
JSR (An)
JSR
SP-3→SP,(PC+3).bp7~0→mem8(SP)
––––37 0001 00A10010
(PC+3).bp15
~
8→mem8(SP+1)
(PC+3).H→mem8(SP+2).bp7,
0→mem8(SP+2).bp6~2,
(PC+3).bp17~16→mem8(SP+2).bp1~0
0→PC.bp17~16
An→PC.bp15~0,0→PC.H
JSR label
SP-3→SP,(PC+5).bp7~0→mem8(SP)
––––56 0001 000H <d12 .... ...>
(PC+5).bp15
~
8→mem8(SP+1)
(PC+5).H→mem8(SP+2).bp7,
0→mem8(SP+2).bp6~2,
(PC+5).bp17~16→mem8(SP+2).bp1~0
PC+5+d12(label)+H→PC
JSR label
SP-3→SP,(PC+6).bp7~0→mem8(SP)
––––67 0001 001H <d16 .... .... ...>
(PC+6).bp15
~
8→mem8(SP+1)
(PC+6).H→mem8(SP+2).bp7,
0→mem8(SP+2).bp6~2,
(PC+6).bp17~16→mem8(SP+2).bp1~0
PC+6+d16(label)+H→PC
JSR label
∗3
∗4
∗5
SP-3→SP,(PC+7).bp7~0→mem8(SP)
––––78 1001 1aaH <abs 18.b p15
〜
0..>0011
(PC+7).bp15
~
8→mem8(SP+1)
(PC+7).H→mem8(SP+2).bp7,
0→mem8(SP+2).bp6~2,
(PC+7).bp17~16→mem8(SP+2).bp1~0
abs18(label)+H→PC
JSRV (tbl4)
SP-3→SP,(PC+3).bp7~0→mem8(SP)
––––39 1111 1110 <t4>
(PC+3).bp15~8→mem8(SP+1)
(PC+3).H→mem8(SP+2).bp7
(PC+3).bp17~16→mem8(SP+2).bp1~0
mem8(x'004080+tbl4<<2)→PC.bp7~0
mem8(x'004080+tbl4<<2+1)→PC.bp15
~
8
mem8(x'004080+tbl4<<2+2).bp7→PC.H
mem8(x'004080+tbl4<<2+2).bp1~0→
           PC.bp17
~
16
∗2 d11 sign extended
∗4 d16 sign extended
∗5 aa=abs18.17
〜
16
123
123
124
124
125
125
126
TBZ (abs16)bp,label
TBZ
if(mem8(abs16)bp=0),PC+9+d7(label)+H→PC
0097/8 1110 0bp. <abs 16.. .... ...> <d7. ...H0011
if(mem8(abs16)bp=1),PC+9→PC
TBZ (io8)bp,label
if(mem8(IOTOP+io8)bp=0),PC+8+d11(label)+H→PC
0086/7 0100 1bp. <io8 ...> <d11 .... ...H0011
if(mem8(IOTOP+io8)bp=1),PC+8→PC
TBZ (abs16)bp,label
if(mem8(abs16)bp=0),PC+10+d11(label)+H→PC
0010 7/8 1110 1bp. <abs 16.. .... ...> <d11 .... ...H0011
if(mem8(abs16)bp=1),PC+10→PC
TBNZ (abs8)bp,label
TBNZ
if(mem8(abs8)bp=1),PC+7+d7(label)+H
→
PC
0076/7 0001 0bp. <abs 8..> <d7. ...H0011
if(mem8(abs8)bp=0),PC+7→PC
TBNZ (io8)bp,label
if(mem8(io)bp=1),PC+7+d7(label)+H→PC
0076/7 0101 0bp. <io8 ...> <d7. ...H0011
if(mem8(io)bp=0),PC+7→PC
TBNZ (abs16)bp,label
∗1
∗2
∗2
∗1
∗1
∗1
if(mem8(abs16)bp=1),PC+9+d7(label)+H→PC
0097/8 1111 0bp. <abs 16.. .... ...> <d7. ...H0011
if(mem8(abs16)bp=0),PC+9→PC
JMP 
(An)
JMP
0→PC.17~16,An→PC.15~0,0→PC.H
––––34 0001 00A00010
JMP 
label
abs18(label)+H→PC ––––75 1001 0aaH <abs 18.b p15
〜
0..>0011 128
128
132
NOP
NOP PC+2→PC ––––21 0000 0000
∗1 d7 sign extended
TBZ (io8)bp,label
if(mem8(IOTOP+io8)bp=0),PC+7+d7(label)+H→PC
0076/7 0100 0bp. <io8 ...> <d7. ...H0011
if(mem8(IOTOP+io8)bp=1),PC+7→PC
∗1
∗5
0→mem8(SP+2).bp6~2,
∗3 d12 sign extended
Note: "Page" refers to the corresponding page in the Instruction Manual.
www.DataSheet4U.com
Chapter 10 Appendices
146 Instruction Set
MN101C00SERIESINSTRUCTIONSET
Group Mnemonic Operation Flag
VF NF CF ZF
Code
Size Cycle
Re-
peat MachineCode
Notes
Page
1234567891011
135
  
REPimm3
REP ※1imm3→RPC −−−−32 0001 1rep0010
RTS
RTS mem8(SP)→(PC).bp7〜0 −−−−27 0000 0001
mem8(SP+1)→(PC).bp15〜8
  
mem8(SP+2).bp7→(PC).H
  
mem8(SP+2).bp1〜0→(PC).bp17〜16
  
SP+3→SP   
  133
134
RTIRTI mem8(SP)→PSW ●●●●211 0000 0011 
mem8(SP+1)→(PC).bp7〜0  
mem8(SP+2)→(PC).bp15〜8
  
mem8(SP+3).bp7→(PC).H
  
mem8(SP+3).bp1〜0→(PC).bp17〜16
  
mem8(SP+4)→HA-l   
mem8(SP+5)→HA-h   
SP+6→SP   
Control instruction
∗1 Number of repeats is 0 when imm3=0.
Note: "Page" refers to the corresponding page in the Instruction Manual.
Expand
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Chapter 10 Appendices
147
Instruction Map
8-3 Instruction Map
0
0 NOP RTS
MOV#8,(io8)
RTI
CMP#8,(abs8)/(abs12)
POPAn ADD#8,Dm
MOVW#8,DWm
MOVW#8,Am
1 JSRd12(label) JSRd16(label)
MOV#8,(abs8)/(abs12)
PUSHAn OR#8,Dm AND#8,Dm
2 Whentheextensioncodeisb'0010'
Whentheextensioncodeisb'0011'
3
4 MOV(abs12),Dm MOV(abs8),Dm MOV(An),Dm
5 MOVDn,(abs12) MOVDn,(abs8) MOVDn,(Am)
6 MOV(io8),Dm MOV(d4,SP),Dm MOV(d8,An),Dm
7 MOVDn,(io8) MOVDn,(d4,SP) MOVDn,(d8,Am)
8 ADD#4,Dm SUBDn,Dn
BGEd7 BRAd7 BEQd7 BNEd7 BCCd7 BCSd7 BLTd7 BLEd7
9 BEQd4 BNEd4
MOVWDWn,(HA)
MOVWAn,(HA)
BGEd11 BRAd11 BEQd11 BNEd11 BCCd11 BCSd11 BLTd11 BLEd11
A MOVDn,Dm/MOV#8,Dm
B BSET(abs8)bp BCLR(abs8)bp
C CMP#8,Dm
MOVW(abs8),Am
MOVW(abs8),DWm
CBEQ#8,Dm,d7
CMPW#16,DWm
MOVW#16,DWm
D MOVDn,(HA)
MOVWAn,(abs8)
MOVWDWn,(abs8)
CBNE#8,Dm,d7 CMPW#16,Am MOVW#16,Am
E MOVW(An),DWm
MOVW(d4,SP),Am
MOVW(d4,SP),DWm
POPDn ADDW#4,Am BRAd4
F MOVWDWn,(Am)
MOVWAn,(d4,SP)
MOVWDWn,(d4,SP)
PUSHDn
ADDW#8,SP ADDW#4,SP
JSRV(tbl4)
123456789ABCDEF
0
0 MOVWAn,Am CMPWAn,Am MOVWSP,Am MOVWAn,SP BTST#8,Dm
1
JMP(A0) JSR(A0) JMP(A1) JSR(A1)
MOVPSW,Dm REP#3
2
BGTd7 BHId7 BLSd7 BNCd7 BNSd7 BVCd7 BVSd7
NOTDn RORDn
3
BGTd11 BHId11 BLSd11 BNCd11 BNSd11 BVCd11 BVSd11
ASRDn LSRDn
4 SUBWDWn,DWm
SUBW#16,DWm
SUBW#16,Am SUBWDWn,Am MOVWDWn,Am
5 ADDWDWn,DWm
ADDW#16,DWm
ADDW#16,Am ADDWDWn,Am CMPWDWn,Am
6 MOV(d16,SP),Dm MOV(d8,SP),Dm MOV(d16,An),Dm
7 MOVDn,(d16,SP) MOVDn,(d8,SP) MOVDn,(d16,Am)
8
MOVWDWn,DWm(NOPL@n=m)
CMPWDWn,DWm ADDUWDn,Am
9 EXTDn,DWm
AND#8,PSW
OR#8,PSW
MOVDn,PSW ADDSWDn,Am
A SUBDn,Dm/SUB#8,Dm
B SUBCDn,Dm
C MOV(abs16),Dm
MOVW(abs16),Am
MOVW(abs16),DWm
CBEQ#8,Dm,d12 MOVWAn,DWm
D MOVDn,(abs16)
MOVWAn,(abs16)
MOVWDWn,(abs16)
CBNE#8,Dm,d12
CBEQ#8,(abs8),d7/d11 CBNE#8,(abs8),d7/d11
E
MOVW(d16,SP),Am
MOVW(d16,SP),DWm
MOVW(d8,SP),Am
MOVW(d8,SP),DWm
MOVW(An),Am ADDW#8,Am DIVU
F
MOVWAn,(d16,SP)
MOVWDWn,(d16,SP)
MOVWAn,(d8,SP)
MOVWDWn,(d8,SP)
MOVWAn,(Am)
ADDW#16,SP
MULU
123456789ABCDEF
MN101C00SERIESINSTRUCTIONMAP
2nd nibble\3rd nibble
Extension code: b'0010'
1st nibble\2nd nibble
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Chapter 10 Appendices
148 Instruction Map
0
0 TBZ(abs8)bp,d7 TBZ(abs8)bp,d11
1 TBNZ(abs8)bp,d7 TBNZ(abs8)bp,d11
2 CMPDn,Dm
3 ADDDn,Dm
4 TBZ(io8)bp,d7 TBZ(io8)bp,d11
5 TBNZ(io8)bp,d7 TBNZ(io8)bp,d11
6 ORDn,Dm
7 ANDDn,Dm
8 BSET(io8)bp BCLR(io8)bp
9 JMPabs18(label) JSRabs18(label)
A XORDn,Dm/XOR#8,Dm
B ADDCDn,Dm
C BSET(abs16)bp BCLR(abs16)bp
D BTST(abs16)bp
cmp#8,(abs16) mov#8,(abs16)
CBEQ#8,(abs16),d7/11 CBNE#8,(abs16),d7/11
E TBZ(abs16)bp,d7 TBZ(abs16)bp,d11
F TBNZ(abs16)bp,d7 TBNZ(abs16)bp,d11
123456789ABCDEF
2nd nibble\3rd nibble
Extension code: b'0011'
Ver2.0(1997.9.26)
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Chapter 10 Appendices
149
Summary of Special Function Registers
Address
X3F00
X3F01
X3F02
X3F03
X3F10
X3F11
X3F12
X3F13
X3F14
Register Bit7 Bit6 Bit5 Bit0Bit1Bit2Bit3Bit4
STOP HALT OSC1 OSC0
STOP
transferrequest HALT
transferrequest Oscillationcontrol
IVBAIOW0IOW1
II/0buswaitvalueset
Specifiesbaseaddress
ofinterruptvectortable
WDEN
Watchdog
timertable
DLYS0DLYS1
Setsoscillation
stabilizationwaitperiod
IRWE
X3F16
X3F17
X3F15
X3F18
X3F1F
X3F20
X3F21
X3F22
X3F23
CPUM
MEMCTR
WDCTR
DLYCTR
P0OUT
P1OUT
P2OUT
P6OUT
P7OUT
P8OUT
P0IN
P1IN
P2IN
P0OUT2P0OUT6 P0OUT1 P0OUT0
Port0output
P1OUT4 P1OUT3 P1OUT2 P1OUT1 P1OUT0
Port1output
P2OUT7
Port2output
P6OUT7 P6OUT6 P6OUT5 P6OUT4 P6OUT3 P6OUT2 P6OUT1 P6OUT0
Port6output
P7OUT0
Port7
output
P8OUT7 P8OUT6 P8OUT5 P8OUT4 P8OUT3 P8OUT2 P8OUT1 P8OUT0
Port8output
P0IN1P0IN2 P0IN0
Port0input
P1IN4 P1IN3 P1IN2 P1IN1 P1IN0
Port1input
P2IN2 P2IN1 P2IN0
Port2input
BitSymbol
X3F0E EXADV
Disablestouse
Disablestouse
Reference
page
LSIManual
MN101C00seriesﾞ
89
30
89
 41，45
 41，45
 41，45
 41，45
 41，45
 41，45
 41，45
 41，45
 41，45
Mustbeset
to"0"
P0IN6
Disablestouse
Disablestouse
Disablestouse
8-4 Summary of Special Function Registers
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Chapter 10 Appendices
150
Summary of Special Function Registers
Address Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
X3F31
X3F35
X3F33
X3F34
X3F36
X3F37
X3F38
X3F39
X3F3A
X3F3C
X3F40
X3F41
P1DIR
Disablestouse
P6DIR
P7DIR
P8DIR
P1OMD
PAIMD
Disablestouse
P0PLU
P1PLU
BitSymbol
P1DIR4 P1DIR3 P1DIR2 P1DIR1 P1DIR0
Port1I/Odirectioncontrol
Port0I/Odirectioncontrol
Port6I/Odirectioncontrol
Port7I/O
directioncontrol
Port8I/Odirectioncontrol
P6DIR7 P6DIR6 P6DIR5 P6DIR4 P6DIR3 P6DIR2 P6DIR1 P6DIR0
P7DIR0
P8DIR7 P8DIR6 P8DIR5 P8DIR4 P8DIR3 P8DIR2 P8DIR1 P8DIR0
P14TCO P13TCO P12TCO P10TCO
PAAIN5 PAAIN4 PAAIN3 PAAIN2 PAAIN1 PAAIN0
I/Oport/Specialfunctionpincontrol
I/Oport/Specialfunctionpincontrol
P0PLU2P0PLU6 P0PLU1 P0PLU0
P1PLU4 P1PLU3 P1PLU2 P1PLU1 P1PLU0
Port0pull-upresistorON/OFFcontrol
Port1pull-upresistorON/OFFcontrol
P7IN
X3F26
X3F27
X3F28
X3F2A
X3F30
P8IN
PAIN
P0DIR
Port6input
Port7
input
P6IN5P6IN7 P6IN6 P6IN0P6IN1
P6IN2
P6IN3P6IN4
P7IN0
P8IN7 P8IN6 P8IN5 P8IN4 P8IN3 P8IN2 P8IN1 P8IN0
PAIN5 PAIN4 PAIN3 PAIN2 PAIN1 PAIN0
P0DIR2P0DIR6 P0DIR1 P0DIR0
Port8input
PortAinput
Disablestouse
Disablestouse
Disablestouse
Disablestouse
Reference
Page
41，45
41，45
41，45
41，45
41，45
41，45
41，45
41，45
41，45
41，46
41，46
41，45
42，45
P6IN
X3F24
X3F25
PAIN7 PAIN6
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Chapter 10 Appendices
151
Summary of Special Function Registers
BitSymbol
Address Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
X3F52
X3F50
X3F51
X3F46
X3F47
X3F48
X3F4A
X3F4B
X3F4C
X3F53
X3F54
X3F55
X3F56
X3F57
X3F58
SC0RXB
SC0TRB
Disablestouse
SC0MD2
SC0MD0
SC0MD1
SC0MD3
SC0CTR
SC0CKM
SC0RXB7 SC0RXB6 SC0RXB5 SC0RXB4 SC0RXB3 SC0RXB2 SC0RXB1 SC0RXB0
Disablestouse
SC0CK1 SC0CK0 SC0BRKF SC0ERE SC0TRI
Select1/8period
offreq.
SC0IOM
SC0SBOM SC0SBTM SC0SBOS SC0SBIS SC0SBTS
SC0RXB4SC0RXB5SC0BSY SC0ORESC0PEKSC0FEFSC0CMD
SC0TRB7 SC0TRB5 SC0TRB4 SC0TRB3 SC0TRB2 SC0TRB1 SC0TRB0
SC0TRB6
Receivedatainputedge
Transmitdataoutputedge Startbitsetup
fortransmit Transferbitcount
Selectsync.
seroalUART
Statusof
serialbus
Synchrounouserial
starteditionselect
SC0BRKE
SC0FM1 SC0FM0 SC0PM1 SC0PM0 SC0NPE
SC0LNG2SC0CE0 SC0CE1 SC0DIR SC0LNG1 SC0LNG0
SC0STE
Port6pull-upresistorON/OFFcontrol
Portpull-uppulldown
resistorON/OFFcontrol
P8PLU7 P8PLU6 P8PLU5 P8PLU4 P8PLU3 P8PLU2 P8PLU1 P8PLU0
PAPLUD5 PAPLUD4 PAPLUD3 PAPLUD2 PAPLUD1 PAPLUD0
Port8pull-upresistorON/OFFcontrol
P7PLUD0
P6PLU7  P6PLU5P6PLU6  
P6PLU4P6PLU3P6PLU2P6PLU1P6PLU0
P6PLU
P7PLUD
P8PLU
PAPLUD
FLOAT1
Disablestouse P21M
P7RDWN
PARDWNP21M
Clocksourceselection
Breakstatus
rec.monitor
Errormonitor
Trans/recinterrup
requestflag
Controlbreak
statustrans.
Specifiesframemode Specifiesaddedbit Enables
parity
Detectframing
error Detectparity
error Detectoverrun
error
Serialinterface0transmit/receiveshiftregister
Serialinterface0receivedatabuffer
PortApull-uppull-downresistorON/OFFcontrol
SBO0pin
selection
SBI0/SBO0
pinconnection SelectSBT
pinformat SelectSBO
pinfunction
Reference
Page
42，45
42，45
42，45
42，45
42，46
108
109
110
111
112
107
107
ControlSBI
input SelectSBT0
pinfunction
P21input
modeselectionPortApullpﾟ
pulldownsel.Port7pullupﾟ
pulldownsel.
X3F42
X3F43
X3F44
X3F45
P2PLU
Disablestouse
Disablestouse
Disablestouse
P2PLU2 P2PLU1 P2PLU0
Port2pull-upresistorON/OFFcontrol 42，45
PAPLUD6PAPLUD7
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Chapter 10 Appendices
152
Summary of Special Function Registers
BitSymbol
Address Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Binarycounter5
TM5BC7TM5BC6TM5BC5TM5BC4TM5BC3
TM5BC2TM5BC1TM5BC0
TM4BCH6
Binarycounter4(Upper8bits）
TM4BCH7 TM4BCH5TM4BCH4TM4BCH3TM4BCH2TM4BCH1TM4BCH0




TM4BCL6 TM4BCL4 TM4BCL2

Binarycounter4（Lower8bits）
TM4BCL7 TM4BCL5 TM4BCL3 TM4BCL1TM4BCL0
TM3BC2
Binarycounter2
TM2BC7TM2BC6 TM2BC5 TM2BC4TM2BC3TM2BC2TM2BC1TM2BC0
TM2BC
TM3BC
TM4BCL
TM5BC
Disablestouse
TM2OC
TM4OCL
TM4ICL7TM4ICL6TM4ICL5TM4ICL4TM4ICL3TM4ICL2TM4ICL1TM4ICL0
Inputcaptureregister（Lower8bits）
TM4ICH7TM4ICH6TM4ICH5TM4ICH4TM4ICH3TM4ICH2TM4ICH1TM4ICH0
Inputcapturereigster(Upper8bits)
Binarycounter3
TM3BC7TM3BC6TM3BC5TM3BC4TM3BC3 TM3BC1TM3BC0
TM3OC7TM3OC6TM3OC5TM3OC4TM3OC3TM3OC2TM3OC1TM3OC0
Compareregister3
TM4OCL7 TM4OCL6 TM4OCL5 TM4OCL4 TM4OCL3 TM4OCL2 TM4OCL1 TM4OCL0
Compareregister4（Lower8bits）
X3F63
X3F62
X3F73
X3F74
X3F72
X3F68
X3F70
X3F71
X3F67
X3F66
X3F65
X3F64
TM4BCH
TM4ICL
TM4ICH
Disablestouse
TM3OC
TM2OC7TM2OC6TM2OC5TM2OC4
Compareregister2
TM2OC3 TM2OC2 TM2OC1 TM2OC0
X3F61Disablestouse
Reference
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 83
84
84
84
−
−
82
82
83
X3F59
X3F5A
X3F5C
X3F5B
X3F5D
X3F60
Disablestouse
Disablestouse
Disablestouse
Disablestouse
Disablestouse
Disablestouse
www.DataSheet4U.com
Chapter 10 Appendices
153
Summary of Special Function Registers
BitSymbol
Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Address
X3FF2
X3FF1
X3FF0
X3FEF
X3FEE
X3FED
X3FEC
X3FEB
X3FEA
IRQ3ICR
Disablestouse
TM3ICR
TM4ICR
TM5ICR
Disablestouse
Disablestouse
IRQ2ICR
ADICR
Interrupt
requestflag
Interrupt
requestflag
Interrupt
requestflag
Interrupt
requestflag
Interrupt
requestflag
Externalinterrupt
validedgeflag
ﾞ
Interruptlevelflag
fortimer3interrupt
Interruptlevelflag
fortimer4interrupt
Interruptlevelflag
fortimer5interrupt
Interrup
enableflag
ﾞ
Interrupt
enableflag
ﾞ
Interrupt
enableflag
Interrupt
enableflag
Interrupt
enableflag
IRQ2IE IRQ2IR
TM3IE
TM4IE
TM5IE
IRQ2LV1 IRQ2LV0 REDG2
Interruptlevelflag
forexternalinterrupt
Interruplevelflagfor
A/Dinterrupt
Reference
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ADLV1ADLV0 ADIE ADIR

WDIR
Watchdoginterrupt
requestflag
X3FE0
X3FE1
X3FE2
X3FE3
X3FE4
X3FE5
X3FE6
X3FE7
X3FE8
X3FE9
NMICR
Disablestouse
IRQ0ICR
IRQ1ICR
Disablestouse
Disablestouse
TM2ICR
TBICR
SC0ICR
Disablestouse
IRQ0LV1 IRQ0LV0
Interruplevelflagfor
externalinterrupt
REDG0
Externalinterrupt
validedgeflag
IRQ0IE IRQ0IR
Interrupt
enableflag
Interrupt
requestflag
Interruptlevelflag
forexternalinterrupt
Externalinterrupt
valudedgeflag
Interrupt
enableflag
Interrupt
requestflag
IRQ1LV1 IRQ1LV0 REDG1 IRQ1IE IRQ1IR
Interruptlevelflagfor
timer2interrupt Interrupt
enableflag
Interrupt
requestflag
TM2LV1 TM2LV0 TM2IE TM2IR
Interruptlevelflagfor
timebaseinterrupt Interrupt
enableflag
Interrupt
requestflag
TBLV1 TBLV0 TBIE TBIR
Interruptlevelflagfor
serial0interrupt
Interrup
enableflag
Interrupt
requestflag
SC0LV1 SC0LV0 SC0IE SC0IR
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www.DataSheet4U.com
Chapter 10 Appendices
154
Summary of Special Function Registers
BitSymbol
Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Address
X3FF2
X3FF1
X3FF0
X3FEF
X3FEE
X3FED
X3FEC
X3FEB
X3FEA
IRQ3ICR
Disablestouse
TM3ICR
TM4ICR
TM5ICR
Disablestouse
Disablestouse
IRQ2ICR
ADICR
Interrupt
requestflag
Interrupt
requestflag
Interrupt
requestflag
Interrupt
requestflag
Interrupt
requestflag
Externalinterrupt
validedgeflag
ﾞ
Interruptlevelflag
fortimer3interrupt
Interruptlevelflag
fortimer4interrupt
Interruptlevelflag
fortimer5interrupt
Interrup
enableflag
ﾞ
Interrupt
enableflag
ﾞ
Interrupt
enableflag
Interrupt
enableflag
Interrupt
enableflag
IRQ2IE IRQ2IR
TM3IE
TM4IE
TM5IE
IRQ2LV1 IRQ2LV0 REDG2
Interruptlevelflag
forexternalinterrupt
Interruplevelflagfor
A/Dinterrupt
Reference
Page
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  35
ADLV1ADLV0 ADIE ADIR

WDIR
Watchdoginterrupt
requestflag
X3FE0
X3FE1
X3FE2
X3FE3
X3FE4
X3FE5
X3FE6
X3FE7
X3FE8
X3FE9
NMICR
Disablestouse
IRQ0ICR
IRQ1ICR
Disablestouse
Disablestouse
TM2ICR
TBICR
SC0ICR
Disablestouse
IRQ0LV1 IRQ0LV0
Interruplevelflagfor
externalinterrupt
REDG0
Externalinterrupt
validedgeflag
IRQ0IE IRQ0IR
Interrupt
enableflag
Interrupt
requestflag
Interruptlevelflag
forexternalinterrupt
Externalinterrupt
valudedgeflag
Interrupt
enableflag
Interrupt
requestflag
IRQ1LV1 IRQ1LV0 REDG1 IRQ1IE IRQ1IR
Interruptlevelflagfor
timer2interrupt Interrupt
enableflag
Interrupt
requestflag
TM2LV1 TM2LV0 TM2IE TM2IR
Interruptlevelflagfor
timebaseinterrupt Interrupt
enableflag
Interrupt
requestflag
TBLV1 TBLV0 TBIE TBIR
Interruptlevelflagfor
serial0interrupt
Interrup
enableflag
Interrupt
requestflag
SC0LV1 SC0LV0 SC0IE SC0IR
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www.DataSheet4U.com
MN101C115 / 117
LSI User's Manual
August,1999 1st Edition 1st Printing
Issued by Matsushita Electric Industrial Co., Ltd.
Matsushita Electronics Corporation
©
Matsushita Electric Industrial Co., Ltd.
©
Matsushita Electronics Corporation
www.DataSheet4U.com
Semiconductor Company Matsushita Electronics Corporation
Nagaokakyo, Kyoto, 617-8520 Japan
Tel: (075) 951-8151
http://www.mec.panasonic.co.jp
■U.S.A. SALES OFFICE
Panasonic Industrial Company [PIC]
●New Jersey Office:
2 Panasonic Way, Secaucus, New Jersey 07094
Tel: 201-392-6173
Fax:201-392-4652
●Milpitas Office:
1600 McCandless Drive, Milpitas, California 95035
Tel: 408-945-5630
Fax:408-946-9063
●Chicago Office:
1707 N. Randall Road, Elgin, Illinois 60123-7847
Tel: 847-468-5829
Fax:847-468-5725
●Atlanta Office:
1225 Northbrook Parkway, Suite 1-151,
Suwanee, Georgia 30174
Tel: 770-338-6940
Fax:770-338-6849
●San Diego Office:
9444 Balboa Avenue, Suite 185
San Diego, California 92123
Tel: 619-503-2940
Fax:619-715-5545
■CANADA SALES OFFICE
Panasonic Canada Inc. [PCI]
5700 Ambler Drive Mississauga, Ontario, L4W 2T3
Tel: 905-624-5010
Fax:905-624-9880
■GERMANY SALES OFFICE
Panasonic Industrial Europe G.m.b.H. [PIEG]
●Munich Office:
Hans-Pinsel-Strasse 2 85540 Haar
Tel: 89-46159-156
Fax:89-46159-195
■U.K. SALES OFFICE
Panasonic Industrial Europe Ltd. [PIEL]
●Electric component Group:
Willoughby Road, Bracknell, Berkshire RG12 8FP
Tel: 1344-85-3773
Fax:1344-85-3853
■FRANCE SALES OFFICE
Panasonic Industrial Europe G.m.b.H. [PIEG]
●Paris Office:
270, Avenue de President Wilson
93218 La Plaine Saint-Denis Cedex
Tel: 14946-4413
Fax:14946-0007
■ITALY SALES OFFICE
Panasonic Industrial Europe G.m.b.H. [PIEG]
●Milano Office:
Via Lucini N19, 20125 Milano
Tel: 2678-8266
Fax:2668-8207
SALES OFFICES
■HONG KONG SALES OFFICE
Panasonic Shun Hing Industrial Sales (Hong Kong)
Co., Ltd. [PSI(HK)]
11/F, Great Eagle Centre, 23 Harbour Road,
Wanchai, Hong Kong.
Tel: 2529-7322
Fax:2865-3697
■TAIWAN SALES OFFICE
Panasonic Industrial Sales Taiwan Co.,Ltd. [PIST]
●Head Office:
6th Floor, Tai Ping & First Building No.550. Sec.4,
Chung Hsiao E. Rd. Taipei 10516
Tel: 2-2757-1900
Fax:2-2757-1906
●Kaohsiung Office:
6th Floor, Hsien 1st Road Kaohsiung
Tel: 7-223-5815
Fax:7-224-8362
■SINGAPORE SALES OFFICE
Panasonic Semiconductor of South Asia [PSSA]
300 Beach Road # 16-01
The Concourse Singapore 199555
Tel: 390-3688
Fax:390-3689
■MALAYSIA SALES OFFICE
Panasonic Industrial Company (Malaysia) Sdn. Bhd.
●Head Office: [PICM]
Tingkat 16B Menara PKNS PJ No.17,Jalan Yong
Shook Lin 46050 Petaling Jaya Selangor Darul Ehsan
Malaysia
Tel: 03-7516606
Fax:03-7516666
●Penang Office:
Suite 20-17,MWE PLAZA No.8,Lebuh Farquhar,10200
Penang Malaysia
Tel: 04-2625550
Fax:04-2619989
●Johore Sales Office:
39-01 Jaran Sri Perkasa 2/1,Taman Tampoi
Utama,Tampoi 81200 Johor Bahru,Johor Malaysia
Tel: 07-241-3822
Fax:07-241-3996
■CHINA SALES OFFICE
Panasonic SH Industrial Sales (Shenzhen)
Co., Ltd. [PSI(SZ)]
7A-107, International Business & Exhibition Centre,
Futian Free Trade Zone, Shenzhen 518048
Tel: 755-359-8500
Fax:755-359-8516
Panasonic Industrial (Shanghai) Co., Ltd. [PICS]
1F, Block A, Development Mansion, 51 Ri Jing Street,
Wai Gao Qiao Free Trade Zone, Shanghai 200137
Tel: 21-5866-6114
Fax:21-5866-8000
■THAILAND SALES OFFICE
Panasonic Industrial (Thailand) Ltd. [PICT]
252/133 Muang Thai-Phatra Complex Building,31st
Fl.Rachadaphisek Rd.,Huaykwang,Bangkok 10320
Tel: 02-6933407
Fax:02-6933423
080499