LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS
FANOUT BUFFER
ICS8545I
IDT™ / ICS™
LVDS FANOUT BUFFER 1
ICS8545BGI REV. B MARCH 02, 2009
General Description
The ICS8545I is a low skew, high performance
1-to-4 LVCMOS/LVTTL-to-LVDS Clock Fanout
Buffer and a member of the HiPerClockS™ family of
High Performance Clock Solutions from IDT.
Utilizing Low Voltage Differential Signaling (LVDS)
the ICS8545I provides a low power, low noise, solution for
distributing clock signals over controlled impedances of 100Ω. The
ICS8545I accepts a LVCMOS/LVTTL input level and translates it
to 3.3V LVDS output levels.
Guaranteed output and part-to-part skew characteristics make the
ICS8545I ideal for those applications demanding well defined
performance and repeatability.
Features
•Four differential LVDS output pairs
•Two LVCMOS/LVTTL clock inputs to support redundant
or selectable frequency fanout applications
•Maximum output frequency: 650MHz
•Translates LVCMOS/LVTTL input signals to LVDS levels
•Output skew: 40ps (maximum)
•Part-to-part skew: 500ps (maximum)
•Propagation delay: 3.6ns (maximum)
•Additive phase jitter, RMS: 0.13ps (typical)
•Full 3.3Vsupply mode
•-40°C to 85°C ambient operating temperature
•Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
HiPerClockS™
ICS
ICS8545I
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
Pin Assignment
Block Diagram
0
1
nD
Q
LE
0
1
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
CLK_EN
CLK1
CLK2
CLK_SEL
OE
Pulldown
Pulldown
Pulldown
Pullup
Pullup
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND
OE
nc
CLK2
nc
CLK1
CLK_SEL
CLK_EN
GND
VDD
Q0
Q0
VDD
Q1
Q1
Q2
Q2
GND
Q3
Q3
ICS8545I
LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
IDT™ / ICS™
LVDS FANOUT BUFFER 2
ICS8545BGI REV. B MARCH 02, 2009
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1, 9, 13 GND Power Power supply ground.
2 CLK_EN Input Pullup
Synchronizing clock enable. When HIGH, clock outputs follows clock input.
When LOW, Q outputs are forced low, Q outputs are forced high.
LVCMOS / LVTTL interface levels.
3 CLK_SEL Input Pulldown Clock select input. When HIGH, selects CLK2 input.
When LOW, selects CLK1 input. LVCMOS / LVTTL interface levels.
4 CLK1 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
5, 7 nc Unused No connect.
6 CLK2 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
8 OE Input Pullup Output enable. Controls enabling and disabling of outputs Q0/Q0 through
Q3/Q3. LVCMOS/LVTTL interface levels.
10, 18 VDD Power Positive supply pins.
11, 12 Q3, Q3 Output Differential output pair. LVDS interface levels.
14, 15 Q2, Q2 Output Differential output pair. LVDS interface levels.
16, 17 Q1, Q1 Output Differential output pair. LVDS interface levels.
19, 20 Q0, Q0 Output Differential output pair. LVDS interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CIN Input Capacitance 4 pF
RPULLUP Input Pullup Resistor 51 kΩ
RPULLDOWN Input Pulldown Resistor 51 kΩ
ICS8545I
LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
IDT™ / ICS™
LVDS FANOUT BUFFER 3
ICS8545BGI REV. B MARCH 02, 2009
Function Tables
Table 3A. Control Input Function Table
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK1 and CLK2 inputs as described in Table 3B.
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
Inputs Outputs
OE CLK_EN CLK_SEL Selected Source Q0:Q3 Q0:Q3
0 X X Hi-Z Hi-Z
100CLK1LowHigh
101CLK2LowHigh
1 1 0 CLK1 Active Active
1 1 1 CLK2 Active Active
Inputs Outputs
CLK1 or CLK2 Q0:Q3 Q0:Q3
0LOWHIGH
1HIGHLOW
Enabled
Disabled
CLK1, CLK2
CLK_EN
Q0:Q3
Q0:Q3
ICS8545I
LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
IDT™ / ICS™
LVDS FANOUT BUFFER 4
ICS8545BGI REV. B MARCH 02, 2009
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Item Rating
Supply Voltage, VDD 4.6V
Inputs, VI-0.5V to VDD + 0.5V
Outputs, IO
Continuos Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA 73.2°C/W (0 lfpm)
Storage Temperature, TSTG -65°C to 150°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Positive Supply Voltage 3.135 3.3 3.465 V
IDD Power Supply Current 52 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH Input High Voltage 2 VDD + 0.3 V
VIL
Input Low
Voltage
CLK1, CLK2 -0.3 1.3 V
OE, CLK_EN, CLK_SEL -0.3 0.8 V
IIH
Input
High Current
CLK1, CLK2,
CLK_SEL VDD = VIN = 3.465V 150 µA
OE, CLK_EN VDD = VIN = 3.465V 5µA
IIL
Input
Low Current
CLK1, CLK2,
CLK_SEL VDD = 3.465V, VIN = 0V -5 µA
OE, CLK_EN VDD = 3.465V, VIN = 0V -150 µA
ICS8545I
LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
IDT™ / ICS™
LVDS FANOUT BUFFER 5
ICS8545BGI REV. B MARCH 02, 2009
Table 4C. LVDS DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
AC Electrical Characteristics
Table 5. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
All parameters measured at ƒ ≤ 650MHz unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDD/2 of the input to the differential output crossing point.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOD Differential Output Voltage 200 280 360 mV
∆VOD VOD Magnitude Change 40 mV
VOS Offset Voltage 1.125 1.25 1.375 V
∆VOS VOS Magnitude Change 5 25 mV
IOz High Impedance Leakage -10 ±1 +10 µA
IOFF Power Off Leakage -20 ±1 +20 µA
IOSD Differential Output Short Circuit Current -3.5 -5 mA
IOS Output Short Circuit Current -3.5 -5 mA
VOH Output Voltage High 1.34 1.6 V
VOL Output Voltage Low 0.9 1.06 V
Parameter Symbol Test Conditions Minimum Typical Maximum Units
fMAX Output Frequency 650 MHz
tPD Propagation Delay; NOTE 1 ƒ ≤ 650MHz 1.4 3.6 ns
tjit Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
156.25MHz, Integration Range:
12kHz – 20MHz 0.13 ps
tsk(o) Output Skew; NOTE 2, 4 40 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4 500 ps
tR / tFOutput Rise/Fall Time 20% to 80% @ 50MHz 200 400 700 ps
odc Output Duty Cycle ƒ ≤ 266MHz 45 55 %
ƒ > 266MHz 40 60 %
ICS8545I
LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
IDT™ / ICS™
LVDS FANOUT BUFFER 6
ICS8545BGI REV. B MARCH 02, 2009
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
to the power in the fundamental. When the required offset is
specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The device
meets the noise floor of what is shown, but can actually be lower.
The phase noise is dependant on the input source and
measurement equipment.
SSB Phase Noise dBc/Hz
Offset Frequency (Hz)
ICS8545I
LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
IDT™ / ICS™
LVDS FANOUT BUFFER 7
ICS8545BGI REV. B MARCH 02, 2009
Parameter Measurement Information
3.3V LVDS Output Load AC Test Circuit
Part-to-Part Skew
Output Duty Cycle/Pulse Width/Period
Differential Output Level
Output Skew
Propagation Delay
SCOPE
Qx
nQx
LVDS
3.3V±5%
POWER SUPPLY
+–
Float GND
VDD
Qx
Qx
Qy
Qy
tsk(pp)
Part 1
Part 2
Q0:Q3
Q0:Q3
t
PW
tPERIOD
t
PW
t
PERIOD
odc = x 100%
VDD
GND
Q0:Q3
Q0:Q3
V
CMR
Cross Points
V
PP
Qx
Qx
Qy
Qy
tsk(o)
CLK1,
CLK2
tPD
Q0:Q3
Q0:Q3
ICS8545I
LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
IDT™ / ICS™
LVDS FANOUT BUFFER 8
ICS8545BGI REV. B MARCH 02, 2009
Parameter Measurement Information, continued
Output Rise/Fall Time
Offset Voltage Setup
High Impedance Leakage Current Setup
Power Off Leakage Setup
Differential Output Voltage Setup
Differential Output Short Circuit Setup
Clock
Outputs 20%
80% 80%
20%
t
R
t
F
V
OD
out
out
LVDS
DC Input
➤
➤
➤
VOS/∆ VOS
VDD
out
out
LVDS
DC Inpu
t
➤
➤
3.3V±5% POWER SUPPLY
Float GND
+_
I
OZ
I
OZ
LVDS
➤
IOFF
VDD
➤
➤
➤
100
out
out
LVDS
DC Input VOD/∆ VOD
VDD
out
out
LVDS
DC Input
➤
IOSD
VDD
ICS8545I
LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
IDT™ / ICS™
LVDS FANOUT BUFFER 9
ICS8545BGI REV. B MARCH 02, 2009
Parameter Measurement Information, continued
Output Short Circuit Current Setup
Application Information
Recommendations for Unused Input and Output Pins
Inputs:
CLK Inputs
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the CLK input to ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
Outputs:
LVDS Outputs
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, there should
be no trace attached.
out
LVDS
DC Input
➤
IOS
➤
IOSB
VDD
out
ICS8545I
LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
IDT™ / ICS™
LVDS FANOUT BUFFER 10
ICS8545BGI REV. B MARCH 02, 2009
3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 2. In a 100Ω
differential transmission line environment, LVDS drivers require a
matched load termination of 100Ω across near the receiver input.
For a multiple LVDS outputs buffer, if only partial outputs are used,
it is recommended to terminate the unused outputs.
Figure 2. Typical LVDS Driver Termination
3.3V
LVDS Driver
R1
100Ω
–
+
3.3V 50Ω
50Ω
100Ω Differential Transmission Line
ICS8545I
LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
IDT™ / ICS™
LVDS FANOUT BUFFER 11
ICS8545BGI REV. B MARCH 02, 2009
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8545I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8545I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 52mA = 180.18mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate
air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.180W * 66.6°C/W = 97°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 6. Thermal Resitance θJA for 20 Lead TSSOP, Forced Convection
θJA by Velocity
Linear Feet per Minute 0200500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
ICS8545I
LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
IDT™ / ICS™
LVDS FANOUT BUFFER 12
ICS8545BGI REV. B MARCH 02, 2009
Reliability Information
Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP
Transistor Count
The transistor count for ICS8545I is: 644
Package Outline and Package Dimensions
Package Outline - G Suffix for 20 Lead TSSOP Table 8. Package Dimensions
Reference Document: JEDEC Publication 95, MO-153
θJA by Velocity
Linear Feet per Minute 0200500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
All Dimensions in Millimeters
Symbol Minimum Maximum
N20
A1.20
A1 0.05 0.15
A2 0.80 1.05
b0.19 0.30
c0.09 0.20
D6.40 6.60
E6.40 Basic
E1 4.30 4.50
e0.65 Basic
L0.45 0.75
α0° 8°
aaa 0.10
ICS8545I
LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
IDT™ / ICS™
LVDS FANOUT BUFFER 13
ICS8545BGI REV. B MARCH 02, 2009
Ordering Information
Table 9. Ordering Information
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
Part/Order Number Marking Package Shipping Packaging Temperature
8545BGI ICS8545BGI 20 Lead TSSOP Tube -40°C to 85°C
8545BGIT ICS8545BGI 20 Lead TSSOP 2500 Tape & Reel -40°C to 85°C
8545BGILF ICS8545BGILF “Lead-Free” 20 Lead TSSOP Tube -40°C to 85°C
8545BGILFT ICS8545BGILF “Lead-Free” 20 Lead TSSOP 2500 Tape & Reel -40°C to 85°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT
product for use in life support devices or critical medical instruments.
ICS8545I
LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
IDT™ / ICS™
LVDS FANOUT BUFFER 14
ICS8545BGI REV. B MARCH 02, 2009
Revision History Sheet
Rev Table Page Description of Change Date
BT5
1
5
6
11
Features Section - added Additive Phase Jitter bullet.
AC Characteristics Table - added Additive Phase Jitter spec.
Added Additive Phase Jitter Plot.
Added Power Considerations section.
5/31/07
B T9 13 Ordering Information Table - added lead-free marking. 2/15/08
ICS8545I
LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
www.IDT.com
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
Asia
Integrated Device Technology
IDT (S) Pte. Ltd.
1 Kallang Sector, #07-01/06
Kolam Ayer Industrial Park
Singapore 349276
+65 67443356
Fax: +65 67441764
Europe
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
England
+44 (0) 1372 363 339
Fax: +44 (0) 1372 37885
idteurope@idt.com
Japan
NIPPON IDT KK
Sanbancho Tokyu, Bld. 7F,
8-1 Sanbancho
Chiyoda-ku, Tokyo 102-0075
+81 3 3221 9822
Fax: +81 3 3221 9824
