ICS8545I LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER General Description Features The ICS8545I is a low skew, high performance 1-to-4 LVCMOS/LVTTL-to-LVDS Clock Fanout HiPerClockSTM Buffer and a member of the HiPerClockSTM family of High Performance Clock Solutions from IDT. Utilizing Low Voltage Differential Signaling (LVDS) the ICS8545I provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100. The ICS8545I accepts a LVCMOS/LVTTL input level and translates it to 3.3V LVDS output levels. * * Four differential LVDS output pairs * * * * * * * * * Maximum output frequency: 650MHz ICS Guaranteed output and part-to-part skew characteristics make the ICS8545I ideal for those applications demanding well defined performance and repeatability. Q LE 00 CLK2 Pulldown 11 Output skew: 40ps (maximum) Part-to-part skew: 500ps (maximum) Propagation delay: 3.6ns (maximum) Additive phase jitter, RMS: 0.13ps (typical) Full 3.3Vsupply mode -40C to 85C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages GND CLK_EN CLK_SEL CLK1 nc CLK2 nc nD CLK1 Pulldown Translates LVCMOS/LVTTL input signals to LVDS levels Pin Assignment Block Diagram CLK_EN Pullup Two LVCMOS/LVTTL clock inputs to support redundant or selectable frequency fanout applications CLK_SEL Pulldown Q0 Q0 Q1 Q1 OE GND VDD Q2 Q2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Q0 Q0 VDD Q1 Q1 Q2 Q2 GND Q3 Q3 ICS8545I Q3 Q3 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm OE Pullup package body G Package Top View IDTTM / ICSTM LVDS FANOUT BUFFER 1 ICS8545BGI REV. B MARCH 02, 2009 ICS8545I LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Table 1. Pin Descriptions Number Name Type Description 1, 9, 13 GND Power 2 CLK_EN Input Pullup 3 CLK_SEL Input Pulldown Clock select input. When HIGH, selects CLK2 input. When LOW, selects CLK1 input. LVCMOS / LVTTL interface levels. 4 CLK1 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 5, 7 nc Unused 6 CLK2 Input Power supply ground. Synchronizing clock enable. When HIGH, clock outputs follows clock input. When LOW, Q outputs are forced low, Q outputs are forced high. LVCMOS / LVTTL interface levels. No connect. Pulldown Pullup Single-ended clock input. LVCMOS/LVTTL interface levels. Output enable. Controls enabling and disabling of outputs Q0/Q0 through Q3/Q3. LVCMOS/LVTTL interface levels. 8 OE Input 10, 18 VDD Power Positive supply pins. 11, 12 Q3, Q3 Output Differential output pair. LVDS interface levels. 14, 15 Q2, Q2 Output Differential output pair. LVDS interface levels. 16, 17 Q1, Q1 Output Differential output pair. LVDS interface levels. 19, 20 Q0, Q0 Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k IDTTM / ICSTM LVDS FANOUT BUFFER Test Conditions 2 Minimum Typical Maximum Units ICS8545BGI REV. B MARCH 02, 2009 ICS8545I LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Function Tables Table 3A. Control Input Function Table Inputs Outputs OE CLK_EN CLK_SEL 0 X X 1 0 0 1 0 1 1 Selected Source Q0:Q3 Q0:Q3 Hi-Z Hi-Z CLK1 Low High 1 CLK2 Low High 1 0 CLK1 Active Active 1 1 CLK2 Active Active After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK1 and CLK2 inputs as described in Table 3B. Enabled Disabled CLK1, CLK2 CLK_EN Q0:Q3 Q0:Q3 Figure 1. CLK_EN Timing Diagram Table 3B. Clock Input Function Table Inputs Outputs CLK1 or CLK2 Q0:Q3 Q0:Q3 0 LOW HIGH 1 HIGH LOW IDTTM / ICSTM LVDS FANOUT BUFFER 3 ICS8545BGI REV. B MARCH 02, 2009 ICS8545I LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuos Current Surge Current 10mA 15mA Package Thermal Impedance, JA 73.2C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 3.3V 5%, TA = -40C to 85C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 52 mA Maximum Units 2 VDD + 0.3 V CLK1, CLK2 -0.3 1.3 V OE, CLK_EN, CLK_SEL -0.3 0.8 V Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V 5%, TA = -40C to 85C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL Input High Current Input Low Current Test Conditions Minimum Typical CLK1, CLK2, CLK_SEL VDD = VIN = 3.465V 150 A OE, CLK_EN VDD = VIN = 3.465V 5 A CLK1, CLK2, CLK_SEL VDD = 3.465V, VIN = 0V -5 A OE, CLK_EN VDD = 3.465V, VIN = 0V -150 A IDTTM / ICSTM LVDS FANOUT BUFFER 4 ICS8545BGI REV. B MARCH 02, 2009 ICS8545I LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Table 4C. LVDS DC Characteristics, VDD = 3.3V 5%, TA = -40C to 85C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change IOz High Impedance Leakage IOFF Power Off Leakage IOSD Test Conditions Minimum Typical Maximum Units 200 280 360 mV 40 mV 1.25 1.375 V 5 25 mV -10 1 +10 A -20 1 +20 A Differential Output Short Circuit Current -3.5 -5 mA IOS Output Short Circuit Current -3.5 -5 mA VOH Output Voltage High 1.34 1.6 V VOL Output Voltage Low 1.125 0.9 1.06 V AC Electrical Characteristics Table 5. AC Characteristics, VDD = 3.3V 5%, TA = -40C to 85C Parameter Symbol fMAX Output Frequency tPD Propagation Delay; NOTE 1 tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Test Conditions Minimum 650MHz 1.4 156.25MHz, Integration Range: 12kHz - 20MHz Typical Maximum Units 650 MHz 3.6 ns 0.13 ps tsk(o) Output Skew; NOTE 2, 4 40 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 500 ps tR / tF Output Rise/Fall Time 700 ps odc Output Duty Cycle 20% to 80% @ 50MHz 200 400 266MHz 45 55 % > 266MHz 40 60 % All parameters measured at 650MHz unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2 of the input to the differential output crossing point. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. IDTTM / ICSTM LVDS FANOUT BUFFER 5 ICS8545BGI REV. B MARCH 02, 2009 ICS8545I LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band SSB Phase Noise dBc/Hz to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. Offset Frequency (Hz) meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device IDTTM / ICSTM LVDS FANOUT BUFFER 6 ICS8545BGI REV. B MARCH 02, 2009 ICS8545I LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Parameter Measurement Information VDD SCOPE Qx VDD 3.3V5% POWER SUPPLY + Float GND - Q0:Q3 V LVDS Cross Points PP V CMR Q0:Q3 nQx GND 3.3V LVDS Output Load AC Test Circuit Differential Output Level Par t 1 Qx Qx Qx Qx Qy Par t 2 Qy Qy Qy tsk(o) tsk(pp) Part-to-Part Skew Output Skew Q0:Q3 Q0:Q3 CLK1, CLK2 t PW t PERIOD Q0:Q3 t PW odc = x 100% Q0:Q3 t PERIOD tPD Output Duty Cycle/Pulse Width/Period IDTTM / ICSTM LVDS FANOUT BUFFER Propagation Delay 7 ICS8545BGI REV. B MARCH 02, 2009 ICS8545I LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Parameter Measurement Information, continued 80% 80% VOD Clock Outputs LVDS 20% 20% tF tR VDD IOFF Output Rise/Fall Time Power Off Leakage Setup VDD VDD out LVDS out out DC Input LVDS 100 VOD/ VOD VOS/ VOS out DC Input Offset Voltage Setup Differential Output Voltage Setup VDD out 3.3V5% POWER SUPPLY + Float GND _ IOZ DC Input out LVDS DC Input IOZ IOSD out out High Impedance Leakage Current Setup IDTTM / ICSTM LVDS FANOUT BUFFER LVDS Differential Output Short Circuit Setup 8 ICS8545BGI REV. B MARCH 02, 2009 ICS8545I LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Parameter Measurement Information, continued VDD out DC Input IOS LVDS IOSB out Output Short Circuit Current Setup Application Information Recommendations for Unused Input and Output Pins Inputs: Outputs: CLK Inputs LVDS Outputs For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground. All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, there should be no trace attached. LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. IDTTM / ICSTM LVDS FANOUT BUFFER 9 ICS8545BGI REV. B MARCH 02, 2009 ICS8545I LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER 3.3V LVDS Driver Termination A general LVDS interface is shown in Figure 2. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V 50 3.3V LVDS Driver + R1 100 - 50 100 Differential Transmission Line Figure 2. Typical LVDS Driver Termination IDTTM / ICSTM LVDS FANOUT BUFFER 10 ICS8545BGI REV. B MARCH 02, 2009 ICS8545I LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Power Considerations This section provides information on power dissipation and junction temperature for the ICS8545I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8545I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 52mA = 180.18mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.180W * 66.6C/W = 97C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer). Table 6. Thermal Resitance JA for 20 Lead TSSOP, Forced Convection JA by Velocity Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 114.5C/W 98.0C/W 88.0C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2C/W 66.6C/W 63.5C/W IDTTM / ICSTM LVDS FANOUT BUFFER 11 ICS8545BGI REV. B MARCH 02, 2009 ICS8545I LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Reliability Information Table 7. JA vs. Air Flow Table for a 20 Lead TSSOP JA by Velocity Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 114.5C/W 98.0C/W 88.0C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2C/W 66.6C/W 63.5C/W Transistor Count The transistor count for ICS8545I is: 644 Package Outline and Package Dimensions Package Outline - G Suffix for 20 Lead TSSOP Table 8. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0 8 aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 IDTTM / ICSTM LVDS FANOUT BUFFER 12 ICS8545BGI REV. B MARCH 02, 2009 ICS8545I LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Ordering Information Table 9. Ordering Information Part/Order Number 8545BGI 8545BGIT 8545BGILF 8545BGILFT Marking ICS8545BGI ICS8545BGI ICS8545BGILF ICS8545BGILF Package 20 Lead TSSOP 20 Lead TSSOP "Lead-Free" 20 Lead TSSOP "Lead-Free" 20 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDTTM / ICSTM LVDS FANOUT BUFFER 13 ICS8545BGI REV. B MARCH 02, 2009 ICS8545I LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Revision History Sheet Rev B B Table T5 T9 Page Description of Change Date 1 5 6 11 Features Section - added Additive Phase Jitter bullet. AC Characteristics Table - added Additive Phase Jitter spec. Added Additive Phase Jitter Plot. Added Power Considerations section. 5/31/07 13 Ordering Information Table - added lead-free marking. 2/15/08 IDTTM / ICSTM LVDS FANOUT BUFFER 14 ICS8545BGI REV. B MARCH 02, 2009 ICS8545I LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 netcom@idt.com 480-763-2056 Corporate Headquarters Asia Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology IDT (S) Pte. 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