1
®
FN6032.1
ISL43140, ISL43141, ISL43142
Low-Voltage, Single and Dual Supply,
High Performance, Quad SPST, Analog
Switches
The Intersil ISL43140–ISL43142 devices are CMOS,
precision, quad analog switches designed to o perate from a
single +2V to +12V supply or from a ±2V to ±6V supply.
Targeted applications include ba ttery powered equipment that
benefit from the devices’ low powe r consumption (1µW), low
leakage currents (1nA max), and fa st switching speeds
(tON = 30ns, tOFF = 18ns). A 12Ω maximum RON flatness
ensures signal fidelity, while cha nnel-to-ch annel mi smatch is
guaranteed to be less than 2.5Ω. The 3mm x 3mm Quad No-
Lead Flatpack (QFN) package alleviates board space
limitations, making this newest line of low-vo ltage switches an
ideal solution.
The ISL43140/ISL43141/ISL43142 are qu ad single -pole/
single-throw (SPST) device s. The ISL43140 has four normally
closed (NC) switches; the ISL43141 has four normally open
(NO) switches; the ISL43142 has two NO and two NC
switches and can be used as a dual SPDT, or a dual 2:1
multiplexer.
Table 1 summarizes the performance of this family.
TABLE 1. FEATURES AT A GLANCE
Features
• Fully Specified at ±5V, 12V, 5V, and 3V Supplies for 10%
Tolerances
• Four Separately Controlled SPST Switches
• Pin Compatible with DG411/DG412/DG413
• ON Resistance (RON) . . . . . . . . . . . . . . . . . . . . . . . . 50Ω
•R
ON Matching Between Channels. . . . . . . . . . . . . . . . . . . 2Ω
• Low Charge Injection . . . . . . . . . . . . . . . . . . . . . . 5pC (Max)
• Low Power Consumption (PD). . . . . . . . . . . . . . . . . . . .<1µW
• Low Leakage Current (Max at 85°C) . . . . . . . . . . . . . 5nA
• Fast Switching Action
-t
ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30ns
-t
OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18ns
• Guaranteed Break-Before-Make (ISL43142 only)
• Minimum 2000V ESD Protection per Method 3015.7
• TTL, CMOS Compatible
• Pb-free Available
Applications
• Battery Powered, Handheld, and Portable Equipment
- Cellula r/Mobile Phones
- Pagers
- Laptops, Notebooks, Palmtops
• Communications Systems
- Military Radios
- RF “Tee” Switches
• Test Equipment
- Ultrasound
- Electrocardiograph
• Heads-Up Displays
• Audio and Video Switching
• General Purpose Circuits
- +3V/+5V DACs and ADCs
- Digital Filters
- Operational Amplifier Gain Switching Networks
- High Freq uency Analog Switching
- High Speed Multiplexing
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mo unt Devices
(SMDs)”
ISL43140 ISL43141 ISL43142
Number of Switches 4 4 4
Configuration All NC All NO 2 NC / 2 NO
10.8V RON 50Ω50Ω50Ω
10.8V tON / tOFF 30ns / 18ns 30ns / 18ns 30ns / 18ns
±4.5V RON 50Ω50Ω50Ω
±4.5V tON / tOFF 40ns / 15ns 40ns / 15ns 40ns / 15ns
4.5V RON 110Ω110Ω110Ω
4.5V tON / tOFF 50ns / 20ns 50ns / 20ns 50ns / 20ns
2.7V RON 200Ω200Ω200Ω
2.7V tON / tOFF 120ns / 25ns 120ns / 25ns 120ns / 25ns
Packages 16 Ld SOIC (N), 16 Ld 3x3 QFN,
16 Ld TSSOP
Data Sheet July 2004
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2
Pinouts (Note 1)
ISL43140 (SOIC, TSSOP)
TOP VIEW ISL43140 (QFN)
TOP VIEW
ISL43141 (SOIC, TSSOP)
TOP VIEW ISL43141 (QFN)
TOP VIEW
ISL43142 (SOIC, TSSOP)
TOP VIEW ISL43142 (QFN)
TOP VIEW
NOTE:
1. Switches Shown for Logic “0” Input.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
IN1
COM1
NC1
V-
GND
NC4
IN4
COM4
IN2
NC2
V+
N.C.
NC3
COM3
IN3
COM2
1
3
4
15
NC1
V-
GND
NC4
COM1
IN1
IN2
COM2
16 14 13
2
12
10
9
11
6578
NC2
V+
N.C.
NC3
COM4
IN4
IN3
COM3
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
IN1
COM1
NO1
V-
GND
NO4
IN4
COM4
IN2
NO2
V+
N.C.
NO3
COM3
IN3
COM2
1
3
4
15
NO1
V-
GND
NO4
COM1
IN1
IN2
COM2
16 14 13
2
12
10
9
11
6578
NO2
V+
N.C.
NO3
COM4
IN4
IN3
COM3
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
IN1
COM1
NO1
V-
GND
NO4
IN4
COM4
IN2
NC2
V+
N.C.
NC3
COM3
IN3
COM2
1
3
4
15
NO1
V-
GND
NO4
COM1
IN1
IN2
COM2
16 14 13
2
12
10
9
11
6578
NC2
V+
N.C.
NC3
COM4
IN4
IN3
COM3
ISL43140, ISL43141, ISL43142
3
Truth Table
LOGIC
ISL43140 ISL43141 ISL43142
SW 1, 2, 3, 4 SW 1, 2, 3, 4 SW 1, 4 SW 2, 3
0ON OFFOFFON
1 OFF ON ON OFF
NOTE: Logic “0” ≤ 0.8V. Logic “1” ≥ 2.4V.
Pin Descriptions
PIN FUNCTION
V+ Positive Power Supply Input
V- Negative Power Supply Input. Connect to GND for
Single Supply Configurations.
GND Ground Connection
IN Digital Control Input
COM Analog Switch Common Pin
NO Analog Switch Normally Open Pin
NC Analog Switch Normally Closed Pin
N.C. No Internal Connection
Ordering Information
PART NO.
(BRAND)
(NOTE 2) TEMP.
RANGE (°C) PACKAGE PKG.
DWG. #
ISL43140IB -40 to 85 16 Ld SOIC (N) M16.15
ISL43140IBZ
(Note 3) -40 to 85 16 Ld SOIC (N) (Pb-free) M16.15
ISL43140IR
(140I) -40 to 85 16 Ld QFN L16.3x3
ISL43140IRZ
(140I) (Note 3) -40 to 85 16 Ld QFN (Pb-free) L16.3x3
ISL43140IV -40 to 85 16 Ld TSSOP M16.173
ISL43140IVZ
(Note 3) -40 to 85 16 Ld TSSOP (Pb-free) M16.173
ISL43141IB -40 to 85 16 Ld SOIC (N) M16.15
ISL43141IBZ
(Note 3) -40 to 85 16 Ld SOIC (N) (Pb-free) M16.15
ISL43141IR
(141I) -40 to 85 16 Ld QFN L16.3x3
ISL43141IRZ
(141I) (Note 3) -40 to 85 16 Ld QFN (Pb-free) L16.3x3
ISL43141IV -40 to 85 16 Ld TSSOP M16.173
ISL43141IVZ
(Note 3) -40 to 85 16 Ld TSSOP (Pb-free) M16.173
ISL43142IB -40 to 85 16 Ld SOIC (N) M16.15
ISL43142IBZ
(Note 3) -40 to 85 16 Ld SOIC (N) (Pb-free) M16.15
ISL43142IR
(142I) -40 to 85 16 Ld QFN L16.3x3
ISL43142IRZ
(142I) (Note 3) -40 to 85 16 Ld QFN (Pb-free) L16.3x3
ISL43142IV -40 to 85 16 Ld TSSOP M16.173
ISL43142IVZ
(Note 3) -40 to 85 16 Ld TSSOP (Pb-free) M16.173
NOTES:
2. Most surface mount devices are available on tape and reel; add
“-T” to suffix.
3. Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
ISL43140, ISL43141, ISL43142
4
Absolute Maximum Ratings Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V
V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to 0.3V
All Other Pins (Note 4). . . . . . . . . . . . . ((V-) - 0.3V) to ((V+) + 0.3V)
Continuous Current (Any Terminal). . . . . . . . . . . . . . . . . . . . . 10mA
Peak Current, IN, NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . 20mA
ESD Rating (Per MIL-STD-883 Method 3015). . . . . . . . . . . . . .>2kV
Operating Conditions
Temperature Range
ISL4314XIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85° C
Thermal Resistance (Typical, Note 5) θJA (°C/W)
16 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 115
16 Ld QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . 75
16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 150
Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Moisture Sensitivity (See Technical Brief TB363)
All Other Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 2
Maximum Storage Temperature Range. . . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . 300°C
(SOIC and TSSOP - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operat i onal sections of this specification is not implied.
NOTES:
4. Signals on NC, NO, COM, or IN exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum current ratings.
5. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications: ±5V Supply Test Conditions VSUPPLY = ±4.5V to ±5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 6),
Unless Otherwise Specified
PARAMETER TEST CONDITIONS TEMP
(°C) (NOTE 7)
MIN TYP (NOTE 7)
MAX UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG Full V- - V+ V
ON Resistance, RON VS = ±4.5V, ICOM = 1.0mA, VNO or VNC = ±3V,
See Figure 5 25 - 50 65 Ω
Full - - 75 Ω
RON Matching Between Channels,
∆RON VS = ±4.5V, ICOM = 1.0mA, VNO or VNC = ±3V 25 - 2 2.5 Ω
Full - - 5 Ω
RON Flatness, RFLAT(ON) VS = ±4.5V, ICOM = 1.0mA, VNO or VNC = ±3V, Note 9 25 - 10 12 Ω
Full - - 13 Ω
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF) VS = ±5.5V, VCOM = ±4.5V, VNO or VNC = +4.5V,
Note 8 25 -1 0.01 1 nA
Full -5 - 5 nA
COM OFF Leakage Current,
ICOM(OFF) VS = ±5.5V, VCOM = ±4.5V, VNO or VNC = +4.5V,
Note 8 25 -1 0.01 1 nA
Full -5 - 5 nA
COM ON Leakage Current,
ICOM(ON) VS = ±5.5V, VCOM = VNO or VNC = ±4.5V, Note 8 25 -2 0.01 2 nA
Full -10 - 10 nA
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, VINH Full 2.4 1.6 - V
Input Voltage Low, VINL Full - 1.6 0.8 V
Input Current, IINH, IINL VS = ±5.5V, VIN = 0V or V+ Full -0.5 0.03 0.5 µA
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON VS = ±4.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3V, See Figure 1 25 - 40 80 ns
Full - - 100 ns
Turn-OFF Time, tOFF VS = ±4.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3V, See Figure 1 25 - 15 30 ns
Full - - 40 ns
Break-Before-Make Time De la y
(ISL43142), tDVS = ±5.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3V, See Figure 3 Full 5 20 - ns
Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, See Figure 2 25 - 1 5 pC
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 7 - pF
COM OFF Capacitance,
CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 7 - pF
COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 14 - pF
ISL43140, ISL43141, ISL43142
5
OFF Isolation RL = 50Ω, CL = 15pF, f = 100kHz,
VNO or VNC = 1VRMS, See Figures 4, 6, and 19 25 - >90 - dB
Crosstalk, Note 10 25 - <-90 - dB
All Hostile Crosstalk RL = 50Ω, CL = 15pF, f = 10MHz,
VNO or VNC = 1VRMS, See Figure 19 25 - -60 - dB
Power Supply Rejection Ratio RL = 50Ω, CL = 15pF, f = 1MHz, See Figure 20 25 - 60 - dB
POWER SUPPLY CHARACTERISTICS
Power Supply Range Full ±2-±6V
Positive Supply Current, I+ VS = ±5.5V, VIN = 0V or V+, Switch On or Off 25 -1 0.05 1 µA
Full -1 - 1 µA
Negative Supply Current, I- 25 -1 0.05 1 µA
Full -1 - 1 µA
NOTES:
6. VIN = Input voltage to perform proper function.
7. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
8. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at 25°C.
9. Flatness is defined as the delta between the maximum and minimum RON values over the specified voltage range.
10. Between any two switches.
Electrical Specifications: 12V Supply Test Conditions: V+ = +10.8V to +13.2V, V- = GND = 0V, VINH = 5V, VINL = 0.8V (Note 6),
Unless Otherwise Specified
PARAMETER TEST CONDITIONS TEMP
(°C) (NOTE 7)
MIN TYP (NOTE 7)
MAX UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG Full 0 - V+ V
ON Resistance, RON V+ = 10.8V, ICOM = 1.0mA, VNO or VNC = 9 V,
See Figure 5 25 - 50 65 Ω
Full - 60 75 Ω
RON Matching Between Channels,
∆RON V+ = 10.8V, ICOM = 1.0mA, VNO or VNC = 9V 25 - 2 2.5 Ω
Full - - 5 Ω
RON Flatness, RFLAT(ON) V+ = 10.8V, ICOM = 1.0mA, VNO or VNC = 3V, 6V, 9V,
Note 9 25 - 8 12 Ω
Full - 9 13 Ω
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF) V+ = 13.2V, VCOM = 1V, 10V, VNO or VNC = 10 V, 1V,
Note 8 25 -1 - 1 nA
Full -5 - 5 nA
COM OFF Leakage Current,
ICOM(OFF) V+ = 13.2V, VCOM = 10V, 1V, VNO or VNC = 1V , 1 0V,
Note 8 25 -1 - 1 nA
Full -5 - 5 nA
COM ON Leakage Current,
ICOM(ON) V+ = 13.2V, VCOM = 1V, 10V, or VNO or VNC = 1V,
10V, Note 8 25 -2 - 2 nA
Full -10 - 10 nA
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, VINH Full 3.5 3.1 - V
Input Voltage Low, VINL Full - - 0.8 V
Input Current, IINH, IINL V+ = 13.2V, VIN = 0V or V+ Full -1 - 1 µA
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON V+ = 10.8V, VNO or VNC = 10V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3.3V, See Figure 1 25 - 30 70 ns
Full - 34 100 ns
Turn-OFF Time, tOFF V+ = 10.8V, VNO or VNC = 10V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3.3V, See Figure 1 25 - 18 50 ns
Full - 20 75 ns
Break-Before-Make Time De la y
(ISL43142), tDV+ = 13. 2V, VNO or VNC = 10V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3.3V, See Figure 3 Full 0 8 - ns
Electrical Specifications: ±5V Supply Test Conditions VSUPPLY = ±4.5V to ±5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 6),
Unless Otherwise Specified (Continued)
PARAMETER TEST CONDITIONS TEMP
(°C) (NOTE 7)
MIN TYP (NOTE 7)
MAX UNITS
ISL43140, ISL43141, ISL43142
6
Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, See Figure 2 25 - 5 15 pC
OFF Isolation RL = 50Ω, CL = 15pF, f = 100kHz,
VNO or VNC = 1VRMS, See Figures 4, 6, and 19 25 - >90 - dB
Crosstalk, Note 10 25 - <-90 - dB
All Hostile Crosstalk RL = 50Ω, CL = 15pF, f = 10MHz,
VNO or VNC = 1VRMS, See Figure 19 25 - -60 - dB
Power Supply Rejection Ratio RL = 50Ω, CL = 15pF, f = 1MHz, See Figure 20 25 - 60 - dB
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 7 - pF
COM OFF Capacitance,
CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 7 - pF
COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 14 - pF
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+ V+ = 13.2V, VIN = 0V or V+, Switch On or Off 25 -1 0.05 1 µA
Full -1 - 1 µA
Negative Supply Current, I- 25 -1 0.05 1 µA
Full -1 - 1 µA
Electrical Specifications: 5V Supply Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 6),
Unless Otherwise Specified
PARAMETER TEST CONDITIONS TEMP
(°C) MIN
(NOTE 7) TYP MAX
(NOTE 7)UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG Full 0 - V+ V
ON Resistance, RON V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3.5V,
See Figure 5 25 - 110 120 Ω
Full - - 150 Ω
RON Matching Between Channels,
∆RON V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3.5V 25 - 1.5 2 Ω
Full - - 5 Ω
RON Flatness, RFLAT(ON) V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 1.5V to 4.5V,
Note 9 25 - 12 16 Ω
Full - - 20 Ω
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF) V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 4.5V, 1V,
Note 8 25 -1 0.01 1 nA
Full -5 - 5 nA
COM OFF Leakage Current,
ICOM(OFF) V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 4.5V, 1V,
Note 8 25 -1 0.01 1 nA
Full -5 - 5 nA
COM ON Leakage Current,
ICOM(ON) V+ = 5.5V, VCOM = 1V, 4.5V, Note 8 25 -2 - 2 nA
Full -10 - 10 nA
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, VINH Full 2.4 1.6 - V
Input Voltage Low, VINL Full - 1.6 0.8 V
Input Current, IINH, IINL V+ = 5.5V, VIN = 0V or V+ Full -0.5 0.03 0.5 µA
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3V, See Figure 1 25 - 50 100 ns
Full - - 150 ns
Turn-OFF Time, tOFF V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3V, See Figure 1 25 - 20 50 ns
Full - - 75 ns
Break-Before-Make Time De la y
(ISL43142), tDV+ = 5. 5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3V, See Figure 3 Full 10 30 - ns
Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, See Figure 2 25 - 1 5 pC
OFF Isolation RL = 50Ω, CL = 15pF, f = 100kHz,
VNO or VNC = 1VRMS, See Figures 4, 6, and 19 25 - >90 - dB
Crosstalk, Note 10 25 - <-90 - dB
Electrical Specifications: 12V Supply Test Conditions: V+ = +10.8V to +13.2V, V- = GND = 0V, VINH = 5V, VINL = 0.8V (Note 6),
Unless Otherwise Specified (Continued)
PARAMETER TEST CONDITIONS TEMP
(°C) (NOTE 7)
MIN TYP (NOTE 7)
MAX UNITS
ISL43140, ISL43141, ISL43142
7
All Hostile Crosstalk RL = 50Ω, CL = 15pF, f = 10MHz,
VNO or VNC = 1VRMS, See Figure 19 25 - -60 - dB
Power Supply Rejection Ratio RL = 50Ω, CL = 15pF, f = 1MHz, See Figure 20 25 - 60 - dB
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 7 - pF
COM OFF Capacitance,
CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 7 - pF
COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 14 - pF
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+ V+ = 5.5V, VIN = 0V or V+, Switch On or Off 25 -1 0.05 1 µA
Full -1 - 1 µA
Negative Supply Current, I- 25 -1 0.05 1 µA
Full -1 - 1 µA
Electrical Specifications: 3V to 3.3V Supply Test Conditions: V+ = +2.7V to +3.6V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V
(Note 6), Unless Otherwise Specified
PARAMETER TEST CONDITIONS TEMP
(°C) MIN
(NOTE 7) TYP MAX
(NOTE 7)UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG Full 0 - V+ V
ON Resistance, RON V+ = 2.7V, ICOM = 1.0mA, VNO or VNC = 1V,
See Figure 5 25 - 200 250 Ω
Full - - 270 Ω
RON Matching Between Channels,
∆RON V+ = 2.7V, ICOM = 1.0mA, VNO or VNC = 1V 25 - 2 4 Ω
Full - - 6 Ω
RON Flatness, RFLAT(ON) V+ = 2.7V, ICOM = 1.0mA, VNO or VNC = 0.5V to 1.5V,
Note 9 25 - 80 100 Ω
Full - - 120 Ω
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF) V+ = 3.6V, VCOM = 1V, 2.6V, VNO or VNC = 2.6V, 1V,
Note 8 25 -1 0.01 1 nA
Full -5 - 5 nA
COM OFF Leakage Current,
ICOM(OFF) V+ = 3.6V, VCOM = 1V, 2.6V, VNO or VNC = 2.6V, 1V,
Note 8 25 -1 0.01 1 nA
Full -5 - 5 nA
COM ON Leakage Current,
ICOM(ON) V+ = 3.6V, VCOM = 1V, 2.6V, Note 8 25 -2 - 2 nA
Full -10 - 10 nA
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, VINH Full 2.4 1.6 - V
Input Voltage Low, VINL Full - 1.6 0.8 V
Input Current, IINH, IINL V+ = 3.6V, VIN = 0V or V+ Full -0.5 0.03 0.5 µA
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON V+ = 2.7V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF,
VIN = 0 to V+, See Figure 1 25 - 120 180 ns
Full - - 220 ns
Turn-OFF Time, tOFF V+ = 2.7V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF,
VIN = 0 to V+, See Figure 1 25 - 25 45 ns
Full - - 60 ns
Break-Before-Make Time De la y
(ISL43142), tDV+ = 3.6V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF,
VIN = 0 to 3V, See Figure 3 25 15 50 - ns
Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, See Figure 2 25 - 0.5 5 pC
OFF Isolation RL = 50Ω, CL = 15pF, f = 100kHz,
VNO or VNC = 1VRMS, See Figures 4, 6, and 19 25 - >90 - dB
Crosstalk, Note 10 25 - <-90 - dB
All Hostile Crosstalk RL = 50Ω, CL = 15pF, f = 10MHz,
VNO or VNC = 1VRMS, See Figure 19 25 - -60 - dB
Power Supply Rejection Ratio RL = 50Ω, CL = 15pF, f = 1MHz, See Figure 20 25 - 60 - dB
Electrical Specifications: 5V Supply Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 6),
Unless Otherwise Specified (Continued)
PARAMETER TEST CONDITIONS TEMP
(°C) MIN
(NOTE 7) TYP MAX
(NOTE 7)UNITS
ISL43140, ISL43141, ISL43142
8
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 7 - pF
COM OFF Capacitance,
CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 7 - pF
COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 14 - pF
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+ V+ = 3.6V, VIN = 0V or V+, Switch On or Off 25 -1 0.05 1 µA
Full -1 - 1 µA
Negative Supply Current, I- 25 -1 0.05 1 µA
Full -1 - 1 µA
Test Circuits and Waveforms
Logic input waveform is inverted for switches that have the opposite
logic sense.
FIGURE 1A. MEASUREMENT POINTS
Repeat test for all switches. CL includes fixture and stray
capacitance.
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
Logic input waveform is inverted for switches that have the opposite
logic sense.
FIGURE 2A. MEASUREMENT POINTS
Repeat test for all switches. CL includes fixture and stray
capacitance. FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
Electrical Specifications: 3V to 3.3V Supply Test Conditions: V+ = +2.7V to +3.6V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V
(Note 6), Unless Otherwise Specified (Continued)
PARAMETER TEST CONDITIONS TEMP
(°C) MIN
(NOTE 7) TYP MAX
(NOTE 7)UNITS
50%
tr < 20ns
tf < 20ns
tOFF
90%
3V
0V
VNX
0V
tON
LOGIC
INPUT
SWITCH
INPUT
SWITCH
OUTPUT
90%
VOUT
VOUT V(NO or NC) RL
RLRON()
+
------------------------------
=
SWITCH
INPUT
LOGIC
INPUT
VOUT
RL CL
COM
NO or NC
IN
300Ω35pF
GND
V+ C
V- C
VNX
C
VOUT
∆VOUT
ON OFF ON
Q = ∆VOUT x CL
SWITCH
OUTPUT
LOGIC
INPUT
3V
0V CL
VOUT
RG
VGGND
COM
NO or NC
V+ C
LOGIC
INPUT
IN
CV-
ISL43140, ISL43141, ISL43142
9
FIGURE 3A. MEASUREMENT POINTS
CL includes fixture and stray capacitance.
Reconfigure accordingly to test SW3 and SW4.
FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME (ISL43142 ONLY)
Repeat test for all switches.
FIGURE 4. OFF ISOLATION TEST CIRCUIT
Repeat test for all switches.
FIGURE 5. RON TEST CIRCUIT
FIGURE 6. CROSSTALK TEST CIRCUIT FIGURE 7. CAPACITANCE TEST CIRCUIT
Test Circuits and Waveforms (Co ntinued)
90%
3V
0V
tD
0V
LOGIC
INPUT
SWITCH
OUTPUT
SWITCH
OUTPUT
90%
tD
0V
VOUT1
VOUT2
90%
90% LOGIC
INPUT
IN1
COM1 RL1 CL1
VOUT1
300Ω
35pF
COM2
RL2 CL2
VOUT2 300Ω
35pF
NO1
NC2
GND
IN2
VNX
V+ C
C
V-
C
ANALYZER
RL
SIGNAL
GENERATOR
V+ C
0V or 2.4V
NO or NC
COM
IN
GND
C
V-
V+
C
0.8V or 2.4V
NO or NC
COM
IN
GND
VNX
V1
RON = V1/1mA
1mA
C
V-
0V or 2.4V
ANALYZER
V+
C
NO1 or NC1
SIGNAL
GENERATOR
RLGND
IN1
COM1
IN2
50Ω
0V or 2.4V
NO
COM2 NO2 or NC2
C
V-
CONNECTION
V+
GND
NO or NC
COM
IN
IMPEDANCE
ANALYZER
0V or 2.4V
V-
ISL43140, ISL43141, ISL43142
10
Detailed Description
The ISL43140–ISL43142 quad analog switches offer precise
switching capability from a bipolar ±2V to ±6V or a single 2V
to 12V supply with low on-resistance (50Ω) and high speed
switching (tON = 40ns, tOFF = 15ns). The devices are
especially well suited to portable battery powered equipment
thanks to the low operating supply voltage (2V), low power
consumption (1µW), low leakage currents (1nA max), and the
tiny QFN packaging. High frequency app lications also benefit
from the wide bandwidth, and the very high off isolation and
crosstalk rejection.
Supply Sequencing And Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to V- (see
Figure 8). To prevent forward biasing these diodes, V+ an d
V- must be applied before any input signals, and input signal
voltages must remain between V+ and V-. If these conditions
cannot be guaranteed, then one of th e following two
protection methods should be employed.
Logic inputs can easily be protected by adding a 1kΩ
resistor in series with the input (see Figure 8). The resisto r
limits the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
Adding a series resistor to the switch input defeats the
purpose of using a low RON switch, so two small signal
diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (see Figure 8). These
additional diodes limit the analog signal from 1V below V+ to
1V above V-. The low leakage current performance is
unaffected by this approach, but the switch resistance may
increase, especially at low supply voltages.
Power-Supply Considerations
The ISL4314X construction is typical of most CMOS analog
switches, in that they have three supply pins: V+, V-, and
GND. V+ and V- drive the internal CMOS switches and set
their analog voltage limits, so there are no connections
between the analog signal path and GND. Unlike switches
with a 13V maximum supply voltage, the ISL4314X 15V
maximum supply voltage provides plenty of room for the
10% tolerance of 12V supplies (±6V or 12V single supply),
as well as room for overshoot and noise spikes.
This family of switches performs equally well when operated
with bipolar or single voltage supplies. The ad dition of the
GND pin allows for asymmetrical bipolar supplies (e.g. +5V
and -3V). The minimum recommended supply voltage is 2V
or ±2V. It is important to note that the input signal range,
switching times, and on-resistance degrade at lower supply
voltages. Refer to the electrical specification tables and
Typical Performance Curves for details.
V+ and GND po wer th e in tern al lo gic (th us se ttin g the d igi tal
switching point) and level shifters. The level shifters convert
the logic levels to switched V+ and V- signals to dri v e the
analog switch gate terminals, so switch parameters -
especially RON - are strongly influenced by V-.
Logic-Level Thresholds
V+ and GND power the internal logic stages, so V- has no
affect on logic thresholds. This switch family is TTL
compatible (0.8V and 2.4V) over a V+ supply range of 2.5V
to 10V (see Figure 17). At 12V the VIH level is about 2.7V,
so for best results use a logic family the provides a VOH
greater than 3V.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
High-Frequency Performance
In 50Ω systems, signal response is reasonably flat even past
100MHz (see Figure 18). Figure 18 also illustrates that the
frequency response is very consistent over a wide V+ range,
and for varying analog signal levels.
An off switch acts like a capacitor and passes higher
frequencies with less attenuatio n, resulting in signal
feedthrough from a switch’s input to its output. Off Isolation
is the resistance to this feedthrough, whi le Crosstalk
indicates the amount of feedthrough from one switch to
another. Figure 19 details the high Off Isolation and
Crosstalk rejection provided by this family. At 10MHz, off
isolation is about 50dB in 50Ω systems, decreasing
approximately 20dB per decade as frequency increases.
Higher load impedances decrease Off Isolation and
Crosstalk rejection due to the voltage divider action of the
switch OFF impedance and the load imp edance.
FIGURE 8. OVERVOLTAGE PROTECTION
V-
VCOM
VNO or NC
OPTIONAL PROTECTION
V+
INX
DIODE
OPTIONAL PROTECTION
DIODE
OPTIONAL
PROTECTION
RESISTOR
ISL43140, ISL43141, ISL43142
11
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and V-. One
of these diodes conducts if any analog signal exceeds V+
or V-.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or V-. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or V- and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and V- pins constitutes the analog-signal-
path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection betwe en the analog signal
paths and GND.
Typical Performance Curves TA = 25°C, Unless Otherwise Specified
FIGURE 9. ON RESISTANCE vs POSITIVE SUPPLY VOLTAGE FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE
RON (Ω)
V+ (V)
24681012
0
50
100
150
200
250
300
35791113
-40°C
85°C 25°C
V- = 0V
40
60
80
100
120
50
60
70
80
90
100
40
V- = -3V
V- = -5V VCOM = (V+) - 1V
ICOM = 1mA
-40°C
85°C
25°C
-40°C
85°C
25°C
RON (Ω)
VCOM (V)
024681012
20
30
40
50
60
70
80
1357911
-40°C
85°C V+ = 12V
V- = 0V
55
75
95
115
135
50
100
150
200
250
25°C
V+ = 3V
V+ = 5V
25°C
-40°C
85°C
25°C
-40°C
85°C
V- = 0V
V- = 0V ICOM = 1mA
RON (Ω)
VCOM (V)
-4-2024
30
50
70
90
-5 -3 -1 1 3 5
VS = ±5V
40
60
80
100
120 VS = ±3V
60
100
140
180 ICOM = 1mA VS = ±2V
25°C
85°C
25°C
-40°C
85°C
25°C
-40°C
85°C
-40°C
Q (pC)
VCOM (V)
-5 0 5 10
-10
-5
0
5
-2.5 2.5 7.5 12.5
-7.5
-2.5
2.5
VS = ±5V V+ = 5V
V+ = 3V V+ = 12V
ISL43140, ISL43141, ISL43142
12
FIGURE 13. TURN - ON TIME vs POSITIVE SUPPLY VOLTAGE FIGURE 14. TURN - OFF TIME vs POSITIVE SUPPLY VOLTAGE
FIGURE 15. TURN - ON TIME vs POSITIVE SUPPLY VOLTAGE FIGURE 16. TURN - OFF TIME vs POSITIVE SUPPLY VOLTAGE
FIGURE 17. DIGITAL SWITCHING POINT vs
POSITIVE SUPPLY VOLTAGE FIGURE 18. FREQUENCY RESPONSE
Typical Performance Curves TA = 25°C, Unless Otherwise Specified (Continued)
tON (ns)
V+ (V)
24681012
0
50
100
150
200
250
300
357911
-40°C
85°C
25°C
V- = 0V
VCOM = (V+) - 1V
tOFF (ns)
V+ (V)
24681012
10
20
30
40
50
357911
-40°C
85°C
25°C
VCOM = (V+) - 1V
V- = 0V
0
50
100
150
200
250
tON (ns)
V+ (V)
0
50
100
150
200
250 VCOM = (V+) - 1V
24681012357911
-40°C
85°C
V- = -3V
V- = -5V
-40°C 85°C
-40°C
25°C
-40°C
25°C
25°C
0
50
100
150
200
250
300
tOFF (ns)
V+ (V)
-40°C
85°C
0
50
100
25
75
125 VCOM = (V+) - 1V
V- = -3V
V- = -5V
-40°C 85°C
-40°C
25°C
85°C
24681012357911
25°C
V+ (V)
VINH AND VINL (V)
2 4 6 8 10 12
0.5
1
1.5
2
2.5
3
3.5
357911
-40°C
85°C
-40°C
85°C
VINH
VINL
25°C
25°C
V- = 0V to -5V
FREQUENCY (MHz)
3
0
-3
NORMALIZED GAIN (dB)
GAIN
PHASE 0
45
90
135
180
PHASE (DEGREES)
1 10 100 600
RL = 50Ω
V+ = 2.7V (VIN = 2VP-P)
VS = ±2V (VIN = 3VP-P) or V+ = 5V (VIN = 4VP-P)
VS = ±2V (VIN = 3VP-P)
V+ = 5V (VIN = 4VP-P)
VS = ±5V (VIN = 5VP-P)
VS = ±5V (VIN = 5VP-P)
V+ = 2.7V (VIN = 2VP-P)
ISL43140, ISL43141, ISL43142
13
FIGURE 19. CROSSTALK AND OFF ISOLATION FIGURE 20. ±PSRR vs FREQUENCY
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
V-
TRANSISTOR COUNT:
ISL43140: 188
ISL43141: 188
ISL43142: 188
PROCESS:
Si Gate CMOS
Typical Performance Curves TA = 25°C, Unless Otherwise Specified (Continued)
FREQUENCY (Hz)
1k 100k 1M 100M 500M10k 10M
-110
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
CROSSTALK (dB)
OFF ISOLATION (dB)
110
10
20
30
40
50
60
70
80
90
100
ISOLATION
ALL HOSTILE CROSSTALK
CROSSTALK
RL = 50Ω
VS = ±2V to ±5V
V+ = 3V to 12V or
PSRR (dB)
FREQUENCY (MHz)
0
10
20
30
40
50
60
70
80
0.3 1 10 100 1000
RL = 50Ω
VIN = 1VP-P
V+ = 3V to 12V or
VS = ±2V to ±5V
-PSRR, SWITCH ON
+PSRR, SWITCH ON
+PSRR, SWITCH OFF
-PSRR, SWITCH OFF
ISL43140, ISL43141, ISL43142
14
ISL43140, ISL43141, ISL43142
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C A
MBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H
µ
0.25(0.010) B
MM
α
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A0.053 0.069 1.35 1.75 -
A1 0.004 0.010 0.10 0.25 -
B0.014 0.019 0.35 0.49 9
C0.007 0.010 0.19 0.25 -
D0.386 0.394 9.80 10.00 3
E0.150 0.157 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H0.228 0.244 5.80 6.20 -
h0.010 0.020 0.25 0.50 5
L0.016 0.050 0.40 1.27 6
N16 167
α0o8o0o8o-
Rev. 1 02/02
15
ISL43140, ISL43141, ISL43142
Thin Shrink Small Outline Plastic Packages (TSSOP)
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08 mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact. (Angles in degrees)
α
INDEX
AREA E1
D
N
123
-B-
0.10(0.004) C AMBS
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004) c
E0.25(0.010) BM M
L
0.25
0.010
GAUGE
PLANE
A2
0.05(0.002)
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.043 - 1.10 -
A1 0.002 0.006 0.05 0.15 -
A2 0.033 0.037 0.85 0.95 -
b 0.0075 0.012 0.19 0.30 9
c 0.0035 0.008 0.09 0.20 -
D 0.193 0.201 4.90 5.10 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.020 0.028 0.50 0.70 6
N16 167
α0o8o0o8o-
Rev. 1 2/02
16
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is grant ed by impl icati on or ot herwise under any patent or patent rights o f Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
ISL43140, ISL43141, ISL43142
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
INDEX
D1/2
D1
D/2
D
E1/2 E/2
E
A
2X 0.15 B
C
0.10 BAMC
A
N
SEATING PLANE
N
6
3
2
2
3
e
1
1
0.08
FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/S IDE
CC
SECTION "C-C"
NX b A1
C
2X C
0.15
0.15
2X B
0
REF.
(Nd-1)Xe
(Ne-1)Xe
REF.
5
A1
4X P
A
C
C
4X P
B
2X AC0.15
A2
A3
D2
D2
E2
E2/2
TERMINAL TIP
SIDE VIEW
TOP VIEW
7
BOTTOM VIEW
7
5
C
LC
L
ee
E1
2
NX k
NX b
8
NX L
8
8
9
AREA
9
4X 0.10 C
/ /
9
(DATUM B)
(DATUM A)
AREA
INDEX
6
AREA
N9
CORNER
OPTION 4X
L1 L
10 L1 L
10
L16.3x3
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A 0.80 0.90 1.00 -
A1 - - 0.05 -
A2 - - 1.00 9
A3 0.20 REF 9
b 0.18 0.23 0.30 5, 8
D 3.00 BSC -
D1 2.75 BSC 9
D2 1.35 1.50 1.65 7, 8, 10
E 3.00 BSC -
E1 2.75 BSC 9
E2 1.35 1.50 1.65 7, 8, 10
e 0.50 BSC -
k0.20 - - -
L 0.30 0.40 0.50 8
N162
Nd 4 3
Ne 4 3
P- -0.609
θ--129
Rev. 1 6/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Compliant to JEDEC MO-220VEED-2 Issue C, except for the E2
and D2 MAX dimension.
