APPLICATIONS RF, VCO, and PLL power supplies Mobile phones Digital camera and audio devices Portable and battery-powered equipment Post dc-to-dc regulation Portable medical devices TYPICAL APPLICATION CIRCUIT VIN = 2.3V 1 VIN 2 GND 3 EN VOUT = 1.8V VOUT 5 1F 1F ON NC 4 08627-001 Ultralow noise: 9 V rms No noise bypass capacitor required Stable with 1 F ceramic input and output capacitors Maximum output current: 200 mA Input voltage range: 2.2 V to 5.5 V Low quiescent current IGND = 10 A with 0 load IGND = 265 A with 200 mA load Low shutdown current: <1 A Low dropout voltage: 140 mV at 200 mA load Initial accuracy: 1% Accuracy over line, load, and temperature: 2.5% 16 fixed output voltage options: 1.1 V to 3.3 V PSRR performance of 70 dB at 10 kHz Current-limit and thermal overload protection Logic controlled enable Internal pull-down resistor on EN input 5-lead TSOT package 6-lead LFCSP package 4-ball, 0.4 mm pitch WLCSP OFF NC = NO CONNECT Figure 1. TSOT ADP151 with Fixed Output Voltage, 1.8 V 1 2 VIN VOUT VOUT = 1.8V VIN = 2.3V A CIN TOP VIEW (Not to Scale) ON EN OFF GND COUT 1F 08627-002 FEATURES B Figure 2. WLCSP ADP151 with Fixed Output Voltage, 1.8 V VIN = 2.3V 1F ON OFF 6 5 4 VIN VOUT ADP151 NC TOP VIEW NC (Not to Scale) EN GND 1 2 VOUT = 1.8V 1F 3 NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 08627-047 Data Sheet Ultralow Noise, 200 mA, CMOS Linear Regulator ADP151 Figure 3. LFCSP ADP151 with Fixed Output Voltage, 1.8 V GENERAL DESCRIPTION The ADP151 is an ultralow noise, low dropout linear regulator that operates from 2.2 V to 5.5 V and provides up to 200 mA of output current. The low 140 mV dropout voltage at 200 mA load improves efficiency and allows operation over a wide input voltage range. Using an innovative circuit topology, the ADP151 achieves ultralow noise performance without the necessity of a bypass capacitor, making it ideal for noise-sensitive analog and RF applications. The ADP151 also achieves ultralow noise performance without compromising PSRR or transient line and load performance. The low 265 A of quiescent current at 200 mA load makes the ADP151 suitable for battery-operated portable equipment. The ADP151 is specifically designed for stable operation with tiny 1 F, 30% ceramic input and output capacitors to meet the requirements of high performance, space constrained applications. The ADP151 is capable of 16 fixed output voltage options, ranging from 1.1 V to 3.3 V. Short-circuit and thermal overload protection circuits prevent damage in adverse conditions. The ADP151 is available in tiny 5-lead TSOT, 6-lead LFCSP, and 4-ball, 0.4 mm pitch, halide-free WLCSP packages for the smallest footprint solution to meet a variety of portable power application requirements. The ADP151 also includes an internal pull-down resistor on the EN input. Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2010-2012 Analog Devices, Inc. All rights reserved. ADP151 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................7 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 11 Typical Application Circuit ............................................................. 1 Applications Information .............................................................. 12 General Description ......................................................................... 1 Capacitor Selection .................................................................... 12 Revision History ............................................................................... 2 Enable Feature ............................................................................ 13 Specifications..................................................................................... 3 Adjustable Output Voltage Operation ..................................... 13 Input and Output Capacitor, Recommended Specifications .. 4 Current-Limit and Thermal Overload Protection ................. 15 Absolute Maximum Ratings............................................................ 5 Thermal Considerations............................................................ 15 Thermal Data ................................................................................ 5 Printed Circuit Board Layout Considerations ............................ 20 Thermal Resistance ...................................................................... 5 Outline Dimensions ....................................................................... 21 ESD Caution .................................................................................. 5 Ordering Guide .......................................................................... 22 Pin Configurations and Function Descriptions ........................... 6 REVISION HISTORY 4/12--Rev. D to Rev. E Changes to Figure 33 ...................................................................... 13 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 22 3/11--Rev. C to Rev. D Changes to Current-Limit Threshold Temperature Range ......... 4 Added EPAD Notation .................................................................... 6 Changes to Ordering Guide .......................................................... 22 1/11--Rev. B to Rev. C Changes to Figure 23 ........................................................................ 9 12/10--Rev. A to Rev. B Added LFCSP Package ....................................................... Universal Added Figure 3; Renumbered Sequentially .................................. 1 Added Table 2 Caption; Renumbered Sequentially ..................... 4 Changes to Table 4 ............................................................................ 5 Added Figure 6, Changes to Table 5............................................... 6 Changes to Figure 23 ........................................................................ 9 Changes to Figure 37 and Figure 38 ............................................. 14 Added Figure 51 to Figure 56 ....................................................... 18 Added Figure 59 ............................................................................. 19 Added Figure 62 ............................................................................. 20 Added Figure 65 ............................................................................. 21 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 23 8/10--Rev. 0 to Rev. A Changes to Figure 8 ...........................................................................7 Changes to Figure 15 Caption and Figure 16 Caption .................8 Changes to Figure 17 Caption and Figure 18 Caption .................9 Changes to Ordering Guide .......................................................... 21 3/10--Revision 0: Initial Version Rev. E | Page 2 of 24 Data Sheet ADP151 SPECIFICATIONS VIN = (VOUT + 0.4 V) or 2.2 V, whichever is greater; EN = VIN, IOUT = 10 mA, CIN = COUT = 1 F, TA = 25C, unless otherwise noted. Table 1. Parameter INPUT VOLTAGE RANGE OPERATING SUPPLY CURRENT SHUTDOWN CURRENT Symbol VIN IGND IGND-SD Conditions TJ = -40C to +125C IOUT = 0 A IOUT = 0 A, TJ = -40C to +125C IOUT = 100 A IOUT = 100 A, TJ = -40C to +125C IOUT = 10 mA IOUT = 10 mA, TJ = -40C to +125C IOUT = 200 mA IOUT = 200 mA, TJ = -40C to +125C EN = GND EN = GND, TJ = -40C to +125C Min 2.2 IOUT = 10 mA TJ = -40C to +125C VOUT < 1.8 V 100 A < IOUT < 200 mA, VIN = (VOUT + 0.4 V) to 5.5 V VOUT 1.8 V 100 A < IOUT < 200 mA, VIN = (VOUT + 0.4 V) to 5.5 V TJ = -40C to +125C VOUT < 1.8 V 100 A < IOUT < 200 mA, VIN = (VOUT + 0.4 V) to 5.5 V VOUT 1.8 V 100 A < IOUT < 200 mA, VIN = (VOUT + 0.4 V) to 5.5 V Typ Max 5.5 1.0 Unit V A A A A A A A A A A -1 +1 % -3 +2 % -2.5 +1.5 % -2.5 +2 % -2 +1.5 % -0.05 +0.05 %/V %/mA %/mA %/mA 10 20 20 40 60 90 265 350 0.2 OUTPUT VOLTAGE ACCURACY TSOT/LFCSP WLCSP REGULATION Line Regulation Load Regulation (TSOT/LFCSP) 1 Load Regulation (WLCSP)1 DROPOUT VOLTAGE 2 TSOT/LFCSP WLCSP VOUT VOUT VOUT VOUT/VIN VOUT/IOUT VOUT/IOUT VDROPOUT VIN = (VOUT + 0.4 V) to 5.5 V, TJ = -40C to +125C VOUT < 1.8 V IOUT = 100 A to 200 mA IOUT = 100 A to 200 mA, TJ = -40C to +125C VOUT 1.8 V IOUT = 100 A to 200 mA IOUT = 100 A to 200 mA, TJ = -40C to +125C VOUT < 1.8 V IOUT = 100 A to 200 mA IOUT = 100 A to 200 mA, TJ = -40C to +125C VOUT 1.8 V IOUT = 100 A to 200 mA IOUT = 100 A to 200 mA, TJ = -40C to +125C IOUT = 10 mA IOUT = 10 mA, TJ = -40C to +125C IOUT = 200 mA IOUT = 200 mA, TJ = -40C to +125C IOUT = 200 mA IOUT = 200 mA, TJ = -40C to +125C Rev. E | Page 3 of 24 0.006 0.012 0.003 0.008 0.004 0.009 0.002 0.006 10 30 150 230 135 200 %/mA %/mA %/mA %/mA %/mA %/mA %/mA mV mV mV mV mV mV ADP151 Parameter START-UP TIME 3 CURRENT-LIMIT THRESHOLD 4 UNDERVOLTAGE LOCKOUT Input Voltage Rising Input Voltage Falling Hysteresis THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis EN INPUT EN Input Logic High EN Input Logic Low EN Input Pull-Down Resistance OUTPUT NOISE POWER SUPPLY REJECTION RATIO VIN = VOUT + 0.5 V Data Sheet Symbol tSTART-UP ILIMIT Conditions VOUT = 3.3 V TJ = 0C to +125C TJ = -40C to +125C UVLORISE UVLOFALL UVLOHYS Min 220 Typ 180 300 Max 400 1.96 120 V V mV 150 15 C C 1.28 TSSD TSSD-HYS TJ rising VIH VIL REN OUTNOISE 2.2 V VIN 5.5 V 2.2 V VIN 5.5 V VIN = VEN = 5.5 V 10 Hz to 100 kHz, VIN = 5 V, VOUT = 3.3 V 10 Hz to 100 kHz, VIN = 5 V, VOUT = 2.5 V 10 Hz to 100 kHz, VIN = 5 V, VOUT = 1.1 V Unit s mA 1.2 2.6 9 9 9 V V M V rms V rms V rms 70 55 70 55 70 55 dB dB dB dB dB dB 0.4 PSRR 10 kHz, VIN = 3.8 V, VOUT = 3.3 V, IOUT = 10 mA 100 kHz, VIN = 3.8 V, VOUT = 3.3 V, IOUT = 10 mA 10 kHz, VIN = 4.3 V, VOUT = 3.3 V, IOUT = 10 mA 100 kHz, VIN = 4.3 V, VOUT = 3.3 V, IOUT = 10 mA 10 kHz, VIN = 2.2 V, VOUT = 1.1 V, IOUT = 10 mA 100 kHz, VIN = 2.2 V, VOUT = 1.1 V, IOUT = 10 mA VIN = VOUT + 1 V Based on an end-point calculation using 0.1 mA and 200 mA loads. See Figure 8 for typical load regulation performance for loads less than 1 mA. Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages above 2.2 V. 3 Start-up time is defined as the time between the rising edge of EN and VOUT being at 90% of its nominal value. 4 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V (that is, 2.7 V). 1 2 INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS Table 2. Parameter Minimum Input and Output Capacitance 1 Capacitor ESR 1 Symbol CMIN Conditions TA = -40C to +125C Min 0.7 RESR TA = -40C to +125C 0.001 Typ Max Unit F 0.2 The minimum input and output capacitance should be greater than 0.7 F over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use with any LDO. Rev. E | Page 4 of 24 Data Sheet ADP151 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VIN to GND VOUT to GND EN to GND Storage Temperature Range Operating Junction Temperature Range Operating Ambient Temperature Range Soldering Conditions Rating -0.3 V to +6.5 V -0.3 V to VIN -0.3 V to +6.5V -65C to +150C -40C to +125C -40C to +125C JEDEC J-STD-020 Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL DATA Absolute maximum ratings apply individually only, not in combination. The ADP151 can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that TJ is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. In applications with moderate power dissipation and low PCB thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature (TJ) of the device is dependent on the ambient temperature (TA), the power dissipation of the device (PD), and the junction-to-ambient thermal resistance of the package (JA). The maximum junction temperature (TJ) is calculated from the ambient temperature (TA) and power dissipation (PD) using the formula on PCB material, layout, and environmental conditions. The specified values of JA are based on a 4-layer, 4 in. x 3 in. circuit board. See JESD51-7 and JESD51-9 for detailed information on the board construction. For additional information, see the AN-617 Application Note, MicroCSPTM Wafer Level Chip Scale Package, available at www.analog.com. JB is the junction-to-board thermal characterization parameter with units of C/W. JB of the package is based on modeling and calculation using a 4-layer board. The JESD51-12, Guidelines for Reporting and Using Electronic Package Thermal Information, states that thermal characterization parameters are not the same as thermal resistances. JB measures the component power flowing through multiple thermal paths rather than a single path as in thermal resistance, JB. Therefore, JB thermal paths include convection from the top of the package as well as radiation from the package, factors that make JB more useful in real-world applications. Maximum junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (PD) using the formula TJ = TB + (PD x JB) See JESD51-8 and JESD51-12 for more detailed information about JB. THERMAL RESISTANCE JA and JB are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type 5-Lead TSOT 4-Ball, 0.4 mm Pitch WLCSP 6-Lead 2 mm x 2 mm LFCSP ESD CAUTION TJ = TA + (PD x JA) The junction-to-ambient thermal resistance (JA) of the package is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal board design is required. The value of JA may vary, depending Rev. E | Page 5 of 24 JA 170 260 63.6 JB 43 58 28.3 Unit C/W C/W C/W ADP151 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADP151 A TOP VIEW (Not to Scale) EN 3 4 NC NC = NO CONNECT 08627-003 GND 2 2 VOUT 1 VOUT Figure 4. 5-Lead TSOT Pin Configuration VIN NC 2 VOUT TOP VIEW (Not to Scale) B EN GND GND 3 08627-004 5 Figure 5. 4-Ball WLCSP Pin Configuration 6 VIN ADP151 TOP VIEW (Not to Scale) 5 NC 4 EN 08627-048 1 VIN 1 NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND. Figure 6. 6-Lead LFCSP Pin Configuration Table 5. Pin Function Descriptions TSOT 1 2 3 Pin No. WLCSP A1 B2 B1 4 5 N/A N/A N/A A2 N/A N/A LFCSP 6 3 4 Mnemonic VIN GND EN 2 1 5 NC VOUT NC EPAD Description Regulator Input Supply. Bypass VIN to GND with a 1 F or greater capacitor. Ground. Enable Input. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic startup, connect EN to VIN. No Connect. Not connected internally. Regulated Output Voltage. Bypass VOUT to GND with a 1 F or greater capacitor. No Connect. Not connected internally. Exposed Pad. The exposed pad must be connected to ground. The exposed pad enhances the thermal performance of the package. Rev. E | Page 6 of 24 Data Sheet ADP151 TYPICAL PERFORMANCE CHARACTERISTICS VIN = 5 V, VOUT = 3.3 V, IOUT = 1 mA, CIN = COUT = 1 F, TA = 25C, unless otherwise noted. 3.35 1k 3.29 LOAD = 10A LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 200mA 3.27 3.25 -40 -5 25 85 125 JUNCTION TEMPERATURE (C) 100 10 LOAD = 10A LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 200mA 1 -40 -5 25 85 08627-008 GROUND CURRENT (A) 3.31 08627-005 VOUT (V) 3.33 125 JUNCTION TEMPERATURE (C) Figure 7. Output Voltage vs. Junction Temperature Figure 10. Ground Current vs. Junction Temperature 3.35 1k GROUND CURRENT (A) VOUT (V) 3.33 3.31 3.29 100 0.1 1 10 100 10 0.01 08627-006 3.25 0.01 1000 ILOAD (mA) 0.1 1 10 100 08627-009 3.27 1000 ILOAD (mA) Figure 8. Output Voltage vs. Load Current Figure 11. Ground Current vs. Load Current 1k 3.35 LOAD = 10mA LOAD = 100mA LOAD = 200mA LOAD = 10A LOAD = 100A LOAD = 1mA 3.29 3.27 3.25 3.6 LOAD = 10A LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 200mA 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 VIN (V) 5.4 100 10 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 VIN (V) Figure 9. Output Voltage vs. Input Voltage Figure 12. Ground Current vs. Input Voltage Rev. E | Page 7 of 24 5.4 08627-010 GROUND CURRENT (A) 3.31 08627-007 VOUT (V) 3.33 ADP151 0.35 0.30 700 0.25 0.20 0.15 0.10 600 500 400 300 200 100 0.05 -25 0 25 50 75 100 0 3.10 08627-011 0 -50 125 TEMPERATURE (C) 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50 3.55 VIN (V) Figure 16. Ground Current vs. Input Voltage (in Dropout) Figure 13. Shutdown Current vs. Temperature at Various Input Voltages 0 120 -10 100 -20 200mA 100mA 10mA 1mA 100A -30 80 PSRR (dB) DROPOUT VOLTAGE (mA) IOUT = 1mA IOUT = 5mA IOUT = 10mA IOUT = 50mA IOUT = 100mA IOUT = 200mA 08627-014 SHUTDOWN CURRENT (A) 0.40 800 VIN = 3.6V VIN = 3.8V VIN = 4.2V VIN = 4.4V VIN = 4.8V VIN = 5.5V GROUND CURRENT (A) 0.45 Data Sheet 60 40 -40 -50 -60 -70 -80 20 1 10 100 1000 ILOAD (mA) -100 10 08627-012 0 Figure 14. Dropout Voltage vs. Load Current 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 08627-015 -90 Figure 17. Power Supply Rejection Ratio vs. Frequency, VOUT = 1.2 V, VIN = 2.2 V 0 3.40 -10 3.35 -20 3.30 200mA 100mA 10mA 1mA 100A -30 PSRR (dB) 3.20 3.15 IOUT = 1mA IOUT = 5mA IOUT = 10mA IOUT = 50mA IOUT = 100mA IOUT = 200mA 3.05 3.00 3.10 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50 3.55 VIN (V) Figure 15. Output Voltage vs. Input Voltage (in Dropout) -40 -50 -60 -70 -80 -90 -100 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 08627-016 3.10 08627-013 VOUT (V) 3.25 Figure 18. Power Supply Rejection Ratio vs. Frequency, VOUT = 2.8 V, VIN = 3.3 V Rev. E | Page 8 of 24 Data Sheet 0 -10 -20 ADP151 14 200mA 100mA 10mA 1mA 100A 12 11 10 -30 9 NOISE (V rms) PSRR (dB) 3.3V 2.8V 1.2V 1.1V 13 -40 -50 -60 8 7 6 5 -70 4 -80 3 2 -90 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 0 0.001 -20 PSRR (dB) -30 VOUT = 3.3V, VOUT = 3.3V, VOUT = 2.8V, VOUT = 2.8V, VOUT = 1.1V, VOUT = 1.1V, 1 10 100 1000 IOUT = 200mA IOUT = 10mA IOUT = 200mA IOUT = 10mA IOUT = 200mA IOUT = 10mA -40 -50 -60 -70 -80 1k Figure 22. Output Noise vs. Load Current and Output Voltage, VIN = 5 V, COUT = 1 F NOISE SPECTRAL DENSITY (nV/ Hz) 0 0.1 LOAD CURRENT (mA) Figure 19. Power Supply Rejection Ratio vs. Frequency, VOUT = 3.3 V, VIN = 3.8 V -10 0.01 08627-020 1 08627-017 -100 10 3.3V 2.8V 1.2V 1.1V 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 10 10 08627-018 100 -10 -20 1k 10k 100k FREQUENCY (Hz) Figure 23. Output Noise Spectral Density vs. Frequency, VIN = 5 V, ILOAD = 10 mA, COUT = 1 F Figure 20. Power Supply Rejection Ratio vs. Frequency at Various Output Voltages and Load Currents, VOUT - VIN = 0.5 V, except for VOUT = 1.1 V, VIN = 2.2 V 0 100 08627-021 -90 -100 10 T IOUT = 200mA, VIN = 3.3V IOUT = 10mA, VIN =3.3V IOUT = 200mA, VIN = 3.8V IOUT = 10mA, VIN = 3.8V LOAD CURRENT 1 PSRR (dB) -30 -40 -50 -60 2 VOUT -70 -80 100 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 21. Power Supply Rejection Ratio vs. Frequency at Various Voltages and Load Currents, VOUT = 2.8 V CH1 200mA CH2 50mV M20s T 10.00% A CH1 64.0mA 08627-022 -100 10 08627-019 -90 Figure 24. Load Transient Response, CIN, COUT = 1 F, ILOAD = 1 mA to 200 mA Rev. E | Page 9 of 24 ADP151 Data Sheet T T INPUT VOLTAGE INPUT VOLTAGE 2 2 VOUT VOUT CH1 1V CH2 2mV M10s T 10.80% A CH1 4.56V CH1 1V Figure 25. Line Transient Response, CIN, COUT = 1 F, ILOAD = 200 mA CH2 2mV M10s T 10.80% A CH1 4.56V 08627-024 1 08627-023 1 Figure 26. Line Transient Response, CIN, COUT = 1 F, ILOAD = 1 mA Rev. E | Page 10 of 24 Data Sheet ADP151 THEORY OF OPERATION The ADP151 is an ultralow noise, low quiescent current, low dropout linear regulator that operates from 2.2 V to 5.5 V and can provide up to 200 mA of output current. Drawing a low 265 A of quiescent current (typical) at full load makes the ADP151 ideal for battery-operated portable equipment. Shutdown current consumption is typically 200 nA. Using new innovative design techniques, the ADP151 provides superior noise performance for noise-sensitive analog and RF applications without the need for a noise bypass capacitor. The ADP151 is also optimized for use with small 1 F ceramic capacitors. VIN VOUT SHORT-CIRCUIT, UVLO, AND THERMAL PROTECT SHUTDOWN REN REFERENCE R2 08627-025 EN An internal pull-down resistor on the EN input holds the input low when the pin is left open. The ADP151 is available in 16 output voltage options, ranging from 1.1 V to 3.3 V. The ADP151 uses the EN pin to enable and disable the VOUT pin under normal operating conditions. When EN is high, VOUT turns on; when EN is low, VOUT turns off. For automatic startup, EN can be tied to VIN. R1 GND Internally, the ADP151 consists of a reference, an error amplifier, a feedback voltage divider, and a PMOS pass transistor. Output current is delivered via the PMOS pass device, which is controlled by the error amplifier. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more current to pass and increasing the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is pulled higher, allowing less current to pass and decreasing the output voltage. Figure 27. Internal Block Diagram Rev. E | Page 11 of 24 ADP151 Data Sheet APPLICATIONS INFORMATION Output Capacitor The ADP151 is designed for operation with small, space-saving ceramic capacitors but can function with most commonly used capacitors as long as care is taken with regard to the effective series resistance (ESR) value. The ESR of the output capacitor affects the stability of the LDO control loop. A minimum of 1 F capacitance with an ESR of 1 or less is recommended to ensure the stability of the ADP151. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the ADP151 to large changes in load current. Figure 28 shows the transient responses for an output capacitance value of 1 F. T LOAD CURRENT Figure 29 depicts the capacitance vs. voltage bias characteristic of an 0402, 1 F, 10 V X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is ~15% over the -40C to +85C temperature range and is not a function of package or voltage rating. 1.2 1.0 CAPACITANCE (F) CAPACITOR SELECTION 1 0.8 0.6 0.4 0 0 2 4 6 8 VOLTAGE BIAS 2 10 08627-027 0.2 Figure 29. Capacitance vs. Voltage Bias Characteristic VOUT CH2 50mV M20s T 10.00% A CH1 64mA 08627-026 CH1 200mA Use Equation 1 to determine the worst-case capacitance, accounting for capacitor variation over temperature, component tolerance, and voltage. CEFF = CBIAS x (1 - TEMPCO) x (1 - TOL) Figure 28. Output Transient Response, COUT = 1 F Input Bypass Capacitor (1) where: CBIAS is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. Connecting a 1 F capacitor from VIN to GND reduces the circuit sensitivity to the printed circuit board (PCB) layout, especially when long input traces or high source impedance are encountered. If greater than 1 F of output capacitance is required, the input capacitor should be increased to match it. In this example, the worst-case temperature coefficient (TEMPCO) over -40C to +85C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and CBIAS is 0.94 F at 1.8 V, as shown in Figure 29. Input and Output Capacitor Properties Substituting these values in Equation 1 yields Any good quality ceramic capacitor can be used with the ADP151, as long as it meets the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. Capacitors must have an adequate dielectric to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recommended. Y5V and Z5U dielectrics are not recommended, due to their poor temperature and dc bias characteristics. CEFF = 0.94 F x (1 - 0.15) x (1 - 0.1) = 0.719 F Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP151, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. Rev. E | Page 12 of 24 Data Sheet ADP151 ENABLE FEATURE 3.5 3.0 3.0 ENABLE VOLTAGE The ADP151 uses the EN pin to enable and disable the VOUT pin under normal operating conditions. As shown in Figure 30, when a rising voltage on EN crosses the active threshold, VOUT turns on. When a falling voltage on EN crosses the inactive threshold, VOUT turns off. 2.5 2.0 1.5 1.0 ENABLE 3.3V 2.8V 1.1V 0.5 VOUT 2.0 0 0 1.5 50 100 150 200 250 300 350 400 450 TIME (s) 08627-030 2.5 Figure 32. Typical Start-Up Behavior 1.0 ADJUSTABLE OUTPUT VOLTAGE OPERATION 0 0.5 1.0 1.5 2.0 2.5 ENABLE VOLTAGE Figure 30. ADP151 Typical EN Pin Operation As shown in Figure 30, the EN pin has hysteresis built in. This prevents on/off oscillations that can occur due to noise on the EN pin as it passes through the threshold points. The EN pin active/inactive thresholds are derived from the VIN voltage. Therefore, these thresholds vary with changing input voltage. Figure 31 shows typical EN active/inactive thresholds when the input voltage varies from 2.2 V to 5.5 V. The unique architecture of the ADP151 makes an adjustable version difficult to implement in silicon. However, it is possible to create an adjustable regulator at the expense of increasing the quiescent current of the regulator circuit. The ADP151, and similar LDOs, are designed to regulate the output voltage, VOUT, appearing at the VOUT pin with respect to the GND pin. If the GND pin is at a potential other than 0 V (for example, at VOFFSET), the ADP151 output voltage is VOUT + VOFFSET. By taking advantage of this behavior, it is possible to create an adjustable ADP151 circuit that retains most of the desirable characteristics of the ADP151. VIN 1 2 GND 3 EN VOUT C2 NC 4 VOFFSET VEN RISE 800 VOUT 5 U1 1000 ENABLE VOLTAGE VIN C1 1200 R2 VEN FALL R1 C3 VOUT = VLDO x (1 + R2/R1) 600 08627-131 0 08627-028 0.5 Figure 33. Adjustable LDO Using the ADP151 400 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 INPUT VOLTAGE 5.5 08627-029 200 Figure 31. Typical EN Pin Thresholds vs. Input Voltage The ADP151 uses an internal soft start to limit the inrush current when the output is enabled. The start-up time for the 3.3 V option is approximately 160 s from the time the EN active threshold is crossed to when the output reaches 90% of its final value. As shown in Figure 32, the start-up time is dependent on the output voltage setting. The circuit shown in Figure 33 is an example of an adjustable LDO using the ADP151. A stable VOFFSET voltage is created by passing a known current through R2. The current through R2 is determined by the voltage across R1. Because the voltage across R1 is set by the voltage between VOUT and GND, the current passing through R2 is fixed, and VOFFSET is stable. To minimize the effect variation of the ADP151 ground current (IGND) with load, it is best to keep R1 as small as possible. It is also best to size the current passing through R2 to at least 20x greater than the maximum expected ground current. To create a 4 V LDO circuit, start with the 3.3 V version of the ADP151 to minimize the value of R2. Because VOUT is 4 V, VOFFSET must be 0.7 V, and the current through R2 must be 7 mA. R1 is, therefore, 3.3 V/7 mA or 471 . A 470 standard value introduces less than 1% error. Capacitor C3 is necessary to stabilize the LDO; a value of 1 F is adequate. Rev. E | Page 13 of 24 ADP151 Data Sheet Figure 34 through Figure 38 show the typical performance of the 4 V LDO circuit. 11 10 9 8 1 10 100 1k LOAD CURRENT (mA) 08627-134 The PSRR of the 4 V circuit is as much as 10 dB poorer than the 3.3 V LDO with 500 mV of headroom because the ground current of the LDO varies slightly with input voltage. This, in turn, modulates VOFFSET and reduces the PSRR of the regulator. By increasing the headroom to 1 V, the PSRR performance is nearly restored to the performance of the fixed output LDO. NOISE (V rms) The noise performance of the 4 V LDO circuit is only about 1 V worse than the same LDO used at 3.3 V because the output noise of the circuit is almost solely determined by the LDO and not the external components. The small difference may be attributed to the internally generated noise in the LDO ground current working with R2. By keeping R2 small, this noise contribution can be minimized. Figure 36. 4 V LDO Circuit, Typical RMS Output Noise, 10 Hz to 100 kHz 4.04 0 4.03 -10 -20 4.02 200mA 100mA 50mA 10mA -30 PSRR (dB) 4.00 3.99 3.97 3.96 -40 -90 -5 25 85 125 Figure 34. 4 V LDO Circuit, Typical Load Regulation over Temperature 4.035 4.030 -60 -80 JUNCTION TEMPERATURE (C) 4.040 -50 -70 08627-132 3.98 LOAD = 10mA LOAD = 20mA LOAD = 50mA LOAD = 100mA LOAD = 150mA LOAD = 200mA -40 -100 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 08627-049 VOUT (V) 4.01 Figure 37. 4 V LDO Circuit, Typical PSRR vs. Load Current, 1 V Headroom 0 LOAD = 10mA LOAD = 20mA LOAD = 50mA LOAD = 100mA LOAD = 150mA LOAD = 200mA -10 -20 200mA 100mA 50mA 10mA -30 PSRR (dB) VOUT (V) 4.025 4.020 4.015 -40 -50 -60 -70 4.010 -80 4.005 4.8 5.0 VIN (V) 5.2 5.4 -100 10 08627-133 4.6 Figure 35. 4 V LDO Circuit, Typical Line Regulation over Load Current 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 08627-050 -90 4.000 4.4 Figure 38. 4 V LDO Circuit, Typical PSRR vs. Load Current, 500 mV Headroom Rev. E | Page 14 of 24 Data Sheet ADP151 CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION The ADP151 is protected against damage due to excessive power dissipation by current and thermal overload protection circuits. The ADP151 is designed to current limit when the output load reaches 300 mA (typical). When the output load exceeds 300 mA, the output voltage is reduced to maintain a constant current limit. Thermal overload protection is included, which limits the junction temperature to a maximum of 150C (typical). Under extreme conditions (that is, high ambient temperature and power dissipation) when the junction temperature starts to rise above 150C, the output is turned off, reducing the output current to 0. When the junction temperature drops below 135C, the output is turned on again, and output current is restored to its nominal value. Consider the case where a hard short from VOUT to ground occurs. At first, the ADP151 current limits, so that only 300 mA is conducted into the short. If self-heating of the junction causes its temperature to rise above 150C, thermal shutdown activates, turning off the output and reducing the output current to 0. As the junction temperature cools and drops below 135C, the output turns on and conducts 300 mA into the short, again causing the junction temperature to rise above 150C. This thermal oscillation between 135C and 150C causes a current oscillation between 300 mA and 0 mA that continues as long as the short remains at the output. Current- and thermal-limit protections are intended to protect the device against accidental overload conditions. For reliable operation, device power dissipation must be externally limited so that junction temperatures do not exceed 125C. THERMAL CONSIDERATIONS In most applications, the ADP151 does not dissipate much heat due to its high efficiency. However, in applications with a high ambient temperature and a high supply voltage to output voltage differential, the heat dissipated in the package can cause the junction temperature of the die to exceed the maximum junction temperature of 125C. When the junction temperature exceeds 150C, the converter enters thermal shutdown. It recovers only after the junction temperature has decreased below 135C to prevent any permanent damage. Therefore, thermal analysis for the chosen application is very important to guarantee reliable performance over all conditions. The junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to the power dissipation, as shown in Equation 2. To guarantee reliable operation, the junction temperature of the ADP151 must not exceed 125C. To ensure that the junction temperature stays below this maximum value, the user must be aware of the parameters that contribute to junction temperature changes. These parameters include ambient temperature, power dissipation in the power device, and thermal resistances between the junction and ambient air (JA). The JA number is dependent on the package assembly compounds that are used and the amount of copper used to solder the package GND pins to the PCB. Table 6 shows typical JA values of the 5-lead TSOT, 6-lead LFCSP, and 4-ball WLCSP packages for various PCB copper sizes. Table 7 shows the typical JB values of the 5-lead TSOT, 6-lead LFCSP, and 4-ball WLCSP. Table 6. Typical JA Values Copper Size (mm2) 01 50 100 300 500 1 TSOT 170 152 146 134 131 JA (C/W) WLCSP 260 159 157 153 151 LFCSP 231.2 161.8 150.1 111.5 91.8 Device soldered to minimum size pin traces. Table 7. Typical JB Values Model TSOT WLCSP LFCSP JB (C/W) 43 58 28.3 The junction temperature of the ADP151 can be calculated from the following equation: TJ = TA + (PD x JA) (2) where: TA is the ambient temperature. PD is the power dissipation in the die, given by PD = [(VIN - VOUT) x ILOAD] + (VIN x IGND) (3) where: ILOAD is the load current. IGND is the ground current. VIN and VOUT are input and output voltages, respectively. Power dissipation due to ground current is quite small and can be ignored. Therefore, the junction temperature equation simplifies to the following: TJ = TA + {[(VIN - VOUT) x ILOAD] x JA} (4) As shown in Equation 4, for a given ambient temperature, input-tooutput voltage differential, and continuous load current, there exists a minimum copper size requirement for the PCB to ensure that the junction temperature does not rise above 125C. Figure 39 through Figure 59 show junction temperature calculations for various ambient temperatures, load currents, VIN-to-VOUT differentials, and areas of PCB copper. Rev. E | Page 15 of 24 ADP151 Data Sheet 140 140 MAXIMUM JUNCTION TEMPERATURE 100 80 60 40 20 0 0.3 ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 1.3 1.8 ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA 2.3 2.8 3.3 VIN - VOUT (V) 3.8 4.3 4.8 120 100 80 60 40 20 0 0.3 Figure 39. WLCSP 500 mm2 of PCB Copper, TA = 25C ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 2.3 2.8 3.3 VIN - VOUT (V) 3.8 4.3 4.8 140 MAXIMUM JUNCTION TEMPERATURE MAXIMUM JUNCTION TEMPERATURE 100 80 60 40 20 0.8 1.3 1.8 ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA 2.3 2.8 3.3 VIN - VOUT (V) 3.8 4.3 4.8 100 80 60 40 20 0 0.3 Figure 40. WLCSP 100 mm2 of PCB Copper, TA = 25C ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 1.8 2.3 2.8 3.3 VIN - VOUT (V) 3.8 4.3 4.8 Figure 43. WLCSP 100 mm2 of PCB Copper, TA = 50C 140 140 MAXIMUM JUNCTION TEMPERATURE MAXIMUM JUNCTION TEMPERATURE JUNCTION TEMPERATURE, TJ (C) 120 100 80 60 40 ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 1.3 1.8 ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA 2.3 2.8 3.3 VIN - VOUT (V) 3.8 4.3 4.8 120 100 80 60 40 20 0 0.3 08627-033 20 0 0.3 1.3 ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA Figure 41. WLCSP 50 mm2 of PCB Copper, TA = 25C ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 1.3 1.8 ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA 2.3 2.8 3.3 VIN - VOUT (V) 3.8 4.3 Figure 44. WLCSP 50 mm2 of PCB Copper, TA = 50C Rev. E | Page 16 of 24 4.8 08627-036 0 0.3 ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 120 08627-035 JUNCTION TEMPERATURE, TJ (C) 120 08627-032 JUNCTION TEMPERATURE, TJ (C) 1.8 Figure 42. WLCSP 500 mm2 of PCB Copper, TA = 50C 140 JUNCTION TEMPERATURE, TJ (C) 1.3 ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA 08627-034 JUNCTION TEMPERATURE, TJ (C) 120 08627-031 JUNCTION TEMPERATURE, TJ (C) MAXIMUM JUNCTION TEMPERATURE Data Sheet ADP151 140 140 MAXIMUM JUNCTION TEMPERATURE 100 80 60 40 20 0.8 1.3 1.8 ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA 2.3 2.8 3.3 VIN - VOUT (V) 3.8 4.3 4.8 100 80 60 40 20 0 0.3 Figure 45. TSOT 500 mm2 of PCB Copper, TA = 25C ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 4.3 4.8 80 60 40 20 ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 1.3 1.8 ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA 2.3 2.8 3.3 VIN - VOUT (V) 3.8 4.3 4.8 120 100 80 60 40 20 0 0.3 ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 1.3 1.8 ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA 2.3 2.8 3.3 VIN - VOUT (V) 3.8 4.3 4.8 08627-041 JUNCTION TEMPERATURE, TJ (C) 100 08627-038 JUNCTION TEMPERATURE, TJ (C) 3.8 MAXIMUM JUNCTION TEMPERATURE 120 Figure 46. TSOT 100 mm2 of PCB Copper, TA = 25C Figure 49. TSOT 100 mm2 of PCB Copper, TA = 50C 140 140 MAXIMUM JUNCTION TEMPERATURE MAXIMUM JUNCTION TEMPERATURE JUNCTION TEMPERATURE, TJ (C) 120 100 80 60 40 20 ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 1.3 1.8 ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA 2.3 2.8 3.3 VIN - VOUT (V) 3.8 4.3 4.8 120 100 80 60 40 20 0 0.3 08627-039 JUNCTION TEMPERATURE, TJ (C) 2.3 2.8 3.3 VIN - VOUT (V) 140 MAXIMUM JUNCTION TEMPERATURE 0 0.3 1.8 Figure 48. TSOT 500 mm2 of PCB Copper, TA = 50C 140 0 0.3 1.3 ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA Figure 47. TSOT 50 mm2 of PCB Copper, TA = 25C ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 1.3 1.8 ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA 2.3 2.8 3.3 VIN - VOUT (V) 3.8 4.3 Figure 50. TSOT 50 mm2 of PCB Copper, TA = 50C Rev. E | Page 17 of 24 4.8 08627-042 0 0.3 ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 120 08627-040 JUNCTION TEMPERATURE, TJ (C) 120 08627-037 JUNCTION TEMPERATURE, TJ (C) MAXIMUM JUNCTION TEMPERATURE ADP151 Data Sheet 140 140 MAXIMUM JUNCTION TEMPERATURE 100 80 60 40 20 0 0.3 ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 1.3 1.8 ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA 2.3 2.8 3.3 VIN - VOUT (V) 3.8 4.3 4.8 120 100 80 60 40 20 0 0.3 Figure 51. LFCSP 500 mm2 of PCB Copper, TA = 25C ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 1.8 2.3 2.8 3.3 VIN - VOUT (V) 3.8 4.3 4.8 Figure 54. LFCSP 500 mm2 of PCB Copper, TA = 50C 140 140 MAXIMUM JUNCTION TEMPERATURE MAXIMUM JUNCTION TEMPERATURE 100 80 60 40 20 0 0.3 ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 1.3 1.8 ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA 2.3 2.8 3.3 VIN - VOUT (V) 3.8 4.3 4.8 120 100 80 60 40 20 0 0.3 Figure 52. LFCSP 100 mm2 of PCB Copper, TA = 25C ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 1.3 1.8 ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA 2.3 2.8 3.3 VIN - VOUT (V) 3.8 4.3 4.8 08627-056 JUNCTION TEMPERATURE, TJ (C) 120 08627-052 JUNCTION TEMPERATURE, TJ (C) 1.3 ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA 08627-055 JUNCTION TEMPERATURE, TJ (C) 120 08627-051 JUNCTION TEMPERATURE, TJ (C) MAXIMUM JUNCTION TEMPERATURE Figure 55. LFCSP 100 mm2 of PCB Copper, TA = 50C 140 140 100 80 60 40 20 0 0.3 ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 1.3 1.8 ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA 2.3 2.8 3.3 VIN - VOUT (V) 3.8 4.3 4.8 100 80 60 40 20 0 0.3 Figure 53. LFCSP 50 mm2 of PCB Copper, TA = 25C MAXIMUM JUNCTION TEMPERATURE 120 ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 1.3 1.8 ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA 2.3 2.8 3.3 VIN - VOUT (V) 3.8 4.3 Figure 56. LFCSP 50 mm2 of PCB Copper, TA = 50C Rev. E | Page 18 of 24 4.8 08627-057 JUNCTION TEMPERATURE, TJ (C) 120 08627-053 JUNCTION TEMPERATURE, TJ (C) MAXIMUM JUNCTION TEMPERATURE Data Sheet ADP151 140 In the case where the board temperature is known, use the thermal characterization parameter, JB, to estimate the junction temperature rise (see Figure 57 and Figure 58). Maximum junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (PD) using the following formula: The typical value of JB is 58C/W for the 4-ball WLCSP package, 43C/W for the 5-lead TSOT package, and 28.3C/W for the 6-lead LFCSP package. 140 80 60 40 20 0 0.3 MAXIMUM JUNCTION TEMPERATURE ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 1.3 120 1.8 ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA 2.3 2.8 3.3 VIN - VOUT (V) 3.8 4.3 4.8 Figure 58. TSOT, TA = 85C 100 140 MAXIMUM JUNCTION TEMPERATURE 60 40 20 0 0.3 ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 1.3 1.8 ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA 2.3 2.8 3.3 VIN - VOUT (V) 3.8 4.3 4.8 Figure 57. WLCSP, TA = 85C 120 100 80 60 40 20 0 0.3 ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 1.3 ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA 2.3 3.3 VIN - VOUT (V) Figure 59. LFCSP, TA = 85C Rev. E | Page 19 of 24 4.3 5.3 08627-059 JUNCTION TEMPERATURE, TJ (C) 80 08627-043 JUNCTION TEMPERATURE, TJ (C) 100 08627-044 (5) JUNCTION TEMPERATURE, TJ (C) TJ = TB + (PD x JB) MAXIMUM JUNCTION TEMPERATURE 120 ADP151 Data Sheet PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS Heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the ADP151. However, as listed in Table 6, a point of diminishing returns is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. 08627-046 Place the input capacitor as close as possible to the VIN and GND pins. Place the output capacitor as close as possible to the VOUT and GND pins. Use of 0402 or 0603 size capacitors and resistors achieves the smallest possible footprint solution on boards where area is limited. 08627-045 Figure 61. Example WLCSP PCB Layout 08627-054 Figure 60. Example TSOT PCB Layout Figure 62. Example LFCSP PCB Layout Rev. E | Page 20 of 24 Data Sheet ADP151 OUTLINE DIMENSIONS 2.90 BSC 5 4 2.80 BSC 1.60 BSC 1 2 3 0.95 BSC 1.90 BSC *0.90 MAX 0.70 MIN *1.00 MAX 0.50 0.30 8 4 0 SEATING PLANE 0.60 0.45 0.30 100708-A 0.10 MAX 0.20 0.08 *COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS. Figure 63. 5-Lead Thin Small Outline Transistor Package [TSOT] (UJ-5) Dimensions show in millimeters 0.660 0.600 0.540 0.430 0.400 0.370 0.800 0.760 SQ 0.720 SEATING PLANE 2 1 A 0.280 0.260 0.240 BALL A1 IDENTIFIER B 0.40 BALL PITCH BOTTOM VIEW 0.230 0.200 0.170 (BALL SIDE UP) 0.050 NOM COPLANARITY 011509-A TOP VIEW (BALL SIDE DOWN) Figure 64. 4-Ball Wafer Level Chip Scale Package [WLCSP] (CB-4-3) Dimensions show in millimeters 1.70 1.60 1.50 2.00 BSC SQ 0.65 BSC 6 4 1.10 1.00 0.90 EXPOSED PAD 0.425 0.350 0.275 1 3 TOP VIEW 0.60 0.55 0.50 SEATING PLANE BOTTOM VIEW 0.05 MAX 0.02 NOM 0.35 0.30 0.25 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.20 REF Figure 65. 6-Lead Lead Frame Chip Scale Package [LFCSP_UD] 2.00 mm x 2.00 mm Body, Ultra Thin, Dual Lead (CP-6-3) Dimensions show in millimeters Rev. E | Page 21 of 24 PIN 1 INDICATOR (R 0.15) 05-04-2010-A PIN 1 INDEX AREA ADP151 Data Sheet ORDERING GUIDE Model 1 ADP151ACBZ-1.1-R7 ADP151ACBZ-1.2-R7 ADP151ACBZ-1.5-R7 ADP151ACBZ-1.8-R7 ADP151ACBZ-2.5-R7 ADP151ACBZ-2.6-R7 ADP151ACBZ-2.75-R7 ADP151ACBZ-2.8-R7 ADP151ACBZ-2.85-R7 ADP151ACBZ-3.0-R7 ADP151ACBZ-3.3-R7 ADP151ACBZ-2.1-R7 ADP151AUJZ-1.2-R7 ADP151AUJZ-1.5-R7 ADP151AUJZ-1.8-R7 ADP151AUJZ-2.5-R7 ADP151AUJZ-2.8-R7 ADP151AUJZ-3.0-R7 ADP151AUJZ-3.3-R7 ADP151ACPZ-1.2-R7 ADP151ACPZ-1.5-R7 ADP151ACPZ-1.8-R7 ADP151ACPZ-2.5-R7 ADP151ACPZ-2.7-R7 ADP151ACPZ-2.8-R7 ADP151ACPZ-3.0-R7 ADP151ACPZ-3.3-R7 ADP151UJZ-REDYKIT ADP151CPZ-REDYKIT ADP151CB-3.3-EVALZ Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Output Voltage (V) 2 1.1 1.2 1.5 1.8 2.5 2.6 2.75 2.8 2.85 3.0 3.3 2.1 1.2 1.5 1.8 2.5 2.8 3.0 3.3 1.2 1.5 1.8 2.5 2.7 2.8 3.0 3.3 Package Description 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 5-Lead TSOT 5-Lead TSOT 5-Lead TSOT 5-Lead TSOT 5-Lead TSOT 5-Lead TSOT 5-Lead TSOT 6-Lead LFCSP_UD 6-Lead LFCSP_UD 6-Lead LFCSP_UD 6-Lead LFCSP_UD 6-Lead LFCSP_UD 6-Lead LFCSP_UD 6-Lead LFCSP_UD 6-Lead LFCSP_UD Evaluation Board Kit Evaluation Board Kit Evaluation Board Package Option 3 CB-4-1 CB-4-3 CB-4-3 CB-4-3 CB-4-3 CB-4-3 CB-4-3 CB-4-3 CB-4-3 CB-4-3 CB-4-3 CB-4-3 UJ-5 UJ-5 UJ-5 UJ-5 UJ-5 UJ-5 UJ-5 CP-6-3 CP-6-3 CP-6-3 CP-6-3 CP-6-3 CP-6-3 CP-6-3 CP-6-3 Z = RoHS Compliant Part. For additional voltage options for the ADP151ACBZ package option, contact a local Analog Devices, Inc., sales or distribution representative. 3 The ADP151ACBZ package option is halide free. 1 2 Rev. E | Page 22 of 24 Branding 8R 4R 4S 4T 4U 8Q 4V 4X 4Y 4Z 50 5E LF6 LF7 LF8 LF9 LFG LFH LFJ LF6 LF7 LF8 LF9 LKZ LFG LFH LFJ Data Sheet ADP151 NOTES Rev. E | Page 23 of 24 ADP151 Data Sheet NOTES (c)2010-2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08627-0-4/12(E) Rev. E | Page 24 of 24