MOTOROLA CMOS LOGIC DATA 1
MC14580B
The MC14580B is a 4 by 4 multiport register useful in small scratch pad
memories, arithmetic operations when coupled with an adder , and other data
storage applications. It allows independent reading of any two words (or the
same word at both outputs) while writing into any one of four words.
Address changing and data entry occur on the rising edge of the clock.
When the write enable input is low, the contents of any word may be
accessed but not altered.
•No Restrictions on Clock Input Rise or Fall Times
•3–State Outputs
•Single Phase Clocking
•Supply Voltage Range = 3.0 Vdc to 18 Vdc
•Capable of Driving Two Low–power TTL Loads or one Low–power
Schottky TTL Load Over the Rated Temperature Range
•Pin Compatible with CD40108
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol Parameter Value Unit
VDD DC Supply Voltage – 0.5 to + 18.0 V
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current (DC or Transient),
per Pin ± 10 mA
PDPower Dissipation, per Package† 500 mW
Tstg Storage Temperature – 65 to + 150
_
C
TLLead Temperature (8–Second Soldering) 260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_
C From 65
_
C To 125
_
C
Ceramic “L” Packages: – 12 mW/
_
C From 100
_
C To 125
_
C
BLOCK DIAGRAM
CLOCK 16
15
20
19
17
19
18
DATA
INPUT
WE
R1B
R0B
R1A
R0A
W1W0 1011141398
DECODER 3–STATE A
3
4
5
6
7
22
23
2
1
21
3–STATE B
4 X 4
MEMORY
VDD = PIN 24
VSS = PIN 12
D0
D1
D2
D3
Q0A
Q1A
Q2A
Q3A
Q0B
Q1B
Q2B
Q3B
WORD A
OUTPUT
WORD B
OUTPUT
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
L SUFFIX
CERAMIC
CASE 623
ORDERING INFORMATION
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBDW SOIC
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 709
DW SUFFIX
SOIC
CASE 751E
PIN ASSIGNMENT
Q2A
Q0A
3–STATE A
Q2B
Q3B
WRITE 0
Q3A
Q1AD0
3–STATE B
Q0B
Q1B
VDD
WE
CLOCK
D3
5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
13
11
12
21
22
23
24
READ 0A
READ 1A
D2
D1
READ 0B
VSS
READ 1B
WRITE 1
MOTOROLA CMOS LOGIC DATAMC14580B
2
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Symbol
VDD
Vdc
– 55
_
C 25
_
C 125
_
C
Unit
Characteristic
Symbol
VDD
Vdc
Min Max Min Typ # Max Min Max
Unit
Output Voltage “0” Level
Vin = VDD or 0 VOL 5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
Vin = 0 or VDD VOH 5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Input Voltage “0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL 5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
Vdc
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH 5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
IOH 5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
mAdc
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOL 5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current Iin 15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdc
Input Capacitance
(Vin = 0) Cin — — — — 5.0 7.5 — — pF
Quiescent Current
(Per Package) IDD 5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.010
0.020
0.030
5.0
10
20
—
—
—
150
300
600
µAdc
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
IT5.0
10
15
IT = (1.18 µA/kHz) f + IDD
IT = (1.91 µA/kHz) f + IDD
IT = (2.67 µA/kHz) f + IDD
µAdc
Three–State Leakage Current ITL 15 — ±0.1 — ±0.0001 ±0.1 — ±3.0 µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’ s potential performance.
**The formulas given are for the typical characteristics only at 25
_
C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However ,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.
MOTOROLA CMOS LOGIC DATA 3
MC14580B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25
_
C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH, tTHL
(Figures 3 and 6) 5.0
10
15
—
—
—
100
50
40
200
100
80
ns
Propagation Delay Time
Clock to Output tPLH, tPHL
(Figures 3 and 6) 5.0
10
15
—
—
—
650
250
170
1300
500
340
ns
Write Enable Setup Time
(Enabling a Write or Read) tsu
(Figure 5) 5.0
10
15
800
300
200
400
150
100
—
—
—
ns
Write Enable Removal Time
(Disabling a Write or Read) trem
(Figure 5) 5.0
10
15
0
0
0
– 100
– 50
– 35
—
—
—
ns
Setup Time**
Address, Data to Clock tsu
(Figure 3) 5.0
10
15
50
30
25
20
0
0
—
—
—
ns
Hold Time**
Clock to Address, Data th
(Figure 3) 5.0
10
15
480
195
150
160
65
50
—
—
—
ns
3–State Enable/Disable Delay Time tPHZ, tPLZ
tPZH, tPZL
(Figures 4 and 7)
5.0
10
15
—
—
—
130
60
45
260
120
90
ns
Clock Pulse Width tw
(Figure 3) 5.0
10
15
820
330
220
410
165
110
—
—
—
ns
**When loading repetitive highs, the output may glitch low momentarily after the rising edge of Clock. However , data integrity remains unaffected
and data is valid after the propagation delays listed in the Switching Characteristics Table.
Figure 1. Output Drive Current Test Circuit
Sink Current Source Current
Position of S1 2 1
VGS = VDD – VDD
VDS = Vout Vout – VDD
EXTERNAL
POWER
SUPPLY
Vout
IDS
VDD
VSS
PULSE
GENERATOR
VDD
VSS S1
1
2
WE
W0
W1
R0A
R1A
R0B
R1B
C
D0
D1
D2
D3
Q0A
Q1A
Q2A
Q3A
Q0B
Q1B
Q2B
Q3B
MOTOROLA CMOS LOGIC DATAMC14580B
4
Figure 2. Power Dissipation Test Circuit and Waveforms (3–State Inputs are High)
PULSE
GENERATOR
1
PULSE
GENERATOR
2
PULSE
GENERATOR
3
VDD IDD
WE
W0
W1
R0A
R1A
R0B
R1B
C
D0
D1
D2
D3
Q0A
Q1A
Q2A
Q3A
Q0B
Q1B
Q2B
Q3B
VSS CL
CL
CL
CL
CL
CL
CL
CLREPETITIVE WAVEFORMS
P.G. 1
P.G. 2
P.G. 3
OUTPUT
Qn A, B
Figure 3. Figure 4.
CLOCK
ADDRESS DATA
Q
tw(H) tw(L) VDD
VSS
VDD
VSS
VOH
VOL
50%
tsu th
50%
tPLH, tPHL
tTLH, tTHL
50% 90%
10%
3–STATE
A OR B
VDD
VSS
VOH
VOL
VOH
VOL
QA
QB
tPHZ 90%
50% 50%
10%
90%
10%
tPZL
tPZH
tPZL
CLOCK
WE
tsu trem
50%
50%
50% 50% VDD
VSS
VDD
VSS
DEVICE
UNDER
TEST
Q
CL
DEVICE
UNDER
TEST
Q
CL
1 k
Ω
CONNECT TO VCC WHEN TESTING tPLZ AND tPZL
CONNECT TO GND WHEN TESTING tPHZ AND tPZH
Figure 5. Figure 6. Test Circuit
Figure 7. Test Circuit
MOTOROLA CMOS LOGIC DATA 5
MC14580B
LOGIC DIAGRAM
16
15
17
18
19
20
9
8
W0
W1
D0
D1
D2
D3
WE
CLOCK
R0A
13
C
D Q
C
DQ
C
DQ
C
DQ
C
D Q
Q
C
DQ
Q
R0B
11 3–STATE A
3
R1A
14 R1B
10
C
DQ
Q C
D Q
Q C
DQ
Q C
DQ
Q
C
D
3–STATE
Q
C
D
3–STATE
Q
C
D
3–STATE
Q
C
D
3–STATE
Q
C
D
3–STATE
Q
C
D
3–STATE
Q
C
D
3–STATE
Q
C
D
3–STATE
Q
21
3–STATE B
7
6
5
4
1
2
23
22
Q3A
Q2A
Q1A
Q0A
Q3B
Q2B
Q1B
Q0B
TRUTH TABLE
Clock WE Write 1 Write 0 Read 1ARead 0ARead 1BRead 0B3–State A 3–State B DnQnA QnB
1 0 1 0 1 0 1 1 1 1 1 1
1 0 1 0 1 0 1 1 1 0 0 0
X X X X X X X 1 1 X No
Change No
Change
X X X X X X X X 0 0 X Z Z
0 X X X X X X X 1 1 X No
Change No
Change
1 X X X X X X X 1 1 X No
Change No
Change
1 0 0 0 1 1 0 1 1 Dn to
word 0 Contents
of word 1
displayed
Contents
of word 2
displayed
0 0 0 0 1 1 0 1 1 Word 0
not
altered
Contents
of word 1
displayed
Contents
of word 2
displayed
Z = High Impedance
X = Don’t Care
MOTOROLA CMOS LOGIC DATAMC14580B
6
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 709–02
ISSUE C
L SUFFIX
CERAMIC DIP PACKAGE
CASE 623–05
ISSUE M
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A31.37 32.13 1.235 1.265
B13.72 14.22 0.540 0.560
C3.94 5.08 0.155 0.200
D0.36 0.56 0.014 0.022
F1.02 1.52 0.040 0.060
G2.54 BSC 0.100 BSC
H1.65 2.03 0.065 0.080
J0.20 0.38 0.008 0.015
K2.92 3.43 0.115 0.135
L15.24 BSC 0.600 BSC
M0 15 0 15
N0.51 1.02 0.020 0.040
_ _ _ _
1 12
1324
B
H
A
FD
G
K
SEATING
PLANE
N
C
MJ
L
NOTES:
1. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
2. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION (WHEN FORMED
PARALLEL).
1 12
24 13
B
A
SEATING
PLANE
F
D
GK
N
C
MJ
L
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A31.24 32.77 1.230 1.290
B12.70 15.49 0.500 0.610
C4.06 5.59 0.160 0.220
D0.41 0.51 0.016 0.020
F1.27 1.52 0.050 0.060
G2.54 BSC 0.100 BSC
J0.20 0.30 0.008 0.012
K3.18 4.06 0.125 0.160
L15.24 BSC 0.600 BSC
M0 15 0 15
N0.51 1.27 0.020 0.050
_ _ _ _
MOTOROLA CMOS LOGIC DATA 7
MC14580B
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751E–04
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
–A–
–B– P12X
D24X
12
1324
1
M
0.010 (0.25) B M
S
A
M
0.010 (0.25) B S
T
–T–
G
22X
SEATING
PLANE
K
C
RX 45
_
M
F
J
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A15.25 15.54 0.601 0.612
B7.40 7.60 0.292 0.299
C2.35 2.65 0.093 0.104
D0.35 0.49 0.014 0.019
F0.41 0.90 0.016 0.035
G1.27 BSC 0.050 BSC
J0.23 0.32 0.009 0.013
K0.13 0.29 0.005 0.011
M0 8 0 8
P10.05 10.55 0.395 0.415
R0.25 0.75 0.010 0.029
____
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided
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MC14580B/D
*MC14580B/D*
◊
