PRELIMINARY CY7C1006 256K x 4 Static RAM Features Functional Description Reading from the device is accomplished . . : by taking chip enable (CE) and output en- * High speed The CY7C1006 is a high-performance able (OF) LOW while forcing write enable taa = 12 ns CMOS static RAM organized as 262,144 (WE) HIGH. Under these conditions, the CMOS for optimum speed/power e Low active power words by 4 bits. Easy memory expansion is provided by an active LOW chip enable (CE), an active LOW output enable (OE), and three-state drivers. The device has an contents of the memory location specified by the address pins will appear on the four I/O pins. 910 mW . automatic power-down feature that re- : : * Low standby power duces power consumption by more than VO.)are eae Micimpedunce eters 275 mW 65% when deselected, when the device is deselected (CE HIGH), @ 2.0V data retention (optional) Writing to the device is accomplished by the outputs are disabled (OE HIGH), or 100,.W taking chip enable (CE) and write enable during a write operation (CE and WE e Automatic power-down when deselected (WE) inputs LOW, Data on the four I/O pins (I/O 9 through I/Q3) is then written into the location specified on the address LOW). The CY7C1006 is available in standard e TITL-compatible inputs and outputs pins (Ag through Aj7). 300-mil-wide DIPs and SOJs. Logic Block Diagram Pin Configuration DIP/SOJ Top View INPUT BUFFER Ay COLUMN DECODER eorn OF YU Oh Tre PrTrenrrtre Pe Teddatitada Ag o Og As a o Ag Oo = VO. As Ww B12 x 512 x4 a ? Ae ARRAY o Ay = < VO, Ag & 0 Ag VO 1006-1 Selection Guide 7C1006 -B2 7C100615 7C100620 7C100625 Maximum Access Time (ns) 12 15 20 25 Maximum Operating Current (mA) Commercial 165 155 145 130 Military 165 150 140 Maximum Standby Current (mA} Commercial 50 30 30 30 Military 40 30 30 Shaded area contains advanced information. Cypress Semiconductor Corporation 3901 North First Street @ SanJose @ CA95134 @ 408-943-2600 November 1991 Revised February 1996PRELIMINARY CY7C1006 Maximum Ratings (Above which the useful life maybe impaired. Foruser guidelines, Static Discharge Voltage ..............00 000 eee >2001V not tested.) (per MIL-STD-883, Method 3015) Storage Temperature ..........0000005, 65Cto +150C - Latch-Up Current .......... 0... eer ee rere >200 mA Ambient Temperature with * Power Applied ......ssseeseeeeeeeeees -s5C1o +125 Operating Range Supply Voltage on Vcc Relative to GNDU!) , -0,5V to +7.0V Range Temperatnn 2] Vee DC Voltage Applied to Outputs : in High Z State sn eeeevses -0.5V to Vcc + 0.5V Commercial OC to +70C SV + 10% DC Input Voltagel!] ......0......... -0.5V to Vcc + 0.5V Military 55C to +125C 5V + 10% Current into Outputs (LOW) ...............00 ees 20 mA Electrical Characteristics Over the Operating Rangel?) 7C100612 | 7C1006-15 | 7C1006-20 | 7C100625 Parameter Description Test Conditions Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit Vou Output HIGH Vcc = Min., 24 2.4 24 24 Vv Voltage lon = 4.0mA VoL Output LOW Voc = Min, Io, = 8.0mA 0.4 0.4 0.4 0.4 Vv Voltage Vin Input HIGH 22 | Vcc | 2.2 | Veco | 2.2 | Vee 2.2 | Vcc Vv Voltage +03 +03 + 0.3 +03 VIL Input LOW -03 | 08 | -03]) 08 7-03] 08 | -03] 08 Vv Voltagel!] Tix InputLoadCurrent | GND < Vj < Voc ~1 +1 -1 +1 -1 +1 -1 +1 | pA loz Output Leakage GND < V] < Vee, 5 +5 -5 +5 -5 +5 -5 +5 pA Current Output Disabled los Output Short Veco = Max., 300 300 300 300 | mA Circuit Currentl4]) | Vour = GND Tec Vec Operating Vcc = Max. Com'l 165 155 140 130 | mA Supply Current Iputr = 0 mA, - f = fMax = lite | Mil 165 150 140 Isp Automatic CE Max. Vcc, Com! 50 30 30 30 | mA Power-Down CE > Vin, Current Vin = Vin or - TTL Inputs Vin = Vin. Mil 40 30 30 f = fax Isp Automatic CE Max. Vcc Com'l 10 10 10 10 | mA Power-Down CE > Voc 03V, Current Vin= Vec-0.3v LL 2 2 2 2 CMOS Inputs | or Vin < 0.39, f=0 | Mil 10 10 10 L 2 2 2 Shaded area contains advanced information. Capacitance) Parameter Description Test Conditions Max. Unit Cin: Addresses Input Capacitance Ta = 25C, f = 1 MHz, 7 pF - Voc = 5.0V Cin: Controls 10 pF Cout Output Capacitance 10 pF Notes: 1. Vy. Gnin.} = 2.0V for pulse durations of less than 20 ns. 2. Ty is the instant on case temperature. 4, Not morethan 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 3, See the last page of this specification for Group A subgroup testing in- 5. Tested initially and after any design or process changes that may affect these parameters. formation.PRELIMINARY CY7C1006 R1 4802 R1 4802 ALL INPUT PULSES N Oo N Oo 3.0V 90% 90% OUTPUT oT 3 OUTPUT oT_4 = Re 5 oF = Re GND 1% 30 rT f 2550 Lf 2se 3 L 3 INCLUDING = = INCLUDING == = sens sens JIG AND JIG AND SCOPE SCOPE (a) (b) 1006-3 1006-4 Equivalent to: THEVENIN EQUIVALENT 1672 OUTPUT O_wa 0~O=*i_73V Switching Characteristics Over the Operating Rangel3. 6] 7C100612 7C100615 7C100620 7C100625 Parameter Description Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit READ CYCLE tre Read Cycle Time 12 15 20 25 ns taa Address to Data Valid 12 15 20 25 ns toHA Data Hold from Address Change 3 3 3 3 ns tace CE LOW to Data Valid 12 15 20 25 ns tpoE OE LOW to Data Valid 6 7 8 10 ns tLZOR OE LOW to Low Z 0 0 0 0 ns tHZ0R OE HIGH to High ZI? 8] 6 7 8 10 ns tLZCE CE LOW to Low ZI] 3 3 3 3 ns tHzcE CE HIGH to High ZI. 8] 6 7 8 10 ns teu CE LOW to Power-Up 0 0 0 0 ns tpp CE HIGH to Power-Down 12 15 20 25 ns WRITE CYCLEL. 1 two Write Cycle Time 12 15 20 25 ns tscR CE LOW to Write End 10 12 15 20 ns taw Address Set-Up to Write End 10 12 15 20 ns tHa Address Hold from Write End 0 0 0 0 ns tsa Address Set-Up to Write Start 6 0 0 0 ns tpwE WE Pulse Width 10 12 15 20 ns tsp Data Set-Up to Write End 7 8 10 1s ns typ Data Hold from Write End 0 0 0 0 ns tL7weE WE HIGH to Low Z3) 3 3 3 3 ns tHZWE WE LOW to High Zl. 3] 6 7 8 10 ns Shaded area contains advanced information. Notes: __ 6. Test conditions assume signal transition time of 3 nsorless.timingref- 9. The internal write time of the memory is defined by the overlap of CE erence levels of 1.5V. inputpulse levels of Oto 3.0V. and output loading and WE LOW. CE and WE must be LOW to initiate a write, and the of the specified Ig] /Ipy and 30-pF load capacitance. transition of either of these signals can terminate the write. The input 7. tyzor. tuzce. and tyzwpare specified with aload capacitance of 5 pF data set-up and hold timing should be referenced to the leading edge as in part (b} of AC Test Loads. Transition is measured +500 mV from of the signal that terminates the write. _ steady-state voltage. 10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, 8. At any given temperature and voltage condition. tyzcp is less than OE LOW) is the sum of tyzwe and tgp. tizce. tyzog is less than tLzog. and tyzwe is less than tp7wefor any given device.PRELIMINARY CY7C1006 Data Retention Characteristics Over the Operating Range (L Version Only) Commercial Military Parameter Description Conditions!!!) Min. | Max. | Min. | Max. | Unit Vpr Vcc for Data Retention 2.0 2.0 Vv Iccpr Data Retention Current Vcc = Vopr = 2.09, 50 70 pA - - - CE > Vcc 0.39, tcpr] Chip Deselect to Data Retention Time Vin = Vec 0.3V or 0 0 ns tpbl Operation Recovery Time Vin = 0.3V tre tre ns Data Retention Waveform DATA RETENTION MODE + Voc 45V Vor = 2V | 4 tcor tp > G1008-5 Switching Waveforms Read Cycle No. 1[!2, 13] 7 IRC >| ADDRESS > 4 bl toa x p' ton, 4J DATA OUT PREVIOUS DATA VALID KK DATA VALID G1006-6 Read Cycle No. 2 (OE Controlled)[13. 14] ADDRESS CE tpoe HIGH IMPEDANCE tLZ0E HIGH IMPEDANCE DATA OUT DATA VALID tizce Voc SUPPLY CURRENT tpy Icc ISB 1006-7 Notes: 11. No input may exceed Voc + 05V. 13. WE is HIGH for read cycle. 12. Device is continuously selected, OE and CE = Vy. 14. Address valid prior to or coincident with CE transition LOW.PRELIMINARY CY7C1006 Switching Waveforms (continued) Write Cycle No. 1 (CE Controllea)l>. 16] 7 twe * ADDRESS * * a tsa - taw ~e tHa tpwe FE Raw. LLL _ i ere tr DATA VO DATA VALID C1006-8 Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[!5- 16] two ~ ADDRESS * x }* tsce = Wok Viti taw whe tn tsa - a tpwe - re WOK x OEY e tsp etee} tp DATA 1/0 XXX K DATA VALID ht tHZ0E C1006-9 Notes: 15. IfCEgoes HIGH simultaneously with WE going HIGH, the outputre- 16. Data I/O is high impedance if OE = V)y. mains in a high-impedance state.PRELIMINARY CY7C1006 Switching Waveforms Write Cycle No. 3 (WE Controlled, OF LOW) 16] < twe - ADDRESS 4 x } tsce - ce WH LZ C2 at taw = tha >] ht tos at tpwe We 4 We N 7 a tsp aee tp oaravo KKK KKK onmvaus | >>-K KOO tHzwe e ti2ve G1008-10 Truth Table CE | OF | WE] V0, -T/0; Mode Power H | X | X | HighZ Power-Down Standby (Isp) L | L |] AY] DataOut Read Active (Icc) L | X | L | Dataln Write Active (Icc) L | H] AY] HighZ Selected, Outputs Disabled | Active (Icc)Document #: 38-00201-C PRELIMINARY CY7C1006 Ordering Information Speed Package Operating (ns) Ordering Code Name Package Type Range 12 CY7C1006~12PC P21 28-Lead (300-Mil)} Molded DIP Commercial CY7C100612VC V2i1 28-Lead (300-Mil) Molded SO} 15 CY7C1006-15PC P21 28-Lead (300-Mil) Molded DIP Commercial CY7C1006-15VC v21 28-Lead (300-Mil) Molded SOF CY7C1006-15DMB D22 28-Lead (300-Mil) CerDIP Military 20 CY7C1006-20PC P21 28-Lead (300-Mil) Molded DIP Commercial CY7C1006-20VC v21 28-Lead (300-Mil) Molded SOF CY7C1006-20DMB D22 28-Lead (300-Mil) CerDIP Military 25 CY7C1006-25PC P21 28-Lead (300-Mil) Molded DIP Commercial CY7C1006-25VC v21 28-Lead (300-Mil} Molded SO] CY7C1006-25DMB D22 28-Lead (300-Mil) CerDIP Military Shaded area contains advanced information. Contact factory for L version availability. MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Switching Characteristics Parameter Subgroups Parameter Subgroups VoH 1, 2,3 READ CYCLE VoL 1, 2,3 tre 7, 8,9, 10, 11 Vin 1,2,3 taa 7,8, 9,10, 11 Vi Max. 1, 2,3 toHa 7, 8, 9, 10, 11 Iix 1, 2,3 tack 7, 8, 9, 10, 11 loz, 1, 2,3 tpor 7, 8, 9, 10, 11 lec 1, 2,3 WRITE CYCLE Ispi 1, 2,3 twec 7, 8, 9, 10, 11 Isp 1, 2,3 tsce 7, 8, 9, 10, 11 taw 7, 8,9, 10, 11 tHA 7, 8, 9, 10, 11 tsa 7, 8, 9, 10, 11 tpwE 7, 8, 9, 10, 11 tsp 7, 8,9, 10, 11 typ 7, 8, 9, 10, 11PRELIMINARY Package Diagrams 28-Lead (300-Mil) CerDIP D22 MIL-STD-1835 D-15 Config. A PIn 1, oop eoneeooaMm ; )) J als | a 4 WOOO OOo oS Oo MIM, SE DIMENSIONS In INCHES Mas =] ree 155 Zar | ia HI 0 yl ft nee re i re SEATING PLANE 28-Lead (300-Mil) Molded DIP P21 PIN 1 r hh f DIMENSIONS IN INCHET MIN. Mas. ( w250 ero : t TOP or oe a O02 0.080 ia ZEATING PLANE zen 1425 28 ot ; c ql 440 filet mee TORE } f_ense _ ous | A ol80 | ft | | | us ne f _ 2 MIM, O.1i0 CY7C1006PRELIMINARY CY7C1006 Package Diagrams (continued) 28-Lead (300-Mil) Molded SOJ V21 PIM 1 ID DIMENSION? IM TMHCHES MI-, eg? W713 |b Tin | o.007 u.140 {_ 1.0 m * 0.013 THR, ine 025 MIM, here Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied ina Cypress Semiconductor Corporation product. Nor does it convey or imply any license under patent or otherrights. Cypress Semicon- ductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems applications implies that the manufacturer assumes all risk of such use and in so doing indemnifies Cypress Semiconductor against all damages.