W83195BR-341 Data Sheet WINBOND CLOCK GENERATOR FOR VIA P4/KT SERIES CHIPSET -1- Publication Release Date: April 13, 2005 Revision 1.1 W83195BR-341 Table of Contents1. GENERAL DESCRIPTION ..........................................................................................................1 2. FEATURES ..................................................................................................................................1 3. PIN CONFIGURATION ................................................................................................................2 4. BLOCK DIAGRAM .......................................................................................................................3 5. PIN DESCRIPTION......................................................................................................................3 5.1 Crystal I/O ........................................................................................................................................ 4 5.2 CPU, AGP, PCI Clock Outputs ....................................................................................................... 4 5.3 Fixed Frequency Outputs................................................................................................................ 5 5.4 DRAM Buffer.................................................................................................................................... 5 5.5 I2C Control Interface ....................................................................................................................... 5 5.6 Output Control Pins ......................................................................................................................... 6 5.7 Power an GND Pins ........................................................................................................................ 6 6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE .................................................7 7. I2C CONTROL AND STATUS REGISTERS ................................................................................8 7.1 Register 0: Frequency Select (Default = 08h) ................................................................................ 8 7.2 Register 1: SRC/CPU Clock (1 = Enable, 0 = Disable) (Default: A1h).......................................... 8 7.3 Register 2: PCI Clock (1 = Enable, 0 = Disable) (Default: FEh) .................................................... 9 7.4 Register 3: REF, 24_48,48,AGP Clock (1 = Enable, 0 = Disable) (Default: F7h)......................... 9 7.5 Register 4,5 Reserved..................................................................................................................... 9 7.6 Register 6: M/N Program (Default: 8Bh).........................................................................................9 7.7 Register 7: M/N Program (Default: 2Fh).......................................................................................10 7.8 Register 8: Spread Spectrum Program (Default: 1Fh).................................................................10 7.9 Register 9: Divider Ratio (Default: 03h) ........................................................................................10 7.10 Register 10: Control (Default: 0Ah)........................................................................................11 7.11 Register 11: Control (Default: E7h)........................................................................................12 7.12 Register 12: Control (Default: 3Ch) .......................................................................................12 7.13 Register 13: Control (Default: 24h) ........................................................................................13 7.14 Register 14: Control (Default: 56h) ........................................................................................13 7.15 Register 15: Slew Rate Control (Default: 55h) ......................................................................13 7.16 Register 16: DRAM Buffer Control (1 = Enable, 0 = Disable) (Default: 7Fh).......................14 7.17 Register 17: Slew Rate Control (Default: CFh) .....................................................................14 7.18 Register 18: M/N Time & Type Control (Default: 5Bh)..........................................................14 7.19 Register 19: Reserved ...........................................................................................................15 7.20 Register 20: Winbond Chip ID - (Ready Only) (Default: 61h)..............................................15 - II - W83195BR-341 7.21 8. Register 21: Winbond Chip ID - (Ready Only) (Default: 50h)..............................................15 ACCESS INTERFACE ...............................................................................................................16 8.1 Block Write Protocol ......................................................................................................................16 8.2 Block Read Protocol......................................................................................................................16 8.3 Byte Write Protocol........................................................................................................................16 8.4 Byte Read Protocol........................................................................................................................16 9. SPECIFICATIONS .....................................................................................................................17 9.1 Absolute Maximum Ratings ..........................................................................................................17 9.2 General Operating Characteristics ...............................................................................................17 9.3 Skew Group Timing Clock ............................................................................................................17 9.4 CPU 0.7V Electrical Characteristics .............................................................................................18 9.5 CPU 1.0V Electrical Characteristics .............................................................................................18 9.6 AGP Electrical Characteristics ......................................................................................................18 9.7 PCI Electrical Characteristics........................................................................................................19 9.8 24M, 48M Electrical Characteristics .............................................................................................19 9.9 REF Electrical Characteristics.......................................................................................................19 10. ORDERING INFORMATION......................................................................................................20 11. HOW TO READ THE TOP MARKING.......................................................................................20 12. PACKAGE DRAWING AND DIMENSIONS...............................................................................21 13. REVISION HISTORY .................................................................................................................22 - III - Publication Release Date: April 13, 2005 Revision 1.1 W83195BR-341 1. GENERAL DESCRIPTION The W83195BR-341 is a Clock Synthesizer for Intel P4 Springdale/Prescott series chipset and support AMD Athlon processors. W83195BR-341 provides all clocks required for high-speed microprocessor and provides step-less frequency programming and 32 different frequencies of CPU, AGP, and PCI clocks setting. All clocks are externally selectable with smooth transitions. The W83195BR-341 provides I2C serial bus interface to program the registers to enable or disable each clock outputs and provides +/-0.25%, +/-0.5% center type and -0.5%, -1.0% down type spread spectrum or programmable S.S.T. scale to reduce EMI. The W83195BR-341 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. 2. FEATURES * 1 pairs differential clock for CPU (P4 or Athlon) * 1 pairs differential clock for Chipset * 3 AGP clock outputs * Support two DDR DIMMS or three SDRAM DIMMS * 7 PCI synchronous clocks, 1 free running * 1 48 MHz clock outputs for USB * 1 24_48 MHz for I/O chip, default 24 MHz * 2 REF 14.318MHz clock outputs * AGP leads PCICLK from 1.5 nS to 3.5 nS * I2C 2-Wire serial interface supports block and byte mode read/write * Step-less frequency programming * Smooth frequency switch with selections from 66 to 200 MHz * Programmable clock outputs Slew rate control and Skew control * +/- 0.25% center type spread spectrum in table mode * Programmable S.S.T. scale to reduce EMI * Programmable registers to enable/stop each output and select modes * Packaged in 56-pin SSOP -1- Publication Release Date: April 13, 2005 Revision 1.1 W83195BR-341 3. PIN CONFIGURATION F S 0 * /R E F 0 GND X IN XOUT VDDAGP AGP0 S E L P 4 _ K 7 * /A G P 1 AGP2 GND & F S 1 /P C I_ F & S E L S D _ D D /P C I1 M U L T S E L * /P C I2 GND P C I3 P C I4 VDDPCI P C I5 P C I6 GND F S 3 & /4 8 M h z F S 2 & /2 4 _ 4 8 M H z V DD48 VDD GND IR E F P D # * /R E S E T # SCLK* SD ATA* 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 #: Active low *: Internal pull up resistor 120K to VDD & : Internal Pull-down resistor 120K to GND -2- V T T _ P W R G D # /R E F 1 VDDR GND C P U T /C P U O D _ T C P U C /C P U O D _ C VDDC VDDI CPUCS_C CPUCS_T GND FBOUT B U F _ IN D D R T 0 /S D R A M 0 D D R C 0 /S D R A M 1 D D R T 1 /S D R A M 2 D D R C 1 /S D R A M 3 VDDD GND D D R T 2 /S D R A M 4 D D R C 2 /S D R A M 5 D D R T 3 /S D R A M 6 D D R C 3 /S D R A M 7 VDDD GND D D R T 4 /S D R A M 8 D D R C 4 /S D R A M 9 D D R T 5 /S D R A M 1 0 D D R C 5 /S D R A M 1 1 W83195BR-341 4. BLOCK DIAGRAM FBOUT D D R T (0 :5 )/ S D R A M ( 0 ,2 ,4 ,6 ,8 ,1 0 ) D D R C ( 0 :5 )/ 6 S D R A M (1 ,3 ,5 ,7 ,9 ,1 1 ) 6 B U F _ IN PLL2 48M H z 24_48M H z D iv id e r X IN XOUT 2 XTAL OSC PLL1 S p re a d S p e c tru m PD #* P C I_ S T O P # * CLK_STO P#* C P U T /C P U O D _ T C P U C /C P U O D _ C VCOCLK CPU CS_T C PU C S_C 3 M /N /R a tio ROM VTT_PW RGD # F S (0 :3 ) SELP4_K7* SELSD _D D & M U LTSEL* R E F 0 :1 A G P ( 0 :2 ) D iv id e r P C I_ F L a tc h & POR 6 P C I 1 :6 C o n tr o l L o g ic & C o n fig R e g is te r RESET# R re f IREF SDATA* SCLK* I2 C In te rfa c e 5. PIN DESCRIPTION BUFFER TYPE SYMBOL IN FUNCTION DESCRIPTION Input INtd120k Latch input pin and internal 120K pull down INtp120k Latch input pin and internal 120K pull up OUT OD I/O I/OD Output Open Drain Bi-directional Pin Bi-directional Pin, Open Drain # Active Low * Internal 120k pull-up & Internal 120k pull-down -3- Publication Release Date: April 13, 2005 Revision 1.1 W83195BR-341 5.1 Crystal I/O PIN PIN NAME TYPE 3 XIN IN 4 XOUT OUT DESCRIPTION Crystal input with internal loading capacitors (18pF) and feedback resistors. Crystal output at 14.318 MHz nominally with internal loading capacitors (18pF). 5.2 CPU, AGP, PCI Clock Outputs PIN 53, 52 49, 48 7 6 8 10 11 PIN NAME CPUT/CPUOD_T CPUC/CPUOD_C 14, 15, 17, 18 DESCRIPTION OUT Current Mode differential clock outputs for P4 CPU or Open Drain Mode differential clock outputs for K7 CPU, selected by hardware trapping power on 7 pin SELP4_K7* selecting. SELP4_K7 = 1 Current Mode, SELP4_K7 = 0 Open Drain Mode. CPUCS_C, CPUCS_T OUT 2.5V differential clock outputs for Chipset. AGP1 OUT 3.3V 66MHz clock output SELP4_K7* INtp120k AGP_0 OUT AGP2 OUT PCI_STOP#* INtp120k PCI_F OUT FS1& INtd120k PCI1 OUT SELSD_DD& PCI2 12 TYPE Power up Latched input to selecting pin 53,52 and 56 output type, SELP4_K7 = 1 the 53,52 is P4 Mode and pin 56 is VTT_PWRGD#, SELP4_K7 = 0 the 53,52 is K7 Mode and pin 56 is REF1.This is internal 120K pull up. 3.3V 66MHz clock output. 3.3V 66MHz clock output. PCI clock stop control pin, This pin is low active. Internal 120k pull up, Selected by Register 1 bit 6 = 0 and Register 9 bit 6 = 1, see Page 10 Table 2. 3.3V 33 MHz free running clock output. Latched input for FS1 at initial power up for H/W selecting the output frequency clocks. This is internal 120K pull down. 3.3V 33 MHz clock output. Latched input at initial power up for DRAM buffer output type INtd120k selecting, SELSD_DD = 0 DDR Mode SELSD_DD = 1 SDR Mode, This is internal 120K pull down. OUT MULTSEL* INtp120k PCI [3:6] OUT 3.3V 33MHz clock output. Power on trapping for different current reference. The reference current is referred for Pin 25 (IREF), see page 5 Table 1. This pin is latched during VTT_PWRGD#. This pin is internal pull up 120K. 3.3V 33 MHz clock outputs. -4- W83195BR-341 5.3 Fixed Frequency Outputs PIN 1 56 20 21 PIN NAME TYPE REF0 OUT FS0* INtp120k REF1 OUT DESCRIPTION 14.318 MHz output. Latched input for FS0 at initial power up for H/W selecting the output frequency clocks. This is internal 120K pull up. If SELP4_K7 = 0 this pin is 14.318 MHz output. If SELP4_K7 = 1 this pin is Power good input signal comes from ACPI with low active. This 3.3V input is level sensitive strobe used to determine FS [3:0] and MULTSEL input are valid and is ready to sample. This pin is low active. 48 MHz clock output. VTT_PWRGD# IN 48 MHz OUT FS3& INtd120k Latched input for FS3 at initial power up for H/W selecting the output frequency clocks. This is internal 120K pull down. 24_48 MHz OUT 24(default) or 48 MHz clock output, select by register 4 bit 7 SEL24 FS2& INtd120k Latched input for FS2 at initial power up for H/W selecting the output frequency clocks. This is internal 120K pull down. 5.4 DRAM Buffer PIN PIN NAME TYPE 45 BUF_IN IN 46 FBOUT OUT 44, 42, DDRT[0:5] 38, 36, SDRAM [0, 2, 4, 32, 30 6, 8, 10] OUT 43, 41, DDRC[0:5] 37, 35, SDRAM [1, 3, 5, 31, 29 7, 9, 11] OUT DESCRIPTION Reference input from chipset. 2.5V input for DDR only mode. 3.3V for standard SDRAM mode. Feedback clock for chipset. Output voltage depends on VDDD Clock outputs. SELSD_DD = 1, these pins are copies of BUF_IN. SELSD_DD = 0, these pins are copies of BUF_IN. Voltage depends on the VDDD. Clock outputs. SELSD_DD = 1, these pins are complementary copies of BUF_IN. SELSD_DD = 0, these pins are copies of BUF_IN. Voltage depends on the VDDD. 5.5 I2C Control Interface PIN PIN NAME TYPE DESCRIPTION 28 SDATA* I/OD Serial data of I2C 2-wire control interface with internal pull-up resistor 120K. 27 SCLK* IN Serial clock of I2C 2-wire control interface with internal pull-up resistor 120K. -5- Publication Release Date: April 13, 2005 Revision 1.1 W83195BR-341 5.6 Output Control Pins PIN PIN NAME TYPE DESCRIPTION Deciding the reference current for the CPUT/C pairs. The pin was connected to the precision resistor tied to ground to decide the appropriate current. The table is show as follows. TABLE 1 25 IREF OUT MULTSEL Board Target Reference R, Iref (PIN 11) Trace/ Term Z = VDD/(3*Rr) 1 50 Ohms 0 50 Ohms R = 475 1% Iref = 2.32mA R = 221 1% Iref = 5mA Output Current Ioh @ Z Ioh = 6*Iref 0.7V @ 50 Ioh = 4*Iref 1.0V @ 50 RESET# OD Select by register 1 bit 6 L_MODE if L_MODE = 1 this pin is System reset signal when the watchdog is time out. This pin will generate 250 mS when the watchdog timer is timeout PD#* IN Select by register 1 bit 6 L_MODE if L_MODE = 0 this pin is Power Down Function. This is internal 120K pull up. 26 5.7 Power an GND Pins PIN PIN NAME TYPE DESCRIPTION 5 VDDAGP PWR 3.3V power supply for AGP. 16 VDDPCI PWR 3.3V power supply for PCI. 22 VDD48 PWR 3.3V power supply for 48MHz. 23 VDD PWR 3.3V power supply analog core. 34,40 VDDD PWR 3.3V or 2.5V power for DRAM buffer part. 50 VDDI PWR 2.5V power supply for CPUCS_T/C. 51 VDDC PWR 3.3V power supply for CPUT/C. 55 VDDR PWR 3.3V power supply for REF 2, 9, 13, 19, 24, 33, 39, 47, 54 GND PWR Ground pin for 3.3 V -6- W83195BR-341 6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE This frequency table is used at power on latched FS [4:0] value or software programming at SSEL [4:0] (Register 0 bit 7 ~ 3). FS4 FS3 FS2 FS1 FS0 CPU (MHZ) AGP (MHZ) PCI (MHz) 0 0 0 0 0 66.8 66.8 33.4 0 0 0 0 1 99.9 66.6 33.3 0 0 0 1 0 120.2 60.1 30.0 0 0 0 1 1 133.2 66.6 33.3 0 0 1 0 0 72.0 72.0 36.0 0 0 1 0 1 105.1 70.1 35.0 0 0 1 1 0 160.1 64.0 32.0 0 0 1 1 1 140.1 70.1 35.0 0 1 0 0 0 77.0 77.0 38.5 0 1 0 0 1 110.0 73.3 36.7 0 1 0 1 0 180.3 60.1 30.0 0 1 0 1 1 166.6 66.6 33.3 0 1 1 0 0 90.1 60.1 30.0 0 1 1 0 1 99.9 66.6 33.3 0 1 1 1 0 199.8 66.6 33.3 0 1 1 1 1 133.2 66.6 33.3 1 0 0 0 0 160.1 80.1 40.0 1 0 0 0 1 164.0 82.0 41.0 1 0 0 1 0 166.6 66.6 33.3 1 0 0 1 1 169.9 67.9 34.0 1 0 1 0 0 175.1 70.0 35.0 1 0 1 0 1 180.3 72.1 36.1 1 0 1 1 0 184.8 73.9 37.0 1 0 1 1 1 190.0 76.0 38.0 1 1 0 0 0 66.8 66.8 33.4 1 1 0 0 1 100.9 67.3 33.6 1 1 0 1 0 133.6 66.8 33.4 1 1 0 1 1 200.5 66.8 33.4 1 1 1 0 0 66.6 66.6 33.3 1 1 1 0 1 99.9 66.6 33.3 1 1 1 1 0 199.8 66.6 33.3 1 1 1 1 1 133.2 66.6 33.3 -7- Publication Release Date: April 13, 2005 Revision 1.1 W83195BR-341 7. I2C CONTROL AND STATUS REGISTERS (The register No. Is increased by 1 if use byte data read/write protocol) 7.1 Register 0: Frequency Select (Default = 08h) BIT NAME PWD 7 SSEL [4] 0 6 SSEL [3] 0 5 SSEL [2] 0 4 SSEL [1] 0 3 SSEL [0] 1 FUNCTION DESCRIPTION Software frequency table selection through I2C Enable software table selection FS [4:0]. 2 EN_SSEL 0 0 = Hardware table setting (Jump mode). 1 = Software table setting through Bit7~3. (Jump less mode) Enable spread spectrum mode under clock output. 1 SPSPEN 0 0 = Spread Spectrum mode disable 1 = Spread Spectrum mode enable 0 Reserved 0 Reserved 7.2 Register 1: SRC/CPU Clock (1 = Enable, 0 = Disable) (Default: A1h) BIT 7 6 NAME CPUCS_T CPUCS_C L_MODE PWD 1 0 FUNCTION DESCRIPTION Pin 48,49 CPUCS_T/C output control Selection for Pin 26. Power Down Input / System Reset Control Output 1: System Reset feature 0: Power Down feature (Default) 5 CPUT/C 1 Pin 53,52 CPUT/C output control 4 FS4 0 Mapping software table. 3 FS3 X Power on latched value of FS3 (20) pin. Default 0 (Read only) 2 FS2 X Power on latched value of FS2 (21) pin. Default 0 (Read only) 1 FS1 X Power on latched value of FS1 (10) pin. Default 0 (Read only) 0 FS0 X Power on latched value of FS (1) pin. Default 1 (Read only) -8- W83195BR-341 7.3 Register 2: PCI Clock (1 = Enable, 0 = Disable) (Default: FEh) BIT NAME PWD FUNCTION DESCRIPTION 7 PCI_F 1 Pin 10 PCI_F output control 6 PCI6 1 Pin 18 PCI6 output control 5 PCI5 1 Pin 17 PCI5 output control 4 PCI4 1 Pin 15 PCI4 output control 3 PCI3 1 Pin 14 PCI3 output control 2 PCI2 1 Pin 12 PCI2 output control 1 PCI1 1 Pin 11 PCI1 output control 0 INV_CPUCS 0 Invert the CPUCS phase, 0: Default, 1: Inverse 7.4 Register 3: REF, 24_48,48,AGP Clock (1 = Enable, 0 = Disable) (Default: F7h) BIT NAME PWD FUNCTION DESCRIPTION 7 PREF1 1 Pin 56 REF1 output control 6 PREF0 1 Pin 1 REF0 output control 5 PUSB24 1 Pin 21 24_48 MHz output control 4 PUSB48 1 Pin 20 48 MHz output control 3 INV_USB48 0 Invert the 48 MHz phase, 0: In phase with 24_48 MHz, 1: 180 degrees out of phase 2 AGP2 1 Pin 8 AGP2 output control 1 AGP1 1 Pin 7 AGP1 output control 0 AGP0 1 Pin 6 AGP0 output control 7.5 Register 4,5 Reserved 7.6 Register 6: M/N Program (Default: 8Bh) BIT NAME PWD 7 N_DIV [8] 1 6 M_DIV [6] 0 5 M_DIV [5] 0 4 M_DIV [4] 0 3 M_DIV [3] 1 2 M_DIV [2] 0 1 M_DIV [1] 1 0 M_DIV [0] 1 FUNCTION DESCRIPTION Programmable N divisor value. Bit 7 ~0 are defined in the Register 7. Programmable M divisor value. -9- Publication Release Date: April 13, 2005 Revision 1.1 W83195BR-341 7.7 Register 7: M/N Program (Default: 2Fh) BIT NAME PWD 7 N_DIV [7] 0 6 N_DIV [6] 0 5 N_DIV [5] 1 4 N_DIV [4] 0 3 N_DIV [3] 1 2 N_DIV [2] 1 1 N_DIV [1] 1 0 N_DIV [0] 1 FUNCTION DESCRIPTION Programmable N divisor value bit 7~0. The bit 8 is defined in Register 6, Bit 7. The bit 9 is defined in Register 9, Bit 7. 7.8 Register 8: Spread Spectrum Program (Default: 1Fh) BIT NAME PWD 7 SP_UP [3] 0 6 SP_UP [2] 0 5 SP_UP [1] 0 4 SP_UP [0] 1 3 SP_DOWN [3] 1 2 SP_DOWN [2] 1 1 SP_DOWN [1] 1 0 SP_DOWN [0] 1 FUNCTION DESCRIPTION Spread Spectrum Up Counter bit 3 ~ bit 0. Spread Spectrum Down Counter bit 3 ~ bit 0 2's complement representation. Ex: 1 -> 1111; 2 -> 1110; 7 -> 1001; 8 -> 1000 7.9 Register 9: Divider Ratio (Default: 03h) BIT NAME PWD FUNCTION DESCRIPTION 7 N<9> 0 Programmable N divisor value bit 9 6 SEL_CLKSTOP 0 Refer to Table-2 5 Reserved 0 Reserved 4 Reserved 0 Reserved 3 Reserved 0 Reserved 2 DS2 0 1 DS1 1 0 DS0 1 Define the CPU/AGP/PCI divider ratio Refer to Table-3 - 10 - W83195BR-341 Table-2 Register 1 /bit 6 L_MODE Register 9/bit6 SEL_CLKSTOP PIN 26 PIN8 PIN18 0 0(default) PD# AGP2 PCI6 0 1 PD# PCI_STOP# CLK_STOP# 1 0 RESET# AGP2 PCI6 1 1 RESET# AGP2 PCI6 Table-3 CPU, AGP, PCI divider ratio selection Table DS2~DS0 CPU AGP PCI 000 2 5 10 001 2 6 12 010 3 6 12 011 4 6 12 100 6 6 12 101 3 7 14 110 4 8 16 111 4 10 20 7.10 Register 10: Control (Default: 0Ah) BIT NAME PWD FUNCTION DESCRIPTION 7 EN_MN_PROG 0 0: Output frequency depend on frequency table 1: Program all clock frequency by changing M/N value The equation is VCO =14.318MHz*(N+4)/ M. 6 N<10> 0 Programmable N divisor value bit 10 5 Reserve 0 4 Reserve 0 3 IVAL<3> 1 2 IVAL<2> 0 1 IVAL<1> 1 0 IVAL<0> 0 Reserved Charge pump current selection - 11 - Publication Release Date: April 13, 2005 Revision 1.1 W83195BR-341 7.11 Register 11: Control (Default: E7h) BIT 7 NAME CPUT_DRI PWD 1 FUNCTION DESCRIPTION CPUT output state in during POWER DOWN or Stop mode assertion. 0: Driven (2*Iref), 1: Tristate (Floating) CPUC always tri-state (floating) in power down Assertion. On P4 mode CPU clock output level selection Refer to Page 5 Table-1 Default value follow hardware trapping data on pin12 MULTSEL/PCI2 (Default 1) 6 MULTSEL X 5 SPCNT [5] 1 4 SPCNT [4] 0 3 SPCNT [3] 0 Spread Spectrum Programmable time, the resolution is 280ns. 2 SPCNT [2] 1 Default period is 11.8 S 1 SPCNT [1] 1 0 SPCNT [0] 1 7.12 Register 12: Control (Default: 3Ch) BIT NAME PWD 7 INV_CPU 0 6 TRI_EN 0 FUNCTION DESCRIPTION Invert the CPU phase 0: Default, 1: Inverse Tri-state all output if set 1 Spread spectrum implementation method 5 SPSP_TYPE 1 1: Pendulum type 0: Original 4 SPSP1 1 Spread Spectrum type select. 00: Down 1% 3 SPSP0 1 01: Down 0.5% 10: Center 0.5% 11: Center 0.25% 2 ASKEW [2] 1 1 ASKEW [1] 0 0 ASKEW [0] 0 CPU to AGP skew control, Skew resolution is 340pS Expand the skew direction is same as CPU_AGP_SKEW [2:0] setting - 12 - W83195BR-341 7.13 Register 13: Control (Default: 24h) BIT NAME PWD 7 6 5 INV_AGP INV_PCI CSKEW [2] 0 0 1 4 3 2 1 0 CSKEW [1] CSKEW [0] PSKEW [2] PSKEW [1] PSKEW [0] 0 0 1 0 0 FUNCTION DESCRIPTION Invert the AGP phase 0: Default, 1: Inverse Invert the PCI phase 0: Default, 1: Inverse CPU to CPUCS skew control, Skew resolution is 340 pS Expand the skew direction is same as CPU_CPUCS_SKEW [2:0] setting CPU to PCI skew control, Skew resolution is 340 pS Expand the skew direction is same as CPU_PCI_SKEW [2:0] setting 7.14 Register 14: Control (Default: 56h) BIT NAME PWD 7 6 5 CPUCS_S2 CPUCS_S1 USB48_S2 0 1 0 4 3 2 USB48_S1 AGP_S2 AGP_S1 1 0 1 1 0 SELP4_K7 SELSD_DD FUNCTION DESCRIPTION CPUCS_T/C slew rate control 11: Strong, 00: Weak, 10/01: Normal USB48/DOT48/USB24_48 slew rate control 11: Strong, 00: Weak, 10/01: Normal AGP2, 1, 0 slew rate control 11: Strong, 00: Weak, 10/01: Normal X Device active mode selection 1: P4 mode; 0: K7 mode Default value follow hardware trapping data on pin7 SELP4_K7/AGP1 (Default 1) X DRAM module selection 1: SDRAM mode; 0: DDR mode Default value follow hardware trapping data on pin11 SELSD_DD/PCI1 (Default 0) 7.15 Register 15: Slew Rate Control (Default: 55h) BIT NAME PWD 7 6 5 PCI_F_S2 PCI_F_S1 PCI_64_S2 1 0 4 3 2 1 0 PCI_64_S1 PCI_31_S2 PCI_31_S1 REF_S2 REF_S1 1 0 1 0 1 0 FUNCTION DESCRIPTION PCI_F slew rate control 11: Strong, 00: Weak, 10/01: Normal PCI6, 5,4 slew rate control 11: Strong, 00: Weak, 10/01: Normal PCI3, 2, 1 slew rate control 11: Strong, 00: Weak, 10/01: Normal REF0, REF1 slew rate control 11: Strong, 00: Weak, 10/01: Norma - 13 - Publication Release Date: April 13, 2005 Revision 1.1 W83195BR-341 7.16 Register 16: DRAM Buffer Control (1 = Enable, 0 = Disable) (Default: 7Fh) BIT NAME PWD FUNCTION DESCRIPTION 7 Reserve 0 Reserve 6 FBOUT_EN 1 FBOUT output control 5 DDR5 1 DDRT5, DDRC5 / SDRAM10, 11 output control 4 DDR4 1 DDRT4, DDRC4 / SDRAM8, 9 output control 3 DDR3 1 DDRT3, DDRC3 / SDRAM6, 7 output control 2 DDR2 1 DDRT2, DDRC2 / SDRAM4, 5 output control 1 DDR1 1 DDRT1, DDRC1 / SDRAM2, 3 output control 0 DDR0 1 DDRT0, DDRC0 / SDRAM0, 1 output control 7.17 Register 17: Slew Rate Control (Default: CFh) PWD Function Description Bit Name 7 FBOUT_S2 1 FBOUT slew rate control 6 FBOUT_S1 1 11: Strong, 00: Weak, 10/01: Normal 5 CPUOD_S2 0 CPUODT/C slew rate control 4 CPUOD_S1 0 11: Strong, 00: Weak, 10/01: Normal 3 DDR3_S2 1 DDR3, 4, 5/SDRAM6, 7, 8, 9, 10, 11 slew rate control 2 DDR3_S1 1 11: Strong, 00: Weak, 10/01: Normal 1 DDR0_S2 1 DDR0, 1, 2/SDRAM 0, 1, 2, 3, 4, 5 slew rate control 0 DDR0_S1 1 11: Strong, 00: Weak, 10/01: Normal 7.18 Register 18: M/N Time & Type Control (Default: 5Bh) BIT NAME PWD FUNCTION DESCRIPTION 7 N_Time<2> 0 6 N_Time<1> 1 5 N_Time<0> 0 4 M_Time<2> 1 3 M_Time<1> 1 2 M_Time<0> 0 1 N_TYPE 1 Reserved for Winbond internal use, don't modify it 0 M_TYPE 1 Reserved for Winbond internal use, don't modify it M/N mode N value change time control M/N mode M value change time control Note: This Byte only for Winbond internal and BOIS program use, the release version please reserved this byte. - 14 - W83195BR-341 M_Time<2:0> or N_Time<2:0> M_Divider or N_Divider timing counter 000 6.152 S 001 12.304 S 010 24.608 S 011 49.216 S 100 98.432 S 101 196.864 S 110 393.728 S 111 787.456 S 7.19 Register 19: Reserved 7.20 Register 20: Winbond Chip ID - (Ready Only) (Default: 61h) BIT NAME PWD FUNCTION DESCRIPTION 7 CHPI_ID [7] 0 Winbond Chip ID. W83195BR-341 (SA5861). 6 CHPI_ID [6] 1 Winbond Chip ID. 5 CHPI_ID [5] 1 Winbond Chip ID. 4 CHPI_ID [4] 0 Winbond Chip ID. 3 CHPI_ID [3] 0 Winbond Chip ID. 2 CHPI_ID [2] 0 Winbond Chip ID. 1 CHPI_ID [1] 0 Winbond Chip ID. 0 CHPI_ID [0] 1 Winbond Chip ID. 7.21 Register 21: Winbond Chip ID - (Ready Only) (Default: 50h) BIT NAME PWD FUNCTION DESCRIPTION 7 MAS_ID [1] 0 MASK definition for master body 6 MAS_ID [0] 1 *A****: 01, *B****: 10, *C****: 11, *D****:00 5 SUB_ID [1] 0 MASK definition for code body 4 SUB_ID [0] 1 *A****001: 01, 3 MAS_VER_ID [1] 0 MASK version definition for master body 2 MAS_VER_ID [0] 0 1 SUB_VER_ID [1] 0 MASK version definition for code body 0 SUB_VER_ID [0] 0 *A****001A: 00, *A****001B: 01 *A****001C: 10, *A****001D: 11 *A****002: 10, *A****003: 11, *A****004:00 *A****001AA: 00, *A****001AB: 01, *A****001AC: 10, *A****001AD: 11. - 15 - Publication Release Date: April 13, 2005 Revision 1.1 W83195BR-341 8. ACCESS INTERFACE The W83195BR-341 provides I2C Serial Bus for microprocessor to read/write internal registers. In the W83195BR-341 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C address is defined at 0xD2. Block Read and Block Write Protocol 8.1 Block Write Protocol 8.2 Block Read Protocol ## In block mode, the command code must filled 00H 8.3 Byte Write Protocol 8.4 Byte Read Protocol - 16 - W83195BR-341 9. SPECIFICATIONS 9.1 Absolute Maximum Ratings Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD). PARAMETER RATING Absolute 3.3V Core Supply Voltage Absolute 3.3V I/O Supple Voltage Operating 3.3V Core Supply Voltage Operating 3.3V I/O Supple Voltage Storage Temperature -0.5V to +4.6V -0.5 V to +4.6 V 3.135V to 3.465V 3.135V to 3.465V Ambient Temperature -55C to +125C -65C to +150C Operating Temperature 0C to +70C 2000V Input ESD Protection (Human body model) 9.2 General Operating Characteristics VDD = VDDAGP = VDDC = VDDR = VDDPCI = VDD48 = 3.3V 5 %, TA = 0C to +70C, Cl = 10 pF PARAMETER Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Operating Supply Current Input pin capacitance Output pin capacitance Input pin inductance SYM. VIL VIH VOL VOH MIN. MAX. UNITS 0.8 Vdc Vdc Vdc Vdc 2.0 0.4 2.4 Idd 350 mA Cin Cout Lin 5 6 7 pF pF nH TEST CONDITIONS All outputs using 3.3V power All outputs using 3.3V power CPU = 100 to 200 MHz PCI = 33.3 MHz with load 9.3 Skew Group Timing Clock VDD = VDDAGP = VDDC = VDDR = VDDPCI = VDD48 = 3.3V 5 %, TA = 0C to +70C, Cl = 10 pF PARAMETER AGP to PCI Skew CPU to CPU Skew AGP to AGP Skew PCI to PCI Skew 48MHz to 48MHz Skew REF to REF Skew MIN. TYP. MAX. UNITS 1.5 2.6 3.5 200 250 500 1000 500 nS pS pS pS pS pS - 17 - TEST CONDITIONS Measured at 1.5V Crossing point Measured at 1.5V Measured at 1.5V Measured at 1.5V Measured at 1.5V Publication Release Date: April 13, 2005 Revision 1.1 W83195BR-341 9.4 CPU 0.7V Electrical Characteristics VDDCPU = 3.3V 5 %, TA = 0C to +70C, Test load Rs = 33, Rp = 49.9 Cl = 10pF, Vr = 475, IREF = 2.32 mA, Ioh = 6*IREF PARAMETER MIN MAX UNITS Rise Time 175 700 pS 100 to 200 MHz Fall Time 175 700 pS 100 to 200 MHz Absolute Crossing Point Voltages 250 550 mV 100 to 200 MHz 150 pS 100 to 200 MHz 55 % 100 to 200 MHz Cycle to Cycle jitter Duty Cycle 45 TEST CONDITIONS 9.5 CPU 1.0V Electrical Characteristics VDDCPU = 3.3V 5 %, TA = 0C to +70C, Test load Rs = 33, Rp = 49.9 Cl = 10pF, Vr = 221, IREF= 5mA, Ioh = 4*IREF PARAMETER MIN. MAX. UNITS Rise Time 175 700 pS 100 to 200 MHz Fall Time 175 700 pS 100 to 200 MHz Absolute Crossing Point Voltages 510 760 mV 100 to 200 MHz 150 pS 100 to 200 MHz 55 % 100 to 200 MHz Cycle to Cycle Jitter Duty Cycle 45 TEST CONDITIONS 9.6 AGP Electrical Characteristics VDDAGP= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF, PARAMETER MIN. MAX. UNITS Rise Time 500 2000 pS Measure from 0.4V to 2.4V Fall Time 500 2000 pS Measure from 2.4V to 0.4V 250 pS Measure 1.5V point 55 % Cycle to Cycle Jitter Duty Cycle 45 Pull-Up Current Min. -33 Pull-Up Current Max. Pull-Down Current Min. Pull-Down Current Max. -33 30 38 - 18 - TEST CONDITIONS mA Vout = 1.0V mA Vout = 3.135V mA Vout = 1.95V mA Vout = 0.4V W83195BR-341 9.7 PCI Electrical Characteristics VDDPCI= 3.3V 5 %, TA = 0C to +70C, Test load, Cl = 10 pF, PARAMETER MIN. MAX. UNITS Rise Time 500 2000 pS Measure from 0.4V to 2.4V Fall Time 500 2000 pS Measure from 2.4V to 0.4V 250 pS Measure 1.5V point 55 % Cycle to Cycle Jitter Duty Cycle 45 Pull-Up Current Min. -33 Pull-Up Current Max. Pull-Down Current Min. -33 30 Pull-Down Current Max. 38 TEST CONDITIONS mA Vout = 1.0V mA Vout = 3.135V mA Vout = 1.95V mA Vout = 0.4V 9.8 24M, 48M Electrical Characteristics VDD48= 3.3V 5 %, TA = 0C to +70C, Test load, Cl = 10 pF PARAMETER MIN. MAX. UNITS Rise Time 500 2000 pS Measure from 0.4V to 2.4V Fall Time 500 2000 pS Measure from 2.4V to 0.4V 500 pS Measure 1.5V point 55 % Long Term Jitter Duty Cycle 45 Pull-Up Current Min. -33 Pull-Up Current Max. Pull-Down Current Min. -33 30 Pull-Down Current Max. 38 TEST CONDITIONS mA Vout = 1.0V mA Vout = 3.135V mA Vout = 1.95V mA Vout = 0.4V 9.9 REF Electrical Characteristics VDDR= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF PARAMETER MIN. MAX. UNITS Rise Time 1000 4000 pS Measure from 0.4V to 2.4V Fall Time 1000 4000 pS Measure from 2.4V to 0.4V 1000 pS Measure 1.5V point 55 % Cycle to Cycle Jitter Duty Cycle 45 Pull-Up Current Min. -33 Pull-Up Current Max. Pull-Down Current Min. Pull-Down Current Max. -33 30 38 TEST CONDITIONS mA Vout = 1.0V mA Vout = 3.135V mA Vout = 1.95V mA Vout = 0.4V - 19 - Publication Release Date: April 13, 2005 Revision 1.1 W83195BR-341 10. ORDERING INFORMATION PART NUMBER PACKAGE TYPE PRODUCTION FLOW W83195BR-341 56 PIN SSOP Commercial, 0C to +70C 11. HOW TO READ THE TOP MARKING W83195BR-341 28051234 342GAASA 1st line: Winbond logo and the type number: W83195BR-341 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 342 G A A SA 342: packages made in '2003, week 42 G: assembly house ID; O means OSE, G means GR A: Internal use code A: IC revision SA: mask version All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 20 - W83195BR-341 12. PACKAGE DRAWING AND DIMENSIONS .035 .045 SYMBOL .045 .055 0.40/0.50 DIA E END VIEW HE TOP VIEW SEE DETAIL "A" c D A2 A A1 e b SIDE VIEW c 0.13 D HE 18.2 18.42 18.54 910.16 10.31 10.41 E 7.42 0.51 7.52 0.64 0.61 0.81 1.40 e L L1 Y SEATING PLANE A A1 A2 b DIMENSION IN MM PARTING LINE Y c DIMENSION IN INCH MIN. NOM MAX. MIN. NOM 0.095 0.101 2.41 2.57 2.79 0.41 0.008 0.012 0.20 0.30 0.088 0.090 2.34 2.24 2.29 0.25 0.20 0.34 0.008 0.010 0 0.25 7.59 0.76 1.02 0.08 8 MAX. 0.110 0.016 0.092 0.0135 0.005 0.010 0.720 0.400 0.292 0.020 0.024 0.725 0.730 0.406 0.410 0.296 0.299 0.025 0.030 0.032 0.040 0.055 0.003 0 8 L L1 DETAIL"A" - 21 - Publication Release Date: April 13, 2005 Revision 1.1 W83195BR-341 13. REVISION HISTORY VERSION DATE PAGE DESCRIPTION All of the versions before 0.50 are for internal use. 0.5 07/07/03 n.a. First published preliminary version. 0.6 26/8/03 n.a. Some description red text part 0.7 12/18/03 19 Correction IC version, 1.0 05/04/04 1.1 4/13/2005 Update on web 22 Add disclaimer Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd. No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd. 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 22 -