DS030 (v1.8) October 10, 2001 www.xilinx.com 1
Product Specification 1-800-255-7778
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Introduction
The Spartan™ family of PROMs provides an easy-to-use,
cost -effective method for stor ing Spar tan device co nfigura-
tion bitstreams.
When the Spartan device is in Master Serial mode, it gener-
ates a configuration clock that driv es the Spartan PROM. A
short acce ss t ime af ter th e r ising clo ck edge, data appear s
on the PROM D ATA output pin that is connected to the Spar-
tan device DIN pin. The Spartan device generates the
appropr iate numb er of c lock pulses to com plete th e confi g-
uration. Once configured, it disables the PROM. When a
Spartan device is in Slave Serial m ode, the PROM and th e
Spartan device must both be clocked by an incoming signal.
For device programming, either the Xilinx Alliance or the
F oundation series dev elopment systems compiles the Spar-
tan device desig n file into a standard HEX for mat which is
then transferred to most commercial PROM programmers.
Spartan PROM Features
•Configuration one-time programmable (OTP) read-only
memory designed to store configuration bitstreams for
Spartan, Spartan-XL, and Spartan-II FPGA devices
•Simple interface to the Spartan device requires only
one user I/O pin
•Programmable reset polarity (active High or active
Low)
•Low-power CMOS floating gate process
•Available in 5V and 3.3V versions
•Availabl e in compact plastic 8-pin DIP, 8-pin VOIC, or
20-pin SOIC packages.
•Programming support by leading programmer
manufacturers.
•Design support using the Xilinx Alliance and
Foundation series software packages.
•Guaranteed 20 year life data retention
0Spartan Family of One-Time
Programmable Configuration
PROMs (XC17S00)
DS030 (v1.8 ) October 10, 2001 05Product Specification
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Spartan FPGA Configuration Bits Compatible Spartan PROM
XCS05 53,984 XC17S05
XCS05XL 54,544 XC17S05XL
XCS10 95,008 XC17S10
XCS10XL 95,752 XC17S10XL
XCS20 178,144 XC17S20
XCS20XL 179,160 XC17S20XL
XCS30 247,968 XC17S30
XCS30XL 249,168 XC17S30XL
XCS40 329,312 XC17S40
XCS40XL 330,696 XC17S40XL
XC2S50 559,232 XC17S50XL
XC2S100 781,248 XC17S100XL
XC2S150 1,040,128 XC17S150XL
Spartan Family of One-Time Programmable Configuration PROMs (XC17S00)
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1-800-255-7778 Product Specification
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Pin Description
Controlli ng PROMs
Connecting the Spartan device with the PROM:
•The DATA output of the PROM drives the DIN input of
the lead Spartan device.
•The Master Spartan device CCLK output drives the
CLK input of the PROM.
•The RESET/OE input of the PROM is driven by the
INIT output of the Spartan device. This connection
assures that the PROM address counter is reset before
the start of any (re)configuration, even when a
reconfiguration is initiated by a VCC glitch. Other
methods—such as driving RESET/OE from LDC or
system reset—assume that the PROM internal
power-on-reset is always in step with the FPGAs
internal power-on-reset, which may not be a safe
assumption.
•The CE input of the PROM is driven by the DONE
output of the Spartan device, provided that DONE is
not permanently grounded. Otherwise, LDC can be
used to drive CE, but must then be unconditionally
High during user operation. CE can also be
permanently tied Low, but this keeps the DATA output
active and causes an unnecessary supply current of
10 mA maximum.
FPGA Master Serial Mode Summary
The I/O and logic functi ons of the Configurable Logic B lock
(CLB) and their associated interconnections are established
by a configuration program. The program is loaded either
automatically upon power up, or on command, depending
on the state of the Spartan device MODE pin. In Master
Serial mode, the Spartan device automatically loads the
configuratio n program from an exter nal me mory. The S par-
tan PROM has been designed for compatibility with the
Master Serial mode.
Upon power-up or reconfiguration, the Spartan device
enters the Master Seri al mode when the MODE pi n is Low.
Data is read from the PROM sequentially on a single data
line. Synchronization is provided by the rising edge of the
temporary signal CCLK, which is generated during configu-
ration.
Table 1: Spartan PROM Pinouts
Pin Name
8-pin
PDIP and
VOIC
20-pin
SOIC Pin Description
D ATA 1 1 Data output, High-Z state when either CE or OE are inactiv e. During programming,
the DATA pin is I/O. Note that OE can be programmed to be either active High or
active Low.
CLK 2 3 Each rising edge on the CLK input increments the internal address counter , if both
CE and OE are active.
RESET/OE
(OE/RESET)3 8 When High, this input holds the address counter reset and puts the D ATA output in
a high-impedance state. The polarity of this input pin is programmable as either
RESET/OE or OE/RESET. To avoid confusion, this document describes the pin as
RESET/OE, although the opposite polarity is possible on all devices. When RESET
is active, the address counter is held at zero, and the DATA output is in a
high-impedance state. The polarity of this input is programmable. The default is
active High RESET, but the pref erred option is active Low RESET, because it can
be driven by the FPGAs INIT pin.
The polarity of this pin is controlled in the programmer interface. This input pin is
easily inverted using the Xilinx HW-130 programmer software. Third-party
programmers have different methods to invert this pin.
CE 4 10 When High, this pin disables the internal address counter, puts the D ATA output in
a high-impedance state, and forces the device into low-ICC standby mode.
GND 5 11 GND is the ground connection.
VCC 7, 8 18, 20 The VCC pins are to be connected to the positive voltage supply.
Notes:
1. Pins not listed in the table are reserved and must not be externally connected.
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Product Specification 1-800-255-7778
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Master Serial mode provides a simple configuration inter-
face (Figure 1). Only a serial data line and two control lines
are required to configure the Spartan device. Data from the
PROM is read sequentially, accessed via the internal
address and bit counters which are incremented on every
valid rising edge of CCLK.
If the user-programmable, dual-function DIN pin on the
Spartan device is used only for configuration, it must still be
held at a defined level dur ing nor mal operation. The Spar-
tan family takes care of this automatically with an on-chip
default pull-up resistor.
Pr ogrammi ng the FPGA With Counters
Unchanged Upon Completion
When multiple-configurations for a single Spartan device
are stored in a PROM, the OE pin should be tied Low. Upon
power-up, the inter n al add ress co unters ar e rese t and con-
figuration begins with the first program stored in memory.
Since the OE pin is held Low, the addres s counter s are left
unchanged after configuration is complete. Therefore, to
reprogram the FPGA with anothe r program, the DONE line
is pulled Low and configuration begins at the last value of
the address counters.
This metho d fails if a user appli es RESE T dur ing t he Spar-
tan device configuration process. The Spartan device
aborts the con figuration a nd then r estarts a n ew configura-
tion, as in tended, but the PROM doe s not re set its addre ss
counter , since it never saw a High lev el on its OE input. The
new configuration, therefore, reads the remaining data in
the PROM and interprets it as preamble, length count etc.
Since the Spartan device is the Master , it issues the neces-
sary number of CCLK pulses, up to 16 million (224) and
DONE goes High. However, the Spar tan device configura-
tion will be completely wrong, with potential contentions
inside the Spartan device and on its output pins. This
method must, therefore, never be used when there is any
chance of external reset during configuration.
Figure 1: Master Serial Mode. The one-time-programmable Spartan PROM supports automatic loading of configuration programs.
An early DONE inhibits the PROM data output one CCLK cycle before the Spartan FPGA I/Os become active.
D
IN
CCLK
INIT
DONE
Spartan
PROM
DATA
3.3V
CLK
CE
Spartan
Master Serial
(Low Resets the Address Pointer)
DS030_01_101001
CCLK
(Output)
D
IN
D
OUT
(Output)
OE/RESET
MODE
4.7K
V
CC
V
CC
V
CC
Spartan Family of One-Time Programmable Configuration PROMs (XC17S00)
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Standby Mode
The PROM enters a low-power standby mode whenev er CE
is asser ted High. The output remains in a high-impedance
state regardless of the state of the OE input.
Programming the Spartan Family
PROMs
The devices can be programmed on programmers supplied
by Xilinx or qualified third-party vendors. The user must
ensure that the appropriate programming algorithm and the
latest version of the programmer software are used. The
wrong choice can permanently damage the device.
Important:
Always tie the two VCC pins together in your application.
Figure 2: Simplified Block Diagram (does not show programming circuit)
Table 2: Truth Table for XC17S00 Control Inputs
Control Inputs
Internal Address(2)
Outputs
RESET(1) CE DATA ICC
Inactive Low If address < TC: increment
If address > TC: don’t change Active
High-Z Active
Reduced
Active Low Held reset High-Z Active
Inactive High Not changing High-Z Standby
Active High Held reset High-Z Standby
Notes:
1. The XC17S00 RESET input has programmable polarity
2. TC = Terminal Count = highest address value. TC + 1 = address 0.
EPROM
Cell
Matrix
Address Counter
CE
DATA
OE
Output
CLK
VCC GND
DS030_02_011300
TC
OE
RESET/
OE/
RESET
or
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Product Specification 1-800-255-7778
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XC17S05, XC17S10, XC17S20, XC17S30, XC17S40
Absolute Maxim um Ratings(1)
Operating Conditi ons (1)
DC Characteristics Over Operating Condition
Symbol Description Value Units
VCC Su pply voltage relative to GN D –0.5 to +7.0 V
VIN Input voltage relative to GND –0.5 to VCC +0.5 V
VTS Voltage applied to High-Z output –0.5 to VCC +0.5 V
TSTG Storage temperature (ambien t) –65 to +150
p
C
TSOL Maximum soldering temperature (10s @ 1/16 in.) +260
p
C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional opera tion of the device at the se or an y oth er conditio ns bey o nd tho se li sted und er Op erating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Symbol Description Conditions Min Max Units
VCC Commercial Supply voltage relative to GND (TA = 0
p
C to +70
p
C) 4.75 5.25 V
Industrial Supply voltage relative to GND (TA = –40
p
C to +85
p
C) 4.50 5.50 V
Notes:
1. During normal read operation both VCC pins must be connected together.
Symbol Description Min Max Units
VIH High-level input voltage 2.0 VCC V
VIL Low-level input voltage 0 0.8 V
VOH High-level output voltage (IOH = –4 mA) Commerc ia l 3.86 - V
VOL Low-level output voltage (IOL = +4 mA) - 0.32 V
VOH High-level output voltage (IOH = –4 mA) Industria l 3.76 - V
VOL Low-level output voltage (IOL = +4 mA) - 0.37 V
ICCA Supply current, active mode (at maximum frequency) - 10 mA
ICCS Supply current, standby mode XC17S05, XC17S10,
XC17S20, XC17S30 -50
N
A
XC17S40 - 100
N
A
ILInput or output leakage current –10 10
N
A
CIN Input Capacitance (VIN = GND, f = 1.0 MHz) - 10 pF
COUT Output Capacitance (VIN = GND, f = 1.0 MHz) - 10 pF
Spartan Family of One-Time Programmable Configuration PROMs (XC17S00)
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XC17S05XL, XC17S10XL, XC17S20XL, XC17S30XL, XC17S40XL, XC17S50XL,
XC17S100XL, XC17S150XL
Absolute Maxim um Ratings(1)
Operating Conditi ons (1)
DC Characteristics Over Operating Condition
Symbol Description Value Units
VCC Supply voltage relative to GND –0.5 to +4.0 V
VIN Input voltage with respect to GND –0.5 to VCC +0.5 V
VTS Voltage applied to High-Z output –0.5 to VCC +0.5 V
TSTG Storage temperature (ambient) –65 to +150
p
C
TSOL Maximum soldering temperature (10s @ 1/16 in.) +260
p
C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and function al opera tion of the device at these or any other conditions bey on d thos e li st ed under Oper a tin g C ond itions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Symbol Description Min Max Units
VCC Commercial Supply voltage relative to GND (TA = 0
p
C to +70
p
C) 3.0 3.6 V
Industrial Supply voltage relative to GND (TA = –40
p
C to +85
p
C) 3.0 3.6 V
Notes:
1. During normal read operation both VCC pins must be connected together.
Symbol Description Min Max Units
VIH High-level input voltage 2.0 VCC V
VIL Low-level input voltage 0 0 .8 V
VOH High-level output voltage (IOH = –3 mA) 2.4 - V
VOL Low-level output voltage (IOL = +3 mA) - 0.4 V
ICCA Supply current, active mode (at maximum frequency) - 5 mA
ICCS Supply current, standby mode - 50
N
A
ILInput or output leakage current –10 10
N
A
CIN Input Capacitance (VIN = GND, f = 1.0 MHz) - 10 pF
COUT Output Capacitance (VIN = GND, f = 1.0 MHz) - 10 pF
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Product Specification 1-800-255-7778
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AC Characteristics Over Operating Condition(1)
RESET/OE
CE
CLK
DATA
TCE
TOE
TLC
TSCE TSCE THCE
THOE
TCAC TOH TDF
TOH
THC
DS0306_03_011300
TCYC
Symbol Description Min Max Units
TOE RESET/OE to Data Delay - 45 ns
TCE CE to Data Delay - 60 ns
TCAC CLK to Data Delay - 80 ns
TOH Data Hold From CE, RESET/OE, or CLK(2) 0-ns
TDF CE or RESE T/OE to Data Float Delay(2,3) -50ns
TCYC Clock Periods 100 - ns
TLC CLK Low Time(2) 50 - ns
THC CLK High Time(2) 50 - ns
TSCE CE Setup Time to CLK (to guarantee proper counting) 25 - ns
THCE CE Hold Time to CLK (to guarantee proper counting) 0 - ns
THOE RESET/OE Hold Time (guarantees counters are reset) 25 - ns
Notes:
1. AC test load = 50 pF
2. Guaranteed by design, not tested.
3. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
Spartan Family of One-Time Programmable Configuration PROMs (XC17S00)
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Ordering Information
Spartan 5V Valid Ordering Combinations (XC17S00)
Spartan 3.3V Valid Ordering Combinations (XC17S00XL)
Marking Information
Due to the small size of the PROM package, the complete ordering part number cannot be marked on the package. The XC
XC17S05PD8C XC17S10PD8C XC17S20PD8C XC17S30PD8C XC17S40PD8C
XC17S05VO8C XC17S10VO8C XC17S20VO8C XC17S30VO8C XC17S40SO20C
XC17S05PD8I XC17S10PD8I XC17S20PD8I XC17S30PD8I XC17S40PD8I
XC17S05VO8I XC17S10VO8I XC17S20VO8I XC17S30VO8I XC17S40SO20I
XC17S05XLPD8C XC17S100XLPD8C XC17S20XLPD8C XC17S40XLPD8C
XC17S05XLVO8C XC17S100XLSO20C XC17S20XLVO8C XC17S40XLSO20C
XC17S05XLPD8I XC17S100XLPD8I XC17S20XLPD8I XC17S40XLPD8I
XC17S05XLVO8I XC17S100XLSO20I XC17S20XLVO8I XC17S40XLSO20I
XC17S10XLPD8C XC17S150XLPD8C XC17S30XLPD8C XC17S50XLPD8C
XC17S10XLVO8C XC17S150XLSO20C XC17S30XLVO8C XC17S50XLSO20C
XC17S10XLPD8I XC17S150XLPD8I XC17S30XLPD8I XC17S50XLPD8I
XC17S10XLVO8I XC17S150XLSO20I XC17S30XLVO8I XC17S50XLSO20I
XC17S20XL VO8 C
Operating Range/Processing
C=Commercial (T
A = 0
p
C to +70
p
C)
I = Industri al (TA = –40
p
C to +85
p
C)
Package Type
PD8 = 8-pin Plastic DIP
VO8 = 8-pin Plastic Sm all- Ou tli ne Thin Package
SO20 = 20-pin Plastic Small-Outline Package
Device Number
XC17S05
XC17S05XL
XC17S10
XC17S10XL
XC17S20
XC17S20XL
XC17S30
XC17S30XL
XC17S40
XC17S40XL
XC17S50XL
XC17S100XL
XC17S150XL
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Product Specification 1-800-255-7778
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prefix is deleted and the package code is simplified. De vice marking is as follows.
Note:
When marking the device number on the XL parts, an L is used in place of an XL.
Revision History
The following ta ble shows the revision history for this docume nt.
Date Revision Revision
07/14/98 1.1 Cosmetic edits for pages 1, 2, and 3.
09/08/98 1.2 Clarified the SPARTAN FPGA and PROM interface by removing ref erences to CEO pin. Removed
the ESD notation in Absolute Maximum table since it is now included in Xilinx’s Reliability Monitor
Report.
01/20/00 1.3 Added additional Spartan-XL parts, changed SPROM to PROM.
02/18/00 1.4 Changed device ordering numbers, added 4.7K resistor to OE/RESET in Figure 1.
04/04/00 1.5 Added XC17S200XL PROM for Spartan XC2S200.
08/06/00 1.6 Updated format.
04/07/01 1.7 Added to features: “Guaranteed 20 year life data retention.”
10/10/01 1.8 Added a note to Table 1. Changed VPP to VCC on Figure 1.
17S20L V C
Operating Range/Processing
C=Commercial (T
A = 0
p
C to +70
p
C)
I = Industri al (TA = –40
p
C to +85
p
C)
Package Mark
P = 8-pin Plastic DIP
V = 8-pin Plasti c Sm all - Ou tline Th in Package
S = 20-pin Plastic Small-Outline Package
Device Number
17S05
17S05L
17S10
17S10L
17S20
17S20L
17S30
17S30L
17S40
17S40L
17S50L
17S100L
17S150L
