AT73C500-JC - Atmel Corporation

Features

•Fulfills IEC 1036, Class 1 Accuracy Requirements

•Fulfills IEC 687, Class 0.5 and Class 0.2 Accuracy, with External Temperature

Compensated Voltage Reference

•Fulfills IEC 1268, Requirements for Reactive Power

•Simultaneous Active, Reactive and Apparent Power and Energy Measurement

•Power Factor, Frequency, Voltage and Current Measurement

•Single- and Poly-phase Operation

•Three Basic Operating Modes: Stand-alone Mode, Microprocessor Mode and Multi-

Channel Mode

•Flexible Interfacing, 8-bit Microprocessor Interface, 8-bit Status Output and Eight

Impulse Outputs

•Calibration of Gain and Phase Error

•Compensation of the Non-linearity of Low Power Measurement

•Adjustable Starting Current and Meter Constant

•Measurement Bandwidth of 1000 Hz

•Tamper-proof Design

•Single +5V Supply

Description

A two chip so lu tio n , co nsis tin g of A T7 3C50 0 and AT 73 C501 (or AT 7 3C50 2) , offer s all

main features required for the measurement and calculation of various power and

energy quantities in static Watt-hour meters. The devices operate according to

IEC1036, class 1, specification. IEC 687, class 0.5 and 0.2 requirements are fulfilled

when used with external temperature compensated voltage reference.

The AT73C501 contains six, high-performance, Sigma-Delta analog-to-digital convert-

ers (A DC). T he A T73C50 0 is an efficie nt di gital sign al p roces sor ( DSP) that supp orts

interfacing both with the AT73C501 and with an external microprocessor. The

AT73C500 can also be used with the differential input ADC, AT73C502.

With this chipset, only a minimum of discrete components is required to develop prod-

ucts ranging from simple domestic Watt-hour meters to sophisticated industrial

meters. The c hipset can be used in single-pha se as well as in poly- phase systems .

The AT73C500 is easy to configure. By changing the mode of the AT73C500, the

device can be operated in a stand-alone environment or be used with a separate con-

trol processor. It is also possible to configure the circuit to perform the functions of

three independent single phase Wh meters.

The chips support calibration of gain and phase error. All calibrations are done in the

digital domain and no trimming components are needed. T he calibration coefficients

are either stored in an EEPROM memory or supplied by an external microprocessor.

(continued)

Chipset

Solution for

Watt-hour

Meters

AT73C500 with

AT73C501 or

AT73C502

Rev. 1035B–09/99

AT73C500

Figure 1. Block diagram of the AT73C500 chipset in stand-alone configuration

The AT73C 500 is progra mmed to m easur e act ive, rea ctive

and apparent phase powers. Phase factors, phase volt-

ages, phase currents and line frequency are also mea-

sured, simultaneously. Based on the individual phase

powers, total active power is determined.

The po wer value s are c alculate d over one- line freq uency

cycle. The negative and positive results are accumulated in

different registers, which allows for separate billing of

imported an d exported active energy. Also, the reactive

results are sorted depending on whether capacitive or

inducti ve loa d is appl ie d.

Eight pulse outputs are provided. Each billing quantity

(+Wh, -Wh, +VArh, -Varh) is supplied with its own meter

constant output, as well as a display counter output. In

multi-c hannel mo de, AT73C500 performs th e function s of

three independent single phase Wh meters and three

impulse outputs are available, one for each meter element.

All measu remen t informatio n is availab le on an 8-bit mi cro-

processor bus. The results are o utput in six packages, 16

bytes each. Mode and status information of the meter is

also transferred with each data block.

Figure 2. Block diagram of the AT73C500 chipset in microprocessor configuration

AT73C500

DEDICATED DSP

FOR ENERGY

METERING

STROBE

RD/WR

ADDR1

ADDR0

IRQ0

IRQ1

SIN

SCLK

SOUT1

SOUT0

DATA BUS

STATUS BUS

XRES

VCC

GND

DGND

BRDY

TAMP

STUP

FAIL

DATRDY

INI

AT93C46

EEPROM

128*8 bit

AT73C501

SIX SINGLE-ENDED,

INDEPENDENT

SIGMA-DELTA

CONVERTERS

AIN2

AIN4

AIN6

AIN1

AIN3

AIN5

XI XO MODE

VSA

VSSA

VDA

VDDA

VCC

AGND

GND

VGND

VREF

BGD

RESET

PFAIL

ACK

DATA

CLKR

CLK

L1 L2 L3

-VArh

+VArh

-Wh

+Wh

-Wh

+VArh

-VArh

MODE2

MODE1

MODE0

RESET

EXTERNAL CONNECTOR

CLK

AT73500

DEDICATED DSP

FOR ENERGY

METERING

STROBE

RD/WR

ADDR1

ADDR0

IRQ0

IRQ1

SIN

SCLK

SOUT1

SOUT0

DATA BUS

STATUS BUS

XRES

VCC

BRDY

AT73501

SIX SINGLE-ENDED,

INDEPENDENT

SIGMA-DELTA

CONVERTERS

AIN2

AIN4

AIN6

AIN1

AIN3

AIN5

XI XO MODE

VSA

VSSA

VDA

VDDA

VCC

AGND

VREF

BGD

RESET

PFAIL

ACK

DATA

CLKR

CLK

L1 L2 L3

MODE2

MODE1

MODE0

RESET

B14

B13

B12

DATRDY

AT90Sxx

MICROCONTROLLER

MODEM

LCD

EEPROM

GND

VGND GND

DGND

AT73C500

Pin Description

AT73C501 Single-ended ADC

Figure 3. PLCC-28 package pin layout

Power

Supply

Pins Pin I/O Description

VDDA 13 PWR Analog Sup ply, Positive, +5V

VSSA 12 PWR Analog Supply, Negative, 0V

VDA 21 PWR Analog Sup ply, Positive, +5V

VSA 20 PWR Analog Supply, Negative, 0V

AGND 9 PWR Analog Ground Reference

Input

VREF 11 PWR Reference Voltage

Output/Input

VCC 7 PWR Digital Supply, Positive, +5V

VGND 23 PWR Digital Supply, Negative, 0V

Crystal Osc

Signals Pin I/O Description

XI 3 I Crystal Oscillator Input

XO 4 O Crystal Oscillator Output

RESET

DAT

FSRACKCLKRCLKXIXO

26272812

N/C

VGND

AIN5

VSS

VDD

AIN2 AIN4 AIN6 AIN1 AIN3

18171615141312

BGD

VCC

PFAI

AGN

VCIN

VREF

Analog

Signals Pin I/O Description

AIN1 17 I Current, Channel 1

AIN2 14 I Voltage, Channel 1

AIN3 18 I Current, Channel 2

AIN4 15 I Voltage, Channel 2

AIN5 19 I Current, Channel 3

AIN6 16 I Voltage, Channel 3

VCIN 10 I Input to Voltage Monitoring

Block

Digital

Control

Signals Pin I/O Description

BGD 5 I By-pass Control

for Reference Voltage

CS 6 I Chip Select Input

PD 22 I Power Down Control

for A/D Modulators

N/C 24 I Connect to VGND

RESET 25 I Reset Inp ut, Acti ve High

Status

Flags Pin I/O Description

PFAIL 8 O Output of Voltage Monitoring

Block

Output Bus

Signals Pin I/O Description

CLK 2 O Master Clock Output

CLKR 1 O Serial Bus Clock Output

DATA 26 O Serial Data Output

FSR 27 O Output Sample Frame

Signal

ACK 28 O Data Re ady Ac knowledge

Output

AT73C500

AT73C 50 2 Di ff erential-Ended ADC

Figure 4. QFP-44 package pin layout

Power

Supply

Pins Pin I/O Description

VDA 12, 13,

29, 30 PWR Analog Supply, Positive, +5V

VSA 10, 11,

27, 28 PWR Analog Supply, Negative, 0V

AGND 6 PWR Analog Ground Reference

Input

VREF 8 PWR Reference Voltage

Output/Input

VCC 3, 4 PWR Digital Supply, Positive, +5V

VGND 32 PWR Digital Supply, Negative, 0V

Crystal

Osc

Signals Pin I/O Description

XI 43 I Crystal Osc illator Input

XO 44 O Crystal Osci llato r Output

Analog

Signals Pin I/O Description

AIN2P 14 I Voltage, Channel 1, Positiv e

AIN2N 15 I Voltage, Channel 1, Negativ e

AIN4P 16 I Voltage, Channel 2, Positiv e

AIN4N 17 I Voltage, Channel 2, Negativ e

BGD N/C

CLKRCLK N/CN/CN/C

XI RESETXO

322

133

4344 42 41 40 39 38 37 36 35 34

DATAACK FSR

VGND

31 PD

30 VDA

29 VDA

28 VSA

27 VSA

26 SINGLE

25 AIN5N

24 AIN5P

23 AIN3N

1312 14 15 16 17 18 19 20 21 22

VCC 3

VCC 4

PFAIL 5

AGND 6

VCIN 7

VREF 8

N/C 9

VSA 10

VSA 11

AIN1NAIN6NAIN4NAIN2NVDA AIN3PAIN1PAIN6PAIN4PAIN2PVDA

AIN6P 18 I Voltage, Channel 3, Positive

AIN6N 19 I Voltage, Channel 3, Negative

AIN1P 20 I Current, Channel 1, Positive

AIN1N 21 I Current, Channel 1, Nega tive

AIN3P 22 I Current, Channel 2, Positive

AIN3N 23 I Current, Channel 2, Nega tive

AIN5P 24 I Current, Channel 3, Positive

AIN5N 25 I Current, Channel 3, Nega tive

VCIN 7 I Input to Voltage Monit oring

Block

N/C 9 I Must be left floating

Digital

Control

Signals Pin I/O Description

BGD 1 I By-pass Control for

Reference Voltage

CS 2 I Chip Select Input

PD 31 I Power Down Control for A/D

Modulators

N/C 33 I Connect to VGND

RESET 34 I Reset Input, Active High

SINGLE 26 I Single / Differential selector.

· Low: Differential

· High or n/c: Single-ended

Status

Flags Pin I/O Description

PFAIL 5 O Output of Voltage Monit oring

Block

Output

Bus

Signals Pin I/O Description

CLK 41 O Master Clock Output

CLKR 39 O Serial Bus Clock Output

DATA 35 O Serial Data Output

FSR 36 O Output Sample Frame

Signal

ACK 37 O Data Ready Acknowledge

Output

Analog

Signals Pin I/O Description

AT73C500

AT73C500 DSP

Figure 5. PLCC-44 package pin layout

Power

Supply

Pins Pin I/O Description

VCC 35, 42 PWR Digital Supply, Positive, +5V

GND

1, 2, 6, 7,

1 1, 12,16,

20, 27, 30,

PWR Digital Supply, Negative, 0V

Digital

Inputs Pin I/O Description

CLK 44 I Clock Input

XRES 38 I Reset Input, active low

IRQ0 3 I Interrupt Input, usually

connec ted to PFAIL output

of AT73C501

IRQ1 31 I Interrupt I nput, c onnected to

ACK Output of AT73C501

Status/

Mode

Bus Pin I/O Description

B15 17 I/O Status/Mode Bus, Bit7

B14 15 I/O Status/Mode Bus, Bit6

B13 14 I/O Status/Mode Bus, Bit5

B12 13 I/O Status/Mode Bus, Bit4

B11 29 I/O Status/Mode Bus, Bit3

B10 28 I/O Status/Mode Bus, Bit2

B9 26 I/O Status/Mode Bus, Bit1

B8 25 I/O Status/Mode Bus, Bit0

GND ADDR0

GND

739

SOUT1

SOUT0

IRQ0 /

PFAIL

GND

CLK

STROBE

VCC

ADDR1

BRDY

XRES

VCC

RD/WR

SIN

GND

IRQ1 / ACK

SCLK

B11

GND

B0 8

B1 9

B2 10

GND 11

GND 12

B12 13

B13 14

B14 15

GND 16

B15 17

GND

N/C

GND

B10

Microprocessor

Bus Pin I/O Description

B7 23 I/O µP Bus, Bit7

B6 22 I/O µP Bus, Bit6

B5 21 I/O µP Bus, Bit5

B4 19 I/O µP Bus, Bit4

B3 18 I/O µP Bus, Bit3

B2 10 I/O µP Bus, Bit2

B1 9 I/O µP Bus, Bit1

B0 8 I/O µP Bus, Bit0

AT73C501 /

AT73C502 and

EEPROM

Interface Pin I/O Description

SOUT0 4 O Serial Output, used as a

clock for EEPROM

SOUT1 5 O

Serial Output, used as Chip

Select (CS) for AT73C501

and as Data Input (DI) for

EEPROM

SIN 33 I Serial Data Input, data from

AT73C501 or from EEPROM

SCLK 32 I Seri al Clock Input, bit clock

from AT73C501

Control Signals

of µP Bus and

Status/Mode

Bus Pin I/O Description

STROBE 43 O Strobe Output

BRDY 37 I Microprocessor ready for

I/O, Active Low

ADDR1 40 O Addres s Ou tpu t 1, used for

µP bus

ADDR0 39 O Addres s Ou tpu t 0, used for

Status/ Mode bus and for

Impulse Outputs

RD/WR 36 O Read/Write Signal

AT73C500

AT73C501 and AT73C502

The AT73C 501 consi sts of s ix, 16 -bit a nalog-to -digi tal con-

verters. The converters are equipped with single-ended

input s. For differenti al ended applic ations, the AT73 C502

chip is used.

The conv erters contain a referenc e volta ge gener ator, vo lt-

age monit oring bl ock and seri al output inter face. Bo th con-

verters are based on high-performance, oversampling

Sigma-Delta modulators and digital decimation filters.

Figure 6. Block diagram of the single-ended ADC chip, AT73C501

In a 50 Hz meter, the nominal decimated sampling rate of

3200 Hz is us ed. Th is co rresponds to 64 samples per eac h

line frequency cycle. 60 Hz meters operate with 3840 Hz

sample rate. The master clock frequency of the ADC is

1024 times higher than the above frequencies, i.e.

3.2768 MHz in 50 Hz meters and 3.93216 MHz in 60 Hz

systems. The default meter constant of AT73C500 energy

counters is based on the above sample rates.

Other sample frequencies can be used, bu t the energy

results have to be scaled accordingly. If higher sampling

rate is selec ted, the meter constant will also be increased

by the same ratio.

The three current inputs of AT73C501 are fed from second-

ary outputs of current transformers, from Hall sensors or

other similar sensors. In differential-ended applications,

such as with current shunt resistors, the AT73C502 ADC

can be used. On both of these converters, the voltage

inputs must be equipped with simple external voltage divid-

ers.

The input voltage range of each converter is 2VPP. The

characteristics of a Watt-hour meter operating, according to

IEC1036 specification, are based on a certain basic cur-

rent, IB. As a default, the basic current of AT73C500

chipset is to 6.25% of the current input full scale value. This

means that if a meter is designed for IB = 5A RMS, the full

scale range of the current channels will be:

The following current transformer and voltage divider con-

figuration is recomm ended for a 230V, 3-phase system,

with 5A basic current:

With the above settings, the nominal pulse rate of the

meter constant outputs is 1250 impulses/kWh (1250

impulses/kVArh) and the r ate of four display outputs 100

impulses/kWh (100 imp/kVArh).

When used in a 5A transformer operated meter, the maxi-

mum cur ren t r ang e ca n b e s c aled down to 8A f or exam pl e.

In this case, the meter constant will be ten times higher

than in an 80A meter, i.e. 12500 impulses/kWh. Simila rly,

the starting current level will be transferred to 2mA, from

20mA.

VOLTAGE

REFERENCE

SERIAL OUTPUT

LOGIC

VOLTAGE

MONITORING

TIMING AND

CONTROL

DECIMATION

FILTER

DECIMATION

FILTER

DECIMATION

FILTER

DECIMATION

FILTER

DECIMATION

FILTER

SIGMA-DELTA

MODULATOR

SIGMA-DELTA

MODULATOR

SIGMA-DELTA

MODULATOR

SIGMA-DELTA

MODULATOR

SIGMA-DELTA

MODULATOR

SIGMA-DELTA

MODULATOR DECIMATION

FILTER

Voltage Inputs Current Inputs

Converter full-scale input 2.0VPP 2.0VPP

Corresponding full-scale

line voltage / current 270VRMS 80ARMS

IFS = 5 ARMS 100

6.25

-----------

×80 ARMS

AT73C500

If the n ominal voltage is chosen to be 120V, the vo ltage

divider can either have the same config uration as in the

230V meter, or it can be modified to produce 2.0Vpp with

140V phase voltage. In the latter case, the default meter

constant will be roughly twice the constant of 230V meter,

i.e. 241 1 impul ses/ kWh. T he mete r constan t ca n be scale d

to an even number value by means of calibration.

As des cribed above, the c onfigu ration of v oltage d ividers

and cur rent trans former s affects to al most all p arameter s

being metered, li ke energy counters and i mpulse outputs.

A calibration coefficient is provided for the adjustment of

the display pulse rates. With this coefficient, the effect of

various vo ltage divider and current transformer configura-

tions can be c ompensated. Care should be taken that the

dynamic range of the A/D conve rters is alway s effectively

utilized. The use of calibr ation coeff icients i s described in

the next section.

Current and voltage samples of AT73C501/AT73C502 are

multiplexed and transferred to AT73C500 through a serial

interface. The timing of the interface is presented in the

next section.

AT73C50 1/AT73 C502 contai n an inter nal b andgap voltag e

refere nce. When used in class 0.5 and 0.2 me ters, small er

temperature drift is required. This can be achieved by

bypassing the internal reference and using temperature

compensated external reference instead. The referenc e is

selected with the BGD input.

There is an in teg ra ted voltage moni torin g blo ck on the con-

verter chi p. The PFAIL output is forced high if the level of

voltage s uppli ed to VCIN input dr ops below 4.2V . There is a

hysteresis in the monitoring function and PFAIL returns low

if voltage at VCIN is raised back above 4.3V.

PFAIL output of AT73C501/AT73C502 can be connected

to an inter rupt input o f AT73C500. A T73C500 det ects the

rising ed ge of PFAIL. To assure reliable power-down pro-

cedure after voltage break, the VCC supply of AT73C500

must be equipped with a 470 µF or larger capacitor.

AT73C500

AT73C50 0 p er forms p ower and en er gy c alc ulati ons . It a lso

controls the i nterfacing to the AT73C501 (or AT73C502)

and to an external microprocessor. The block diagram of

the DSP is presented below.

Figure 7. Block diagram of DSP software

Serial Bus Interface

The timing of the serial b us interfac e connecting the A DC

and DSP devices is presented in Figure 8. The same bus is

used to read the calibration data from an external

EEPROM. This operation is descri bed in section “Loading

of Calibration Coefficients” on page 19.

When the three current and three voltage samples are

ready, AT73C501/AT73C502 raises the ACK output.

AT73C50 0 de tec ts the ri si ng e dge of A CK, a nd, a fter a f ew

clock c ycles, it is ready to read the samples th rough the

serial bus. The transfer is initiated by CS/SOUT1 signal

and the data bits are strobed in at the falling edge of

CLKR/SCLK clock. Six 16-bit samples is transferred in the

following sequence: I1, U1, I2, U2, I3 and U3.

BGD Reference

0 (VSS) Internal

1 (VDD)External

ACTIVE ENERGY

CALCULATION

CURRENT

DERIVATION

GAIN

CALIBRATION

FREQUENCY

MEASUREMENT

VOLTAGE

MEASUREMENT

DC OFFSET

SUPPRESSION

PHASE

CALIBRATION

HILBERT

TRANSFORM

ACTIVE POWER

MEASUREMENT GAIN AND OFFSET

CALIBRATION

REACTIVE POWER

MEASUREMENT

POWER FACTOR

DERIVATION

APPARENT POWER

EVALUATION

GAIN AND OFFSET

CALIBRATION

REACTIVE ENERGY

CALCULATION

u1(n)

u2(n)

u3(n)

i1(n)

i2(n)

i3(n)

AT73C500

Figure 8. Serial bus timing

Operating Modes of AT73C500

The AT73C500 chipset has six operating modes. The

mode is selected by three mode control inputs which

AT73C500 reads through a bus during the initialization pro-

cedure after a reset state. The operation of

AT73C501/AT73C502 is independent of the mode

selected.

In operatin g mode 7, the defaul t display pulse rate is 10

impulses per kWh, instead of 100 impulses per kWh, as in

other modes.

Normal Measurement Mode

AT73C500 devices support both stand-alone and micropro-

cessor confi gurati on. The calib ratio n coeffi cient s can eit her

be supplied by a processor or stored in an 128 x 8-bit

EEPROM. The ROM is interfaced with AT73C500 via three

pin serial bus. AT73C500 and the processor communicate

through an 8-bit bus.

The onl y operat ional differ ence between s tand-alone an d

µP mode i s t he wa y of r ead in g c ali br ati on co effi ci en ts. Th is

allo ws variou s com binat ions of t hese tw o conf igur ation s to

be utiliz ed. For ex ample, th e calibra tion data can be sto red

in an EEPROM even though the processor reads and dis-

plays the measurement results supplied by AT73C500

device.

In most cases, the use of external EEPROM gives flexibility

to the meter testing and calibration, and also makes the

processor interface easier to implement. Therefore, th is

configuration is recommended even in meters equipped

with a separate microprocessor.

The same sequence of basic calculations is performed

both in poly-phase and single-phase meters. This

sequence consists of DC offset suppression, phase, gain

and of fset cal ibra tio n, c alcul atio ns of m ea surem ent quant i-

ties and data transfer to µP bus and pulse outputs.

AT73C50 0 co ns tantl y m oni tor s var io us tampering an d faul t

situations, which are indicated by status bits.

After a reset state, AT73C500 goes through an initialization

sequence. The device reads the operating mode and

fetches the cali bration coeffici ents and adjustment factors

for output pulse rate and starting current level, either from a

non-volatile memory or from a microprocessor. After that

the normal measurement starts. The reset state is normally

activated by power-up reset following the recovery from a

voltage int e rru pti on.

CLK

CLKR

ACK

FSR

DATA

CH1, B15

MSB CH1, B14 CH1, B0

LSB CH2, B15

MSB CH2, B0

LSB CH6, B1 CH6, B0

6 * 16 BITS

Mode Number Mode Bit 2 Mode Bit 1 Mode Bit 0 Operating Mode Calibration Data Storage

0000Not in use

1001Normal operationEEPROM

2010Multi-channel operationEEPROM

3011Normal operationMicro-processor

4100Multi-channel operationMicro-processor

5101Test mode None

6110Not in use

7111Normal operationEEPROM

AT73C500

Measurements and Calculations

The first operation performed by AT73C500 is digital high-

pass filtering. The purpose of the filtering is to remove the

DC offset of both current and voltage samples.

From offset free samples, active power is calculated

phase-by-phase with simple multiplication and addition

operations.

First, the current samples are multiplied by voltage sam-

ples. The multipl ication re sults are summed over one l ine

period and finally the sum value is divided by 64. This dis-

crete t ime o per ati on gives the av erag e power of one 50 Hz

period and the result corresponds to the following continu-

ous time formula:

where

T = 1/50 Hz,

n = 1, 2, 3,..., 20 (basic 50 Hz frequency and the har-

monics),

An = frequency response of calculations.

This method of calculation does take into account the effect

of harmonics.

The total power is calculated by summing the power of

each line phase. Reactive power calculation is based on a

similar procedure. Before mu ltiplying the cur rent and volt-

age samples AT73C500 performs a frequency independent

90 degree pha se shift of the voltage s ig nal. T hi s is r ea li zed

with a di git al H ilber t t ran sform ati on f ilter . Th e ba ndwi dth of

reactive powe r mea sure men t is limited to 360 Hz.

Based on the active and reactive results apparent power

and pow er fac tors are determi ned. RMS phas e voltages

are calculated by squaring and summing the voltage sam-

ples and fin ally ta king a squar e root of the r esul ts. Cur rent

is deter mined by dividi ng apparent po wer result by corr e-

sponding phase voltage.

Frequency measurement is based on a comparison of the

line frequency and AT73C500 sampling clock frequency.

The measurement range is from 20 Hz to 350 Hz.

All measurements and calculations, except frequency mea-

sureme nt, a re mad e ov er 1 0 l ine cy cle per io ds . The resu lts

are updated and transferred to processor bus once in 200

ms.

Measurement Registers

For the measurement parameters 25 registers are allo-

cated:

The size of the registers is either 16-bit or 32-bit. IEC spec-

ifications apply to the calculations of active and reactive

power and energy (REG 0-5 and REG 12-15). Other results

are intended mainly for demand recording and for va rious

diagnostic and display functions. The accuracy of those are

limited due to the finite resolution.

--- ANUNsin n wt×{}ANINsin n wt ∅+×N

{}dt×××××[]

∫







n0=

∑

---AnAnUnIncos ∅n

()×××××





n0=

∑

REG0 Phase 1, active powe r, P1(10T), 32-bit register;

REG1 Phase 2, active powe r, P2(10T), 32-bit register;

REG2 Phase 3, active powe r, P3(10T), 32-bit register;

REG3 Phase 1, reactive power, Q1(10T), 32-b it regi ste r ;

REG4 Phase 2, reactive power, Q2(10T), 32-b it regi ste r ;

REG5 Phase 3, reactive power, Q3(10T), 32-b it regi ste r ;

REG6 Phase 1, apparent power, S1(10T), 16-bit register;

REG7 Phase 2, apparent power, S2(10T), 16-bit register;

REG8 Phase 3, apparent power, S3(10T), 16-bit register;

REG9 Phase 1, power factor, PF1, 16-bit register;

REG10 Phase 2, power factor, PF2, 16-bit register;

REG11 Phase 3, power factor, PF3, 16-bit register;

REG12 Active exported energy since the latest reset, +Wp,

32-bit counter;

REG13 Active import ed energy sin ce the latest reset, -Wp,

32-bit counter;

REG14 Reactive energy, inductive load, Wqind, 32-bit

counter;

REG15 Reactive energy, capacitive load, Wqcap, 32-bit

counter;

REG16 Number of 10T periods elapsed since the latest

reset, 32-bit counter;

REG17 Fre que nc y, f, 16-bit register;

REG18 Reserved for further use, 16-bit register;

REG19 Phase 1, voltage U1, 16-bit register;

REG20 Phase 2, voltage U2, 16-bit register;

REG21 Phase 3, voltage U3, 16-bit register;

REG22 Phase 1, current I1, 16-bit register;

REG23 Phase 2, current I2, 16-bit register;

REG24 Phase 3, current I3, 16-bit register.

AT73C500

In multi-channel mode the active energy of each three

meters (phase s) is store d in regi sters 12- 14. REG 15 is not

in use.

The maximum value of different power registers differs,

depending on the calculation formulas used. The scaling of

registers is described below.

If a full scale sine signal is applied to voltage and current

inputs and the voltage and current channels are exactly in

the same phase, a value of 258F C2F7H will be produced

in the 32 -bit P1, P2 a nd P3 regist ers. The LS bit will corre-

spond to about 34 microwatts in nominal input conditions of

270V maximum phase voltage and 80A maximum current.

If the loa d is full y reacti ve (± 90° phase diffe rence) and full

scale signals are applied, the Q1, Q2 and Q3 register con-

tent will be 2231 594DH positive or negative, and the LSB

will represent about 38 µVAr. The maximum value of the

16-bit S regis ters is 258EH an d this value is obt ained if a

full scale amplitude is produced to the current and voltage

inputs. LS bit of the S registers correspond to about 2.25VA

power.

The following formula is used to calculate the power factor:

The PF register contents 7FFFH represents power factor

value one and the contents 0000H value zero. Negative PF

valu es are s tored cor resp ondingl y as n egativ e bina ry nu m-

bers. It shoul d be noted that th e si gn of power fact or res ult

indicates whether the loading is inductive (+) or capacitive

(-).

The co nten ts of frequency r egi st er ( REG 1 7) actually r epre-

sents a 16-bit figure whi ch corr esponds to the du ration o f

50 line frequency cycles. The measurement is made by

comparing the line frequency with one of the sampling

clocks of AT73C500 and therefore the result depends on

the crystal frequency used. With default 3.2768 MHz crys-

tal, the resolution of time value is 1.25 ms. To get the fre-

quency, the following calculation has to be made:

If the master c lock frequency (MCLK ) of AT73C500 is not

nominal, the following formula gives frequency results:

In the default condition, value 7FFFH of register 17 corre-

sponds to 1.22 Hz frequency, value 0320H represents

50 Hz and 0001H 40 kHz. However, in practice, the band-

width of frequency measurement is limited to 20 Hz to

350 Hz.

The frequency measurement is locked with one of the

phase v oltages . If this volt age disa ppears, AT73C500 tries

to track one of the other phases. The frequency measure-

ment works down to about 10% level of the full scale volt-

age range. The harmonics content of phase voltage should

be below 10%. I f it is hi gher, er roneous f requency results

may be obtained.

The voltage regis ters (REG19-REG21) are scale d so that

full scale sinusoidal input signal at AT73C501/AT73C502

voltage channe ls will produce 7A8BH value into voltage

registers. This means that the resolution of the registers is

about 8.6 mV. Accordingly, full scale current will produce

7DA4H to curr ent registers (REG22-REG24) pr oviding a

resolution of about 2.5 mA. In practice, the voltage can be

measured down to about 25V leve l and current do wn to

about 100mA.

If either voltage or current, or both, contain a considerable

amount of ha rmonics produc ing a squar e wave type wave-

form, it is recommended to scale the input range so that the

maximum pe ak -to -peak val ue i s at leas t 1 0% be low the ful l

scale range of inputs. This is to avoid overflow in the calcu-

latio ns perfo rm ed by AT73 C500 .

Energy Counters

Four 32-bit counters (REG12-REG15) measure energy

consumption. In nominal situations, the counters are

alway s increm ented wh en 0.4W h (0.4V Arh) ener gy is co n-

sumed. The counters can store minimum of 1100 days con-

sumption, provided that AT73C501/AT73C502 and

AT73C500 are used with default settings.

Impulse outputs are generated from these counters. The

meter constant rate represents 2 LSBs of a counter which

equals 0.8 Wh (0.8 VArh) and produces 1250

impulses/kWh. (1250 impulses/kVArh). In modes 1 to 4, the

display pulses are generated from 25 LSBs of a counter.

This corresponds to an impulse rate of 100 impulses/kW h

(100 impulses/kVArh). It is possible to adjust this rate with

MCC cali bration c oefficient. In mode 7, 250 LSBs of th e

energy register is neede d to generate one impu lse (10

impulses/kWh).

The default values above are based on 80ARMS full sca le

current, 270VRMS full scale vol tage and 3.2768 MHz clock

rate.

The cr ysta l fr e quen cy wi ll aff ect the value s o f en er gy r egis-

ters (REG12-REG15) and time register (REG 16). It will

also change the pulse rates of the impulse outputs.

PF sign Q

()abs P()

abs S()

------------------

×=

f40000

REG17

------------------- Hz=

f40000

REG17

------------------- MCLK

3.2768MHz

------------------------------

×Hz=

AT73C500

It is r ecommended tha t 50 Hz mete rs are operate d from

3.2768 MHz crystal. In 60 Hz system, a 3.93216 MHz clock

is normally used. Because the clock frequency generates a

time reference for energy calculations, the content of

energy r egister s and als o the puls e rate of impulse outp uts

will change when crystal is changed. For example, the

nominal meter constant and display pulse rate of 60 Hz

meter (3.93216 MHz clock) is:

and

The LSB of energy re gister s corres pon d to 0.3 3W h ins tea d

of 0.4Wh, as follow s:

The pulse rate can be scaled to 100 imp/kWh by program-

ming value 5 to MCC coefficient, as below:

which equals 100 impulses per kilowatt hour.

The foll owing table sum marizes the co ntents of all m ea-

surement registers.

MC 60Hz

50Hz

--------------1250 imp

kWh

------------

×1500 imp

kWh

------------

DP 60Hz

50Hz

--------------100

×imp

kWh

------------120 imp

kWh

------------

ELSB 3.2768MHz

3.93216MHz

----------------------------------0.4Wh

×0.333333…Wh==

IMP (25 MCC) 1

imp

--------- ELSB

×+30 1

imp

--------- 0.3333…Wh×10Wh

imp

---------

===

REG0 - REG2 U = 270V, I = 80A, PF = 1 258F C2F7 34.276 µW

REG3 - REG5 U = 270V, I = 80A, PF = 0 2231 594D 37.653 µVAr

REG6 - REG8 U = 270V, I = 80A 258E 2.2467 VA

REG9 - REG11 PF = 1

PF = -1 7FFF

8001 0.0000305

-0.0000305

REG12 - REG15 W = 1.718GWh FFFF FFFF 0.4Wh

REG16 ∆T = 238609.3h FFFF FFFF 0.2s

REG17 50*T = 40.959s 7FFF 1.25 ms

REG19 - 21 U = 270V 7A8B 8.6 mV

REG22 - 24 I = 80A 7DA4 2.5 mA

AT73C500

Output Operations

The data output by AT73C500 can be divided into three

catego ries: d ata t o extern al proc essor, status inform ation

and impul se output s. AT73 C500 reads mode infor mation,

and in mode 3 and 4, also calibration data via external bus.

For the I/O operation, two 8-bit buses are allocated.

The same eight data lines are reserved both for the

impulse outputs and for the processo r interface. The se pa-

ration is don e wi th two a ddr ess pi ns. W hen c omm uni ca tin g

with the microprocessor, address 1 (pin A DDR1) is acti-

vated (high). Impulses are output combined with a high

level of a ddress 0 (ADDR0). For sta tus informati on sepa-

rate 8-bit bus is reserved. The table below describes the

use of the two buses of AT73C500.

For status and impulse outputs, external latches are

needed to store the information while buses are used for

other tas ks. In most ca ses, the dat a bus of AT73C5 00 and

processor I/O bus can be connecte d directly with each

other. The data transfer is controlled by handshake signals,

ADDR1, RD/WR, STROBE and BRDY. One of the status

outputs DATRDY (B9, ADDR0) can be used as an interrupt

signal. Interrupt can be also generated from the handshake

lines.

In most meters, only some of the I/O operations of

AT73C50 0 are needed. If a meter con tains a sepa rate pro-

cessor, status outputs of AT73C500 are typically not used

since the processor will anyway track the status information

supplied by AT73C500. Often only one or two of the

impulse outputs are wired to the test LED or electrome-

chanic al co unte r.

Data Transfer to External Microprocessor

The calculation results of AT73C500 are transferred to pro-

cessor via 8-bit p arallel bus. During normal operation, the

information transfer is divided into six packages which are

written in 2 00ms intervals after th e calculations over ten

line frequency cycles have been completed. There is a time

interval of one line cycle between each individual data

package. The first four bytes of a package contain synchro-

nization, mode and status information, and the rest 12

bytes are reserved for the actual measurement results. The

contents of the six data packages are as follows:

Data bits Bus Address Mode Usage

B0 - B7 Data Bus ADDR0 Output Impulse

Outputs

B8 - B15 Status Bus ADDR0 Output Status

Information

B0 - B7 Data Bus ADDR1 Input/

Output Processor

Interface

B12 - B14 Status Bus ADDRx Input Mode

Inputs

Table 1. Package 0

Byte Data Order Meaning

1 Sy nc LS Sin gle byte Synchroniz ati on

2 Sync MS Single byte Synchronization

3 Mode Single byte Mode information

4 Status Single byte Status information

5 REG0 (LS+2) byte Active power, phase 1

6 REG0 MS byte Active power, phase 1

7 REG0 LS byte Active power, phase 1

8 REG0 (LS+1) byte Active power, phase 1

9 REG1 (LS+2) byte Active power, phase 2

10 REG1 MS byte Active power, phase 2

11 REG1 LS byte Active power, phase 2

12 REG1 (LS+1) byte Active power, phase 2

13 REG2 (LS+2) byte Active power, phase 3

14 REG2 MS byte Active power, phase 3

15 REG2 LS byte Active power, phase 3

16 REG2 (LS+1) byte Active power, phase 3

AT73C500

Table 2. Package 1

Byte Data Order Meaning

1 Sync LS Single byte Synchronization

2 Sync MS Single byte Synchronization

3 Mode Single byte Mode information

4 Status Single byte Status information

5 REG3 (LS+2) byte Reactive power, phase 1

6 REG3 MS byte Reactive power, phase 1

7 REG3 LS byte Reactive power, phase 1

8 REG3 (LS+1) byte Reactive power, phase 1

9 REG4 (LS+2) byte Reactive power, phase 2

10 REG4 MS byte Reactive power, phase 2

11 REG4 LS byte Reactive power, phase 2

12 REG4 (LS+1) byte Reactive power, phase 2

13 REG5 (LS+2) byte Reactive power, phase 3

14 REG5 MS byte Reactive power, phase 3

15 REG5 LS byte Reactive power, phase 3

16 REG5 (LS+1) byte Reactive power, phase 3

Table 3. Package 2

Byte Data Order Meaning

1 Sync LS Single byte Synchronization

2 Sync MS Single byte Synchronization

3 Mode Single byte M od e info rma tion

4 Status Sing le by te Status information

5 REG6 LS byte Apparent power, phase 1

6 REG6 MS byte Apparent power, phase 1

7 REG7 LS byte Apparent power, phase 2

8 REG7 MS byte Apparent power, phase 2

9 REG8 LS byte Apparent power, phase 3

10 REG8 MS byte Apparent powe r, phase 3

11 REG9 LS byte Power factor, phase 1

12 REG9 MS byte Power factor, phase 1

13 REG10 LS byte Power factor, phase 2

14 REG10 MS byte Power factor, phase 2

15 REG11 LS byte Power factor, phase 3

16 REG11 MS byte Power factor, phase 3

Table 4. Package 3

Byte Data Order Meaning

1 Sync LS Single byte Synchronization

2 Sync MS Single byte Synchronization

3 Mode Single byte Mode information

4 Status Single byte Status information

5 REG12 (LS+2) byte Active exported energy

6 REG12 MS byte Active exported energy

7 REG12 LS byte Active exported energy

8 REG12 (LS+1) byte Active exported energy

9 REG13 (LS+2) byte Active imported energy

10 REG13 MS byte Active imported energy

11 REG13 LS byte Active imported energy

12 REG13 (LS+1) byte Active imported energy

13 REG14 (LS+2) byte Reactive energy,

inducti ve load

14 REG14 MS byte Reactive energy,

inducti ve load

15 REG1 4 LS byte Reactive energy,

inducti ve load

16 REG14 (LS+1) byte Reactive energy,

inducti ve load

AT73C500

The six data packages arrive as follows:

Figure 9. Data transfer to processor in six packages

In normal mode, the Sync LS byte indicates the number of

data pack age whi ch will follo w (value 0...5) . There are also

two special situations indicated by this byte. Value six of

Sync LS byte means that the processor is expected to sup-

ply calibration data to AT73C500. Value seven is written by

AT73C500 in cas e power interruption is detected and bill-

ing information needs to be transferred to microprocessor.

In this c as e the pr oces so r k no ws th at b oth p a cka ges 3 an d

4 will follow one after each other as shown in Figure 10.

Table 5. Package 4

Byte Data Order Meaning

1 Sync LS Single byte Synchronization

2 Sync MS Single byte Sy nchro nizat ion

3 Mode Single byte Mode information

4 Status Single byte Status information

5 REG15 (LS+2) byte Reactive energy,

capacitive load

6 REG15 MS byte Reactive energy,

capacitive load

7 REG15 LS byte Reactive energy,

capacitive load

8 REG15 (LS+1) byte Reactive energy,

capacitive load

9 REG16 (LS+2) byte Counter

10 REG16 MS byte Counter

11 REG16 LS byte Counter

12 REG16 (LS+1) byte Counter

13 REG17 LS byte Frequency

14 REG17 MS byte Frequency

15 REG18 LS byte Reserved

16 REG18 MS byte Reserved

Table 6. Package 5

Byte Data Order Meaning

1 Sync LS Single byte Synchronization

2 Sync MS Single b y te Synchronizati on

3 Mode Single byte Mode information

4 Status Single byte Status information

5 REG19 LS byte Voltage, phase 1

6 REG19 MS byte Voltage, phase 1

7 REG20 LS byte Voltage, phase 2

8 REG20 MS byte Voltage, phase 2

9 REG21 LS byte Voltage, phase 3

10 REG21 MS byte Voltage, phase 3

11 REG22 LS byte Current, phas e 1

12 REG22 MS byte Current, phase 1

13 REG23 LS byte Current, phase 2

14 REG23 MS byte Current, phase 2

15 REG24 LS byte Current, phase 3

16 REG24 MS byte Current, phase 3

1234567891012345

200ms = 655360 clocks @ 3.2768 MHz

20 ms

Pack

0Pack

1Pack

2Pack

3Pack

4Pack

5Pack

0Pack

1Pack

2Pack

DATRDY

LINE PERIOD

AT73C500

Content of S ync LS by te is des cri bed in t he following table.

Bits 3-7 of the Sync LS byte are not used. The Sync MS byte contains a unique 8-bit data, 80H. It can

be used as a synchronization byte by the external control-

ler.

The mode byte contains the following information:

Figure 10. Meaning of bits in mode byte

The contents of the status byte equals the content of the

external Status bus as described in the section “Status

Information” on page 17.

In the beginning of I/O operation, AT73C500 writes a high

pulse to B9 pin of the Status bus (ADDR0). This pin can be

externally latched to lengthen the pulse over the whole out-

put operation. It can be used to generate a data ready

(DATRDY) interrupt to processor.

Figure 11 shows the timing of one data package. In nomi-

nal conditions, it takes 200 clock cycles to transfer all 16

bytes. A high pulse (DATRDY) is written to bit B9

(SMBUS1) of Status bus 11 c locks be fore the fir st byte is

available and low pulse 12 cloc ks after the last byte has

been sent.

Table 7. Sync LS Byte

B7 - B3 B2 B1 B0 Data

package Mode

X X X X X 0 0 0 0 Normal operation,

Data output

X X X X X 0 0 1 1 Normal operation,

Data output

X X X X X 0 1 0 2 Normal operation,

Data output

X X X X X 0 1 1 3 Normal operation,

Data output

X X X X X 1 0 0 4 Normal operation,

Data output

X X X X X 1 0 1 5 Normal operation,

Data output

X X X X X 1 1 0 (none) DSP waiting for

calibration data

X X X X X 1 1 1 3 and 4 PFAIL active,

billing information

to be transferred

B0B1B2B3B4B5B6B7

Mode byt e

Not used State of MODE

input pins of the

DSP

AT73C500

Figure 11. Conten ts of a data package

AT73C500 offers some time for the processor to analyze

the synchronization, status and mode information before

starting to supply the measurement results. The 12 mea-

surement bytes are written on every 11th clock period.

Four handshake signals are provided, ADDR1, RD/WR,

STROBE and BRDY, for interfacing with the microproces-

sor. ADDR1 is always taken high when AT73C500 is either

writing to µP bus or reading the bus contents. When used

with slow peripheral, the BRDY input of AT73C500 can be

used to hold the device in write mode until the processor

has finished readi ng the bus. However, the total length of

one data package should always be less than 300 clock

cycles of AT73C500. Longer I/O periods may result errone-

ous measurement results.

Figure 12. Handshake signals of the DSP

Following the falling edge of BRDY, the data can be

stro bed into the µP by the risi ng edge of the S TROBE s ig-

nal. If the microprocessor is able to read data continuously,

BRDY can be kept constantly low. Also BRDY should be

low whenever DATRDY is inactive allowing AT73C500

freely use its buses.

To avoid c onflicts, the processor shou ld always k eep its

bus in t ri-s tate mode, unles s it is used to wri te calibrat ion

coefficients to AT73C500.

Sync LS Sync MS Mode Status Data 1 Data 2 Data 11

Measurement data, 12 bytes

Synchronisation data Status data

Data 12

200 clock cycles

45 clock cycles 143 clock cycles

LATCHED

DATRDY

CLK

STROBE

RWSU

ASU

RWH

BRS

CLK

DATA

FROM DSP

BRDY

STROBE

ADDR1

RD/WR

SDLY

DDLY

AT73C500

Status Infor m atio n

AT73C500 provides the following status information

through the Status bus of AT73C500 (B8 - B15, ADDR0).

High level of Lx flags indicates that a phase voltage is

above 10% level of the full scale voltage. If a voltage drop

is detected, the corresp onding status bit is written low.

AT73C500 is contin uously mon itoring the voltage of eac h

phase.

FAIL flag signifies that something abnormal has been

detected. The following situations may cause a high level of

FAIL: re ad operation of cali bration coeffic ients is not suc-

cessful, the serial bus of A T73C501 or AT73C502 i s not

working properly, the measurement results can’t be trans-

ferred to microprocessor, AT73C500 has detected an inter-

nal failure.

If any of the calibration coefficients and corresponding

back-up values do not match, AT73C500 performs two

extra rea d op erations to eli minat e the po ssib ility of a tran s-

fer error. If the error still exists after the third trial, incorrect

coefficients are replaced by the default values. FAIL flag is

activated indicating that a potential error has been

detected. FAIL is also taken high in case i t is not possible

to read c alibra tion c oefficie nts from the µP o r EE PROM, or

if the processor supplies too few coefficients. In both cases,

the read operation will finish in a time-out situation.

The voltage monitoring block of AT73C501/AT73C502 is

used to detect voltage interruptions before the supply volt-

age of AT73C500 drops. High level of PFAIL output at the

ADC indicates a voltage break situation. The measurement

results suppli ed by AT73C501/AT 73C502 may be err one-

ous, and AT73C500 and microprocessor has to be pre-

pared for supply vo ltage inter ruption . A high level o f PFAIL

causes an immediate write of data packages 3 and 4

(accumulated energy information) to pro cessor bus. The

tim i ng of t h is op eration i s presente d i n F i g ure 1 3. Th e re ar e

16 clocks between the two 12 byte data packages but the

header b ytes a re not r epeated in the b eginni ng of pa ckag e

Figure 13. Transfer of billing information to processor following a PFAIL interrupt

In case of an imminen t voltage break, the microproces sor

stores the energy val ues into a non-vo latile mem ory. The

devices can operate for a short period of time powered by

an electrolytic capacitor or by battery back-up.

AT73 C500 de vices are taken to a soft reset state a nd nor-

mal operation will be recovered after the supply voltage is

high again. About one line cycle is needed to start normal

measurements. During this initialization phase no calcula-

tions are performed.

STUP output (active high) indicates that the current of each

of the three phases is below the specified starting level and

no energy is accumulated. This status flag is very useful

during the calibration of a mete r since immediate feedback

about staring current level is provided.

TAMP flag informs about potential tampering. It is activated

if one or more phase currents are zero or negative. There-

fore it very effectively indicates current transformer reversal

or short-circuit.

Status

Bus Bit Status

Flag Meaning

B15 TAMP High: Potential event of

tampering detected

B14 STUP High: Current of all phases

below starting level

B13 L3 High: Phase 1 voltage above

10% of full-sc ale

B12 L2 High: Phase 2 voltage above

10% of full-sc ale

B11 L1 High: Phase 3 voltage above

10% of full-sc ale

B10 FAIL High: Operating error detected

B9 DATRDY High: Data available on the µP bus

B8 INI

Low: AT73C500 in initializati on

phase, EEPROM interface in use,

AT73C501 (or AT73C502) interface

disabled

Sync LS Sync MS Mode Status Data 1 Data 2 Data 12

Measurement data, 12 bytes + 12 bytes

Synchronisation data Status data

Data 1

337 clock cycles

45 clock cycles 280 clock cycles

Data 12Data 2

LATCHED

DATDRY

CLK

STROBE

AT73C500

Impulse Outputs

AT73C5 00 pr ovides eigh t imp ulse ou tputs, fo ur mete r c on-

stant outputs and four pulse outputs to drive electrome-

chanical display counters which can register exported and

imported active energy and capacitive and inductive reac-

tive energy. These outputs use the same output lines as

used for the processor interface. Impulses are combined

with address 0 (ADDR0). The table below shows the

impulse outpu ts availab le in mo des 1 an d 3 . Mode 7 offe rs

the same outputs, but the rate of the display pulses is

10imp/kWh (kVArh).

An external register is needed to latch and buffer the

pulses . The regis ter c an fur ther d riv e both electr omec hani-

cal dis play c ounte rs and LE Ds. In modes 1 to 4, th e nomi-

nal pulse rate of display outputs is 100imp/kWh or

100imp/kVArh (UMAX = 270V, IMAX = 80A) and meter con-

stant outputs 1250imp/kWh (1250imp/kVArh). The length

of each display pulse is 117ms when operated from

3.2678 MHz c rys tal . Me ter c ons ta nt p ulse stays h igh for 2 0

ms.

If th e de vi ce s ar e us ed in a 5A me te r, cu rr e nt in pu t s ca n be

scaled to 8A full scale level. In this case, the nominal

impulse rates are ten times higher than the above values.

Multi-channel Mode

Modes 2 a nd 4 ar e res er ved fo r mul ti-c han nel op er ation. In

these mode s, th e chip s oper ate like thr ee ind ependen t sin-

gle phase meters and st ore the calcul ation resul ts in sepa-

rate regi ster s phas e-by- phase (m eter-by- meter ). Th e bas ic

sequence of o peration is otherwise similar to the normal

mode.

Impulse Outputs

In multichannel oper ation three impulse outputs are avail-

able for display counters. The absolute energy value is

measur ed and the rev ersal of cur rent flow doesn’t affe ct t o

pulse rates. The FAIL signal can, however, be used to

determine whether the energy being registered is pos itive

or neg ative. Met er co nstan t pulse rat e co rresp onds to total

active energy of the three single phase channels summed

together as shown in the table b elo w.

Test Mode

This mod e can be used for initi al calibr ation purpose s or in

a special meter for additional processing of sample data. In

this mode, A T73C501/AT73C502 sample s the six inputs

normally and transfers the samples to AT 73C500, which

performs DC suppression and further writes the samples to

8-bit processor bus together with header bytes in the fol-

lowing sequence.

Several inpu t combinations can be measured to check the

gain and phase error in different conditions. An interfacing

computer can be programmed to calculate the calibration

coefficients based on the samples supplied by AT73C500.

At the end of the calibration, the coefficie nts have to be

stored in a non-volatile memory of the meter as described

in “Loading of Calibration Coefficients” on page 19.

Table 8. Impulse Outputs in Operating Modes 1 and 3

Output Bit Impulse Output Type Impulse Rate

B7 - VArh Meter Constant 1250imp/kVArh

B6 + VArh Meter Const ant 1250imp/kVArh

B5 - Wh Meter Constant 1250imp/k Wh

B4 + Wh Meter Constant 1250imp/kWh

B3 + Wh Display 100imp/kWh

B2 - Wh Display 100i mp/kWh

B1 + VArh Display 100imp/k VArh

B0 - VArh Display 100imp/kVArh

Output Bit Impulse Output Type Impulse Rate

B7 Not Used Not Used -

B6 Not Used Not Used -

B5 Not Used Not Used -

B4 ± Wh Meter Constant

Sum of all 3

channels 1250imp/kWh

B3 ± Wh Display,

Channel 1 100imp/kWh

B2 ± Wh Display,

Channel 3 100imp/kWh

B1 ± Wh Display,

Channel 2 100imp/kVArh

B0 Not Used Not Used -

Byte Contents

1 Sync LS byte

2 Sync MS byte

3 Mode Byte

4 Status Byte

5,6 I1, LS byte and MS byte

7,8 U1, LS byte and MS byte

9,10 I2, LS byte and MS byte

11,12 U2, LS byte and MS byte

13,14 I3, LS byte and MS byte

15,16 U3, LS byte and MS byte

AT73C500

Calibration

The calibr ation coeffic ients always have to be loaded into

AT73C500 registers after reset state. The co efficients are

either read from an external EEPROM or supplied by a

microprocessor via the 8-bit bus.

Loading of Calibration Coefficients

In modes 3 and 4, a microprocessor takes care that the

coefficient s are kep t in a non-volatile m emory during volt-

age break . After the voltag e break, the DSP first write s the

four header bytes, Sync LS, Sync MS, mode and status

information on the µP bus and then starts waiting for the

calibration data. The processor reads the status and mode

and af ter that writ es the c oefficients on the bus . The con-

tents of AT73C500 header bytes is described in “Data

Transfer to Ex ternal Micropr ocessor” on page 12 and “Sta-

tus Information” on page 17.

Figure 14. Timing of calibration coefficient read operation

Before using the µP bus, AT73C500 writes a short pulse

(DATRDY) to B9 bit of the Status bus combine d with high

level of address 0 (ADDR0 output). This bit can be taken

directly or throug h an ext ernal latch t o the inte rrupt in put of

the processor. After writing the status and mode bytes,

AT73C50 0 goes to a read mo de and starts waiti ng for c ali-

bration coefficients from the µP. Processor supplies the

coefficients as 8-bit bytes one after another. The timing of

this sequence is presented in Figure 14.

Nine gain calib ration, six offs et calibr ation and three phas e

calibrati on coeffi cients a re read i nto the AT7 3C500 m em-

ory. At the same ti me, a scaling fact or for t he disp lay pu lse

rate and a n adjustment value for starting curr ent is stored.

To minimize the risk of erroneous calibration values, a

back-u p va lue of ea ch coeff ici ent i s als o tr ansfer red by the

microprocessor or from the ROM. The back-up value has to

be written as 2’s complem ent binary number of the actual

calibr ation figure.

. . .

CLK

DATRDY

STROBE

HEADER DATA SUPPLIED BY AT73C500 44 COEFFEICIENTS READ

AT73C500 READY TO

READ CALIBRATION DATA

SYNC LS SYNC MS MODE STATUS COEFFICIENT 0 COEFFICIENT 1

COEFFICIENT 42 COEFFICIENT 43

AT73C500

The calibration data is transferred in the following sequence:

The meaning of the calibration coefficient mnemonics are as follows:

Byte Calibration Coefficient Byte Calibration Coefficient

0 PC1 1 PC1 back-up

2 PC2 3 PC2 back-up

4 PC3 5 PC3 back-up

6 MCC 7 MCC back-up

8 Not used 9 Not used

10 AGC1 11 AGC1 back-up

12 AGC2 13 AGC2 back-up

14 AGC3 15 AGC3 back-up

16 RGC1 17 RGC1 back-up

18 RGC2 19 RGC2 back-up

20 RGC3 21 RGC3 back-up

22 UGC1 23 UGC1 back-up

24 UGC2 25 UGC2 back-up

26 UGC3 27 UGC3 back-up

28 STUPC 29 STUPC back-up

30 AOF1 31 AOF1 back-up

32 AOF2 33 AOF2 back-up

34 AOF3 35 AOF3 back-up

36 ROF1 37 ROF1 back-up

38 ROF2 39 ROF2 back-up

40 ROF3 41 ROF3 back-up

42 OFFMOD 43 OFFMOD back-up

Mnemonic Meaning

PCNPhase calibration factor, phase N

MCC Display pulse adjustment factor for active and reactive energy

AGCNGain calibrati on factor for active power and energy calculati on, ph ase N

RGCNGain calibration factor for reactive power and energy calculation, phase N

UGCNGain calibration factor for phase voltage, phase N

STUPC Starting current adjustment factor

AOFNOffset calibration factor for active power and energy calculation, phase N

ROFNOffset calibration factor for reactive power and energy calculation, phase N

OFFMOD Controls the use of offset factors

AT73C500

AT73C500 provides four handshaking signals, ADDR1,

RD/WR, STROBE and BRDY, for interfacing with the

microprocessor. Microprocessor can use the BRDY input of

AT73C5 00 to ext end th e read and write cyc les. A T73C50 0

stays in t he re ad or w rite mode a s lon g as BRDY is high .

BRDY is sampled a t the rising edge of AT73 C500 master

clock. As s oon as BRDY goes low, the read/write cycle of

AT73C500 will end at the first rising edge of CLK clock.

During read operation data is latched into AT73C500 regis-

ter on the risin g edge of the ST ROBE signal following the

low level of BRDY. A more detailed description about the

handshak e signals is pr esented in sectio n “Data Transfer

to External Microprocessor” on page 12.

Fifteen idle cycles are inserted by AT73C500 between the

read operation of each calibration byte. This allows the pro-

cessor to prepare the next coefficient for transfer or to raise

the BRDY signal in case it is not ready to write the following

byte. If the da ta is ava ilable, BRDY ca n be kep t cons tantly

low. M icroproc ess or ha s to always s upp ly all 44 c alib ratio n

bytes even though some of those may be zero and don't

affect to measurement results.

If AT73C500 detects an error when comparing the calibra-

tion data and corresponding back-up values, it writes the

DATRDY bit high and after that the header bytes on pro-

cessor bus indicating that it is still in initializ ation routine

and wishes to get the calibration data to be transported

once again. If the error still exists after the third trial,

AT73C500 notifies the situation by a FAIL status bit a nd

starts normal operation, discarding potentially incorrect cal-

ibration coefficients.

If AT73C500 is programmed to mode 1 or 2, the coeffi-

cients are stored in an EEPROM of type AT93C46. The

ROM has to support comm unication through a three pin

serial I/O port. The serial ROM inte rface uses the same

port, which also connects AT73C500 to

AT73C501/AT73C502 sample output. During the initializa-

tion phas e, the ADC interfa ce has to be di sabled. Th is can

be done by B8 bit of AT73C500 Status bus (ADDR0). The

output has to be l atc hed by an exte rn al fli p-fl op t o k ee p th e

state over the whole initialization period. The same output

can be used as Chip Select input for the EEPROM.

AT73C500 reads, checks and stores automatically all 44

calibr ation coe fficients . After t hat, B8 bit of S tatus byte is

written low and normal measurement can start. If the

EEPR OM contai ns erro neous data and on e or more c oeffi-

cients don’t matc h with thei r back- up va lue s, the sa me pr o-

cedure is follow ed as in the proc essor mode .

Gain Calibration

Gain calibration is used to compensate the accumulated

magnitude error of voltage dividers, current transformers

and A/D converters. There is a separate 8-bit gain calibra-

tion coefficient for each phase, and for active and r eactive

energy mea su re men t. A si mi la r f or mul a i s als o u se d to ca l-

ibrate the phase voltage values, only the calibration range

is different, 20% for power and 8% for voltage. These cali-

brations will automatically correct the gain error of other

measurement parameters.

The following calculations are done to get the calibrated

results. For active power:

where PN is the active power of phase N and AGCN is the

gain calibration factor of that pha se. The valid range for

AGCN is -128 to +127. Similarly, for reactive power:

where QN is the reactive power of phase N and RGCN is

the gain calibration coefficient for that phase. RGCN vali d

range is -128 to +127.

Gain calibration performed on voltage measurements are:

where UN is the line voltage of phas e N and UGCN is th e

corresponding gain calibration coefficient, ranging from

-128 to +127.

Apparent power and current are automatically gain

adju sted to match the ca librated setti ngs of active po wer,

reactive power and voltage.

Offset Calibration

The low current response of current sensors is often more

or less non-linear. The error caused by thi s non-linearity

can be compensated by a small offset factor which is

added in powe r result s. Offs et cali bration i s done for act ive

and reac tive po wer, separ ately for each p hase. The follow-

ing formulas are used:

and

where PN and QN are the active and reactive power for

phase N, AOFN and ROFN are the respective offset calibra-

tion coefficients and PFS and QFS are the corresponding full

PNPN10.2AGCN

128

----------------

×+





QNQN10.2RGCN

128

-----------------

×+





UNUN10.08UGCN

128

-----------------

×+





PNPNAOFN

128

----------------0.004157 sign

×× (PN)P

×+≡

QNQNROFN

128

----------------0.00457 sign(QN

×× )Q

×+=

AT73C500

scale va lues of the powers. The nomi nal full-scal e values

are:

The valid r ange for the offset c alibration facto rs is -128 to

+127.

The scale of offset calibration for active and reactive power

is different, 89W versus 98VAr in nominal conditions of

270V maximum phase voltage and 80A maximum phase

current. Typically, a small offset factor of a few watts is

enough to com pen sa te the non- l ine arity of cu r re nt se ns ing .

It should be noted that offset calibration will also affect the

starting current level of a meter. If the full sc ale current or

voltage is changed to a non-default value, the range for off-

set calibration will be scaled accordingly.

The same offset value is used independent of phase angle.

However, as default (OFFMOD=0), the sign of power is

taken into account in the c al culations so tha t pos i tiv e of fse t

factor will always increase the absolute power value and

negative coefficient will decrease absolute results. This

guaran tees that curr ent sens or non-l inear ity i s co rre cted in

the same way even though the current flow is reversed.

It is pos sible to ch ange this d efault conditi on by pro gram-

ming value one to O FFMOD coe ffici ent. In th is cas e, offset

coefficient will be always added to power result without

checking the sign of the power. Positive coefficient will

incr ease the absol ute value of posi tive power r esults and

decrease the absolute value of negative result.

Phase Calibration

The phas e dif ferenc e be twee n vol tag e and curr ent chan nel

is compen sated with three 8-bi t phase ca libration figur es.

The dis placement is usua lly due to the ph ase shi ft in cur-

rent transformers. Based on the calibration values, th e

DSP interpolates new current samples with sample instants

coinciding with the corresponding voltage samples. The fol-

lowing formula is used to determine the phase of fset to be

used in the interpolation. One 8-bit phase calibration value

is stored for each of the three phases.

where PON is the sample phase offset of channel N, mea-

sured as phase(U) - phase (I). The allowed range for phase

calibr ati on fact or, PC N, is -128 to +127.

Starting Current Adjustment

The meter IC is designed to fulfill IEC 1036, class 1 specifi-

cation. This specification is based on a certain basic cur-

rent, Ib. As a default, AT73C500 o perat es with 5A basic

current. The chipset has a preprogra mmed star ting curre nt

level of

where IFS is the full scale current of the m eter, i.e. 80A i n

nominal conditions. The default startup current corre-

sponds to 0.4% of the 5A Ib, assuming that the full-scale

range is 80A. Wh en the phas e current is below the startin g

level, the calculated cyc le power resu lts are replaced by

zeros and no energy is accumulated.

It is possible to adjust the start-up level in the range of 0.2

to 10 compared with the nominal va lue. This is performed

with a special c alibration factor. The following formula is

used to determine the current:

where STUPC is the starting current calibration factor,

allowed to vary in rang e -4 to +45, onl y. Care should b e

taken that the ST UPC is correctly programmed and is not

beyond -4 to 45 range. Also, it should be noted that low

starting thresholds may force the device to a level where

accuracy is restricted due to a finite resolution of converters

and mathematics.

Adjustment of Display Pulse Rate

An 8-b it by te is pr ovid ed for a dju stmen t of the impu lse r ate

of display pulses. This coefficient will only affect the display

pulse rate of active and reactive energy but not to the meter

constant rate. The content of all measurement registers will

remain unc han ged .

The impu lse rate can be s caled in the rang e of 1 t o 6 com-

pared to the nominal value. In default conditions (Umax =

270V, Imax = 80A) the LS B of e nergy r egister s REG1 2-15

(See “Status I nformation” on page 17.) corresponds to

0.4Wh. This means that accumulated 25 LSBs of energy

will generate o ne pulse to the displa y pulse output (25 x

0.4Wh/impulse = 10 Wh/impulse = 100 impulses/kWh).

By using MCC calibration coefficient, the nom inal figur e 25

can be chang ed in the ran ge of 25 to 152 . MCC may range

from 0 to 12 7, on ly . The followi ng f ormul as ar e used to cal-

culate the impulse rate.

and

PFS 270V 80A×21.6kW==

QFS 270V 80A×21.6VAr==

PONPCN

128

------------5.625°×=

ISU 1

4000

-------------IFS

×=

ISU 1

4000

-------------IFS (1 0.2 STUPC)×+××=

IMP (25 MCC) ELSB

×+=

PR 1000

(25 MCC) ELSB

×+

--------------------------------------------------=

AT73C500

where ELSB is the energy value of one LSB in the energy

regist er, 0.4Wh in default con ditions. W hen the mete r is

operated in non-standard conditions, the energy LSB may

be recalc ul ated as:

where f is the clock frequency used, and UFS and IFS are

the full-scale values of voltage and current.

In case the mete r is used with a non-de faul t vo ltag e div ider

or curre nt sensor , MCC fac tor is a c onve nient way to read-

just the imp uls e ra te.

Example

The mete r is to be c onfigured for u se in 120V networks,

with a max imum line voltage of 14 0V. The dis play pulse

rate is required to remain at 100imp/kWh. To start off, the

front end of the meter must be configured for the new line

voltage. The voltage dividers must be configured to pro-

duce an input signal of 0.707V at the input of the ADC at

maximum line voltage. At nominal meter settings, the volt-

age divider ratio is 270V:0.707V, in this case it must b e

140V:0.707V.

Note that a djustin g the lin e vo ltage of the meter w ill rend er

the formatting of most calculation registers to alternative

settings. For example, the meter constant pulse rate will

change as follows:

In our case of a m eter for 1 20V netw orks, th e new met er

constant pulse rate would be:

To make the m ete r constant pu lse r ate to a n ev en n umb er ,

for exam ple 2500, we m ay choose to either re-scale th e

line voltage or scale the maximum line current. 2500

impulses per kilowatt hour is gained by either setting the

maximum line voltage to:

or by retaining the line voltage at 140V and scaling the

maximum line current to:

Regardless of which parameter (or both) is chosen, the

scaling pr ocess is a simple matte r of gain cali brati on. If, for

example, the line voltage is chosen to be rescaled to 135V,

this is realized with a resistor divider of half the nominal,

and finetuning using the voltage gain coefficients. Also, all

values resulting from voltage calculation, such as the data

transfe rred vi a energy regist ers, s houl d be nor malize d with

respect to the new voltage setting.

Going back to the calibration of the display pulse rate, the

new LSB value of energy registers is:

To mainta in the displ ay pulse ra te at 100 , the MCC c alibr a-

tion coefficient must be programmed as:

The ene rgy va lue of ea ch disp lay coun ter i mpuls e is ther e-

after:

In mode 7, the default display pulse rate is 10

impulses/kWh(kVArh) instead of 100 impulses/kWh. This is

convenient for meters where only one decimal digit wants

to be shown. This default rate can al so calibrated and the

calibrati on for mu las are:

and

Master Clock

The master clock of AT73C500 is generated by a crystal

oscillator with crystal connected between pins XI and XO of

AT73C5 01/AT7 3C502 . Mas ter c lock c an also be f ed to the

XI input from a separate clock source. The sys tem clock

rate of AT73C500 is the same as the clock of

AT73C501/AT73C502 and is fed to the CLK input of the

device from the CLK output of AT73C501/AT73C502.

ELSB 3.2768MHz

------------------------------ UFS IFS

270V 80A×

-------------------------------0.4Wh

××=

MC 270V 80A

UFS IFS

-------------------------------f

3.2768MHz

------------------------------ 1250 imp

kWh

------------

××=

MC 270V

140V

--------------1250 imp

kWh

------------

×2410.714…imp

kWh

------------

UFS 270V

2500 imp

kWh

------------

------------------------- 1250 imp

kWh

------------

×135V==

IFS 270V 80A×

140V 2500 imp

kWh

------------

----------------------------------------------1250 imp

kWh

------------

×77.143…A==

ELSB 140V

270V

--------------0.4Wh

×0.20741…Wh==

MCC 1000

PR ELSB

------------------------------25–1000

100 imp

kWh

------------0.20741Wh

----------------------------------------------------------- 25–23.216…23≈== =

IMP (25 23) 1

imp

--------- 140V

270V

--------------0.4Wh 10.0Wh

imp

---------

≈××+=

IMP (250 MCC) ELSB

×+=

PR 1000

(250 MCC) ELSB

×+

-----------------------------------------------------=

AT73C500

Electrical Characteristics Measurement Accuracy

The accurac y measurements are based on the usage of

the AT73C500 DSP with the single-ended ADC,

AT73C501. Using the differential-ended ADC, AT73C502,

improves some of the results.

Input Conditions

When specifying measurement accuracy, it is assumed

that 80ARMS phase current will produce 2VPP full scal e inpu t

voltage to current converters. The basic current, IB, is sup-

posed to be 5ARMS.

The nomi nal phase vo ltage, U N, is sp ecified to be 230VRMS

and 2VPP full scale input is produced by 270VRMS.

Overall Accuracy, Active and Reactive Power and

Energy Measurement

Overall accuracy including errors caused by A/D-conver-

sion of cu rren t and voltag e sign als, c alibrati on and c alcul a-

tions.

The accur acy figures are measu red in nom inal conditions

unless otherwise indicated in the parameter field of the

table below.

Absolute Maximum Ratings

Parameter Min Typ Max Unit

Supply Voltage VCC,

VDA, VDDA 4.75 5.25 V

Input Voltage, Digital -0.3 VDD

+0.3 V

Input Voltage, Analog -0.3 VDA

+0.3 V

Input Voltage, CI and

VI inputs 1.25 3.75 V

Ambient Op erating

Temp. -25 +70 C

Storage Temperature -65 +150 C

Calibration Characteristics

Parameter Min Typ Max Units

Gain Calibr ation

Calibration Range ± 20 %

Calibration

Resolution 0.16 %

Phase Calibration

Calibration Range ±5.625 degree

Calibration

Resolution 0.044 degree

Offset Cali bration,

Active Power

Calibration Range 89.8 W

Calibration

Resolution 0.7015 W

Range,% of Full

Scale Phase Power 0.4157 %

Offset Cali bration,

Reactive Power

Calibration Range 98.7 VAr

Calibration

Resolution 0.7712 VAr

Range,% of Full

Scale Phase Power 0.457 %

Parameter Nominal Value

Nomin al vo ltag e, UN230V, ±1%

Full-scale voltage, UFS 270V

Full-scale current, IFS 80A

Base curr ent, IB5A

Frequency, f 50.0 Hz, ±0.3%

Power factor, PF 1

Harmonic contents of voltage less than 2%

Harmonic contents of current less than 20%

Te mperature, T 23°C, ±2°C

AT73C500 master clock 3.2768 MHz

AT73C500

The measurements are done according to IEC1036 specifi-

cation. The results are averaged over a period of 10s.

Before measurements, AT73C500 devices have been

operational for minimum 1h.

Effect of Crosstalk

The error caused by crosstalk from one current input to

other two current inputs wh en the met er is ca rrying a si n-

gle-phase load.

Influence Quantities

The additional error caused by different influence quanti-

ties.

Table 9. Measurement Bandwidth

Parameter Min Typ Max Units

General, 50 Hz line

frequency

- high limit (-3dB) 750 Hz

- low limit (-3dB) 30 Hz

Reactive Power and

Energy, Voltage and

Current Measurement

- high limit 360 Hz

- low limit 40 Hz

Line Frequency

- high limit 350 Hz

- low limit 20 Hz

Table 10. Maximum Error

Current Voltage Power

Factor Min Typ Max Units

0.05IBUN1.000 -0.4 +0.4 %

0.1IB...IFS UN1.000 -0.2 +0.2 %

0.1IBUN0.5

lagging -0.4 +0.4 %

0.2IB...IFS UN0.5

lagging -0.4 +0.4 %

0.1IBUN0.8

leading -0.4 +0.4 %

0.2IB...IFS UN0.8

leading -0.4 +0.4 %

0.2IB...IFS UN0.25

lagging -1.0 +1.0 %

Table 11. Single-phase Load Error

Current Voltage Power

Factor Min Typ Max Units

0.1IB...IFS UN1.000 -0.5 +0.5 %

0.1IB...IFS UN0.5

lagging -0.5 +0.5 %

Table 12. Voltage Variation Error

Current Voltage Power

Factor Min Typ Max Units

0.1IB0.9UN...

1.1UN1.000 -0.2 +0.2 %

0.1IB0.9UN...

1.1UN

0.5

lagging -0.2 +0.2 %

AT73C500

Table 13. Frequency Variation Error

Frequency Current Voltage Power Factor Min Typ Max Units

0.95fN...1.05fN0.1IBUN1.000 -0.2 +0.2 %

0.95fN...1.05fN0.1IBUN0.5 lagging -0.2 +0.2 %

0.8fN...5fN0.1IBUN1.000 -5.0 +0.5 %

0.8fN...5fN0.1IBUN0.5 lagging -5.0 +0.5 %

Table 14. Harmonic Distortion Error

Current Voltage Min Typ Max Units

40% of 5th harmonic in current 10% of 5th harmonic in voltage -0.5 +0.5 %

Table 15. Reversed Phase Sequence Error

Current Voltage Min Typ Max Units

0.1IBUN-0.3 +0.3 %

Table 16. Voltage Unbalance Error

Current Voltage Min Typ Max Units

0.1IBOne or two phases carry 0V -0.4 +0.4 %

Table 17. D C Compon ent in Curre nt Error

Current Voltage Min Typ Max Units

IDC = 0.1IFS UN-0.5 +0.5 %

AT73C500

Starting Current

As default, the starting current is based on 5A basic current

and 80A full scale current range.

Temperature Coefficient

Measured with the internal reference voltage source of

AT73C501/AT73C502.

Other Parameters

The ac curacy of the fol lowing p arameter s is meas ured in

the conditions below unless otherwise indicated in the

parameter field of the table. The measurement error has

been calculated based on values averaged over 1min

period.

The accuracy of Power Factor measurements was tested

with PF values 0.5, -0.5, -1 and 1.

Table 18. S tar ting Cur rent

Voltage Min Typ Max Units

UN0.004 IB

Table 19. Mean Temperature Coefficient

Current Voltage Power

Factor Min Typ Max Units

0.1IB...IFS UN1.000 0.02 0.04 %/K

0.1IB...IFS UN0.5

lagging 0.02 0.04 %/K

Parameter Nominal Value

Nominal voltag e, UN230V, ±1%

Full-scale voltage, UFS 270V

Full-scale current, IFS 80A

Base cu rr ent , IB5A

Frequency, f 50.0 Hz, ±0.3%

Power factor, PF 1

Harmonic contents of voltage 0%

Harmonic contents of current 0%

Te mperature, T 23C, ±2°C

AT73C500 master clock 3.2768 MHz

Table 20. Apparent Power and Energy Error

Current Min Typ Max Units

0.05IFS...IFS -0.5 +0.5 %

0.005IFS...0.05IFS -2.0 +2.0 %

0.001IFS...0.005IFS -5.0 +5.0 %

Table 21. Power Factor Error

Current Min Typ Max Units

0.05IFS...IFS -0.5 +0.5 %

0.005IFS...0.05IFS -2.5 +2.5 %

Table 22. Phase Volt age Error

Voltage Min Typ Max Units

0.2UFS...UFS -0.5 +0.5 %

Table 23. Phase Current Error

Current Min Typ Max Units

0.05IFS...IFS -0.5 +0.5 %

0.005IFS...0.05IFS -2.5 +2.5 %

Table 24. Frequency Error

Frequency Min Typ Max Units

40 Hz...100 Hz -0.5 +0.5 %

Parameter Nominal Value

AT73C500

Digital Characteristics

VDD = 5V, VDA = 5V

Parameter Min Typ Max Units

High-Level Input Voltage 4.0 V

Low-Level Input Voltage 1.0 V

High-Level Output Voltage, ISOURCE = -100 µA 4.0 V

Low-Level Output Voltag e, ISINK = 0.5 mA 0.4 V

Input Leakage Current -10 10 µA

Crystal Oscillator

Parameter Min Typ Max Units

Crystal Frequency 1.0 6.0 MHz

Crystal Inaccuracy 30 ppm

Crystal Temp Coefficient (-25°C to +70°C) 30 ppm/C

AC Parameters

Parameter Min Typ Max Units

Master Clock Frequency 1.0 6.0 MHz

Clock Duty Cycle at XI pin 40 60 %

Timing of 8- bit Bus

Parameter Parameter Min Typ Max Units

DDLY Data Dela y from Fal ling Edge of STROBE 25 ns

DH Data Hold Time From Rising Edge of STROBE 5 ns

SDLY Str obe Delay from F alling Edge of Cl ock 0 20 ns

SH Strobe Hold Time From Rising Edge of Clock 3 20 ns

ASU Addr Setup Time to Rising Edge of STROBE 10 ns

AH Addr Hold Time From Rising Edge of STROBE 3 ns

RWSU RD/WR Setup to Rising Edge of STROBE 10 ns

RWH RD/WR Hold from Rising Edge of STROBE 3 ns

BRS BRDY Set-Up Time to Rising Edge of Clock 40 ns

Power Supply Characteristics

Parameter Parameter Min Typ Max Units

VDD, VDA Supply Voltage 4.75 5.25 V

IDD (AT73C501/AT73C502 + AT73C500) Supply Current 15 22 mA

IDA (ADC) Supply Current 10 15 mA

AGND Analog Ground Voltage 2.45 2.5 2.55 V

VREF-AGND Reference Voltage 1.17 1.27 1.37 V

AT73C500

Ordering Information

Ordering Code Package Operation Range

AT73C500-JC 44J Commercial

(0°C to 70°C)

AT73C501-JC 28J Commercial

(0°C to 70°C)

AT73C502-QC 44Q Commercial

(0°C to 70°C)

Package Type

28J 28-lead, Plastic J-leaded Chip Carrier (PLCC)

44J 44-lead, Plastic J-leaded Chip Carrier (PLCC)

44Q 44-lead, Plastic Gull Wing Quad Flat Package

AT73C500

Packaging Informati on

.045(1.14) X 45°PIN NO. 1

IDENTIFY

.032(.813)

.026(.660)

.050(1.27) TYP .300(7.62) REF SQ

.045(1.14) X 30° - 45°

.022(.559) X 45° MAX (3X)

.012(.305)

.008(.203)

.021(.533)

.013(.330)

.430(10.9)

.390(9.91)SQ

.043(1.09)

.020(.508)

.120(3.05)

.090(2.29)

.180(4.57)

.165(4.19)

.456(11.6)

.450(11.4)

.495(12.6)

.485(12.3)

.045(1.14) X 45°PIN NO. 1

IDENTIFY .045(1.14) X 30° - 45°.012(.305)

.008(.203)

.021(.533)

.013(.330)

.630(16.0)

.590(15.0)

.043(1.09)

.020(.508)

.120(3.05)

.090(2.29)

.180(4.57)

.165(4.19)

.500(12.7) REF SQ

.032(.813)

.026(.660)

.050(1.27) TYP

.022(.559) X 45° MAX (3X)

.656(16.7)

.650(16.5)

.695(17.7)

.685(17.4)SQ

*Controlling dimension: millimeters

13.45 (0.525)

12.95 (0.506)

0.50 (0.020)

0.35 (0.014)

PIN 1 ID

0.80 (0.031) BSC

10.10 (0.394)

9.90 (0.386) SQ

0.17 (0.007)

0.13 (0.005)

1.03 (0.041)

0.78 (0.030)

2.45 (0.096) MAX

0.25 (0.010) MAX

28J, 28-lead, Plastic J-leaded Chip Carrier (PLCC)

Dimensions in Inches and (Millimeters)

JEDEC STAND ARD MS -018 AB

44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)

Dimensions in Inches and (Millimeters)

JEDEC STAN DARD MS -018 AC

44Q, 44-lead, Plastic Quad Flat Package (PQFP)

Dimensions in Millimeters and (Inches)*

JEDEC STAND ARD MS -022 AB

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-

ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for

any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without

notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop-

erty of Atmel are grant ed by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are

not authorized for use as critical components in life support devices or systems.

Marks bearing ® and/or ™ are re giste red t radem arks a nd tr adem arks of Atm el Co rpora tion.

Terms and product names in this document may be trademarks of others.

Atmel Headquarters Atmel Operations

Corporate Headquarters

2325 Orchard Parkway

San Jose, CA 95131

TEL (408) 441- 0311

FAX (408) 487-2600

Europe

Atmel U.K., Ltd.

Coliseum Business Centre

Riverside Way

Camberley, Surrey GU15 3YL

England

TEL (44) 1276-686-677

FAX (44) 1276-686-697

Asia

Atmel Asia, Ltd.

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimhatsui

East Kowloon

Hong Kong

TEL (852) 2721 -9778

FAX (852) 2722-1369

Japan

Atmel Japan K.K.

9F, Tonetsu Shinkawa Bldg.

1-24 -8 Shinka wa

Chuo-ku, Tokyo 104-0033

Japan

TEL (81) 3-3523-3551

FAX (81) 3-3523-7581

Atmel Colorado Springs

1150 E. Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TEL (719) 576-3300

FAX (719) 540-1759

Atmel Rousset

Zone Indu strie lle

13106 Rousset Cedex

France

TEL (33) 4-4253-6000

FAX (33) 4-4253-6001

Fax-on-Demand

North America:

1-(800) 292-8635

International:

1-(408) 441-0732

e-mail

literature@atmel.com

Web Site

http://www.atmel.com

BBS

1-(408) 436-4309

Printed on recycled paper.

1035B–09/99/xM