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confirm that this is the latest version.
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BIPOLAR ANALOG INTEGRATED CIRCUIT
μ
PC1251GR-9LG, 358GR-9LG
LOW POWER DUAL OPERATIONAL AMPLIFIERS
PRELIMINARY DATA SHEET
Document No. G17929EJ2V0DS00 (2nd edition)
Date Published November 2006 NS CP(N)
Printed in Japan
2006
DESCRIPTION
The
μ
PC1251GR-9LG, 358GR-9LG are dual operational amplifiers which are designed to operate from a single
power supply over a wide range of voltages. Operation from split power supplies is also possible and the power
supply current drain is very low. Further advantage, the input commonmode voltage range includes ground in the
linear mode.
FEATURES
Internally frequency compensation
Wide output voltage swing V to V+ 1.5 V
Common mode input voltage range includes V
Wide supply voltage range
3 V to 30 V (Single)
±1.5 V to ±15 V (Split)
Output short circuit protection
ORDERING INFORMATION
Part Number Package
μ
PC1251GR-9LG-A 8-pin plastic TSSOP (5.72 mm (225))
μ
PC1251GR(5)-9LG-A 8-pin plastic TSSOP (5.72 mm (225))
μ
PC358GR-9LG-A 8-pin plastic TSSOP (5.72 mm (225))
μ
PC358GR(5)-9LG-A 8-pin plastic TSSOP (5.72 mm (225))
PIN CONFIGURATION (Marking Side)
OUT1
II1
IN1
V
V+
OUT2
II2
IN2
1
2
3
4
8
7
6
5
+1
+ 2
EQUIVALENT CIRCUIT (1/2 Circuit)
V+
V
OUT
Q
6
Q
5
Q
7
Q
13
Q
12
Q
11
Q
10
Q
9
Q
8
Q
4
Q
3
Q
2
Q
1
C
C
I
I
I
N
R
SC
6 A
μ
6 A
μ
100 A
μ
50 A
μ
Preliminary Data Sheet G17929EJ2V0DS
2
μ
PC1251GR-9LG, 358GR-9LG
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Parameter Symbol
μ
PC1251GR-9LG
μ
PC358GR-9LG Unit
Voltage between V+ and V Note 1 V
+ V 0.3 to +32 V
Differential Input Voltage VID ±32 V
Input Voltage Note 2 VI V
0.3 to V + 32 V
Output Voltage Note 3 VO V
0.3 to V+ + 0.3 V
Power Dissipation Note 4 PT 440 mW
Output Short Circuit Duration Note 5 Indefinite s
Operating Ambient Temperature TA 40 to +125 40 to +85 °C
Storage Temperature Tstg 55 to +150 55 to +125 °C
Notes 1. Reverse connection of supply voltage can cause destruction.
2. The input voltage should be allowed to input without damage or destruction independent of the magnitude of
V+. Either input signal should not be allowed to go negative by more than 0.3 V. The normal operation will
establish when the both inputs are within the Common Mode Input Voltage Range of electrical
characteristics.
3. This specification is the voltage which should be allowed to supply to the output terminal from external
without damage or destructive. Even during the transition period of supply voltage, power on/off etc., this
specification should be kept. The output voltage of normal operation will be the Output Voltage Swing of
electrical characteristics.
4. The thermal deleting factor of these IC are same value as 5.5mW/°C, but the delete beginning temperature
in different as follows.
μ
PC1251GR-9LG : 69°C
μ
PC358GR-9LG : 44°C
The calculated junction to ambient thermal resistance at above conditions is 183°C/W.
5. Pay careful attention to the total power dissipation not to exceed the absolute maximum ratings, Note 4.
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol MIN. TYP. MAX. Unit
Supply Voltage (Split) V± ±1.5 ±15 V
Supply Voltage (V = GND) V+ +3 +30 V
Preliminary Data Sheet G17929EJ2V0DS 3
μ
PC1251GR-9LG, 358GR-9LG
μ
PC1251GR-9LG,
μ
PC358GR-9LG
ELECTRICAL CHARACTERISTICS (TA = 25 °C, V+ = +5 V, V = GND)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input Offset Voltage VIO RS = 0 Ω ±2 ±7 mV
Input Offset Current IIO ±5 ±50 nA
Input Bias Current Note 6 IB 45 250 nA
Large Signal Voltage Gain AV RL 2 kΩ 25 100 V/mA
Supply Current Note 7 ICC RL = , IO = 0 A 0.7 1.2 mA
Common Mode Rejection Ratio CMR 65 70 dB
Supply Voltage Rejection Ratio SVR 65 100 dB
Output Voltage Swing VO RL = 2 kΩ (Connect to GND) 0 V+ 1.5 V
Common Mode Input Voltage Range VICM 0 V+ 1.5 V
Output Current (SOURCE) IO SOURCE VIN+ = +1 V, VIN = 0 V 20 40 mA
VIN = +1 V, VIN+ = 0 V 10 20 mA Output Current (SINK) IO SINK
VIN = +1 V, VIN+ = 0 V,
VO = 200 mV
12 50
μ
A
Channel Separation f = 1 kHz to 20 kHz 120 dB
Notes 6. Input bias currents flow out from IC. Because each currents are base current of PNP-transistor on input
stage.
7. This current flows irrespective of the existence of use.
μ
PC1251GR(5)-9LG,
μ
PC358GR(5)-9LG
ELECTRICAL CHARACTERISTICS (TA = 25 °C, V+ = +5 V, V = GND)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input Offset Voltage VIO RS = 0 Ω ±2 ±3 mV
Input Offset Current IIO ±5 ±50 nA
Input Bias Current Note 6 IB 45 60 nA
Large Signal Voltage Gain AV RL 2 kΩ 50 100 V/mA
Supply Current Note 7 ICC RL = , IO = 0 A 0.7 0.9 mA
Common Mode Rejection Ratio CMR 65 70 dB
Supply Voltage Rejection Ratio SVR 65 100 dB
Output Voltage Swing VO RL = 2 kΩ (Connect to GND) 0 V+ 1.5 V
Common Mode Input Voltage Range VICM 0 V+ 1.4 V
Output Current (SOURCE) IO SOURCE VIN+ = +1 V, VIN = 0 V 30 40 mA
VIN = +1 V, VIN+ = 0 V 15 20 mA Output Current (SINK) IO SINK
VIN = +1 V, VIN+ = 0 V,
VO = 200 mV
30 50
μ
A
Channel Separation f = 1 kHz to 20 kHz 120 dB
Notes 6. Input bias currents flow out from IC. Because each currents are base current of PNP-transistor on input
stage.
7. This current flows irrespective of the existence of use.
Preliminary Data Sheet G17929EJ2V0DS
4
μ
PC1251GR-9LG, 358GR-9LG
PACKAGE DRAWING
S
y
e
Sxb M
θ
L
c
Lp
D
HE
ZD
A1
A2
A
D1
E
A3
S
0.145±0.055
(UNIT:mm)
ITEM DIMENSIONS
D
D1
E
HE
A
A1
A2
A3
3.15±0.15
3.00±0.10
4.40±0.10
6.40±0.20
1.20 MAX.
0.10±0.05
1.00±0.05
0.25
c
θ
e
x
y
ZD
0.65
0.10
0.10
0.60
L
Lp
L1
0.50
0.60±0.15
1.00±0.20
P8GR-65-9LG
3°+5°
3°
NOTE
Each lead centerline is located within 0.10mm of
its true position at maximum material condition.
detail of lead end
8-PIN PLASTIC TSSOP (5.72mm (225))
0.24
b
4
5
1
8
L1
+0.06
0.05
Preliminary Data Sheet G17929EJ2V0DS 5
μ
PC1251GR-9LG, 358GR-9LG
RECOMMENDED SOLDERING CONDITIONS
The
μ
PC1251GR-9LG, 358GR-9LG should be soldered and mounted under the following recommended conditions.
For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales
representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Type of Surface Mount Device
Process Conditions Symbol
Infrared ray reflow Peak temperature: 260 °C or below (Package surface temperature),
Reflow time: 60 seconds or less (at 220 °C or higher),
Maximum number of reflow processes: 3 time.
IR60-00-3
Wave soldering Solder temperature: 260 °C or below, Flow time: 10 seconds or less,
Maximum number of flow processes: 1 time,
Pre-heating temperature: 120 °C or below (Package surface temperature).
WS60-00-1
Partial heating method Pin temperature: 350 °C or below,
Heat time: 3 seconds or less (Per each side of the device).
P350
Caution Apply only one kind of soldering condition to a device, except for “partial heating method”, or the
device will be damaged by heat stress.
REFERENCE DOCUMENTS
Document Name Document No.
QUALITY GRADES ON NEC SEMICONDUCTOR DEVICES C11531E
SEMICONDUCTOR DEVICE MOUNT MANUAL http://www.necel.com/pkg/en/mount/index.html
NEC SEMICONDUCTOR DEVICE RELIABILITY/QUALITY CONTROL SYSTEM
- STANDARD LINEAR IC
IEI-1212
μ
PC1251GR-9LG, 358GR-9LG
The information in this document is current as of November, 2006. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
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