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PI6C49004
Networking Clock Generator
Block Diagram
Features
• 3.3V+/-10%SupplyVoltage
• Uses25MHzxtalsuchasSaronix-eCera™SRX7278
• TwelvePCIe®100MHzoutputswithoptional-0.5%spread
spectrumsupport
• TwoLVCMOS50MHzoutputsthatsupport+/-10%
frequencymargining
• Onefrequencyselectable33/66/133MHzLVCMOSoutput
• One32.256MHzLVCMOSoutput
• Industrialtemperature-40°Cto85°C
• Package:56-pinTSSOPpackage
Description
ThePI6C49004isaclockgeneratordeviceintendedforPCIe®/
networking applications. The device includes twelve 100MHz
differential Host Clock Signal Level (HCSL) outputs for PCIe,
twosingle-ended50MHzoutputs,onesingle-ended32.256MHz
output,andoneselectablesingle-ended33/66/133MHzoutput.
UsingaseriallyprogrammableSMBUSinterface,thePI6C49004
incorporatesspreadspectrummodulationonthetwelve100MHz
HCSLPCIeoutputs,andindependentfrequencymarginingonthe
50MHzoutput,33.3333MHzand66.6666MHzclockoutputs.
Pin Conguration
VDD
12
12
100M_OUT(0-11)
50M_OUT(1-2)
33/66/133M_OUT1
32.256M_OUT1
ISET
475 Ohms
1%
GND
8
PD_RESET
SDATA
SCLK
PLL, Dividers,
Buffers, and
Logic
Clock Buffer/
Crystal
Oscillator
25 MHz
crystal or
clock input
2
VDD
IREF
NC
100M_Q11-
100M_Q11+
100M_Q10-
100M_Q10+
VDD
VDD
GND
100M_Q9-
100M_Q9+
100M_Q8-
100M_Q8+
100M_Q7-
100M_Q7+
SCLK
SDATA
GND
50M_OUT1
50M_OUT2
VDD
GND
VDD
32.256M_OUT1
GND
NC
PD_RESET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
VDD
100M_Q0-
100M_Q0+
100M_Q1+
100M_Q1-
VDD
GND
VDD
100M_Q2+
100M_Q2-
100M_Q3+
100M_Q3-
100M_Q4+
100M_Q4-
100M_Q5+
100M_Q5-
VDD
GND
VDD
100M_Q6+
100M_Q6-
33/66/133M_OUT1
VDD
GND
VDD
X2
X1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
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PI6C49004
Networking Clock Generator
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Pin Description
Pin # Pin Name Pin Type Pin Description
1 VDD Power 3.3VSupplyPin
2 IREF Output Connectto475-OhmresistortosetHCSLoutputdrivecurrent
3NC Noconnect.Leaveopen
4 100M_Q11- Output 100MHzHCSLoutput
5 100M_Q11+ Output 100MHzHCSLoutput
6 100M_Q10- Output 100MHzHCSLoutput
7 100M_Q10+ Output 100MHzHCSLoutput
8VDD Power 3.3VSupplyPin
9VDD Power 3.3VSupplyPin
10 GND Power Ground
11 100M_Q9- Output 100MHzHCSLoutput
12 100M_Q9+ Output 100MHzHCSLoutput
13 100M_Q8- Output 100MHzHCSLoutput
14 100M_Q8+ Output 100MHzHCSLoutput
15 100M_Q7- Output 100MHzHCSLoutput
16 100M_Q7+ Output 100MHzHCSLoutput
17 SCLK Input SMBuscompatibleinputclock.Supportsfastmode400kHzinputclock.
18 SDATA I/O SMBuscompatibledataline
19 GND Power Ground
20 50M_Out1 Output 50MHzLVCMOSoutput.Whendisabled,outputistrisatedandhasanominal110k-
Ohmpull-down.
21 50M_Out2 Output 50MHzLVCMOSoutput.Whendisabled,outputistrisatedandhasanominal
110kOhmpull-down.
22 VDD Power 3.3VSupplyPin
23 GND Power Ground
24 VDD Power 3.3VSupplyPin
25 32.256M_Out1 Output 32.256MHzLVCMOSoutput.Whendisabled,outputistrisatedandhasanominal
110k-Ohmpull-down.
26 GND Power GND
27 NC Noconnect.Leaveopen
28 PD_RESET Input Powerdownreset-whenlowallPLL'sarepowereddownandoutputstristated.
SMBusregistersareresettodefaultvalues.
29 X1 Input Crystalinput.Integrated6pFcapacitance
30 X2 Output Crystaloutput.Integrated6pFcapacitance
31 VDD Power 3.3VSupplyPin
32 GND Power GND
33 VDD Power Connectto3.3V
14-0199
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PI6C49004
Networking Clock Generator
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Pin # Pin Name Pin Type Pin Description
34 33/66/133M_Out1 Output 33/66/133MHzselectableLVCMOSoutput.Whendisabled,outputistrisatedandhas
anominal110k-Ohmpull-down.
35 100M_Q6- Output 100MHzHCSLoutput
36 100M_Q6+ Output 100MHzHCSLoutput
37 VDD Power 3.3VSupplyPin
38 GND Power Ground
39 VDD Power 3.3VSupplyPin
40 100M_Q5- Output 100MHzHCSLoutput
41 100M_Q5+ Output 100MHzHCSLoutput
42 100M_Q4- Output 100MHzHCSLoutput
43 100M_Q4+ Output 100MHzHCSLoutput
44 100M_Q3- Output 100MHzHCSLoutput
45 100M_Q3+ Output 100MHzHCSLoutput
46 100M_Q2- Output 100MHzHCSLoutput
47 100M_Q2+ Output 100MHzHCSLoutput
48 VDD Power 3.3VSupplyPin
49 GND Power Ground
50 VDD Power 3.3VSupplyPin
51 100M_Q1- Output 100MHzHCSLoutput
52 100M_Q1+ Output 100MHzHCSLoutput
53 100M_Q0- Output 100MHzHCSLoutput
54 100M_Q0+ Output 100MHzHCSLoutput
55 VDD Power 3.3VSupplyPin
56 GND Power Ground
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PI6C49004
Networking Clock Generator
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33/66/133 MHz Frequency Margining Table
FS6 FS5 FS4 33M/66M/133M_OUT1
0 0 0 33.3333MHz
0 0 166.6666MHz+2%
010 66.6666MHz+1%
01 1 66.6666MHz+0%
10 0 66.6666MHz-2%
10166.6666MHz-4%
1 1 0 66.6666MHz-6%
1 1 1 133.3333MHz
50MHz Frequency Margining Table
FS3 FS2 FS1 FS0 50M_OUT1,50M_OUT2
0 0 0 0 nominal
0 0 0 1nominal+1%
0 0 10 nominal+2%
0 0 1 1 nominal+3%
010 0 nominal+4%
0101nominal+5%
01 1 0 nominal+6%
01 1 1 nominal+8%
10 0 0 nominal+10%
10 0 1nominal-1%
1010 nominal-2%
101 1 nominal-3%
1 1 0 0 nominal-4%
1 1 01nominal-6%
1 1 1 0 nominal-8%
1 1 1 1 nominal-10%
14-0199
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PI6C49004
Networking Clock Generator
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Serial Data Interface (SMBus)
PI6C49004isaslaveonlySMBusdevicethatsupportsindexedblockreadandindexedblockwriteprotocolusingasingle7-bitad-
dressandread/writebitasshownbelow.
Address Assignment
A6 A5 A4 A3 A2 A1 A0 W/R
1 1 0 1 0 0 1 0/1
How to Write
1 bit 8 bits 1 8 bits 1 8 bits 1 8 bits 1 8 bits 1 1 bit
Start
bit D2H Ack Register
offset Ack Byte
Count = N Ack Data Byte
0Ack … Data Byte
N - 1 Ack Stop
bit
Note:
1.Registeroffsetforindicatingthestartingregisterforindexedblockwriteandindexedblockread.ByteCountinwritemodecannotbe0.
Byte 0: Spread Spectrum Control Register
Bit Description Type Power Up
Condition
Output(s)
Affected Notes
7SpreadSpectrumSelectionfor100MHzHCSL
PCI-Expressclocks RW 0All100MHzHCSL
PCIExpressoutputs
0=spreadoff
1=-0.5%down
spread
6EnableshardwareorsoftwarecontrolofOEbits
(seeByte0–Bit6andBit5Functionalitytable) RW 0PD_RESETpin,
bit5
0=hardwarecntl
1=softwarectrl
5
SoftwarePD_RESETbit.Enablesordisablesall
outputs
(seeByte0–Bit6andBit5Functionalitytable)
RW 1Alloutputs 0=disabled
1=enabled
4 FrequencymarginingselectbitFS3 RW 1
50M_Out1and
50M_Out2
See50MHzFrequen-
cyMarginingTable
onPage3
3FrequencymarginingselectbitFS2 RW 0
2 FrequencymarginingselectbitFS1 RW 1
1FrequencymarginingselectbitFS0 RW 0
0 OEforsingle-ended50MHzoutput50M_Out2 RW 1
Single-ended
50MHzoutput
50M_Out2
0=disabled
1=enabled
How to Read (M:abbreviationforMasterorController;S:abbreviationforslave/clock)
1 bit 8 bits 1 bit 8 bits 1 bit 1 bit 8 bits 1 bit 8 bits 1 bit 8 bits 1 bit … 8 bits 1 bit 1 bit
M:
Start
bit
M:
Send
"D2h"
S:
sends
Ack
M:send
starting
databyte
location:
N
S:
sends
Ack
M:
Start
bit
M:
Send
"D3h"
S:
sends
Ack
S:
sends
#of
data
bytes
that
will
be
sent:
X
M:
sends
Ack
S:
sends
start-
ing
data
byte
N
M:
sends
Ack
…
S:
sends
data
byte
N+X-
1
M:
Not
Ac-
knowl-
edge
M:
Stop
bit
14-0199
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PI6C49004
Networking Clock Generator
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Byte 1: Control Register
Bit Description Type Power Up Condi-
tion Output(s) Affected Notes
7 OEfor32.256M_Out1 RW 132.256M_Out1 0=disabled
1=enabled
6 OEfor50M_Out1 RW 150M_Out1 0=disabled
1=enabled
5 OEfor33/66/133M_Out1 RW 133/66/133M_Out1 0=disabled
1=enabled
4 OEfor100M_Q11HCSLoutput RW 1100M_Q11 0=disabled
1=enabled
3 OEfor100M_Q10HCSLoutput RW 0 100M_Q10 0=disabled
1=enabled
2 OEfor100M_Q09HCSLoutput RW 0 100M_Q9 0=disabled
1=enabled
1OEfor100M_Q08HCSLoutput RW 0 100M_Q8 0=disabled
1=enabled
0 OEfor100M_Q07HCSLoutput RW 0 100M_Q7 0=disabled
1=enabled
Byte 2: Control Register
Bit Description Type Power Up Condi-
tion Output(s) Affected Notes
7 FrequencymarginingselectbitFS6 RW 1
33/66/133M_Out1
See33/66/133MHz
FrequencyMar-
giningTableon
Page3
6 FrequencymarginingselectbitFS5 RW 0
5 FrequencymarginingselectbitFS4 RW 0
4to0 Reserved R Undened NotApplicable
Byte 0 - Bit 6 and Bit 5 Functionality
Bit 6 Bit 5 Description
0 X PD_RESETHWpin/signal=enabled
10Disablesalloutputsandtri-statestheoutputs,PD_RESETHWpin/signal=DONOTCARE
1 1 Enablealloutputs,PD_RESETHWpin/signal=DON'TCARE
14-0199
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PI6C49004
Networking Clock Generator
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Byte 4 & 5: Control Register
Bit Description Type Power Up Condi-
tion Output(s) Affected Notes
7to0 Reserved R Undened NotApplicable
Byte 6: Control Register
Bit Description Type Power Up Condi-
tion Output(s) Affected Notes
7 RevivsionIDbit3 R 0 NotApplicable
6 RevivsionIDbit2 R 0 NotApplicable
5 RevivsionIDbit1 R 0 NotApplicable
4 RevivsionIDbit0 R 0 NotApplicable
3VendorIDbit3 R 0 NotApplicable
2 VendorIDbit2 R 0 NotApplicable
1VendorIDbit1 R 1NotApplicable
0 VendorIDbit0 R 1NotApplicable
Byte 3: Control Register
Bit Description Type Power Up Con-
dition Output(s) Affected Notes
7 OEfor100M_Q6HCSLOutput RW 0 100M_Q6 0=disabled
1=enabled
6 OEfor100M_Q5HCSLOutput RW 0 100M_Q5 0=disabled
1=enabled
5 OEfor100M_Q4HCSLOutput RW 0 100M_Q4 0=disabled
1=enabled
4 OEfor100M_Q3HCSLOutput RW 0 100M_Q3 0=disabled
1=enabled
3OEfor100M_Q2HCSLOutput RW 0 100M_Q2 0=disabled
1=enabled
2 OEfor100M_Q1HCSLOutput RW 1100M_Q1 0=disabled
1=enabled
1OEfor100M_Q0HCSLOutput RW 1100M_Q0 0=disabled
1=enabled
0 Reserved R Undened NotApplicable
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PI6C49004
Networking Clock Generator
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Absolute Maximum Ratings1 (Overoperatingfree-airtemperaturerange)
Symbol Parameters Min. Max. Units
VDD 3.3VI/OSupplyVoltage -0.5 4.6
VVIH InputHighVoltage 4.6
VIL InputLowVoltage -0.5
Ts StorageTemperature -65 150 °C
VESD ESDProtection 2000 V
Note:
1. Stressbeyondthoselistedunder“AbsoluteMaximumRatings”maycausepermanentdamagetothedevice.
MaximumSupplyVoltage,VDD............................................................ 7V
AllInputsandOutputs...............................................–0.5VtoVDD+0.5V
AmbientOperatingTemperature....................................... –40°Cto+85°C
StorageTemperature........................................................ –65°Cto+150°C
JunctionTemperature........................................................................125°C
PeakSolderingTemperature..............................................................260°C
Note:
StressesgreaterthanthoselistedunderMAXIMUMRAT-
INGSmaycausepermanentdamagetothedevice.Thisisa
stressratingonlyandfunctionaloperationofthedeviceat
theseoranyother conditions above thoseindicatedinthe
operationalsectionsofthisspecicationisnotimplied.Ex-
posuretoabsolutemaximumratingconditionsforextended
periodsmayaffectreliability.
Maximum Ratings
(Abovewhichusefullifemaybeimpaired.Foruserguidelines,nottested.)
DC Electrical Characteristics
Unlessotherwisespecied,VDD=3.3V±10%,AmbientTemperature–40°Cto+85°C
Symbol Parameter Conditions Min Typ Max Units
VDD OperatingSupplyVoltage 3.0 3.6
V
VIH InputHighVoltage 2 VDD
VIL InputLowVoltage –0.3 0.8
VIH InputHighVoltage SDATA,SCLK 0.7VDD VDD
VIL InputLowVoltage SDATA,SCLK 0.3VDD
IDD OperatingSupplyCurrent 320 mA
IDDatOutputDisableCondition PD_RESET=0 3.3
RPU/RPD InternalPull-Up/Pull-DownResistor PD_RESET 216 k–Ohm
Allsingle-endedoutputs 75
CIN InputCapacitance Allinputpins 6 pF
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PI6C49004
Networking Clock Generator
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Electrical Characteristics - Single-Ended
Unlessotherwisespecied,VDD=3.3V±10%,AmbientTemperature–40°Cto+85°C
Symbol Parameter Conditions Min Typ Max Units
FIN InputClockFrequency 25 MHz
SCLKFrequency 100 400 kHz
MinimumPulseWidthofPD_RESET
Input 100 ns
OutputFrequencyError FS0,FS6=0 0 ppm
OutputFrequencyError 32.256MHz 7
tr,tfOutputRise/FallTime VDD=3.3V,0.8Vto2.4V 0.5 1ns
OutputClockDutyCycle MeasuredatVDD/2 45 50 55 %
VOH High-LevelOutputVoltage IOH=-4mA VDD-0.4
VOH High-LevelOutputVoltage IOH=-8mA 2.4 V
VOL Low-LevelOutputVoltage IOL=8mA 0.4
Peak-to-PeakJitter
50MHzclockoutput 140 200
ps
33/66/133MHzclockoutput 125 175
32.256MHzclockoutput 115 150
Cycle-to-CycleJitter 50MHzclockoutput 120 175
33/66/133MHzclockoutput 120 160
ClockStabilizationTimefromPower
Up 310 ms
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Networking Clock Generator
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Electrical Characteristics - 100MHz Differential HCSL Outputs
Unlessotherwisespecied,VDD=3.3V±10%,AmbientTemperature–40°Cto+85°C
Symbol Parameter Conditions Min Typ Max Units
OutputFrequency 100 MHz
TCC/Jitter Cycle-to-CycleJitter 150
ps
Peak-to-PeakPhaseJitter UsingPCIejittermeasure-
mentmethod 86
SpreadModulationPercentage -0.5 0 %
SpreadModulationFrequency 32 kHz
TDC DutyCycle 45 50 55 %
Rising/FallingEdgeRate Note3,4 0.6 4.0 V/ns
TOSKEW OutputSkew VT=50%(measurement
threshold) 200 ps
ZC-DC ClockSourceDCImpedance,singleended 50 Ohm
VOH High-LevelOutputVoltage Note2,(RS=33-Ohm,
RT=50-Ohm) 0.65 0.71 0.85
V
VOL Low-LevelOutputVoltage –0.20 0 0.05
IOH IOH@6*IREF –13 –14.2 –17 mA
VCROSS AbsoluteCrossingPointVoltage Note2,5,6 0.25 0.55 V
VCROSSDelta VariationofVCROSSoverallrisingclock
edges Note2,5,8 140 mV
TPERIODAVG AverageClockPeriodAccuracy Note3,9,10 –300 2800 ppm
TPERIODABS AbsolutePeriod(includingjitterandspread
spectrum) Note3,7 9.847 10.203 ns
Notes:
1. Measuredattheendofan8-inchtracewitha5pFload.
2. Measurementtakenfromasingle-endedwaveform.
3. Measurementtakenfromadifferentialwaveform.
4. Measuredfrom-150mVto+150mVonthedifferentialwaveform.Thesignalismonotonicthroughthemeasurementregionforriseandfalltime.
The300mVmeasurementwindowiscenteredonthedifferentialzerocrossing.
5. Measuredatcrossingpointwheretheinstantaneousvoltagevalueoftherisingedgeof100M+equalsthefallingedge100M–.
6. Referstothetotalvariationfromthelowestcrossingpointtothehighest,regardlessofwhichedgeiscrossing.
Referstoallcrossingpointsforthismeasurement.
7. Denesastheabsoluteminimumormaximuminstantaneousperiod.Thisincludescycle-to-cyclejitter,relativePPMtolerance,
andspreadspectrummodulation.
8. Denedasthetotalvariationofallcrossingvoltagesofrising100M+andfalling100M–.
9. Refertosection4.3.2.1ofthePCIExpressBaseSpecication,Revision1.1forinformationregardingPPMconsiderations.
10. PPMreferstopartspermillionandisaDCabsoluteperiodaccuracyspecication.1PPMis1/1,000,000thof100MHzexactlyor100Hz.For300PPMthere
isanerrorbudgetof100Hz/PPM*300PPM=30kHz.Theperiodismeasuredwithafrequencycounterwithmeasurementwindowsetat100msorgreater.
Withspreadspectrumturnedofftheerrorislessthan±300ppm.Withspreadspectrumturnedonthereisanadditional+2500PPMnominalshiftinmaximum
periodresultingfromthe-0.5%downspread.
14-0199
11
PI6C49004
Networking Clock Generator
www.pericom.com 11/11/14 All trademarks are property of their respective owners.
Conguration test load board termination for HCSL Outputs
Rs
33Ω
5%
Rs
33Ω
5%
Rp
49.9Ω
1%
475Ω
1%
Rp
49.9Ω
1%
2pF
5%
2pF
5%
Clock#
Clock
TLA
TLB
PI6C49004
Figure4.CongurationTestLoadBoardTermination
14-0199
12
PI6C49004
Networking Clock Generator
www.pericom.com 11/11/14 All trademarks are property of their respective owners.
Ordering Information(1-3)
Ordering Code Package Code Package Description
PI6C49004AE A 56-pin,240-milwide(TSSOP)
Notes:
1.Thermalcharacteristicscanbefoundonthecompanywebsiteatwww.pericom.com/packaging/
2.E=Pb-freeandGreen
3.AddinganXsufx=Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
1
DESCRIPTION: 56-pin, 240-mil wide TSSOP
PACKAGE CODE: A56
DOCUMENT CONTROL #: PD-1502 REVISION: M
Notes:
1. Controlling dimensions in millimeters.
2. Ref: JEDEC MO-153F/EE
3. Package Outline Exclusive of Mold Flash and Metal Burr
DATE: 09/11/06
06-0736
Note:
• Forlatestpackageinfo,pleasecheck:http://www.pericom.com/products/packaging/mechanicals.php
Packaging Mechanical: 56-Contact TSSOP(A)
14-0199