DSP56F805/D
Rev. 6.0, 8/2001
Semiconductor Products Sector
© Motorola, Inc., 2001. All rights reserved.
DSP56F805
Preliminary Technical Data
DSP56F805 16 -bit Digital Signal Processor
• Up to 40 MIPS at 80 MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Hardware DO and REP loops
• MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipul at i on unit , 14 addr ess ing modes
•31.5K × 16-bit words Program Flash
• 512 × 16-bit words Program RAM
•4K × 16-bit words Data Flash
•2K × 16-bit words Data RAM
•2K × 16-bit words Boot Flash
• Up to 64K × 16-bit words each of external
program and data memory
• Two 6-channel PWM Modules
• Two 4-ch annel , 12- bi t ADCs
• Two Quadratu re Decoders
• CAN 2.0 B Module
• Two Serial Communication Interfaces (SCIs)
• Serial Peripheral Interface (SPI)
• Up to four General Purpose Quad Timers
•JTAG/OnCE
TM port for debugging
• 14 Dedicated and 18 Shared GPIO lines
• 144-pin LQFP Package
Figure 1. DSP56F805 Block Diagram
JTAG/
OnCE
Port
Digital Reg Analog Reg
Low Voltage
Supervisor
Program Controller
and
Hardware Looping Unit
Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Address
Generation
Unit
Bit
Manipulation
Uni t
PLL
Clock Gen
16-Bit
DSP56800
Core
PAB
PDB
XDB2
CGDB
XAB1
XAB2
XTAL
EXTAL
INTERRUPT
CONTROLS IPBB
CONTROLS
IPBus Bridge
(IPBB)
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
COP RESET
RESET
IRQAIRQB
Application-
Specific
Memory &
Peripherals
Interrupt
Controller
Program Memory
32252 x 16 Flash
512 x 16 SRAM
Boot Flash
2048 x 16 Flash
Data Memory
4096 x 16 Flash
2048 x 16 SRAM
COP/
Watchdog
SPI
or
GPIO
SCI0
or
GPIO
Quad Timer D
/ Alt Func
Quad Timer C
A/D1
A/D2 ADC
4
2
4
4
4
4
6PWM Outputs
Fault Inputs
PWMA
16 16
VCAPC VDD VSS VDDA VSSA
628 8
••
•
•
••••
EXTBOOT
Current Sense Inputs
3
Quadrature
Decode r 0 /
Quad A Timer
CAN 2.0A/B
2
CLKO
External
Address Bus
Switch
Bus
Control
External
Data Bus
Switch
External
Bus
Interface
Unit
RD Enable
WR Enable
DS Select
PS Select
10
16
6A[00:05]
D[00:15]
A[06:15] or
GPIO-E2:E3 &
GPIO-A0:A7
4
4
6PWM Outputs
Fault Inputs
PWMB
Current Sense Inputs
3
Quadrature
Decoder 1 /
Quad B Timer
4
2
SCI1
or
GPIO
2
Dedicated
GPIO
14
VPP
RSTO
VREF
2DSP56F805 Prel im i nary Tech nical Data
Part 1 O verview
1.1 DSP56F805 Features
1.1.1 Digital Signal Processi ng Core
• Efficient 16-bit DSP56800 family DSP engine with dual Harvard architecture
• As many as 40 Million Instructions Per Second (MIPS) at 80 MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Two 36-bit accumulators, including extension bits
• 16-bit bidirectiona l barrel shifter
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Three internal address buses and one external address bus
• Four internal data bus es and one external data bus
• Instructi on set supports both DSP and controller functions
• Controller style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by m emory
• JTAG/OnCE debug programming interfac e
1.1.2 Memory
• Harvard architecture per mits as many as three simul ta neous accesses to program and data memory
• On-chip memory including a low cost, high volume flash solution
—31.5K × 16 bit words of Program Flash
—512 × 16-bit words of Program RAM
—4K× 16-bit words of Data Flash
—2K × 16-bit words of Data RAM
—2K × 16-bit words of Boot Flash
• Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait stat es
— As much as 64K × 16 bits of data memory
— As much as 64K × 16 bits of program memory
1.1.3 Peripheral Circuits for DSP56F805
• Two Pulse Width Modulat or modul es eac h with six PWM out puts, t hree Cur rent S ense input s, and
four Fault inputs, fault tolerant design with dead-time insertion; supports both center- and edge-
aligned modes
• Two 12-bit Analog-to-Digital Converters (ADC) which support two simultaneous conversions;
ADC and PWM modules can be synchronized
• Two Quadrature Decoders each with four inputs or two additional Quad Timers
DSP56F805 Description
DSP56F805 Prel im i nary Tech nical Data 3
• Two General Purpo se Quad T imers to taling si x pins: T imer C with two pins and T imer D with four
pins
• CAN 2.0 B Module with 2-pin port for transmit and receive
• Two Serial Communication Interfaces, each with two pins (or four additional GPIO lines)
• Serial Peripheral Interface (SPI) with configurable four-pin port (or four additional GPIO lines)
• 14 dedicated General Purpose I/O (GPIO) pins, 18 multiplexed GPIO pins
• Computer Oper ating Properly (COP) watchdog timer
• Two dedicated external interrupt pins
• External reset input pin for hardware reset
• External reset output pin for system reset
• JTAG/On-Chip Emulation (OnCE™) module for unobtrusive, processor speed-independent
debugging
• Software-programmable, Phase Lock Loop-based frequency synthesizer for the DSP core clock
1.1.4 Energy Information
• Fabricated in high-density CMOS with 5V tolerant, TTL-compatible digital inputs
• Uses a single 3.3V power supply
• On-chip reg ulato rs for d igital an d analog circuitry to lower cos t and reduc e noise
• Wait and Stop modes available
1.2 DSP56F805 Description
The DSP56F805 is a member of the DSP56800 core-based family of Digital Signal Processors (DSPs). It
combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with
a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,
configuration flexibility, and compact program code, the DSP56F805 is well-suited for many applications.
The DSP56F805 includes many peripherals that are especially useful for applications such as motion
control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and control,
automotive control, engine management, noise suppression, remote utility metering, and industrial control
for power, lighting, and automation.
The DSP56800 core is based on a Harvard-style architecture consisting of three execution units operating
in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style
programming model and optimized instruction set allow straightforward generation of efficient, compact
code for both MCU and DSP applications. The instruction set is also highly efficient for C compilers to
enable rapid development of optimized control applications.
The DSP56F805 supports program execution from either internal or external memories. Two data
operands can be accessed from the on-chip Data RAM per instruction cycle. The DSP56F805 also
provides two external dedicated interrupt lines, and up to 32 General Purpose Input/Output (GPIO) lines,
depending on peripheral configuration.
The DSP56F805 DSP controller includes 31.5K words (16-bit) of Program Flash and 4K words of Data
flash (ea ch programmable through the JT AG port) with 512 words of Progra m RAM and 2K words of Data
RAM. It also supports program execution from external memory (64K).
4DSP56F805 Prel im i nary Tech nical Data
The DSP56F805 incorporates a total of 2K words of Boot Flash for easy customer-inclusion of field-
programmable software routines that can be used to program the main Program and Data Flash memory
areas. Both Program and Data Flash memories can be independently bulk-erased or erased in page sizes of
256 words. The Boot Flash memory can also be either bulk- or page-erased.
Key application-specific features of the DSP56F805 include the two Pulse Width Modulator (PWM)
modules. These m odules each incorporate three complementary, individually programmable PWM signal
outputs (each module is also capable of supporting six independent PWM functions for a total of 12 PWM
outputs) to enhance motor control functionality. Complementary operation permits programmable dead-
time insertion, distortion correction via current sensing by software, and separate top and bottom output
polarity control. The up-counter value is programmable to support a continuously variable PWM
frequency. Edge- and center-aligned synchronous pulse width control (0% to 100% modulation) is
supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors), both
BDC and BLDC (Brush and Brushless DC motors), SRM and VRM (Switched and Variable Reluctance
Motors), and stepper motors. The PWMs incorporate fault protection and cycle-by-cycle current limiting
with sufficient output drive capability to directly drive standard opto-isolators. A “smoke-inhibit”, write-
once protection fe ature for key parameters and a patented PWM waveform distortion correction circuit are
also prov ide d . Each PWM is dou ble -b u ff er ed and incl ude s interrupt control s t o perm i t i nte gra l r eload rates
to be pro gra mmable fr om 1 to 16 . The P WM modules pro vide a r efer ence out put t o synchr onize the ADCs.
The DSP56F805 incorporates two separate Quadrature Decoders capable of capturing all four transitions
on the two-phase inputs, permitting generation of a number proportional to actual position. Speed
computati on capa bili ties accommodat e both fas t and s low movin g sh afts. The int egrated wa tch dog ti mer in
the Quadrature Decoder can be programmed with a timeout value to alarm when no shaft motion is
detected. Each input is fi ltered to ensure only true transitions are recorded.
This DSP controller also provides a full set of standard programmable peripherals that include two Serial
Communications Interfaces (SCI), one Serial Peripheral Interface (SPI), and four Quad Timers. Any of
these interfaces can be used as General Purpose Input/Outputs (GPIOs) if that function is not required. A
Controller Area Network interface (CAN Version 2.0 A/B-compliant), an internal interrupt controller and
14 dedicated GPIO are also included on the DSP56F805.
1.3 “Best in Class” Development Environment
The SDK (Software Development Kit) provides fully debugged periphera l drivers, libraries and interfaces
that allow programmers to create their unique C application code independent of component architecture.
The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of Evaluation Modules (EVMs) and development system cards
support concurrent engineering. Together, the SDK, CodeWarrior, and EVMs create a complete, scalable
tools solution for easy, fast, and efficient development.
Product Documen tation
DSP56F805 Prel im i nary Tech nical Data 5
1.4 Product Documentation
The four documents listed in Table 1 are required for a complete description and proper design with the
DSP56F805. Documentation is available from local Motorola distributors, Motorola semiconductor sales
offices, Motorola Literature Distribution Centers, or online at www.motorola.com/semiconductors/dsp.
Table 1. DSP56F8 05 Chi p Docume nta ti on
1.5 Data Sh eet Conventions
This data sheet uses the following conventions:
Topic Description Order Number
DSP56800
Family Manual Detailed description of the DSP56800 family architecture, and 16-bit
DSP core processor and the instruction set DSP56800FM/D
DSP56F801/803/805/807
User’s Manual Detailed description of memory, peripherals, and interfaces of the
DSP56F801, DSP56F803, DSP56F805, and DSP56F807 DSP56F801-7UM/D
DSP56F805
Technical Data Sheet Electrical and timing specifications, pin descriptions, and package
des criptions (thi s do c um e nt) DSP56F805/D
DSP56F805
Produ ct Brief Summa ry descrip tion and block diagram of the DSP56F805 core,
memory, peripherals and interfaces DSP56F805PB/D
OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when
low.
“asserted” A high true (active high) signal is high or a low tr ue (active low) signal is low.
“deasserted” A high true (active high ) signal is low or a low true (active low) signal is high.
Examples: Signal/Symbol Logic State Signal State Voltage1
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
PIN True Asserted VIL/VOL
PIN False Deasserted VIH/VOH
PIN True Asserted VIH/VOH
PIN False Deasserted VIL/VOL
6DSP56F805 Prel im i nary Tech nical Data
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the DSP56F805 are organized into functional groups, as shown in Table 2
and as illustrated in Figure 2. In Table 3 through Table 19, each table row describes the signal or signals
present on a pin.
Table 2. Functional Group Pin Allocations
Functional Group Number of Pins Detailed Description
Power (VDD or VDDA)9Table 3
Ground (VSS or VSSA)9Table 4
Supply Capacitors and VPP 3 Table 5
PLL and Clock 3 Table 2.3
Address Bus116 Table 7
Data Bus 16 Table 8
Bus Control 4 Table 9
Interrupt and Program Control 5 Table 10
Dedicated General Purpose Input/Output 14 Table 11
Pulse Width Modulator (PWM) Port 26 Table 12
Serial Peripheral Interface (SPI) Port1
1. A l ternately, GPIO pins
4Table 13
Quadrature Decoder Port2
2. Altern at el y, Quad Tim er pins
8Table 14
Serial Communications Interface (SCI) Port14Table 15
CAN Port 2 Table 16
Analog to Digital Converter (ADC) Port 9 Table 17
Quad Timer Module Ports 6 Table 18
JTAG/On-Chip Emulation (OnCE) 6 Table 19
Introduction
DSP56F805 Prel im i nary Tech nical Data 7
Figure 2. DSP56F805 Signals Identified by Functional Group1
1. Alternate pin functionality is shown in parenthesis.
DSP56F805
Power Port
Ground Port
Power Port
Ground Port
PLL
and
Clock
External
Address Bus or
GPIO
External
Data Bus
External
Bus Control
Dedicated
GPIO
SCI0 Port
or GP IO
SCI1 Port
or GPI0
VDD
VSS
VDDA
VSSA
VCAPC
VPP
EXTAL
XTAL
CLKO
A0-A5
A6-7 (GPIOE2-E3)
A8-15 (GPIOA0-A7)
D0–D15
PS
DS
RD
WR
PHASE A0 (T A0)
PHASE B0 (T A1)
INDEX0 (TA2)
HOME0 (TA3)
PHASE A1 (T B0)
PHASE B1 (T B1)
INDEX1 (TB2)
HOME1 (TB3)
TCK
TMS
TDI
TDO
TRST
DE
Quadrature
Decoder0 or
Quad Timer A
JTAG/OnCE
Port
GPIOB0–7
GPIOD0–5
PWMA0-5
ISA0-2
FAULTA0-3
PWMB0-5
ISB0-2
FAULTB0-3
SCLK (GPIOE4)
MOSI (GPIOE5)
MISO (G PIOE6)
SS (GPIOE7)
TXD0 (GPIOE0)
RXD0 (GPIOE1)
TXD1 (GPIOD6)
RXD1 (GPIOD7)
ANA0 -7 (GPIOC6)
VREF
MSCAN_RX
MSCAN_TX
TC0-1
TD0-3
IRQA
IRQB
RESET
RSTO
EXTBOOT
PWMB
Port
Quad
T imers
C & D
ADCA
Port
Other
Supply
Ports
8
8
1
1
2
1
1
1
1
6
2
8
16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Interrupt/
Program
Control
8
6
6
3
4
6
3
4
1
1
1
1
1
1
1
1
8
1
1
1
2
4
1
1
1
1
1
Quadrature
Decoder1 or
Quad Timer B
PWMA
Port
SPI Por t
or GPIO
CAN
8DSP56F805 Prel im i nary Tech nical Data
2.2 Power and Ground Signals
2.3 Clock and Phase Lock Loop Signals
Table 3. Power Inputs
No. of
Pins Signal
Name Signal Description
8VDD Power—These pins provide power to the internal structures of the chip, and should all be attached to
VDD.
1VDDA Analog Power—These pins supp ly an analog power source.
Table 4. Grounds
No. of
Pins Signal
Name Signal Des c r iption
7VSS GND—These pi ns prov ide gro unding for the in ternal s truct ures of the chi p, and sh ould al l be attac hed
to VSS.
1VSSA Analog Ground—This pin supplies an analog ground.
1TCS TCS—This pi n is res er ved fo r fac tor y use an d mus t be ti ed to V SS for normal use. In b lock diagrams,
this pin is consid ered an additional VSS.
Table 5. Supply Capacitors and VPP
No. of
Pins Signal
Name Signal
Type
State
During
Reset Signal Des cr i ption
2VCAPC Supply Supply VCAPC - Connect each pin to a 2.2 µF bypass capacitor in order to bypass
the core logic vo ltage regu lator, requ ired for pr oper c hip operatio n. For more
information, please refer to Section 5.2.
1VPP Input Input VPP - This pin should be lef t unco nnected as an open cir c uit for norma l
functionality.
Table 6. PLL and Clock
No. of
Pins Signal
Name Signal
Type
State
During
Reset Signal Description
1EXTAL Input Input External Crystal Oscillator Input—This input can be connected to an
8 MHz external crystal. If an 8MHz or less external clock source is used,
EXTAL can be used as the input and XTAL must not be conn ected. For
more information, please refer to Section 3.5.2.
This input can also be connected to an external 8 MHz clock. Fo r more
information, please refer to Section 3.5.
The input clock can be select ed to provide the cloc k directly to the DSP
core. Thi s input clock can also be select ed as input clock for the on-chip
PLL.
Address, Data, an d Bus Control Signals
DSP56F805 Prel im i nary Tech nical Data 9
2.4 Address, Data, and Bus Control Signals
1XTAL Output Chip-
driven Crystal Oscillator Output—This output connects the inte rnal crystal
oscillator ou tput to an external crystal. If an external clock source over
8MHz is used, XTAL m ust be used as the input and EXTAL connected to
GND. For more information, please refer to Se ct ion 3.5.2.
1CLKO Output Chip-
driven Clock Output—This pin outputs a buffered clock signal. By programming
the CS[1:0] bits in the PLL Control Register (PCR1), the user can select
between o utputtin g a version o f the signal a pplied to XTAL and a versio n of
the DSP master clock at t he output of the PL L. The clock frequency on th is
pin can also be disabled by progr a mming the CS[1:0] bi ts in PC R1.
Table 7. Address Bus Signals
No. of
Pins Signal
Name Signal
Type
State
During
Reset Si gnal Description
6A0–A5 Output Tri-stated Address Bus—A0–A5 specify the address for external program or data
memory accesses.
2A6–A7
GPIOE2–
GPIOE3
Output
Input/
Output
Tri-stated
Input
Address Bus—A6–A7 specify the address for external program or data
memory accesses.
Port E GPIO—These two General Purpose I/O (GPIO) pins can be
individually programmed as input or output pins.
After reset, the default state is Address Bus.
8A8–A15
GPIOA0–
GPIOA7
Output
Input/
Output
Tri-stated
Input
Address Bus—A8–A15 specify the addr ess for external program or data
memory accesses.
Port A GPIO—These ei ght General Purpose I/O (GPIO) pins c a n be
ind ividually be programmed as input or output pins .
After reset, the default state is Address Bus.
Table 8. Data Bus Signals
No. of
Pins Signal
Name Signal
Type
State
During
Reset Sign al Desc r iption
16 D0–D15 Input/
Output Tri-stated Data Bus— D0–D15 specify the data f or external pr ogram or data memory
accesses. D0–D15 are tri-stat ed when the external bus is in active.
Table 6. PLL and Clock (Continued)
No. of
Pins Signal
Name Signal
Type
State
During
Reset Signal Description
10 DSP56F805 Prel im i nary Tech nical Data
2.5 Interrupt and Program Control Signals
Table 9. Bus Control Signals
No. of
Pins Signal
Name Signal
Type
State
During
Reset Signal Description
1PS Output Tri-
stated Pro gram Memory Select —PS is asserted low for external program memory
access.
1DS Output Tri-
stated Data M emory Select—DS is asserted low for external data memory access.
1WR Output Tri-
stated Write Enable—WR is asserted during ex ternal memory write cycles. When
WR is assert ed low, p ins D0–D15 become ou tputs a nd the DSP puts data on
the bus. When WR is deasserted high, the external data is latched inside the
external device. When WR is asserted, it qualifies the A0–A15, PS, and DS
pins. WR can be connect ed directly to t he WE pin of a Static RAM.
1RD Output Tri-
stated Read Enable—RD is asserted during ex ternal memory rea d cycles. When
RD is asserted low, pins D0–D15 become inputs and an external dev ice is
enabled onto the DSP d ata bu s. When RD is deasserted high, the external data
is latched inside the DSP. When RD is asserted, it qualifies the A0–A15, PS,
and DS pi ns. RD can be connected directly to the OE pin of a Static RAM or
ROM. Internal pullups may be active.
Table 10. Interrupt and Program Control Signals
No. of
Pins Signal
Name Signal
Type
State
During
Reset Signal Desc r iptio n
1IRQA Input Input External Interrupt Request A—The IRQA input is a synch ron ized extern al
interrupt request indicating an external device is requesting service. It can be
programmed to be level-sensitive or negative-edge- triggered.
1IRQB Input Input External Interrupt Request B—The IRQB input is an external interrupt
request indicating an external devic e is request ing service. It can be
programmed to be level-sensitive or negative-edge-triggered.
1RESET Input Input Reset—This input is a direct hardware reset on the processor. When RESET
is asserted low, the DSP is initialized and placed in the Reset state. A Schmitt
trigger input is used for noise immunity. When the RESET pin is deasserted,
the initial chip operating mode is latched from the EXTBOOT pin. The
internal reset signal will be deasserted synchronous with the internal clocks,
after a fixed number of internal clocks.
To ensure complete hardware reset, RESET and TRST sho uld be asserted
toget her. The only exception occurs in a debugging environment when a
hardware DSP reset is required and it is necessary not to reset th e OnCE/
JTAG module. In this case, assert RESET, but do not assert TRS T.
1RSTO Output Output Reset Output—This output reflects the internal reset state of the chip.
1EXTBOOT Input Input External Boot—This input is tied to VDD to force device to boot from off-
chip memory. Otherwise, it is tied to VSS.
GPIO Signals
DSP56F805 Prel im i nary Tech nical Data 11
2.6 GPIO Signals
2.7 Pulse Width Modulator (PWM) Signals
Table 11. Dedicated General Purpose Input/Output (GPIO) Signals
No. of
Pins Signal
Name Signal
Type
State
During
Reset Si gnal Descri ption
8GPIOB0–
GPIOB7 Input
or
Output
Input Port B GPIO—These eight dedica te d General Purpose I / O (G PI O ) pins can
be individually progr a mmed as input or output pi ns.
After reset, the default state is GPIO input.
6GPIOD0–
GPIOD5 Input
or
Output
Input Port D GPIO—These six dedicated GPI O pins can be individually
programmed as an input or output pins.
After reset, the default state is GPIO input.
Table 12. Pulse Width Modulator (PWMA and PWMB) Signals
No. of
Pins Sign al Name Signal
Type
State
During
Reset Signal Descrip tion
6PWMA0–5Output Tri-
stated PWMA0–5—These are six PWMA output pins.
3ISA0–2Input Input ISA0–2—These three input current status pins are used for top/bottom pulse
width correction in compl ementary channel operati on for PWMA.
4FAULTA0–3Input Input FAULTA0–3—These four Fault input pins are used for di sabling sel ected
PWMA outputs in cases where fault conditions originate off-chip.
6PWMB0–5Output Output PWMB0–5—These are six PWMB ou tput pins.
3ISB0–2Input Input ISB0–2— These three input current status pins are used for top/bo ttom
pulse width correction in compleme ntary channel operation for PWMB.
4FAULTB0–3Input Input FAULTB0–3—These four F aul t input pins are u sed for disabling selected
PWMB outputs in cases where fault conditions originate off-chip.
12 DSP56F805 Prel im i nary Tech nical Data
2.8 Serial Peripheral Interface (SPI) Signals
Table 13. Serial Peripheral Interface (SPI) Signals
No. of
Pins Signal
Name Signal
Type
State
During
Reset Signal Description
1MISO
GPIOE6
Input/
Output
Input/
Output
Input
Input
SPI Master In/Slave Out (MISO)—This serial data pin is an input to a
master device and an output from a slave device. The MISO line of a slave
devic e is placed in the hi gh-impedan ce state if the slave device i s not
selected.
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.
After reset, the default state is MISO.
1MOSI
GPIOE5
Input/
Output
Input/
Output
Input
Input
SPI Master Out/Slav e In (MOS I) —This serial da ta pin i s an ou tpu t f rom
a master device and an inpu t to a sl ave device. Th e master device places
data on th e MOSI line a ha lf-cycle before the clock edge that the slave
device us e s to latch the dat a.
Port E GPIO—This General Purpose I/O (GPIO) pin can be individually
progra m m ed as a n input or ou tp ut pin .
After reset, the default state is MOSI.
1SCLK
GPIOE4
Input/
Output
Input/
Output
Input
Input
SPI Serial Clock—In master mode, this pin serves as an output, clocking
slaved listeners. In slave mode, this p in serves as the data clock input.
Port E GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as an input or output pin.
After reset, the default state is SCLK.
1SS
GPIOE7
Input
Input/
Output
Input
Input
SPI Slave Select—In mast er mode, this pi n is used to arbit r ate multiple
masters. In slave mode, this pin is used to select the slave.
Port E GPIO—This Gen er al Pu r po s e I /O (GPIO) pin can be individually
programmed as input or output pi n.
After reset, the default state is SS.
Quadrature Decoder Signals
DSP56F805 Prel im i nary Tech nical Data 13
2.9 Quadrature Decoder Signals
Table 14. Quadrature Decoder (Quad Dec0 and Quad Dec1) Signals
No. of
Pins Signal
Name Signal
Type
State
During
Reset Signal Description
1PHASEA0
TA0
Input
Input/Output
Input
Input
Phase A—Quadrature Decoder #0 PHASEA input
TA0—Timer A Channel 0
1PHASEB0
TA1
Input
Input/Output
Input
Input
Phase B—Quadrature Decoder #0 PHASEB inpu t
TA1—Timer A Channel 1
1INDEX0
TA2
Input
Input/Output
Input
Input
Index—Quadrature Decoder #0 INDEX input
TA2—Timer A Channel 2
1HOME0
TA3
Input
Input/Output
Input
Input
Home—Quadrature Decoder #0 HOME input
TA3—Timer A Channel 3
1PHASEA1
TB0
Input
Input/Output
Input
Input
Phase A—Quadrature Decoder #1 PHASEA input
TB0—Timer B Channel 0
1PHASEB1
TB1
Input
Input/Output
Input
Input
Phase B—Quadrature Decoder #1 PHASEB inpu t
TB1—Timer B Channel 1
1INDEX1
TB2
Input
Input/Output
Input
Input
Index—Quadrature Decoder #1 INDEX input
TB2—Timer B Channel 2
1HOME1
TB3
Input
Input/Output
Input
Input
Home—Quadrature Decoder #1 HOME input
TB3—Timer B Channel 3
14 DSP56F805 Prel im i nary Tech nical Data
2.10 Serial Communications Interface (SCI) Signals
2.11 CAN Signals
Table 15. Serial Communications Interface (SCI0 and SCI1) Signals
No. of
Pins Signal
Name Signal
Type
State
During
Reset Sign al De sc r ipt io n
1TXD0
GPIOE0
Output
Input/
Output
Input
Input
Transmit Data (TXD0)—transmit data output
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can
indi viduall y be prog rammed as input or ou tput pin.
After reset, the default state is SCI output.
1RXD0
GPIOE1
Input
Input/
Output
Input
Input
Receive Data (RXD0)— receive data input
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can
indi viduall y be prog rammed as input or ou tput pin.
After reset, the default state is SCI input.
1TXD1
GPIOD6
Output
Input/
Output
Input
Input
Transmit Data (TXD1)—transmit data output
Port D GPIO—This pin is a General Pu rp ose I/O (GPIO) pin that can
indi viduall y be programmed as input or ou tput pin .
After reset, the default state is SCI output.
1RXD1
GPIOD7
Input
Input/
Output
Input
Input
Receive Data (RXD1)—receive data i np ut
Port D GPIO—This pin is a General Pu rp ose I/O (GPIO) pin that can
indi viduall y be programmed as input or ou tput pin .
After reset, the default state is SCI input.
Table 16. CAN Module Signals
No. of
Pins Signal
Name Signal
Type
State
During
Reset Signal Descrip tion
1MSCAN_ RX Input Input MSCAN Receive Data—MSCAN input. This pin has an inte rnal pull-up
resistor.
1MSCAN_ TX Output Output MSCAN Transmit Data—MSCAN output. CAN output is open-drain
output an d pull-up resist or is ne e ded .
Analog-to-Digital Converter (ADC) Signals
DSP56F805 Prel im i nary Tech nical Data 15
2.12 Analog-to-Digital Converter (ADC) Signals
2.13 Quad Timer Module Signals
2.14 JTAG/OnCE
Table 17. Analog to Digital Converter Signals
No. of
Pins Signal
Name Signal
Type State During
Reset Signal Description
4ANA0–3Input Input ANA0–3—Analog inputs to ADC channel 1
4ANA4–7Input Input ANA4–7—Analog inputs to ADC channel 2
1VREF Input Input VREF—Analog reference voltage
Table 18. Quad Timer Module Signals
No. of
Pins Signal
Name Signal Type State
During
Reset Si gnal Description
2TC0-1 Input/Output Input TC0–1—Timer C Channels 0 and 1
4TD0-3 Input/Output Input TD0–3—Timer D Channels 0, 1, 2, and 3
Table 19. JTAG/On-Chip Emulation (OnCE) Signals
No. of
Pins Signal
Name Signal
Type State During
Reset Si gnal Descr iption
1TCK Input Input, pulled
low internally Test Clock Input—This i nput pin provides a gated clock to synchroni z e
the test logic and shift serial data to the JTAG/OnCE port. The pin is
connected intern ally to a pull-d own resistor.
1TMS Input Input, pulled
high inter n ally Test Mode Select Input—This input pin is used to sequence the JTAG
TAP controller’s state machine. It is sampled on the rising edge of TCK
and has an on-chip pull-up resistor.
1TDI Input Input, pulled
high inter n ally Test Data Input—This input pin provides a serial input data stream to the
JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-
chip pull-up resistor.
1TDO Output Tri-stated Test Data Output—This tri-stat able output pi n provides a serial output
data stream from the JTAG/OnCE port. It is driven in the Shift-IR and
Shift-DR controller states, and changes on the falling edge of TCK.
1TRST Input Input, pulled
high inter n ally Test Reset—As an input, a low signal on this pin provides a reset signal to
the JTAG TAP controller. To ensure complete hardware reset, TRST
should be asserted whenever RESET is asserted. The o nl y exception
occurs in a debugging environment when a hardware DSP reset is required
and it is necessary not to reset the On CE/JTAG module. In this c ase, assert
RESET, but do not assert TRST.
1DE Output Output Debug Event—DE provides a lo w pul s e on recogn ized debug events.
16 DSP56F805 Prel im i nary Tech nical Data
Part 3 Specifications
3.1 General Characteristics
The DSP56F805 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs.
The term “5-volt tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process
technology, to w ithstand a voltage up to 5.5V without damaging the device. Many systems have a mixture
of device s designed for 3.3V and 5V power supplies. In such systems, a bus m ay carry both 3.3V and 5V-
compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ±
10% during normal operation without causing damage). This 5V tolerant capability therefore offers the
power savings of 3.3V I/O levels while being able to receive 5V levels without being damaged.
Absolute maximum ratings given in Table 20 are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.
The DSP56F805 D C/AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.
CAUTION
This device contains protective circuitry to guard
against damage due to high static voltage or
electrical fields. However, normal precautions are
advised to avoid application of any voltages higher
than maximum rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate voltage level.
Table 20. Absolute Maximum Ratings
Characteristic Symbol Min Max Unit
Supply voltage VDD VSS – 0.3 VSS + 4.0 V
All other input voltages, excluding Analog inputs VIN VSS – 0.3 VSS + 5.5V V
Analog inputs, ANA0-7 and VREF VIN VSSA VDDA V
Current drain per pin excluding VDD, VSS, PWM outputs,
TCS, VPP, VDDA, VSSA
I—10mA
Current drain per pin for PWM outputs I — 20 mA
Junction temperature TJ—150°C
Storage t e mperatur e range TSTG -55 150 °C
DC Electrical Characteristics
DSP56F805 Prel im i nary Tech nical Data 17
3.2 DC Electrical Characteristics
Table 21. Recommended Operating Conditions
Characteristic Symbol Min Max Unit
Supp ly voltage VDD,VDDA 3.0 3.6 V
Ambient operating temperature TA-40 85 °C
Flash program/erase temperature TF085°C
Table 22. Thermal Characteristics1
1. See Section 5.1 for more detail.
Characteristic 144-pin LQF P
Symbol Value Unit
Thermal resistance junc tion -to -a mbient (e stim ated ) θJA 42.7 °C/W
I/O pin power dissip a tion PI/O User Determined W
Power dissipation PDPD = ( I DD × VDD) + PI/O W
Maximu m allowed PDPDMAX (TJ – TA) / θJA °C
Table 23. DC Electrical Characteristics
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to + 8 5°C, CL ≤ 50 pF, fop = 80 MHz
Characteristic Symbol Min Typ Max Unit
Input high voltage (XTAL/EXTAL) VIHC 2.25 2.5 2.75 V
Input low voltage (XTAL/EXTAL) VILC -0.3 — 0.5 V
Input high voltage VIH 2.0 — 5.5 V
Inp u t low volt age VIL -0.3 — 0.8 V
Input current low (pullups disabled) IIL -1 — 1 µA
Input cu rr e nt hig h (pu llu ps dis a bled) IIH -1 — 1 µA
Output tri- state current l ow IOZL -10 — 10 µA
Output tri- state current hi gh IOZH -10 — 10 µA
Output High Voltage with IOH load VOH VDD – 0.7 — — V
Output Low Voltage with IOL load VOL ——0.4 V
Output High Current IOH -300 — — µA
18 DSP56F805 Prel im i nary Tech nical Data
Output Low Current IOL —— 2 mA
Input cap acitance CIN —8—pF
Output capacitance COUT —12— pF
PWM pin out put source current1IOHP — — -10 mA
PWM pin out put sink cur rent2IOLP ——16mA
Total supply current IDDT3
Run ,4 PLL set to 5 MHz out — 120 145 mA
Run,4 PLL set to 20 MHz out — 141 166 mA
Run,4 PLL set to 40 MHz out — 143 168 mA
Run,4 PLL set to 80 MHz out — 150 175 mA
Wait5—90120mA
Stop —65105mA
Low Voltage Interrupt6VEI —2.5TBDV
Low Voltage Interrupt Recovery Hysteresis VEIH —50—mV
Power on Reset7POR — 1.5 2.0 V
1. PWM pin output source c ur rent measured wit h 50% duty cycle.
2. PWM pin output sink current measured with 50% duty cycle.
3. IDDT = IDD + IDDA (Total supply current for VDD + VDDA)
4. Run (operating) IDD measured using external square wave clock source (fosc = 8 MHz ) in to XTAL. All in pu ts 0 .2 V
from rail; no DC loads; outputs unloaded. All ports configured as inputs; measured with all modules enabled.
5. Wai t IDD measured using exte rnal squ are wa ve clo ck sourc e (fosc = 8 MHz) into XTAL; all inputs 0.2 V from rail;
no DC loads; less than 50 pF on all outputs. CL = 20 pF on EXTAL; all ports configured as inputs; EXTAL capacitance
linearly aff ects wait IDD; measured with PLL.
6. When VDD drops below VEI max value, an interr upt is gener a ted.
7. Power-on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power
is ramping up, this signal remains active for as long as the internal 2.5V is below 1.5V ty pical no matter how long the
ramp up rate is. T he int ernally regu lated volta ge is t ypically 1 00 mV less than V DD during ramp up until 2.5 V is reach ed,
at which time it self regulates.
Table 23. DC Electrical Characteristics (Continued)
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to + 8 5°C, CL ≤ 50 pF, fop = 80 MHz
Characteristic Symbol Min Typ Max Unit
AC Electrical Characteristics
DSP56F805 Prel im i nary Tech nical Data 19
3.3 AC Electrical Characteristics
Timing wave for ms i n Sec ti on 3. 3 are tested wit h a VIL maximum of 0.8 V and a VIH minimum of 2.0 V for
all pins except XTAL, which is tested using the input levels in Section 3.2. In Figure 3 the leve ls of VIH
and VIL for an input signal are shown.
Figure 3. Input Signal Measurement References
Figure 4 shows the definitions of the following signal states:
• Active state, when a bus or signal is driven, and enters a low impedance state.
• Tri-stated, when a bus or signal is placed in a high impedance state.
• Data Valid state, when a signal level has reached VOL or VOH.
• Data Invalid state, when a signal level is in transition between VOL and VOH.
Figure 4. Signal States
VIH
VIL
Fall Time
Input Signa l
Note: The midpoint is VIL + (VIH – VIL)/2.
Midpoint1
Low High 90%
50%
10%
Rise Time
Data Invalid State
Data1
Data2 Valid
Data
Tri-stated
Data3 Valid
Data2 Data3
Data1 Valid
Data Active Data Active
20 DSP56F805 Prel im i nary Tech nical Data
3.4 Flash Memory Characteristics
Table 24. Flash Memory Truth Table
Mode XE1
1. X address en able, all rows are disabled when XE = 0
YE2
2. Y address enable, YMUX is disabled when YE = 0
SE3
3. Sense amplifier enable
OE4
4. Output enable, tri-st ate flash data out bus when OE = 0
PROG5
5. Defines program cycle
ERASE6
6. Defines erase cycle
MAS17
7. Defines mass erase cycle, erase whole block
NVSTR8
8. Define s non-volatile sto re cycle
Standby LLLL L L L L
Read H H H H L L L L
Word Program H H L L H L L H
Page Erase HLLL L H L H
Mass Erase H L L L L H H H
Table 25. IFREN Truth Table
Mode IFREN = 1 IFREN = 0
Read Read information block Read main memory block
Word program Program information block Program main memory block
Page erase E rase information block Erase main memory block
Mass erase Erase both block Erase main memory block
Flash Memory Characteristics
DSP56F805 Prel im i nary Tech nical Data 21
*The flash interface unit provides registers for the control of these parameters.
Table 26. Timing Symbols
Characteristic Symbol See Figure(s)
X address access time Txa -
Y address access time Tya -
OE access time Toa -
PROG/ERASE to NVSTR set up time Tnvs* Figure 5, Figure 6, Figure 7
NVSTR hold time Tnvh* Figure 5, Figure 6
NVSTR hold time(mass erase) Tnvh1* Figure 7
NVSTR to program set up time Tpgs* Figure 5
Prog ram hold t ime Tpgh Figure 5
Address/data set up time Tads Figure 5
Address/data hold time Tadh Figure 5
Recovery time Trcv* Figure 5, Figure 6, Figure 7
Cumulative program HV period Thv Figure 5
Program time Tprog* Figure 5
Erase time Terase* Figure 6
Mass erase time Tme* Figure 7
22 DSP56F805 Prel im i nary Tech nical Data
Table 27. Flash Timing Parameters
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to + 8 5°C, CL ≤ 50 pF
Characteristic Symbol Min Typ Max Unit
Program time1
1. Program specification guaranteed from T A = 0 °C to 85 °C.
Tprog 20 – – us
Erase time2
2. Erase specification guaranteed from TA = 0 °C to 85 °C.
Terase 20 – – ms
Mass erase time3
3. Mass erase sp ecification guaranteed from TA = 0 °C to 85° C.
Tme 100 – – ms
Endurance4
4. One cycle is equal to an erase, program, and read.
ECYC 10,000 – – cycles
Data Retention DRET 10 – – years
The follow ing parameters should on ly be used in the Manual Word Programming mode.
PROG/ERASE to NVSTR set up time Tnvs –5–us
NV STR hold ti me Tnvh –5–us
NVSTR hold time(mass eras e) Tnvh1 –100– us
NVSTR to program set up time Tpgs –10–us
Recovery time Trcv –1–us
Cumulative program HV period5
5. Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot
be programmed twice before next erase.
Thv –3–ms
Flash Memory Characteristics
DSP56F805 Prel im i nary Tech nical Data 23
Figure 5. Flash Program Cycle
Figure 6. Flash Erase Cycle
XADR
YADR
YE
DIN
PROG
NVSTR
Tnvs
Tpgs
Tadh
Tprog
Tads
Tpgh
Tnvh Trcv
Thv
IFREN
XE
XADR
YE=SE=OE=MAS1=0
ERASE
NVSTR
Tnvs
Tnvh Trcv
Terase
IFREN
XE
24 DSP56F805 Prel im i nary Tech nical Data
Figure 7. Flash Mass Erase Cycle
3.5 External Clock Operation
The DSP56F805 system clock can be derived from a crystal or an external system clock signal. To
generate a reference frequency using the internal oscillator, a reference crystal must be connected between
the EXTAL and XTAL pi ns.
3.5.1 Crystal Oscillator
The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the
frequency range specified for the external crystal in Table 29. In Figure 8 a typical crystal oscillator
circuit is shown. Follow the crystal supplier’s recommendations when selecting a crystal, because crystal
parameters determine the component values required to provide maximum stability and reliable start-up.
The crystal and associated components should be mounted as close as possible to the EXTAL and XTAL
pins to m inimize output distortion and start-up stabilization time.
Figure 8. Crystal Oscillator
XADR
YE=SE=OE=0
ERASE
NVSTR
Tnvs
Tnvh1 Trcv
Tme
MAS1
IFREN
XE
Sample External Crystal Parameters:
Rz = 10 MΩ
Crystal Frequency = 4–8 MHz (optimized for 8 MHz)
EXTAL XTAL
Rz
External Clock Operation
DSP56F805 Prel im i nary Tech nical Data 25
3.5.2 External Clock Source
The recommended method of connecting an external clock is given in Figure 9. The external clock source
is connected to XTAL and the EXTAL pin is grounded.
Figure 9. Connecting an External Clock Signal using XTAL
It is possible to instead drive EXTAL with an external clock, though this is not the recommended method.
If you elect to drive EXTAL with an external clock source the following conditions must be met:
1. XTAL must be completely un-loaded,
2. the maximum frequency of the applied clock must be less than 8 MHz.
Figure 10 illus trates how to c onnect an ex tern al clock ci rcuit wit h a exter nal c lock s ource u sing EXTAL a s
the input.
Figure 10. Connecting an External Clock Signal using EXTAL
Table 28. External Clock Operation Timing Requirements5
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to + 8 5°C
Characteristic Symbol Min Typ Max Unit
Frequ e ncy of operation (extern a l clock dr iver)1
1. See Figure 9 for details on usin g the r ecommended connection of an exte r nal clo c k driv e r .
fosc 0—80MHz
Clock Pulse Width2, 5
2. The high or low pulse width must be no smaller than 6.25 ns or the chip will not function.
tPW 6.25 — — ns
External clo ck inp ut rise time3, 5
3. External clock input rise time is measured from 10% to 90%.
trise —— 3ns
External clo ck inp ut fall time4, 5
4. Ex te r na l clo c k input fall time is mea s ur e d fro m 90% to 10%.
5. Paramete rs listed are guaranteed by design.
tfall —— 3ns
DSP56F805
XTAL EXTAL
External VSS
Clock
DSP56F805
XTAL EXTAL
No External
Connection Clock ( < 8MHz)
26 DSP56F805 Prel im i nary Tech nical Data
Figure 11. External Clock Timing
3.6 External Bus Asynchronous Timing
Table 29. PLL Timing
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to + 8 5°C
Characteristic Symbol Min Typ Max Unit
External reference crystal frequency for the PLL1
1. An externally supplied reference cl ock should be as free as possible from any phase jitter for the PLL to work
correctly . The PLL is optimized for 8 MHz input crystal.
fosc 488MHz
PLL output frequency fop 40 — 80 MHz
PLL stabilization time 2
2. This is the minimum time required after the PLL setup is changed to ensure reliable operation.
tplls —110ms
Table 30. External Bus Asynchronous Timing 1, 2
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to + 8 5°C, CL ≤ 50 pF, fop = 80 MHz
Characteristic Symbol Typical Min Typical Max Unit
Address Valid to WR Asserted tAWR 6.5 — ns
WR Width Asserted
Wait states = 0
Wait states > 0
tWR 7.5
(T*WS)+7.5 —
—ns
ns
WR Asserted to D0–D15 Ou t Va lid tWRD —T+4.2ns
Data Out Hold Tim e from WR Deasserted tDOH 4.8 — ns
Data Out Set Up Time to WR Deasserted
Wait states = 0
Wait states > 0
tDOS 6.4
(T*WS)+6.4 —
—ns
ns
RD Deasserted to Address Not Valid tRDA 0—ns
External
Clock
VIH
VIL
Note: The midpoint is VIL + (VIH – VIL)/2.
90%
50%
10%
90%
50%
10% tPW tPW tfall trise
External Bus Asynchronous Timing
DSP56F805 Prel im i nary Tech nical Data 27
Address Valid to RD Deasserted
Wait states = 0
Wait states > 0
tARDD 18.7
(T*WS) + 18.7
—ns
ns
Input Data Hold to RD Deasserted tDRD 0—ns
RD Assertion Width
Wait states = 0
Wait states > 0
tRD 19
(T*WS)+19 —
—ns
ns
Address Valid to Input Data Valid
Wait states = 0
Wait states > 0
tAD —
—1
(T*WS)+1 ns
ns
Address Valid to RD Asserted tARDA -4.4 — ns
RD Asserted to Input Data Valid
Wait states = 0
Wait states > 0
tRDD —
—2.4
(T*WS) + 2.4 ns
ns
WR Deasserted to RD Asserted tWRRD 6.8 — ns
RD Deasserted to RD Asserted tRDRD 0—ns
WR Deasserted to WR Asserted tWRWR 14.1 — ns
RD Deasserted to WR Asserted tRDWR 12.8 — ns
1. Timing is both wait state and frequency dependent . In the formulas listed, WS = the num ber of wait states an d
T = Clock Period. For 80 MHz operation, T = 12.5ns.
2. Parameters listed are guaranteed by design.
To calculate the required access time for an external memory for any frequency < 80 Mhz, use this formula:
Top = Clock period @ desired operating frequency
WS = Number of wait states
Memory Access Time = (Top*WS) + (Top- 11.5)
Table 30. External Bus Asynchronous Timing (Continued)1, 2
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to + 8 5°C, CL ≤ 50 pF, fop = 80 MHz
Characteristic Symbol Typical Min Typical Max Unit
28 DSP56F805 Prel im i nary Tech nical Data
Figure 12. External Bus Asynchronous Timing
A0–A15,
PS, DS
(See Note)
WR
D0–D15
RD
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
Data In
Data Out
tAWR
tARDA
tARDD tRDA
tRD tRDRD
tRDWR
tWRWR tWR
tDOS
tWRD
tWRRD
tAD
tDOH
tDRD
tRDD
Reset, Stop, Wai t, Mode S e lect, and Interrupt Timing
DSP56F805 Prel im i nary Tech nical Data 29
3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 31. Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 6
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to + 8 5°C, CL ≤ 50 pF
1. In the formulas, T = clock cycle. For an operating frequenc y of 80 MHz, T = 12.5 ns.
Characteristic Symbol Typical Min Typical
Max Unit See Figure
RESET Assertion to Address, Data and Control Signals
High Impedance tRAZ —21nsFigure 13
Minimum RESET Assertion Duration2
OMR Bit 6 = 0
OMR Bit 6 = 1
2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
• After power-on reset
• When recovering from Stop state
tRA 275,000T
128T —
—ns
ns
Figure 13
RESET De-assertion to First External Address Output tRDA 33T 34T ns Figure 13
Edge-sensitive Interrupt Request Width tIRW 1.5T — ns Figure 14
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction execution
in the inte rrupt service routine
tIDM — 15T ns Figure 15
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
tIG — 16T ns Figure 15
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State3tIRI — 13T ns Figure 16
IRQA Width Assertion to Recover from Stop State 4tIW —2TnsFigure 17
Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tIF
—
—275,000T
12T ns
ns
Figure 17
Duration for Level Sensitive IRQA Assertio n to Ca use
the Fetch of First IRQA Interrupt Instruction (exiting
Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tIRQ
—
—275,000T
12T ns
ns
Figure 18
Delay from Level Sensitive IRQA Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tII
—
—275,000T
12T ns
ns
Figure 18
RSTO pulse width5
normal op eration
internal reset mode
tRSTO 63ET
2,097,151ET ns
ns
Figure 19
30 DSP56F805 Prel im i nary Tech nical Data
Figure 13. Asynchronous Reset Timing
Figure 14. External Interrupt Timing (Negative-Edge-Sensitive)
Figure 15. External Level-Sensitive Interrupt Timing
3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the
Stop state. This is not the minimum required so that the IRQA interrupt is accepted.
4. The interrupt instructio n fetch is visible on the pins only in Mode 3.
5. ET = External Clock period, For an external crystal frequency of 8 MHz, ET=125 ns.
6. Paramete rs listed are guaranteed by design.
First Fetch
A0–A15,
D0–D15
PS, DS,
RD, WR
RESET
First Fetch
tRDA
tRA
tRAZ
IRQA
IRQB tIRW
A0–A15,
PS, DS ,
RD, WR
IRQA,
IRQB
First Interrupt Instruction Execution
a) First Interrupt Instruction Execution
Purpose
I/O Pin
IRQA,
IRQB
b) General Purpose I/O
tIG
tIDM
Reset, Stop, Wai t, Mode S e lect, and Interrupt Timing
DSP56F805 Prel im i nary Tech nical Data 31
Figure 16. Interrupt from Wait State Timing
Figure 17. Recovery from Stop State Using Asynchronous Interrupt Timing
Figure 18. Recovery from Stop State Using IRQA Interrupt Service
Figure 19. Reset Output Timing
Instruction Fetch
IRQA,
IRQB
First Interrupt Vector
A0–A15,
PS, DS,
RD, WR
tIRI
Not IRQA Interrupt V ector
IRQA
A0–A15,
PS, DS,
RD, WR First Instruction Fetch
tIW
tIF
Instruction Fetch
IRQA
A0–A15
PS, DS,
RD, WR First IR Q A Interrupt
tIRQ
tII
RSTO
tRSTO
32 DSP56F805 Prel im i nary Tech nical Data
3.8 Serial Peripheral Interface (SPI) Timing
1. Parameters listed are gu aranteed by design.
Table 32. SPI Timing1
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50 pF, fOP = 80 MHz
Characteristic Symbol Min Max Unit See Figure
Cycle time
Master
Slave
tC50
50 —
—ns
ns
Figures 20,
21, 22, 23
Enable lead time
Master
Slave
tELD —
25 —
—ns
ns
Figure 23
Enable lag time
Master
Slave
tELG —
100 —
—ns
ns
Figure 23
Clock (SCLK) high time
Master
Slave
tCH 17.6
25 —
—ns
ns
Figures 20,
21, 22, 23
Clock (SCLK) low tim e
Master
Slave
tCL 24.1
25 —
—ns
ns
Figure 23
Data setup time required for inputs
Master
Slave
tDS 20
0—
—ns
ns
Figures 20,
21, 22, 23
Data hold time required for inputs
Master
Slave
tDH 0
2—
—ns
ns
Figures 20,
21, 22, 23
Access time (tim e to data active from high-impedance state)
Slave tA4.8 15 ns Figure 23
Disable time (hold time to high-impedance state)
Slave tD3.7 15.2 ns Figure 23
Data Valid for outputs
Master
Slave (after en able edge)
tDV —
—4.5
20.4 ns
ns
Figures 20,
21, 22, 23
Data invalid
Master
Slave
tDI 0
0—
—ns
ns
Figures 20,
21, 22, 23
Rise time
Master
Slave
tR—
—11.5
10.0 ns
ns
Figures 20,
21, 22, 23
Fall time
Master
Slav e
tF—
—9.7
9.0 ns
ns
Figures 20,
21, 22, 23
Serial Peripheral Interface (SPI) Timing
DSP56F805 Prel im i nary Tech nical Data 33
Figure 20. SPI Master Timing (CPHA = 0)
Figure 21. SPI Master Timing (CPHA = 1)
SCLK (CPOL = 0)
(Output)
SCLK (CPOL = 1)
(Output)
MISO
(Input)
MOSI
(Output)
MSB in Bits 14–1 LSB in
Master MSB out Bits 14–1 Master LSB out
SS
(Input) SS is held High on master
tCtRtF
tCH
tCL
tFtR
tCH
tCH
tDV
tDH
tDS
tDI tDI(ref)
tFtR
tCL
SCLK (CPOL = 0)
(Output)
SCLK (CPOL = 1)
(Output)
MISO
(Input)
MOSI
(Output)
MSB in Bits 14–1 LSB in
Master MSB out Bits 14– 1 Master LSB out
SS
(Input) SS is held High on m aster
tR
tF
tC
tCH
tCL
tCH
tCL
tF
tDS
tDH
tR
tDI
tDV(ref) tDV
tFtR
34 DSP56F805 Prel im i nary Tech nical Data
Figure 22. SPI Slave Timing (CPHA = 0)
Figure 23. SPI Slave Timing (CPHA = 1)
SCLK (CPOL = 0)
(Input)
SCLK (CPOL = 1)
(Input)
MISO
(Output)
MOSI
(Input)
Slave MSB out Bits 14–1
MSB in Bits 14–1 LSB in
SS
(Input)
Slave LSB out
tDS
tCL
tCL
tDI tDI
tCH
tCH
tR
tR
tELG
tDH
tELD
tCtF
tFtD
tA
tDV
SCLK (CPOL = 0)
(Input)
SCLK (CPOL = 1)
(Input)
MISO
(Output)
MOSI
(Input)
Slave MSB out Bits 14–1
MSB in Bits 14–1 LSB in
SS
(Input)
Slave LSB out
tELG
tDI
tDS
tDH
tELD
tC
tCL
tCH
tR
tF
tF
tCL
tCH
tDV
tA
tDV
tRtD
Quad Timer Tim i ng
DSP56F805 Prel im i nary Tech nical Data 35
3.9 Quad Timer Timing
Table 33. Timer Timing1, 2
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3 .6 V, TA = –40° to +85°C, CL ≤ 50 pF, fOP = 80 MHz
1. In the formulas listed, T = clock cycle. For 80 MHz operation , T = 12.5 ns.
2. Parameters listed are guaranteed by des ig n.
Characteristic Symbol Min Max Unit
Timer input period PIN 4T+6 — ns
Timer input high /low perio d PINHL 2T+3 — ns
Timer output per iod POUT 2T-3 — ns
Timer output hi gh/low per iod POUTHL 1T-3 — ns
Figure 24. Timer Timing
Timer Inputs
Timer Outputs
PINHL PINHL
PIN
POUTHL
POUTHL
POUT
36 DSP56F805 Prel im i nary Tech nical Data
3.10 Quadrature Decoder Timing
Table 34. Quadrature Decoder Timing1, 2
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3 .6 V, TA = –40° to +85°C, CL ≤ 50 pF, fOP = 80 MHz
1. In the formula s listed, T = clock cycle. For 80 MHz operation, T = 12 .5 ns. VSS = 0 V, VDD = 3.0–3.6 V,
TA = –40° to +85°C, CL ≤ 50 pF.
2. Parameters listed are guaranteed by des ig n.
Characteristic Symbol Min Max Unit
Quadrature input period PIN 8T+12 — ns
Quadrature inp ut high /lo w period PHL 4T+6 — ns
Quadrature phase period PPH 2T+3 — ns
Figure 25. Quadrature Decoder Timing
Phase B
(Input)
Phase A
(Input)
PPH
PPH
PPH
PPH
PIN
PIN PHL PHL
PHL
PHL
Serial Communication In terface (SCI) Timing
DSP56F805 Prel im i nary Tech nical Data 37
3.11 Serial Communication Interface (SCI) Timing
Figure 26. RXD Pulse Width
Figure 27. TXD Pulse Width
Table 35. SCI Timing4
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to + 8 5°C, CL ≤ 50 pF, fOP = 80 MHz
Characteristic Symbol Min Max Unit
Baud Rate1
1. fMAX is the frequency of operation of the system clock in MHz.
BR —(fMAX*2.5)/(80) Mbps
RXD2 Pulse Wid th
2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
RXDPW 0.965/BR 1.04/BR ns
TXD3 Pulse Width
3. The TXD pin i n SCI0 is named TXD0 and t he T XD pin in SCI1 is named TXD1.
4. Parameter s lis ted are guaranteed by design.
TXDPW 0.965/BR 1.04/BR ns
RXD
SCI receive
data pin
(Input) RXDPW
TXD
SCI receive
data pin
(Input) TXDPW
38 DSP56F805 Prel im i nary Tech nical Data
3.12 Analog-to-Digital Converter (ADC) Characteristics
NOTE:
IADC quiescent current (both ADCs) is 39.3 mA
IVREF quie s cent current (bo th ADCs) is 11.85 mA
Typical val ues measured at VDD = 3.3, VREF = 3.0
VREF must be equal to or less than VDD
VREF can go as low as 2.7V.
Table 36. ADC Characteristics
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to + 8 5°C, CL ≤ 50 pF, fOP = 80 MHz
Characteristic Symbol Min Typ Max Unit
Input voltages VADIN 0—VDDA1
1. VDDA should be tied to the same potentia l as VDD via separate traces.
V
Resolution RES 12 — 12 Bits
Integral Non-Linearity INL — +/- 3 TB D LSB2
2. LSB = Least Signi fic ant Bit.
Differential Non-Linearity DNL — +/- .8 TBD LSB2
Monotonicity GUARANTEED
ADC internal clock fADIC 0.5 — 5 MHz
Conversion range RAD VSSA —VDDA V
Power-up time tADPU —16 —
tAIC cycles3
3. tAIC = 1/fADIC.
Conversion time tADC —6 —
tAIC cycles3
Sample time tADS —1 —
tAIC cycles3
Input capacitance CADI —5 — pF4
4. See Figure 28
VREF current IVREF —— 14.5 mA
Gain Error (transfer gain) EGAIN — .99725 — —
Offs et Voltage VOFFSET —25TBD mV
SINAD SINAD — 59 — —
ENOB ENOB — 9.5 — bit
SFDR SFDR — 64 — db
Bandwidth BW — 100 — KHz
Controller Area Network (CAN) Timing
DSP56F805 Prel im i nary Tech nical Data 39
Figure 28. Equivalent Analog Input Circuit
1. Parasitic capacitance due to package, pin to pin, and pin to package base coupling. 1.8pf
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing.
2.04pf
3. Equivalent resistance for the ESD isolation resistor and the channel select mux. 500 ohms
4. Sampling capacitor at the sample and hold circuit. 1pf
3.13 Controller Area Network (CAN) Timing
Figure 29. Bus Wakeup Detection
Table 37. CAN Timing2
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to + 8 5°C, CL ≤ 50 pF,
MSCAN Clock = 30 MHz
Characteristic Symbol Min Max Unit
Baud Rate BRCAN —1Mbps
Bus Wakeup detecti on 1
1. If W akeup gl itch fi lter is e nabled d uring the desi gn ini tializa tion and also CAN is put in to Sle ep mode then, a ny b us
event (on MSCAN_RX pin) whose duration is less than 5 microseconds is filtered away. However, a valid CAN bus
wakeup det ectio n take s place for a wakeup p ulse e qual to or great er than 5 mi croseco nds. Th e number 5 micros econds
originates from the fact that the CAN wakeup message consis ts of 5 dominant bits at th e highest possibl e baud rate of 1
Mbps.
2. Parameter s li s ted are guaranteed by design.
T WAKEUP 5—us
1
2
3
4
ADC analog input
MSCAN_RX
CAN receive
data pin
(Input) T WAKEUP
40 DSP56F805 Prel im i nary Tech nical Data
3.14 JTAG Timing Table 38. JTAG Timing1, 3
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3. 0–3.6 V, TA = –40° to +85°C, CL ≤ 50 pF, fOP = 80 MHz
1. Timing is both wait state and frequency dependent . F or t he values listed, T = clock cycle. For 80 MHz
operation, T = 12.5 ns.
Characteristic Symbol Min Max Unit
TCK frequency of operation2
2. TCK frequency of operatio n must be less than 1/8 the processor rate.
3. Parameters listed are guaranteed by design.
fOP DC 10 MHz
TCK cycle time tCY 100 — ns
TCK clock pulse width tPW 50 — ns
TMS, TDI data setup time tDS 0.4 — ns
TMS, TD I data hold time tDH 1.2 — ns
TCK low to TDO data valid tDV —26.6ns
TCK low to TDO tri-state tTS —23.5ns
TRST assertion time tTRST 50 — ns
DE assertion time tDE 4T — ns
Figure 30. Test Clock Input Timing Diagram
TCK
(Input) VM
VIL
VM = VIL + (VIH – VIL)/2
VM
VIH
tPW
tPW
tCY
JTAG Timing
DSP56F805 Prel im i nary Tech nical Data 41
Figure 31. Test Access Port Timing Diagram
Figure 32. TRST Timing Diagram
Figure 33. OnCE—Debug Event
Input Data Valid
Output Data Valid
Output Data Valid
TCK
(Input)
TDI
(Input)
TDO
(Output)
TDO
(Output)
TDO
(Output)
TMS
tDV
tTS
tDV
tDS tDH
TRST
(Input) tTRST
DE
tDE
42 DSP56F805 Prel im i nary Tech nical Data
Part 4 Packaging
4.1 Package and Pin-Out Information DSP56F805
This section contains package and pin-out information for the 144-pin LQFP configuration of the
DSP56F805.
Figure 34. Top View, DSP56F805 144-pin LQFP Package
Orientation Mark
1
37
73109
D10
D11
D12
D13
D14
D15
A0
VDD
PWMB0
VSS
PWMB1
A1
PWMB2
A2
PWMB3
A3
A4
A5
PWMB4
A6
PWMB5
A7
ISB0
A8
ISB1
A9
ISB2
A10
FAULTB0
A11
FAULTB1
A12
A13
VDD
PS
DS
RXD0
TXD0
PWMA5
PWMA4
GPIOD2
PWMA3
GPIOD1
PWMA2
GPIOD0
PWMA1
GPIOB7
PWMA0
GPIOB6
HOME0
GPIOB5
INDEX0
GPIOB4
VSS
GPIOB3
VDD
GPIOB2
PHASEB0
GPIOB1
PHASEA0
GPIOB0
VSS
VDD
VDD
VDDA
VSSA
EXTAL
XTAL
ANA7
ANA6
ANA5
ANA4
144
Motorola
DSP56F805
E
XTBOOT
RESET
DE
CLKO
TD0
TD1
VDD
TD2
VSS
TD3
RSTO
SS
GPIOD3
MISO
GPIOD4
MOSI
SCLK
VCAPC
GPIOD5
D0
VPP
D1
D2
INDEX1
VDD
PHASEB1
VSS
P
HASEA1
D3
HOME1
D4
D5
D6
D7
D8
D9
ANA3
ANA2
ANA1
ANA0
VREF
FAULTA3
FAULTA2
MSCAN_R
X
FAULTA1
MSCAN_T
X
FAULTA0
RXD1
ISA2
VSS
ISA1
VDD
ISA0
VCAPC
TRST
TDO
TXD1
TDI
TC1
TMS
TC0
TCK
FAULTB3
TCS
FAULTB2
IRQB
IRQA
RD
WR
VSS
A15
A14
Package and Pin-Out Information DSP56F805
DSP56F805 Prel im i nary Tech nical Data 43
Table 39. DSP56F805 Pin Identification by Pin Number
Pin
No. Sign al N am e Pin
No. Sign al Nam e Pin
No. Signal Name Pin
No. Sign al Name
1 D10 37 A14 73 ANA4 109 EXTBOOT
2 D11 38 A15 74 ANA5 110 RESET
3 D12 39 VSS 75 ANA6 111 DE
4 D13 40 WR 76 ANA7 112 CLKO
5 D14 41 RD 77 XTAL 113 TD0
6 D15 42 IRQA 78 EXTAL 114 TD1
7 A0 43 IRQB 79 VSSA 115 VDD
8V
DD 44 FAULTB2 80 VDDA 116 TD2
9PWMB045 TCS 81 V
DD 117 VSS
10 VSS 46 FAULTB3 82 VDD 118 TD3
11 PWMB1 47 TCK 83 VSS 119 RSTO
12 A1 48 TC0 84 GPIOB0 120 SS
13 PWMB2 49 TMS 85 PHASEA0 121 GPIOD3
14 A2 50 TC1 86 GPIOB1 122 MISO
15 PWMB3 51 TDI 87 PHASEB0 123 GPIOD4
16 A3 52 TXD1 88 GPIOB2 124 MOSI
17 A4 53 TDO 89 VDD 125 SCLK
18 A5 54 TRST 90 GPIOB3 126 VCAPC
19 PWMB4 55 VCAPC 91 VSS 127 GPIOD5
20 A6 56 ISA0 92 GPIOB4 128 D0
21 PWMB5 57 VDD 93 INDEX0 129 VPP
22 A7 58 ISA1 94 GPIOB5 130 D1
23 ISB0 59 VSS 95 HOME0 131 D2
24 A8 60 ISA2 96 GPIOB6 132 INDEX1
25 ISB1 61 RXD1 97 PWMA0 133 VDD
26 A9 62 FAULTA0 98 GPIOB7 134 PHASEB1
27 ISB2 63 MSCAN_TX 99 PWMA1 135 VSS
44 DSP56F805 Prel im i nary Tech nical Data
28 A10 64 FAULTA1 100 GPIOD0 136 PHASEA1
29 FAULTB0 65 MSCAN_RX 101 PWMA2 137 D3
30 A11 66 FAULTA2 102 GPIOD1 138 HOME1
31 FAULTB1 67 FAULTA3 103 PWMA3 139 D4
32 A12 68 VREF 104 GPIOD2 140 D5
33 A13 69 ANA0 105 PWMA4 141 D6
34 VDD 70 ANA1 106 PWMA5 142 D7
35 PS 71 ANA2 107 TXD0 143 D8
36 DS 72 ANA3 108 RXD0 144 D9
Table 39. DSP56F805 Pin Identification by Pi n Number (Continued)
Pin
No. Sign al N am e Pin
No. Sign al Nam e Pin
No. Signal Name Pin
No. Sign al Name
Package and Pin-Out Information DSP56F805
DSP56F805 Prel im i nary Tech nical Data 45
Figure 35. 144-pin LQFP Mechanical Information
46 DSP56F805 Prel im i nary Tech nical Data
Part 5 Design Considerations
5.1 Thermal Design Considerations
An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation:
Equation 1:
Where:
TA = ambient temperature °C
RθJA = package junction-to-ambient thermal resistance °C/W
PD = power dissipation in package
Historically, thermal resist ance has been expressed as the sum of a junction-to-case thermal resistance and
a case-to-ambient thermal resistance:
Equation 2:
Where:
RθJA = package junction-to-ambient thermal resistance °C/W
RθJC = package junction-to-case thermal resistance °C/W
RθCA = package case-to-ambient thermal resistance °C/W
RθJC is device-related and cannot be influenced by the user. The user controls the thermal environment to
chang e the ca se-t o-a mbien t ther mal res ista nce, R θCA. For example, t he user can ch ange the ai r flow arou nd
the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or
otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated
through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations
where the heat flow is spli t between a path to the case and an alternate path through the PCB, analysis of
the device thermal performance may need the additional modeling capability of a system level thermal
simulation tool .
The thermal performance of plastic packages is more dependent on the temperature of the PCB to which
the package is mounted. Again, if the estimations obtained from RθJA do not satisfactorily answer whether
the thermal perf ormanc e is ad equate, a system level model may be appropriate.
Definitions:
A complicating factor is the existence of three common definitions for determining the junction-to-case
thermal r esistance in plasti c pack ages:
• Measure the thermal resistance from the junction to the outside surface of the package (case) closest
to the chip mounting area w hen that surface has a proper heat sink. This is done to minimize
temperature variation across the surface.
• Measure the thermal resistance from the junction to where the leads are attached to the case. This
definition is approximately equal to a junction to board thermal resistance.
TJTAPDRθJA
×()+=
RθJA RθJC RθCA
+=
47 DSP56F805 Prel im i nary Tech nical Data
• Use the value obtained by the equation (TJ – TT)/PD where TT is the temperature of the package
case determined by a thermocouple.
The junction-to-case thermal resistances quoted in this data sheet are determined using the first definition
on page 45. From a practica l sta ndpoint , t hat val ue is also s uitabl e for deter mining t he junc tion t emperat ure
from a case thermocouple reading in forced convection environments. In natural convection, using the
junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the
case of th e package will est imate a juncti on temper ature slightly hotter than act ual. Hence, th e new therma l
metric, Therma l Chara cterization P arame ter, or ΨJT, has been defined to be (TJ – TT)/PD. T his value giv es
a better estimate of the junction temperature in natural convection when using the surface temperature of
the package. Remember that surface temperature readings of packages are subject to significant errors
caused by inadequ ate at tachmen t of th e senso r to th e su rface and to e rrors caused by heat l oss t o the se nsor.
The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the
package with thermally conductive epoxy.
5.2 Electrical Design Considerations
Use the follow ing li st of considerations to assure correct DSP op eration:
• Provide a low-imp edance pat h from the boa rd power sup ply to eac h VDD pin on the DSP, and from
the board ground to each VSS pin.
• The minimum bypass requirement is to place six 0.01–0.1 µF capacitors positioned as close as
possibl e to the package supply pins. The r ecommended bypas s configuration is to place one bypass
capacit or on each of the ni ne VDD/VSS pairs, including VDDA/VSSA. The VCAP capacitors must be
150 milliohm or less ESR capacitors.
• Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and
VSS pins are less than 0.5 inch per capacitor lead.
• Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VDD and VSS.
• Bypass the VDD and VSS layers of the PCB with approximately 100 µF, preferably with a high-
grade capacitor such as a tantalum capacitor.
• Becaus e the DSP outp ut signal s have fast ri se and fal l times, PCB t race leng ths should be minimal.
CAUTION
This device cont ains protec ti ve circui try to guard again st
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.
DSP56F805/D
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respective owners. © Motorola, Inc. 2001.
How to reach us:
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suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, includi ng without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including
“Typicals” must be validated for each customer appli cation by customer’s technical experts. Motorola does not convey any licens e under it s patent rights nor the
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• Consider all device loads as well as parasitic capacita nce due to PCB traces when calculating
capacit ance. This is espe cially cri tical in syste ms with highe r capacitive l oads that cou ld create higher
transient currents in the VDD and VSS circuits.
• Take special care to minim ize noise levels on the VREF, VDDA and VSSA pins .
• Designs that utilize the TRST pin for JTAG port or OnCE mod ule funct ionalit y (such as develo pment
or debuggi ng syste ms) shoul d allow a mea ns to as sert TRST whe never RESET is as serte d, as well as
a means to assert TRST independently of RESET. Designs that do not require debugging functionality ,
such as consumer products, should tie these pins together.
• Because the Flash memory is programmed through t he JT AG/OnCE por t, designers should provide an
interface to this port to allow in-circuit Flash programming.
Part 6 Ordering Information
Table 40 lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales
office or authorized distributor to determine availability and to order parts.
Table 40. DSP56F805 Ordering Information
Part Supply
Voltage Package Type Pin
Count Frequency
(MHz) Order Number
DSP56F805 3.0–3.6 V Low Profile Plastic Quad Flat Pack (LQFP) 144 80 DSP56F805FV80
