Product Specification OS t Z8430/Z84C30 NMOS/CMOS ' Z80 CTC Counter/Timer Circuit FEATURES mw Four independently programmable counter/timer channels, each with a readable downcounter and a selectable 16 or 256 prescaler. Downcounters are reloaded automatically at zero count. @ Selectable positive or negative trigger initiates timer operation. @ Three channels have Zero Count/Timeout outputs capable of driving Darlington transistors. (1.5 mV @ 1.5V} m@ NMOS version for cost sensitive performance solutions. m@ CMOS version for the designs requiring low power consumption m NMOS 20843004 - 4 MHz, Z0843006 - 6.17 MHz. mw CMOS Z84C3006 - DC to 6.17 MHz, 284C3008 - 8 MHz, Z84C3010 - DC to 10 MHz a Interfaces directly to the Z80 CPU orfor baud rate generationto the Z80 SIO. a Standard Z80 Family daisy-chain interrupt structure provides fully vectored, prioritized interrupts without external logic. The CTC may also be used as an interrupt controller. 6 MHz version supports 6.144 MHz CPU clock opera- tion. GENERAL DESCRIPTION The Z80 CTC, hereinafter referred to as Z80 CTC or CTC, four-channel counter/timer can be programmed by system software for a broad range of counting and timing apptica- tions. The four independently programmable channels of the Z80 CTC satisfy common microcomputer system re- quirements for event counting, interrupt andinterval timing, and general clock rate generation. System design is simplified because the CTC connects directly to both the Z80 CPU and the 280 SIO with no additional logic. in larger systems, address decoders and buffers may be required. ~t>] Do CLK/TRG, [-* > dD, ZCITO) -> _P Dz CPU | } dD, CLKITRG, j< DATA zero sus | +>} 1 F> | CHANNEL <>] 0s SIGNALS. ~<+ >| 05 CLKITRG: f-<* ~<+] D; 2ZCcITO2 -> +| CE | C cre So CLKITRG3 controL { >|} cS: FROM ) ] mi RESET J< cpu ~|] iORO >| FD zs0 CTC DAISY ( +] IE CHAIN INTERRUPT | * (EO contro. | <j int tty CLK +5V GND Figure 1. Pin Functions Programming the CTC is straightforward: each channel is programmed with two bytes; a third is necessary when interrupts are enabled. Once started, the CTC counts down, automatically reloads its time constant, and resumes counting. Software timing loops are completely eliminated. Interrupt processing is simplified because only one vector need be specified; the CTC internally generates a unique vector for each channel. The Z80 CTC requires asingle +5%V power supply andithe standard Z80 single-phase system clock. Itis packaged in 28-pin DIPs, a44-pin plastic chip carrier, anda 44-pin Quad Flat Pack. (Figures 2a, 2b, and 2c). Note that the QFP package is only available for CMOS versions. oe C1 28 [J 3 os C2 27] bz Ds ()3 26 [J 0 o7 (4 25 [J 00 eno (5 aT] +5v a Che . 23 [J CLKITRG) zertoo (7 22 [7] cuxrtac, zero, Cys Z80CTC 2:77 cin, zero, C9 20 FF] cLKTRG3 iorna [ 10 197) cs, 10 Cis 18} cso int (7) 12 17 [] RESET ter [13 161] GE mi [14 15 [L] cuk Figure 22a. Pin Assignments 83 DC toLK HLH gTaree 6 5 43 2 t 44 43 42 41 40 GNO NC RO ZC/TOo NC Zc/TO, ZC/TO2 iond NC IEO NC +5V NC CLK/TRGo NC CLK/TAG, CLK/TRG2 CLK/TAG3 18 19 20 21 22 23 24 25 26 27 28 LE LOSES EGEL e Figure 2b. 44-pin Chip Carrier, Pin Assignments to NG mer02 CMOS a zs0 CTC ZurT00 NC GQND or "1 BSS224 882 Figure 2C. 44-Pin Quad Flat Pack Pin Assignments FUNCTIONAL DESCRIPTION The Z80 CTC has four independent counter/timer channels. Each channel is individually programmed with two words: a control word and a time-constant word. The control word selects the operating mode (counter or timer), enables or disables the channel interrupt, and selects certain other operating parameters. If the timing mode is selected, the control word also sets a prescaler, which divides the system clock by either 16 or 256. The time-constant word is a value from 1 to 256. During operation, the individual counter channel counts down from the preset time constant value. In counter mode operation the counter decrements on each of the CLK/TRG input pulses until zero count is reached. Each decrement is synchronized by the system clock. For counts greater than 256, more than one counter can be cascaded. At zero count, the down-counter is automatically reset with the time constant value. The timer mode determines time intervals as small as 2 ps(8 MHz), 3 us (6 MHz), or 4 as (4MHz) without additional logic or software timingloops. Time intervals are generated by dividing the system clock with a prescaler that decre- ments a preset down-counter. Thus, the time interval is an integral multiple of the clock period, the prescaler value (16 or 256), and the time constant that is preset-in the down-counter. A timer is triggered automatically when its time constant value is programmed, or by an external CLK/TRG input. Three channels have two outputs that occur at zero count. The first output is a Zero-count/timeout pulse at the ZC/TO output. The fourth channel (Channel 3) does not have a ZC/TO output; interrupt request is the only output available from Channel 3. The second output is Interrupt Request (INT), which occurs ifthe channel! has its interrupt enabled during programming. When the Z80 CPU acknowledges Interrupt Request, the Z80 CTC places an interrupt vector on the data bus. The four channels of the Z80 CTC are fully prioritized and fit into four contiguous slots in a standard Z80 daisy-chain interrupt structure. Channel 0 is the highest priority and Channel 3 the lowest. Interrupts can be individually enabled (or disabled) for each of the four channels. INTERNAL STRUCTURE The CTC has four major elements, as shown in Figure 3. m CPU bus I/O @ Channel control logic @ Interrupt logic @ Counter/timer circuits CPU Bus I/O. The CPU bus I/O circuit decodes the address inputs, and interfaces the CPU data and control signals to the CTC for distribution on the internal bus. Internal Control Logic. The CTC internal control logic controls overall chip operating functions such as the chip enable, reset, and read/write logic. Interrupt Logic. The interrupt control logic ensures that the CTC interrupts interface properly with the Z80 CPU interrupt system. The logic controls the interrupt priority of the'CTC as a function of the IEI signal. If Elis High, the CTC has priority. During interrupt processing, the interrupt logic holds IEO Low, which inhibits the interrupt operation on lower priority devices. If the IEI input goes Low, priority is relinquished and the interrupt logic drives IEO Low. 84DATA 8 P FROM =) cos 80 CPU uo CONTROL 6 INTERNAL CONTROL LOGIC de iNT INTERRUPT K INTERNAL BUS Locic ~~ 1 -_ IEO 3) zero COUNTER! TIMER Loaic ns ia RESET Figure 3. Functional Block Diagram If a channel is programmed to request an interrupt, the interrupt logic_drives IEO Low at the zero count, and generates an INT signal to the Z80 CPU. When the Z80 CPU responds with interrupt acknowledge (M1 and IORQ), then the interrupt logic arbitrates the CTC internal priorities, and the interrupt control logic places a unique interrupt vector on the data bus. If an interrupt is pending, the interrupt logic holds IEO Low. When the Z80 CPU issues a Return From Interrupt (RETI) instruction, each peripheral device decodes the first byte (ED). If the device has a pending interrupt, it raises EO (High) for one M1 cycle. This ensures that ail lower priority devices can decode the entire RET! instruction and reset properly. CHANNEL CONTROL LoGic TIME CONSTANT REGISTER &-BIT DOWN. b zcio COUNTER CLK/TRG _> cLK PRESCALER | | Figure 4. Counter/Timer Block Diagram INTERNAL BUS Counter/Timer Circuits. The CTC has four independent counter/timer circuits, each containing the logic shown in Figure 4. Channel Control Logic. The channel contral logic receives the 8-bit channel control word when the counter/timer channel is programmed. The channel control logic decodes the control word and sets the following operating conditions: @ Interrupt enable (or disable) m Operating mode (timer or counter) @ Timer mode prescaler factor (16 or 256) m Active slope for CLK/TRG input @ Timer mode trigger (automatic or CLK/TRG input) @ Time constant data word to follow @ Software reset Time Constant Register. When the counter/timer channel is programmed, the time constant register receives and stores an 8-bit time constant value, which can be anywhere from 1 to 256 (0 = 256). This constant is automatically loaded into the down-counter when the countet/timer channel is initialized, and subsequently after each zero count. Prescaler. The prescaler, which is used only in timer mode, divides the system clock frequency by a factor of eithar 16 or 256. The prescaler output clocks the down-counter during timer operation. The effect of the prescaler an the down-counter is a multiplication of the system clock period by 16 or 256. The prescaler factor is programmed by bit 5 of the channel control word. 85Down-Counter. Prior to each count cycle, the down-counter is loaded with the time constant register contents. The counter is then decremented one of two ways, depending on operating mode: mw By the prescaler output (timer mode) @ By the trigger pulses into the CLK/TRG input (counter mode) Without disturbing the down-count, the Z80 CPU can read the count remaining at any time by performing an 1/O read operation at the port address assigned to the CTC channel. When the down-counter reaches the zero count, the ZC/TO output generates a positive-going pulse. When the interrupt is enabled, zero count also triggers an interrupt request signal (INT) from the interrupt logic. PROGRAMMING Each Z80 CTC channel must be programmed prior to operation. Programming consists of writing two words to the '/O port that corresponds to the desired channel. The first word is a control word that selects the operating mode and other parameters; the second word is atime constant, which is a binary data word with a value from 1 to 256. A time constant word must be preceded by a channel contro! word. After initialization, channels may be reprogrammed at any time. If updated control and time constant words are written to a channel during the count operation, the count continues to zero before the new time constant is loaded into the counter. If the interrupt on any Z8O CTC channel is enabled, the programming procedure should also include an interrupt vector. Only one vector is required for all four channels, because the interrupt logic automatically modifies the vector for the channel requesting service. Acontrol word is identified by a1 in bit0. A 1 in bit 2 indicates atime constant word is to follow. interrupt vectors are always addressed to Channel 0, and identified by a0 in bit 0. Addressing. During programming, channels are addressed with the channel select pins CS; and CSp. A 2-bit binary code selects the appropriate channel as shown in the following table. Reset. The CTC has both hardware and software resets. The hardware reset terminates all down-counts and disables all CTC interrupts by resetting the interrupt bits in the control registers. In addition, the ZC/TO and Interrupt outputs go inactive, IEO reflects IEl, and Dg-D7 go to the high-impedance state. All channels must be completely reprogrammed after a hardware reset. The software reset is controlled by bit 1 in the channel contro! word. When a channel receives a software reset, it stops counting. When a software reset is used, the other bits in the control word also change the contents of the channel control register. After a software reset a new time constant word must be written to the same channel. {f the channel control word has both bits D; and Do et to 1, the addressed channel stops operating, pending a new time constant word. The channel is ready to resume after the new constant is programmed. In timer mode, if D3 = 0, operation is triggered automatically when the time constant word is loaded. Channel Control Word Programming. The channel control word is shown in Figure 5. It sets the modes and parameters described below. Interrupt Enable. D7 enables the interrupt, so that an interrupt output (INT) is generated at zero count. Interrupts may be programmed in either mode and may be enabled or disabled at any time. Channel CS, CSo 0 0 0 Mode. Dg selects either timer or counter operating mode. 1 0 1 Prescaler Factor. (Timer Mode Only). Ds selects 2 1 0 factoreither 16 or 256. 3 1 1 [0], [0; 1D, [05 [02], | O | INTERRUPT J L CONTROL OR VECTOR 1 ENABLES INTERRUPT - 0 DISABLES INTERRUPT MODE 0 SELECTS TIMER MODE 1 SELECTS COUNTER MODE 0 = VECTOR 1 = CONTROL WORD RESET 0 = CONTINUED OPERATION 4 = SOFTWARE RESET PRESCALER VALUE* 1 = VALUE OF 256 0 = VALUE OF 16 TIME CONSTANT 0 = NO TIME CONSTANT FOLLOWS 1 = TIME CONSTANT FOLLOWS CLKITAG EDGE SELECTION 0 SELECTS FALLING EDGE 1 SELECTS RISING EDGE TIMER T 0 = AUTOMATIC TRIGGER WHEN TIME CONSTANT IS LOADED 1 = CLK/TRG PULSE STAATS TIMER TIMER MODE ONLY Figure 5. Channel Control Word 86Clock/Trigger Edge Selector. D4 selects the active edge or slope of the CLK/TRG input pulses. Note that reprogramming the CLK/TRG slope during operation is equivalent to issuing an active edge. If the trigger slope is changed by a control word update while a channel is pending operation in timer mode, the result is the same as a CLK/TRG pulse and the timer starts. Similarly, if the channel is in counter mode, the counter decrements. Timer Trigger (Timer Mode Only). D3 selects the trigger mode for timer operation. When Ds is reset to 0, the timer is triggered automatically. The time constant word is programmed during an I/O write operation, which takes one machine cycle. At the end of the write operation there is a setup delay of one clock period. The timer starts automatically (decrements) on the rising edge of the second clock pulse (Tz) of the machine cycle following the write operation. Once started, the timer runs continuously, At zero count the timer reloads automatically and continues counting without interruption or delay, until stopped by a reset. When Ds is set to 1, the timer is triggered externally through the CLK/TRG input. The time constant word is programmed during an 1/O write operation, which takes one machine cycle. The timer is ready for operation on the rising edge of the second clock pulse (T2) of the following machine cycle. Note that the first timer decrement follows the active edge of the CLK/TRG pulse by a delay time of one clock cycle if a minimum setup time to the rising edge of clock is met. If this minimum is not met, the delay is extended by another clock period. Consequently, for immediate triggering, the CLK/TRG input must precede Ts by one clock cycle plus its minimum setup time. If the minimum time is not met, the timer will start on the third clock cycle (T3). Once started the timer operates continuously, without interruption or delay, until stopped by a reset. Time Constant. A 1 in De indicates that the next word addressed to the selected channel is a time constant data word for the time constant register. The time constant word may be written at any time. A0 in Do indicates no time constant word is to follow. This is ordinarily used when the channel is already in operation and the new channel control word is an update. A channel will Figure 6. Time Constant Word not operate without a time constant value. The only way to write a time constant value is to write a control word with Do set. Software Reset. Setting D,; to 1 causes a software reset, which is described in the Reset section. Control Word. Setting Dp to 0 identifies the word as a control word. Time Constant Programming. Before a channel can start counting it must receive a time constant word from the CPU. During programming or reprogramming, a channel contro! word in which bit 2 is set must precede the time constant word to indicate that the next word is a time constant. The time constant word can be any value from 1 to 256 (Figure 6). Note that 004g is interpreted as 256. In timer mode, the time interval is controlled by three factors: m The system clock period (CLK) m The prescaler factor (P), which multiplies the interval by either 16 or 256 @ Thetime constant (1), which is programmed into the time constant register Consequently, the time interval is the product of CLK x P x T. The minimum timer resolution is 16 x CLK (4ys with a 4MHz clock). The maximum timer interval is 256 x CLK x 256 (16.4 ms with a 4MHz clock). For longer intervals timers may be cascaded. interrupt Vector Programming. If the Z80 CTC has one or more interrupts enabled, it can supply interrupt vectars to the Z80 CPU. To do so, the Z80 CTC must be pre-programmed with the most-significant five bits of the interrupt vector. Programming consists of writing a vector word to the 1/O port corresponding to the Z80 CTC Channel 0. Note that Do of the vector word is always zero, to distinguish the vector from a channel control word. D, and Dg are not used in programming the vector word. Thes bits are supplied by the interrupt logic to identify the channel requesting interrupt service with a unique interrupt vector (Figure 7). Channel 0 has the highest priority. L 0 = INTERRUPT VECTOR WORD oe + = CONTROL WORD V7-V. SUPPLIED BY USER CHANNEL IDENTIFIER {AUTOMATICALLY INSERTED BY CTC) 0 0 = CHANNEL O = CHANNEL 1 CHANNEL 2 o4 1052 1. 1 = CHANNEL 3 Figure 7. Interrupt Vector Word 87PIN DESCRIPTION CE. Chip Enable (input, active Low). When enabled the CTC accepts control words, interrupt vectors, or time constant data words from the data bus during an I/O write cycle; or transmits the contents of the downcounter to the CPU during an I/O read cycle. In most applications this signal is decoded from the eight least significant bits of the address bus for any of the four I/O port addresses that are mapped to the four counter-timer channels. CLK. System Clock (input). Standard single-phase Z80 system clock. CLK/TRGo-CLK/TRG3. External Clock/Timer Trigger (input, user-selectable active High or Low). Four pins corresponding to the four Z80 CTC channels. In counter mode, every active edge on this pin decrements the downcounter. In timer mode, an active edge starts the timer. CS -CS,. Channel Select (inputs active High). Two-bit binary address code selects one of the four CTC channels for an I/O write or read (usually connected to Ag and Aj). SYSTEM BUSES +SV * tel ZCITO, cpu PIO Wet J cTc zciTO2 INT (EO tel __ 10 RxCA INT INT TxcA 1EO tet Axce TxCB WIRDYB RDY silo DMA Figure 8. A Typical 280 Environment Do-D7. System Data Bus (bidirectional, 3-state). Transfers all data and commands between the Z80 CPU and the Z80 CTC. 1El. interrupt Enable In (input, active High). A High iridicates that no other interrupting devices of higher priority in the daisy chain are being serviced by the Z80 CPU. 1EO. interrupt Enable Out (output, active High). High only if IEl is High and the Z80 CPU is not servicing an interrupt from any Z80 CTC channel. IEO blocks tower. priority devices from interrupting while a higher priority interrupting device is being serviced. INT. Interrupt Request (output, open drain, active Low). Low when any Z80 CTC channel that has been programmed to enable interrupts as a zero-count condition in its downcounter. iORQ. Input/Output Request (input from CPU, active Low). Used with CE and RD to transfer data and channel control words between the Z80_ CPU and the Z80 CTC. During a write cycle, iORQ and CE are active and RD inactive. The Z80 CTC does not receive a specific write signal; rather, it internally generates is own from the inverse of an active RD signal. In a read cycle, iORQ, CE, and RD are active; the contents of the downcounter are read by the 280 CPU. If TORG and Mi are both true, the CPU is acknowledging an interrupt request, and the highest priority interrupting channel places its interrupt vector on the Z80 data bus. M1. Machine Cycle One (input from CPU, active Low). When Mi and [ORQ are active, the Z80 CPU is acknowledging an interrupt. The Z80 CTC then places an interupt vector on the data bus if it has highest priority, and if achannel has requested an interrupt (INT). RD. Read Cycle_Status (input, active Low). Used in conjunction with TORQ and CE to transfer data and channel control words between the Z80 CPU and the Z80 CTC. RESET. Reset (input active Low). Terminates all down-counts and disables all interrupts by resetting the interrupt bits in all control registers; the ZC/TO and the interrupt outputs go inactive; {EO reflects IE; Dp-D7 go to the high-impedance state. ZC/TOp-ZC/TO2. Zero Count/Timeout (output, active High). Three ZC/TO pins corresponding to 280 CTC channels 2 through 0 (Channel 3 has no ZC/TO pin). In both counter and timer modes the output is an active High pulse when the downcounter decrements to zero.TIMING Read Cycle Timing. Figure 9 shows read cycle timing. This cycle reads the contents of a down-counter without disturbing the count. During clock cycle To, the Z80 CPU initiates a read cycle by driving the following inputs Low: RD, iORQ, and CE. A 2-bit binary code at inputs CS; and CS selects the channel to be read. Mi must be High to distinguish this cycle from an interrupt acknowledge. ty T2 Twa T3 Nh C$o, C81, CE x CHANNEL ADORESS X DATA { ot )} nce Figure 9. Read Cycle Timing Write Cycle Timing. Figure 10 shows write cycle timing for loading control, time constant, or vector words. The CTC does not have a write signal input, so it generates one internally when the read (AD) input is High during T}. During Tz {ORG and CE inputs are Low. M1 must be High to distinguish a write cycle from an interrupt acknowledge. A 2-bit binary code at inputs CS; and CSpq selects the channel to be addressed, and the word being written is placed on the 280 data bus. The data word is latched into the appropriate register with the rising edge of clock cycle T3. in T2 Twa T3 Nh CS$o, CS4, cE x CHANNEL ADDRESS x toRQ \ / _ Fr RD . a _"*? m1 XX Figure 10. Write Cycle Timing DATA Timer Operation. In the timer mode, a CLK/TRG pulse input starts the timer (Figure 11) on the second succeeding rising edge of CLK. The trigger pulse is asynchronous, and it must have a minimum width. A minimum lead time (210 ns) is required between the active edge of the CLK/TRG and the next rising edge of CLK to enable the prescaler on the following clock edge. If the CLK/TRG edge occurs closer than this, the initiation of the timer function is delayed one clock cycle. This corresponds to the start-up timing discussed in the programming section. The timer can also be started automatically if so programmed by the channel! control word. CLK/TRO INTERNAL TIMER START TIMING Figure 11. Timer Mode Timing Counter Operation. In the counter mode, the CLK/TRG pulse input decrements the downcounter. The trigger is asynchronous, but the count is synchronized with CLK. For the decrement to occur on the next rising edge of CLK, the trigger edge must precede CLK by a minimum lead tirne as shown in Figure 12. If the lead time is less than specified, the count is delayed by one clock cycle. The trigger pulsa must have a minimum width, and the trigger period must be at least twice the clock period. If the trigger repetition rate is faster than 3 the clock frequency, then TsCTR(Cs}, AC Characteristics Specification 26, must be met. The ZC/TO output occurs immediately after zero count, and follows the rising CLK edge. cLKITRG INTERNAL COUNTER zciTto Figure 12. Counter Mode Timing 89INTERRUPT OPERATION The Z80 CTC follows the Z80 system interrupt protocol for nested priority interrupts and return from interrupt, wherein the interrupt priority of a peripheral is determined by its location in a daisy chain. Two linesIEl and 1EOin the CTC connect it to the system daisy chain. The device closest to the +5V supply has the highest priority (Figure 13). For additional information on the Z80 interrupt structure, refer to the Z80 CPU Product Specification and the 280 CPU Technical Manual. HIGHEST PRIORITY DEVICE DEVICE 0 DEVICE 1 HI HE tel 1EO nm 11 oO Eb LOWEST PRIORITY DEVICE DEVICE 2 DEVICE 3 rT of 4 EN ae Figure 13. Daisy-Chain Interrupt Priorities +5 . Within the Z80 CTC, interrupt priority is predetermined by channel number: Channel 0 has the highest priority, and Channet 3 the lowest. If a device or channel is being serviced with an interrupt routine, it cannot be interrupted by a device or channel with lower priority until service is complete. Higher priority devices or channels may interrupt the servicing of lower priority devices or channels. A Z80 CTC channel may be programmed to request an interrupt every time its downcounter reaches zero. Note that the CPU must be programmed for interrupt mode 2. Some time after the interrupt request, the CPU sends an interrupt acknowiedge. The CTC interrupt control logic determines the highest priority channel that is requesting an interrupt. Then, if the CTC {El input is High (indicating that it has priority within the system daisy chain) it places an 8-bit th T2 Twa Twa 3 7) DATA VECTOR Figure 14. Interrupt Acknowledge Timing interrupt vector on the system data bus. The high-order five bits of this vector were written to the CTC during the programming process; the next two bits are provided by the CTC interrupt contro! logic as a binary code that iclentifies the highest priority channel requesting an interrupt; the low-order bit is always zero. interrupt Acknowledge Timing. Figure 14 shows interrupt acknowledge timing. After an interrupt request, the 280 CPU sends an interrupt acknowledge (M1 and IORQ). All channels are inhibited from changing their interrupt request status when M1 is activeabout two clock cycles earlier than (ORQ. RD is High to distinguish this cycle from an instruction fetch. The CTC interrupt logic determines the highest priority channel requesting an interrupt. If the CTC interrupt enable input (IEl) is High, the highest priority interrupting channel within the CTC places its interrupt vector on the data bus when IORQ goes Low. Two wait states (Twa) are automatically inserted at this time to allow the daisy chain to stabilize. Additional wait states may be added. Return from interrupt Timing. At the end of an interrupt service routine the RETI (Return From Interrupt) instruction initializes the daisy chain enable lines for proper contro! of nested priority interrupt handling. The CTC decodes the 2-byte RET! code internally and determines whether it is intended for a channel being serviced. Figure 15 shows RETI timing. If several Z80 peripherals are in the daisy chain, IEI settles active (High) on the chip currently being serviced when the opcode ED4 is decoded. If the following opcode is 4D 4g, the peripheral being serviced is released and its IEO becomes active. Additional wait states are allowed. th T2 T3 T YW Tz T3 Te Do-D7 { D 4 0 ) _ se te Jy 1EO / Figure 15. Return From Interrupt TimingABSOLUTE MAXIMUM RATINGS Voltages on Vcc with respect toVsg ..... ~0.3V to +7.0V Voltages on all inputs with respect toVsg eee ~0.3V to Voc + 0.3V Storage Temperature......0....... ~65C to + 150C Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress raling only; operation of the device at any condition above these indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. STANDARD TEST CONDITIONS The characteristics below apply for the following test conditions, unless otherwise noted. All voltages are +8 referenced to GND (OV). Positive current flows into the referenced pin. Available operating temperature range is: 2.1K @ S=0C to +70C, V., Range FROM OUTPUT NMOS: +4.75V $V. < +5.25V UNDER TEST CMOS: +4.50V < V,, $ +5.50V _ @ E= -40C to 100C, +4.50V <V, $ +5.50V 250 The Ordering Information section lists package temperature 100 Pf nA ranges and product numbers. Refer to the Literature List for additional documentation. Package drawings are in the Package Information section. = SF = DC CHARACTERISTICS (z84C30/CMOS Z80 CTC) Voc=5-0V + 10%, unless otherwise specified Symbol Parameter Min Max Unit Condition Vac Clock Input Low Voltage -0.3 +0.45 Vv Veec Clock Input High Voltage Ve,70.6 Voct 0.3 -V Ve Input High Voltage 2.2 Voce V Vas Input Low Voltage -0.3 0.8 V Va. Output Low Voltage 0.4 Vv |, 9=2.0MA Vou Output High Voltage 2.4 Vv lgy=- 1 6mA Vow Output High Voltage Voe-0.8 Vv I y=-250pA My Input Leakage Current -10 10 BA Vy=0.4V to V,. lo 3-state Output Leakage Current in Float -10 10 pA Va =0.4V to Vo, loos Power Supply Current - 4MHz 7 {ij mA Veg 5V - 6MHHz 8 [1] mA CLK=4,.6,8, 1OMHz - 8MHz 10 [1] mA Vag=Vo-0.2V - 10MHz 12 [1] mA V, =0.2V loco Standby Supply Current 10 pA Vop=5V CLK=(0) Vy Veg-0-2V V,=0.2V lava Darlington Drive Current 1.5 -5.0 mA Voy= 1.SV REXT=1.1K ohm Note: [1] Measurements made with outputs floating. CAPACITANCE Symbol Parameter Max Unit CLK Clock Capacitance 10 pf Cin input Capacitance 10 pf Cout Output Capacitance 15 pf Ta = 25C, f = 1 MHz Unmeasured pins returned to ground. 91AC CHARACTERISTICS (Z84C30/CMOS Z80 CTC) 92AC CHARACTERISTICS (Z84C30/CMOS 280 CTC Continued) 284C3004* Z84C3006 Z84C3008 784C3010 Note No Symbol Parameter Min Max Min Max Min Max Min Max 1 TcC Clock Cycle Time 250 [1] 162 [1] 125 [1] 100 [1] 2 Tweh Clock pulse Width (High) 110 DC 65 DC 55 DC 42 DC 3 Twi Clock pulse Width (Low) 110 DC 65 DC 55 DC 42 DC 4 Tic Clock Falt Time 30 20 10 10 5 TrC Clock Rise Time 30 20 10 10 6 Th All Hold Times 0 0 0 0 7 TsCS(C) ICS to Clock Rise Setup Time 160 100 50 35 8 TsCE(C) ICE to Clock Rise Setup Time 150 100 50 35 9 TsIQ(C) /ORQ to Clock Rise Setup Time 115 70 40 35 10 TsRD(C) /RD Falt.to Clock Rise Setup Time 115 70 40 35 11. TdC(DO) Clock Rise to Data Out 200 130 90 90 (2) Float Delay 12 TdRir(DOz) /RD, /ORQ rising to Data Outime 50 40 40 40 Float Delay 13 TsDI (C) Data In to Clock rising set-up 50 40 30 30 14 TsM1(C) /M1 to Clock Rise Setup Time 90 70 ~ 0 40 15 TdM1(IEO) /M1 Fall to IEO Fall Delay (Interrupt Immediately Preceding 190 130 90 70 [3] /M1 Fatt) : 16 TdlO(DIO) /IORQ Fall to Data Out Delay 160 110 80 80 [2,6] (AINTACK Cycle) 17 TdIEKIEOf) EI Fall to 1EO Fall Delay 130 100 70 70 [3] 18 TdIEKIEOr) {El Rise to JEO Rise Delay 160 110 70 70 [3} (After ED Decode) 19 TdC(INT) Clock Rise to /INT Fail Delay (TcC+140) (TcC+120) (TcC+100) (TcC+80) [4] 20 TdCLK(INT) CLK/TRG Rise to /INT Fall Delay TsCTR(C) Satisfied (19)+(26) (19)+(26) (19)+(26) (419)+(26) [5] TsCTR(C) Not Satisfied (1)+(19)+(26) (1)+(19)+(26) (1)+(19)4+(26) (1)+(19)+(26) [5] 21 TcCTR CLK/TRG Cycle Time (2TcC) (2TcC) (2TcC) (2TcC) [5] 22 TrCTR CLK/TRG Rise Time 50 40 30 30 23 TICTR CLK/TRG Fall Time 50 40 30 30 24 TwCTRh CLK/TRG Width (Low) 200 120 90 90 25 TwCTR! CLK/TRG Width (High) 200 120 90 90 26 TsCTR(Cs) CLK/TRG Rise to Clock Rise 210 150 110 90 (5]} Setup Time for Immediate Count 27 TsCTR(Ct) CLK/TRG Rise to Clock Rise 210 150 110 90 [4] Setup Time for Enabling of Prescaler On Following Clock Rise * 4 MHz 284C30 is obsoleted and replaced by 6 MHz 93Z84C30 AC CHARACTERISTICS (Continued) Z84C3004* Z84C3006 284C3008 284C3010 Note No Symbol Parameter Min Max Min Max Min Max Min Max 28 TdC(ZC/TOr) Clock Rise to ZC/TO Rise Delay 190 140 100 80 29 TdC(ZC/TOL) Clock Fall to ZC/TO Fall Delay 190 140 100 80 30. ThRir(D) ICE, AORQ Rise to Data Hold 20 20 10 10 31 ThC(CS) Clock Rise to /CS Hold 20 20 10 10 * RESET must be active for a minimum of 3 clock cycles. Units in Nanoseconds Notes: [1] ToC = TwCh + TwCl + TrC + TIC. [2] Increasing delay by 10nS for each SOpF increase in loading, 200pF max for data lines, and 100pF for control fines. [3} Increase delay by 2nS for each 10pF increase in loading, 100pF max. [4] Timer mode. {5] Counter mode. [6] 2.5TcT > (N-2)TdIEKIEOH + TAM1(1EO) + TsIEKIO) + TTL Butter Delay, if any. * 4 MHz Z84C30 is obsoleted and replaced by 6 MHz 94DC CHARACTERISTICS (z8430/NMOS Z80 CTC) Symbol Parameter Min Max Unit Condition ViLc Clock Input Low Voltage ~0.3 +0.452 v VIHC Clock Input High Voltage Voc ~- 0.64 Voc +0.3b Vv Vit input Low Voltage -0.3 +0.84 Vv Vt Input High Voltage +2.28 Vec> v Vou Output Low Voltage +0.48 Vv lo. = 2.0mA VoH Output High Voltage +2.4a Vv lou = 250 pA loc Power Supply Current: +1208 mA lu Input Leakage Current +108 pA Vin = 0.4toVcc Ilo 3-State Output Leakage Current in Float +108 pA Vout = 0.4 to Voc loHD Darlington Drive Current - 1.54 mA VoH = 1.5V Rext = 390Q CAPACITANCE Symbol Parameter Max Unit CLK Clock Capacitance 20 pf Cin Input Capacitance 5 pf Cout Output Capacitance 16 pf Ta = 25C, t = 1 MHz Unmeasured pins returned to ground. Parameter Test Status: 8 Tested D Guaranteed Guaranteed by characterization/design 95AC CHARACTERISTICS (Z8430/NMOS Z80 CTC Continued) ~IVPRIVLVSN Or) | C0, C81 = * n \, a hO> O>| neaD iona \ Ros or m \. f o>] O>| para = _ ete, 8; Vf "4 E-5TFO- et \. f write O On| iors \. Sf Oo Or bara Vf x hO| -O~ ( om f- EE rs AcKmowLEDaE ( f0RG ff Pon , ve > i " 7 ito \ - f o \ / ce -@-|| @+|-@ ~ of aAC CHARACTERISTICS (28430/NMOS Z80 CTC) Z0843004 20843006 Number Symbol Parameter Min Max Min Max Notest 4 TcC Clock Cycle Time 250 (1) 162 (1] 2 wh Clock Width (High) 105 2000 65 2000 3 Ww Clock Width (Low) 105 2000 65 2000 4 TiC Clock Fall Time 30 20 5 Tc Clock Rise Time 30 20 6 Th All Hold Times 0 0 7 TsCS(C) CS to Clock Setup Time 160 100 8 TsCE(C) CE to Clock t Setup Time 150 100 9 ~ TslO\C) {ORG 4 to Clock t Setup Time 115 70 10 TsRD(C) RD #10 Clock t Setup Time 115 70 11 TdC(DO) Clock t to Data Out Delay 200 130 (2) 12 TdC(DOz) Clock 4 to Data Out Float Delay 110 90 13. TsDKC) Data In to Clock t Setup Time 50 40 14. TsM1(C) Mi to Clock t Setup Time 90 70 15 TdMi(IEOQ) M1 sto EO 4 Delay (Interrupt immediately preceding M1) 190 130 {3] 16 TdlO(OO!) iORQ 4 to Data Out Delay (INTA Cycle) 160 110 (2] 17 TdIEWIEON ~sIEI 4 to lEO + Delay 130 100 (3) 18 TdlEKIEO) EI ttolEOt Delay (After ED Decode) 160 110 [3} 19 TdC(INT) Clock to INT 4 Delay (1) +140 (1) +120 {4.6} - 20 TdCLK(INT) CLK/TRGttoiNTs tsCTR(C) satisfied (19) + (26) (19) + (26) [5.6] tsCTR(C) not satistied (1) + (19) + (26) (1)+(19)+(26) [5.6] 21. TcCTR , CLK/TRG Cycle Time 2TcC 2TcC (5) 22 CTR CLK/TRG Rise Time 50 40 23 ~sTICTR CLK/TRG Fall Time 50 40 24 WCTRI CLK/TRG Width (Low) 200 120 25. WwCTRh CLK/TRG Width (High) 200 120 NOTES: {1] TcC = TwCh + WCl + TC + TIC. [2] increase delay by 10 ns for each 50 pf increase in loading, 200 pf maximum for data lines, and 100 pf for control lines. [3] Increase delay by 2 ns for each 10 pf increase in loading, 100 pf maximum. [4] Timer mode [5] Counter mode. [6] Parenthetical numbers reference the table number of a parameter. e.g, (1) refers to TcC. + 2.5 TcC > (n- 2) TDIEMIEOR + TOM1(1EO) + TsIEWIO) + TTL iouffer delay, if any. RESET must be active for a minimum of 3 clock cyties. Units are nanoseconds unless otherwise specified. 97AC CHARACTERISTICS (Z8430/NMOS Z80 CTC Continued) 20843004 20843006 Number Symbol! Parameter Min Max Min Max Notest 26 TsCTR(Cs) CLK/TRG tto Clock t Setup Time for Immediate Count 210 150 (5] 27 TsCTR(Ct) ~CLK/TRG f to Clock t Setup , Time for enabling of Prescaler on following clock t 210 150 [4] 28 TdC(ZC/TOr Clock t to ZC/TO t Delay -190 140 29 = TdC(ZC/TOA) Clock $ to ZC/TO # Delay 190 140 NOTES: [1] TcC = WCh + WC! + WC + TIC. [2] Increase delay by 10 ns for each 50 pf increase in loading, 200 pf maximum for data lines, and 100 pt for control lines. {3} Increase delay by 2 ns for each 10 pf increase in loading. 100 pf maximum. (4) Timer mode [5] Counter mode. [6] Parenthetical numbers reference the table number of a parameter. e.g., (1) refers to TcC. t2.5TcC >(n- 2 TDIEKIEON + TDM1(IEO) + TsIEK(IO) + TTL butter delay, if any. ET must be active for a minimum of 3 clock cycles. Units are nanoseconds unless otherwise specified. 98