©2001 Fairch ild Semicond uctor C orpo ration HUF76407P3 Rev. B
HUF76407P3
12A, 60 V, 0.107 Ohm, N-Channel, Logic
Level UltraFET® Power MOSF ET
Packaging
Symbol
Features
• Ultra Low On-Resistance
-r
DS(ON) = 0.092Ω, VGS = 10V
-r
DS(ON) = 0.107Ω, VGS = 5V
• Simulation Models
- Temperature Compensated PSPIC E® and SABER™
Electr ical Models
- Spice and SABER Thermal Impedance Mo de ls
- www.fairchildsemi.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Switching Time vs RGS Curves
Ordering Information
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
For severe environments, see our Autom otive HUF A series.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 qualit y systems certification.
JEDEC TO-220AB
DRAIN
(FLANGE)
DRAIN
SOURCE
GATE
HUF76407P3
D
G
SPART NUMBER PACKAGE BRAND
HUF76407P3 TO-220AB 76407P
NOTE: When ordering, use the entir e part number.
HUF76407P3 UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS 60 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 60 V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±16 V
Drain Current
Continuous (TC = 25oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC = 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC = 135oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC = 135oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
12
13
6
6
Figure 4
A
A
A
A
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS Figures 6, 17, 18
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
0.25 W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 175 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300
260
oC
oC
NOTE:
1. TJ = 25oC to 150oC.
CAUTION: Stresse s above those listed in “Ab solute Maximum Ratings” may cause perman ent damage to th e device. This is a stress only ratin g and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Data Sheet December 2001
©2001 Fairch ild Semicond uctor C orpo ration HUF76407P3 Rev. B
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
OFF STATE SPECIFICATIONS
Drain to Source B reakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 12) 60 - - V
ID = 250µA, V GS = 0V , TC = -40oC (Figure 12) 55 - - V
Zero Gate Vo ltage Drain C urrent IDSS VDS = 55V, VGS = 0V - - 1 µA
VDS = 50V, VGS = 0V, TC = 150oC - - 250 µA
Gate to Source Leakage Current IGSS VGS = ±16V - - ±100 nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 11) 1 - 3 V
Drain to Source On Resist ance rDS(ON) ID = 13A, VGS = 10V (Figures 9, 10) - 0.077 0.092 Ω
ID = 8A, VGS = 5V (Figure 9) - 0.095 0.107 Ω
ID = 8A, VGS = 4. 5V (Figure 9) - 0.107 0.117 Ω
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case RθJC TO-220 - - 3.94 oC/W
Thermal Resistance Junction to
Ambient RθJA --62
oC/W
SWITCHING SPECIFICATIONS (VGS = 4.5V)
Turn-On Time tON VDD = 30V, ID = 8A
VGS = 4.5V, RGS = 32Ω
(Figures 15, 21, 22)
- - 170 ns
Turn-On De lay Time td(ON) -8-ns
Rise Time tr- 105 - ns
Turn-Off De lay Time td(OFF) -22-ns
Fall Tim e tf-39-ns
Turn-Off T ime tOFF - - 92 ns
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time tON VDD = 30V, ID = 13A
VGS = 10V,
RGS = 32Ω
(Figures 16, 21, 22)
- - 56 ns
Turn-On De lay Time td(ON) -5-ns
Rise Time tr-32-ns
Turn-Off De lay Time td(OFF) -43-ns
Fall Tim e tf- 45 - ns
Turn-Off T ime tOFF - - 132 ns
GATE CHARGE SPECIFICATIONS
Total Gate Charge Qg(TOT) VGS = 0V to 10V VDD = 30V,
ID = 8A,
Ig(REF) = 1.0mA
(Figures 14, 19, 20)
- 9.4 11.3 nC
Gate Charge at 5V Qg(5) VGS = 0V to 5V - 5.2 6.2 nC
Threshold Gate Charge Qg(TH) VGS = 0V to 1V - .36 .43 nC
Gate to Source Gate C harge Qgs -1.2-nC
Gate to Drain “Miller” Charge Qgd -2.5-nC
CAPACITANCE SPECIFICATIONS
Input Capacitance CISS VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 13)
- 350 - pF
Output Capacitance COSS - 105 - pF
Reverse Transfer Capacitance CRSS -23-pF
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to D rain Diode Volt age VSD ISD = 8A - - 1.25 V
ISD = 4A - - 1.0 V
Reverse Recovery Time trr ISD = 8A, dISD/dt = 100A/µs--66ns
Reverse Recovered Charge QRR ISD = 8A, dISD/dt = 100A/µs - - 159 nC
HUF76407P3
©2001 Fairch ild Semicond uctor C orpo ration HUF76407P3 Rev. B
Typical Performance Curves
FIGURE 1. NORMALIZED PO WER DISSIPA TI ON vs CASE
TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. PEAK CURRENT CAPABILITY
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
00 25 50 75 100 17
5
0.2
0.4
0.6
0.8
1.0
1.2
125 150
5
10
15
25 50 75 100 125 150 17
5
0
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
VGS = 10V
VGS = 4.5V
0.1
1
10-5 10-4 10-3 10-2 10-1 100101
0.01
2
t, RECTANGULAR PULSE DURATION (s)
ZθJC, NORMALIZED
SINGLE PULSE NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
PDM
t1t2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
THERMAL IMPEDANCE
100
10-5 10-4 10-3 10-2 10-1 10010
1
200
10
IDM, PEAK CURRENT (A)
t, PULSE WIDTH (s)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
TC = 25oC
I = I25 175 - TC
150
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLO WS:
VGS = 5V
HUF76407P3
©2001 Fairch ild Semicond uctor C orpo ration HUF76407P3 Rev. B
FIGURE 5. FORWARD BIAS SAFE O PERATING AREA
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SATURATION CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
Typical Performance Curves (Continued)
1
10
100
110100
0.1
20
0
100
µ
s
10ms
1ms
VDS, DRAIN TO SOURCE VOLTAGE (V)
I
D
, DRAIN CURRENT (A)
LIMITED BY rDS(ON)
AREA MAY BE
OPERATION IN THIS
TJ = MAX RATED TC = 25oC
SINGLE PULSE
10
100
0.001 0.01 0.1 1 1
0
1
IAS, AVALANCHE CURRENT (A)
tAV, TIME IN AVALANCHE (ms)
STARTING TJ = 25oC
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R = 0
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
STA RTING TJ = 150oC
3
6
9
12
15
2345
0
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
TJ = 175oC
TJ = 25oC
TJ = -55oC
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 3V
VGS = 5V
VGS = 10V
VGS = 4V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
3
6
9
12
15
01234
0
VGS = 3.5V
Tc = 25oC
90
120
150
24681
0
60
ID = 3A
VGS, GATE TO SOURCE VOLTAGE (V)
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
PULSE DURATION = 80µs
DUTY CYCLE = 0 .5% MAX
TC = 25oC
ID = 12A
ID = 5A
1.0
1.5
2.0
2.5
-80 -40 0 40 80 120 160 20
0
0.5
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATURE (oC)
ON RESISTANCE
VGS = 10V, ID = 1 3A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
HUF76407P3
©2001 Fairch ild Semicond uctor C orpo ration HUF76407P3 Rev. B
FIGURE 11. NORMALIZED GATE THRESHOLD V OLTAGE vs
JUNCTION TEMPERATURE FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMP ERATURE
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 14. GA TE CHARGE W AVEFORMS FOR CONSTANT
GATE CURRENT
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Typical Performance Curves (Continued)
0.8
1.0
1.2
-80 -40 0 40 80 120 160 200
0.6
NORMALIZED GATE
TJ, JUNCTION TEMPERATURE (oC)
VGS = VDS, ID = 250µA
THRESHOLD VOLTAGE
1.0
1.1
1.2
-80 -40 0 40 80 120 160 200
0.9
TJ, JUNCTION TEMPERAT URE (oC)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
ID = 250µA
100
1000
0.1 1.0 10 60
10
C, CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 0V, f = 1MHz
CISS = CGS + CGD
COSS @ CDS + CGD
CRSS = CGD
2
4
6
8
10
024681
0
0
V
GS
, GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
VDD = 30V
I
D
= 12A
I
D
= 5A
WAVEFORMS IN
DESCENDING ORDER:
I
D
= 3A
50
100
150
0 102030405
0
0
SWITCHING TIME (ns)
RGS, GAT E TO SO URCE RESISTANCE (Ω)
VGS = 4.5V, VDD = 30V, ID = 6A
tr
tf
td(ON)
td(OFF) 20
40
60
80
0 102030405
0
0
SWITCHING TIME (ns)
RGS, GAT E TO SO URCE RESISTANCE (
Ω
)
VGS = 10V, VDD = 30V, ID = 12A
tr
td(ON)
tf
td(OFF)
HUF76407P3
©2001 Fairch ild Semicond uctor C orpo ration HUF76407P3 Rev. B
Test Circuits and Waveforms
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 18. UNCLAMPED ENERGY W AVEFORMS
FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS
FIGURE 21. SWITCHING TIME TEST CIRCUIT FIGURE 22. SWITCHING TIME WAVEFORM
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
RL
VGS +
-
VDS
VDD
DUT
Ig(REF)
VDD
Qg(TH)
VGS = 1V
Qg(5)
VGS = 5V
Qg(TOT)
VGS = 10
V
VDS
VGS
I
g(REF)
0
0
Qgs Qgd
VGS
RL
RGS DUT
+
-VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
HUF76407P3
©2001 Fairch ild Semicond uctor C orpo ration HUF76407P3 Rev. B
PSPICE Ele ctrical Model
.SUBCKT HUF76407 2 1 3 ; rev 28June 1999
CA 12 8 3.9e-9
CB 15 14 4.9e-9
CIN 6 8 3.25e-10
DBODY 7 5 DBODYMOD
DBRE AK 5 11 D B REAK MOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 67.8
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTH R ES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRA IN 2 5 1.0e - 9
LGATE 1 9 5.42e-9
LSOURCE 3 7 2.57e-9
MMED 16 6 8 8 MME DMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 3.7e-2
RGATE 9 20 3.37
RLDRAIN 2 5 10
RLGATE 1 9 54.2
RLSOURCE 3 7 2 5.7
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 2.50e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTE M P 18 19 RVTE MPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMO D
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMO D
VBAT 22 1 9 DC 1
ESL C 51 50 VALU E={( V(5,51) /ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*30),3))}
.MODEL DBOD YMOD D (IS = 1.75e-13 RS = 1.75e-2 TRS1 = 1e-4 TRS2 = 5e-6 CJO = 5.9e-10 TT = 5.45e-8 N = 1.03 M = 0.6)
.MODEL DBREAKMOD D (RS = 6.50e- 1TRS1 = 1.25e- 4TRS2 = 1.34e-6)
.MODEL DPLC APMOD D (CJO = 3.21e-1 0IS = 1e-3 0N = 10 M = 0.81)
.MODEL MMEDM OD NMO S (VTO = 2.02 KP = .83 I S = 1e-3 0 N = 10 T OX = 1 L = 1u W = 1u RG = 3.37)
.MODEL MSTRO M OD NMOS (VTO = 2.39 KP = 14 IS = 1e-30 N = 10 TO X = 1 L = 1u W = 1u)
.MODEL MWEAKMOD N MOS ( VTO = 1.78 K P = 0.02 IS = 1e-3 0 N = 10 TO X = 1 L = 1u W = 1u RG = 33.7 RS = 0. 1)
.MODEL RBREAK MOD R ES (TC1 = 1.06e- 3TC2 = 0)
.MODEL RDRAINMOD RES (TC1 = 1.23e-2 TC2 = 2.58e-5)
.MODEL RSLCMOD RES (TC1 = 0 TC2 = 0)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -2.19e-3 TC2 = -4.97e-6)
.MODEL RVTEMPMO D RES (TC1 = -1.6e- 3TC 2 = 1e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4 VOFF= -2.5)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.5 VOFF= -4)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.5 VOFF= 0)
.MODEL S2BMOD VS WITCH (RON = 1e-5 ROFF = 0.1 VON = 0 VOFF= -0.5)
.ENDS
NOT E: For further discussion of the PSPICE model, consult A New PSPI CE Sub-Circuit for the Power M OSFET Featu ring Gl obal
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, writt en by William J. Hepp and C. Frank Wheatley.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
HUF76407P3
©2001 Fairch ild Semicond uctor C orpo ration HUF76407P3 Rev. B
SABER Electrical Model
REV 28 June 1999
templ ate huf76407 n2,n 1 , n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 1.75e-13, cjo = 5.9e-10, tt = 5.45e-8, n=1.03, m = 0.6)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 3.2 1e-10, is = 1e-30, m = 0.81 )
m..model mmedmod = (type=_n, vto = 2.02, kp = .83, i s = 1e-30, tox = 1)
m..model mstrongmod = ( type=_n, vto = 2 .39, kp = 14, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.78, kp = 0.02, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4, voff = -2.5)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.5, voff = -4)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0, voff = -0.5)
c.ca n12 n8 = 3.9e-10
c.cb n15 n14 = 4.9e-10
c.cin n6 n8 = 3.25e-10
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1.0-9
l.lgate n1 n9 = 5.42e-9
l.lsourc e n3 n7 = 2.57e-9
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res. rb r ea k n17 n18 = 1, tc1 = 1.06e- 3, tc2 = 0
res.rdbody n71 n5 = 1.75e-2, tc1 = 1e-4, tc2 = 5e-6
res.rdbreak n72 n5 = 6.50e-1, tc1 = 1.25e-4, tc2 = 1.34e-6
res.rdrain n50 n16 = 3.7e-2, tc1 = 1.23e-2, tc2 = 2.58e-5
res.rgate n9 n20 = 3.37
res.r ldrain n2 n5 = 10
res.rlgate n1 n9 = 54.2
res.rlsource n3 n7 = 25.7
res.rslc1 n5 n51 = 1e-6, tc1 = 0, tc2 =0
res.r slc2 n5 n50 = 1e3
res.rsource n8 n7 = 2.50e-2, tc1 = 1e-3, tc2 =0
res.rvtemp n18 n19 = 1, tc1 = -1.6e-3, tc2 = 1.0e-7
res.rvthres n22 n8 = 1, tc1 = -2.19e-3, tc2 = -4.97e-6
spe.ebreak n11 n7 n17 n18 = 67.8
spe.e ds n14 n8 n5 n8 = 1
spe.e gs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e- 9+abs(v(n5,n51))))*((abs(v (n5,n51)*1e 6/30))** 3))
}
}
18
22
+-
6
8
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
RDBODY
RDBREAK
72
71
HUF76407P3
©2001 Fairch ild Semicond uctor C orpo ration HUF76407P3 Rev. B
SPICE Thermal Model
REV 28June 1999
HUF76407T
CTHERM1 th 6 4.5e-4
CTHERM2 6 5 2 .5e-3
CTHERM3 5 4 1 .9e-3
CTHERM4 4 3 2 .6e-3
CTHERM5 3 2 5 .5e-3
CTHERM6 2 tl 1.8e-2
RTHERM1 th 6 3.1e-2
RTHERM2 6 5 1 5.1e-2
RTHERM3 5 4 4 .2e-1
RTHERM4 4 3 8 .4e-1
RTHERM5 3 2 8 .7e-1
RTHERM6 2 tl 1.5
SABER Thermal Model
SABER thermal model HUF76407T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm 1 t h 6 = 4.5e-4
ctherm.ctherm 2 6 5 = 2.5e- 3
ctherm.ctherm 3 5 4 = 1.9e- 3
ctherm.ctherm 4 4 3 = 2.6e- 3
ctherm.ctherm 5 3 2 = 5.5e- 3
ctherm.ctherm6 2 tl = 1.8e-2
rtherm.rtherm1 th 6 = 3.1e-2
rtherm.rtherm2 6 5 = 15.1e-2
rtherm.rtherm3 5 4 = 4.2e-1
rtherm.rtherm4 4 3 = 8.4e-1
rtherm.rtherm5 3 2 = 8.7e-1
rtherm.rtherm6 2 tl = 1.5
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th JUNCTION
CASE
HUF76407P3
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