HD6432645 - Renesas Technology / Hitachi Semiconductor

Regarding the change of names mentioned in the document, such as Hitachi

Electric and Hitachi XX, to Renesas Technology Corp.

The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas

Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog

and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)

Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand

names are mentioned in the document, these names have in fact all been changed to Renesas

Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and

corporate statement, no changes whatsoever have been made to the contents of the document, and

these changes do not constitute any alteration to the contents of the document itself.

Renesas Technology Home Page: http://www.renesas.com

Renesas Technology Corp.

Customer Support Dept.

April 1, 2003

To all our customers

Cautions

Keep safety first i n your circ uit desi gns!

1. Renesas Technology Corporation puts the maximu m effort into making semiconductor product s better and more reliable, but

ther e is always the possibility that trouble may occur with them. Trouble with semiconductor s may lead to personal injury, fire

or property damage.

Remembe r to give du e consider ation to sa fety when making your circuit designs, with appropriate measures such as (i)

placement of sub sti tut ive, au x iliar y circ uits , (ii) u se of nonf lam ma ble mate ria l or (iii) pr even tio n agai n st any malf u ncti on or

mishap.

Note s regardin g t hese materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation

product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any

other rights, belonging to Renesas Technology Corporation or a third party.

2. Renesas Technology Corporation assumes no responsibility for any damage , or infringement of any third -party's rights,

originating in the use of any product d ata, diagrams, charts, programs, algorit hms, or circuit application examples contained in

these materials.

3. All in formation contained in these materials, includi ng product data, diagrams, charts, pr ograms and algorithms represents

information on products at the time of publication of these materials, and are subject to change by Renesas Technology

Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact

Renesas Technology Corporation or an authorized Renesas Technology Corpor ation product distributor for the latest product

informatio n before pur chasing a product listed here i n.

The i nf o rm ation de scribed here may co ntain tech nical inac curacie s or ty p og r aphical er rors.

Renesas Technology Corporatio n assumes no responsibili ty for any damage , liability, or other loss rising from these

inaccuracie s or error s.

Please also pay attention to information publi shed by Renesas Technology Corporation by various means, including the

Renesas Technology Corporation Semiconductor home page (htt p://www.renesas.com ).

4. When usin g a n y or al l of the information contained in these m aterials, including pr o d uct da t a, diagrams, chart s , programs, and

algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of

the inf ormation and products. Renesa s Technology Corp oration assumes no respons ibility for any damage, liability or other

loss resulting fro m the information contained herein.

5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used

under circumstances in whi ch human life is potentially at st ake. Pl ease contact Rene sas Technology Corporation or an

authorized Renesas Technology Corporation product distributor when consi dering the use of a product cont ained herein fo r

any specific pur pose s, such as ap para tus or system s for tra nsp orta tio n, veh ic ular, med ica l, aero space, nu clear, or unde rs ea

repeater use.

6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these

materials.

7. If these pro ducts or technologies are subject to th e Japanese export control restrict ions, they must be ex ported under a li cense

fro m the Japanese government and cannot be imported into a country other than the ap proved destination.

Any diversion or reexport contrary to the export control laws and regulations of Japan and /or the country of destination is

prohibited.

8. Please contact Renesas Technology Corporation for further details on these ma terials or th e products cont ained therein.

Hitachi 16-Bit Single-Chip Microcomputer

H8S/2646 Series

H8S/2646

HD6432646

H8S/2645

HD6432645

H8S/2647

HD6432647

H8S/2648

HD6432648

H8S/2646R F-ZTAT™

HD64F2646R

H8S/2648R F-ZTAT™

HD64F2648R

Hardware Manual

ADE-602-207C

Rev. 4.0

9/20/02

Hitachi, Ltd.

The revision list can be viewed directly by 

clicking the title page.

The revision list summarizes the locations of 

revisions and additions. Details should always 

be checked by referring to the relevant text.

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s

patent, copyright, trademark, or other intellectual property rights for information contained in

this document. Hitachi bears no responsibility for problems that may arise with third party’s

rights, including intellectual property rights, in connection with use of the information

contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you

have received the latest product standards or specifications before final design, purchase or

use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.

However, contact Hitachi’s sales office before using the product in an application that

demands especially high quality and reliability or where its failure or malfunction may directly

threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear

power, combustion control, transportation, traffic, safety equipment or medical equipment for

life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi

particularly for maximum rating, operating supply voltage range, heat radiation characteristics,

installation conditions and other characteristics. Hitachi bears no responsibility for failure or

damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,

consider normally foreseeable failure rates or failure modes in semiconductor devices and

employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi

product does not cause bodily injury, fire or other consequential damage due to operation of

the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document

without written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi

semiconductor products.

General Precautions on the Handling of Products

1. Treatment of NC Pins

Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are

used as test pins or to reduce noise. If something is connected to the NC pins, the

operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins

Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are high-impedance input pins. If unused pins

are in their open states, intermediate levels are induced by noise in the vicinity, a pass-

through current flows internally, and a malfunction may occur.

3. Processing before Initialization

Note: When power is first supplied, the product’s state is undefined. The states of internal

circuits are undefined until full power is supplied throughout the chip and a low level is

input on the reset pin. During the period where the states are undefined, the register

settings and the output state of each pin are also undefined. Design your system so that it

does not malfunction because of processing while it is in this undefined state. For those

products which have a reset function, reset the LSI immediately after the power supply has

been turned on.

4. Prohibition of Access to Undefined or Reserved Address

Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers

may have been be allocated to these address. Do not access these registers: the system’s

operation is not guaranteed if they are accessed.

Preface

The H8S/2646 Series is a series of high-performance microcontrollers with a 32-bit H8S/2600

CPU core, and a set of on-chip supporting functions required for system configuration.

This LSI is equipped with a 16-bit timer pulse unit (TPU), programmable pulse generator (PPG),

watchdog timer (WDT), serial communication interface (SCI), A/D converter, motor control

PWM timer (PWM), LCD controller/driver (LCDC) and I/O ports as on-chip supporting modules.

In addition, data transfer controller (DTC) is provided, enabling high-speed data transfer without

CPU intervention. This LSI is suitable for use as an embedded processor for high-level control

systems. Its on-chip ROM are flash memory (F-ZTAT™*) that provides flexibility as it can be

reprogrammed in no time to cope with all situations from the early stages of mass production to

full-scale mass production. This is particularly applicable to application devices with

specifications that will most probably change.

Note: * F-ZTAT™ is a trademark of Hitachi, Ltd.

Target Users: This manual was written for users who will be using the H8S/2646 Series in the

design of application systems. Members of this audience are expected to understand

the fundamentals of electrical circuits, logical circuits, and microcomputers.

Objective: This manual was written to explain the hardware functions and electrical

characteristics of the H8S/2646 Series to the above audience. Refer to the

H8S/2600 Series, H8S/2000 Series Programming Manual for a detailed description

of the instruction set.

Notes on reading this manual:

• In order to understand the overall functions of the chip

Read the manual according to the contents. This manual can be roughly categorized into parts

on the CPU, system control functions, peripheral functions and electrical characteristics.

• In order to understand the details of the CPU's functions

Read the H8S/2600 Series, H8S/2000 Series Programming Manual.

• In order to understand the details of a register when its name is known

The addresses, bits, and initial values of the registers are summarized in Appendix B, Internal

I/O Registers.

Example: Bit order: The MSB is on the left and the LSB is on the right.

Related Manuals: The latest versions of all related manuals are available from our web site.

Please ensure you have the latest versions of all documents you require.

http://www.hitachisemiconductor.com/

H8S/2646 Series manuals:

Manual Title ADE No.

H8S/2646 Series Hardware Manual This manual

H8S/2600 Series, H8S/2000 Series Programming Manual ADE-602-083

Users manuals for development tools:

Manual Title ADE No.

C/C++ Complier, Assembler, Optimized Linkage Editor User's Manual ADE-702-247

Simulator Debugger (for Windows) Users Manual ADE-702-037

Hitachi Embedded Workshop Users Manual ADE-702-201

Application Notes:

Manual Title ADE No.

H8S Series Technical Q & A ADE-502-059

List of Items Revised or Added for This Version

Section Page Description

2.10.2 Caution to

observe when using

bit manipulation

instructions

76, 77 Newly added

The BSET, BCLR, BNOT, BST and BIST instructions read data in a unit of byte,

then, after bit manipulation, they write data in a unit of byte. Therefore, caution

must be exercised when executing any of these instructions for registers and

ports that include write-only bits.

The BCLR instruction can be used to clear the flag of an internal I/O register to

0. In that case, if it is clearly known that the pertinent flag is set to 1 in an

interrupt processing routine or other processing, there is no need to read the

flag in advance.

8.3.10 Number of

DTC Execution States 207 4th line changed as follows

Number of execution states = I · (SI +1) + Σ (J · SJ + K · SK + L · SL) + M · SM

For example, when the DTC vector address table is located in on-chip ROM,

normal mode is set, and data is transferred from the on-chip ROM to an internal

I/O register, the time required for the DTC operation is 14 states. The time from

activation to the end of the data write is 11 states.

9.4.2 Register

Configuration

Table 9-6 Port 3

Configuration

242

Name Abbreviation R/W Initial Value Address*

Port 3 data direction register P3DDR W H'00 H'FE32

Port 3 data register P3DR R/W H'00 H'FF02

Port 3 register PORT3 R Undefined H'FFB2

Port 3 open drain control register P3ODR R/W H'00 H'FE46

9.9.2 Register

Configuration 263 15th line changed as follows

In mode 7, if a pin is in the input state in accordance with the settings in the

DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up

for that pin.

9.10.3 Pin Functions

Table 9-20 Port C

Pin Functions

269 (Incorrect)PCDDR

(Correct)PCnDDR

9.13.1 Overview

Figure 9-12 Port F

Pin Functions

281

PF7 (input) / ø (output)

PF6 (I/O) / AS (output) / SEG20 (output) / SEG36* (output)

PF5 (I/O) / RD (output) / SEG19 (output) / SEG35* (output)

Pin functions in modes 4 to 6

Section Page Description

9.13.2 Register

Configuration 283 Part F Data Register (PFDR)

Bit:76543210

—PF6DR PF5DR PF4DR PF3DR PF2DR —PF0DR

Initial value : 0 0 0 0 0 0

undefined

R/W : R/W R/W R/W R/W R/W R/W —R/W

2nd line changed as follows

PFDR is an 8-bit readable/writable register that stores output data for the port F

pins (PF6 to PF2, PF0).

6th line changed as follows

Bits 7 and 1 in PFDR are reserved, and only 0 may be written to it.

15.2.3 Bit

Configuration

539 Figure of Detailed Description of Timing within 1 Bit, HCAN bit rate calculation,

BCR Setting Constraints, Table of Setting Range for TSEG1 and TSEG2 in

BCR

Moved to Bit Rate and Bit Timing Settings in section 15.3.2, Initialization after

Hardware Reset.

15.2.11 Interrupt

has transmitted an overload frame.

Bit 15: IRR7 Description

0 [Clearing condition]

Writing 1 (Initial value)

1 Overload frame transmission

[Setting conditions]

When overload frame is transmitted

15.2.16 Unread

Message Status

555 Bit table amended and Note added

UMSR

Bit: 15 14 13 12 11 10 9 8

UMSR7 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0

Initial value: 0 0 0 0 0 0 0 0

R/W: R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*

Bit: 7 6 5 4 3 2 1 0

UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 UMSR8

Initial value: 0 0 0 0 0 0 0 0

R/W: R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*

Note: *Only 1 can be written, to clear the flag.

Section Page Description

15.3.2 Initialization

after Hardware

Reset

Bit Rate and Bit

Timing Settings

565 to

567

Bit Rate and Bit Timing Settings: As bit rate settings, a baud rate setting and bit timing

setting must be made each time a CAN node begins communication. The baud rate and

bit timing settings are made in the bit configuration register (BCR).

Note: BCR can be written to at all times, but should only be modified in configuration mode.

Settings should be made so that all CAN controllers connected to the CAN bus have the

same baud rate and bit width.

Refer to table 15.3 for the range of values that can be used as settings (TSEG1, TSEG2,

BRP, sample point, and SJW) for BCR.

Table 15-3 BCR Register Value Setting Ranges

Name Abbreviation Min.

Value Max.

Value

Time segment 1 TSEG1 B'0011 B'1111

Time segment 2 TSEG2 B'001 B'111

Baud rate prescaler BRP B'000000 B'111111

Sample point SAM B'0 B'1

Re-synchronization jump width SJW B'00 B'11

Value Setting Ranges

• The value of SJW is stipulated in the CAN specifications.

3 ≥ SJW ≥ 0

• The minimum value of TSEG1 is stipulated in the CAN specifications.

TSEG1 > TSEG2

• The minimum value of TSEG2 is stipulated in the CAN specifications.

TSEG2 ≥ SJW

The following formula is used to calculate the baud rate.

CLK

2 × (BRP + 1) × (3 + TSEG1 + TSEG2)

Bit rate =

Note: f

CLK

= φ (system clock)

The BCR value is used in the BRP, TSEG1, and TSEG2.

Section Page Description

15.3.2 Initialization

after Hardware

Reset

Bit Rate and Bit

Timing Settings

565 to

567

Example: With a 1 Mb/s baud rate and a 20 MHz input clock:

20 MHz

2 × (0 + 1) × (3 + 4 + 3)

1 Mb/s =

Set Values Actual Values

CLK

= 20 MHz —

BRP = 0 (B'000000) System clock × 2

TSEG1 = 4 (B'0100) 5TQ

TSEG2 = 3 (B'011) 4TQ

SYNC_SEG PRSEG PHSEG1 PHSEG2

1-bit time 1-bit time (8–25 time quanta)

Quantum

1 TSEG1 (time segment 1)

2–16

TSEG2 (time segment 2)

2–8

Legend

SYNC_SEG: Segment for establishing synchronization of nodes on the CAN bus. (Normal

bit edge transitions occur in this segment.)

PRSEG: Segment for compensating for physical delay between networks.

PHSEG1: Buffer segment for correcting phase drift (positive). (This segment is extended

when synchronization (resynchronization) is established.)

PHSEG2: Buffer segment for correcting phase drift (negative). (This segment is

shortened when synchronization (resynchronization) is established.)

Note: The time quanta values of TSEG1 and TSEG2 become the value of TSEG + 1.

Figure 15-6 Detailed Description of Timing within 1 Bit

HCAN bit rate calculation:

CLK

2 × (BRP + 1) × (3 + TSEG1 + TSEG2)

Bit rate =

Note: f

CLK

= ø (system clock)

The BCR values are used for BRP, TSEG1, and TSEG2.

BCR Setting Constraints

TSEG1 > TSEG2 ≥ SJW (SJW = 0 to 3)

These constraints allow the setting range shown in table 15-4 for TSEG1 and TSEG2 in BCR.

Table 15-4 Setting Range for TSEG1 and TSEG2 in BCR

TSEG2 (BCR [14:12])

001 010 011 100 101 110 111

TSEG1 0011 No Yes No No No No No

(BCR [11:8]) 0100 Yes*Yes Yes No No No No

0101 Yes*Yes Yes Yes No No No

0110 Yes*Yes Yes Yes Yes No No

0111 Yes*Yes Yes Yes Yes Yes No

1000 Yes*Yes Yes Yes Yes Yes Yes

1001 Yes*Yes Yes Yes Yes Yes Yes

1010 Yes*Yes Yes Yes Yes Yes Yes

1011 Yes*Yes Yes Yes Yes Yes Yes

1100 Yes*Yes Yes Yes Yes Yes Yes

1101 Yes*Yes Yes Yes Yes Yes Yes

1110 Yes*Yes Yes Yes Yes Yes Yes

1111 Yes*Yes Yes Yes Yes Yes Yes

Notes: The time quanta value for TSEG1 and TSEG2 is the TSEG value + 1.

*Only a value other than BRP[13:8] = B'000000 can be set.

Section Page Description

15.3.7 Interrupt 583 IRR3 Error warning interrupt (TEC ≥ 96)

Interface IRR4 Error warning interrupt (REC ≥ 96)

Table 15-5 HCAN

Interrupt Sources IRR7 Overload frame transmission interrupt

15.5 Usage Notes

9. HTxD pin output

in error passive state

10. Transition to

HCAN sleep mode

11. Message

transmission

cancellation (TxCR)

12. TxCR in the bus

off state

587 Newly added

9. HTxD pin output in error passive state

If the HRxD pin becomes fixed at 1 during message transmission or

reception when the HCAN is in the error active state, the HTxD pin will

output 0 continuously while in the error passive state. To stop continuous 0

output to the CAN bus, disable the HCAN by means of an error warning

interrupt or by setting the HCAN module stop mode through detection of a

fixed 1 state by the HxRD pin monitor.

10. Transition to HCAN sleep mode

The HCAN stops (transmission/reception stops) when MCR0 is cleared to 0

immediately after an HCAN sleep mode transition effected by setting TXPR

of the HCAN to 1 and setting MCR5 to 1. When a transition is made to the

HCAN sleep mode by means of the above steps, a 10-cycle wait should be

inserted after the TxPR setting. After an HCAN sleep mode transition,

release the HCAN sleep mode by clearing MCR5 to 0.

11. Message transmission cancellation (TxCR)

If all the following conditions are met when cancellation of a transmission

message is performed by means of TxCR of the HCAN, the TxCR or TxPR

bit indicating cancellation is not cleared even though internal transmission

is canceled.

When canceling a message using TxCR, 1 should be written continuously

until TxCR or TxPR becomes 0.

12. TxCR in the bus off state

If TxPR is set before the HCAN goes to the bus off state, and a transition is

made to the bus off state with transmission incomplete, cancellation will be

performed even if TxCR is set during the bus off period, and the message

will be transmitted after a transition to the error active state.

18.1.4 Register

Configuration

Table 18-2 LCD

Controller/Driver

Registers

633

LCD RAM —R/W Undefined H'FC40 to H'FC53

Module stop control

Note * 2 deleted

22.6.3 Setting

Oscillation

Stabilization Time

after Clearing

Software Standby

Mode

743 Note amended

Note: * Do not use this setting.

Section Page Description

23.1 Absolute

Maximum Ratings

Table 23-1

Absolute Maximum

Ratings

753

Input voltage (OSC1, OSC2) Vin –0.3 +3.5 V

lnput voltage (XTAL, EXTAL) Vin –0.3 to ACC +0.3 V

Input voltage (ports 4 and 9) Vin –0.3 to AVCC +0.3 V

Input voltage (ports A, B, C, D, E,

ports PF2, PF4 to PF6) Vin –0.3 to LPVCC +0.3 V

Input voltage (ports H and J) Vin –0.3 to PWMVCC +0.3 V

Input voltage (except ports 4, 9, A,

B, C, D, E, ports PF2, PF4 to PF6,

H and J)

Vin –0.3 to VCC +0.3 V

23.3 DC

Characteristics

Table 23-2 DC

Characteristics

755,

758

Input high

voltage RES, STBY,

NMI, FWE,

MD2 to MD0

– 0.7 —V

+ 0.3 V

EXTAL V

× 0.7 —V

+ 0.3

Ports 1 to 3, 5,

H, J, K

Ports PF0, PF3,

PF7

2.2 —V

+ 0.3

HRxD 2.2 —V

+ 0.3

Ports A to E,

Ports PF2, PF4

to PF6

2.2 —LPV

+ 0.3

Ports 4, 9 AV

× 0.7 —AV

+ 0.3

Input low

voltage RES, STBY,

NMI, FWE,

MD2 to MD0

–0.3 —0.5 V

EXTAL –0.3 —0.8

Ports 1 to 3, 5,

A to F, H, J, K –0.3 —0.8

HRxD –0.3 —V

+ 0.2

Notes amended

*1 If the A/D converter is not used, do not leave the AVCC, Vref , and AVSS pins

open. Apply a voltage between 4.5 V and 5.5 V to the AVCC and Vref pins by

connecting them to VCC, for instance. Set Vref AV CC.

*3 The values are for VRAM LPV CC < 3.0 V, VIH min = VCC × 0.9, and VIL max =

0.3 V.

23.4.1 Clock Timing

Table 23-4 Clock

Timing

761 (Incorrect)20MHz

(Correct)Condition

B.1 Address 858 Data Bus Width of H'EBC0 to H'EFBF

(Incorrect)16/32

(Correct)8/16/32*

Section Page Description

B.2 Functions 882 TXACK—Transmit Acknowledge Register H'F80A HCAN

TXACK7

R/(W)*

TXACK6

R/(W)*

TXACK5

R/(W)*

TXACK4

R/(W)*

TXACK3

R/(W)*

—

TXACK2

R/(W)*

TXACK1

R/(W)*

TXACK15

R/(W)*

TXACK14

R/(W)*

TXACK13

R/(W)*

TXACK12

R/(W)*

TXACK11

R/(W)*

TXACK8

R/(W)*

TXACK10

R/(W)*

TXACK9

R/(W)*

Bit

Initial value

Read/Write

Bit

Initial value

Read/Write

Note added

Note: * Only 1 can be written, to clear the flag.

883 ABACK—Abort Acknowledge Register H'F80C HCAN

ABACK7

R/(W)*

ABACK6

R/(W)*

ABACK5

R/(W)*

ABACK4

R/(W)*

ABACK3

R/(W)*

—

ABACK2

R/(W)*

ABACK1

R/(W)*

ABACK15

R/(W)*

ABACK14

R/(W)*

ABACK13

R/(W)*

ABACK12

R/(W)*

ABACK11

R/(W)*

ABACK8

R/(W)*

ABACK10

R/(W)*

ABACK9

R/(W)*

Bit

Initial value

Read/Write

Bit

Initial value

Read/Write

Note added

Note: * Only 1 can be written, to clear the flag.

RXPR—Receive Complete Register H'F80E HCAN

RXPR7

R/(W)*

RXPR6

R/(W)*

RXPR5

R/(W)*

RXPR4

R/(W)*

RXPR3

R/(W)*

RXPR0

R/(W)*

RXPR2

R/(W)*

RXPR1

R/(W)*

RXPR15

R/(W)*

RXPR14

R/(W)*

RXPR13

R/(W)*

RXPR12

R/(W)*

RXPR11

R/(W)*

RXPR8

R/(W)*

RXPR10

R/(W)*

RXPR9

R/(W)*

Bit

Initial value

Read/Write

Bit

Initial value

Read/Write

Note added

Note: * Only 1 can be written, to clear the flag.

Section Page Description

B.2 Functions 884 RFPR—Remote Request Register H'F810 HCAN

RFPR7

R/(W)*

RFPR6

R/(W)*

RFPR5

R/(W)*

RFPR4

R/(W)*

RFPR3

R/(W)*

RFPR0

R/(W)*

RFPR2

R/(W)*

RFPR1

R/(W)*

RFPR15

R/(W)*

RFPR14

R/(W)*

RFPR13

R/(W)*

RFPR12

R/(W)*

RFPR11

R/(W)*

RFPR8

R/(W)*

RFPR10

R/(W)*

RFPR9

R/(W)*

Bit

Initial value

Read/Write

Bit

Initial value

Read/Write

Note added

Note: * Only 1 can be written, to clear the flag.

885,

886

IRR—Interrupt Register H'F812 HCAN

IRR7

R/(W)*

IRR6

R/(W)*

IRR5

R/(W)*

IRR4

R/(W)*

IRR3

R/(W)*

IRR0

R/(W)*

IRR2

R/(W)*

IRR1

R/(W)*

Bit

Initial value

Read/Write

0 [Clearing condition]

Writing 1

1 Overload frame transmission

[Setting conditions]

When overload frame is transmitted

Overload Frame Interrupt Flag

—

IRR12

R/(W)*

—

IRR8

R/(W)*

—

IRR9

R/(W)*

Bit

Initial value

Read/Write

Note added

Note: * Only 1 can be written, to clear the flag.

Section Page Description

B.2 Functions 890 UMSR—Unread Message Status Register H'F81A HCAN

UMSR7

R/(W)*

UMSR6

R/(W)*

UMSR5

R/(W)*

UMSR4

R/(W)*

UMSR3

R/(W)*

UMSR0

R/(W)*

UMSR2

R/(W)*

UMSR1

R/(W)*

UMSR15

R/(W)*

UMSR14

R/(W)*

UMSR13

R/(W)*

UMSR12

R/(W)*

UMSR11

R/(W)*

UMSR8

R/(W)*

UMSR10

R/(W)*

UMSR9

R/(W)*

Bit

Initial value

Read/Write

Bit

Initial value

Read/Write

Unread Message Status Flags

0 [Clearing condition]

Writing 1

(x = 15 to 0)

1 Unread receive message is overwritten by a new message

[Setting condition]

When a new message is received before RXPR is cleared

Note added

Note: * Only 1 can be written, to clear the flag.

1009 PFDR—Port F Data Register H'FF0E Port

—

R/W

PF6DR

R/W

PF5DR

R/W

PF4DR

R/W

PF3DR

R/W

PF0DR

R/W

PF2DR

R/W

—

Undefined

—

Bit

Initial value

Read/Write

C.12 Port F Block

Diagrams 1107

WDDRF

Reset

Internal data bus

Mode 4/5/6

PF7DDR

Contents

Section 1 Overview.......................................................................................... 1

1.1 Overview............................................................................................................................ 1

1.2 Internal Block Diagram ..................................................................................................... 6

1.3 Pin Description.................................................................................................................. 8

1.3.1 Pin Arrangement .................................................................................................. 8

1.3.2 Pin Functions in Each Operating Mode................................................................ 10

1.3.3 Pin Functions........................................................................................................ 20

Section 2 CPU.................................................................................................. 27

2.1 Overview............................................................................................................................ 27

2.1.1 Features ................................................................................................................ 27

2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU.................................. 28

2.1.3 Differences from H8/300 CPU............................................................................. 29

2.1.4 Differences from H8/300H CPU.......................................................................... 29

2.2 CPU Operating Modes ...................................................................................................... 30

2.3 Address Space.................................................................................................................... 35

2.4 Register Configuration ......................................................................................................36

2.4.1 Overview.............................................................................................................. 36

2.4.2 General Registers.................................................................................................. 37

2.4.3 Control Registers.................................................................................................. 38

2.4.4 Initial Register Values.......................................................................................... 40

2.5 Data Formats...................................................................................................................... 41

2.5.1 General Register Data Formats ............................................................................ 41

2.5.2 Memory Data Formats.......................................................................................... 43

2.6 Instruction Set.................................................................................................................... 44

2.6.1 Overview.............................................................................................................. 44

2.6.2 Instructions and Addressing Modes ..................................................................... 45

2.6.3 Table of Instructions Classified by Function........................................................ 47

2.6.4 Basic Instruction Formats..................................................................................... 56

2.7 Addressing Modes and Effective Address Calculation..................................................... 58

2.7.1 Addressing Mode.................................................................................................. 58

2.7.2 Effective Address Calculation.............................................................................. 61

2.8 Processing States ............................................................................................................... 65

2.8.1 Overview.............................................................................................................. 65

2.8.2 Reset State............................................................................................................ 66

2.8.3 Exception-Handling State .................................................................................... 67

2.8.4 Program Execution State...................................................................................... 70

2.8.5 Bus-Released State............................................................................................... 70

2.8.6 Power-Down State................................................................................................ 70

2.9 Basic Timing...................................................................................................................... 71

2.9.1 Overview.............................................................................................................. 71

2.9.2 On-Chip Memory (ROM, RAM) ......................................................................... 71

2.9.3 On-Chip Supporting Module Access Timing....................................................... 73

2.9.4 On-Chip HCAN Module Access Timing............................................................. 75

2.9.5 External Address Space Access Timing............................................................... 76

2.10 Usage Note ........................................................................................................................ 76

2.10.1 TAS Instruction.................................................................................................... 76

2.10.2 Caution to observe when using bit manipulation instructions.............................. 76

Section 3 MCU Operating Modes................................................................... 79

3.1 Overview............................................................................................................................ 79

3.1.1 Operating Mode Selection.................................................................................... 79

3.1.2 Register Configuration ......................................................................................... 80

3.2 Register Descriptions......................................................................................................... 80

3.2.1 Mode Control Register (MDCR).......................................................................... 80

3.2.2 System Control Register (SYSCR) ...................................................................... 81

3.2.3 Pin Function Control Register (PFCR) ................................................................ 82

3.3 Operating Mode Descriptions............................................................................................ 84

3.3.1 Mode 4.................................................................................................................. 84

3.3.2 Mode 5.................................................................................................................. 84

3.3.3 Mode 6.................................................................................................................. 84

3.3.4 Mode 7.................................................................................................................. 84

3.4 Pin Functions in Each Operating Mode............................................................................. 85

3.5 Address Map in Each Operating Mode ............................................................................. 85

Section 4 Exception Handling......................................................................... 89

4.1 Overview............................................................................................................................ 89

4.1.1 Exception Handling Types and Priority............................................................... 89

4.1.2 Exception Handling Operation............................................................................. 90

4.1.3 Exception Vector Table........................................................................................ 90

4.2 Reset.................................................................................................................................. 92

4.2.1 Overview.............................................................................................................. 92

4.2.2 Reset Sequence..................................................................................................... 92

4.2.3 Interrupts after Reset............................................................................................ 94

4.2.4 State of On-Chip Supporting Modules after Reset Release ................................. 95

4.3 Traces ................................................................................................................................ 95

4.4 Interrupts............................................................................................................................ 96

4.5 Trap Instruction ................................................................................................................. 97

4.6 Stack Status after Exception Handling.............................................................................. 98

4.7 Notes on Use of the Stack.................................................................................................. 99

iii

Section 5 Interrupt Controller..........................................................................101

5.1 Overview............................................................................................................................ 101

5.1.1 Features ................................................................................................................ 101

5.1.2 Block Diagram...................................................................................................... 102

5.1.3 Pin Configuration ................................................................................................. 103

5.1.4 Register Configuration ......................................................................................... 103

5.2 Register Descriptions......................................................................................................... 104

5.2.1 System Control Register (SYSCR) ...................................................................... 104

5.2.2 Interrupt Priority Registers A to H, J, K, M

(IPRA to IPRH, IPRJ, IPRK, IPRM) ................................................................... 105

5.2.3 IRQ Enable Register (IER) .................................................................................. 106

5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 107

5.2.5 IRQ Status Register (ISR).................................................................................... 108

5.3 Interrupt Sources................................................................................................................ 109

5.3.1 External Interrupts................................................................................................ 109

5.3.2 Internal Interrupts................................................................................................. 110

5.3.3 Interrupt Exception Handling Vector Table......................................................... 110

5.4 Interrupt Operation............................................................................................................ 114

5.4.1 Interrupt Control Modes and Interrupt Operation................................................ 114

5.4.2 Interrupt Control Mode 0...................................................................................... 117

5.4.3 Interrupt Control Mode 2...................................................................................... 119

5.4.4 Interrupt Exception Handling Sequence .............................................................. 121

5.4.5 Interrupt Response Times..................................................................................... 122

5.5 Usage Notes....................................................................................................................... 123

5.5.1 Contention between Interrupt Generation and Disabling..................................... 123

5.5.2 Instructions that Disable Interrupts ...................................................................... 124

5.5.3 Times when Interrupts are Disabled..................................................................... 124

5.5.4 Interrupts during Execution of EEPMOV Instruction.......................................... 125

5.5.5 IRQ Interrupts ...................................................................................................... 125

5.6 DTC Activation by Interrupt ............................................................................................. 125

5.6.1 Overview.............................................................................................................. 125

5.6.2 Block Diagram...................................................................................................... 125

5.6.3 Operation.............................................................................................................. 126

Section 6 PC Break Controller (PBC)..............................................................129

6.1 Overview............................................................................................................................ 129

6.1.1 Features ................................................................................................................ 129

6.1.2 Block Diagram...................................................................................................... 130

6.1.3 Register Configuration ......................................................................................... 131

6.2 Register Descriptions......................................................................................................... 131

6.2.1 Break Address Register A (BARA) ..................................................................... 131

6.2.2 Break Address Register B (BARB)...................................................................... 132

6.2.3 Break Control Register A (BCRA) ...................................................................... 132

6.2.4 Break Control Register B (BCRB)....................................................................... 134

6.2.5 Module Stop Control Register C (MSTPCRC).................................................... 134

6.3 Operation ........................................................................................................................... 135

6.3.1 PC Break Interrupt Due to Instruction Fetch........................................................ 135

6.3.2 PC Break Interrupt Due to Data Access............................................................... 135

6.3.3 Notes on PC Break Interrupt Handling ................................................................ 136

6.3.4 Operation in Transitions to Power-Down Modes ................................................ 136

6.3.5 PC Break Operation in Continuous Data Transfer............................................... 137

6.3.6 When Instruction Execution is Delayed by One State ......................................... 138

6.3.7 Additional Notes .................................................................................................. 139

Section 7 Bus Controller..................................................................................141

7.1 Overview............................................................................................................................ 141

7.1.1 Features ................................................................................................................ 141

7.1.2 Block Diagram...................................................................................................... 142

7.1.3 Pin Configuration ................................................................................................. 143

7.1.4 Register Configuration ......................................................................................... 143

7.2 Register Descriptions......................................................................................................... 144

7.2.1 Bus Width Control Register (ABWCR)............................................................... 144

7.2.2 Access State Control Register (ASTCR).............................................................. 144

7.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 146

7.2.4 Bus Control Register H (BCRH).......................................................................... 150

7.2.5 Bus Control Register L (BCRL)........................................................................... 151

7.2.6 Pin Function Control Register (PFCR) ................................................................ 152

7.3 Overview of Bus Control................................................................................................... 154

7.3.1 Area Partitioning .................................................................................................. 154

7.3.2 Bus Specifications................................................................................................ 155

7.3.3 Memory Interfaces................................................................................................ 156

7.3.4 Interface Specifications for Each Area................................................................. 157

7.4 Basic Bus Interface............................................................................................................ 158

7.4.1 Overview.............................................................................................................. 158

7.4.2 Data Size and Data Alignment ............................................................................. 158

7.4.3 Valid Strobes........................................................................................................ 160

7.4.4 Basic Timing ........................................................................................................ 161

7.4.5 Wait Control......................................................................................................... 169

7.5 Burst ROM Interface ......................................................................................................... 171

7.5.1 Overview.............................................................................................................. 171

7.5.2 Basic Timing ........................................................................................................ 171

7.5.3 Wait Control......................................................................................................... 173

7.6 Idle Cycle........................................................................................................................... 174

7.6.1 Operation.............................................................................................................. 174

7.6.2 Pin States During Idle Cycles............................................................................... 177

7.7 Write Data Buffer Function............................................................................................... 178

7.8 Bus Arbitration.................................................................................................................. 179

7.8.1 Overview.............................................................................................................. 179

7.8.2 Operation.............................................................................................................. 179

7.8.3 Bus Transfer Timing ............................................................................................ 179

7.9 Resets and the Bus Controller............................................................................................ 180

Section 8 Data Transfer Controller (DTC) ......................................................181

8.1 Overview............................................................................................................................ 181

8.1.1 Features ................................................................................................................ 181

8.1.2 Block Diagram...................................................................................................... 182

8.1.3 Register Configuration ......................................................................................... 183

8.2 Register Descriptions......................................................................................................... 184

8.2.1 DTC Mode Register A (MRA)............................................................................. 184

8.2.2 DTC Mode Register B (MRB)............................................................................. 186

8.2.3 DTC Source Address Register (SAR).................................................................. 187

8.2.4 DTC Destination Address Register (DAR).......................................................... 187

8.2.5 DTC Transfer Count Register A (CRA) .............................................................. 187

8.2.6 DTC Transfer Count Register B (CRB)............................................................... 188

8.2.7 DTC Enable Registers (DTCER) ......................................................................... 188

8.2.8 DTC Vector Register (DTVECR)........................................................................ 189

8.2.9 Module Stop Control Register A (MSTPCRA).................................................... 190

8.3 Operation ........................................................................................................................... 192

8.3.1 Overview.............................................................................................................. 192

8.3.2 Activation Sources................................................................................................ 194

8.3.3 DTC Vector Table................................................................................................ 195

8.3.4 Location of Register Information in Address Space............................................ 199

8.3.5 Normal Mode........................................................................................................ 200

8.3.6 Repeat Mode ........................................................................................................ 201

8.3.7 Block Transfer Mode............................................................................................ 202

8.3.8 Chain Transfer...................................................................................................... 204

8.3.9 Operation Timing................................................................................................. 205

8.3.10 Number of DTC Execution States........................................................................ 206

8.3.11 Procedures for Using DTC................................................................................... 208

8.3.12 Examples of Use of the DTC................................................................................ 209

8.4 Interrupts............................................................................................................................ 212

8.5 Usage Notes....................................................................................................................... 212

Section 9 I/O Ports...........................................................................................213

9.1 Overview............................................................................................................................ 213

9.2 Port 1.................................................................................................................................. 221

9.2.1 Overview.............................................................................................................. 221

9.2.2 Register Configuration ......................................................................................... 222

9.2.3 Pin Functions........................................................................................................ 224

9.3 Port 2.................................................................................................................................. 232

9.3.1 Overview.............................................................................................................. 232

9.3.2 Register Configuration ......................................................................................... 232

9.3.3 Pin Functions........................................................................................................ 234

9.4 Port 3.................................................................................................................................. 242

9.4.1 Overview.............................................................................................................. 242

9.4.2 Register Configuration ......................................................................................... 242

9.4.3 Pin Functions........................................................................................................ 245

9.5 Port 4.................................................................................................................................. 247

9.5.1 Overview.............................................................................................................. 247

9.5.2 Register Configuration ......................................................................................... 248

9.5.3 Pin Functions........................................................................................................ 248

9.6 Port 5.................................................................................................................................. 249

9.6.1 Overview.............................................................................................................. 249

9.6.2 Register Configuration ......................................................................................... 250

9.6.3 Pin Functions........................................................................................................ 251

9.7 Port 9.................................................................................................................................. 253

9.7.1 Overview.............................................................................................................. 253

9.7.2 Register Configuration ......................................................................................... 254

9.7.3 Pin Functions........................................................................................................ 254

9.8 Port A................................................................................................................................. 255

9.8.1 Overview.............................................................................................................. 255

9.8.2 Register Configuration ......................................................................................... 256

9.8.3 Pin Functions........................................................................................................ 258

9.8.4 MOS Input Pull-Up Function............................................................................... 260

9.9 Port B................................................................................................................................. 261

9.9.1 Overview.............................................................................................................. 261

9.9.2 Register Configuration ......................................................................................... 262

9.9.3 Pin Functions........................................................................................................ 264

9.9.4 MOS Input Pull-Up Function............................................................................... 265

9.10 Port C................................................................................................................................. 266

9.10.1 Overview.............................................................................................................. 266

9.10.2 Register Configuration ......................................................................................... 267

9.10.3 Pin Functions........................................................................................................ 269

9.10.4 MOS Input Pull-Up Function............................................................................... 270

9.11 Port D................................................................................................................................. 271

9.11.1 Overview.............................................................................................................. 271

9.11.2 Register Configuration ......................................................................................... 272

9.11.3 Pin Functions........................................................................................................ 274

9.11.4 MOS Input Pull-Up Function............................................................................... 275

9.12 Port E................................................................................................................................. 276

9.12.1 Overview.............................................................................................................. 276

vii

9.12.2 Register Configuration ......................................................................................... 277

9.12.3 Pin Functions........................................................................................................ 279

9.12.4 MOS Input Pull-Up Function............................................................................... 279

9.13 Port F ................................................................................................................................. 281

9.13.1 Overview.............................................................................................................. 281

9.13.2 Register Configuration ......................................................................................... 282

9.13.3 Pin Functions........................................................................................................ 284

9.14 Port H................................................................................................................................. 287

9.14.1 Overview.............................................................................................................. 287

9.14.2 Register Configuration ......................................................................................... 287

9.14.3 Pin Functions........................................................................................................ 289

9.15 Port J.................................................................................................................................. 289

9.15.1 Overview.............................................................................................................. 289

9.15.2 Register Configuration ......................................................................................... 290

9.15.3 Pin Functions........................................................................................................ 291

9.16 Port K................................................................................................................................. 292

9.16.1 Overview.............................................................................................................. 292

9.16.2 Register Configuration ......................................................................................... 292

9.16.3 Pin Functions........................................................................................................ 294

Section 10 16-Bit Timer Pulse Unit (TPU)........................................................295

10.1 Overview............................................................................................................................ 295

10.1.1 Features ................................................................................................................ 295

10.1.2 Block Diagram...................................................................................................... 299

10.1.3 Pin Configuration ................................................................................................. 300

10.1.4 Register Configuration ......................................................................................... 302

10.2 Register Descriptions......................................................................................................... 304

10.2.1 Timer Control Register (TCR) ............................................................................. 304

10.2.2 Timer Mode Register (TMDR) ............................................................................ 309

10.2.3 Timer I/O Control Register (TIOR) ..................................................................... 311

10.2.4 Timer Interrupt Enable Register (TIER).............................................................. 324

10.2.5 Timer Status Register (TSR)................................................................................ 327

10.2.6 Timer Counter (TCNT)........................................................................................ 331

10.2.7 Timer General Register (TGR) ............................................................................ 332

10.2.8 Timer Start Register (TSTR)................................................................................ 333

10.2.9 Timer Synchro Register (TSYR).......................................................................... 334

10.2.10 Module Stop Control Register A (MSTPCRA).................................................... 335

10.3 Interface to Bus Master...................................................................................................... 336

10.3.1 16-Bit Registers.................................................................................................... 336

10.3.2 8-Bit Registers...................................................................................................... 336

10.4 Operation ........................................................................................................................... 338

10.4.1 Overview.............................................................................................................. 338

10.4.2 Basic Functions .................................................................................................... 339

viii

10.4.3 Synchronous Operation........................................................................................ 345

10.4.4 Buffer Operation .................................................................................................. 347

10.4.5 Cascaded Operation.............................................................................................. 351

10.4.6 PWM Modes ........................................................................................................ 353

10.4.7 Phase Counting Mode .......................................................................................... 358

10.5 Interrupts............................................................................................................................ 365

10.5.1 Interrupt Sources and Priorities............................................................................ 365

10.5.2 DTC Activation.................................................................................................... 367

10.5.3 A/D Converter Activation.................................................................................... 367

10.6 Operation Timing .............................................................................................................. 368

10.6.1 Input/Output Timing ............................................................................................ 368

10.6.2 Interrupt Signal Timing........................................................................................ 372

10.7 Usage Notes....................................................................................................................... 376

Section 11 Programmable Pulse Generator (PPG)............................................387

11.1 Overview............................................................................................................................ 387

11.1.1 Features ................................................................................................................ 387

11.1.2 Block Diagram...................................................................................................... 388

11.1.3 Pin Configuration ................................................................................................. 389

11.1.4 Registers............................................................................................................... 390

11.2 Register Descriptions......................................................................................................... 391

11.2.1 Next Data Enable Registers H and L (NDERH, NDERL)................................... 391

11.2.2 Output Data Registers H and L (PODRH, PODRL)............................................ 392

11.2.3 Next Data Registers H and L (NDRH, NDRL).................................................... 393

11.2.4 Notes on NDR Access.......................................................................................... 393

11.2.5 PPG Output Control Register (PCR).................................................................... 395

11.2.6 PPG Output Mode Register (PMR)...................................................................... 397

11.2.7 Port 1 Data Direction Register (P1DDR)............................................................. 400

11.2.8 Module Stop Control Register A (MSTPCRA).................................................... 400

11.3 Operation ........................................................................................................................... 401

11.3.1 Overview.............................................................................................................. 401

11.3.2 Output Timing...................................................................................................... 402

11.3.3 Normal Pulse Output............................................................................................ 403

11.3.4 Non-Overlapping Pulse Output............................................................................ 405

11.3.5 Inverted Pulse Output........................................................................................... 408

11.3.6 Pulse Output Triggered by Input Capture ............................................................ 409

11.4 Usage Notes.......................................................................................................................... 410

Section 12 Watchdog Timer..............................................................................413

12.1 Overview............................................................................................................................ 413

12.1.1 Features ................................................................................................................ 413

12.1.2 Block Diagram...................................................................................................... 414

12.1.3 Pin Configuration ................................................................................................. 416

12.1.4 Register Configuration ......................................................................................... 416

12.2 Register Descriptions......................................................................................................... 417

12.2.1 Timer Counter (TCNT)........................................................................................ 417

12.2.2 Timer Control/Status Register (TCSR)................................................................ 417

12.2.3 Reset Control/Status Register (RSTCSR)............................................................ 422

12.2.4 Notes on Register Access..................................................................................... 423

12.3 Operation ........................................................................................................................... 425

12.3.1 Watchdog Timer Operation.................................................................................. 425

12.3.2 Interval Timer Operation...................................................................................... 427

12.3.3 Timing of Setting Overflow Flag (OVF).............................................................. 427

12.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) ......................... 428

12.4 Interrupts............................................................................................................................ 429

12.5 Usage Notes....................................................................................................................... 429

12.5.1 Contention between Timer Counter (TCNT) Write and Increment..................... 429

12.5.2 Changing Value of PSS and CKS2 to CKS0........................................................ 430

12.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 430

12.5.4 Internal Reset in Watchdog Timer Mode............................................................. 430

12.5.5 OVF Flag Clearing in Interval Timer Mode ........................................................ 430

Section 13 Serial Communication Interface (SCI) ............................................431

13.1 Overview............................................................................................................................ 431

13.1.1 Features ................................................................................................................ 431

13.1.2 Block Diagram...................................................................................................... 433

13.1.3 Pin Configuration ................................................................................................. 434

13.1.4 Register Configuration ......................................................................................... 435

13.2 Register Descriptions......................................................................................................... 436

13.2.1 Receive Shift Register (RSR)............................................................................... 436

13.2.2 Receive Data Register (RDR) .............................................................................. 436

13.2.3 Transmit Shift Register (TSR).............................................................................. 437

13.2.4 Transmit Data Register (TDR)............................................................................. 437

13.2.5 Serial Mode Register (SMR)................................................................................ 438

13.2.6 Serial Control Register (SCR).............................................................................. 441

13.2.7 Serial Status Register (SSR)................................................................................. 445

13.2.8 Bit Rate Register (BRR)....................................................................................... 449

13.2.9 Smart Card Mode Register (SCMR).................................................................... 456

13.2.10 Module Stop Control Register B (MSTPCRB).................................................... 457

13.3 Operation ........................................................................................................................... 459

13.3.1 Overview.............................................................................................................. 459

13.3.2 Operation in Asynchronous Mode........................................................................ 461

13.3.3 Multiprocessor Communication Function............................................................ 472

13.3.4 Operation in Clocked Synchronous Mode ........................................................... 480

13.4 SCI Interrupts .................................................................................................................... 488

13.5 Usage Notes....................................................................................................................... 489

Section 14 Smart Card Interface........................................................................499

14.1 Overview............................................................................................................................ 499

14.1.1 Features ................................................................................................................ 499

14.1.2 Block Diagram...................................................................................................... 500

14.1.3 Pin Configuration ................................................................................................. 501

14.1.4 Register Configuration ......................................................................................... 502

14.2 Register Descriptions......................................................................................................... 503

14.2.1 Smart Card Mode Register (SCMR).................................................................... 503

14.2.2 Serial Status Register (SSR)................................................................................. 505

14.2.3 Serial Mode Register (SMR)................................................................................ 507

14.2.4 Serial Control Register (SCR).............................................................................. 509

14.3 Operation ........................................................................................................................... 510

14.3.1 Overview.............................................................................................................. 510

14.3.2 Pin Connections.................................................................................................... 510

14.3.3 Data Format.......................................................................................................... 512

14.3.4 Register Settings................................................................................................... 514

14.3.5 Clock .................................................................................................................... 516

14.3.6 Data Transfer Operations ..................................................................................... 518

14.3.7 Operation in GSM Mode...................................................................................... 525

14.3.8 Operation in Block Transfer Mode ...................................................................... 526

14.4 Usage Notes....................................................................................................................... 527

Section 15 Hitachi Controller Area Network (HCAN) .....................................531

15.1 Overview............................................................................................................................ 531

15.1.1 Features ................................................................................................................ 531

15.1.2 Block Diagram...................................................................................................... 532

15.1.3 Pin Configuration ................................................................................................. 533

15.1.4 Register Configuration ......................................................................................... 533

15.2 Register Descriptions......................................................................................................... 535

15.2.1 Master Control Register (MCR)........................................................................... 535

15.2.2 General Status Register (GSR)............................................................................. 536

15.2.3 Bit Configuration Register (BCR)........................................................................ 538

15.2.4 Mailbox Configuration Register (MBCR)............................................................ 540

15.2.5 Transmit Wait Register (TXPR) .......................................................................... 541

15.2.6 Transmit Wait Cancel Register (TXCR).............................................................. 542

15.2.7 Transmit Acknowledge Register (TXACK) ........................................................ 543

15.2.8 Abort Acknowledge Register (ABACK).............................................................. 544

15.2.9 Receive Complete Register (RXPR).................................................................... 545

15.2.10 Remote Request Register (RFPR)........................................................................ 546

15.2.11 Interrupt Register (IRR) ....................................................................................... 547

15.2.12 Mailbox Interrupt Mask Register (MBIMR)........................................................ 551

15.2.13 Interrupt Mask Register (IMR) ............................................................................ 552

15.2.14 Receive Error Counter (REC) .............................................................................. 554

15.2.15 Transmit Error Counter (TEC)............................................................................. 554

15.2.16 Unread Message Status Register (UMSR) ........................................................... 555

15.2.17 Local Acceptance Filter Masks (LAFML, LAFMH)........................................... 556

15.2.18 Message Control (MC0 to MC15)........................................................................ 557

15.2.19 Message Data (MD0 to MD15)............................................................................ 561

15.2.20 Module Stop Control Register C (MSTPCRC).................................................... 561

15.3 Operation ........................................................................................................................... 562

15.3.1 Hardware and Software Resets ............................................................................ 562

15.3.2 Initialization after Hardware Reset ...................................................................... 562

15.3.3 Transmit Mode ..................................................................................................... 569

15.3.4 Receive Mode....................................................................................................... 575

15.3.5 HCAN Sleep Mode .............................................................................................. 581

15.3.6 HCAN Halt Mode ................................................................................................ 582

15.3.7 Interrupt Interface................................................................................................. 583

15.3.8 DTC Interface....................................................................................................... 584

15.4 CAN Bus Interface ............................................................................................................ 585

15.5 Usage Notes....................................................................................................................... 585

Section 16 A/D Converter..................................................................................587

16.1 Overview............................................................................................................................ 587

16.1.1 Features ................................................................................................................ 587

16.1.2 Block Diagram...................................................................................................... 588

16.1.3 Pin Configuration ................................................................................................. 589

16.1.4 Register Configuration ......................................................................................... 590

16.2 Register Descriptions......................................................................................................... 591

16.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 591

16.2.2 A/D Control/Status Register (ADCSR)................................................................ 592

16.2.3 A/D Control Register (ADCR)............................................................................. 595

16.2.4 Module Stop Control Register A (MSTPCRA).................................................... 596

16.3 Interface to Bus Master...................................................................................................... 597

16.4 Operation ........................................................................................................................... 598

16.4.1 Single Mode (SCAN = 0)..................................................................................... 598

16.4.2 Scan Mode (SCAN = 1) ....................................................................................... 600

16.4.3 Input Sampling and A/D Conversion Time.......................................................... 602

16.4.4 External Trigger Input Timing ............................................................................. 603

16.5 Interrupts............................................................................................................................ 604

16.6 Usage Notes....................................................................................................................... 604

Section 17 Motor Control PWM Timer.............................................................611

17.1 Overview............................................................................................................................ 611

17.1.1 Features ................................................................................................................ 611

17.1.2 Block Diagram...................................................................................................... 612

17.1.3 Pin Configuration ................................................................................................. 614

xii

17.1.4 Register Configuration ......................................................................................... 615

17.2 Register Descriptions......................................................................................................... 616

17.2.1 PWM Control Registers 1 and 2 (PWCR1, PWCR2).......................................... 616

17.2.2 PWM Output Control Registers 1 and 2 (PWOCR1, PWOCR2)........................ 617

17.2.3 PWM Polarity Registers 1 and 2 (PWPR1, PWPR2)........................................... 618

17.2.4 PWM Counters 1 and 2 (PWCNT1, PWCNT2) .................................................. 619

17.2.5 PWM Cycle Registers 1 and 2 (PWCYR1, PWCYR2) ....................................... 619

17.2.6 PWM Duty Registers 1A, 1C, 1E, 1G (PWDTR1A, 1C, 1E, 1G) ....................... 620

17.2.7 PWM Buffer Registers 1A, 1C, 1E, 1G (PWBFR1A, 1C, 1E, 1G) ..................... 622

17.2.8 PWM Duty Registers 2A to 2H (PWDTR2A to PWDTR2H) ............................. 622

17.2.9 PWM Buffer Registers 2A to 2D (PWBFR2A to PWBFR2D)............................ 624

17.2.10 Module Stop Control Register D (MSTPCRD).................................................... 625

17.3 Bus Master Interface.......................................................................................................... 626

17.3.1 16-Bit Data Registers ........................................................................................... 626

17.3.2 8-Bit Data Registers ............................................................................................. 626

17.4 Operation ........................................................................................................................... 627

17.4.1 PWM Channel 1 Operation.................................................................................. 627

17.4.2 PWM Channel 2 Operation.................................................................................. 628

17.5 Usage Note ........................................................................................................................ 629

Section 18 LCD Controller/Driver....................................................................631

18.1 Overview............................................................................................................................ 631

18.1.1 Features ................................................................................................................ 631

18.1.2 Block Diagram...................................................................................................... 632

18.1.3 Pin Configuration ................................................................................................. 633

18.1.4 Register Configuration ......................................................................................... 633

18.2 Register Descriptions......................................................................................................... 634

18.2.1 LCD Port Control Register (LPCR) ..................................................................... 634

18.2.2 LCD Control Register (LCR)............................................................................... 637

18.2.3 LCD Control Register 2 (LCR2).......................................................................... 639

18.2.4 Module Stop Control Register D (MSTPCRD).................................................... 640

18.3 Operation ........................................................................................................................... 641

18.3.1 Settings up to LCD Display.................................................................................. 641

18.3.2 Relationship between LCD RAM and Display.................................................... 643

18.3.3 Operation in Power-Down Modes........................................................................ 651

18.3.4 Boosting the LCD Drive Power Supply............................................................... 652

Section 19 RAM................................................................................................653

19.1 Overview............................................................................................................................ 653

19.1.1 Block Diagram...................................................................................................... 653

19.1.2 Register Configuration ......................................................................................... 654

19.2 Register Descriptions......................................................................................................... 654

19.2.1 System Control Register (SYSCR) ...................................................................... 654

xiii

19.3 Operation ........................................................................................................................... 655

19.4 Usage Notes....................................................................................................................... 655

Section 20 ROM.................................................................................................657

20.1 Features.............................................................................................................................. 657

20.2 Overview............................................................................................................................ 658

20.2.1 Block Diagram...................................................................................................... 658

20.2.2 Mode Transitions.................................................................................................. 659

20.2.3 On-Board Programming Modes ........................................................................... 660

20.2.4 Flash Memory Emulation in RAM....................................................................... 662

20.2.5 Differences between Boot Mode and User Program Mode.................................. 663

20.2.6 Block Configuration............................................................................................. 664

20.3 Pin Configuration .............................................................................................................. 665

20.4 Register Configuration ...................................................................................................... 666

20.5 Register Descriptions......................................................................................................... 666

20.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 666

20.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 669

20.5.3 Erase Block Register 1 (EBR1)............................................................................ 670

20.5.4 Erase Block Register 2 (EBR2)............................................................................ 670

20.5.5 RAM Emulation Register (RAMER)................................................................... 671

20.5.6 Flash Memory Power Control Register (FLPWCR)............................................ 672

20.6 On-Board Programming Modes ........................................................................................ 673

20.6.1 Boot Mode............................................................................................................ 673

20.6.2 User Program Mode ............................................................................................. 678

20.7 Flash Memory Programming/Erasing................................................................................ 680

20.7.1 Program Mode...................................................................................................... 682

20.7.2 Program-Verify Mode.......................................................................................... 683

20.7.3 Erase Mode........................................................................................................... 687

20.7.4 Erase-Verify Mode............................................................................................... 687

20.8 Protection........................................................................................................................... 689

20.8.1 Hardware Protection............................................................................................. 689

20.8.2 Software Protection.............................................................................................. 690

20.8.3 Error Protection.................................................................................................... 691

20.9 Flash Memory Emulation in RAM.................................................................................... 693

20.10 Interrupt Handling when Programming/Erasing Flash Memory....................................... 695

20.11 Flash Memory Programmer Mode.................................................................................... 695

20.11.1 Socket Adapter Pin Correspondence Diagram..................................................... 696

20.11.2 Programmer Mode Operation............................................................................... 698

20.11.3 Memory Read Mode............................................................................................. 699

20.11.4 Auto-Program Mode ............................................................................................ 702

20.11.5 Auto-Erase Mode.................................................................................................. 704

20.11.6 Status Read Mode................................................................................................. 706

20.11.7 Status Polling........................................................................................................ 707

xiv

20.11.8 Programmer Mode Transition Time..................................................................... 707

20.11.9 Notes on Memory Programming.......................................................................... 708

20.12 Flash Memory and Power-Down States............................................................................ 709

20.12.1 Notes on Power-Down States............................................................................... 709

20.13 Flash Memory Programming and Erasing Precautions ..................................................... 710

Section 21 Clock Pulse Generator.....................................................................715

21.1 Overview............................................................................................................................ 715

21.1.1 Block Diagram...................................................................................................... 715

21.1.2 Register Configuration ......................................................................................... 716

21.2 Register Descriptions......................................................................................................... 716

21.2.1 System Clock Control Register (SCKCR) ........................................................... 716

21.2.2 Low-Power Control Register (LPWRCR)............................................................ 717

21.3 Oscillator............................................................................................................................ 718

21.3.1 Connecting a Crystal Resonator........................................................................... 718

21.4 PLL Circuit........................................................................................................................ 721

21.5 Medium-Speed Clock Divider........................................................................................... 721

21.6 Bus Master Clock Selection Circuit .................................................................................. 721

21.7 Subclock Oscillator............................................................................................................ 722

21.8 Subclock Waveform Generation Circuit ........................................................................... 723

21.9 Note on Crystal Resonator................................................................................................. 723

Section 22 Power-Down Modes........................................................................725

22.1 Overview............................................................................................................................ 725

22.1.1 Register Configuration ......................................................................................... 729

22.2 Register Descriptions......................................................................................................... 730

22.2.1 Standby Control Register (SBYCR) .................................................................... 730

22.2.2 System Clock Control Register (SCKCR) ........................................................... 732

22.2.3 Low-Power Control Register (LPWRCR)............................................................ 733

22.2.4 Timer Control/Status Register (TCSR)................................................................ 736

22.2.5 Module Stop Control Register (MSTPCR).......................................................... 737

22.3 Medium-Speed Mode........................................................................................................ 738

22.4 Sleep Mode........................................................................................................................ 739

22.4.1 Sleep Mode........................................................................................................... 739

22.4.2 Exiting Sleep Mode.............................................................................................. 739

22.5 Module Stop Mode............................................................................................................ 740

22.5.1 Module Stop Mode............................................................................................... 740

22.5.2 Usage Notes.......................................................................................................... 741

22.6 Software Standby Mode .................................................................................................... 742

22.6.1 Software Standby Mode ....................................................................................... 742

22.6.2 Clearing Software Standby Mode ........................................................................ 742

22.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode .. 743

22.6.4 Software Standby Mode Application Example.................................................... 743

22.6.5 Usage Notes.......................................................................................................... 744

22.7 Hardware Standby Mode................................................................................................... 745

22.7.1 Hardware Standby Mode...................................................................................... 745

22.7.2 Hardware Standby Mode Timing......................................................................... 746

22.8 Watch Mode ...................................................................................................................... 746

22.8.1 Watch Mode ......................................................................................................... 746

22.8.2 Exiting Watch Mode ............................................................................................ 747

22.8.3 Notes..................................................................................................................... 747

22.9 Sub-Sleep Mode ................................................................................................................ 748

22.9.1 Sub-Sleep Mode ................................................................................................... 748

22.9.2 Exiting Sub-Sleep Mode ...................................................................................... 748

22.10 Sub-Active Mode............................................................................................................... 749

22.10.1 Sub-Active Mode.................................................................................................. 749

22.10.2 Exiting Sub-Active Mode..................................................................................... 749

22.11 Direct Transitions.............................................................................................................. 750

22.11.1 Overview of Direct Transitions............................................................................ 750

22.12 ø Clock Output Disabling Function................................................................................... 750

22.13 Usage Notes....................................................................................................................... 751

Section 23 Electrical Characteristics..................................................................753

23.1 Absolute Maximum Ratings.............................................................................................. 753

23.2 Power Supply Voltage and Operating Frequency Range.................................................. 754

23.3 DC Characteristics............................................................................................................. 755

23.4 AC Characteristics............................................................................................................. 760

23.4.1 Clock Timing........................................................................................................ 761

23.4.2 Control Signal Timing.......................................................................................... 763

23.4.3 Bus Timing........................................................................................................... 765

23.4.4 Timing of On-Chip Supporting Modules ............................................................. 771

23.5 A/D Conversion Characteristics........................................................................................ 776

23.6 LCD Characteristics .......................................................................................................... 777

23.7 Flash Memory Characteristics........................................................................................... 778

Appendix A Instruction Set...............................................................................781

A.1 Instruction List................................................................................................................... 781

A.2 Instruction Codes............................................................................................................... 805

A.3 Operation Code Map.......................................................................................................... 820

A.4 Number of States Required for Instruction Execution...................................................... 824

A.5 Bus States During Instruction Execution .......................................................................... 838

A.6 Condition Code Modification............................................................................................ 852

Appendix B Internal I/O Register.....................................................................858

B.1 Address.............................................................................................................................. 858

B.2 Functions............................................................................................................................ 874

xvi

Appendix C I/O Port Block Diagrams........................................................... 1075

C.1 Port 1 Block Diagrams ..................................................................................................... 1075

C.2 Port 2 Block Diagrams ..................................................................................................... 1081

C.3 Port 3 Block Diagrams ..................................................................................................... 1083

C.4 Port 4 Block Diagram....................................................................................................... 1090

C.5 Port 5 Block Diagrams ..................................................................................................... 1091

C.6 Port 9 Block Diagram....................................................................................................... 1095

C.7 Port A Block Diagram ...................................................................................................... 1096

C.8 Port B Block Diagram ...................................................................................................... 1097

C.9 Port C Block Diagram ...................................................................................................... 1098

C.10 Port D Block Diagram...................................................................................................... 1099

C.11 Port E Block Diagram....................................................................................................... 1100

C.12 Port F Block Diagrams..................................................................................................... 1101

C.13 Port G Block Diagram...................................................................................................... 1108

C.14 Port J Block Diagram ....................................................................................................... 1109

C.15 Port K Block Diagram...................................................................................................... 1110

Appendix D Pin States................................................................................... 1111

D.1 Port States in Each Mode ................................................................................................. 1111

Appendix E Timing of Transition to and Recovery

from Hardware Standby Mode.................................................. 1117

Appendix F Package Dimensions.................................................................. 1118

Section 1 Overview

1.1 Overview

The H8S/2646 Series is a series of microcomputers (MCUs: microcomputer units), built around

the H8S/2600 CPU, employing Hitachi's proprietary architecture, and equipped with peripheral

functions on-chip.

The H8S/2600 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general

registers and a concise, optimized instruction set designed for high-speed operation, and can

address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300

and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300,

H8/300L, or H8/300H Series.

On-chip peripheral functions required for system configuration include data transfer controller

(DTC) bus masters, ROM and RAM memory, a 16-bit timer pulse unit (TPU), programmable

pulse generator (PPG), watchdog timer (WDT), serial communication interface (SCI), Hitachi

controller area network (HCAN), A/D converter, motor control PWM timer (PWM), LCD

controller/driver (LCDC), and I/O ports.

On-chip ROM is available as 128-kbyte flash memory (F-ZTAT™ version)* or 128/64-kbyte

mask ROM. ROM is connected to the CPU via a 16-bit data bus, enabling both byte and word data

to be accessed in one state. Instruction fetching has been speeded up, and processing speed

increased.

Four operating modes, modes 4 to 7, are provided, and there is a choice of single-chip mode or

external expansion mode.

The features of the H8S/2646 Series are shown in table 1-1.

Note: * F-ZTAT™ is a trademark of Hitachi, Ltd.

Table 1-1 Overview

Item Specification

CPU • General-register machine

 Sixteen 16-bit general registers (also usable as sixteen 8-bit registers

or eight 32-bit registers)

• High-speed operation suitable for realtime control

 Maximum clock rate: 20 MHz

 High-speed arithmetic operations

8/16/32-bit register-register add/subtract : 50 ns

16 × 16-bit register-register multiply : 200 ns

16 × 16 + 42-bit multiply and accumulate : 200 ns

32 ÷ 16-bit register-register divide : 1000 ns

• Instruction set suitable for high-speed operation

 Sixty-nine basic instructions

 8/16/32-bit move/arithmetic and logic instructions

 Unsigned/signed multiply and divide instructions

 Multiply-and accumulate instruction

 Powerful bit-manipulation instructions

• Two CPU operating modes

 Normal mode: 64-kbyte address space (not used on this device)

 Advanced mode: 16-Mbyte address space

Bus controller • Address space divided into 8 areas, with bus specifications settable

independently for each area

• Choice of 8-bit or 16-bit access space for each area

• 2-state or 3-state access space can be designated for each area

• Number of program wait states can be set for each area

• Direct connection to burst ROM supported

PC break controller • Supports debugging functions by means of PC break interrupts

• Two break channels

Data transfer

controller (DTC) • Can be activated by internal interrupt or software

• Multiple transfers or multiple types of transfer possible for one activation

source

• Transfer possible in repeat mode, block transfer mode, etc.

• Request can be sent to CPU for interrupt that activated DTC

16-bit timer pulse

unit (TPU) • 6-channel 16-bit timer on-chip

• Pulse I/O processing capability for up to 16 pins'

• Automatic 2-phase encoder count capability

Programmable

pulse generator

(PPG)

• Maximum 8-bit pulse output possible with TPU as time base

• Output trigger selectable in 4-bit groups

• Non-overlap margin can be set

• Direct output or inverse output setting possible

Item Specification

Watchdog timer

(WDT) 2 channels • Watchdog timer or interval timer selectable

• Operation using sub-clock supported (WDT1 only)

Serial communica-

tion interface (SCI)

2 channels

(SCI0 and SCI1)

H8S/2646,

H8S/2646R,

H8S/2645

• Asynchronous mode or synchronous mode selectable

• Multiprocessor communication function

• Smart card interface function

Serial communica-

tion interface (SCI)

3 channels

(SCI0, SCI1, and

SCI2)

H8S/2648,

H8S/2648R,

H8S/2647

Hitachi controller

area network

(HCAN) 1 channels

• CAN: Ver. 2.0B compliant

• Buffer size: 15 transmit/receive messages, transmit only one message

• Filtering of receive messages

A/D converter • Resolution: 10 bits

• Input: 12 channels

• High-speed conversion: 13.3 µs minimum conversion time

(at 20 MHz operation)

• Single or scan mode selectable

• Sample and hold circuit

• A/D conversion can be activated by external trigger or timer trigger

Motor control PWM

timer (PWM) • Maximum of 16 10-bit PWM outputs

• Eight outputs with two channels each built in

• Duty settable between 0% and 100%

• Automatic transfer of buffer register data supported

• Block transfer and one-word data transfer supported using DTC

LCD controller/driver

(LCDC) • 24 segments and 4COM*1

• 40 segments and 4COM*2

• Display LCD RAM (8 bits × 20 bytes (160 bits)

• Segment output pins may be selected four at a time as ports

• On-chip power supply division resistor

Notes: *1 In the H8S/2646, H8S/2646R, and H8S/2645.

*2 In the H8S/2648, H8S/2648R, and H8S/2647.

I/O ports • 92 I/O pins, 16 input-only pins

Item Specification

Memory • Flash memory

• High-speed static RAM

Product Name ROM RAM

H8S/2646, H8S/2646R 128 kbytes 4 kbytes

H8S/2648, H8S/2648R

H8S/2645 64 kbytes 2 kbytes

H8S/2647

Interrupt controller • Seven external interrupt pins (NMI, IRQ0 to IRQ5)

• Internal interrupt sources

 43 (H8S/2646, H8S/2646R, H8S/2645)

 47 (H8S/2648, H8S/2648R, H8S/2647)

• Eight priority levels settable

Power-down states • Medium-speed mode

• Sleep mode

• Module-stop mode

• Software standby mode

• Hardware standby mode

• Sub-clock operation

Operating modes Four MCU operating modes

CPU External Data Bus

Mode Operating

Mode Description On-Chip

ROM Initial

Value Maximum

Value

4 Advanced On-chip ROM disabled

expansion mode Disabled 16 bits 16 bits

5 On-chip ROM disabled

expansion mode Disabled 8 bits 16 bits

6 On-chip ROM enabled

expansion mode Enabled 8 bits 16 bits

7 Single-chip mode Enabled — —

Clock pulse

generator • On-chip PLL circuit (×1, ×2, ×4)

• Input clock frequency: 4 to 20 MHz

• Sub-clock frequency: 32.768 kHz

Packages • 144-pin plastic QFP (FP-144)

Item Specification

Product lineup Model Name

Mask ROM Version F-ZTAT Version ROM/RAM (Bytes)Packages

HD6432646 HD64F2646R 128 k/4 k FP-144J

HD6432645 — 64 k/2 k FP-144G

HD6432648 HD64F2648R 128 k/4 k FP-144J

HD6432647 — 64 k/2 k FP-144G

The HD64F2646R and HD64F2648R use an FP-144J package.

1.2 Internal Block Diagram

Figures 1-1 (1) and 1-1 (2) show internal block diagrams.

PE7/D7

PE6/D6

PE5/D5

PE4/D4

PE3/D3

PE2/D2

PE1/D1

PE0/D0

PD7/D15

PD6/D14

PD5/D13

PD4/D12

PD3/D11

PD2/D10

PD1/D9

PD0/D8

VCC

PWMVCC

LPVCC

VSS

PWMVSS

VCL

PA7/A23/SEG24

PA6/A22/SEG23

PA5/A21/SEG22

PA4/A20/SEG21

PA3/A19/COM4

PA2/A18/COM3

PA1/A17/COM2

PA0/A16/COM1

PB7/A15/SEG16

PB6/A14/SEG15

PB5/A13/SEG14

PB4/A12/SEG13

PB3/A11/SEG12

PB2/A10/SEG11

PB1/A9/SEG10

PB0/A8/SEG9

PC7/A7/SEG8

PC6/A6/SEG7

PC5/A5/SEG6

PC4/A4/SEG5

PC3/A3/SEG4

PC2/A2/SEG3

PC1/A1/SEG2

PC0/A0/SEG1

P37

P36

P35/SCK1/IRQ5

P34/RxD1

P33/TxD1

P32/SCK0/IRQ4

P31/RxD0

P30/TxD0

P97

P96

P95

P94

P93/AN11

P92/AN10

P91/AN9

P90/AN8

P47/AN7

P46/AN6

P45/AN5

P44/AN4

P43/AN3

P42/AN2

P41/AN1

P40/AN0

Vref

AVCC

AVSS

P10/PO8/TIOCA0

P11/PO9/TIOCB0

P12/PO10/TIOCC0/TCLKA

P13/PO11/TIOCD0/TCLKB

P14/PO12/TIOCA1/IRQ0

P15/PO13/TIOCB1/TCLKC

P16/PO14/TIOCA2/IRQ1

P17/PO15/TIOCB2/TCLKD

P20/TIOCA3

P21/TIOCB3

P22/TIOCC3

P23/TIOCD3

P24/TIOCA4

P25/TIOCB4

P26/TIOCA5

P27/TIOCB5

P52

P51

P50

PK7

PK6

PF7/ø

PF6/AS/SEG20

PF5/RD/SEG19

PF4/HWR/SEG18

PF3/LWR/ADTRG/IRQ3

PF2/WAIT/SEG17

PF0/IRQ2

RAM

TPU

HCAN

PPG

MD2

MD1

MD0

OSC2

OSC1

EXTAL

XTAL

PLLCAP

PLLVSS

STBY

RES

NMI

FWE*2

HTxD

HRxD

H8S/2600 CPU

DTC

PH0/PWM1A

PH1/PWM1B

PH2/PWM1C

PH3/PWM1D

PH4/PWM1E

PH5/PWM1F

PH6/PWM1G

PH7/PWM1H

PJ0/PWM2A

PJ1/PWM2B

PJ2/PWM2C

PJ3/PWM2D

PJ4/PWM2E

PJ5/PWM2F

PJ6/PWM2G

PJ7/PWM2H

LCDC

PLL

Port J Port 4Port HPort 1

Port FPort 5Port 2Port K

Port 9 Port 3 Port C Port B Port A

ROM

(mask ROM,

flash memory*1)

WDT × 2 channel

SCI × 2 channel

A/D converter

Motor control PWM timer

Interrupt controller

PC break controller

Bus controller

Clock pulse

generator

Internal data bus

Peripheral data bus

Peripheral address bus

Port D Port E

Internal address bus

Notes: *1 Flash memory version only.

*2 The FWE pin is for compatibility with the flash memory version.

Figure 1-1 (1) H8S/2646, H8S/2646R, and H8S/2645 Internal Block Diagram

PE7/D7/SEG8

PE6/D6/SEG7

PE5/D5/SEG6

PE4/D4/SEG5

PE3/D3/SEG4

PE2/D2/SEG3

PE1/D1/SEG2

PE0/D0/SEG1

PD7/D15/SEG16

PD6/D14/SEG15

PD5/D13/SEG14

PD4/D12/SEG13

PD3/D11/SEG12

PD2/D10/SEG11

PD1/D9/SEG10

PD0/D8/SEG9

VCC

PWMVCC

LPVCC

VSS

PWMVSS

VCL

PA7/A23/SEG40

PA6/A22/SEG39

PA5/A21/SEG38

PA4/A20/SEG37

PA3/A19/COM4

PA2/A18/COM3

PA1/A17/COM2

PA0/A16/COM1

PB7/A15/SEG32

PB6/A14/SEG31

PB5/A13/SEG30

PB4/A12/SEG29

PB3/A11/SEG28

PB2/A10/SEG27

PB1/A9/SEG26

PB0/A8/SEG25

PC7/A7/SEG24

PC6/A6/SEG23

PC5/A5/SEG22

PC4/A4/SEG21

PC3/A3/SEG20

PC2/A2/SEG19

PC1/A1/SEG18

PC0/A0/SEG17

P37

P36

P35/SCK1/IRQ5

P34/RxD1

P33/TxD1

P32/SCK0/IRQ4

P31/RxD0

P30/TxD0

P97

P96

P95

P94

P93/AN11

P92/AN10

P91/AN9

P90/AN8

P47/AN7

P46/AN6

P45/AN5

P44/AN4

P43/AN3

P42/AN2

P41/AN1

P40/AN0

Vref

AVCC

AVSS

P10/PO8/TIOCA0

P11/PO9/TIOCB0

P12/PO10/TIOCC0/TCLKA

P13/PO11/TIOCD0/TCLKB

P14/PO12/TIOCA1/IRQ0

P15/PO13/TIOCB1/TCLKC

P16/PO14/TIOCA2/IRQ1

P17/PO15/TIOCB2/TCLKD

P20/TIOCA3

P21/TIOCB3

P22/TIOCC3

P23/TIOCD3

P24/TIOCA4

P25/TIOCB4

P26/TIOCA5

P27/TIOCB5

P52/SCK2

P51/RxD2

P50/TxD2

PK7

PK6

PF7/ø

PF6/AS/SEG36

PF5/RD/SEG35

PF4/HWR/SEG34

PF3/LWR/ADTRG/IRQ3

PF2/WAIT/SEG33

PF0/IRQ2

RAM

TPU

HCAN

PPG

MD2

MD1

MD0

OSC2

OSC1

EXTAL

XTAL

PLLCAP

PLLVSS

STBY

RES

NMI

FWE*2

HTxD

HRxD

H8S/2600 CPU

DTC

PH0/PWM1A

PH1/PWM1B

PH2/PWM1C

PH3/PWM1D

PH4/PWM1E

PH5/PWM1F

PH6/PWM1G

PH7/PWM1H

PJ0/PWM2A

PJ1/PWM2B

PJ2/PWM2C

PJ3/PWM2D

PJ4/PWM2E

PJ5/PWM2F

PJ6/PWM2G

PJ7/PWM2H

LCDC

PLL

Port J Port 4Port HPort 1

Port FPort 5Port 2Port K

Port 9 Port 3 Port C Port B Port A

ROM

(mask ROM,

flash memory*1)

WDT × 2 channel

SCI × 3 channel

A/D converter

Motor control PWM timer

Interrupt controller

PC break controller

Bus controller

Clock pulse

generator

Internal data bus

Peripheral data bus

Peripheral address bus

Port D Port E

Internal address bus

Notes: *1 Flash memory version only.

*2 The FWE pin is for compatibility with the flash memory version.

Figure 1-1 (2) H8S/2648, H8S/2648R, and H8S/2647 Internal Block Diagram

1.3 Pin Description

1.3.1 Pin Arrangement

Figure 1-2 (1) shows the pin arrangement of the H8S/2646, H8S/2646R, and H8S/2645, and figure

1-2 (2) shows that of the H8S/2648, H8S/2648R, and H8S/2647.

PE0/D0

PE1/D1

PE2/D2

PE3/D3

PE4/D4

PE5/D5

PE6/D6

PE7/D7

VSS

PD0/D8

PD1/D9

PD2/D10

PD3/D11

PD4/D12

PD5/D13

PD6/D14

PD7/D15

LPVCC

PC0/A0/SEG1

PC1/A1/SEG2

PC2/A2/SEG3

PC3/A3/SEG4

PC4/A4/SEG5

PC5/A5/SEG6

PC6/A6/SEG7

PC7/A7/SEG8

PB0/A8/SEG9

PB1/A9/SEG10

PB2/A10/SEG11

PB3/A11/SEG12

PB4/A12/SEG13

PB5/A13/SEG14

PB6/A14/SEG15

P17/PO15/TIOCB2/TCLKD

P16/PO14/TIOCA2/IRQ1

P15/PO13/TIOCB1/TCLKC

P14/PO12/TIOCA1/IRQ0

P13/PO11/TIOCD0/TCLKB

P12/PO10/TIOCC0/TCLKA

P11/PO9/TIOCB0

P10/PO8/TIOCA0

PF7/ø

PF3/LWR/ADTRG/IRQ3

PF0/IRQ2

FWE

EXTAL

VSS

XTAL

VCL

VCC

OSC2

OSC1

VSS

PLLCAP

PLLVSS

STBY

NMI

RES

P37

P36

P35/SCK1/IRQ5

P34/RXD1

P33/TXD1

P32/SCK0/IRQ4

P31/RXD0

P30/TXD0

MD0

MD1

108

107

106

105

104

103

102

101

100

MD2

PWMVSS

PJ7/PWM2H

PJ6/PWM2G

PJ5/PWM2F

PJ4/PWM2E

PWMVCC

PJ3/PWM2D

PJ2/PWM2C

PJ1/PWM2B

PJ0/PWM2A

PWMVSS

PH7/PWM1H

PH6/PWM1G

PH5/PWM1F

PH4/PWM1E

PWMVCC

PH3/PWM1D

PH2/PWM1C

PH1/PWM1B

PH0/PWM1A

PWMVSS

PA3/A19/COM4

PA2/A18/COM3

PA1/A17/COM2

PA0/A16/COM1

PA7/A23/SEG24

PA6/A22/SEG23

PA5/A21/SEG22

PA4/A20/SEG21

PF6/AS/SEG20

PF5/RD/SEG19

VSS

PF4/HWR/SEG18

PF2/WAIT/SEG17

PB7/A15/SEG16

HTxD

HRxD

P50

P51

P52

P20/TIOCA3

P21/TIOCB3

P22/TIOCC3

P23/TIOCD3

P25/TIOCB4

VCC

P24/TIOCA4

PK6

P27/TIOCB5

VSS

P26/TIOCA5

PK7

AVCC

Vref

P40/AN0

P41/AN1

P42/AN2

P43/AN3

P44/AN4

P45/AN5

P46/AN6

P47/AN7

P90/AN8

P91/AN9

P92/AN10

P93/AN11

P94

P95

P96

P97

AVSS

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

Top View

(FP-144J, FP-144G)

Figure 1-2 (1) H8S/2646, H8S/2646R, and H8S/2645 Pin Arrangement

(FP-144J, FP-144G: Top View)

PE0/D0/SEG1

PE1/D1/SEG2

PE2/D2/SEG3

PE3/D3/SEG4

PE4/D4/SEG5

PE5/D5/SEG6

PE6/D6/SEG7

PE7/D7/SEG8

VSS

PD0/D8/SEG9

PD1/D9/SEG10

PD2/D10/SEG11

PD3/D11/SEG12

PD4/D12/SEG13

PD5/D13/SEG14

PD6/D14/SEG15

PD7/D15/SEG16

LPVCC

PC0/A0/SEG17

PC1/A1/SEG18

PC2/A2/SEG19

PC3/A3/SEG20

PC4/A4/SEG21

PC5/A5/SEG22

PC6/A6/SEG23

PC7/A7/SEG24

PB0/A8/SEG25

PB1/A9/SEG26

PB2/A10/SEG27

PB3/A11/SEG28

PB4/A12/SEG29

PB5/A13/SEG30

PB6/A14/SEG31

P17/PO15/TIOCB2/TCLKD

P16/PO14/TIOCA2/IRQ1

P15/PO13/TIOCB1/TCLKC

P14/PO12/TIOCA1/IRQ0

P13/PO11/TIOCD0/TCLKB

P12/PO10/TIOCC0/TCLKA

P11/PO9/TIOCB0

P10/PO8/TIOCA0

PF7/ø

PF3/LWR/ADTRG/IRQ3

PF0/IRQ2

FWE

EXTAL

VSS

XTAL

VCL

VCC

OSC2

OSC1

VSS

PLLCAP

PLLVSS

STBY

NMI

RES

P37

P36

P35/SCK1/IRQ5

P34/RXD1

P33/TXD1

P32/SCK0/IRQ4

P31/RXD0

P30/TXD0

MD0

MD1

108

107

106

105

104

103

102

101

100

MD2

PWMVSS

PJ7/PWM2H

PJ6/PWM2G

PJ5/PWM2F

PJ4/PWM2E

PWMVCC

PJ3/PWM2D

PJ2/PWM2C

PJ1/PWM2B

PJ0/PWM2A

PWMVSS

PH7/PWM1H

PH6/PWM1G

PH5/PWM1F

PH4/PWM1E

PWMVCC

PH3/PWM1D

PH2/PWM1C

PH1/PWM1B

PH0/PWM1A

PWMVSS

PA3/A19/COM4

PA2/A18/COM3

PA1/A17/COM2

PA0/A16/COM1

PA7/A23/SEG40

PA6/A22/SEG39

PA5/A21/SEG38

PA4/A20/SEG37

PF6/AS/SEG36

PF5/RD/SEG35

VSS

PF4/HWR/SEG34

PF2/WAIT/SEG33

PB7/A15/SEG32

HTxD

HRxD

P50/TxD2

P51/RxD2

P52/SCK2

P20/TIOCA3

P21/TIOCB3

P22/TIOCC3

P23/TIOCD3

P25/TIOCB4

VCC

P24/TIOCA4

PK6

P27/TIOCB5

VSS

P26/TIOCA5

PK7

AVCC

Vref

P40/AN0

P41/AN1

P42/AN2

P43/AN3

P44/AN4

P45/AN5

P46/AN6

P47/AN7

P90/AN8

P91/AN9

P92/AN10

P93/AN11

P94

P95

P96

P97

AVSS

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

Top View

(FP-144J, FP-144G)

Figure 1-2 (2) H8S/2648, H8S/2648R, and H8S/2647 Pin Arrangement

(FP-144J, FP-144G: Top View)

1.3.2 Pin Functions in Each Operating Mode

Tablse 1-2 (1) and 1-2 (2) show the pin functions in each of the operating modes.

Table 1-2 (1) Pin Functions in Each Operating Mode (H8S/2646, H8S/2646R, H8S/2645)

Pin Name

Pin No. Mode 4 Mode 5 Mode 6 Mode 7

1V1V1V1V1

2V2V2V2V2

3V3V3V3V3

4 PE0/D0 PE0/D0 PE0/D0 PE0

5 PE1/D1 PE1/D1 PE1/D1 PE1

6 PE2/D2 PE2/D2 PE2/D2 PE2

7 PE3/D3 PE3/D3 PE3/D3 PE3

8 PE4/D4 PE4/D4 PE4/D4 PE4

9 PE5/D5 PE5/D5 PE5/D5 PE5

10 PE6/D6 PE6/D6 PE6/D6 PE6

11 PE7/D7 PE7/D7 PE7/D7 PE7

12 Vss Vss Vss Vss

13 D8 D8 D8 PD0

14 D9 D9 D9 PD1

15 D10 D10 D10 PD2

16 D11 D11 D11 PD3

17 D12 D12 D12 PD4

18 D13 D13 D13 PD5

19 D14 D14 D14 PD6

20 D15 D15 D15 PD7

21 LPVcc LPVcc LPVcc LPVcc

22 A0 A0 PC0/A0/SEG1 PC0/SEG1

23 A1 A1 PC1/A1/SEG2 PC1/SEG2

24 A2 A2 PC2/A2/SEG3 PC2/SEG3

25 A3 A3 PC3/A3/SEG4 PC3/SEG4

26 A4 A4 PC4/A4/SEG5 PC4/SEG5

27 A5 A5 PC5/A5/SEG6 PC5/SEG6

Pin Name

Pin No. Mode 4 Mode 5 Mode 6 Mode 7

28 A6 A6 PC6/A6/SEG7 PC6/SEG7

29 A7 A7 PC7/A7/SEG8 PC7/SEG8

30 PB0/A8/SEG9 PB0/A8/SEG9 PB0/A8/SEG9 PB0/SEG9

31 PB1/A9/SEG10 PB1/A9/SEG10 PB1/A9/SEG10 PB1/SEG10

32 PB2/A10/SEG11 PB2/A10/SEG11 PB2/A10/SEG11 PB2/SEG11

33 PB3/A11/SEG12 PB3/A11/SEG12 PB3/A11/SEG12 PB3/SEG12

34 PB4/A12/SEG13 PB4/A12/SEG13 PB4/A12/SEG13 PB4/SEG13

35 PB5/A13/SEG14 PB5/A13/SEG14 PB5/A13/SEG14 PB5/SEG14

36 PB6/A14/SEG15 PB6/A14/SEG15 PB6/A14/SEG15 PB6/SEG15

37 PB7/A15/SEG16 PB7/A15/SEG16 PB7/A15/SEG16 PB7/SEG16

38 PF2/WAIT/SEG17 PF2/WAIT/SEG17 PF2/WAIT/SEG17 PF2/SEG17

39 HWR/SEG18 HWR/SEG18 HWR/SEG18 PF4/SEG18

40 Vss Vss Vss Vss

41 RD/SEG19 RD/SEG19 RD/SEG19 PF5/SEG19

42 AS/SEG20 AS/SEG20 AS/SEG20 PF6/SEG20

43 PA4/A20/SEG21 PA4/A20/SEG21 PA4/A20/SEG21 PA4/SEG21

44 PA5/A21/SEG22 PA5/A21/SEG22 PA5/A21/SEG22 PA5/SEG22

45 PA6/A22/SEG23 PA6/A22/SEG23 PA6/A22/SEG23 PA6/SEG23

46 PA7/A23/SEG24 PA7/A23/SEG24 PA7/A23/SEG24 PA7/SEG24

47 PA0/A16/COM1 PA0/A16/COM1 PA0/A16/COM1 PA0/COM1

48 PA1/A17/COM2 PA1/A17/COM2 PA1/A17/COM2 PA1/COM2

49 PA2/A18/COM3 PA2/A18/COM3 PA2/A18/COM3 PA2/COM3

50 PA3/A19/COM4 PA3/A19/COM4 PA3/A19/COM4 PA3/COM4

51 PWMVss PWMVss PWMVss PWMVss

52 PH0/PWM1A PH0/PWM1A PH0/PWM1A PH0/PWM1A

53 PH1/PWM1B PH1/PWM1B PH1/PWM1B PH1/PWM1B

54 PH2/PWM1C PH2/PWM1C PH2/PWM1C PH2/PWM1C

55 PH3/PWM1D PH3/PWM1D PH3/PWM1D PH3/PWM1D

56 PWMVcc PWMVcc PWMVcc PWMVcc

57 PH4/PWM1E PH4/PWM1E PH4/PWM1E PH4/PWM1E

58 PH5/PWM1F PH5/PWM1F PH5/PWM1F PH5/PWM1F

59 PH6/PWM1G PH6/PWM1G PH6/PWM1G PH6/PWM1G

60 PH7/PWM1H PH7/PWM1H PH7/PWM1H PH7/PWM1H

Pin Name

Pin No. Mode 4 Mode 5 Mode 6 Mode 7

61 PWMVss PWMVss PWMVss PWMVss

62 PJ0/PWM2A PJ0/PWM2A PJ0/PWM2A PJ0/PWM2A

63 PJ1/PWM2B PJ1/PWM2B PJ1/PWM2B PJ1/PWM2B

64 PJ2/PWM2C PJ2/PWM2C PJ2/PWM2C PJ2/PWM2C

65 PJ3/PWM2D PJ3/PWM2D PJ3/PWM2D PJ3/PWM2D

66 PWMVcc PWMVcc PWMVcc PWMVcc

67 PJ4/PWM2E PJ4/PWM2E PJ4/PWM2E PJ4/PWM2E

68 PJ5/PWM2F PJ5/PWM2F PJ5/PWM2F PJ5/PWM2F

69 PJ6/PWM2G PJ6/PWM2G PJ6/PWM2G PJ6/PWM2G

70 PJ7/PWM2H PJ7/PWM2H PJ7/PWM2H PJ7/PWM2H

71 PWMVss PWMVss PWMVss PWMVss

72 MD2 MD2 MD2 MD2

73 MD1 MD1 MD1 MD1

74 MD0 MD0 MD0 MD0

75 P30/TxD0 P30/TxD0 P30/TxD0 P30/TxD0

76 P31/RxD0 P31/RxD0 P31/RxD0 P31/RxD0

77 P32/SCK0/IRQ4 P32/SCK0/IRQ4 P32/SCK0/IRQ4 P32/SCK0/IRQ4

78 P33/TxD1 P33/TxD1 P33/TxD1 P33/TxD1

79 P34/RxD1 P34/RxD1 P34/RxD1 P34/RxD1

80 P35/SCK1/IRQ5 P35/SCK1/IRQ5 P35/SCK1/IRQ5 P35/SCK1/IRQ5

81 P36 P36 P36 P36

82 P37 P37 P37 P37

83 RES RES RES RES

84 NMI NMI NMI NMI

85 STBY STBY STBY STBY

86 PLLVss PLLVss PLLVss PLLVss

87 PLLCAP PLLCAP PLLCAP PLLCAP

88 Vss Vss Vss Vss

89 OSC1 OSC1 OSC1 OSC1

90 OSC2 OSC2 OSC2 OSC2

91 Vcc Vcc Vcc Vcc

92 Vcc Vcc Vcc Vcc

Pin Name

Pin No. Mode 4 Mode 5 Mode 6 Mode 7

93 VCL VCL VCL VCL

94 XTAL XTAL XTAL XTAL

95 Vss Vss Vss Vss

96 EXTAL EXTAL EXTAL EXTAL

97 FWE FWE FWE FWE

98 PF0/IRQ2 PF0/IRQ2 PF0/IRQ2 PF0/IRQ2

99 PF3/LWR/ADTRG/IRQ3 PF3/LWR/ADTRG/IRQ3 PF3/LWR/ADTRG/IRQ3 PF3/ADTRG/IRQ3

100 PF7/φPF7/φPF7/φPF7/φ

101 P10/PO8/TIOCA0 P10/PO8/TIOCA0 P10/PO8/TIOCA0 P10/PO8/TIOCA0

102 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P11/PO9/TIOCB0

103 P12/PO10/TIOCC0/

TCLKA P12/PO10/TIOCC0/

TCLKA

104 P13/PO11/TIOCD0/

TCLKB P13/PO11/TIOCD0/

TCLKB

105 P14/PO12/TIOCA1/

IRQ0

P14/PO12/TIOCA1/

IRQ0

P14/PO12/TIOCA1/

IRQ0

P14/PO12/TIOCA1/

IRQ0

106 P15/PO13/TIOCB1/

TCLKC P15/PO13/TIOCB1/

TCLKC

107 P16/PO14/TIOCA2/

IRQ1

P16/PO14/TIOCA2/

IRQ1

P16/PO14/TIOCA2/

IRQ1

P16/PO14/TIOCA2/

IRQ1

108 P17/PO15/TIOCB2/

TCLKD P17/PO15/TIOCB2/

TCLKD

109 HTxD HTxD HTxD HTxD

110 HRxD HRxD HRxD HRxD

111 P50 P50 P50 P50

112 P51 P51 P51 P51

113 P52 P52 P52 P52

114 P20/TIOCA3 P20/TIOCA3 P20/TIOCA3 P20/TIOCA3

115 P21/TIOCB3 P21/TIOCB3 P21/TIOCB3 P21/TIOCB3

116 P22/TIOCC3 P22/TIOCC3 P22/TIOCC3 P22/TIOCC3

117 P23/TIOCD3 P23/TIOCD3 P23/TIOCD3 P23/TIOCD3

118 P25/TIOCB4 P25/TIOCB4 P25/TIOCB4 P25/TIOCB4

119 Vcc Vcc Vcc Vcc

120 P24/TIOCA4 P24/TIOCA4 P24/TIOCA4 P24/TIOCA4

Pin Name

Pin No. Mode 4 Mode 5 Mode 6 Mode 7

121 PK6 PK6 PK6 PK6

122 P27/TIOCB5 P27/TIOCB5 P27/TIOCB5 P27/TIOCB5

123 Vss Vss Vss Vss

124 P26/TIOCA5 P26/TIOCA5 P26/TIOCA5 P26/TIOCA5

125 PK7 PK7 PK7 PK7

126 AVcc AVcc AVcc AVcc

127 Vref Vref Vref Vref

128 P40/AN0 P40/AN0 P40/AN0 P40/AN0

129 P41/AN1 P41/AN1 P41/AN1 P41/AN1

130 P42/AN2 P42/AN2 P42/AN2 P42/AN2

131 P43/AN3 P43/AN3 P43/AN3 P43/AN3

132 P44/AN4 P44/AN4 P44/AN4 P44/AN4

133 P45/AN5 P45/AN5 P45/AN5 P45/AN5

134 P46/AN6 P46/AN6 P46/AN6 P46/AN6

135 P47/AN7 P47/AN7 P47/AN7 P47/AN7

136 P90/AN8 P90/AN8 P90/AN8 P90/AN8

137 P91/AN9 P91/AN9 P91/AN9 P91/AN9

138 P92/AN10 P92/AN10 P92/AN10 P92/AN10

139 P93/AN11 P93/AN11 P93/AN11 P93/AN11

140 P94 P94 P94 P94

141 P95 P95 P95 P95

142 P96 P96 P96 P96

143 P97 P97 P97 P97

144 AVss AVss AVss AVss

Note: In mode 4 and mode 5 the following pins (D8 to D15, A0 to A7, RD, AS, HWR) are used to

interface with external ROM. Therefore, these pins must not be set to the SEG signal.

Table 1-2 (2) Pin Functions in Each Operating Mode (H8S/2648, H8S/2648R, H8S/2647)

Pin Name

Pin No. Mode 4 Mode 5 Mode 6 Mode 7

1V1V1V1V1

2V2V2V2V2

3V3V3V3V3

4 PE0/D0/SEG1 PE0/D0/SEG1 PE0/D0/SEG1 PE0/SEG1

5 PE1/D1/SEG2 PE1/D1/SEG2 PE1/D1/SEG2 PE1/SEG2

6 PE2/D2/SEG3 PE2/D2/SEG3 PE2/D2/SEG3 PE2/SEG3

7 PE3/D3/SEG4 PE3/D3/SEG4 PE3/D3/SEG4 PE3/SEG4

8 PE4/D4/SEG5 PE4/D4/SEG5 PE4/D4/SEG5 PE4/SEG5

9 PE5/D5/SEG6 PE5/D5/SEG6 PE5/D5/SEG6 PE5/SEG6

10 PE6/D6/SEG7 PE6/D6/SEG7 PE6/D6/SEG7 PE6/SEG7

11 PE7/D7/SEG8 PE7/D7/SEG8 PE7/D7/SEG8 PE7/SEG8

12 Vss Vss Vss Vss

13 D8 D8 D8/SEG9 PD0/SEG9

14 D9 D9 D9/SEG10 PD1/SEG10

15 D10 D10 D10/SEG11 PD2/SEG11

16 D11 D11 D11/SEG12 PD3/SEG12

17 D12 D12 D12/SEG13 PD4/SEG13

18 D13 D13 D13/SEG14 PD5/SEG14

19 D14 D14 D14/SEG15 PD6/SEG15

20 D15 D15 D15/SEG16 PD7/SEG16

21 LPVcc LPVcc LPVcc LPVcc

22 A0 A0 PC0/A0/SEG17 PC0/SEG17

23 A1 A1 PC1/A1/SEG18 PC1/SEG18

24 A2 A2 PC2/A2/SEG19 PC2/SEG19

25 A3 A3 PC3/A3/SEG20 PC3/SEG20

26 A4 A4 PC4/A4/SEG21 PC4/SEG21

27 A5 A5 PC5/A5/SEG22 PC5/SEG22

Pin Name

Pin No. Mode 4 Mode 5 Mode 6 Mode 7

28 A6 A6 PC6/A6/SEG23 PC6/SEG23

29 A7 A7 PC7/A7/SEG24 PC7/SEG24

30 PB0/A8/SEG25 PB0/A8/SEG25 PB0/A8/SEG25 PB0/SEG25

31 PB1/A9/SEG26 PB1/A9/SEG26 PB1/A9/SEG26 PB1/SEG26

32 PB2/A10/SEG27 PB2/A10/SEG27 PB2/A10/SEG27 PB2/SEG27

33 PB3/A11/SEG28 PB3/A11/SEG28 PB3/A11/SEG28 PB3/SEG28

34 PB4/A12/SEG29 PB4/A12/SEG29 PB4/A12/SEG29 PB4/SEG29

35 PB5/A13/SEG30 PB5/A13/SEG30 PB5/A13/SEG30 PB5/SEG30

36 PB6/A14/SEG31 PB6/A14/SEG31 PB6/A14/SEG31 PB6/SEG31

37 PB7/A15/SEG32 PB7/A15/SEG32 PB7/A15/SEG32 PB7/SEG32

38 WAIT/SEG33 WAIT/SEG33 WAIT/SEG33 PF2/SEG33

39 HWR/SEG34 HWR/SEG34 HWR/SEG34 PF4/SEG34

40 Vss Vss Vss Vss

41 RD/SEG35 RD/SEG35 RD/SEG35 PF5/SEG35

42 AS/SEG36 AS/SEG36 AS/SEG36 PF6/SEG36

43 PA4/A20/SEG37 PA4/A20/SEG37 PA4/A20/SEG37 PA4/SEG37

44 PA5/A21/SEG38 PA5/A21/SEG38 PA5/A21/SEG38 PA5/SEG38

45 PA6/A22/SEG39 PA6/A22/SEG39 PA6/A22/SEG39 PA6/SEG39

46 PA7/A23/SEG40 PA7/A23/SEG40 PA7/A23/SEG40 PA7/SEG40

47 PA0/A16/COM1 PA0/A16/COM1 PA0/A16/COM1 PA0/COM1

48 PA1/A17/COM2 PA1/A17/COM2 PA1/A17/COM2 PA1/COM2

49 PA2/A18/COM3 PA2/A18/COM3 PA2/A18/COM3 PA2/COM3

50 PA3/A19/COM4 PA3/A19/COM4 PA3/A19/COM4 PA3/COM4

51 PWMVss PWMVss PWMVss PWMVss

52 PH0/PWM1A PH0/PWM1A PH0/PWM1A PH0/PWM1A

53 PH1/PWM1B PH1/PWM1B PH1/PWM1B PH1/PWM1B

54 PH2/PWM1C PH2/PWM1C PH2/PWM1C PH2/PWM1C

55 PH3/PWM1D PH3/PWM1D PH3/PWM1D PH3/PWM1D

56 PWMVcc PWMVcc PWMVcc PWMVcc

57 PH4/PWM1E PH4/PWM1E PH4/PWM1E PH4/PWM1E

58 PH5/PWM1F PH5/PWM1F PH5/PWM1F PH5/PWM1F

59 PH6/PWM1G PH6/PWM1G PH6/PWM1G PH6/PWM1G

60 PH7/PWM1H PH7/PWM1H PH7/PWM1H PH7/PWM1H

Pin Name

Pin No. Mode 4 Mode 5 Mode 6 Mode 7

61 PWMVss PWMVss PWMVss PWMVss

62 PJ0/PWM2A PJ0/PWM2A PJ0/PWM2A PJ0/PWM2A

63 PJ1/PWM2B PJ1/PWM2B PJ1/PWM2B PJ1/PWM2B

64 PJ2/PWM2C PJ2/PWM2C PJ2/PWM2C PJ2/PWM2C

65 PJ3/PWM2D PJ3/PWM2D PJ3/PWM2D PJ3/PWM2D

66 PWMVcc PWMVcc PWMVcc PWMVcc

67 PJ4/PWM2E PJ4/PWM2E PJ4/PWM2E PJ4/PWM2E

68 PJ5/PWM2F PJ5/PWM2F PJ5/PWM2F PJ5/PWM2F

69 PJ6/PWM2G PJ6/PWM2G PJ6/PWM2G PJ6/PWM2G

70 PJ7/PWM2H PJ7/PWM2H PJ7/PWM2H PJ7/PWM2H

71 PWMVss PWMVss PWMVss PWMVss

72 MD2 MD2 MD2 MD2

73 MD1 MD1 MD1 MD1

74 MD0 MD0 MD0 MD0

75 P30/TxD0 P30/TxD0 P30/TxD0 P30/TxD0

76 P31/RxD0 P31/RxD0 P31/RxD0 P31/RxD0

77 P32/SCK0/IRQ4 P32/SCK0/IRQ4 P32/SCK0/IRQ4 P32/SCK0/IRQ4

78 P33/TxD1 P33/TxD1 P33/TxD1 P33/TxD1

79 P34/RxD1 P34/RxD1 P34/RxD1 P34/RxD1

80 P35/SCK1/IRQ5 P35/SCK1/IRQ5 P35/SCK1/IRQ5 P35/SCK1/IRQ5

81 P36 P36 P36 P36

82 P37 P37 P37 P37

83 RES RES RES RES

84 NMI NMI NMI NMI

85 STBY STBY STBY STBY

86 PLLVss PLLVss PLLVss PLLVss

87 PLLCAP PLLCAP PLLCAP PLLCAP

88 Vss Vss Vss Vss

89 OSC1 OSC1 OSC1 OSC1

90 OSC2 OSC2 OSC2 OSC2

91 Vcc Vcc Vcc Vcc

92 Vcc Vcc Vcc Vcc

Pin Name

Pin No. Mode 4 Mode 5 Mode 6 Mode 7

93 VCL VCL VCL VCL

94 XTAL XTAL XTAL XTAL

95 Vss Vss Vss Vss

96 EXTAL EXTAL EXTAL EXTAL

97 FWE FWE FWE FWE

98 PF0/IRQ2 PF0/IRQ2 PF0/IRQ2 PF0/IRQ2

99 PF3/LWR/ADTRG/IRQ3 PF3/LWR/ADTRG/IRQ3 PF3/LWR/ADTRG/IRQ3 PF3/ADTRG/IRQ3

100 PF7/φPF7/φPF7/φPF7/φ

101 P10/PO8/TIOCA0 P10/PO8/TIOCA0 P10/PO8/TIOCA0 P10/PO8/TIOCA0

102 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P11/PO9/TIOCB0

103 P12/PO10/TIOCC0/

TCLKA P12/PO10/TIOCC0/

TCLKA

104 P13/PO11/TIOCD0/

TCLKB P13/PO11/TIOCD0/

TCLKB

105 P14/PO12/TIOCA1/

IRQ0

P14/PO12/TIOCA1/

IRQ0

P14/PO12/TIOCA1/

IRQ0

P14/PO12/TIOCA1/

IRQ0

106 P15/PO13/TIOCB1/

TCLKC P15/PO13/TIOCB1/

TCLKC

107 P16/PO14/TIOCA2/

IRQ1

P16/PO14/TIOCA2/

IRQ1

P16/PO14/TIOCA2/

IRQ1

P16/PO14/TIOCA2/

IRQ1

108 P17/PO15/TIOCB2/

TCLKD P17/PO15/TIOCB2/

TCLKD

109 HTxD HTxD HTxD HTxD

110 HRxD HRxD HRxD HRxD

111 P50/TxD2 P50/TxD2 P50/TxD2 P50/TxD2

112 P51/RxD2 P51/RxD2 P51/RxD2 P51/RxD2

113 P52/SCK2 P52/SCK2 P52/SCK2 P52/SCK2

114 P20/TIOCA3 P20/TIOCA3 P20/TIOCA3 P20/TIOCA3

115 P21/TIOCB3 P21/TIOCB3 P21/TIOCB3 P21/TIOCB3

116 P22/TIOCC3 P22/TIOCC3 P22/TIOCC3 P22/TIOCC3

117 P23/TIOCD3 P23/TIOCD3 P23/TIOCD3 P23/TIOCD3

118 P25/TIOCB4 P25/TIOCB4 P25/TIOCB4 P25/TIOCB4

119 Vcc Vcc Vcc Vcc

120 P24/TIOCA4 P24/TIOCA4 P24/TIOCA4 P24/TIOCA4

Pin Name

Pin No. Mode 4 Mode 5 Mode 6 Mode 7

121 PK6 PK6 PK6 PK6

122 P27/TIOCB5 P27/TIOCB5 P27/TIOCB5 P27/TIOCB5

123 Vss Vss Vss Vss

124 P26/TIOCA5 P26/TIOCA5 P26/TIOCA5 P26/TIOCA5

125 PK7 PK7 PK7 PK7

126 AVcc AVcc AVcc AVcc

127 Vref Vref Vref Vref

128 P40/AN0 P40/AN0 P40/AN0 P40/AN0

129 P41/AN1 P41/AN1 P41/AN1 P41/AN1

130 P42/AN2 P42/AN2 P42/AN2 P42/AN2

131 P43/AN3 P43/AN3 P43/AN3 P43/AN3

132 P44/AN4 P44/AN4 P44/AN4 P44/AN4

133 P45/AN5 P45/AN5 P45/AN5 P45/AN5

134 P46/AN6 P46/AN6 P46/AN6 P46/AN6

135 P47/AN7 P47/AN7 P47/AN7 P47/AN7

136 P90/AN8 P90/AN8 P90/AN8 P90/AN8

137 P91/AN9 P91/AN9 P91/AN9 P91/AN9

138 P92/AN10 P92/AN10 P92/AN10 P92/AN10

139 P93/AN11 P93/AN11 P93/AN11 P93/AN11

140 P94 P94 P94 P94

141 P95 P95 P95 P95

142 P96 P96 P96 P96

143 P97 P97 P97 P97

144 AVss AVss AVss AVss

Note: In mode 4 and mode 5 the following pins (D8 to D15, A0 to A7, RD, AS, HWR) are used to

interface with external ROM. Therefore, these pins must not be set to the SEG signal.

1.3.3 Pin Functions

Table 1-3 outlines the pin functions of the H8S/2646.

Table 1-3 Pin Functions

Type Symbol I/O Name and Function

Power Vcc Input Power supply: For connection to the power supply.

All Vcc pins should be connected to the system power

supply.

PWMVcc Input PWM port power supply: Power supply pin for port H,

port J, and the motor control PWM timer output

LPVcc Input Port power supply: Power supply pin for ports A, B, C,

D, E, and part of port F (PF2 and PF4 to PF6)

V1, V2, V3 Input LCD power supply: Power supply pin for LCD

controller/driver. There is an on-chip power supply

division resistor, so this pin is normally left open.

Power supply conditions: LPVcc ≥ V1 ≥ V2 ≥ V3 ≥ Vss

Vss Input Ground: For connection to ground (0 V). All Vss pins

should be connected to the system power supply (0 V).

PWMVss Input Ground: Power supply pin for port H, port J, and the

motor control PWM timer output. Connect all pins to

the system power supply (0 V)

VCL Input On-chip step-down power supply pin: Pin for

connecting the on-chip step-down power supply to a

capacitor for voltage stabilization. Connect to Vss via a

0.1 µF capacitor (which should be located near the

pin). Do not connect this pin to an external power

supply.

Clock PLLVss Input PLL ground: Ground for on-chip PLL oscillator.

PLLCAP Input PLL capacitance: External capacitance pin for on-chip

PLL oscillator.

XTAL Input Connects to a crystal oscillator.

See section 21, Clock Pulse Generator, for typical

connection diagrams for a crystal oscillator.

Use a crystal resonator for the system clock pulse

generator. External clock drive cannot be used.

EXTAL Input Connects to a crystal oscillator.

See section 21, Clock Pulse Generator, for typical

connection diagrams for a crystal oscillator.

OSC1 Input Subclock: Connects to a 32 kHz crystal oscillator.

See section 21, Clock Pulse Generator, for typical

connection diagrams for a crystal oscillator.

Type Symbol I/O Name and Function

Clock OSC2 Input Subclock: Connects to a 32 kHz crystal oscillator.

See section 21, Clock Pulse Generator, for typical

connection diagrams for a crystal oscillator.

øOutput System clock: Supplies the system clock to an external

device.

Operating mode

control MD2 to MD0 Input Mode pins: These pins set the operating mode.

The relation between the settings of pins MD2 to MD0

and the operating mode is shown below. These pins

should not be changed while the H8S/2646 Series is

operating.

MD2 MD1 MD0 Operating Mode

000—

1—

10—

1—

1 0 0 Mode 4

1 Mode 5

1 0 Mode 6

1 Mode 7

System control RES Input Reset input: When this pin is driven low, the chip is

reset.

STBY Input Standby: When this pin is driven low, a transition is

made to hardware standby mode.

FWE Input Flash write enable: Pin for flash memory use (in

planning stage).

Interrupts NMI Input Nonmaskable interrupt: Requests a nonmaskable

interrupt. When this pin is not used, it should be fixed

high.

IRQ5 to IRQ0 Input Interrupt request 5 to 0: These pins request a

maskable interrupt.

Address bus A23 to A0 Output Address bus: These pins output an address.

Data bus D15 to D0 I/O Data bus: These pins constitute a bidirectional data

bus.

Bus control AS Output Address strobe: When this pin is low, it indicates that

address output on the address bus is enabled.

RD Output Read: When this pin is low, it indicates that the

external address space can be read.

Type Symbol I/O Name and Function

Bus control HWR Output High write: A strobe signal that writes to external space

and indicates that the upper half (D15 to D8) of the

data bus is enabled.

LWR Output Low write: A strobe signal that writes to external space

and indicates that the lower half (D7 to D0) of the data

bus is enabled.

WAIT Input Wait: It is necessary to insert a wait state into the bus

cycle when accessing the external three-state address

space.

16-bit timer

pulse unit (TPU) TCLKD to

TCLKA Input Clock input D to A: These pins input an external clock.

TIOCA0,

TIOCB0,

TIOCC0,

TIOCD0

I/O Input capture/ output compare match A0 to D0:

The TGR0A to TGR0D input capture input or output

compare output, or PWM output pins.

TIOCA1,

TIOCB1 I/O Input capture/ output compare match A1 and B1:

The TGR1A and TGR1B input capture input or output

compare output, or PWM output pins.

TIOCA2,

TIOCB2 I/O Input capture/ output compare match A2 and B2:

The TGR2A and TGR2B input capture input or output

compare output, or PWM output pins.

TIOCA3,

TIOCB3,

TIOCC3,

TIOCD3

I/O Input capture/ output compare match A3 to D3:

The TGR3A to TGR3D input capture input or output

compare output, or PWM output pins.

TIOCA4,

TIOCB4 I/O Input capture/output compare match A4 and B4:

The TGR4A and TGR4B input capture input or output

compare output, or PWM output pins.

TIOCA5,

TIOCB5 I/O Input capture/output compare match A5 and B5:

The TGR5A and TGR5B input capture input or output

compare output, or PWM output pins.

Programmable

pulse generator

(PPG)

PO15 to PO8 Output Pulse output 15 to 8: Pulse output pins.

Type Symbol I/O Name and Function

Serial

communication

interface (SCI)/

TxD1, TxD0 Output Transmit data: Data output pins.

Smart Card

interface RxD1, RxD0 Input Receive data: Data input pins.

H8S/2646,

H8S/2646R,

H8S/2645

SCK1, SCK0 I/O Serial clock: Clock I/O pins.

The SCK0 output type is NMOS push-pull.

Serial

communication

interface (SCI)/

TxD2 to

TxD0 Output Transmit data: Data output pins.

Smart Card

interface RxD2 to

RxD0 Input Receive data: Data input pins.

H8S/2648,

H8S/2648R,

H8S/2647

SCK2 to

SCK0 I/O Serial clock: Clock I/O pins.

The SCK0 output type is NMOS push-pull.

HCAN HTxD Output HCAN transmit data. Pin for CAN bus transmission.

HRxD Input HCAN receive data. Pin for CAN bus reception.

A/D converter AN11 to AN0 Input Analog 11 to 0: Analog input pins.

ADTRG Input A/D conversion external trigger input: Pin for input of

an external trigger to start A/D conversion.

AVcc Input Analog power supply: A/D converter power supply pin.

If the A/D converter is not used, connect this pin to the

system power supply (+5 V).

AVss Input Analog ground: Analog circuit ground and reference

voltage. Connect this pin to the system power supply

(0 V).

Vref Input Analog reference power supply: A/D converter

reference voltage input pin. If the A/D converter is not

used, connect this pin to the system power supply

(+5 V).

Motor control

PWM PWM1H to

PWM1A Output PWM output: Motor control PWM channel 1 output pins

PWM2H to

PWM2A Output PWM output: Motor control PWM channel 2 output pins

Type Symbol I/O Name and Function

LCD

controller/driver SEG24 to

SEG1

(H8S/2646,

H8S/2646R,

H8S/2645)

Output LCD segment output: LCD segment output pins

SEG40 to

SEG1

(H8S/2648,

H8S/2648R,

H8S/2647)

COM4 to

COM1 Output LCD common output: LCD common output pins

I/O ports P17 to P10 I/O Port 1: 8-bit I/O pins. Input or output can be designated

for each bit by means of the port 1 data direction

P27 to P20 I/O Port 2: 8-bit I/O pins. Input or output can be designated

for each bit by means of the port 2 data direction

P37 to P30 I/O Port 3: 8-bit I/O pins. Input or output can be designated

for each bit by means of the port 3 data direction

P47 to P40 Input Port 4: 8-bit input pins.

P52 to P50 I/O Port 5: 3-bit I/O pins. Input or output can be designated

for each bit by means of the port 5 data direction

P97 to P90 Input Port 9: 8-bit input pins.

PA7 to PA0 I/O Port A: 8-bit I/O pins. Input or output can be

designated for each bit by means of the port A data

direction register (PADDR).

PB7 to PB0 I/O Port B: 8-bit I/O pins. Input or output can be

designated for each bit by means of the port B data

direction register (PBDDR).

PC7 to PC0 I/O Port C: 8-bit I/O pins. Input or output can be

designated for each bit by means of the port C data

direction register (PCDDR).

PD7 to PD0 I/O Port D: 8-bit I/O pins. Input or output can be

designated for each bit by means of the port D data

direction register (PDDDR).

PE7 to PE0 I/O Port E: 8-bit I/O pins. Input or output can be

designated for each bit by means of the port E data

direction register (PEDDR).

Type Symbol I/O Name and Function

I/O ports PF7 to PF2,

PF0 I/O Port F: 7-bit I/O pins. Input or output can be designated

for each bit by means of the port F data direction

PH7 to PH0 I/O Port H: 8-bit I/O pins. Input or output can be

designated for each bit by means of the port H data

direction register (PHDDR).

PJ7 to PJ0 I/O Port J: 8-bit I/O pins. Input or output can be designated

for each bit by means of the port J data direction

PK6 to PK7 I/O Port K: 2-bit I/O pins. Input or output can be

designated for each bit by means of the port K data

direction register (PKDDR).

Section 2 CPU

2.1 Overview

The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that

is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit

general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is

ideal for realtime control.

2.1.1 Features

The H8S/2600 CPU has the following features.

• Upward-compatible with H8/300 and H8/300H CPUs

 Can execute H8/300 and H8/300H object programs

• General-register architecture

 Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit

registers)

• Sixty-nine basic instructions

 8/16/32-bit arithmetic and logic instructions

 Multiply and divide instructions

 Powerful bit-manipulation instructions

 Multiply-and-accumulate instruction

• Eight addressing modes

 Register direct [Rn]

 Register indirect [@ERn]

 Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]

 Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]

 Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]

 Immediate [#xx:8, #xx:16, or #xx:32]

 Program-counter relative [@(d:8,PC) or @(d:16,PC)]

 Memory indirect [@@aa:8]

• 16-Mbyte address space

 Program: 16 Mbytes

 Data: 16 Mbytes (4 Gbyte architecturally)

• High-speed operation

 All frequently-used instructions execute in one or two states

 Maximum clock rate : 20 MHz

 8/16/32-bit register-register add/subtract : 50 ns

 8 × 8-bit register-register multiply : 150 ns

 16 ÷ 8-bit register-register divide : 600 ns

 16 × 16-bit register-register multiply : 200 ns

 32 ÷ 16-bit register-register divide : 1000 ns

• Two CPU operating modes

 Normal mode*

 Advanced mode

Note: * Not available in the H8S/2646 Series.

• Power-down state

 Transition to power-down state by SLEEP instruction

 CPU clock speed selection

2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU

The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.

• Register configuration

The MAC register is supported only by the H8S/2600 CPU.

• Basic instructions

The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the

H8S/2600 CPU.

• Number of execution states

The number of execution states of the MULXU and MULXS instructions is different in each

CPU.

Execution States

Instruction Mnemonic H8S/2600 H8S/2000

MULXU MULXU.B Rs, Rd 3 12

MULXU.W Rs, ERd 4 20

MULXS MULXS.B Rs, Rd 4 13

MULXS.W Rs, ERd 5 21

In addition, there are differences in address space, CCR and EXR register functions, power-down

modes, etc., depending on the model.

2.1.3 Differences from H8/300 CPU

In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements.

• More general registers and control registers

 Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been

added.

• Expanded address space

 Normal mode* supports the same 64-kbyte address space as the H8/300 CPU.

 Advanced mode supports a maximum 16-Mbyte address space.

Note: * Not available in the H8S/2646 Series.

• Enhanced addressing

 The addressing modes have been enhanced to make effective use of the 16-Mbyte address

space.

• Enhanced instructions

 Addressing modes of bit-manipulation instructions have been enhanced.

 Signed multiply and divide instructions have been added.

 A multiply-and-accumulate instruction has been added.

 Two-bit shift instructions have been added.

 Instructions for saving and restoring multiple registers have been added.

 A test and set instruction has been added.

• Higher speed

 Basic instructions execute twice as fast.

2.1.4 Differences from H8/300H CPU

In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements.

• Additional control register

 One 8-bit and two 32-bit control registers have been added.

• Enhanced instructions

 Addressing modes of bit-manipulation instructions have been enhanced.

 A multiply-and-accumulate instruction has been added.

 Two-bit shift instructions have been added.

 Instructions for saving and restoring multiple registers have been added.

 A test and set instruction has been added.

• Higher speed

 Basic instructions execute twice as fast.

2.2 CPU Operating Modes

The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode* supports a

maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address

space (architecturally a maximum 16-Mbyte program area and a maximum of 4 Gbytes for

program and data areas combined). The mode is selected by the mode pins of the microcontroller.

Note: * Not available in the H8S/2646 Series.

CPU operating modes

Note: * Not available in the H8S/2646 Series.

Normal mode*

Advanced mode

Maximum 64 kbytes, program

and data areas combined

Maximum 16-Mbytes for

program and data areas

combined

Figure 2-1 CPU Operating Modes

(1) Normal Mode (Not Available in the H8S/2646 Series)

The exception vector table and stack have the same structure as in the H8/300 CPU.

Address Space: A maximum address space of 64 kbytes can be accessed.

Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as

the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain

any value, even when the corresponding general register (Rn) is used as an address register. If the

general register is referenced in the register indirect addressing mode with pre-decrement (@–Rn)

or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding

extended register (En) will be affected.

Instruction Set: All instructions and addressing modes can be used. Only the lower 16 bits of

effective addresses (EA) are valid.

Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area

starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16

bits (figure 2-2). The exception vector table differs depending on the microcontroller. For details

of the exception vector table, see section 4, Exception Handling.

H'0000

H'0001

H'0002

H'0003

H'0004

H'0005

H'0006

H'0007

H'0008

H'0009

H'000A

H'000B

Reset exception vector

Exception vector 1

Exception vector 2

Exception

vector table

(Reserved for system use)

Figure 2-2 Exception Vector Table (Normal Mode)

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses

an 8-bit absolute address included in the instruction code to specify a memory operand that

contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16-

bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note

that this area is also used for the exception vector table.

Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call,

and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto

the stack in exception handling, they are stored as shown in figure 2-3. When EXR is invalid, it is

not pushed onto the stack. For details, see section 4, Exception Handling.

(a) Subroutine Branch (b) Exception Handling

(16 bits) EXR*1

Reserved*1*3

CCR

CCR*3

(16 bits)

SP SP

Notes: *1

When EXR is not used it is not stored on the stack.

SP when EXR is not used.

Ignored when returning.

(SP )

Figure 2-3 Stack Structure in Normal Mode

(2) Advanced Mode

Address Space: Linear access is provided to a 16-Mbyte maximum address space (architecturally

a maximum 16-Mbyte program area and a maximum 4-Gbyte data area, with a maximum of 4

Gbytes for program and data areas combined).

Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as

the upper 16-bit segments of 32-bit registers or address registers.

Instruction Set: All instructions and addressing modes can be used.

Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top

area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32

bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2-4).

For details of the exception vector table, see section 4, Exception Handling.

H'00000000

H'00000003

H'00000004

H'0000000B

H'0000000C

Exception vector table

Reserved

Reset exception vector

(Reserved for system use)

Reserved

Exception vector 1

Reserved

H'00000010

H'00000008

H'00000007

Figure 2-4 Exception Vector Table (Advanced Mode)

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses

an 8-bit absolute address included in the instruction code to specify a memory operand that

contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing

a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as

H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the

first part of this range is also the exception vector table.

Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a

subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR)

are pushed onto the stack in exception handling, they are stored as shown in figure 2-5. When

EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling.

(a) Subroutine Branch (b) Exception Handling

(24 bits)

EXR*1

Reserved*1*3

CCR

(24 bits)

SP SP

Notes: *1

When EXR is not used it is not stored on the stack.

SP when EXR is not used.

Ignored when returning.

(SP )

Reserved

Figure 2-5 Stack Structure in Advanced Mode

2.3 Address Space

Figure 2-6 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear

access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte

(architecturally 4-Gbyte) address space in advanced mode.

(b) Advanced Mode

H'0000

H'FFFF

H'00000000

H'FFFFFFFF

H'00FFFFFF

(a) Normal Mode*

Data area

Program area

Cannot be

used by the

H8S/2646 Series

Note: * Not available in the H8S/2646 Series.

Figure 2-6 Memory Map

2.4 Register Configuration

2.4.1 Overview

The CPU has the internal registers shown in figure 2-7. There are two types of registers: general

registers and control registers.

————

I2 I1 I0EXR 76543210

23 0

15 07 07 0

R0H

R1H

R2H

R3H

R4H

R5H

R6H

R7H

R0L

R1L

R2L

R3L

R4L

R5L

R6L

R7L

General Registers (Rn) and Extended Registers (En)

Control Registers (CR)

Legend Stack pointer

Program counter

Extended control register

Trace bit

Interrupt mask bits

Condition-code register

Interrupt mask bit

User bit or interrupt mask bit*

SP:

PC:

EXR:

I2 to I0:

CCR:

UI:

Note: * Cannot be used as an interrupt mask bit in the H8S/2646 Series.

ER0

ER1

ER2

ER3

ER4

ER5

ER6

ER7 (SP)

HUNZVCCCR 76543210

Sign extension

63 32

031

MAC MACL

Half-carry flag

User bit

Negative flag

Zero flag

Overflow flag

Carry flag

Multiply-accumulate register

MAC:

MACH

Figure 2-7 CPU Registers

2.4.2 General Registers

The CPU has eight 32-bit general registers. These general registers are all functionally alike and

can be used as both address registers and data registers. When a general register is used as a data

as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).

The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R

(R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit

registers. The E registers (E0 to E7) are also referred to as extended registers.

The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and

RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit

registers.

Figure 2-8 illustrates the usage of the general registers. The usage of each register can be selected

independently.

• Address registers

• 32-bit registers • 16-bit registers • 8-bit registers

ER registers

(ER0 to ER7)

E registers (extended registers)

(E0 to E7)

R registers

(R0 to R7)

RH registers

(R0H to R7H)

RL registers

(R0L to R7L)

Figure 2-8 Usage of General Registers

General register ER7 has the function of stack pointer (SP) in addition to its general-register

function, and is used implicitly in exception handling and subroutine calls. Figure 2-9 shows the

stack.

Free area

Stack area

SP (ER7)

Figure 2-9 Stack

2.4.3 Control Registers

The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR),

8-bit condition-code register (CCR), and 64-bit multiply-accumulate register (MAC).

(1) Program Counter (PC): This 24-bit counter indicates the address of the next instruction the

CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant

PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.)

(2) Extended Control Register (EXR): This 8-bit register contains the trace bit (T) and three

interrupt mask bits (I2 to I0).

Bit 7—Trace Bit (T): Selects trace mode. When this bit is cleared to 0, instructions are executed

in sequence. When this bit is set to 1, a trace exception is generated each time an instruction is

executed.

Bits 6 to 3—Reserved: These bits are reserved. They are always read as 1.

Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to

7). For details, refer to section 5, Interrupt Controller.

Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC

instructions. All interrupts, including NMI, are disabled for three states after one of these

instructions is executed, except for STC.

(3) Condition-Code Register (CCR): This 8-bit register contains internal CPU status

information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z),

overflow (V), and carry (C) flags.

Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted

regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exception-

handling sequence. For details, refer to section 5, Interrupt Controller.

Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the

LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask

bit. For details, refer to section 5, Interrupt Controller.

Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B

instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0

otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is

set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L,

SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or

borrow at bit 27, and cleared to 0 otherwise.

Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and

XORC instructions.

Bit 3—Negative Flag (N): Stores the value of the most significant bit (sign bit) of data.

Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.

Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other

times.

Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:

• Add instructions, to indicate a carry

• Subtract instructions, to indicate a borrow

• Shift and rotate instructions, to store the value shifted out of the end bit

The carry flag is also used as a bit accumulator by bit manipulation instructions.

Some instructions leave some or all of the flag bits unchanged. For the action of each instruction

on the flag bits, refer to Appendix A.1, Instruction List.

Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC

instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch

(Bcc) instructions.

(4) Multiply-Accumulate Register (MAC): This 64-bit register stores the results of multiply-

and-accumulate operations. It consists of two 32-bit registers denoted MACH and MACL. The

lower 10 bits of MACH are valid; the upper bits are a sign extension.

2.4.4 Initial Register Values

Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the

trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits

and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized.

The stack pointer should therefore be initialized by an MOV.L instruction executed immediately

after a reset.

2.5 Data Formats

The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data.

Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte

operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit

BCD data.

2.5.1 General Register Data Formats

Figure 2-10 shows the data formats in general registers.

76543210 Don’t care

Don’t care 76543210

Don’t careUpper Lower

LSB

MSB LSB

Data Type Register Number Data Format

1-bit data

4-bit BCD data

Byte data

RnH

RnL

RnH

RnL

RnH

RnL

MSB

Don’t care Upper Lower

Don’t care

Don’t care 70

Figure 2-10 General Register Data Formats

MSB LSB

Word data

LSB

MSB

En Rn

General register ER

General register E

General register R

General register RH

General register RL

Most significant bit

Least significant bit

Legend

ERn:

En:

Rn:

RnH:

RnL:

MSB:

LSB:

MSB LSB

Longword data ERn

Data Type Register Number Data Format

Figure 2-10 General Register Data Formats (cont)

2.5.2 Memory Data Formats

Figure 2-11 shows the data formats in memory. The CPU can access word data and longword data

in memory, but word or longword data must begin at an even address. If an attempt is made to

access word or longword data at an odd address, no address error occurs but the least significant

bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to

instruction fetches.

76543210

MSB LSB

MSB

LSB

MSB

LSB

Data Type Data Format

1-bit data

Byte data

Word data

Longword data

Address

Address L

Address 2M

Address 2M + 1

Address 2N

Address 2N + 1

Address 2N + 2

Address 2N + 3

Figure 2-11 Memory Data Formats

When ER7 is used as an address register to access the stack, the operand size should be word size

or longword size.

2.6 Instruction Set

2.6.1 Overview

The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in

table 2-1.

Table 2-1 Instruction Classification

Function Instructions Size Types

Data transfer MOV BWL 5

POP*1, PUSH*1WL

LDM, STM L

MOVFPE*3, MOVTPE*3B

Arithmetic ADD, SUB, CMP, NEG BWL 23

operations ADDX, SUBX, DAA, DAS B

INC, DEC BWL

ADDS, SUBS L

MULXU, DIVXU, MULXS, DIVXS BW

EXTU, EXTS WL

TAS*4B

MAC, LDMAC, STMAC, CLRMAC —

Logic operations AND, OR, XOR, NOT BWL 4

Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL 8

Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,

BIAND, BOR, BIOR, BXOR, BIXOR B14

Branch Bcc*2, JMP, BSR, JSR, RTS —5

System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP —9

Block data transfer EEPMOV —1

Total: 69

Notes: B-byte size; W-word size; L-longword size.

*1 POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,

@-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L

ERn, @-SP.

*2 Bcc is the general name for conditional branch instructions.

*3 Not available in the H8S/2646 Series.

*4 Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

2.6.2 Instructions and Addressing Modes

Table 2-2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU

can use.

Table 2-2 Combinations of Instructions and Addressing Modes

Addressing Modes

Function

Data

transfer

Arithmetic

operations

Instruction

MOV BWL BWL BWL BWL BWL BWL B BWL —BWL ————

POP, PUSH —— ——————— ————WL

LDM, STM —— ——————— ————L

ADD, CMP BWL BWL ——————— —————

SUB WL BWL ——————— —————

ADDX, SUBX B B ——————— —————

ADDS, SUBS —L——————— —————

INC, DEC —BWL ——————— —————

DAA, DAS —B——————— —————

NEG —BWL ——————— —————

EXTU, EXTS —WL ——————— —————

TAS*2—— B—————— —————

MAC —— ——— ——— —————

CLRMAC —— ——————— ————

MOVFPE*1,—— —————B— —————

MOVTPE*1

MULXU, —BW ——————— —————

DIVXU

MULXS, —BW ——————— —————

DIVXS

LDMAC, —L——————— —————

STMAC

#xx

@ERn

@(d:16,ERn)

@(d:32,ERn)

@–ERn/@ERn+

@aa:8

@aa:16

@aa:24

@aa:32

@(d:8,PC)

@(d:16,PC)

@@aa:8

—

Addressing Modes

Function

Logic

operations

System

control

Block data transfer

Shift

Bit manipulation

Branch

Instruction

AND, OR, BWL BWL ——————— —————

XOR

ANDC, B — ——————— —————

ORC, XORC

Bcc, BSR —— ——————— — ——

JMP, JSR —— —————— ——— —

RTS —— ——————— ————

TRAPA —— ——————— ————

RTE —— ——————— ————

SLEEP —— ——————— ————

LDC B B WWWW—W—W————

STC —B WWWW—W—W————

NOT —BWL ——————— —————

—BWL ——————— —————

—BB———BB—B————

NOP —— ——————— ————

—— ——————— ————BW

Legend

B: Byte

W: Word

L: Longword

Notes: *1 Not available in the H8S/2646 Series.

*2 Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

#xx

@ERn

@(d:16,ERn)

@(d:32,ERn)

@–ERn/@ERn+

@aa:8

@aa:16

@aa:24

@aa:32

@(d:8,PC)

@(d:16,PC)

@@aa:8

—

2.6.3 Table of Instructions Classified by Function

Table 2-3 summarizes the instructions in each functional category. The notation used in table 2-3

is defined below.

Operation Notation

Rd General register (destination)*

Rs General register (source)*

Rn General register*

ERn General register (32-bit register)

MAC Multiply-accumulate register (32-bit register)

(EAd) Destination operand

(EAs) Source operand

EXR Extended control register

CCR Condition-code register

N N (negative) flag in CCR

Z Z (zero) flag in CCR

V V (overflow) flag in CCR

C C (carry) flag in CCR

PC Program counter

SP Stack pointer

#IMM Immediate data

disp Displacement

+ Addition

–Subtraction

×Multiplication

÷Division

∧Logical AND

∨Logical OR

⊕Logical exclusive OR

→Move

¬NOT (logical complement)

:8/:16/:24/:32 8-, 16-, 24-, or 32-bit length

Note: *General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to

R7, E0 to E7), and 32-bit registers (ER0 to ER7).

Table 2-3 Instructions Classified by Function

Type Instruction Size*1Function

Data transfer MOV B/W/L (EAs) → Rd, Rs → (EAd)

Moves data between two general registers or between a

general register and memory, or moves immediate data

to a general register.

MOVFPE B Cannot be used in the H8S/2646 Series.

MOVTPE B Cannot be used in the H8S/2646 Series.

POP W/L @SP+ → Rn

Pops a register from the stack. POP.W Rn is identical to

MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L

@SP+, ERn.

PUSH W/L Rn → @–SP

Pushes a register onto the stack. PUSH.W Rn is

identical to MOV.W Rn, @–SP. PUSH.L ERn is identical

to MOV.L ERn, @–SP.

LDM L @SP+ → Rn (register list)

Pops two or more general registers from the stack.

STM L Rn (register list) → @–SP

Pushes two or more general registers onto the stack.

Type Instruction Size*1Function

Arithmetic

operations ADD

SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd

Performs addition or subtraction on data in two general

registers, or on immediate data and data in a general

byte data in a general register. Use the SUBX or ADD

instruction.)

ADDX

SUBX B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd

Performs addition or subtraction with carry or borrow on

byte data in two general registers, or on immediate data

and data in a general register.

INC

DEC B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd

Increments or decrements a general register by 1 or 2.

(Byte operands can be incremented or decremented by

1 only.)

ADDS

SUBS L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd

Adds or subtracts the value 1, 2, or 4 to or from data in a

32-bit register.

DAA

DAS B Rd decimal adjust → Rd

Decimal-adjusts an addition or subtraction result in a

general register by referring to the CCR to produce 4-bit

BCD data.

MULXU B/W Rd × Rs → Rd

Performs unsigned multiplication on data in two general

registers: either 8 bits × 8 bits → 16 bits or 16 bits ×

16 bits → 32 bits.

MULXS B/W Rd × Rs → Rd

Performs signed multiplication on data in two general

registers: either 8 bits × 8 bits → 16 bits or 16 bits ×

16 bits → 32 bits.

DIVXU B/W Rd ÷ Rs → Rd

Performs unsigned division on data in two general

registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit

remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-

bit remainder.

Type Instruction Size*1Function

Arithmetic

operations DIVXS B/W Rd ÷ Rs → Rd

Performs signed division on data in two general

registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit

remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-

bit remainder.

CMP B/W/L Rd – Rs, Rd – #IMM

Compares data in a general register with data in another

general register or with immediate data, and sets CCR

bits according to the result.

NEG B/W/L 0 – Rd → Rd

Takes the two's complement (arithmetic complement) of

data in a general register.

EXTU W/L Rd (zero extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size,

or the lower 16 bits of a 32-bit register to longword size,

by padding with zeros on the left.

EXTS W/L Rd (sign extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size,

or the lower 16 bits of a 32-bit register to longword size,

by extending the sign bit.

TAS B @ERd – 0, 1 → (<bit 7> of @ERd)*2

Tests memory contents, and sets the most significant bit

(bit 7) to 1.

MAC —(EAs) × (EAd) + MAC → MAC

Performs signed multiplication on memory contents and

adds the result to the multiply-accumulate register. The

following operations can be performed:

16 bits × 16 bits + 32 bits → 32 bits, saturating

16 bits × 16 bits + 42 bits → 42 bits, non-saturating

CLRMAC —0 → MAC

Clears the multiply-accumulate register to zero.

LDMAC

STMAC L Rs → MAC, MAC → Rd

Transfers data between a general register and a

multiply-accumulate register.

Type Instruction Size*1Function

Logic

operations AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd

Performs a logical AND operation on a general register

and another general register or immediate data.

OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd

Performs a logical OR operation on a general register

and another general register or immediate data.

XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd

Performs a logical exclusive OR operation on a general

NOT B/W/L ¬ (Rd) → (Rd)

Takes the one's complement of general register

contents.

Shift

operations SHAL

SHAR B/W/L Rd (shift) → Rd

Performs an arithmetic shift on general register contents.

1-bit or 2-bit shift is possible.

SHLL

SHLR B/W/L Rd (shift) → Rd

Performs a logical shift on general register contents.

1-bit or 2-bit shift is possible.

ROTL

ROTR B/W/L Rd (rotate) → Rd

Rotates general register contents.

1-bit or 2-bit rotation is possible.

ROTXL

ROTXR B/W/L Rd (rotate) → Rd

Rotates general register contents through the carry flag.

1-bit or 2-bit rotation is possible.

Type Instruction Size*1Function

Bit-

manipulation

instructions

BSET B 1 → (<bit-No.> of <EAd>)

Sets a specified bit in a general register or memory

operand to 1. The bit number is specified by 3-bit

immediate data or the lower three bits of a general

BCLR B 0 → (<bit-No.> of <EAd>)

Clears a specified bit in a general register or memory

operand to 0. The bit number is specified by 3-bit

immediate data or the lower three bits of a general

BNOT B ¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)

Inverts a specified bit in a general register or memory

operand. The bit number is specified by 3-bit immediate

data or the lower three bits of a general register.

BTST B ¬ (<bit-No.> of <EAd>) → Z

Tests a specified bit in a general register or memory

operand and sets or clears the Z flag accordingly. The

bit number is specified by 3-bit immediate data or the

lower three bits of a general register.

BAND

BIAND

C ∧ (<bit-No.> of <EAd>) → C

ANDs the carry flag with a specified bit in a general

carry flag.

C ∧ [¬ (<bit-No.> of <EAd>) ] → C

ANDs the carry flag with the inverse of a specified bit in

a general register or memory operand and stores the

result in the carry flag.

The bit number is specified by 3-bit immediate data.

BOR

BIOR

C ∨ (<bit-No.> of <EAd>) → C

ORs the carry flag with a specified bit in a general

carry flag.

C ∨ ¬ (<bit-No.> of <EAd>) → C

ORs the carry flag with the inverse of a specified bit in a

general register or memory operand and stores the

result in the carry flag.

The bit number is specified by 3-bit immediate data.

Type Instruction Size*1Function

Bit-

manipulation

instructions

BXOR

BIXOR

C ⊕ (<bit-No.> of <EAd>) → C

Exclusive-ORs the carry flag with a specified bit in a

general register or memory operand and stores the

result in the carry flag.

C ⊕ [¬ (<bit-No.> of <EAd>) ] → C

Exclusive-ORs the carry flag with the inverse of a

specified bit in a general register or memory operand

and stores the result in the carry flag.

The bit number is specified by 3-bit immediate data.

BLD

BILD

(<bit-No.> of <EAd>) → C

Transfers a specified bit in a general register or memory

operand to the carry flag.

¬ (<bit-No.> of <EAd>) → C

Transfers the inverse of a specified bit in a general

The bit number is specified by 3-bit immediate data.

BST

BIST

C → (<bit-No.> of <EAd>)

Transfers the carry flag value to a specified bit in a

general register or memory operand.

¬ C → (<bit-No.> of <EAd>)

Transfers the inverse of the carry flag value to a

specified bit in a general register or memory operand.

The bit number is specified by 3-bit immediate data.

Type Instruction Size*1Function

Branch

instructions Bcc —Branches to a specified address if a specified condition

is true. The branching conditions are listed below.

Mnemonic Description Condition

BRA(BT) Always (true) Always

BRN(BF) Never (false) Never

BHI High C ∨ Z = 0

BLS Low or same C ∨ Z = 1

BCC(BHS) Carry clear

(high or same) C = 0

BCS(BLO) Carry set (low) C = 1

BNE Not equal Z = 0

BEQ Equal Z = 1

BVC Overflow clear V = 0

BVS Overflow set V = 1

BPL Plus N = 0

BMI Minus N = 1

BGE Greater or equal N ⊕ V = 0

BLT Less than N ⊕ V = 1

BGT Greater than Z∨(N ⊕ V) = 0

BLE Less or equal Z∨(N ⊕ V) = 1

JMP —Branches unconditionally to a specified address.

BSR —Branches to a subroutine at a specified address.

JSR —Branches to a subroutine at a specified address.

RTS —Returns from a subroutine

Type Instruction Size*1Function

System control TRAPA —Starts trap-instruction exception handling.

instructions RTE —Returns from an exception-handling routine.

SLEEP —Causes a transition to a power-down state.

LDC B/W (EAs) → CCR, (EAs) → EXR

Moves the source operand contents or immediate data

to CCR or EXR. Although CCR and EXR are 8-bit

registers, word-size transfers are performed between

them and memory. The upper 8 bits are valid.

STC B/W CCR → (EAd), EXR → (EAd)

Transfers CCR or EXR contents to a general register or

memory. Although CCR and EXR are 8-bit registers,

word-size transfers are performed between them and

memory. The upper 8 bits are valid.

ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR

Logically ANDs the CCR or EXR contents with

immediate data.

ORC B CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR

Logically ORs the CCR or EXR contents with immediate

data.

XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR

Logically exclusive-ORs the CCR or EXR contents with

immediate data.

NOP —PC + 2 → PC

Only increments the program counter.

Type Instruction Size*1Function

Block data

transfer

instruction

EEPMOV.B

EEPMOV.W

—

if R4L ≠ 0 then

Repeat @ER5+ → @ER6+

R4L–1 → R4L

Until R4L = 0

else next;

if R4 ≠ 0 then

Repeat @ER5+ → @ER6+

R4–1 → R4

Until R4 = 0

else next;

Transfers a data block according to parameters set in

general registers R4L or R4, ER5, and ER6.

R4L or R4: size of block (bytes)

ER5: starting source address

ER6: starting destination address

Execution of the next instruction begins as soon as the

transfer is completed.

Notes: *1 Size refers to the operand size.

B: Byte

W: Word

L: Longword

*2 Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

2.6.4 Basic Instruction Formats

The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation

field (op field), a register field (r field), an effective address extension (EA field), and a condition

field (cc).

(1) Operation Field: Indicates the function of the instruction, the addressing mode, and the

operation to be carried out on the operand. The operation field always includes the first four bits of

the instruction. Some instructions have two operation fields.

(2) Register Field: Specifies a general register. Address registers are specified by 3 bits, data

registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register

field.

(3) Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute

address, or a displacement.

(4) Condition Field: Specifies the branching condition of Bcc instructions.

Figure 2-12 shows examples of instruction formats.

op rn rm

NOP, RTS, etc.

ADD.B Rn, Rm, etc.

MOV.B @(d:16, Rn), Rm, etc.

(1) Operation field only

(2) Operation field and register fields

(3) Operation field, register fields, and effective address extension

rn rm

EA (disp)

(4) Operation field, effective address extension, and condition field

op cc EA (disp) BRA d:16, etc

Figure 2-12 Instruction Formats (Examples)

2.7 Addressing Modes and Effective Address Calculation

2.7.1 Addressing Mode

The CPU supports the eight addressing modes listed in table 2-4. Each instruction uses a subset of

these addressing modes. Arithmetic and logic instructions can use the register direct and

immediate modes. Data transfer instructions can use all addressing modes except program-counter

relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or

absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and

BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.

Table 2-4 Addressing Modes

No. Addressing Mode Symbol

1 Register direct Rn

2 Register indirect @ERn

3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn)

4 Register indirect with post-increment

@–ERn

5 Absolute address @aa:8/@aa:16/@aa:24/@aa:32

6 Immediate #xx:8/#xx:16/#xx:32

7 Program-counter relative @(d:8,PC)/@(d:16,PC)

8 Memory indirect @@aa:8

(1) Register Direct—Rn: The register field of the instruction specifies an 8-, 16-, or 32-bit

general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit

registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified

as 32-bit registers.

(2) Register Indirect—@ERn: The register field of the instruction code specifies an address

instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00).

(3) Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn): A 16-bit or 32-bit

displacement contained in the instruction is added to an address register (ERn) specified by the

displacement is sign-extended when added.

(4) Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn:

• Register indirect with post-increment—@ERn+

The register field of the instruction code specifies an address register (ERn) which contains the

address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address

access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or

longword transfer instruction, the register value should be even.

• Register indirect with pre-decrement—@-ERn

The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field

in the instruction code, and the result becomes the address of a memory operand. The result is

also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer

instruction, or 4 for longword transfer instruction. For word or longword transfer instruction,

the register value should be even.

(5) Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32: The instruction code contains the

absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits

long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32).

To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits

(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF).

For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can

access the entire address space.

A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8

bits are all assumed to be 0 (H'00).

Table 2-5 indicates the accessible absolute address ranges.

Table 2-5 Absolute Address Access Ranges

Absolute Address Normal Mode*Advanced Mode

Data address 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF

16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF,

H'FF8000 to H'FFFFFF

32 bits (@aa:32) H'000000 to H'FFFFFF

Program instruction

address 24 bits (@aa:24)

Note: *Not available in the H8S/2646 Series.

(6) Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit

(#xx:16), or 32-bit (#xx:32) immediate data as an operand.

The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit

manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit

number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a

vector address.

(7) Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and

BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and

added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch

address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the

displacement is added is the address of the first byte of the next instruction, so the possible

branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to

+16384 words) from the branch instruction. The resulting value should be an even number.

(8) Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The

instruction code contains an 8-bit absolute address specifying a memory operand. This memory

operand contains a branch address. The upper bits of the absolute address are all assumed to be 0,

so the address range is 0 to 255 (H'0000 to H'00FF in normal mode*, H'000000 to H'0000FF in

advanced mode). In normal mode* the memory operand is a word operand and the branch address

is 16 bits long. In advanced mode the memory operand is a longword operand, the first byte of

which is assumed to be all 0 (H'00).

Note that the first part of the address range is also the exception vector area. For further details,

refer to section 4, Exception Handling.

Note: * Not available in the H8S/2646 Series.

(a) Normal Mode*(b) Advanced Mode

Branch address

Specified

by @aa:8 Specified

by @aa:8 Reserved

Branch address

Note: * Not available in the H8S/2646 Series.

Figure 2-13 Branch Address Specification in Memory Indirect Mode

If an odd address is specified in word or longword memory access, or as a branch address, the

least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched

at the address preceding the specified address. (For further information, see section 2.5.2, Memory

Data Formats.)

2.7.2 Effective Address Calculation

Table 2-6 indicates how effective addresses are calculated in each addressing mode. In normal

mode* the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.

Note: * Not available in the H8S/2646 Series.

Table 2-6 Effective Address Calculation

pre-decrement

• Register indirect with post-increment @ERn+

No. Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)

1 Register direct (Rn)

op rm rn Operand is general register contents.

@(d:16, ERn) or @(d:32, ERn)

• Register indirect with pre-decrement @–ERn

General register contents

Sign extension disp

General register contents

1, 2, or 4

General register contents

1, 2, or 4

Byte

Word

Longword

Operand Size Value added

31 0

31 0 31 0

31 0

op r

rop

disp

24 23

Don’t care

24 23

Don’t care

24 23

Don’t care

24 23

Don’t care

@aa:8

Absolute address

@aa:16

@aa:32

6Immediate #xx:8/#xx:16/#xx:32

31 08 7

Operand is immediate data.

No. Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)

@aa:24

31 0

16 15

31 0

24 23

31 0

op abs

abs

op IMM

H'FFFF

Don’t care

24 23

Don’t care

24 23

Don’t care

24 23

Don’t care Sign extension

7Program-counter relative

@(d:8, PC)/@(d:16, PC)

8Memory indirect @@aa:8

• Normal mode*

• Advanced mode

No. Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)

31 8 7

disp

H'000000

abs

H'000000

31 0

24 23

31 0

16 15

31 0

24 23

op disp

op abs

Sign

extension

PC contents

abs

Memory contents

H'00

Don’t care

24 23

Don’t care

Note: * Not available in the H8S/2646 Series.

2.8 Processing States

2.8.1 Overview

The CPU has five main processing states: the reset state, exception handling state, program

execution state, bus-released state, and power-down state. Figure 2-14 shows a diagram of the

processing states. Figure 2-15 indicates the state transitions.

Reset state

The CPU and all on-chip supporting modules have been

initialized and are stopped.

Exception-handling

state

A transient state in which the CPU changes the normal

processing flow in response to a reset, interrupt, or trap

instruction.

Program execution

state

The CPU executes program instructions in sequence.

Bus-released state

The external bus has been released in response to a bus

request signal from a bus master other than the CPU.

Power-down state

CPU operation is stopped

to conserve power.*

Sleep mode

Software standby

mode

Hardware standby

mode

Processing

states

Note:

*The power-down state also includes a medium-speed mode, module stop mode,

subactive mode, subsleep mode, and watch mode.

Figure 2-14 Processing States

Exception handling state

Bus-released state

Hardware standby mode*2

Software standby mode

Reset state *1

Sleep mode

Power-down state*3

Program execution state

End of bus request

Bus request

Interrupt request

External interrupt request

RES= High

Request for exception handling

STBY= High, RES= Low

End of bus

request

Bus request

SLEEP

instruction

with

SSBY = 0

SLEEP

instruction

with

SSBY = 1

Notes: *1

From any state except hardware standby mode, a transition to the reset state occurs whenever RES

goes low. A transition can also be made to the reset state when the

watchdog timer overflows.

From any state, a transition to hardware standby mode occurs when STBY goes low.

Apart from these states, there are also the watch mode, subactive mode, and the subsleep mode.

See section 22, Power-Down Modes.

End of exception

handling

Figure 2-15 State Transitions

2.8.2 Reset State

When the RES goes low, all current processing stops and the CPU enters the reset state. In reset

state all interrupts are disenabled.

Reset exception handling starts when the RES signal changes from low to high.

The reset state can also be entered by a watchdog timer overflow. For details, refer to section 12,

Watchdog Timer.

2.8.3 Exception-Handling State

The exception-handling state is a transient state that occurs when the CPU alters the normal

processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address

(vector) from the exception vector table and branches to that address.

(1) Types of Exception Handling and Their Priority

Exception handling is performed for traces, resets, interrupts, and trap instructions. Table 2-7

indicates the types of exception handling and their priority. Trap instruction exception handling is

always accepted, in the program execution state.

Exception handling and the stack structure depend on the interrupt control mode set in SYSCR.

Table 2-7 Exception Handling Types and Priority

Priority Type of Exception Detection Timing Start of Exception Handling

High Reset Synchronized with clock Exception handling starts

immediately after a low-to-high

transition at the RES pin, or

when the watchdog timer

overflows.

Trace End of instruction

execution or end of

exception-handling

sequence*1

When the trace (T) bit is set to

1, the trace starts at the end of

the current instruction or current

exception-handling sequence

Interrupt End of instruction

execution or end of

exception-handling

sequence*2

When an interrupt is requested,

exception handling starts at the

end of the current instruction or

current exception-handling

sequence

Low

Trap instruction When TRAPA instruction

is executed Exception handling starts when

a trap (TRAPA) instruction is

executed*3

Notes: *1 Traces are enabled only in interrupt control mode 2. Trace exception-handling is not

executed at the end of the RTE instruction.

*2 Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions,

or immediately after reset exception handling.

*3 Trap instruction exception handling is always accepted, in the program execution state.

(2) Reset Exception Handling

After the RES pin has gone low and the reset state has been entered, when RES goes high again,

reset exception handling starts. The CPU enters the reset state when the RES is low. When reset

exception handling starts the CPU fetches a start address (vector) from the exception vector table

and starts program execution from that address. All interrupts, including NMI, are disabled during

reset exception handling and after it ends.

(3) Traces

Traces are enabled only in interrupt control mode 2. Trace mode is entered when the T bit of EXR

is set to 1. When trace mode is established, trace exception handling starts at the end of each

instruction.

At the end of a trace exception-handling sequence, the T bit of EXR is cleared to 0 and trace mode

is cleared. Interrupt masks are not affected.

The T bit saved on the stack retains its value of 1, and when the RTE instruction is executed to

return from the trace exception-handling routine, trace mode is entered again. Trace exception-

handling is not executed at the end of the RTE instruction.

Trace mode is not entered in interrupt control mode 0, regardless of the state of the T bit.

(4) Interrupt Exception Handling and Trap Instruction Exception Handling

When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer

(ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU

alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start

address (vector) from the exception vector table and program execution starts from that start

address.

Figure 2-16 shows the stack after exception handling ends.

CCR

(24 bits)

CCR

(24 bits)

EXR

Reserved*1

(a) Interrupt control mode 0 (b) Interrupt control mode 2

CCR

CCR*1

(16 bits)

CCR

CCR*1

(16 bits)

EXR

Reserved*1

Normal mode*2

Advanced mode

Notes: *1 Ignored when returning.

*2 Not available in the H8S/2646 Series.

Figure 2-16 Stack Structure after Exception Handling (Examples)

2.8.4 Program Execution State

In this state the CPU executes program instructions in sequence.

2.8.5 Bus-Released State

This is a state in which the bus has been released in response to a bus request from a bus master

other than the CPU. While the bus is released, the CPU halts operations.

Bus masters other than the CPU is data transfer controller (DTC).

For further details, refer to section 7, Bus Controller.

2.8.6 Power-Down State

The power-down state includes both modes in which the CPU stops operating and modes in which

the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode,

software standby mode, hardware standby mode, subsleep mode, and watch mode. There are also

three other power-down modes: medium-speed mode, module stop mode, and subactive mode. In

medium-speed mode the CPU and other bus masters operate on a medium-speed clock. Module

stop mode permits halting of the operation of individual modules, other than the CPU. Subactive

mode, subsleep mode, and watch mode are power-down states using subclock input. For details,

refer to section 22, Power-Down Modes.

(1) Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while

the software standby bit (SSBY) in the standby control register (SBYCR) is cleared to 0. In sleep

mode, CPU operations stop immediately after execution of the SLEEP instruction. The contents of

CPU registers are retained.

(2) Software Standby Mode: A transition to software standby mode is made if the SLEEP

instruction is executed while the SSBY bit in SBYCR is set to 1, the LSON bit in LPWRCR is set

to 0, and the PSS bit in TCSR (WDT1) is set to 0. In software standby mode, the CPU and clock

halt and all MCU operations stop. As long as a specified voltage is supplied, the contents of CPU

registers and on-chip RAM are retained. The I/O ports also remain in their existing states.

(3) Hardware Standby Mode: A transition to hardware standby mode is made when the STBY

pin goes low. In hardware standby mode, the CPU and clock halt and all MCU operations stop.

The on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip

RAM contents are retained.

2.9 Basic Timing

2.9.1 Overview

The H8S/2600 CPU is driven by a system clock, denoted by the symbol ø. The period from one

rising edge of ø to the next is referred to as a "state." The memory cycle or bus cycle consists of

one, two, or three states. Different methods are used to access on-chip memory, on-chip

supporting modules, and the external address space.

2.9.2 On-Chip Memory (ROM, RAM)

On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and

word transfer instruction. Figure 2-17 shows the on-chip memory access cycle. Figure 2-18 shows

the pin states.

Internal address bus

Internal read signal

Internal data bus

Internal write signal

Internal data bus

Bus cycle

Address

Read data

Write data

Read

access

Write

access

Figure 2-17 On-Chip Memory Access Cycle

Bus cycle

HeldAddress bus

HWR, LWR

Data bus

High

High-impedance state

Figure 2-18 Pin States during On-Chip Memory Access

2.9.3 On-Chip Supporting Module Access Timing

The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits

wide, depending on the particular internal I/O register being accessed. Figure 2-19 shows the

access cycle for the on-chip supporting modules. Figure 2-20 shows the pin states.

Bus cycle

T1 T2

Address

Read data

Write data

Internal read signal

Internal data bus

Internal write signal

Internal data bus

Read

access

Write

access

Internal address bus

Figure 2-19 On-Chip Supporting Module Access Cycle

Bus cycle

T1 T2

Held

Address bus

HWR, LWR

Data bus

High

High-impedance state

Figure 2-20 Pin States during On-Chip Supporting Module Access

2.9.4 On-Chip HCAN Module Access Timing

On-chip HCAN module access is performed in four states. The data bus width is 16 bits. Wait

states can be inserted by means of a wait request from the HCAN. On-chip HCAN module access

cycle is shown in figures 2-21 and 2-22, and the pin states in figure 2-23.

Internal address bus

HCAN read signal

Internal data bus

HCAN write signal

Internal data bus

Bus cycle

Address

Read

Write

Read data

Write data

T2 T4

Figure 2-21 On-Chip HCAN Module Access Cycle (No Wait State)

Internal address bus

HCAN read signal

Internal data bus

HCAN write signal

Internal data bus

Bus cycle

Address

Read

Write

T2 Tw

Read data

Write data

Tw T4

Figure 2-22 On-Chip HCAN Module Access Cycle (Wait States Inserted)

T1 T3

T2 T4

Bus cycle

HWR, LWR

Data bus

High

HeldAddress bus

High-impedance state

Figure 2-23 Pin States in On-Chip HCAN Module Access

2.9.5 External Address Space Access Timing

The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or

three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to

section 7, Bus Controller.

2.10 Usage Note

2.10.1 TAS Instruction

Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS

instruction is not generated by the Hitachi H8S and H8/300 series C/C++ compilers. If the TAS

instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or

ER5 is used.

2.10.2 Caution to observe when using bit manipulation instructions

The BSET, BCLR, BNOT, BST and BIST instructions read data in a unit of byte, then, after bit

manipulation, they write data in a unit of byte. Therefore, caution must be exercised when

executing any of these instructions for registers and ports that include write-only bits.

The BCLR instruction can be used to clear the flag of an internal I/O register to 0. In that case, if it

is clearly known that the pertinent flag is set to 1 in an interrupt processing routine or other

processing, there is no need to read the flag in advance.

Section 3 MCU Operating Modes

3.1 Overview

3.1.1 Operating Mode Selection

The H8S/2646 Series has four operating modes (modes 4 to 7). These modes enable selection of

the CPU operating mode, enabling/disabling of on-chip ROM, and the initial bus width setting, by

setting the mode pins (MD2 to MD0).

Table 3-1 lists the MCU operating modes.

Table 3-1 MCU Operating Mode Selection

MCU CPU External Data Bus

Operating

Mode MD2 MD1 MD0 Operating

Mode Description On-Chip

ROM Initial

Width Max.

Width

0*000— — — — —

1*1—

2*10

3*1

4 1 0 0 Advanced On-chip ROM disabled, Disabled 16 bits 16 bits

expanded mode 8 bits 16 bits

6 1 0 On-chip ROM enabled,

expanded mode Enabled 8 bits 16 bits

7 1 Single-chip mode — —

Note: * Not available in the H8S/2646 Series.

The CPU’s architecture allows for 4 Gbytes of address space, but the H8S/2646 Series actually

accesses a maximum of 16 Mbytes.

Modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral

devices.

The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program

execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus

controller setting. If 16-bit access is selected for any one area, 16-bit bus mode is set; if 8-bit

access is selected for all areas, 8-bit bus mode is set.

Note that the functions of each pin depend on the operating mode.

The H8S/2646 Series can be used only in modes 4 to 7. This means that the mode pins must be set

to select one of these modes. Do not change the inputs at the mode pins during operation.

3.1.2 Register Configuration

The H8S/2646 Series has a mode control register (MDCR) that indicates the inputs at the mode

pins (MD2 to MD0), and a system control register (SYSCR) that controls the operation of the

H8S/2646 Series. Table 3-2 summarizes these registers.

Table 3-2 MCU Registers

Name Abbreviation R/W Initial Value Address*

Mode control register MDCR R Undetermined H'FDE7

System control register SYSCR R/W H'01 H'FDE5

Pin function control register PFCR R/W H'0D/H'00 H'FDEB

Note: * Lower 16 bits of the address.

3.2 Register Descriptions

3.2.1 Mode Control Register (MDCR)

—

MDS0

—*

MDS2

—*

MDS1

—*

Note: * Determined by pins MD2 to MD0.

Bit

Initial value

R/W

MDCR is an 8-bit read-only register that indicates the current operating mode of the H8S/2646

Series.

Bit 7—Reserved: Cannot be written to.

Bits 6 to 3—Reserved: These bits are always read as 0 and cannot be written to.

Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins

MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to MD2 to MD0.

MDS2 to MDS0 are read-only bits, and they cannot be written to. The mode pin (MD2 to MD0)

input levels are latched into these bits when MDCR is read. These latches are cancelled by a reset.

3.2.2 System Control Register (SYSCR)

MACS

R/W

—

INTM1

R/W

INTM0

R/W

NMIEG

R/W

RAME

R/W

—

R/W

—

Bit

Initial value

R/W

SYSCR is an 8-bit readable-writable register that selects saturating or non-saturating calculation

for the MAC instruction, selects the interrupt control mode, selects the detected edge for NMI, and

enables or disenables on-chip RAM.

SYSCR is initialized to H'01 by a reset and in hardware standby mode. SYSCR is not initialized in

software standby mode.

Bit 7—MAC Saturation (MACS): Selects either saturating or non-saturating calculation for the

MAC instruction.

Bit 7

MACS Description

0 Non-saturating calculation for MAC instruction (Initial value)

1 Saturating calculation for MAC instruction

Bit 6—Reserved: This bit is always read as 0 and cannot be modified.

Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control

mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1,

Interrupt Control Modes and Interrupt Operation.

Bit 5 Bit 4 Interrupt

INTM1 INTM0 Control Mode Description

0 0 0 Control of interrupts by I bit (Initial value)

1—Setting prohibited

1 0 2 Control of interrupts by I2 to I0 bits and IPR

1—Setting prohibited

Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input.

Bit 3

NMIEG Description

0 An interrupt is requested at the falling edge of NMI input (Initial value)

1 An interrupt is requested at the rising edge of NMI input

Bit 2— Reserved: Only 0 should be written to this bit.

Bit 1—Reserved: This bit is always read as 0 and cannot be modified.

Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is

initialized when the reset status is released. It is not initialized in software standby mode.

Bit 0

RAME Description

0 On-chip RAM is disabled

1 On-chip RAM is enabled (Initial value)

Note: When the DTC is used, the RAME bit must not be cleared to 0.

3.2.3 Pin Function Control Register (PFCR)

—

R/W

—

R/W

—

R/W

—

R/W

AE3

1/0

R/W

AE0

1/0

R/W

AE2

1/0

R/W

AE1

R/W

Bit

Initial value

R/W

PFCR is an 8-bit readable-writeable register that performs address output control in extension

modes involving ROM.

PFCR is initialized to H'0D/H'00 by a reset and in the hardware standby mode.

Bits 7 to 4— Reserved: Only 0 should be written to these bits.

Bits 3 to 0—Address Output Enable 3 to 0 (AE3–AE0): These bits select enabling or disabling

of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When a pin is

enabled for address output, the address is output regardless of the corresponding DDR setting.

When a pin is disabled for address output, it becomes an output port when the corresponding DDR

bit is set to 1.

Bit 3 Bit 2 Bit 1 Bit 0

AE3 AE2 AE1 AE0 Description

0000A8–A23 address output disabled (Initial value*)

1 A8 address output enabled; A9–A23 address output disabled

1 0 A8, A9 address output enabled; A10–A23 address output

disabled

1A8–A10 address output enabled; A11–A23 address output

disabled

100A8–A11 address output enabled; A12–A23 address output

disabled

1A8–A12 address output enabled; A13–A23 address output

disabled

10A8–A13 address output enabled; A14–A23 address output

disabled

1A8–A14 address output enabled; A15–A23 address output

disabled

1000A8–A15 address output enabled; A16–A23 address output

disabled

1A8–A16 address output enabled; A17–A23 address output

disabled

10A8–A17 address output enabled; A18–A23 address output

disabled

1A8–A18 address output enabled; A19–A23 address output

disabled

100A8–A19 address output enabled; A20–A23 address output

disabled

1A8–A20 address output enabled; A21–A23 address output

disabled (Initial value*)

10A8–A21 address output enabled; A22, A23 address output

disabled

1A8–A23 address output enabled

Note: *In expanded mode with ROM, bits AE3 to AE0 are initialized to B'0000.

In ROMless expanded mode, bits AE3 to AE0 are initialized to B'1101.

Address pins A0 to A7 are made address outputs by setting the corresponding DDR bits to

3.3 Operating Mode Descriptions

3.3.1 Mode 4

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.

Ports A, B, and C, function as an address bus, ports D and E function as a data bus, and part of

port F carries bus control signals.

The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if 8-

bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits.

3.3.2 Mode 5

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.

Ports A, B, and C, function as an address bus, ports D and E function as a data bus, and part of

port F carries bus control signals.

The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16-

bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and

port E becomes a data bus.

3.3.3 Mode 6

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.

Ports A, B, and C, function as input port pins immediately after a reset. Address output can be

performed by setting the corresponding DDR (data direction register) bits to 1.

Port D functions as a data bus, and part of port F carries bus control signals.

The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16-

bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and

port E becomes a data bus.

3.3.4 Mode 7

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled,

but external addresses cannot be accessed.

All I/O ports are available for use as input-output ports.

3.4 Pin Functions in Each Operating Mode

The pin functions of ports A to F vary depending on the operating mode. Table 3-3 shows their

functions in each operating mode.

Table 3-3 Pin Functions in Each Mode

Port Mode 4 Mode 5 Mode 6 Mode 7

Port A A A P*/A P

Port B A A P*/A P

Port C A A P*/A P

Port D DDDP

Port E P/D*P*/D P*/D P

Port F PF7 P/C*P/C*P/C*P*/C

PF6 to PF4 CCCP

PF3 P/C*P*/C P*/C

PF2 P*/C P*/C P*/C

Legend

P: I/O port

A: Address bus output

D: Data bus I/O

C: Control signals, clock I/O

*: After reset

3.5 Address Map in Each Operating Mode

A address maps of the H8S/2646 Series are shown in figures 3-1 (1) and 3-1 (2).

The address space is 16 Mbytes in modes 4 to 7 (advanced modes).

The address space is divided into eight areas for modes 4 to 7. For details, see section 7, Bus

Controller.

H'000000

H'FFB000

H'FFAFFF

H'FFEFC0

H'FFF800

H'020000

H'01FFFF

H'000000

H'01FFFF

H'000000

H'FFEFBF

External address

space

On-chip RAM*

Reserved area

On-chip RAM*

External address

space

Internal I/O registers

On-chip RAM*

Internal I/O registers

On-chip ROM

External address

space

On-chip ROM

On-chip RAM

Internal I/O registers

Note:

H'FFFFFF

H'FFFF40

H'FFFF60

H'FFFFC0

H'FFE000

H'FFDFFF

H'FFE000

H'FFDFFF

H'FFB000

H'FFAFFF

H'FFE000

H'FFEFC0

H'FFF800

H'FFFF40

H'FFFF60

H'FFFFC0

H'FFFF60

H'FFFFC0

On-chip RAM*

Reserved area

On-chip RAM

External address

space

External address

space External address

space

Internal I/O registers

H'FFFFFF H'FFFFFF

H'FFF800

H'FFFF3F

* External addresses can be accessed by clearing th RAME bit in SYSCR to 0.

Modes 4 and 5

(advanced expanded modes

with on-chip ROM disabled)

Mode 6

(advanced expanded mode

with on-chip ROM enabled)

Mode 7

(advanced single-chip mode)

Figure 3-1 (1) Address Map in Each Operating Mode in the H8S/2646, H8S/2646R,

H8S/2648, and H8S/2648R

H'000000

H'FFB000

H'FFAFFF

H'FFEFC0

H'FFF800

H'020000

H'01FFFF

H'00FFFF

H'010000

H'000000

H'01FFFF

H'000000

H'FFEFBF

External address

space

On-chip RAM*

Reserved area

On-chip RAM*

External address

space

Internal I/O registers

On-chip RAM*

Internal I/O registers

On-chip ROM

External address

space

On-chip ROM

Reserved area Reserved area

On-chip RAM

Internal I/O registers

Note:

H'FFFFFF

H'FFFF40

H'FFFF60

H'FFFFC0

H'FFE800

H'FFE7FF

H'00FFFF

H'010000

H'FFE800

H'FFE7FF

H'FFB000

H'FFAFFF

H'FFE000

H'FFEFC0

H'FFF800

H'FFFF40

H'FFFF60

H'FFFFC0

H'FFFF60

H'FFFFC0

On-chip RAM*

Reserved area

On-chip RAM

External address

space

External address

space External address

space

Internal I/O registers

H'FFFFFF H'FFFFFF

H'FFF800

H'FFFF3F

* External addresses can be accessed by clearing th RAME bit in SYSCR to 0.

Modes 4 and 5

(advanced expanded modes

with on-chip ROM disabled)

Mode 6

(advanced expanded mode

with on-chip ROM enabled)

Mode 7

(advanced single-chip mode)

Figure 3-1 (2) Address Map in Each Operating Mode in the H8S/2645 and H8S/2647

Section 4 Exception Handling

4.1 Overview

4.1.1 Exception Handling Types and Priority

As table 4-1 indicates, exception handling may be caused by a reset, direct transition, trap

instruction, or interrupt. Exception handling is prioritized as shown in table 4-1. If two or more

exceptions occur simultaneously, they are accepted and processed in order of priority. Trap

instruction exceptions are accepted at all times, in the program execution state.

Exception handling sources, the stack structure, and the operation of the CPU vary depending on

the interrupt control mode set by the INTM0 and INTM1 bits of SYSCR.

Table 4-1 Exception Types and Priority

Priority Exception Type Start of Exception Handling

High Reset Starts immediately after a low-to-high transition at the RES

pin, or when the watchdog overflows. The CPU enters the

reset state when the RES pin is low.

Trace*1Starts when execution of the current instruction or exception

handling ends, if the trace (T) bit is set to 1

Direct transition Starts when a direct transition occurs due to execution of a

SLEEP instruction.

Interrupt Starts when execution of the current instruction or exception

handling ends, if an interrupt request has been issued*2

Low Trap instruction (TRAPA)*3Started by execution of a trap instruction (TRAPA)

Notes: *1 Traces are enabled only in interrupt control mode 2. Trace exception handling is not

executed after execution of an RTE instruction.

*2 Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC

instruction execution, or on completion of reset exception handling.

*3 Trap instruction exception handling requests are accepted at all times in program

execution state.

4.1.2 Exception Handling Operation

Exceptions originate from various sources. Trap instructions and interrupts are handled as follows:

1. The program counter (PC), condition code register (CCR), and extended register (EXR) are

pushed onto the stack.

2. The interrupt mask bits are updated. The T bit is cleared to 0.

3. A vector address corresponding to the exception source is generated, and program execution

starts from that address.

For a reset exception, steps 2 and 3 above are carried out.

4.1.3 Exception Vector Table

The exception sources are classified as shown in figure 4-1. Different vector addresses are

assigned to different exception sources.

Table 4-2 lists the exception sources and their vector addresses.

xception

ources

Reset

Trace

Interrupts

Trap instruction

External interrupts: NMI, IRQ5 to IRQ0

Internal interrupts: Interrupts from on-chip supporting modules

43 sources in the H8S/2646, H8S/2646R,

and H8S/2645

47 sources in the H8S/2648, H8S/2648R,

and H8S/2647

Figure 4-1 Exception Sources

Table 4-2 Exception Vector Table

Vector Address*1

Exception Source Vector Number Advanced Mode

Reset 0 H'0000 to H'0003

Reserved for system use 1 H'0004 to H'0007

2 H'0008 to H'000B

3 H'000C to H'000F

4 H'0010 to H'0013

Trace 5 H'0014 to H'0017

Direct Transition*36 H'0018 to H'001B

External interrupt NMI 7 H'001C to H'001F

Trap instruction (4 sources) 8 H'0020 to H'0023

9 H'0024 to H'0027

10 H'0028 to H'002B

11 H'002C to H'002F

Reserved for system use 12 H'0030 to H'0033

13 H'0034 to H'0037

14 H'0038 to H'003B

15 H'003C to H'003F

External interrupt IRQ0 16 H'0040 to H'0043

IRQ1 17 H'0044 to H'0047

IRQ2 18 H'0048 to H'004B

IRQ3 19 H'004C to H'004F

IRQ4 20 H'0050 to H'0053

IRQ5 21 H'0054 to H'0057

Reserved for system use 22 H'0058 to H'005B

23 H'005C to H'005F

Internal interrupt*224



127

H'0060 to H'0063



H'01FC to H'01FF

Notes: *1 Lower 16 bits of the address.

*2 For details of internal interrupt vectors, see section 5.3.3, Interrupt Exception Handling

Vector Table.

*3 See section 22.11, Direct Transitions for details on direct transition.

4.2 Reset

4.2.1 Overview

A reset has the highest exception priority.

When the RES pin goes low, all current operations are stopped, and this LSI enters reset state. A

reset initializes the internal state of the CPU and the registers of on-chip supporting modules.

Immediately after a reset, interrupt control mode 0 is set.

When the RES pin goes from low to high, reset exception handling starts.

The H8S/2646 Series can also be reset by overflow of the watchdog timer. For details see section

12, Watchdog Timer.

4.2.2 Reset Sequence

This LSI enters reset state when the RES pin goes low.

To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at power-up. To reset

during operation, hold the RES pin low for at least 20 states.

When the RES pin goes high after being held low for the necessary time, this LSI starts reset

exception handling as follows.

1. The internal state of the CPU and the registers of the on-chip supporting modules are

initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR.

2. The reset exception handling vector address is read and transferred to the PC, and program

execution starts from the address indicated by the PC.

Figures 4-2 and 4-3 show examples of the reset sequence.

RES

Internal

address bus

Internal read

signal

Internal write

signal

Internal data

bus

Vector

fetch

(1) (3) (5)

High

Internal

processing Prefetch of first program

instruction

(2) (4)

(1) (3) Reset exception handling vector address (when reset, (1) = H'000000,

(3) = H'000002)

(2) (4) Start address (contents of reset exception handling vector address)

(5) Start address ((5) = (2) (4))

(6) First program instruction

(6)

Figure 4-2 Reset Sequence (Modes 6 and 7)

RES

Address bus

HWR, LWR

D15 to D0

(1) (3)

High

(2) (4)

(5)

(6)

* * *

Vector

fetch Internal

processing Prefetch of first program

instruction

(1) (3) Reset exception handling vector address (when reset, (1) = H'000000,

(3) = H'000002)

(2) (4) Start address (contents of reset exception handling vector address)

(5) Start address ((5) = (2) (4))

(6) First program instruction

Note: * 3 program wait states are inserted.

Figure 4-3 Reset Sequence (Mode 4)

4.2.3 Interrupts after Reset

If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and

CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,

including NMI, are disabled immediately after a reset. Since the first instruction of a program is

always executed immediately after the reset state ends, make sure that this instruction initializes

the stack pointer (example: MOV.L #xx: 32, SP).

4.2.4 State of On-Chip Supporting Modules after Reset Release

After reset release, MSTPCRA to MSTPCRD are initialized to H'3F, H'FF, H'FF, and

B'11*******1, respectively, and all modules except the DTC, enter module stop mode.

Consequently, on-chip supporting module registers cannot be read or written to. Register reading

and writing is enabled when module stop mode is exited.

Note: *1 The value of bits 5 to 0 is undefined.

4.3 Traces

Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control

mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5,

Interrupt Controller.

If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on

completion of each instruction.

Trace mode is canceled by clearing the T bit in EXR to 0. It is not affected by interrupt masking.

Table 4-3 shows the state of CCR and EXR after execution of trace exception handling.

Interrupts are accepted even within the trace exception handling routine.

The T bit saved on the stack retains its value of 1, and when control is returned from the trace

exception handling routine by the RTE instruction, trace mode resumes.

Trace exception handling is not carried out after execution of the RTE instruction.

Table 4-3 Status of CCR and EXR after Trace Exception Handling

CCR EXR

Interrupt Control Mode I UI I2 to I0 T

0** **

21——0

Legend

1: Set to 1

0: Cleared to 0

—: Retains value prior to execution.

*: Trace exception handling cannot be used.

4.4 Interrupts

Interrupt exception handling can be requested by seven external sources (NMI, IRQ5 to IRQ0) and

internal sources (43 sources in the H8S/2646, H8S/2646R, and H8S/2645, and 47 sources in the

H8S/2648, H8S/2648R, and H8S/2647) in the on-chip supporting modules. Figure 4-4 classifies

the interrupt sources and the number of interrupts of each type.

The on-chip supporting modules that can request interrupts include the watchdog timer (WDT),

16-bit timer pulse unit (TPU), serial communication interface (SCI), data transfer controller

(DTC), PC break controller (PBC), A/D converter, Hitachi controller area network (HCAN), and

motor control PWM timer. Each interrupt source has a separate vector address.

NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The

interrupt controller has two interrupt control modes and can assign interrupts other than NMI to

eight priority/mask levels to enable multiplexed interrupt control.

For details of interrupts, see section 5, Interrupt Controller.

Interrupts

External

interrupts

Internal

interrupts

NMI (1)

IRQ5 to IRQ0 (6)

WDT* (2)

TPU (26)

SCI (8): H8S/2646, H8S/2646R, H8S/2645

SCI (12): H8S/2648, H8S/2648R, H8S/2647

DTC (1)

PBC (1)

A/D converter (1)

PWM (2)

HCAN (2)

Notes: Numbers in parentheses are the numbers of interrupt sources.

*When the watchdog timer is used as an interval timer, it generates an interrupt request

at each counter overflow.

Figure 4-4 Interrupt Sources and Number of Interrupts

4.5 Trap Instruction

Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction

exception handling can be executed at all times in the program execution state.

The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector

number from 0 to 3, as specified in the instruction code.

Table 4-4 shows the status of CCR and EXR after execution of trap instruction exception

handling.

Table 4-4 Status of CCR and EXR after Trap Instruction Exception Handling

CCR EXR

Interrupt Control Mode I UI I2 to I0 T

01———

21——0

Legend

1: Set to 1

0: Cleared to 0

—: Retains value prior to execution.

4.6 Stack Status after Exception Handling

Figure 4-5 shows the stack after completion of trap instruction exception handling and interrupt

exception handling.

SP CCR

CCR*

(16 bits)

CCR

CCR*

(16 bits)

Reserved*

EXR

(a) Interrupt control mode 0 (b) Interrupt control mode 2

Note: * Ignored on return.

Figure 4-5 (1) Stack Status after Exception Handling (Normal Modes: Not Available in the

H8S/2646 Series)

SP CCR

(24 bits)

CCR

(24 bits)

Reserved*

EXR

(a) Interrupt control mode 0 (b) Interrupt control mode 2

Note: * Ignored on return.

Figure 4-5 (2) Stack Status after Exception Handling (Advanced Modes)

4.7 Notes on Use of the Stack

When accessing word data or longword data, the H8S/2646 Series assumes that the lowest address

bit is 0. The stack should always be accessed by word transfer instruction or longword transfer

instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the

following instructions to save registers:

PUSH.W Rn (or MOV.W Rn, @-SP)

PUSH.L ERn (or MOV.L ERn, @-SP)

Use the following instructions to restore registers:

POP.W Rn (or MOV.W @SP+, Rn)

POP.L ERn (or MOV.L @SP+, ERn)

Setting SP to an odd value may lead to a malfunction. Figure 4-6 shows an example of what

happens when the SP value is odd.

Legend

Note: This diagram illustrates an example in which the interrupt control mode

is 0, in advanced mode.

CCR

R1L

H'FFFEFA

H'FFFEFB

H'FFFEFC

H'FFFEFD

H'FFFEFF

MOV.B R1L, @–ER7

SP set to H'FFFEFF

TRAPA instruction executed

Data saved above SP Contents of CCR lost

CCR: Condition code register

PC: Program counter

R1L: General register R1L

SP: Stack pointer

Figure 4-6 Operation when SP Value is Odd

100

101

Section 5 Interrupt Controller

5.1 Overview

5.1.1 Features

The H8S/2646 Series controls interrupts by means of an interrupt controller. The interrupt

controller has the following features:

• Two interrupt control modes

 Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in

the system control register (SYSCR).

• Priorities settable with IPR

 An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority

levels can be set for each module for all interrupts except NMI.

 NMI is assigned the highest priority level of 8, and can be accepted at all times.

• Independent vector addresses

 All interrupt sources are assigned independent vector addresses, making it unnecessary for

the source to be identified in the interrupt handling routine.

• Seven external interrupts

 NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling

edge can be selected for NMI.

 Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ5

to IRQ0.

• DTC control

 DTC activation is performed by means of interrupts.

102

5.1.2 Block Diagram

A block diagram of the interrupt controller is shown in Figure 5-1.

SYSCR

NMI input

IRQ input

Internal interrupt

request

SWDTEND to

RM0

INTM1 INTM0

NMIEG

NMI input unit

IRQ input unit

ISR

ISCR IER

IPR

Interrupt controller

Priority

determination

Interrupt

request

Vector

number

I2 to I0 CCR

EXR

CPU

ISCR

IER

ISR

IPR

SYSCR

: IRQ sense control register

: IRQ enable register

: IRQ status register

: Interrupt priority register

: System control register

Legend

Figure 5-1 Block Diagram of Interrupt Controller

103

5.1.3 Pin Configuration

Table 5-1 summarizes the pins of the interrupt controller.

Table 5-1 Interrupt Controller Pins

Name Symbol I/O Function

Nonmaskable interrupt NMI Input Nonmaskable external interrupt; rising or

falling edge can be selected

External interrupt

requests 5 to 0 IRQ5 to IRQ0 Input Maskable external interrupts; rising, falling, or

both edges, or level sensing, can be selected

5.1.4 Register Configuration

Table 5-2 summarizes the registers of the interrupt controller.

Table 5-2 Interrupt Controller Registers

Name Abbreviation R/W Initial Value Address*1

System control register SYSCR R/W H'01 H'FDE5

IRQ sense control register H ISCRH R/W H'00 H'FE12

IRQ sense control register L ISCRL R/W H'00 H'FE13

IRQ enable register IER R/W H'00 H'FE14

IRQ status register ISR R/(W)*2H'00 H'FE15

Interrupt priority register A IPRA R/W H'77 H'FEC0

Interrupt priority register B IPRB R/W H'77 H'FEC1

Interrupt priority register C IPRC R/W H'77 H'FEC2

Interrupt priority register D IPRD R/W H'77 H'FEC3

Interrupt priority register E IPRE R/W H'77 H'FEC4

Interrupt priority register F IPRF R/W H'77 H'FEC5

Interrupt priority register G IPRG R/W H'77 H'FEC6

Interrupt priority register H IPRH R/W H'77 H'FEC7

Interrupt priority register J IPRJ R/W H'77 H'FEC9

Interrupt priority register K IPRK R/W H'77 H'FECA

Interrupt priority register M IPRM R/W H'77 H'FECC

Notes: *1 Lower 16 bits of the address.

*2 Can only be written with 0 for flag clearing.

104

5.2 Register Descriptions

5.2.1 System Control Register (SYSCR)

MACS

R/W

—

INTM1

R/W

INTM0

R/W

NMIEG

R/W

RAME

R/W

—

R/W

—

Bit

Initial value

R/W

SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the

detected edge for NMI.

Only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, System Control

SYSCR is initialized to H'01 by a reset and in hardware standby mode. SYSCR is not initialized in

software standby mode.

Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two

interrupt control modes for the interrupt controller.

Bit 5 Bit 4 Interrupt

INTM1 INTM0 Control Mode Description

0 0 0 Interrupts are controlled by I bit (Initial value)

1 — Setting prohibited

1 0 2 Interrupts are controlled by bits I2 to I0, and IPR

1 — Setting prohibited

Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin.

Bit 3

NMIEG Description

0 Interrupt request generated at falling edge of NMI input (Initial value)

1 Interrupt request generated at rising edge of NMI input

105

5.2.2 Interrupt Priority Registers A to H, J, K, M (IPRA to IPRH, IPRJ, IPRK, IPRM)

—

IPR6

R/W

IPR5

R/W

IPR4

R/W

—

IPR0

R/W

IPR2

R/W

IPR1

R/W

Bit

Initial value

R/W

The IPR registers are eleven 8-bit readable/writable registers that set priorities (levels 7 to 0) for

interrupts other than NMI.

The correspondence between IPR settings and interrupt sources is shown in table 5-3.

The IPR registers set a priority (level 7 to 0) for each interrupt source other than NMI.

The IPR registers are initialized to H'77 by a reset and in hardware standby mode.

Bits 7 and 3—Reserved: These bits are always read as 0 and cannot be modified.

Table 5-3 Correspondence between Interrupt Sources and IPR Settings

Bits

IPRA IRQ0 IRQ1

IPRB IRQ2 IRQ4

IRQ3 IRQ5

IPRC —*1DTC

IPRD Watchdog timer 0 —*1

IPRE PC break A/D converter, Watchdog timer 1

IPRF TPU channel 0 TPU channel 1

IPRG TPU channel 2 TPU channel 3

IPRH TPU channel 4 TPU channel 5

IPRJ —*1SCI channel 0

IPRK SCI channel 1 SCI channel 2 (H8S/2648R)*2

IPRM PWM channel 1, 2 HCAN

Notes: *1 Reserved. These bits are always read as 1 and cannot be modified.

*2 In the H8S/2646, H8S/2646R, and H8S/2645 these are reserved bits that are always

read as 1 and should only be written with H'7. In the H8S/2648, H8S/2648R, and

H8S/2647 these are the IPR bits for SCI channel 2.

106

As shown in table 5-3, multiple interrupts are assigned to one IPR. Setting a value in the range

from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding

interrupt. The lowest priority level, level 0, is assigned by setting H'0, and the highest priority

level, level 7, by setting H'7.

When interrupt requests are generated, the highest-priority interrupt according to the priority

levels set in the IPR registers is selected. This interrupt level is then compared with the interrupt

mask level set by the interrupt mask bits (I2 to I0) in the extend register (EXR) in the CPU, and if

the priority level of the interrupt is higher than the set mask level, an interrupt request is issued to

the CPU.

5.2.3 IRQ Enable Register (IER)

—

R/W

—

R/W

IRQ5E

R/W

IRQ4E

R/W

IRQ3E

R/W

IRQ0E

R/W

IRQ2E

R/W

IRQ1E

R/W

Bit

Initial value

R/W

IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests

IRQ5 to IRQ0.

IER is initialized to H'00 by a reset and in hardware standby mode.

Bits 7 and 6—Reserved: These bits are always read as 0, and should only be written with 0.

Bits 5 to 0—IRQ5 to IRQ0 Enable (IRQ5E to IRQ0E): These bits select whether IRQ5 to

IRQ0 are enabled or disabled.

Bit n

IRQnE Description

0 IRQn interrupts disabled (Initial value)

1 IRQn interrupts enabled

(n = 5 to 0)

107

5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)

ISCRH

—

R/W

—

R/W

—

R/W

—

R/W

IRQ5SCB

R/W

IRQ4SCA

R/W

IRQ5SCA

R/W

IRQ4SCB

R/W

Bit

Initial value

R/W

ISCRL

IRQ3SCB

R/W

IRQ3SCA

R/W

IRQ2SCB

R/W

IRQ2SCA

R/W

IRQ1SCB

R/W

IRQ0SCA

R/W

IRQ1SCA

R/W

IRQ0SCB

R/W

Bit

Initial value

R/W

The ISCR registers are 16-bit readable/writable registers that select rising edge, falling edge, or

both edge detection, or level sensing, for the input at pins IRQ5 to IRQ0.

The ISCR registers are initialized to H'0000 by a reset and in hardware standby mode.

Bits 15 to 12—Reserved: These bits are always read as 0, and should only be written with 0.

Bits 11 to 0: IRQ5 Sense Control A and B (IRQ5SCA, IRQ5SCB) to IRQ0 Sense Control A and

B (IRQ0SCA, IRQ0SCB)

Bits 11 to 0

IRQ5SCB to

IRQ0SCB IRQ5SCA to

IRQ0SCA Description

0 0 Interrupt request generated at IRQ5 to IRQ0 input low level

(initial value)

1 Interrupt request generated at falling edge of IRQ5 to IRQ0 input

1 0 Interrupt request generated at rising edge of IRQ5 to IRQ0 input

1 Interrupt request generated at both falling and rising edges of

IRQ5 to IRQ0 input

108

5.2.5 IRQ Status Register (ISR)

—

R/(W)*

—

R/(W)*

IRQ5F

R/(W)*

IRQ4F

R/(W)*

IRQ3F

R/(W)*

IRQ0F

R/(W)*

IRQ2F

R/(W)*

IRQ1F

R/(W)*

Bit

Initial value

R/W

Note: * Only 0 can be written, to clear the flag.

ISR is an 8-bit readable/writable register that indicates the status of IRQ5 to IRQ0 interrupt

requests.

ISR is initialized to H'00 by a reset and in hardware standby mode.

They are not initialized in software standby mode.

Bits 7 and 6—Reserved: These bits are always read as 0.

Bits 5 to 0—IRQ5 to IRQ0 flags (IRQ5F to IRQ0F): These bits indicate the status of IRQ5 to

IRQ0 interrupt requests.

Bit n

IRQnF Description

0 [Clearing conditions] (Initial value)

• Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag

• When interrupt exception handling is executed when low-level detection is set

(IRQnSCB = IRQnSCA = 0) and IRQn input is high

• When IRQn interrupt exception handling is executed when falling, rising, or both-edge

detection is set (IRQnSCB = 1 or IRQnSCA = 1)

• When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the

DTC is cleared to 0

1 [Setting conditions]

• When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA =

• When a falling edge occurs in IRQn input when falling edge detection is set

(IRQnSCB = 0, IRQnSCA = 1)

• When a rising edge occurs in IRQn input when rising edge detection is set

(IRQnSCB = 1, IRQnSCA = 0)

• When a falling or rising edge occurs in IRQn input when both-edge detection is set

(IRQnSCB = IRQnSCA = 1) (n = 5 to 0)

109

5.3 Interrupt Sources

Interrupt sources comprise external interrupts (NMI and IRQ5 to IRQ0) and internal interrupts*.

Note: * 47 sources in the H8S/2648, H8S/2648R, and H8S/2647.

43 sources in the H8S/2646, H8S/2646R, and H8S/2645.

5.3.1 External Interrupts

There are seven external interrupts: NMI and IRQ5 to IRQ0. Of these, NMI and IRQ5 to IRQ0

can be used to restore the H8S/2646 Series from software standby mode.

NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU

regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG

bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling

edge on the NMI pin.

The vector number for NMI interrupt exception handling is 7.

IRQ5 to IRQ0 Interrupts: Interrupts IRQ5 to IRQ0 are requested by an input signal at pins IRQ5

to IRQ0. Interrupts IRQ5 to IRQ0 have the following features:

• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling

edge, rising edge, or both edges, at pins IRQ5 to IRQ0.

• Enabling or disabling of interrupt requests IRQ5 to IRQ0 can be selected with IER.

• The interrupt priority level can be set with IPR.

• The status of interrupt requests IRQ5 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0

by software.

A block diagram of interrupts IRQ5 to IRQ0 is shown in figure 5-2.

IRQn interrupt

request

IRQnE

IRQnF

Clear signal

Edge/level

detection circuit

IRQnSCA, IRQnSCB

IRQn input

Note: n = 5 to 0

Figure 5-2 Block Diagram of Interrupts IRQ5 to IRQ0

110

Figure 5-3 shows the timing of setting IRQnF.

IRQn

input pin

IRQnF

Figure 5-3 Timing of Setting IRQnF

The vector numbers for IRQ5 to IRQ0 interrupt exception handling are 21 to 16.

Detection of IRQ5 to IRQ0 interrupts does not depend on whether the relevant pin has been set for

input or output. However, when a pin is used as an external interrupt input pin, do not clear the

corresponding DDR to 0 and use the pin as an I/O pin for another function.

5.3.2 Internal Interrupts

There are 47 sources in the H8S/2648, H8S/2648R, and H8S/2647 and 43 sources in the

H8S/2646, H8S/2646R, and H8S/2645 for internal interrupts from on-chip supporting modules.

• For each on-chip supporting module there are flags that indicate the interrupt request status,

and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1

for a particular interrupt source, an interrupt request is issued to the interrupt controller.

• The interrupt priority level can be set by means of IPR.

• The DTC can be activated by a TPU, SCI, or other interrupt request. When the DTC is

activated by an interrupt, the interrupt control mode and interrupt mask bits are not affected.

5.3.3 Interrupt Exception Handling Vector Table

Table 5-4 shows interrupt exception handling sources, vector addresses, and interrupt priorities.

For default priorities, the lower the vector number, the higher the priority.

Priorities among modules can be set by means of the IPR. The situation when two or more

modules are set to the same priority, and priorities within a module, are fixed as shown in

table 5-4.

111

Table 5-4 Interrupt Sources, Vector Addresses, and Interrupt Priorities

Origin of

Vector

Address*1

Interrupt Source Interrupt

Source Vector

Number Advanced

Mode IPR Priority

NMI External 7 H'001C High

IRQ0 pin 16 H'0040 IPRA6 to 4

IRQ1 17 H'0044 IPRA2 to 0

IRQ2

IRQ3 18

19 H'0048

H'004C IPRB6 to 4

IRQ4

IRQ5 20

21 H'0050

H'0054 IPRB2 to 0

Reserved for system use —22

23 H'0058

H'005C —

SWDTEND (software activation

interrupt end) DTC 24 H'0060 IPRC2 to 0

WOVI0 (interval timer) Watchdog

timer 0 25 H'0064 IPRD6 to 4

Reserved for system use —26 H'0068 —

PC break PC break

controller 27 H'006C IPRE6 to 4

ADI (A/D conversion end) A/D 28 H'0070 IPRE2 to 0

WOVI1 (interval timer) Watchdog

timer 1 29 H'0074

Reserved for system use —30

31 H'0078

H'007C

TGI0A (TGR0A input

capture/compare match)

TGI0B (TGR0B input

capture/compare match)

TGI0C (TGR0C input

capture/compare match)

TGI0D (TGR0D input

capture/compare match)

TCI0V (overflow 0)

TPU

channel 0 32

H'0080

H'0084

H'0088

H'008C

H'0090

IPRF6 to 4

Reserved for system use —37

H'0094

H'009C Low

112

Origin of

Vector

Address*1

Interrupt Source Interrupt

Source Vector

Number Advanced

Mode IPR Priority

TGI1A (TGR1A input

capture/compare match)

TGI1B (TGR1B input

capture/compare match)

TCI1V (overflow 1)

TCI1U (underflow 1)

TPU

channel 1 40

H'00A0

H'00A4

H'00A8

H'00AC

IPRF2 to 0 High

TGI2A (TGR2A input

capture/compare match)

TGI2B (TGR2B input

capture/compare match)

TCI2V (overflow 2)

TCI2U (underflow 2)

TPU

channel 2 44

H'00B0

H'00B4

H'00B8

H'00BC

IPRG6 to 4

TGI3A (TGR3A input

capture/compare match)

TGI3B (TGR3B input

capture/compare match)

TGI3C (TGR3C input

capture/compare match)

TGI3D (TGR3D input

capture/compare match)

TCI3V (overflow 3)

TPU

channel 3 48

H'00C0

H'00C4

H'00C8

H'00CC

H'00D0

IPRG2 to 0

Reserved for system use —53

H'00D4

H'00DC

TGI4A (TGR4A input

capture/compare match)

TGI4B (TGR4B input

capture/compare match)

TCI4V (overflow 4)

TCI4U (underflow 4)

TPU

channel 4 56

H'00E0

H'00E4

H'00E8

H'00EC

IPRH6 to 4

TGI5A (TGR5A input

capture/compare match)

TGI5B (TGR5B input

capture/compare match)

TCI5V (overflow 5)

TCI5U (underflow 5)

TPU

channel 5 60

H'00F0

H'00F4

H'00F8

H'00FC

IPRH2 to 0

Reserved for system use —64

H'0100

H'013C

—

Low

113

Origin of

Vector

Address*1

Interrupt Source Interrupt

Source Vector

Number Advanced

Mode IPR Priority

ERI0 (receive error 0)

RXI0 (reception completed 0)

TXI0 (transmit data empty 0)

TEI0 (transmission end 0)

SCI

channel 0 80

H'0140

H'0144

H'0148

H'014C

IPRJ2 to 0 High

ERI1 (receive error 1)

RXI1 (reception completed 1)

TXI1 (transmit data empty 1)

TEI1 (transmission end 1)

SCI

channel 1 84

H'0150

H'0154

H'0158

H'015C

IPRK6 to 4

ERI2 (receive error 2)

RXI2 (reception completed 2)

TXI2 (transmit data empty 2)

TEI2 (transmission end 2)

SCI

channel 2*288

H'0160

H'0164

H'0168

H'016C

IPRK2 to 0

Reserved for system use —92

103

H'0170

H'019C

—

CMI1 (PWCYR1 compare match)

CMI2 (PWCYR2 compare match) PWM 104

105 H'01A0

H'01A4 IPRM6 to 4

Reserved for system use —106

107 H'01A8

H'01AC

ERS0, OVR0, RM1, SLE0,

RM0 (mailbox 0 reception) HCAN 108

109 H'01B0

H'01B4 IPRM2 to 0

Reserved for system use —110

111 H'01B8

H'01BC

Reserved for system use —112

123

H'01C0

H'01FC

—

Low

Notes: *1 Lower 16 bits of the start address.

*2 These vectors are used in the H8S/2648, H8S/2648R, and H8S/2647. They are

reserved in the H8S/2646, H8S/2646R, and H8S/2645.

114

5.4 Interrupt Operation

5.4.1 Interrupt Control Modes and Interrupt Operation

Interrupt operations in the H8S/2646 Series differ depending on the interrupt control mode.

NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In

the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for

each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt

sources for which the enable bits are set to 1 are controlled by the interrupt controller.

Table 5-5 shows the interrupt control modes.

The interrupt controller performs interrupt control according to the interrupt control mode set by

the INTM1 and INTM0 bits in SYSCR, the priorities set in IPR, and the masking state indicated

by the I bit in the CPU’s CCR, and bits I2 to I0 in EXR.

Table 5-5 Interrupt Control Modes

Interrupt SYSCR Priority Setting Interrupt

Control Mode INTM1 INTM0 Registers Mask Bits Description

0 00—I Interrupt mask control is

performed by the I bit.

—1——Setting prohibited

2 1 0 IPR I2 to I0 8-level interrupt mask control

is performed by bits I2 to I0.

8 priority levels can be set with

IPR.

—1——Setting prohibited

115

Figure 5-4 shows a block diagram of the priority decision circuit.

Interrupt

acceptance

control

8-level

mask control

Default priority

determination Vector number

Interrupt control mode 2

IPR

Interrupt source

I2 to I0

Interrupt

control

mode 0 I

Figure 5-4 Block Diagram of Interrupt Control Operation

Interrupt Acceptance Control: In interrupt control mode 0, interrupt acceptance is controlled by

the I bit in CCR.

Table 5-6 shows the interrupts selected in each interrupt control mode.

Table 5-6 Interrupts Selected in Each Interrupt Control Mode (1)

Interrupt Mask Bits

Interrupt Control Mode I Selected Interrupts

0 0 All interrupts

1 NMI interrupts

2*All interrupts

Legend

* : Don't care

116

8-Level Control: In interrupt control mode 2, 8-level mask level determination is performed for

the selected interrupts in interrupt acceptance control according to the interrupt priority level

(IPR).

The interrupt source selected is the interrupt with the highest priority level, and whose priority

level set in IPR is higher than the mask level.

Table 5-7 Interrupts Selected in Each Interrupt Control Mode (2)

Interrupt Control Mode Selected Interrupts

0 All interrupts

2 Highest-priority-level (IPR) interrupt whose priority level is greater

than the mask level (IPR > I2 to I0).

Default Priority Determination: When an interrupt is selected by 8-level control, its priority is

determined and a vector number is generated.

If the same value is set for IPR, acceptance of multiple interrupts is enabled, and so only the

interrupt source with the highest priority according to the preset default priorities is selected and

has a vector number generated.

Interrupt sources with a lower priority than the accepted interrupt source are held pending.

Table 5-8 shows operations and control signal functions in each interrupt control mode.

Table 5-8 Operations and Control Signal Functions in Each Interrupt Control Mode

Interrupt

Control Setting Interrupt Acceptance

Control 8-Level Control Default Priority T

Mode INTM1 INTM0 I I2 to I0 IPR Determination (Trace)

000 IM X ——

*2—

210X —*1IM PR T

Legend

: Interrupt operation control performed

X : No operation. (All interrupts enabled)

IM : Used as interrupt mask bit

PR : Sets priority.

—: Not used.

Notes: *1 Set to 1 when interrupt is accepted.

*2 Keep the initial setting.

117

5.4.2 Interrupt Control Mode 0

Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by

means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, and

disabled when set to 1.

Figure 5-5 shows a flowchart of the interrupt acceptance operation in this case.

[1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt

request is sent to the interrupt controller.

[2] The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I

bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending.

[3] Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to

the priority system is accepted, and other interrupt requests are held pending.

[4] When an interrupt request is accepted, interrupt exception handling starts after execution of the

current instruction has been completed.

[5] The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on

the stack shows the address of the first instruction to be executed after returning from the

interrupt handling routine.

[6] Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.

[7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling

routine starts at the address indicated by the contents of that vector address.

118

Program execution status

Interrupt generated?

NMI

IRQ0

IRQ1

HCAN

I=0

Save PC and CCR

I←1

Read vector address

Branch to interrupt handling routine

Yes

Yes No

Yes

Hold pending

Figure 5-5 Flowchart of Procedure Up to Interrupt Acceptance in

Interrupt Control Mode 0

119

5.4.3 Interrupt Control Mode 2

Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts

by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR.

Figure 5-6 shows a flowchart of the interrupt acceptance operation in this case.

[1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt

request is sent to the interrupt controller.

[2] When interrupt requests are sent to the interrupt controller, the interrupt with the highest

priority according to the interrupt priority levels set in IPR is selected, and lower-priority

interrupt requests are held pending. If a number of interrupt requests with the same priority are

generated at the same time, the interrupt request with the highest priority according to the

priority system shown in table 5-4 is selected.

[3] Next, the priority of the selected interrupt request is compared with the interrupt mask level set

in EXR. An interrupt request with a priority no higher than the mask level set at that time is

held pending, and only an interrupt request with a priority higher than the interrupt mask level

is accepted.

[4] When an interrupt request is accepted, interrupt exception handling starts after execution of the

current instruction has been completed.

[5] The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC

saved on the stack shows the address of the first instruction to be executed after returning from

the interrupt handling routine.

[6] The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of

the accepted interrupt.

If the accepted interrupt is NMI, the interrupt mask level is set to H'7.

[7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling

routine starts at the address indicated by the contents of that vector address.

120

Yes

Program execution status

Interrupt generated?

NMI

Level 6 interrupt?

Mask level 5

or below?

Level 7 interrupt?

Mask level 6

or below?

Save PC, CCR, and EXR

Clear T bit to 0

Update mask level

Read vector address

Branch to interrupt handling routine

Hold pending

Level 1 interrupt?

Mask level 0?

Yes

No Yes

Yes

Figure 5-6 Flowchart of Procedure Up to Interrupt Acceptance in

Interrupt Control Mode 2

121

5.4.4 Interrupt Exception Handling Sequence

Figure 5-7 shows the interrupt exception handling sequence. The example shown is for the case

where interrupt control mode 0 is set in advanced mode, and the program area and stack area are

in on-chip memory.

(14)(12)(10)(8)(6)(4)(2)

(1) (5) (7) (9) (11) (13)

Interrupt service

routine instruction

prefetch

Internal

operation

Vector fetchStack

Instruction

prefetch Internal

operation

Interrupt

acceptance

Interrupt level determination

Wait for end of instruction

Interrupt

request signal

Internal

address bus

Internal

read signal

Internal

write signal

Internal

data us

(3)

(1)

(2) (4)

(3)

(5)

(7)

Instruction prefetch address (Not executed.

This is the contents of the saved PC, the return address.)

Instruction code (Not executed.)

Instruction prefetch address (Not executed.)

SP-2

SP-4

Saved PC and saved CCR

Vector address

Interrupt handling routine start address (vector

address contents)

Interrupt handling routine start address ((13) = (10) (12))

First instruction of interrupt handling routine

(6) (8)

(9) (11)

(10) (12)

(13)

(14)

Figure 5-7 Interrupt Exception Handling

122

5.4.5 Interrupt Response Times

The H8S/2646 Series is capable of fast word transfer instruction to on-chip memory, and the

program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling high-

speed processing.

Table 5-9 shows interrupt response times - the interval between generation of an interrupt request

and execution of the first instruction in the interrupt handling routine. The execution status

symbols used in table 5-9 are explained in table 5-10.

Table 5-9 Interrupt Response Times

Normal Mode*5Advanced Mode

No. Execution Status INTM1 = 0 INTM1 = 1 INTM1 = 0 INTM1 = 1

1 Interrupt priority determination*133 33

2 Number of wait states until executing

instruction ends*21 to

(19+2·SI)1 to

(19+2·SI)

3 PC, CCR, EXR stack save 2·SK3·SK2·SK3·SK

4 Vector fetch SISI2·SI2·SI

5 Instruction fetch*32·SI2·SI2·SI2·SI

6 Internal processing*422 22

Total (using on-chip memory) 11 to 31 12 to 32 12 to 32 13 to 33

Notes: *1 Two states in case of internal interrupt.

*2 Refers to MULXS and DIVXS instructions.

*3 Prefetch after interrupt acceptance and interrupt handling routine prefetch.

*4 Internal processing after interrupt acceptance and internal processing after vector fetch.

*5 Not available in the H8S/2646 Series.

123

Table 5-10 Number of States in Interrupt Handling Routine Execution Statuses

Object of Access

External Device

8 Bit Bus 16 Bit Bus

Symbol Internal

Memory 2-State

Access 3-State

Access 2-State

Access 3-State

Access

Instruction fetch SI1 4 6+2m 2 3+m

Branch address read SJ

Stack manipulation SK

Legend

m: Number of wait states in an external device access.

5.5 Usage Notes

5.5.1 Contention between Interrupt Generation and Disabling

When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective

after execution of the instruction.

In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or

MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will

still be enabled on completion of the instruction, and so interrupt exception handling for that

interrupt will be executed on completion of the instruction. However, if there is an interrupt

request of higher priority than that interrupt, interrupt exception handling will be executed for the

higher-priority interrupt, and the lower-priority interrupt will be ignored.

The same also applies when an interrupt source flag is cleared to 0.

Figure 5-8 shows an example in which the TCIEV bit in the TPU’s TIER0 register is cleared to 0.

124

Internal

address bus

Internal

write signal

TCIEV

TCFV

TCIV

interrupt signal

TIER0 write cycle by CPU TCIV exception handling

TIER0 address

Figure 5-8 Contention between Interrupt Generation and Disabling

The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while

the interrupt is masked.

5.5.2 Instructions that Disable Interrupts

Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these

instructions is executed, all interrupts including NMI are disabled and the next instruction is

always executed. When the I bit is set by one of these instructions, the new value becomes valid

two states after execution of the instruction ends.

5.5.3 Times when Interrupts are Disabled

There are times when interrupt acceptance is disabled by the interrupt controller.

The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has

updated the mask level with an LDC, ANDC, ORC, or XORC instruction.

125

5.5.4 Interrupts during Execution of EEPMOV Instruction

Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.

With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer

is not accepted until the move is completed.

With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt

exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this

case is the address of the next instruction.

Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the

following coding should be used.

L1: EEPMOV.W

MOV.W R4,R4

BNE L1

5.5.5 IRQ Interrupts

When operating by clock input, acceptance of input to an IRQ pin is synchronized with the clock.

In software standby mode, the input is accepted asynchronously. For details on the input

conditions, see section 23.4.2, Control Signal Timing.

5.6 DTC Activation by Interrupt

5.6.1 Overview

The DTC can be activated by an interrupt. In this case, the following options are available:

• Interrupt request to CPU

• Activation request to DTC

• Selection of a number of the above

For details of interrupt requests that can be used with to activate the DTC, see section 8, Data

Transfer Controller (DTC).

5.6.2 Block Diagram

Figure 5-9 shows a block diagram of the DTC interrupt controller.

126

Selection

circuit

DTCER

DTVECR

Control logic

Determination of

priority CPU

DTC

Select

signal

IRQ

interrupt

On-chip

supporting

module

Clear signal

Interrupt controller I, I2 to I0

Interrupt source

clear signal

Interrupt

request DTC activation

request vector

number

CPU interrupt

request vector

number

SWDTE

clear signal

Clear signal

Figure 5-9 Interrupt Control for DTC

5.6.3 Operation

The interrupt controller has three main functions in DTC control.

Selection of Interrupt Source: Interrupt factors are selected as DTC activation request or CPU

interrupt request by the DTCE bit of DTCERA to DTCERG, and DTCERI of DTC.

By specifying the DISEL bit of the DTC’s MRB, it is possible to clear the DTCE bit to 0 after

DTC data transfer, and request a CPU interrupt.

If DTC carries out the designate number of data transfers and the transfer counter reads 0, after

DTC data transfer, the DTCE bit is also cleared to 0, and a CPU interrupt requested.

Determination of Priority: The DTC activation source is selected in accordance with the default

priority order, and is not affected by mask or priority levels. See section 8.3.3, DTC Vector Table

for the respective priority.

Operation Order: If the same interrupt is selected as a DTC activation source and a CPU

interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception

handling.

Table 5-11 shows the interrupt factor clear control and selection of interrupt factors by

specification of the DTCE bit of DTCERA to DTCERG, DTCERI of DTC, and the DISEL bit of

DTC’s MRB.

127

Table 5-11 Interrupt Source Selection and Clearing Control

Settings

DTC Interrupt Source Selection/Clearing Control

DTCE DISEL DTC CPU

0*X∆

10 ∆X

1∆

Legend

∆: The relevant interrupt is used. Interrupt source clearing is performed.

(The CPU should clear the source flag in the interrupt handling routine.)

: The relevant interrupt is used. The interrupt source is not cleared.

X : The relevant bit cannot be used.

*: Don’t care

Notes on Use: SCI and A/D converter interrupt sources are cleared when the DTC reads or writes

to the prescribed register.

128

129

Section 6 PC Break Controller (PBC)

6.1 Overview

The PC break controller (PBC) provides functions that simplify program debugging. Using these

functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with

the chip alone, without using an in-circuit emulator. Four break conditions can be set in the PBC:

instruction fetch, data read, data write, and data read/write.

6.1.1 Features

The PC break controller has the following features:

• Two break channels (A and B)

• The following can be set as break compare conditions:

 24 address bits

Bit masking possible

 Bus cycle

Instruction fetch

Data access: data read, data write, data read/write

 Bus master

Either CPU or CPU/DTC can be selected

• The timing of PC break exception handling after the occurrence of a break condition is as

follows:

 Immediately before execution of the instruction fetched at the set address (instruction fetch)

 Immediately after execution of the instruction that accesses data at the set address (data

access)

• Module stop mode can be set

 The initial setting is for PBC operation to be halted. Register access is enabled by clearing

module stop mode.

130

6.1.2 Block Diagram

Figure 6-1 shows a block diagram of the PC break controller.

Output control

Mask control

Output control

Match signal

PC break

interrupt

Match signal

Mask control

BARA BCRA

BARB BCRB

Comparator Control

logic

Comparator Control

logic

Internal address

Access

status

Figure 6-1 Block Diagram of PC Break Controller

131

6.1.3 Register Configuration

Table 6-1 shows the PC break controller registers.

Table 6-1 PC Break Controller Registers

Initial Value

Name Abbreviation R/W Reset Address*1

Break address register A BARA R/W H'XX000000 H'FE00

Break address register B BARB R/W H'XX000000 H'FE04

Break control register A BCRA R/(W)*2H'00 H'FE08

Break control register B BCRB R/(W)*2H'00 H'FE09

Module stop control register C MSTPCRC R/W H'FF H'FDEA

Notes: *1 Lower 16 bits of the address.

*2 Only a 0 may be written to this bit to clear the flag.

6.2 Register Descriptions

6.2.1 Break Address Register A (BARA)

Bit

Initial value

Read/Write —

—

Unde-

fined —

—

Unde-

fined R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

• • •

BARA is a 32-bit readable/writable register that specifies the channel A break address.

BAA23 to BAA0 are initialized to H'000000 by a reset and in hardware standby mode.

Bits 31 to 24—Reserved: These bits return an undefined value if read, and cannot be modified.

Bits 23 to 0—Break Address A23 to A0 (BAA23–BAA0): These bits hold the channel A PC

break address.

132

6.2.2 Break Address Register B (BARB)

BARB is the channel B break address register. The bit configuration is the same as for BARA.

6.2.3 Break Control Register A (BCRA)

Bit

Initial value

Read/Write

Note:* Only a 0 may be written to this bit to clear the flag.

R/(W)*

CMFA

R/W

CDA

R/W

BAMRA2

R/W

BAMRA1

R/W

BAMRA0

R/W

CSELA1

R/W

CSELA0

R/W

BIEA

BCRA is an 8-bit readable/writable register that controls channel A PC breaks. BCRA (1) selects

the break condition bus master, (2) specifies bits subject to address comparison masking, and (3)

specifies whether the break condition is applied to an instruction fetch or a data access. It also

contains a condition match flag.

BCRA is initialized to H'00 by a reset and in hardware standby mode.

Bit 7—Condition Match Flag A (CMFA): Set to 1 when a break condition set for channel A is

satisfied. This flag is not cleared to 0.

Bit 7

CMFA Description

0 [Clearing condition]

When 0 is written to CMFA after reading CMFA = 1 (Initial value)

1 [Setting condition]

When a condition set for channel A is satisfied

Bit 6—CPU Cycle/DTC Cycle Select A (CDA): Selects the channel A break condition bus

master.

Bit 6

CDA Description

0 PC break is performed when CPU is bus master (Initial value)

1 PC break is performed when CPU or DTC is bus master

133

Bits 5 to 3—Break Address Mask Register A2 to A0 (BAMRA2–BAMRA0): These bits

specify which bits of the break address (BAA23–BAA0) set in BARA are to be masked.

Bit 5 Bit 4 Bit 3

BAMRA2 BAMRA1 BAMRA0 Description

0 0 0 All BARA bits are unmasked and included in break conditions

(Initial value)

1 BAA0 (lowest bit) is masked, and not included in break

conditions

1 0 BAA1–0 (lower 2 bits) are masked, and not included in break

conditions

1 BAA2–0 (lower 3 bits) are masked, and not included in break

conditions

1 0 0 BAA3–0 (lower 4 bits) are masked, and not included in break

conditions

1 BAA7–0 (lower 8 bits) are masked, and not included in break

conditions

1 0 BAA11–0 (lower 12 bits) are masked, and not included in break

conditions

1 BAA15–0 (lower 16 bits) are masked, and not included in break

conditions

Bits 2 and 1—Break Condition Select A (CSELA1, CSELA0): These bits selection an

instruction fetch, data read, data write, or data read/write cycle as the channel A break condition.

Bit 2 Bit 1

CSELA1 CSELA0 Description

0 0 Instruction fetch is used as break condition (Initial value)

1 Data read cycle is used as break condition

1 0 Data write cycle is used as break condition

1 Data read/write cycle is used as break condition

Bit 0—Break Interrupt Enable A (BIEA): Enables or disables channel A PC break interrupts.

Bit 0

BIEA Description

0 PC break interrupts are disabled (Initial value)

1 PC break interrupts are enabled

134

6.2.4 Break Control Register B (BCRB)

BCRB is the channel B break control register. The bit configuration is the same as for BCRA.

6.2.5 Module Stop Control Register C (MSTPCRC)

MSTPC7

R/W

Bit

Initial value

Read/Write

MSTPC6

R/W

MSTPC5

R/W

MSTPC4

R/W

MSTPC3

R/W

MSTPC2

R/W

MSTPC1

R/W

MSTPC0

R/W

MSTPCRC is an 8-bit readable/writable register that performs module stop mode control.

When the MSTPC4 bit is set to 1, PC break controller operation is stopped at the end of the bus

cycle, and module stop mode is entered. Register read/write accesses are not possible in module

stop mode. For details, see section 22.5, Module Stop Mode.

MSTPCRC is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 4—Module Stop (MSTPC4): Specifies the PC break controller module stop mode.

Bit 4

MSTPC4 Description

0 PC break controller module stop mode is cleared

1 PC break controller module stop mode is set (Initial value)

135

6.3 Operation

The operation flow from break condition setting to PC break interrupt exception handling is shown

in sections 6.3.1, PC Break Interrupt Due to Instrunction Fetch, and 6.3.2, PC Break Interrupt Due

to Data Access, taking the example of channel A.

6.3.1 PC Break Interrupt Due to Instruction Fetch

1. Initial settings

 Set the break address in BARA. For a PC break caused by an instruction fetch, set the

address of the first instruction byte as the break address.

 Set the break conditions in BCRA.

BCRA bit 6 (CDA): With a PC break caused by an instruction fetch, the bus master must

be the CPU. Set 0 to select the CPU.

BCRA bits 5–3 (BAMA2–0): Set the address bits to be masked.

BCRA bits 2–1 (CSELA1–0): Set 00 to specify an instruction fetch as the break condition.

BCRA bit 0 (BIEA): Set to 1 to enable break interrupts.

2. Satisfaction of break condition

 When the instruction at the set address is fetched, a PC break request is generated

immediately before execution of the fetched instruction, and the condition match flag

(CMFA) is set.

3. Interrupt handling

 After priority determination by the interrupt controller, PC break interrupt exception

handling is started.

6.3.2 PC Break Interrupt Due to Data Access

1. Initial settings

 Set the break address in BARA. For a PC break caused by a data access, set the target

ROM, RAM, I/O, or external address space address as the break address. Stack operations

and branch address reads are included in data accesses.

 Set the break conditions in BCRA.

BCRA bit 6 (CDA): Select the bus master.

BCRA bits 5–3 (BAMA2–0): Set the address bits to be masked.

BCRA bits 2–1 (CSELA1–0): Set 01, 10, or 11 to specify data access as the break

condition.

BCRA bit 0 (BIEA): Set to 1 to enable break interrupts.

136

2. Satisfaction of break condition

 After execution of the instruction that performs a data access on the set address, a PC break

request is generated and the condition match flag (CMFA) is set.

3. Interrupt handling

 After priority determination by the interrupt controller, PC break interrupt exception

handling is started.

6.3.3 Notes on PC Break Interrupt Handling

1. The PC break interrupt is shared by channels A and B. The channel from which the request

was issued must be determined by the interrupt handler.

2. The CMFA and CMFB flags are not cleared to 0, so 0 must be written to CMFA or CMFB

after first reading the flag while it is set to 1. If the flag is left set to 1, another interrupt will be

requested after interrupt handling ends.

3. A PC break interrupt generated when the DTC is the bus master is accepted after the bus has

been transferred to the CPU by the bus controller.

6.3.4 Operation in Transitions to Power-Down Modes

The operation when a PC break interrupt is set for an instruction fetch at the address after a

SLEEP instruction is shown below.

1. When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to

sleep mode, or from subactive mode to subsleep mode:

After execution of the SLEEP instruction, a transition is not made to sleep mode or subsleep

mode, and PC break interrupt handling is executed. After execution of PC break interrupt

handling, the instruction at the address after the SLEEP instruction is executed (figure 6-2

(A)).

2. When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to

subactive mode:

After execution of the SLEEP instruction, a transition is made to subactive mode via direct

transition exception handling. After the transition, PC break interrupt handling is executed,

then the instruction at the address after the SLEEP instruction is executed (figure 6-2 (B)).

3. When the SLEEP instruction causes a transition from subactive mode to high-speed (medium-

speed) mode:

137

After execution of the SLEEP instruction, and following the clock oscillation settling time, a

transition is made to high-speed (medium-speed) mode via direct transition exception

handling. After the transition, PC break interrupt handling is executed, then the instruction at

the address after the SLEEP instruction is executed (figure 6-2 (C)).

4. When the SLEEP instruction causes a transition to software standby mode or watch mode:

After execution of the SLEEP instruction, a transition is made to the respective mode, and PC

break interrupt handling is not executed. However, the CMFA or CMFB flag is set (figure 6-2

(D)).

SLEEP instruction

execution

High-speed

(medium-speed)

mode

SLEEP instruction

execution

Subactive

mode

System clock

→ subclock

Direct transition

exception handling

PC break exception

handling

Execution of instruction

after sleep instruction

Subclock →

system clock,

oscillation settling time

SLEEP instruction

execution

Transition to

respective mode

Direct transition

exception handling

PC break exception

handling

Execution of instruction

after sleep instruction

PC break exception

handling

Execution of instruction

after sleep instruction

(A)

(B) (C)

(D)

SLEEP instruction

execution

Figure 6-2 Operation in Power-Down Mode Transitions

6.3.5 PC Break Operation in Continuous Data Transfer

If a PC break interrupt is generated when the following operations are being performed, exception

handling is executed on completion of the specified transfer.

1. When a PC break interrupt is generated at the transfer address of an EEPMOV.B instruction:

PC break exception handling is executed after all data transfers have been completed and the

EEPMOV.B instruction has ended.

2. When a PC break interrupt is generated at a DTC transfer address:

PC break exception handling is executed after the DTC has completed the specified number of

data transfers, or after data for which the DISEL bit is set to 1 has been transferred.

138

6.3.6 When Instruction Execution is Delayed by One State

Caution is required in the following cases, as instruction execution is one state later than usual.

1. When the PBC is enabled (i.e. when the break interrupt enable bit is set to 1), execution of a

one-word branch instruction (Bcc d:8, BSR, JSR, JMP, TRAPA, RTE, or RTS) located in on-

chip ROM or RAM is always delayed by one state.

2. When break interruption by instruction fetch is set, the set address indicates on-chip ROM or

RAM space, and that address is used for data access, the instruction that executes the data

access is one state later than in normal operation.

3. When break interruption by instruction fetch is set and a break interrupt is generated, if the

executing instruction immediately preceding the set instruction has one of the addressing

modes shown below, and that address indicates on-chip ROM or RAM, and that address is

used for data access, the instruction will be one state later than in normal operation.

@ERn, @(d:16,ERn), @(d:32,ERn), @-ERn/ERn+, @aa:8, @aa:24, @aa:32, @(d:8,PC),

@(d:16,PC), @@aa:8

4. When break interruption by instruction fetch is set and a break interrupt is generated, if the

executing instruction immediately preceding the set instruction is NOP or SLEEP, or has

#xx,Rn as its addressing mode, and that instruction is located in on-chip ROM or RAM, the

instruction will be one state later than in normal operation.

139

6.3.7 Additional Notes

1. When a PC break is set for an instruction fetch at the address following a BSR, JSR, JMP,

TRAPA, RTE, or RTS instruction:

Even if the instruction at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS

instruction is fetched, it is not executed, and so a PC break interrupt is not generated by the

instruction fetch at the next address.

2. When the I bit is set by an LDC, ANDC, ORC, or XORC instruction, a PC break interrupt

becomes valid two states after the end of the executing instruction. If a PC break interrupt is

set for the instruction following one of these instructions, since interrupts, including NMI, are

disabled for a 3-state period in the case of LDC, ANDC, ORC, and XORC, the next instruction

is always executed. For details, see section 5, Interrupt Controller.

3. When a PC break is set for an instruction fetch at the address following a Bcc instruction:

A PC break interrupt is generated if the instruction at the next address is executed in

accordance with the branch condition, but is not generated if the instruction at the next address

is not executed.

4. When a PC break is set for an instruction fetch at the branch destination address of a Bcc

instruction:

A PC break interrupt is generated if the instruction at the branch destination is executed in

accordance with the branch condition, but is not generated if the instruction at the branch

destination is not executed.

140

141

Section 7 Bus Controller

7.1 Overview

The H8S/2646 Series has a built-in bus controller (BSC) that manages the external address space

divided into eight areas. The bus specifications, such as bus width and number of access states,

can be set independently for each area, enabling multiple memories to be connected easily.

The bus controller also has a bus arbitration function, and controls the operation of the internal bus

masters: the CPU, and data transfer controller (DTC).

7.1.1 Features

The features of the bus controller are listed below.

• Manages external address space in area units

 Manages the external space as 8 areas of 2-Mbytes

 Bus specifications can be set independently for each area

 Burst ROM interface can be set

• Basic bus interface

 8-bit access or 16-bit access can be selected for each area

 2-state access or 3-state access can be selected for each area

 Program wait states can be inserted for each area

• Burst ROM interface

 Burst ROM interface can be set for area 0

 Choice of 1- or 2-state burst access

• Idle cycle insertion

 An idle cycle can be inserted in case of an external read cycle between different areas

 An idle cycle can be inserted in case of an external write cycle immediately after an

external read cycle

• Write buffer functions

 External write cycle and internal access can be executed in parallel

• Bus arbitration function

 Includes a bus arbiter that arbitrates bus mastership among the CPU and DTC

• Other

 External bus release function

142

7.1.2 Block Diagram

Figure 7-1 shows a block diagram of the bus controller.

Area decoder

Bus

controller

WAIT

ABWCR

ASTCR

BCRH

BCRL

Internal

address bus

External bus control signals

Legend:

ABWCR : Bus width control register

ASTCR : Access state control register

BCRH : Bus control register H

BCRL : Bus control register L

WCRH : Wait control register H

WCRL : Wait control register L

Internal control

signals

Wait

controller WCRH

WCRL

Bus mode signal

Bus arbiter

CPU bus request signal

DTC bus request signal

CPU bus acknowledge signal

DTC bus acknowledge signal

Internal data bus

Figure 7-1 Block Diagram of Bus Controller

143

7.1.3 Pin Configuration

Table 7-1 summarizes the pins of the bus controller.

Table 7-1 Bus Controller Pins

Name Symbol I/O Function

Address strobe AS Output Strobe signal indicating that address output on address

bus is enabled.

Read RD Output Strobe signal indicating that external space is being

read.

High write HWR Output Strobe signal indicating that external space is to be

written, and upper half (D15 to D8) of data bus is

enabled.

Low write LWR Output Strobe signal indicating that external space is to be

written, and lower half (D7 to D0) of data bus is enabled.

Wait WAIT Input Wait request signal used when accessing external

3-state access space.

7.1.4 Register Configuration

Table 7-2 summarizes the registers of the bus controller.

Table 7-2 Bus Controller Registers

Name Abbreviation R/W Initial Value Address*1

Bus width control register ABWCR R/W H'FF/H'00*2H'FED0

Access state control register ASTCR R/W H'FF H'FED1

Wait control register H WCRH R/W H'FF H'FED2

Wait control register L WCRL R/W H'FF H'FED3

Bus control register H BCRH R/W H'D0 H'FED4

Bus control register L BCRL R/W H'08 H'FED5

Pin function control register PFCR R/W H'0D/H'00 H'FDEB

Notes: *1 Lower 16 bits of the address.

*2 Determined by the MCU operating mode.

144

7.2 Register Descriptions

7.2.1 Bus Width Control Register (ABWCR)

ABW7

R/W

ABW6

R/W

ABW5

R/W

ABW4

R/W

ABW3

R/W

ABW0

R/W

ABW2

R/W

ABW1

R/W

Bit :

Initial value :

Modes 5 to 7

Mode 4

:RW

Initial value :

:RW

ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or

16-bit access.

ABWCR sets the data bus width for the external memory space. The bus width for on-chip

memory and internal I/O registers is fixed regardless of the settings in ABWCR.

After a reset and in hardware standby mode, ABWCR is initialized to H'FF in modes 5, 6, 7, and

to H'00 in mode 4. It is not initialized in software standby mode.

Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select whether the

corresponding area is to be designated for 8-bit access or 16-bit access.

Bit n

ABWn Description

0 Area n is designated for 16-bit access

1 Area n is designated for 8-bit access

(n = 7 to 0)

7.2.2 Access State Control Register (ASTCR)

AST7

R/W

AST6

R/W

AST5

R/W

AST4

R/W

AST3

R/W

AST0

R/W

AST2

R/W

AST1

R/W

Bit

Initial value

R/W

ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access

space or a 3-state access space.

145

ASTCR sets the number of access states for the external memory space. The number of access

states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR.

ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bits 7 to 0—Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the

corresponding area is to be designated as a 2-state access space or a 3-state access space.

Wait state insertion is enabled or disabled at the same time.

Bit n

ASTn Description

0 Area n is designated for 2-state access

Wait state insertion in area n external space is disabled

1 Area n is designated for 3-state access (Initial value)

Wait state insertion in area n external space is enabled

(n = 7 to 0)

146

7.2.3 Wait Control Registers H and L (WCRH, WCRL)

WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait

states for each area.

Program waits are not inserted in the case of on-chip memory or internal I/O registers.

WCRH and WCRL are initialized to H'FF by a reset and in hardware standby mode. They are not

initialized in software standby mode.

WCRH

W71

R/W

W70

R/W

W61

R/W

W60

R/W

W51

R/W

W40

R/W

W50

R/W

W41

R/W

Bit

Initial value

R/W

Bits 7 and 6—Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of

program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set

to 1.

Bit 7 Bit 6

W71 W70 Description

0 0 Program wait not inserted when external space area 7 is accessed

1 1 program wait state inserted when external space area 7 is accessed

1 0 2 program wait states inserted when external space area 7 is accessed

1 3 program wait states inserted when external space area 7 is accessed

(Initial value)

Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of

program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set

to 1.

Bit 5 Bit 4

W61 W60 Description

0 0 Program wait not inserted when external space area 6 is accessed

1 1 program wait state inserted when external space area 6 is accessed

1 0 2 program wait states inserted when external space area 6 is accessed

1 3 program wait states inserted when external space area 6 is accessed

(Initial value)

147

Bits 3 and 2—Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of

program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set

to 1.

Bit 3 Bit 2

W51 W50 Description

0 0 Program wait not inserted when external space area 5 is accessed

1 1 program wait state inserted when external space area 5 is accessed

1 0 2 program wait states inserted when external space area 5 is accessed

1 3 program wait states inserted when external space area 5 is accessed

(Initial value)

Bits 1 and 0—Area 4 Wait Control 1 and 0 (W41, W40): These bits select the number of

program wait states when area 4 in external space is accessed while the AST4 bit in ASTCR is set

to 1.

Bit 1 Bit 0

W41 W40 Description

0 0 Program wait not inserted when external space area 4 is accessed

1 1 program wait state inserted when external space area 4 is accessed

1 0 2 program wait states inserted when external space area 4 is accessed

1 3 program wait states inserted when external space area 4 is accessed

(Initial value)

148

WCRL

W31

R/W

W30

R/W

W21

R/W

W20

R/W

W11

R/W

W00

R/W

W10

R/W

W01

R/W

Bit

Initial value

R/W

Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of

program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set

to 1.

Bit 7 Bit 6

W31 W30 Description

0 0 Program wait not inserted when external space area 3 is accessed

1 1 program wait state inserted when external space area 3 is accessed

1 0 2 program wait states inserted when external space area 3 is accessed

1 3 program wait states inserted when external space area 3 is accessed

(Initial value)

Bits 5 and 4—Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of

program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set

to 1.

Bit 5 Bit 4

W21 W20 Description

0 0 Program wait not inserted when external space area 2 is accessed

1 1 program wait state inserted when external space area 2 is accessed

1 0 2 program wait states inserted when external space area 2 is accessed

1 3 program wait states inserted when external space area 2 is accessed

(Initial value)

149

Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of

program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set

to 1.

Bit 3 Bit 2

W11 W10 Description

0 0 Program wait not inserted when external space area 1 is accessed

1 1 program wait state inserted when external space area 1 is accessed

1 0 2 program wait states inserted when external space area 1 is accessed

1 3 program wait states inserted when external space area 1 is accessed

(Initial value)

Bits 1 and 0—Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of

program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set

to 1.

Bit 1 Bit 0

W01 W00 Description

0 0 Program wait not inserted when external space area 0 is accessed

1 1 program wait state inserted when external space area 0 is accessed

1 0 2 program wait states inserted when external space area 0 is accessed

1 3 program wait states inserted when external space area 0 is accessed

(Initial value)

150

7.2.4 Bus Control Register H (BCRH)

ICIS1

R/W

ICIS0

R/W

BRSTRM

R/W

BRSTS1

R/W

BRSTS0

R/W

—

R/W

—

R/W

—

R/W

Bit

Initial value

R/W

BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle

insertion, and the memory interface for area 0.

BCRH is initialized to H'D0 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted

between bus cycles when successive external read cycles are performed in different areas.

Bit 7

ICIS1 Description

0 Idle cycle not inserted in case of successive external read cycles in different areas

1 Idle cycle inserted in case of successive external read cycles in different areas

(Initial value)

Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted

between bus cycles when successive external read and external write cycles are performed .

Bit 6

ICIS0 Description

0 Idle cycle not inserted in case of successive external read and external write cycles

1 Idle cycle inserted in case of successive external read and external write cycles

(Initial value)

Bit 5—Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM

interface.

Bit 5

BRSTRM Description

0 Area 0 is basic bus interface (Initial value)

1 Area 0 is burst ROM interface

151

Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM

interface.

Bit 4

BRSTS1 Description

0 Burst cycle comprises 1 state

1 Burst cycle comprises 2 states (Initial value)

Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a

burst ROM interface burst access.

Bit 3

BRSTS0 Description

0 Max. 4 words in burst access (Initial value)

1 Max. 8 words in burst access

Bits 2 to 0—Reserved: Only 0 should be written to these bits.

7.2.5 Bus Control Register L (BCRL)

—

R/W

—

R/W

—

R/W

—

R/W

WAITE

R/W

—

R/W

WDBE

R/W

Bit

Initial value

R/W

BCRL is an 8-bit readable/writable register that performs selection of the external bus-released

state protocol, enabling or disabling of the write data buffer function.

BCRL is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bits 7 and 6—Reserved: Only 0 should be written to these bits.

Bit 5—Reserved: It is always read as 0. Cannot be written to.

Bit 4—Reserved: Only 0 should be written to this bit.

Bit 3—Reserved: Only 1 should be written to this bit.

Bit 2—Reserved: Only 0 should be written to this bit.

152

Bit 1—Write Data Buffer Enable (WDBE): This bit selects whether or not to use the write

buffer function in the external write cycle.

Bit 1

WDBE Description

0 Write data buffer function not used (Initial value)

1 Write data buffer function used

Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by means of the

WAIT pin.

Bit 0

WAITE Description

0 Wait input by WAIT pin disabled. WAIT pin can be used as I/O port. (Initial value)

1 Wait input by WAIT pin enabled

7.2.6 Pin Function Control Register (PFCR)

—

R/W

—

R/W

—

R/W

—

R/W

AE3

1/0

R/W

AE0

1/0

R/W

AE2

1/0

R/W

AE1

R/W

Bit

Initial value

R/W

PFCR is an 8-bit read/write register that controls the address output in expanded mode with ROM.

PFCR is initialized to H'0D/H'00 by a reset and in hardware standby mode. It retains its previous

state in software standby mode.

Bits 7 to 4—Reserved: Only 0 should be written to these bits.

153

Bits 3 to 0—Address Output Enable 3 to 0 (AE3–AE0): These bits select enabling or disabling

of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When a pin is

enabled for address output, the address is output regardless of the corresponding DDR setting.

When a pin is disabled for address output, it becomes an output port when the corresponding DDR

bit is set to 1.

Bit 3 Bit 2 Bit 1 Bit 0

AE3 AE2 AE1 AE0 Description

0000A8–A23 address output disabled (Initial value*)

1 A8 address output enabled; A9–A23 address output disabled

1 0 A8, A9 address output enabled; A10–A23 address output

disabled

1A8–A10 address output enabled; A11–A23 address output

disabled

100A8–A11 address output enabled; A12–A23 address output

disabled

1A8–A12 address output enabled; A13–A23 address output

disabled

10A8–A13 address output enabled; A14–A23 address output

disabled

1A8–A14 address output enabled; A15–A23 address output

disabled

1000A8–A15 address output enabled; A16–A23 address output

disabled

1A8–A16 address output enabled; A17–A23 address output

disabled

10A8–A17 address output enabled; A18–A23 address output

disabled

1A8–A18 address output enabled; A19–A23 address output

disabled

100A8–A19 address output enabled; A20–A23 address output

disabled

1A8–A20 address output enabled; A21–A23 address output

disabled (Initial value*)

10A8–A21 address output enabled; A22, A23 address output

disabled

1A8–A23 address output enabled

Note: *In expanded mode with ROM, bits AE3 to AE0 are initialized to B'0000.

In ROMless expanded mode, bits AE3 to AE0 are initialized to B'1101.

Address pins A0 to A7 are made address outputs by setting the corresponding DDR bits to

154

7.3 Overview of Bus Control

7.3.1 Area Partitioning

In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas, 0 to

7, in 2-Mbyte units, and performs bus control for external space in area units. In normal mode*, it

controls a 64-kbyte address space comprising part of area 0. Figure 7-2 shows an outline of the

memory map.

Note: * Not available in the H8S/2646 Series.

Area 0

(2Mbytes)

H'000000

H'FFFFFF

(1) (2)

H'0000

H'1FFFFF

H'200000 Area 1

(2Mbytes)

H'3FFFFF

H'400000 Area 2

(2Mbytes)

H'5FFFFF

H'600000 Area 3

(2Mbytes)

H'7FFFFF

H'800000 Area 4

(2Mbytes)

H'9FFFFF

H'A00000 Area 5

(2Mbytes)

H'BFFFFF

H'C00000 Area 6

(2Mbytes)

H'DFFFFF

H'E00000 Area 7

(2Mbytes)

H'FFFF

Advanced mode Normal mode*

Note: * Not available in the H8S/2646.

Figure 7-2 Overview of Area Partitioning

155

7.3.2 Bus Specifications

The external space bus specifications consist of three elements: bus width, number of access

states, and number of program wait states.

The bus width and number of access states for on-chip memory and internal I/O registers are

fixed, and are not affected by the bus controller.

Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit

bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected

functions as a16-bit access space.

If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit

access, 16-bit bus mode is set. When the burst ROM interface is designated, 16-bit bus mode is

always set.

Number of Access States: Two or three access states can be selected with ASTCR. An area for

which 2-state access is selected functions as a 2-state access space, and an area for which 3-state

access is selected functions as a 3-state access space.

With the burst ROM interface, the number of access states may be determined without regard to

ASTCR.

When 2-state access space is designated, wait insertion is disabled.

Number of Program Wait States: When 3-state access space is designated by ASTCR, the

number of program wait states to be inserted automatically is selected with WCRH and WCRL.

From 0 to 3 program wait states can be selected.

Table 7-3 shows the bus specifications for each basic bus interface area.

156

Table 7-3 Bus Specifications for Each Area (Basic Bus Interface)

ABWCR ASTCR WCRH, WCRL Bus Specifications (Basic Bus Interface)

ABWn ASTn Wn1 Wn0 Bus Width Access States Program Wait

States

00—— 16 2 0

100 3 0

10 2

10—— 82 0

100 3 0

10 2

7.3.3 Memory Interfaces

The H8S/2646 Series memory interfaces comprise a basic bus interface that allows direct

connection or ROM, SRAM, and so on, and a burst ROM interface that allows direct connection

of burst ROM. The memory interface can be selected independently for each area.

An area for which the basic bus interface is designated functions as normal space, and an area for

which the burst ROM interface is designated functions as burst ROM space.

157

7.3.4 Interface Specifications for Each Area

The initial state of each area is basic bus interface, 3-state access space. The initial bus width is

selected according to the operating mode. The bus specifications described here cover basic items

only, and the sections on each memory interface (sections 7.4, Basic Bus Interface and 7.5, Burst

ROM Interface) should be referred to for further details.

Area 0: Area 0 includes on-chip ROM, and in ROM-disabled expansion mode, all of area 0 is

external space. In ROM-enabled expansion mode, the space excluding on-chip ROM is external

space.

Either basic bus interface or burst ROM interface can be selected for area 0.

Areas 1 to 6: In external expansion mode, all of areas 1 to 6 is external space.

Only the basic bus interface can be used for areas 1 to 6.

Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In external expansion mode,

the space excluding the on-chip RAM and internal I/O registers is external space. The on-chip

RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the

RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes

external space.

Only the basic bus interface can be used for the area 7.

158

7.4 Basic Bus Interface

7.4.1 Overview

The basic bus interface enables direct connection of ROM, SRAM, and so on.

The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see

table 7-3).

7.4.2 Data Size and Data Alignment

Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus

controller has a data alignment function, and when accessing external space, controls whether the

upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus

specifications for the area being accessed (8-bit access space or 16-bit access space) and the data

size.

8-Bit Access Space: Figure 7-3 illustrates data alignment control for the 8-bit access space. With

the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of

data that can be accessed at one time is one byte: a word transfer instruction is performed as two

byte accesses, and a longword transfer instruction, as four byte accesses.

D15 D8 D7 D0

Upper data bus

Lower data bus

Byte size

Word size 1st bus cycle

2nd bus cycle

Longword size 1st bus cycle

2nd bus cycle

3rd bus cycle

4th bus cycle

Figure 7-3 Access Sizes and Data Alignment Control (8-Bit Access Space)

159

16-Bit Access Space: Figure 7-4 illustrates data alignment control for the 16-bit access space.

With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are

used for accesses. The amount of data that can be accessed at one time is one byte or one word,

and a longword transfer instruction is executed as two word transfer instructions.

In byte access, whether the upper or lower data bus is used is determined by whether the address is

even or odd. The upper data bus is used for an even address, and the lower data bus for an odd

address.

D15 D8 D7 D0

Upper data bus

Byte size

Word size

1st bus cycle

2nd bus cycle

Longword

size

• Even address

Byte size • Odd address

Lower data bus

Figure 7-4 Access Sizes and Data Alignment Control (16-Bit Access Space)

160

7.4.3 Valid Strobes

Table 7-4 shows the data buses used and valid strobes for the access spaces.

In a read, the RD signal is valid without discrimination between the upper and lower halves of the

data bus.

In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the

lower half.

Table 7-4 Data Buses Used and Valid Strobes

Area Access

Size Read/

Write Address Valid

Strobe Upper Data Bus

(D15 to D8) Lower data bus

(D7 to D0)

8-bit access Byte Read —RD Valid Invalid

space Write —HWR Hi-Z

16-bit access Byte Read Even RD Valid Invalid

space Odd Invalid Valid

Write Even HWR Valid Hi-Z

Odd LWR Hi-Z Valid

Word Read —RD Valid Valid

Write —HWR, LWR Valid Valid

Note: Hi-Z: High impedance.

Invalid: Input state; input value is ignored.

161

7.4.4 Basic Timing

8-Bit 2-State Access Space: Figure 7-5 shows the bus timing for an 8-bit 2-state access space.

When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used.

The LWR pin is fixed high. Wait states cannot be inserted.

Bus cycle

T1T2

Address bus

D15 to D8 Valid

D7 to D0 Invalid

Read

HWR

LWR

D15 to D8 Valid

D7 to D0 High impedance

Write

High

Figure 7-5 Bus Timing for 8-Bit 2-State Access Space

162

8-Bit 3-State Access Space: Figure 7-6 shows the bus timing for an 8-bit 3-state access space.

When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used.

The LWR pin is fixed high. Wait states can be inserted.

Bus cycle

T1T2

Address bus

D15 to D8 Valid

D7 to D0 Invalid

Read

HWR

LWR

D15 to D8 Valid

D7 to D0 High impedance

Write

High

Figure 7-6 Bus Timing for 8-Bit 3-State Access Space

163

16-Bit 2-State Access Space: Figures 7-7 to 7-9 show bus timings for a 16-bit 2-state access

space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used

for the even address, and the lower half (D7 to D0) for the odd address.

Wait states cannot be inserted.

Bus cycle

T1T2

Address bus

D15 to D8 Valid

D7 to D0 Invalid

Read

HWR

D15 to D8 Valid

D7 to D0 High impedance

Write

LWR High

Figure 7-7 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access)

164

Bus cycle

T1T2

Address bus

D15 to D8 Invalid

D7 to D0 Valid

Read

HWR

LWR

D15 to D8 High impedance

D7 to D0 Valid

Write

High

Figure 7-8 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access)

165

Bus cycle

T1T2

Address bus

D15 to D8 Valid

D7 to D0 Valid

Read

HWR

LWR

D15 to D8 Valid

D7 to D0 Valid

Write

Figure 7-9 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access)

166

16-Bit 3-State Access Space: Figures 7-10 to 7-12 show bus timings for a 16-bit 3-state access

space. When a 16-bit access space is accessed , the upper half (D15 to D8) of the data bus is used

for the even address, and the lower half (D7 to D0) for the odd address.

Wait states can be inserted.

Bus cycle

T1T2

Address bus

D15 to D8 Valid

D7 to D0 Invalid

Read

HWR

LWR

D15 to D8 Valid

D7 to D0 High impedance

Write

High

Figure 7-10 Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access)

167

Bus cycle

T1T2

Address bus

D15 to D8 Invalid

D7 to D0 Valid

Read

HWR

LWR

D15 to D8 High impedance

D7 to D0 Valid

Write

High

Figure 7-11 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access)

168

Bus cycle

T1T2

Address bus

D15 to D8 Valid

D7 to D0 Valid

Read

HWR

LWR

D15 to D8 Valid

D7 to D0 Valid

Write

Figure 7-12 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access)

169

7.4.5 Wait Control

When accessing external space, the H8S/2646 Series can extend the bus cycle by inserting one or

more wait states (Tw). There are two ways of inserting wait states: program wait insertion.

Program Wait Insertion: From 0 to 3 wait states can be inserted automatically between the T2

state and T3 state on an individual area basis in 3-state access space, according to the settings of

WCRH and WCRL.

Pin Wait Insertion: Setting the WAITE bit in BCRH to 1 enables wait input by means of the

WAIT pin. When external space is accessed in this state, a program wait is first inserted in

accordance with the settings in WCRH and WCRL. If the WAIT pin is low at the falling edge of ø

in the last T2 or Tw state, another Tw state is inserted. If the WAIT pin is held low, Tw states are

inserted until it goes high.

This is useful when inserting four or more Tw states, or when changing the number of Tw states for

different external devices.

The WAITE bit setting applies to all areas.

170

Figure 7-13 shows an example of wait state insertion timing.

By program wait By WAIT pin

Address bus

WAIT

Data bus Read data

Read

HWR, LWR

Write data

Write

Note: Downward arrows show the timing of WAIT pin sampling.

Data bus

T2TwTwTwT3

Figure 7-13 Example of Wait State Insertion Timing

The settings after a reset are: 3-state access, 3 program wait state insertion.

171

7.5 Burst ROM Interface

7.5.1 Overview

In this LSI, the area 0 external space can be set as burst ROM space and burst ROM interfacing

performed. Burst ROM space interfacing allows 16-bit ROM capable of burst access to be

accessed at high-speed.

The BRSTRM bit of BCRH sets area 0 as burst ROM space. CPU instruction fetches (only) can be

performed using a maximum of 4-word or 8-word continuous burst access. 1 state or 2 states can

be selected in the case of burst access.

7.5.2 Basic Timing

The AST0 bit of ASTCR sets the number of access states in the initial cycle (full access) of the

burst ROM interface. Wait states can be inserted when the AST0 bit is set to 1. The burst cycle

can be set for 1 state or 2 sttes by setting the BRSTS1 bit of BCRH. Wait states cannot be inserted.

When area 0 is set as burst ROM space, area 0 is a 16-bit access space regardless of the ABW0 bit

of ABWCR.

When the BRSTS0 bit of BCRH is cleared to 0, 4-word max. burst access is performed. When the

BRSTS0 bit is set to 1, 8-word max. burst access is performed.

Figure 7.14 (a) and (b) shows the basic access timing for the burst ROM space.

Figure 7.14 (a) is an example when both the AST0 and BRSTS1 bits are set to 1.

Figure 7.14 (b) is an example when both the AST0 and BRSTS1 bits are set to 0.

172

Address bus

Data bus

T2T3T1T2T1

Full access

Burst access

Low address only changes

Read data Read data Read data

Figure 7.14 (a) Example Burst ROM Access Timing (AST0=BRSTS1=1)

Address bus

Data bus

T2T1T1

Full access

Burst access

Low address only changes

Read data Read data Read data

Figure 7.14 (b) Example Burst ROM Access Timing (AST0=BRSTS1=0)

173

7.5.3 Wait Control

As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT

pin can be used in the burst ROM interface initial cycle (full access). See section 7.4.5, Wait

Control.

Wait states cannot be inserted in the burst cycle.

174

7.6 Idle Cycle

7.6.1 Operation

When the H8S/2646 Series accesses external space , it can insert a 1-state idle cycle (TI) between

bus cycles in the following two cases: (1) when read accesses between different areas occur

consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an

idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output

floating time, and high-speed memory, I/O interfaces, and so on.

(1) Consecutive Reads between Different Areas

If consecutive reads between different areas occur while the ICIS1 bit in BCRH is set to 1, an idle

cycle is inserted at the start of the second read cycle.

Figure 7-15 shows an example of the operation in this case. In this example, bus cycle A is a read

cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,

each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in

cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,

and a data collision is prevented.

Address bus

Bus cycle A

Data bus

T2T3T1T2

Bus cycle B Bus cycle A Bus cycle B

Long output

floating time

Note: * The CS signal is generated externally rather than inside the LSI device.

Data

collision

(a) Idle cycle not inserted

(ICIS1 = 0) (b) Idle cycle inserted

(Initial value ICIS1 = 1)

Address bus

Data bus

T2T3TIT1T2

CS* (area A)

CS* (area B)

CS* (area A)

CS* (area B)

;

Figure 7-15 Example of Idle Cycle Operation (1)

175

(2) Write after Read

If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle

cycle is inserted at the start of the write cycle.

Figure 7-16 shows an example of the operation in this case. In this example, bus cycle A is a read

cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an

idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and

the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.

Address bus

Note: * The CS signal is generated externally rather than inside the LSI device.

Bus cycle A

T2T3T1T2

Bus cycle B

Possibility of overlap between

CS (area B) and RD

Address bus

Bus cycle A

T2T3TIT1

Bus cycle B

CS* (area A)

CS* (area B)

CS* (area A)

CS* (area B)

(a) Idle cycle not inserted

(ICIS1 = 0) (b) Idle cycle inserted

(Initial value ICIS1 = 1)

Figure 7-16 Example of Idle Cycle Operation (2)

176

(3) Relationship between Chip Select (CS*) Signal and Read (RD) Signal

Depending on the system’s load conditions, the RD signal may lag behind the CS signal*. An

example is shown in figure 7-17.

In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap

between the bus cycle A RD signal and the bus cycle B CS signal.

Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS

signals.

In the initial state after reset release, idle cycle insertion (b) is set.

Note: * The CS signal is generated externally rather than inside the LSI device.

Address bus

Bus cycle A

;

Data bus

T2T3T1T2

Bus cycle B

Long output

floating time

Data

collision

Address bus

Bus cycle A

Data bus

T2T3TIT1

Bus cycle B

HWR

CS* (area A)

CS* (area B)

CS* (area A)

CS* (area B)

(a) Idle cycle not inserted

(ICIS0 = 0) (b) Idle cycle inserted

(Initial value ICIS0 = 1)

Note: * The CS signal is generated externally rather than inside the LSI device.

Figure 7-17 Relationship between Chip Select (CS)* and Read (RD)

177

7.6.2 Pin States During Idle Cycles

Table 7-5 shows the pin states during idle cycles.

Table 7-5 Pin States During Idle Cycles

Pins Pin State

A23 to A0 Content identical to immediately following bus cycle

D15 to D0 High impedance

AS High level

RD High level

HWR High level

LWR High level

178

7.7 Write Data Buffer Function

The H8S/2646 Series has a write data buffer function in the external data bus. Using this function

enables external writes to be executed in parallel with internal accesses. The write data buffer

function is made available by setting the WDBE bit in BCRL to 1.

Figure 7-18 shows an example of the timing when the write data buffer function is used. When

this function is used, if an external write continues for 2 states or longer, and there is an internal

access next, only an external write is executed in the first state, but from the next state onward an

internal access (on-chip memory or internal I/O register read/write) is executed in parallel with the

external write rather than waiting until it ends.

Internal address bus

A23 to A0

External write cycle

HWR, LWR

T2TWTWT3

On-chip memory read Internal I/O register read

Internal read signal

D15 to D0

External address

Internal memory

External

space

write

Internal I/O register address

Figure 7-18 Example of Timing when Write Data Buffer Function is Used

179

7.8 Bus Arbitration

7.8.1 Overview

The H8S/2646 Series has a bus arbiter that arbitrates bus master operations.

There are two bus masters, the CPU and DTC which perform read/write operations when they

have possession of the bus. Each bus master requests the bus by means of a bus request signal. The

bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a

bus request acknowledge signal. The selected bus master then takes possession of the bus and

begins its operation.

7.8.2 Operation

The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a bus

request acknowledge signal to the bus master making the request. If there are bus requests from

more than one bus master, the bus request acknowledge signal is sent to the one with the highest

priority. When a bus master receives the bus request acknowledge signal, it takes possession of the

bus until that signal is canceled.

The order of priority of the bus masters is as follows:

(High) DTC > CPU (Low)

7.8.3 Bus Transfer Timing

Even if a bus request is received from a bus master with a higher priority than that of the bus

master that has acquired the bus and is currently operating, the bus is not necessarily transferred

immediately. There are specific times at which each bus master can relinquish the bus.

CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC,

the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of

the bus is as follows:

• The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in

discrete operations, as in the case of a longword-size access, the bus is not transferred between

the operations. See Appendix A-5, Bus States During Instruction Execution, for timings at

which the bus is not transferred.

• If the CPU is in sleep mode, it transfers the bus immediately.

DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated.

180

The DTC can release the bus after a vector read, a register information read (3 states), a single data

transfer, or a register information write (3 states). It does not release the bus during a register

information read (3 states), a single data transfer, or a register information write (3 states).

7.9 Resets and the Bus Controller

In a reset, the H8S/2646 Series, including the bus controller, enters the reset state at that point, and

an executing bus cycle is discontinued.

181

Section 8 Data Transfer Controller (DTC)

8.1 Overview

The H8S/2646 Series includes a data transfer controller (DTC). The DTC can be activated by an

interrupt or software, to transfer data.

8.1.1 Features

• Transfer possible over any number of channels

 Transfer information is stored in memory

 One activation source can trigger a number of data transfers (chain transfer)

• Wide range of transfer modes

 Normal, repeat, and block transfer modes available

 Incrementing, decrementing, and fixing of source and destination addresses can be selected

• Direct specification of 16-Mbyte address space possible

 24-bit transfer source and destination addresses can be specified

• Transfer can be set in byte or word units

• A CPU interrupt can be requested for the interrupt that activated the DTC

 An interrupt request can be issued to the CPU after one data transfer ends

 An interrupt request can be issued to the CPU after the specified data transfers have

completely ended

• Activation by software is possible

• Module stop mode can be set

 The initial setting enables DTC registers to be accessed. DTC operation is halted by setting

module stop mode.

182

8.1.2 Block Diagram

Figure 8-1 shows a block diagram of the DTC.

The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to

the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register

information.

Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1.

Interrupt

request

Interrupt controller DTC

Internal address bus

DTC service

request

Control logic

MRA MRB

CRA

CRB

DAR

SAR

CPU interrupt

request

On-chip

RAM

Internal data bus

Legend

MRA, MRB

CRA, CRB

SAR

DAR

DTCERA to DTCERG, I

DTVECR

DTCERA to

DTCERG,

DTCERI

DTVECR

: DTC mode registers A and B

: DTC transfer count registers A and B

: DTC source address register

: DTC destination address register

: DTC enable registers A to G, I

: DTC vector register

Figure 8-1 Block Diagram of DTC

183

8.1.3 Register Configuration

Table 8-1 summarizes the DTC registers.

Table 8-1 DTC Registers

Name Abbreviation R/W Initial Value Address*1

DTC mode register A MRA —*2Undefined —*3

DTC mode register B MRB —*2Undefined —*3

DTC source address register SAR —*2Undefined —*3

DTC destination address register DAR —*2Undefined —*3

DTC transfer count register A CRA —*2Undefined —*3

DTC transfer count register B CRB —*2Undefined —*3

DTC enable registers DTCER R/W H'00 H'FE16 to H'FE1E

DTC vector register DTVECR R/W H'00 H'FE1F

Module stop control register A MSTPCRA R/W H'3F H'FDE8

Notes: *1 Lower 16 bits of the address.

*2 Registers within the DTC cannot be read or written to directly.

*3 Register information is located in on-chip RAM addresses H'EBC0 to H'EFBF. It cannot

be located in external memory space. When the DTC is used, do not clear the RAME

bit in SYSCR to 0.

184

8.2 Register Descriptions

8.2.1 DTC Mode Register A (MRA)

SM1 6

SM0 5

DM1 4

DM0 3

MD1 0

MD0 1

DTS

Bit

Initial value

—

R/W : —

—

*: Undefined

MRA is an 8-bit register that controls the DTC operating mode.

Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is

to be incremented, decremented, or left fixed after a data transfer.

Bit 7 Bit 6

SM1 SM0 Description

0—SAR is fixed

1 0 SAR is incremented after a transfer

(by +1 when Sz = 0; by +2 when Sz = 1)

1 SAR is decremented after a transfer

(by –1 when Sz = 0; by –2 when Sz = 1)

Bits 5 and 4—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether

DAR is to be incremented, decremented, or left fixed after a data transfer.

Bit 5 Bit 4

DM1 DM0 Description

0—DAR is fixed

1 0 DAR is incremented after a transfer

(by +1 when Sz = 0; by +2 when Sz = 1)

1 DAR is decremented after a transfer

(by –1 when Sz = 0; by –2 when Sz = 1)

185

Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode.

Bit 3 Bit 2

MD1 MD0 Description

0 0 Normal mode

1 Repeat mode

1 0 Block transfer mode

1—

Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination

side is set to be a repeat area or block area, in repeat mode or block transfer mode.

Bit 1

DTS Description

0 Destination side is repeat area or block area

1 Source side is repeat area or block area

Bit 0—DTC Data Transfer Size (Sz): Specifies the size of data to be transferred.

Bit 0

Sz Description

0 Byte-size transfer

1 Word-size transfer

186

8.2.2 DTC Mode Register B (MRB)

CHNE 6

DISEL 5

—4

—3

—0

—

—1

—

Bit

Initial value

R/W : —

—

*: Undefined

MRB is an 8-bit register that controls the DTC operating mode.

Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer. With chain transfer, a

number of data transfers can be performed consecutively in response to a single transfer request.

In data transfer with CHNE set to 1, determination of the end of the specified number of transfers,

clearing of the interrupt source flag, and clearing of DTCER is not performed.

Bit 7

CHNE Description

0 End of DTC data transfer (activation waiting state is entered)

1 DTC chain transfer (new register information is read, then data is transferred)

Bit 6—DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are

disabled or enabled after a data transfer.

Bit 6

DISEL Description

0 After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is

0 (the DTC clears the interrupt source flag of the activating interrupt to 0)

1 After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the

interrupt source flag of the activating interrupt to 0)

Bits 5 to 0—Reserved: These bits have no effect on DTC operation in the H8S/2646 Series, and

should always be written with 0.

187

8.2.3 DTC Source Address Register (SAR)

23 22 21 20 19 43210

Bit

Initial value

—

R/W : —

—

*: Undefined

SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.

For word-size transfer, specify an even source address.

8.2.4 DTC Destination Address Register (DAR)

23 22 21 20 19 43210

nitial value

—

/W : ———— —————

***** *****

*: Undefined

DAR is a 24-bit register that designates the destination address of data to be transferred by the

DTC. For word-size transfer, specify an even destination address.

8.2.5 DTC Transfer Count Register A (CRA)

15 14 13 12 11109876543210

CRAH CRAL

Bit

Initial value

—

R/W : —

—

*: Undefined

CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.

In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is

decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.

188

In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits

(CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL

functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is

transferred, and the contents of CRAH are sent when the count reaches H'00. This operation is

repeated.

8.2.6 DTC Transfer Count Register B (CRB)

15 14 13 12 11109876543210

Bit

Initial value

————————————————

R/W :

****************

*: Undefined

CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in

block transfer mode. It functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1

every time data is transferred, and transfer ends when the count reaches H'0000.

8.2.7 DTC Enable Registers (DTCER)

DTCE7

R/W

DTCE6

R/W

DTCE5

R/W

DTCE4

R/W

DTCE3

R/W

DTCE0

R/W

DTCE2

R/W

DTCE1

R/W

Bit

Initial value

R/W

The DTC enable registers comprise eight 8-bit readable/writable registers, DTCERA to DTCERG

and DTCERI, with bits corresponding to the interrupt sources that can control enabling and

disabling of DTC activation. These bits enable or disable DTC service for the corresponding

interrupt sources.

The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode.

189

Bit n—DTC Activation Enable (DTCEn)

Bit n

DTCEn Description

0 DTC activation by this interrupt is disabled (Initial value)

[Clearing conditions]

• When the DISEL bit is 1 and the data transfer has ended

• When the specified number of transfers have ended

1 DTC activation by this interrupt is enabled

[Holding condition]

When the DISEL bit is 0 and the specified number of transfers have not ended

(n = 7 to 0)

A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence

between interrupt sources and DTCE bits is shown in table 8-4, together with the vector number

generated for each interrupt controller.

For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and

writing. If all interrupts are masked, multiple activation sources can be set at one time by writing

data after executing a dummy read on the relevant register.

8.2.8 DTC Vector Register (DTVECR)

SWDTE

R/(W)*1

DTVEC6

R/(W)*2

DTVEC5

R/(W)*2

DTVEC4

R/(W)*2

DTVEC3

R/(W)*2

DTVEC0

R/(W)*2

DTVEC2

R/(W)*2

DTVEC1

R/(W)*2

Notes: *1 Only 1 can be written to the SWDTE bit.

*2 Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0.

Bit

Initial value

R/W

DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by

software, and sets a vector number for the software activation interrupt.

DTVECR is initialized to H'00 by a reset and in hardware standby mode.

190

Bit 7—DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by

software.

Bit 7

SWDTE Description

0 DTC software activation is disabled (Initial value)

[Clearing conditions]

• When the DISEL bit is 0 and the specified number of transfers have not ended

• When 0 s written to the DISEL bit after a software-activated data transfer end

interrupt (SWDTEND) request has been sent to the CPU

1 DTC software activation is enabled

[Holding conditions]

• When the DISEL bit is 1 and data transfer has ended

• When the specified number of transfers have ended

• During data transfer due to software activation

Bits 6 to 0—DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits

specify a vector number for DTC software activation.

The vector address is expressed as H'0400 + ((vector number) << 1). <<1 indicates a one-bit left-

shift. For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420.

8.2.9 Module Stop Control Register A (MSTPCRA)

MSTPA7

R/W

Bit

Initial value

Read/Write

MSTPA6

R/W

MSTPA5

R/W

MSTPA4

R/W

MSTPA3

R/W

MSTPA2

R/W

MSTPA1

R/W

MSTPA0

R/W

MSTPCRA is a 8-bit readable/writable register that performs module stop mode control.

When the MSTPA6 bit in MSTPCRA is set to 1, the DTC operation stops at the end of the bus

cycle and a transition is made to module stop mode. However, 1 cannot be written in the MSTPA6

bit while the DTC is operating. For details, see section 22.5, Module Stop Mode.

MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized in

software standby mode.

191

Bit 6—Module Stop (MSTPA6): Specifies the DTC module stop mode.

Bit 6

MSTPA6 Description

0 DTC module stop mode cleared (Initial value)

1 DTC module stop mode set

192

8.3 Operation

8.3.1 Overview

When activated, the DTC reads register information that is already stored in memory and transfers

data on the basis of that register information. After the data transfer, it writes updated register

information back to memory. Pre-storage of register information in memory makes it possible to

transfer data over any required number of channels. Setting the CHNE bit to 1 makes it possible to

perform a number of transfers with a single activation.

Figure 8-2 shows a flowchart of DTC operation.

Start

Read DTC vector Next transfer

Read register information

Data transfer

Write register information

Clear an activation flag

CHNE=1

End

Yes

Transfer Counter= 0

or DISEL= 1

Clear DTCER

Interrupt exception

handling

Figure 8-2 Flowchart of DTC Operation

193

The DTC transfer mode can be normal mode, repeat mode, or block transfer mode.

The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the

transfer destination address. After each transfer, SAR and DAR are independently incremented,

decremented, or left fixed.

Table 8-2 outlines the functions of the DTC.

Table 8-2 DTC Functions

Address Registers

Transfer Mode Activation Source Transfer

Source Transfer

Destination

• Normal mode

 One transfer request transfers one

byte or one word

 Memory addresses are incremented

or decremented by 1 or 2

 Up to 65,536 transfers possible

• Repeat mode

 One transfer request transfers one

byte or one word

 Memory addresses are incremented

or decremented by 1 or 2

 After the specified number of

transfers (1 to 256), the initial state

resumes and operation continues

• Block transfer mode

 One transfer request transfers a block

of the specified size

 Block size is from 1 to 256 bytes or

words

 Up to 65,536 transfers possible

 A block area can be designated at

either the source or destination

• IRQ

• TPU TGI

• SCI TXI or RXI

• A/D converter ADI

• Motor control PWM

timer CMI

• HCAN RM0

(mail box 0)

• Software

24 bits 24 bits

194

8.3.2 Activation Sources

The DTC operates when activated by an interrupt or by a write to DTVECR by software. An

interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER

bit. An interrupt becomes a DTC activation source when the corresponding bit is set to 1, and a

CPU interrupt source when the bit is cleared to 0.

At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the

activation source or corresponding DTCER bit is cleared. Table 8-3 shows activation source and

DTCER clearance. The activation source flag, in the case of RXI0, for example, is the RDRF flag

of SCI0.

Table 8-3 Activation Source and DTCER Clearance

Activation Source

When the DISEL Bit Is 0 and

the Specified Number of

Transfers Have Not Ended

When the DISEL Bit Is 1, or when

the Specified Number of Transfers

Have Ended

Software activation The SWDTE bit is cleared to 0 The SWDTE bit remains set to 1

An interrupt is issued to the CPU

Interrupt activation The corresponding DTCER bit

remains set to 1

The activation source flag is

cleared to 0

The corresponding DTCER bit is cleared

to 0

The activation source flag remains set to 1

A request is issued to the CPU for the

activation source interrupt

Figure 8-3 shows a block diagram of activation source control. For details see section 5, Interrupt

Controller.

On-chip

supporting

module

IRQ interrupt

DTVECR

Selection circuit

Interrupt controller CPU

DTC

DTCER

Clear

controller

Select

Interrupt

request

Source flag cleared

Clear

Clear request

Interrupt mask

Figure 8-3 Block Diagram of DTC Activation Source Control

195

When an interrupt has been designated a DTC activation source, existing CPU mask level and

interrupt controller priorities have no effect. If there is more than one activation source at the same

time, the DTC operates in accordance with the default priorities.

8.3.3 DTC Vector Table

Figure 8-4 shows the correspondence between DTC vector addresses and register information.

Table 8-4 shows the correspondence between activation and vector addresses. When the DTC is

activated by software, the vector address is obtained from: H'0400 + (DTVECR[6:0] << 1) (where

<< 1 indicates a 1-bit left shift). For example, if DTVECR is H'10, the vector address is H'0420.

The DTC reads the start address of the register information from the vector address set for each

activation source, and then reads the register information from that start address. The register

information can be placed at predetermined addresses in the on-chip RAM. The start address of

the register information should be an integral multiple of four.

The configuration of the vector address is the same in both normal* and advanced modes, a 2-byte

unit being used in both cases. These two bytes specify the lower bits of the address in the on-chip

RAM.

Note: * Not available in the H8S/2646 Series.

start address Register information

Chain transfer

DTC vector

address

Figure 8-4 Correspondence between DTC Vector Address and Register Information

196

Table 8-4 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs

Interrupt Source

Origin of

Interrupt

Source Vector

Number Vector

Address DTCE*1Priority

Write to DTVECR Software DTVECR H'0400+

(DTVECR

[6:0]

<<1)

—High

IRQ0 External pin 16 H'0420 DTCEA7

IRQ1 17 H'0422 DTCEA6

IRQ2 18 H'0424 DTCEA5

IRQ3 19 H'0426 DTCEA4

IRQ4 20 H'0428 DTCEA3

IRQ5 21 H'042A DTCEA2

Reserved —22 to 27 H'042C to

H'0436 —

ADI (A/D conversion end) A/D 28 H'0438 DTCEB6

Reserved —29 to 31 H'043A to

H'043E —

TGI0A (GR0A compare match/

input capture) TPU

channel 0 32 H'0440 DTCEB5

TGI0B (GR0B compare match/

input capture) 33 H'0442 DTCEB4

TGI0C (GR0C compare match/

input capture) 34 H'0444 DTCEB3

TGI0D (GR0D compare match/

input capture) 35 H'0446 DTCEB2

Reserved —36 to 39 H'0448 to

H'044E —

TGI1A (GR1A compare match/

input capture) TPU

channel 1 40 H'0450 DTCEB1

TGI1B (GR1B compare match/

input capture) 41 H'0452 DTCEB0

TGI2A (GR2A compare match/

input capture) TPU

channel 2 44 H'0458 DTCEC7

TGI2B (GR2B compare match/

input capture) 45 H'045A DTCEC6 Low

197

Interrupt Source

Origin of

Interrupt

Source Vector

Number Vector

Address DTCE*1Priority

TGI3A (GR3A compare match/

input capture) TPU

channel 3 48 H'0460 DTCEC5 High

TGI3B (GR3B compare match/

input capture) 49 H'0462 DTCEC4

TGI3C (GR3C compare match/

input capture) 50 H'0464 DTCEC3

TGI3D (GR3D compare match/

input capture) 51 H'0466 DTCEC2

Reserved —52 to 55 H'0468 to

H'046E —

TGI4A (GR4A compare match/

input capture) TPU

channel 4 56 H'0470 DTCEC1

TGI4B (GR4B compare match/

input capture) 57 H'0472 DTCEC0

Reserved —58, 59 H'0474 to

H'0476 —

TGI5A (GR5A compare match/

input capture) TPU

channel 5 60 H'0478 DTCED5

TGI5B (GR5B compare match/

input capture) 61 H'047A DTCED4

Reserved —62 to 80 H'047C to

H'04A0 —

RXI0 (reception complete 0) SCI 81 H'04A2 DTCEE3

TXI0 (transmit data empty 0) channel 0 82 H'04A4 DTCEE2

Reserved —83, 84 H'04A6 to

H'04A8 —

RXI1 (reception complete 1) SCI 85 H'04AA DTCEE1

TXI1 (transmit data empty 1) channel 1 86 H'04AC DTCEE0

Reserved —87, 88 H'04AE to

H'04B0 —

RXI2 (reception complete 2)*2SCI 89 H'04B2 DTCEF7

TXI2 (transmit data empty 2) *2channel 2 90 H'04B4 DTCEF6

Reserved —91 to 103 H'04B6 to

H'04CE —Low

198

Interrupt Source

Origin of

Interrupt

Source Vector

Number Vector

Address DTCE*1Priority

CMI1 (PWCYR1 compare match) PWM 104 H'04D0 DTCEG7 High

CMI2 (PWCYR2 compare match) 105 H'04D2 DTCEG6

Reserved —106 to 108 H'04D4

H'04D8 —

RM0 (Mail box 0) HCAN0 109 H'04DA DTCEG2

Reserved —110 to 124 H'04DC

H'04FC —Low

Notes: *1 DTCE bits with no corresponding interrupt are reserved, and should be written with 0.

*2 These vectors are used in the H8S/2648, H8S/2648R, and H8S/2647. They are

reserved in the H8S/2646, H8S/2646R, and H8S/2645.

199

8.3.4 Location of Register Information in Address Space

Figure 8-5 shows how the register information should be located in the address space.

Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address

of the register information (contents of the vector address). In the case of chain transfer, register

information should be located in consecutive areas.

Locate the register information in the on-chip RAM (addresses: H'FFEBC0 to H'FFEFBF).

information

start address

Chain

transfer Register information

for 2nd transfer in

chain transfer

MRA SAR

MRB DAR

CRA CRB

4 bytes

Lower address

CRA CRB

MRA

0123

SAR

MRB DAR

Figure 8-5 Location of Register Information in Address Space

200

8.3.5 Normal Mode

In normal mode, one operation transfers one byte or one word of data.

From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a

CPU interrupt can be requested.

Table 8-5 lists the register information in normal mode and figure 8-6 shows memory mapping in

normal mode.

Table 8-5 Register Information in Normal Mode

Name Abbreviation Function

DTC source address register SAR Designates source address

DTC destination address register DAR Designates destination address

DTC transfer count register A CRA Designates transfer count

DTC transfer count register B CRB Not used

Transfer

SAR DAR

Figure 8-6 Memory Mapping in Normal Mode

201

8.3.6 Repeat Mode

In repeat mode, one operation transfers one byte or one word of data.

From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the

initial state of the transfer counter and the address register specified as the repeat area is restored,

and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and

therefore CPU interrupts cannot be requested when DISEL = 0.

Table 8-6 lists the register information in repeat mode and figure 8-7 shows memory mapping in

repeat mode.

Table 8-6 Register Information in Repeat Mode

Name Abbreviation Function

DTC source address register SAR Designates source address

DTC destination address register DAR Designates destination address

DTC transfer count register AH CRAH Holds number of transfers

DTC transfer count register AL CRAL Designates transfer count

DTC transfer count register B CRB Not used

Transfer

SAR or

DAR DAR or

SAR

Repeat area

Figure 8-7 Memory Mapping in Repeat Mode

202

8.3.7 Block Transfer Mode

In block transfer mode, one operation transfers one block of data. Either the transfer source or the

transfer destination is designated as a block area.

The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size

counter and the address register specified as the block area is restored. The other address register

is then incremented, decremented, or left fixed.

From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a

CPU interrupt is requested.

Table 8-7 lists the register information in block transfer mode and figure 8-8 shows memory

mapping in block transfer mode.

Table 8-7 Register Information in Block Transfer Mode

Name Abbreviation Function

DTC source address register SAR Designates source address

DTC destination address register DAR Designates destination address

DTC transfer count register AH CRAH Holds block size

DTC transfer count register AL CRAL Designates block size count

DTC transfer count register B CRB Transfer count

203

Transfer

SAR or

DAR DAR or

SAR

Block area

First block

Nth block

Figure 8-8 Memory Mapping in Block Transfer Mode

204

8.3.8 Chain Transfer

Setting the CHNE bit to 1 enables a number of data transfers to be performed consectutively in

response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data

transfers, can be set independently.

Figure 8-9 shows the memory map for chain transfer.

Source

Destination

DTC vector

address Register information

start address

CHNE = 1

CHNE = 0

Figure 8-9 Chain Transfer Memory Map

In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the

end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt

source flag for the activation source is not affected.

205

8.3.9 Operation Timing

Figures 8-10 to 8-12 show an example of DTC operation timing.

DTC activation

request

DTC

request

Address

Vector read

Transfer

information read Transfer

information write

Data transfer

Read Write

Figure 8-10 DTC Operation Timing (Example in Normal Mode or Repeat Mode)

Read Write Read Write

Data transfer

Transfer

information write

Transfer

information read

Vector read

TC activation

equest

TC request

ddress

Figure 8-11 DTC Operation Timing (Example of Block Transfer Mode,

with Block Size of 2)

206

Read Write Read Write

Address

DTC activation

request

DTC

request Data transfer Data transfer

Transfer

information

write

Transfer

information

write

Transfer

information

read

Transfer

information

read

Vector read

Figure 8-12 DTC Operation Timing (Example of Chain Transfer)

8.3.10 Number of DTC Execution States

Table 8-8 lists execution statuses for a single DTC data transfer, and table 8-9 shows the number

of states required for each execution status.

Table 8-8 DTC Execution Statuses

Mode Vector Read

Read/Write

JData Read

KData Write

Internal

Operations

Normal 1 6 1 1 3

Repeat 1 6 1 1 3

Block transfer 1 6 N N 3

N: Block size (initial setting of CRAH and CRAL)

207

Table 8-9 Number of States Required for Each Execution Status

Object to be Accessed

On-

Chip

RAM

On-

Chip

ROM On-Chip I/O

Registers External Devices

Bus width 32 16 8 16 8 8 16 16

Access states 11222323

Execution Vector read SI—1——4 6+2m 2 3+m

status Register

information

read/write

SJ1———————

Byte data read SK112223+m23+m

Word data read SK114246+2m 2 3+m

Byte data write SL112223+m23+m

Word data write SL114246+2m 2 3+m

Internal operation SM11111111

The number of execution states is calculated from the formula below. Note that Σ means the sum

of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,

plus 1).

Number of execution states = I · (SI +1) + Σ (J · SJ + K · SK + L · SL) + M · SM

For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,

and data is transferred from the on-chip ROM to an internal I/O register, the time required for the

DTC operation is 14 states. The time from activation to the end of the data write is 11 states.

208

8.3.11 Procedures for Using DTC

Activation by Interrupt: The procedure for using the DTC with interrupt activation is as follows:

[1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.

[2] Set the start address of the register information in the DTC vector address.

[3] Set the corresponding bit in DTCER to 1.

[4] Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC

is activated when an interrupt used as an activation source is generated.

[5] After the end of one data transfer, or after the specified number of data transfers have ended,

the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue

transferring data, set the DTCE bit to 1.

Activation by Software: The procedure for using the DTC with software activation is as follows:

[1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.

[2] Set the start address of the register information in the DTC vector address.

[3] Check that the SWDTE bit is 0.

[4] Write 1 to SWDTE bit and the vector number to DTVECR.

[5] Check the vector number written to DTVECR.

[6] After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not requested,

the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit

to 1. When the DISEL bit is 1, or after the specified number of data transfers have ended, the

SWDTE bit is held at 1 and a CPU interrupt is requested.

209

8.3.12 Examples of Use of the DTC

Normal Mode: An example is shown in which the DTC is used to receive 128 bytes of data via

the SCI.

[1] Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 =

1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have

any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the

SCI RDR address in SAR, the start address of the RAM area where the data will be received in

DAR, and 128 (H'0080) in CRA. CRB can be set to any value.

[2] Set the start address of the register information at the DTC vector address.

[3] Set the corresponding bit in DTCER to 1.

[4] Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception

complete (RXI) interrupt. Since the generation of a receive error during the SCI reception

operation will disable subsequent reception, the CPU should be enabled to accept receive error

interrupts.

[5] Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an

RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR

to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is

automatically cleared to 0.

[6] When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the

DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt

handling routine should perform wrap-up processing.

210

Chain Transfer: An example of DTC chain transfer is shown in which pulse output is performed

using the PPG. Chain transfer can be used to perform pulse output data transfer and PPG output

trigger cycle updating. Repeat mode transfer to the PPG’s NDR is performed in the first half of the

chain transfer, and normal mode transfer to the TPU’s TGR in the second half. This is because

clearing of the activation source and interrupt generation at the end of the specified number of

transfers are restricted to the second half of the chain transfer (transfer when CHNE = 0).

[1] Perform settings for transfer to the PPG’s NDR. Set MRA to source address incrementing

(SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0,

MD0 = 1), and word size (Sz = 1). Set the source side as a repeat area (DTS = 1). Set MRB to

chain mode (CHNE = 1, DISEL = 0). Set the data table start address in SAR, the NDRH

address in DAR, and the data table size in CRAH and CRAL. CRB can be set to any value.

[2] Perform settings for transfer to the TPU’s TGR. Set MRA to source address incrementing

(SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), normal mode (MD1 =

MD0 = 0), and word size (Sz = 1). Set the data table start address in SAR, the TGRA address

in DAR, and the data table size in CRA. CRB can be set to any value.

[3] Locate the TPU transfer register information consecutively after the NDR transfer register

information.

[4] Set the start address of the NDR transfer register information to the DTC vector address.

[5] Set the bit corresponding to TGIA in DTCER to 1.

[6] Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA

interrupt with TIER.

[7] Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and

NDER for which output is to be performed to 1. Using PCR, select the TPU compare match

to be used as the output trigger.

[8] Set the CST bit in TSTR to 1, and start the TCNT count operation.

[9] Each time a TGRA compare match occurs, the next output value is transferred to NDR and

the set value of the next output trigger period is transferred to TGRA. The activation source

TGFA flag is cleared.

[10] When the specified number of transfers are completed (the TPU transfer CRA value is 0), the

TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to

the CPU. Termination processing should be performed in the interrupt handling routine.

211

Software Activation: An example is shown in which the DTC is used to transfer a block of 128

bytes of data by means of software activation. The transfer source address is H'1000 and the

destination address is H'2000. The vector number is H'60, so the vector address is H'04C0.

[1] Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination

address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz =

0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE =

0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR,

and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB.

[2] Set the start address of the register information at the DTC vector address (H'04C0).

[3] Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated

by software.

[4] Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0.

[5] Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this

indicates that the write failed. This is presumably because an interrupt occurred between steps

3 and 4 and led to a different software activation. To activate this transfer, go back to step 3.

[6] If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred.

[7] After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear

the SWDTE bit to 0 and perform other wrap-up processing.

212

8.4 Interrupts

An interrupt request is issued to the CPU when the DTC finishes the specified number of data

transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation,

the interrupt set as the activation source is generated. These interrupts to the CPU are subject to

CPU mask level and interrupt controller priority level control.

In the case of activation by software, a software activated data transfer end interrupt (SWDTEND)

is generated.

When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers

have ended, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is

generated. The interrupt handling routine should clear the SWDTE bit to 0.

When the DTC is activated by software, an SWDTEND interrupt is not generated during a data

transfer wait or during data transfer even if the SWDTE bit is set to 1.

8.5 Usage Notes

Module Stop: When the MSTPA6 bit in MSTPCRA is set to 1, the DTC clock stops, and the

DTC enters the module stop state. However, 1 cannot be written in the MSTPA6 bit while the

DTC is operating.

On-Chip RAM: The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip

RAM. When the DTC is used, the RAME bit in SYSCR must not be cleared to 0.

DTCE Bit Setting: For DTCE bit setting, use bit manipulation instructions such as BSET and

BCLR. If all interrupts are masked, multiple activation sources can be set at one time by writing

data after executing a dummy read on the relevant register.

213

Section 9 I/O Ports

9.1 Overview

The H8S/2646 Series has 13 I/O ports (ports 1 to 3, 5 and A to F, H, J, K), and two input-only port

(ports 4 and 9).

Table 9-1 summarizes the port functions. The pins of each port also have other functions.

Each I/O port includes a data direction register (DDR) that controls input/output, a data register

(DR) that stores output data, and a port register (PORT) used to read the pin states. The input-only

ports do not have a DR or DDR register.

Ports A to E have a built-in pull-up MOS function, and in addition to DR and DDR, have a MOS

input pull-up control register (PCR) to control the on/off state of MOS input pull-up.

Ports 3, and A to F include an open-drain control register (ODR) that controls the on/off state of

the output buffer PMOS.

When ports A to F are used as the output pins for expanded bus control signals, they can drive one

TTL load plus a 50pF capacitance load. Ports other than A to F can drive one TTL load and a

30pF capacitance load. All I/O ports can drive Darlington transistors when set to output. Ports 1

and A to C can drive a LED (10 mA sink current), and some of the pins in ports A to E and F can

be used as LCD driver pins.

Port 1 pins P16 and P14, and port 3 pins P35 and P32 are Schmitt-trigger inputs.

See Appendix C, I/O Port Block Diagrams, for a block diagram of each port.

214

Table 9-1 (1) Port Functions (H8S/2646, H8S/2646R, H8S/2645)

Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7

Port 1 • 8-bit I/O

port

• Schmitt-

triggered

input

(P16, P14)

P17/PO15/TIOCB2

/TCLKD

P16/PO14/TIOCA2

/IRQ1

P15/PO13/TIOCB1

/TCLKC

P14/PO12/TIOCA1

/IRQ0

P13/PO11/TIOCD0

/TCLKB

P12/PO10/TIOCC0

/TCLKA

P11/PO9/TIOCB0

P10/PO8/TIOCA0

TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0,

TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2,

TIOCB2), PPG output pins (PO15 to PO8), and interrupt input

pins (IRQ0, IRQ1), and 8-bit I/O port

Port 2 • 8-bit I/O

port P27/TIOCB5

P26/TIOCA5

P25/TIOCB4

P24/TIOCA4

P23/TIOCD3

P22/TIOCC3

P21/TIOCB3

P20/TIOCA3

TPU I/O pins (TIOCB5, TIOCA5, TIOCB4, TIOCA4, TIOCD3,

TIOCC3, TIOCB3, TIOCA3) and 8-bit I/O port

Port 3 • 8-bit I/O

port P37

P36

P35/SCK1/IRQ5

P34/RxD1

P33/TxD1

P32/SCK0/IRQ4

P31/RxD0

P30/TxD0

SCI (channels 0, 1) I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1,

SCK1), interrupt input pins (IRQ4, IRQ5), and 8-bit I/O port

Port 4 • 8-bit input

port P47/AN7

P46/AN6

P45/AN5

R44/AN4

P43/AN3

P42/AN2

P41/AN1

P40/AN0

A/D converter analog input (AN7 to AN0) and 8-bit input port

215

Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7

Port 5 • 3-bit I/O

port P52

P51

P50

3-bit I/O port

Port 9 • 8-bit input

port P97

P96

P95

P94

P93/AN11

P92/AN10

P91/AN9

P90/AN8

A/D converter analog input (AN11 to AN8) and 8-bit input port

Port A • 8-bit I/O

port

• Built-in

MOS input

pull-up

• Open-drain

output

capability

PA7/A23/SEG24

PA6/A22/SEG23

PA5/A21/SEG22

PA4/A20/SEG21

PA3/A19/COM4

PA2/A18/COM3

PA1/A17/COM2

PA0/A16/COM1

LCD segment and common output (SEG21 to

SEG24, COM1 to COM4), address output (A23

to A16), and 8-bit I/O port

LCD segment

and common

output (SEG21

to SEG24,

COM1 to

COM4) and 8-

bit I/O port

Port B • 8-bit I/O

port

• Built-in

MOS input

pull-up

• Open-drain

output

capability

PB7/A15/SEG16

PB6/A14/SEG15

PB5/A13/SEG14

PB4/A12/SEG13

PB3/A11/SEG12

PB2/A10/SEG11

PB1/A9/SEG10

PB0/A8/SEG9

LCD segment output (SEG9 to SEG16),

address output (A15 to A8), and 8-bit I/O port LCD segment

output (SEG9

to SEG16) and

8-bit I/O port

Port C • 8-bit I/O

port

• Built-in

MOS input

pull-up

• Open-drain

output

capability

PC7/A7/SEG8

PC6/A6/SEG7

PC5/A5/SEG6

PC4/A4/SEG5

PC3/A3/SEG4

PC2/A2/SEG3

PC1/A1/SEG2

PC0/A0/SEG1

Address output (A7 to A0) LCD segment

output (SEG1

to SEG8),

address output

(A7 to A0),

and 8-bit I/O

port

LCD segment

output (SEG1

to SEG8) and

8-bit I/O port

216

Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7

Port D • 8-bit I/O

port

• Built-in

MOS input

pull-up

PD7/D15

PD6/D14

PD5/D13

PD4/D12

PD3/D11

PD2/D10

PD1/D9

PD0/D8

Data bus I/O 8-bit I/O port

Port E • 8-bit I/O

port

• Built-in

MOS input

pull-up

PE7/D7

PE6/D6

PE5/D5

PE4/D4

PE3/D3

PE2/D2

PE1/D1

PE0/D0

8-bit I/O port in 8-bit bus mode

Data bus I/O and 8-bit I/O port in 16-bit bus

mode

8-bit I/O port

Port F • 7-bit I/O

port PF7/φIf DDR = 0: input port

If DDR = 1: φ output

PF6/AS/SEG20

PF5/RD/SEG19

PF4/HWR/SEG18

LCD segment output (SEG18 to SEG20) and

bus control signals (AS, RD, HWR)LCD segment

output (SEG18

to SEG20) and

I/O port

PF3/LWR/ADTRG

/IRQ3 Bus control signal (LWR) and ADTRG, IRQ3

input Input port and

ADTRG, IRQ3

input

PF2/WAIT/SEG17 If WAITE = 0 (following reset): LCD segment

output (SEG17) and input port

If WAITE = 1: LCD segment output (SEG17)

and WAIT input

LCD segment

output

(SEG17) and

I/O port

PF0/IRQ2 IRQ2 input and I/O port

Port H • 8-bit I/O

port PH7/PWM1H

PH6/PWM1G

PH5/PWM1F

PH4/PWM1E

PH3/PWM1D

PH2/PWM1C

PH1/PWM1B

PH0/PWM1A

Motor control PWM timer (channel 1) output pins (PWM1A to

PWM1H) and 8-bit I/O port

217

Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7

Port J • 8-bit I/O

port PJ7/PWM2H

PJ6/PWM2G

PJ5/PWM2F

PJ4/PWM2E

PJ3/PWM2D

PJ2/PWM2C

PJ1/PWM2B

PJ0/PWM2A

Motor control PWM timer (channel 2) output pins (PWM2A to

PWM2H) and 8-bit I/O port

Port K • 2-bit I/O

port PK7

PK6 2-bit I/O port

Table 9-1 (2) Port Functions (H8S/2648, H8S/2648R, H8S/2647)

Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7

Port 1 • 8-bit I/O

port

• Schmitt-

triggered

input

(P16, P14)

P17/PO15/TIOCB2

/TCLKD

P16/PO14/TIOCA2

/IRQ1

P15/PO13/TIOCB1

/TCLKC

P14/PO12/TIOCA1

/IRQ0

P13/PO11/TIOCD0

/TCLKB

P12/PO10/TIOCC0

/TCLKA

P11/PO9/TIOCB0

P10/PO8/TIOCA0

TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0,

TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2,

TIOCB2), PPG output pins (PO15 to PO8), and interrupt input

pins (IRQ0, IRQ1), and 8-bit I/O port

Port 2 • 8-bit I/O

port P27/TIOCB5

P26/TIOCA5

P25/TIOCB4

P24/TIOCA4

P23/TIOCD3

P22/TIOCC3

P21/TIOCB3

P20/TIOCA3

TPU I/O pins (TIOCB5, TIOCA5, TIOCB4, TIOCA4, TIOCD3,

TIOCC3, TIOCB3, TIOCA3) and 8-bit I/O port

218

Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7

Port 3 • 8-bit I/O

port

• Open-drain

output

capability

P37

P36

P35/SCK1/IRQ5

P34/RxD1

P33/TxD1

P32/SCK0/IRQ4

P31/RxD0

P30/TxD0

SCI (channels 0, 1) I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1,

SCK1), interrupt input pins (IRQ4, IRQ5), and 8-bit I/O port

Port 4 • 8-bit input

port P47/AN7

P46/AN6

P45/AN5

P44/AN4

P43/AN3

P42/AN2

P41/AN1

P40/AN0

A/D converter analog input (AN7 to AN0) and 8-bit input port

Port 5 • 3-bit I/O

port P52/SCK2

P51/RxD2

P50/TxD2

SCI (channel 2) I/O pins (SCK2, RxD2, TxD2) and 3-bit I/O port

Port 9 • 8-bit input

port P97

P96

P95

P94

P93/AN11

P92/AN10

P91/AN9

P90/AN8

A/D converter analog input (AN11 to AN8) and 8-bit input port

Port A • 8-bit I/O

port

• Built-in

MOS input

pull-up

• Open-drain

output

capability

PA7/A23/SEG40

PA6/A22/SEG39

PA5/A21/SEG38

PA4/A20/SEG37

PA3/A19/COM4

PA2/A18/COM3

PA1/A17/COM2

PA0/A16/COM1

LCD segment and common output (SEG37 to

SEG40, COM1 to COM4), address output (A23

to A16), and 8-bit I/O port

LCD segment

and common

output (SEG37

to SEG40,

COM1 to

COM4) and 8-

bit I/O port

219

Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7

Port B • 8-bit I/O

port

• Built-in

MOS input

pull-up

• Open-drain

output

capability

PB7/A15/SEG32

PB6/A14/SEG31

PB5/A13/SEG30

PB4/A12/SEG29

PB3/A11/SEG28

PB2/A10/SEG27

PB1/A9/SEG26

PB0/A8/SEG25

LCD segment output (SEG25 to SEG32),

address output (A15 to A8), and 8-bit I/O port LCD segment

output (SEG25

to SEG32) and

8-bit I/O port

Port C • 8-bit I/O

port

• Built-in

MOS input

pull-up

• Open-drain

output

capability

PC7/A7/SEG24

PC6/A6/SEG23

PC5/A5/SEG22

PC4/A4/SEG21

PC3/A3/SEG20

PC2/A2/SEG19

PC1/A1/SEG18

PC0/A0/SEG17

Address output (A7 to A0) LCD segment

output (SEG17

to SEG24),

address output

(A7 to A0),

and 8-bit I/O

port

LCD segment

output (SEG17

to SEG24) and

8-bit I/O port

Port D • 8-bit I/O

port

• Built-in

MOS input

pull-up

PD7 /D15/SEG16

PD6/D14/SEG15

PD5/D13/SEG14

PD4/D12/SEG13

PD3/D11/SEG12

PD2/D10/SEG11

PD1/D9/SEG10

PD0/D8/SEG9

Data bus I/O LCD segment

output (SEG9

to SEG16) and

data bus I/O

LCD segment

output (SEG17

to SEG24) and

8-bit I/O port

Port E • 8-bit I/O

port

• Built-in

MOS input

pull-up

PE7/D7/SEG8

PE6/D6/SEG7

PE5/D5/SEG6

PE4/D4/SEG5

PE3/D3/SEG4

PE2/D2/SEG3

PE1/D1/SEG2

PE0/D0/SEG1

LCD segment output (SEG1 to SEG8) and I/O

port in 8-bit bus mode

LCD segment output (SEG1 to SEG8), data

bus I/O port, and I/O port in 16-bit bus mode

LCD segment

output (SEG1

to SEG8) and

8-bit I/O port

220

Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7

Port F • 7-bit I/O

port PF7/φIf DDR = 0: input port

If DDR = 1: φ output

PF6/AS/SEG36

PF5/RD/SEG35

PF4/HWR/SEG34

LCD segment output (SEG34 to SEG36) and

bus control signals (AS, RD, HWR)LCD segment

output (SEG34

to SEG36) and

I/O port

PF3/LWR/ADTRG

/IRQ3 Bus control signal (LWR) and ADTRG, IRQ3

input I/O port and

ADTRG, IRQ3

input

PF2/WAIT/SEG33 If WAITE = 0, BREQUE = 0 (following reset):

LCD segment output (SEG33) and I/O port

If WAITE = 1, BREQUE = 0: LCD segment

output and WAIT input

LCD segment

output

(SEG33) and

I/O port

PF0/IRQ2 IRQ2 input and I/O port

Port H • 8-bit I/O

port PH7/PWM1H

PH6/PWM1G

PH5/PWM1F

PH4/PWM1E

PH3/PWM1D

PH2/PWM1C

PH1/PWM1B

PH0/PWM1A

PWM (channel 1) output and 8-bit I/O port

Port J • 8-bit I/O

port PJ7/PWM2H

PJ6/PWM2G

PJ5/PWM2F

PJ4/PWM2E

PJ3/PWM2D

PJ2/PWM2C

PJ1/PWM2B

PJ0/PWM2A

PWM (channel 2) output and 8-bit I/O port

Port K • 2-bit I/O

port PK7

PK6 2-bit I/O port

221

9.2 Port 1

9.2.1 Overview

Port 1 is an 8-bit I/O port. Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O

pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1,

TIOCB1, TIOCA2, and TIOCB2), and external interrupt pins (IRQ0 and IRQ1). Port 1 pin

functions change according to the operating mode.

Figure 9-1 shows the port 1 pin configuration.

P17 (I/O) / PO15 (output) / TIOCB2 (I/O) / TCLKD (input)

P16 (I/O) / PO14 (output) / TIOCA2 (I/O) / IRQ1 (input)

P15 (I/O) / PO13 (output) / TIOCB1 (I/O) / TCLKC (input)

P14 (I/O) / PO12 (output) / TIOCA1 (I/O) / IRQ0 (input)

P13 (I/O) / PO11 (output) / TIOCD0 (I/O) / TCLKB (input)

P12 (I/O) / PO10 (output) / TIOCC0 (I/O) / TCLKA (input)

P11 (I/O) / PO9 (output) / TIOCB0 (I/O)

P10 (I/O) / PO8 (output) / TIOCA0 (I/O)

Port 1

Figure 9-1 Port 1 Pin Functions

222

9.2.2 Register Configuration

Table 9-2 shows the port 1 register configuration.

Table 9-2 Port 1 Registers

Name Abbreviation R/W Initial Value Address*

Port 1 data direction register P1DDR W H'00 H'FE30

Port 1 data register P1DR R/W H'00 H'FF00

Port 1 register PORT1 R Undefined H'FFB0

Note: * Lower 16 bits of the address.

Port 1 Data Direction Register (P1DDR)

Bit:76543210

P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR

Initial value : 0 0 0 0 0 0 0 0

R/W:WWWWWWWW

P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port 1. P1DDR cannot be read; if it is, an undefined value will be read.

Setting a P1DDR bit to 1 makes the corresponding port 1 pin an output pin, while clearing the bit

to 0 makes the pin an input pin.

P1DDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode.

Port 1 Data Register (P1DR)

Bit:76543210

P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

P1DR is an 8-bit readable/writable register that stores output data for the port 1 pins (P17 to P10).

P1DR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode.

223

Port 1 Register (PORT1)

Bit:76543210

P17 P16 P15 P14 P13 P12 P11 P10

Initial value : —*—*—*—*—*—*—*—*

R/W:RRRRRRRR

Note: *Determined by state of pins P17 to P10.

PORT1 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of

output data for the port 1 pins (P17 to P10) must always be performed on P1DR.

If a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read. If a port 1

read is performed while P1DDR bits are cleared to 0, the pin states are read.

After a reset and in hardware standby mode, PORT1 contents are determined by the pin states, as

P1DDR and P1DR are initialized. PORT1 retains its prior state in software standby mode.

224

9.2.3 Pin Functions

Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O pins (TCLKA, TCLKB,

TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and

TIOCB2), and external interrupt input pins (IRQ0 and IRQ1). Port 1 pin functions are shown in

table 9-3.

Table 9-3 Port 1 Pin Functions

Pin Selection Method and Pin Functions

P17/PO15/

TIOCB2/

TCLKD

The pin function is switched as shown below according to the combination of

the TPU channel 2 setting (by bits MD3 to MD0 in TMDR2, bits IOB3 to IOB0

in TIOR2, and bits CCLR1 and CCLR0 in TCR2), bits TPSC2 to TPSC0 in

TCR0 and TCR5, bit NDER15 in NDERH, and bit P17DDR.

TPU Channel

2 Setting Table Below (1) Table Below (2)

P17DDR — 0 1 1

NDER15 — — 0 1

Pin function TIOCB2 output P17

input P17

output PO15

output

TIOCB2 input *1

TCLKD input *2

Notes: *1 TIOCB2 input when MD3 to MD0 = B'0000 or B'01xx, and IOB3 =

*2 TCLKD input when the setting for either TCR0 or TCR5 is: TPSC2

to TPSC0 = B'111.

TCLKD input when channels 2 and 4 are set to phase counting

mode.

TPU Channel

2 Setting (2) (1) (2) (2) (1) (2)

MD3 to MD0 B'0000, B'01xx B'0010 B'0011

IOB3 to IOB0 B'0000

B'0100

B'1xxx

B'0001 to

B'0011

B'0101 to

B'0111

— B'xx00 Other than B'xx00

CCLR1,

CCLR0 — — — — Other

than B'10 B'10

Output

function — Output

compare

output

— — PWM

mode 2

output

—

x: Don’t care

225

Pin Selection Method and Pin Functions

P16/PO14/

TIOCA2/

IRQ1

The pin function is switched as shown below according to the combination of

the TPU channel 2 setting (by bits MD3 to MD0 in TMDR2, bits IOA3 to IOA0

in TIOR2, and bits CCLR1 and CCLR0 in TCR2), bit NDER14 in NDERH, and

bit P16DDR.

TPU Channel

2 Setting Table Below (1) Table Below (2)

P16DDR — 0 1 1

NDER14 — — 0 1

Pin function TIOCA2 output P16

input P16

output PO14 output

TIOCA2 input *1

IRQ1 input

TPU Channel

2 Setting (2) (1) (2) (1) (1) (2)

MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011

IOA3 to IOA0 B'0000

B'0100

B'1xxx

B'0001 to

B'0011

B'0101 to

B'0111

B'xx00 Other than B'xx00

CCLR1,

CCLR0 — — — — Other

than B'01 B'01

Output

function — Output

compare

output

— PWM

mode 1

output *2

PWM

mode 2

output

—

x: Don’t care

Notes: *1 TIOCA2 input when MD3 to MD0 = B'0000 or B'01xx, and IOA3 =

*2 TIOCB2 output is disabled.

226

Pin Selection Method and Pin Functions

P15/PO13/

TIOCB1/TCLKC The pin function is switched as shown below according to the combination of

the TPU channel 1 setting (by bits MD3 to MD0 in TMDR1, bits IOB3 to IOB0

in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bits TPSC2 to TPSC0 in

TCR0, TCR2, TCR4, and TCR5, bit NDER13 in NDERH, and bit P15DDR.

TPU Channel

1 Setting Table Below (1) Table Below (2)

P15DDR — 0 1 1

NDER13 — — 0 1

Pin function TIOCB1 output P15

input P15

output PO13

output

TIOCB1 input *1

TCLKC input *2

Notes: *1 TIOCB1 input when MD3 to MD0 = B'0000 or B'01xx, and IOB3

to IOB0 = B'10xx.

*2 TCLKC input when the setting for either TCR0 or TCR2 is: TPSC2

to TPSC0 = B'110; or when the setting for either TCR4 or TCR5 is

TPSC2 to TPSC0 = B'101.

TCLKC input when channels 2 and 4 are set to phase counting

mode.

TPU Channel

1 Setting (2) (1) (2) (2) (1) (2)

MD3 to MD0 B'0000, B'01xx B'0010 B'0011

IOB3 to IOB0 B'0000

B'0100

B'1xxx

B'0001 to

B'0011

B'0101 to

B'0111

— B'xx00 Other than B'xx00

CCLR1,

CCLR0 — — — — Other

than

B'10

Output

function — Output

compare

output

— — PWM

mode 2

output

—

x: Don’t care

227

Pin Selection Method and Pin Functions

P14/PO12/

TIOCA1/IRQ0 The pin function is switched as shown below according to the combination of

the TPU channel 1 setting (by bits MD3 to MD0 in TMDR1, bits IOA3 to IOA0

in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bit NDER12 in NDERH, and

bit P14DDR.

TPU Channel

1 Setting Table Below (1) Table Below (2)

P14DDR — 0 1 1

NDER12 — — 0 1

Pin function TIOCA1 output P14

input P14

output PO12

output

TIOCA1 input *1

IRQ0 input

TPU Channel

1 Setting (2) (1) (2) (1) (1) (2)

MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011

IOA3 to IOA0 B'0000

B'0100

B'1xxx

B'0001 to

B'0011

B'0101 to

B'0111

B'xx00 Other

than

B'xx00

Other than B'xx00

CCLR1,

CCLR0 — — — — Other

than B'01 B'01

Output

function — Output

compare

output

— PWM

mode 1

output*2

PWM

mode 2

output

—

x: Don't care

Notes: *1 TIOCA1 input when MD3 to MD0 = B'0000 or B'01xx, and IOA3 to

IOA0 = B'10xx.

*2 TIOCB1 output is disabled.

228

Pin Selection Method and Pin Functions

P13/PO11/

TIOCD0/TCLKB The pin function is switched as shown below according to the combination of

the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in

TMDR0, bits IOD3 to IOD0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0),

bits TPSC2 to TPSC0 in TCR0 to TCR2, bit NDER11 in NDERH, and bit

P13DDR.

TPU Channel

0 Setting Table

Below (1) Table Below (2)

P13DDR — 0 1 1

NDER11 — — 0 1

Pin function TIOCD0 output P13 input P13 output PO11 output

TIOCD0 input *1

TCLKB input *2

Notes: *1 TIOCD0 input when MD3 to MD0 = B'0000, and IOD3 to IOD0 =

B'10xx.

*2 TCLKB input when the setting for TCR0 to TCR2 is: TPSC2 to

TPSC0 = B'101.

TCLKB input when channels 1 and 5 are set to phase counting

mode.

TPU Channel

0 Setting (2) (1) (2) (2) (1) (2)

MD3 to MD0 B'0000 B'0010 B'0011

IOD3 to IOD0 B'0000

B'0100

B'1xxx

B'0001 to

B'0011

B'0101 to

B'0111

— B'xx00 Other than B'xx00

CCLR2 to

CCLR0 — — — — Other

than

B'110

Output

function — Output

compare

output

— — PWM

mode 2

output

—

x: Don’t care

229

Pin Selection Method and Pin Functions

P12/PO10/

TIOCC0/TCLKA The pin function is switched as shown below according to the combination of

the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in

TMDR0, bits IOC3 to IOC0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0),

bits TPSC2 to TPSC0 in TCR0 to TCR5, bit NDER10 in NDERH, and bit

P12DDR.

TPU Channel

0 Setting Table

Below (1) Table Below (2)

P12DDR — 0 1 1

NDER10 — — 0 1

Pin function TIOCC0

output P12 input P12 output PO10 output

TIOCC0 input *1

TCLKA input *2

TPU Channel

0 Setting (2) (1) (2) (1) (1) (2)

MD3 to MD0 B'0000 B'001x B'0010 B'0011

IOC3 to IOC0 B'0000

B'0100

B'1xxx

B'0001 to

B'0011

B'0101 to

B'0111

B'xx00 Other than B'xx00

CCLR2 to

CCLR0 — — — — Other

than

B'101

Output

function — Output

compare

output

— PWM

mode 1

output*3

PWM

mode 2

output

—

x: Don’t care

Notes: *1 TIOCC0 input when MD3 to MD0 = B'0000, and IOC3 to IOC0 =

B'10xx.

*2 TCLKA input when the setting for TCR0 to TCR5 is: TPSC2 to

TPSC0 = B'100.

TCLKA input when channels 1 and 5 are set to phase counting

mode.

*3 TIOCD0 output is disabled.

When BFA = 1 or BFB = 1 in TMDR0, output is disabled and

setting (2) applies.

230

Pin Selection Method and Pin Functions

P11/PO9/TIOCB0 The pin function is switched as shown below according to the combination of

the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in

TMDR0, and bits IOB3 to IOB0 in TIOR0H), bit NDER9 in NDERH, and bit

P11DDR.

TPU Channel

0 Setting Table

Below (1) Table Below (2)

P11DDR — 0 1 1

NDER9 — — 0 1

Pin function TIOCB0

output P11

input P11

output PO9

output

TIOCB0 input *

Note: *TIOCB0 input when MD3 to MD0 = B'0000, and IOB3 to IOB0 =

B'10xx.

TPU Channel

0 Setting (2) (1) (2) (2) (1) (2)

MD3 to MD0 B'0000 B'0010 B'0011

IOB3 to IOB0 B'0000

B'0100

B'1xxx

B'0001 to

B'0011

B'0101 to

B'0111

— B'xx00 Other than B'xx00

CCLR2 to

CCLR0 — — — — Other

than

B'010

Output

function — Output

compare

output

— — PWM

mode 2

output

—

x: Don’t care

231

Pin Selection Method and Pin Functions

P10/PO8/TIOCA0 The pin function is switched as shown below according to the combination of

the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in

TMDR0, bits IOA3 to IOA0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0), bit

NDER8 in NDERH, SAE0 bit in DMABCRH, and bit P10DDR.

TPU Channel

0 Setting Table

Below (1) Table Below (2)

P10DDR — 0 1 1

NDER8 — — 0 1

Pin function TIOCA0

output P10

input P10

output PO8

output

TIOCA0 input *1

TPU Channel

0 Setting (2) (1) (2) (1) (1) (2)

MD3 to MD0 B'0000 B'001x B'0010 B'0011

IOA3 to IOA0 B'0000

B'0100

B'1xxx

B'0001 to

B'0011

B'0101 to

B'0111

B'xx00 Other than B'xx00

CCLR2 to

CCLR0 — — — — Other

than

B'001

Output

function — Output

compare

output

— PWM

mode 1

output*2

PWM

mode 2

output

—

x: Don’t care

Notes: *1 TIOCA0 input when MD3 to MD0 = B'0000, and IOA3 to IOA0 =

B'10xx.

*2 TIOCB0 output is disabled.

232

9.3 Port 2

9.3.1 Overview

Port 2 is an 8-bit I/O port. Port 2 also functions as TPU I/O pins (TIOCB5, TIOCA5, TIOCB4,

TIOCA4, TIOCD3, TIOCC3, TIOCB3, TIOCA3). The pin functions of port 2 change with the

operating mode.

Figure 9-2 shows the pin functions for port 2.

P27

P26

P25

P24

P23

P22

P21

P20

Port 2

(I/O) / TIOCB5 (I/O)

(I/O) / TIOCA5 (I/O)

(I/O) / TIOCB4 (I/O)

(I/O) / TIOCA4 (I/O)

(I/O) / TIOCD3 (I/O)

(I/O) / TIOCC3 (I/O)

(I/O) / TIOCB3 (I/O)

(I/O) / TIOCA3 (I/O)

Port 2 pins

Figure 9-2 Port 2 Pin Functions

9.3.2 Register Configuration

Table 9-4 shows the configuration of port 3 registers.

Table 9-4 Port 2 Register Configuration

Name Abbreviation R/W Initial Value Address*

Port 2 data direction register P2DDR W H'00 H'FE31

Port 2 data register P2DR R/W H'00 H'FF01

Port 2 register PORT2 R Undefined H'FFB1

Note: *Lower 16 bits of the address.

233

Port 2 Data Direction Register (P2DDR)

Bit:76543210

P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR

Initial value : 0 0 0 0 0 0 0 0

R/W:WWWWWWWW

P2DDR is an 8-bit write-only register that specifies whether individual bits are input or output for

each of the pins in port 2. It is not possible to read it. An undefined value is returned if an attempt

is made to read it.

Setting one of the bits of P2DDR to 1 sets the corresponding pin in port 2 to output, and clearing

the bit to 0 sets the corresponding pin to input.

P2DDR is initialized to H'00 if a reset occurs and in the hardware standby mode. The previous

values are retained by P2DDR in the software standby mode.

Port 2 Data Register (P2DR)

Bit:76543210

P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

P2DR is an 8-bit readable/writable register that stores output data for the port 2 pins (P27 to P20).

P2DR is initialized to H'00 if a reset occurs and in the hardware standby mode. The previous

values are retained in the software standby mode.

Port 2 Register (PORT2)

Bit:76543210

P27 P26 P25 P24 P23 P22 P21 P20

Initial value : —*—*—*—*—*—*—*—*

R/W:RRRRRRRR

Note: *Determined by state of pins P27 to P20.

PORT2 is an 8-bit read-only register. It is not possible to write to it. It reflects the states of the

pins. Always write output data from the port 2 pins (P27 to P20) to P2DR.

If P2DDR is set to 1, the value of P2DR is returned when port 2 is read. If P2DDR is cleared to 0,

the pin states are returned when port 2 is read.

234

P2DDR and P2DR are initialized if a reset occurs and in the hardware standby mode, so the

content of PORT2 is determined by the pin states. The previous states are retained in the software

standby mode.

9.3.3 Pin Functions

The port 2 pins also function as TPU I/O pins (TIOCB5, TIOCA5, TIOCB4, TIOCA4, TIOCD3,

TIOCC3, TIOCB3, TIOCA3). The pin functions of port 2 change with the operating mode.

Table 9-5 lists the pin functions for port 2.

Table 9-5 Port 2 Pin Functions

Pin Selection Method and Pin Functions

P27/TIOCB5 Switches as follows according to the combinations of the TPU channel 5

setting made using bits MD3 to MD0 of TMDR5, bits IOB3 to IOB0 of TIOR5,

and bits CCLR1 and CCLR0 of TCR5, as well as the P27DDR bit.

TPU Channel

5 Setting Table Below (1) Table Below (2)

P27DDR —01

Pin function TIOCB5 output P27 input P27 output

TIOCB5 input *

Note: * TIOCB5 input if MD3 to MD0 = 0, B'0000, B'01xx, and IOB = 1.

TPU Channel

5 Setting (2) (1) (2) (2) (1) (2)

MD3 to MD0 B'0000, B'01xx B'0010 B'0011

IOB3 to IOB0 B'0000

B'0100

B'1xxx

B'0001 to

B'0011

B'0101 to

B'0111

—B'xx00 Other than B'xx00

CCLR1,

CCLR0 ————Other

than B'10 B'10

Output

function —Output

compare

output

——PWM

mode 2

output

—

235

Pin Selection Method and Pin Functions

P26/TIOCA5 Switches as follows according to the combinations of the TPU channel 5

setting made using bits MD3 to MD0 of TMDR5, bits IOA3 to IOA0 of TIOR5,

and bits CCLR1 and CCLR0 of TCR5, as well as the P26DDR bit.

TPU Channel

5 Setting Table Below (1) Table Below (2)

P26DDR —01

Pin function TIOCA5 output P26 input*P26 output

TIOCA5 input*

TPU Channel

5 Setting (2) (1) (2) (1) (1) (2)

MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011

IOA3 to IOA0 B'0000

B'0100

B'1xxx

B'0001 to

B'0011

B'0101 to

B'0111

B'xx00 Other than B'xx00

CCLR1,

CCLR0 ————Other

than B'01 B'01

Output

function —Output

compare

output

—PWM

mode 1

output *

PWM

mode 2

output

—

Note: * TIOCB5 output prohibited.

236

Pin Selection Method and Pin Functions

P25/TIOCB4 Switches as follows according to the combinations of the TPU channel 4

setting made using bits MD3 to MD0 of TMDR4, bits IOB3 to IOB0 of TIOR4,

and bits CCR1 and CCR0 of TCR4, as well as the P25DDR bit.

TPU Channel

4 Setting Table Below (1) Table Below (2)

P25DDR —01

Pin function TIOCB4 output P25 input P25 output

TIOCB4 input

TPU Channel

4 Setting (2) (1) (2) (2) (1) (2)

MD3 to MD0 B'0000, B'01xx B'0010 B'0011

IOB3 to IOB0 B'0000

B'0100

B'1xxx

B'0001 to

B'0011

B'0101 to

B'0111

—B'xx00 Other than B'xx00

CCLR1,

CCLR0 ————Other

than

B'10

Output

function —Output

compare

output

——PWM

mode 2

output

—

237

Pin Selection Method and Pin Functions

P24/TIOCA4 Switches as follows according to the combinations of the TPU channel 4

setting made using bits MD3 to MD0 of TMDR4, bits IOA3 to IOA0 of TIOR4,

and bits CCR1 and CCR0 of TCR4, as well as the P24DDR bit.

TPU Channel

4 Setting Table Below (1) Table Below (2)

P24DDR —01

Pin function TIOCA4 output P24 input*P24 output

TIOCA4 input*

TPU Channel

4 Setting (2) (1) (2) (1) (1) (2)

MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011

IOA3 to IOA0 B'0000

B'0100

B'1xxx

B'0001 to

B'0011

B'0101 to

B'0111

B'xx00 Other

than

B'xx00

Other than B'xx00

CCLR1,

CCLR0 ————Other

than B'01 B'01

Output

function —Output

compare

output

—PWM

mode 1

output*

PWM

mode 2

output

—

Note: * TIOCB4 output prohibited.

238

Pin Selection Method and Pin Functions

P23/TIOCD3 Switches as follows according to the combinations of the TPU channel 3

setting made using bits MD3 to MD0 of TMDR3, bits IOD3 to IOD0 of TIOR3L,

and bits CCLR2 to CCLR0 of TCR3, as well as the P23DDR bit.

TPU Channel

3 Setting Table Below (1) Table Below (2)

P23DDR —01

Pin function TIOCD3 output P23 input P23 output

TIOCD3 input

TPU Channel

3 Setting (2) (1) (2) (2) (1) (2)

MD3 to MD0 B'0000 B'001x B'0010 B'0011

IOD3 to IOD0 B'0000

B'0100

B'1xxx

B'0001 to

B'0011

B'0101 to

B'0111

—Other

than

B'xx00

Other than B'xx00

CCLR2 to

CCLR0 ————Other

than

B'110

Output

function —Output

compare

output

—PWM

mode 1

output*

PWM

mode 2

output

—

Note: * TIOCD3 output prohibited.

239

Pin Selection Method and Pin Functions

P22/TIOCC3 Switches as follows according to the combinations of the TPU channel 3

setting made using bits MD3 to MD0 of TMDR3, bits IOC3 to IOC0 of TIOR3L,

and bits CCR2 to CCR0 of TCR3, as well as the P22DDR bit.

TPU Channel

3 Setting Table Below (1) Table Below (2)

P22DDR —01

Pin function TIOCC3 output P22 input P22 output

TIOCC3 input

TPU Channel

3 Setting (2) (1) (2) (1) (1) (2)

MD3 to MD0 B'0000 B'001x B'0010 B'0011

IOC3 to IOC0 B'0000

B'0100

B'1xxx

B'0001 to

B'0011

B'0101 to

B'0111

B'xx00 Other than B'xx00

CCLR2 to

CCLR0 ————Other

than

B'101

Output

function —Output

compare

output

—PWM

mode 1

output*

PWM

mode 2

output

—

Note: * TIOCD3 output prohibited.

240

Pin Selection Method and Pin Functions

P21/TIOCB3 Switches as follows according to the combinations of the TPU channel 3

setting made using bits MD3 to MD0 of TMDR3, bits IOB3 to IOB0 of TIOR3L,

and bits CCR2 to CCR0 of TCR3, as well as the P21DDR bit.

TPU Channel

3 Setting Table Below (1) Table Below (2)

P21DDR —01

Pin function TIOCB3 output P21 input P21 output

TIOCB3 input

TPU Channel

3 Setting (2) (1) (2) (2) (1) (2)

MD3 to MD0 B'0000 B'0010 B'0011

IOB3 to IOB0 B'0000

B'0100

B'1xxx

B'0001 to

B'0011

B'0101 to

B'0111

—B'xx00 Other than B'xx00

CCLR2 to

CCLR0 ————Other

than

B'010

Output

function —Output

compare

output

——PWM

mode 2

output

—

241

Pin Selection Method and Pin Functions

P20/TIOCA3 Switches as follows according to the combinations of the TPU channel 3

setting made using bits MD3 to MD0 of TMDR3, bits IOA3 to IOA0 of TIOR3L,

and bits CCR2 to CCR0 of TCR3, as well as the P20DDR bit.

TPU Channel

3 Setting Table Below (1) Table Below (2)

P20DDR —01

Pin function TIOCA3 output P20 input P20 output

TIOCA3 input

TPU Channel

0 Setting (2) (1) (2) (1) (1) (2)

MD3 to MD0 B'0000 B'001x B'0010 B'0011

IOA3 to IOA0 B'0000

B'0100

B'1xxx

B'0001 to

B'0011

B'0101 to

B'0111

B'xx00 Other than B'xx00

CCLR2 to

CCLR0 ————Other

than

B'001

Output

function —Output

compare

output

—PWM

mode 1

output*

PWM

mode 2

output

—

Note: * TIOCB3 output prohibited.

242

9.4 Port 3

9.4.1 Overview

Port 3 is an 8-bit I/O port. Port 3 is a multi-purpose port for SCI I/O pins (TxD0, RxD0, SCK0,

TxD1, RxD1, SCK1), and external interrupt input pins (IRQ4, IRQ5). All of the port 3 pin

functions have the same operating mode. The configuration for each of the port 3 pins is shown in

figure. 9-3.

Port 3 pins

P37

P36

P35

P34

P33

P32

P31

P30

Port 3

(I/O)

(I/O) / SCK1 (I/O) / IRQ5 (input)

(I/O) / RxD1 (input)

(I/O) / TxD1 (output)

(I/O) / SCK0 (I/O) / IRQ4 (input)

(I/O) / RxD0 (input)

(I/O) / TxD0 (output)

Figure 9-3 Port 3 Pin Functions

9.4.2 Register Configuration

Table 9-6 shows the configuration of port 3 registers.

Table 9-6 Port 3 Register Configuration

Name Abbreviation R/W Initial Value Address*

Port 3 data direction register P3DDR W H'00 H'FE32

Port 3 data register P3DR R/W H'00 H'FF02

Port 3 register PORT3 R Undefined H'FFB2

Port 3 open drain control register P3ODR R/W H'00 H'FE46

Notes: *Lower 16 bits of the address.

243

Port 3 Data Direction Register (P3DDR)

P37DDR

Bit

Initial value

Read/Write

P36DDR

P35DDR

P34DDR

P33DDR

P32DDR

P31DDR

P30DDR

P3DDR is an 8-bit write-dedicated register, which specifies the I/O for each port 3 pin by bit.

Read is disenabled. If a read is carried out, undefined values are read out.

By setting P3DDR to 1, the corresponding port 3 pins become output, and be clearing to 0 they

become input.

P3DDR is initialized to H'00 by a reset and in hardware standby mode. The previous state is

maintained in software standby mode. SCI is initialized, so the pin state is determined by the

specification of P3DDR and P3DR.

Port 3 Data Register (P3DR)

P37DR

R/W

Bit

Initial value

Read/Write

P36DR

R/W

P35DR

R/W

P34DR

R/W

P33DR

R/W

P32DR

R/W

P31DR

R/W

P30DR

R/W

P3DR is an 8-bit readable/writable register, which stores the output data of port 3 pins (P35 to

P30).

P3DR is initialized to H'00 by a reset and in hardware standby mode. The previous state is

maintained in software standby mode.

244

Port 3 Register (PORT3)

P37

—*

Bit

Initial value

Read/Write

P36

—*

P35

—*

P34

—*

P33

—*

P32

—*

P31

—*

P30

—*

Note: *Determined by the state of pins P37 to P30.

PORT3 is an 8-bit read-dedicated register, which reflects the state of pins. Write is disenabled.

Always carry out writing off output data of port 3 pins (P37 to P30) to P3DR without fail.

When P3DDR is set to 1, if port 3 is read, the values of P3DR are read. When P3DDR is cleared to

0, if port 3 is read, the states of pins are read out.

P3DDR and P3DR are initialized by a reset and in hardware standby mode, so PORT3 is

determined by the state of the pins. The previous state is maintained in software standby mode.

Port 3 Open Drain Control Register (P3ODR)

P37ODR

R/W

Bit

Initial value

Read/Write

P36ODR

R/W

P35ODR

R/W

P34ODR

R/W

P33ODR

R/W

P32ODR

R/W

P31ODR

R/W

P30ODR

R/W

P3ODR is an 8-bit readable/writable register, which controls the on/off of port 3 pins (P37 to P30).

By setting P3ODR to 1, the port 3 pins become an open drain output, and when cleared to 0 they

become CMOS output.

P3ODR is initialized to H'00 by a reset and in hardware standby mode. The previous state is

maintained in software standby mode.

245

9.4.3 Pin Functions

The port 3 pins also function as SCI I/O input pins (TxD0, RxD0, SCK0, TxD1, RxD1, and

SCK1) and as external interrupt input pins (IRQ4 and IRQ5). The functions of port 3 pins are

shown in Table 9-7.

Table 9-7 Port 3 Pin Functions

Pin Selection Method and Pin Functions

P37 Switches as follows according to the setting of the P37DDR bit.

P37DDR 0 1

Pin function P37 input pin P37 output pin*

Note: * When P37ODR = 1, it becomes NMOS open drain output.

P36 Switches as follows according to the setting of the P36DDR bit.

P36DDR 0 1

Pin function P36 input pin P36 output pin*

Note: * When P36ODR = 1, it becomes NMOS open drain output.

P35/SCK1/

IRQ5 Switches as follows according to the combinations of the C/A bit of SMR1, the

CKE0 and CKE1 bits of SCR, and the P35DDR bit.

CKE1 0 1

C/A01—

CKE0 0 1 ——

P35DDR 0 1 ———

Pin function P35

input pin P35

output pin*SCK1

input pin

IRQ5 input

Note: * When P35ODR = 1, it becomes NMOS open drain output.

P34/RxD1 Switches as follows according to combinations of bit RE of SCR1 and bit P34DDR.

RE 0 1

P34DDR 0 1 —

Pin function P34 input pin P34 output pin*RxD1 input pin

Note: * When P34ODR = 1, it becomes NMOS open drain tray.

246

Pin Selection Method and Pin Functions

P33/TxD1 Switches as follows according to combinations of bit TE of SCR1 and bit P33DDR.

TE 0 1

P33DDR 0 1 —

Pin function P33 input pin P33 output pin*TxD1 output pin*

Note: * When P33ODR = 1, it becomes NMOS open drain output.

P32/SCK0/

IRQ4 Switches as follows according to combinations of bit C/A of SMR0, bits CKE0 and

CKE1 of SCR0, and bit P32DDR.

CKE1 0 1

C/A01—

CKE0 0 1 ——

P32DDR 0 1 ———

Pin function P32

input pin P32

output pin SCK0 output

pin*SCK0 output

pin*SCK0

input pin

IRQ4 input

Note: * When P32ODR = 1, it becomes NMOS open drain output.

P31/RxD0 Switches as follows according to combinations of bit RE of SCR0 and bit P31DDR.

RE 0 1

P31DDR 0 1 —

Pin function P31 input pin P31 output pin*RxD0 input pin

Note: * When P31ODR = 1, it becomes NMOS open drain output.

P30/TxD0 Switches as follows according to combinations of bit TE of SCR0 and bit P30DDR.

TE 0 1

P30DDR 0 1 —

Pin function P30 input pin P30 output pin*TxD0 output pin*

Note: * When P30ODR = 1, it becomes NMOS open drain output.

247

9.5 Port 4

9.5.1 Overview

Port 4 is an 8-bit input-only port. Port 4 pins also function as A/D converter analog input pins

(AN0 to AN7). Port 4 pin functions are the same in all operating modes. Figure 9-4 shows the port

4 pin configuration.

P47

P46

P45

P44

P43

P42

P41

P40

(input) /

AN7 (input)

AN6 (input)

AN5 (input)

AN4 (input)

AN3 (input)

AN2 (input)

AN1 (input)

AN0 (input)

Port 4 pins

Port 4

Figure 9-4 Port 4 Pin Functions

248

9.5.2 Register Configuration

Table 9-8 shows the port 4 register configuration. Port 4 is an input-only port, and does not have a

data direction register or data register.

Table 9-8 Port 4 Registers

Name Abbreviation R/W Initial Value Address*

Port 4 register PORT4 R Undefined H'FFB3

Note: * Lower 16 bits of the address.

Port 4 Register (PORT4): The pin states are always read when a port 4 read is performed.

Bit:76543210

P47 P46 P45 P44 P43 P42 P41 P40

Initial value : —*—*—*—*—*—*—*—*

R/W:RRRRRRRR

Note: *Determined by state of pins P47 to P40.

9.5.3 Pin Functions

Port 4 pins also function as A/D converter analog input pins (AN0 to AN7).

249

9.6 Port 5

9.6.1 Overview

Port 5 is a 3-bit I/O port. The pin functions of port 5 are the same in all operating modes. Figures

9-5 (1) and 9-5 (2) show the pin functions for port 5.

Port 5 pins

P52

P51

P50

Port 5

(I/O)

Figure 9-5 (1) Port 5 Pin Functions (H8S/2646, H8S/2646R, H8S/2645)

Port 5 pins

P52

P51

P50

Port 5

(I/O) / SCK2 (I/O)

(I/O) / RxD2 (input)

(I/O) / TxD2 (output)

Figure 9-5 (2) Port 5 Pin Functions (H8S/2648, H8S/2648R, H8S/2647)

250

9.6.2 Register Configuration

Table 9-9 shows the port 5 register configuration.

Table 9-9 Port 5 Register Configuration

Name Abbreviation R/W Initial Value*2Address*1

Port 5 data direction register P5DDR W H'0 H'FE34

Port 5 data register P5DR R/W H'0 H'FF04

Port 5 register PORT5 R H'0 H'FFB4

Notes: *1 Lower 16 bits of the address.

*2 Value of bits 2 to 0.

Port 5 Data Direction Register (P5DDR)

Bit:76543210

—————P52DDR P51DDR P50DDR

Initial value : Undefined Undefined Undefined Undefined Undefined 000

R/W : —————WWW

P5DDR is an 8-bit write-only register that specifies whether individual bits are input or output for

each of each of the pins in port 5. It is not possible to read it. An undefined value is returned if an

attempt is made to read it.

Setting one of the bits of P5DDR to 1 sets the corresponding pin in port 5 to output, and clearing

the bit to 0 sets the corresponding pin to input.

P5DDR is initialized to H'0 (bits 2 to 0) if a reset occurs and in the hardware standby mode. The

previous values are retained by P5DDR in the software standby mode. Since SCI is initialized in

the H8S/2648, H8S/2648R, and H8S/2647, the pin states are determined by the by the P5DDR and

P5DR settings.

Port 5 Data Register (P5DR)

Bit:76543210

—————P52DR P51DR P50DR

Initial value : Undefined Undefined Undefined Undefined Undefined 000

R/W : —————R/W R/W R/W

P5DR is an 8-bit readable/writable register that stores output data for the port 5 pins (P52 to P50).

251

P5DR is initialized to H'00 if a reset occurs and in the hardware standby mode. The previous

values are retained in the software standby mode.

Port 5 Register (PORT5)

Bit:76543210

—————P52 P51 P50

Initial value : Undefined Undefined Undefined Undefined Undefined —*—*—*

R/W : ————— RRR

Note: *Determined by state of pins P52 to P50.

PORT5 is an 8-bit read-only register that reflects the states of the pins. It is not possible to write to

it. Always write output data from the port 5 pins (P52 to P50) to P5DR.

If P5DDR is set to 1, the value of P5DR is returned when port 5 is read. If P5DDR is cleared to 0,

the pin states are returned when port 5 is read.

P5DDR and P5DR are initialized if a reset occurs and in the hardware standby mode, so the

content of PORT5 is determined by the pin states. The previous states are retained in the software

standby mode.

9.6.3 Pin Functions

Tables 9-10 (1) and 9-10 (2) list the pin functions for port 5. In the H8S/2648, H8S/2648R, and

H8S/2647, port 5 pins also function as SCI I/O pins (TxD2, RxD2, and SCK2).

Table 9-10 (1) Port 5 Pin Functions (H8S/2646, H8S/2646R, H8S/2645)

Pin Selection Method and Pin Functions

P52 Switches as follows according to the setting of the P52DDR bit.

P52DDR 0 1

Pin function P52 input pin P52 output pin

P51 Switches as follows according to the setting of the P51DDR bit.

P51DDR 0 1

Pin function P51 input pin P51 output pin

P50 Switches as follows according to the setting of the P50DDR bit.

P50DDR 0 1

Pin function P50 input pin P50 output pin

252

Table 9-10 (2) Port 5 Pin Functions (H8S/2648, H8S/2648R, H8S/2647)

Pin Selection Method and Pin Functions

P52/SCK2 Switches as follows according to a combination of the C/A bit in SMR and bits CKE0

and CKE1 in SCR of SCI2, and the P52DDR bit.

CKE1 0 1

C/A01—

CK0 0 1 ——

P52DDR 0 0 ———

Pin function P52 input pin P52 output

pin SCK2 output

pin SCK2 input

P51/RxD2 Switches as follows according to a combination of the RE bit in SCR of SCI2 and

the P51DDR bit.

RE 0 1

P51DDR 0 1 —

Pin function P51 input pin P51 output pin RxD2 input pin

P50/TxD2 Switches as follows according to a combination of the TE bit in SCR of SCI2 and

the P50DDR bit.

TE 0 1

P50DDR 0 1 —

Pin function P50 input pin P50 output pin P50 output pin

253

9.7 Port 9

9.7.1 Overview

Port 9 is an 8-bit input-only port. Port 9 pins also function as A/D converter analog input pins

(AN8 to AN11). Port 9 pin functions are the same in all operating modes. Figure 9-6 shows the

port 9 pin configuration.

P97

P96

P95

P94

P93

P92

P91

P90

(input)

(input) /

AN11 (input)

AN10 (input)

AN9 (input)

AN8 (input)

Port 9 pins

Port 9

Figure 9-6 Port 9 Pin Functions

254

9.7.2 Register Configuration

Table 9-11 shows the port 9 register configuration. Port 9 is an input-only port, and does not have

a data direction register or data register.

Table 9-11 Port 9 Registers

Name Abbreviation R/W Initial Value Address*

Port 9 register PORT9 R Undefined H'FFB8

Note: * Lower 16 bits of the address.

Port 9 Register (PORT9): The pin states are always read when a port 9 read is performed.

Bit:76543210

P97 P96 P95 P94 P93 P92 P91 P90

Initial value : —*—*—*—*—*—*—*—*

R/W:RRRRRRRR

Note: *Determined by state of pins P97 to P90.

9.7.3 Pin Functions

Port 9 pins also function as A/D converter analog input pins (AN8 to AN11).

255

9.8 Port A

9.8.1 Overview

Port A is an 8-bit I/O port. Port A pins also function as address bus outputs and LCD driver output

pins (H8S/2646, H8S/2646R, H8S/2645: SEG24 to SEG21 and COM4 to COM1, H8S/2648,

H8S/2648R, H8S/2647: SEG40 to Seg37 and COM4 to COM1). The pin functions change

according to the operating mode.

Port A has a built-in MOS input pull-up function that can be controlled by software.

Figure 9-7 shows the port A pin configuration.

Pin functions in modes 4 to 6Port A pins

PA7 / A23 / SEG24*1 / SEG40*2

PA6 / A22 / SEG23*1 / SEG39*2

PA5 / A21 / SEG22*1 / SEG38*2

PA4 / A20 / SEG21*1 / SEG37*2

PA3 / A19 / COM4*1 / COM4*2

PA2 / A18 / COM3*1 / COM3*2

PA1 / A17 / COM2*1 / COM2*2

PA0 / A16 / COM1*1 / COM1*2

PA7 (I/O) / A23 (output) / SEG24*1 (output) / SEG40*2 (output)

PA6 (I/O) / A22 (output) / SEG23*1 (output) / SEG39*2 (output)

PA5 (I/O) / A21 (output) / SEG22*1 (output) / SEG38*2 (output)

PA4 (I/O) / A20 (output) / SEG21*1 (output) / SEG37*2 (output)

PA3 (I/O) / A19 (output) / COM4*1 (output) / COM4*2 (output)

PA2 (I/O) / A18 (output) / COM3*1 (output) / COM3*2 (output)

PA1 (I/O) / A17 (output) / COM2*1 (output) / COM2*2 (output)

PA0 (I/O) / A16 (output) / COM1*1 (output) / COM1*2 (output)

Mode 7 pins

PA7 (I/O) / SEG24*1 (output) / SEG40*2 (output)

PA6 (I/O) / SEG23*1 (output) / SEG39*2 (output)

PA5 (I/O) / SEG22*1 (output) / SEG38*2 (output)

PA4 (I/O) / SEG21*1 (output) / SEG37*2 (output)

PA3 (I/O) / COM4*1 (output) / COM4*2 (output)

PA2 (I/O) / COM3*1 (output) / COM3*2 (output)

PA1 (I/O) / COM2*1 (output) / COM2*2 (output)

PA0 (I/O) / COM1*1 (output) / COM1*2 (output)

Port A

Notes: *1 In the H8S/2646, H8S/2646R, and H8S/2645.

*2 In the H8S/2648, H8S/2648R, and H8S/2647.

Figure 9-7 Port A Pin Functions

256

9.8.2 Register Configuration

Table 9-12 shows the port A register configuration.

Table 9-12 Port A Registers

Name Abbreviation R/W Initial Value Address*

Port A data direction register PADDR W H'00 H'FE39

Port A data register PADR R/W H'00 H'FF09

Port A register PORTA R Undefined H'FFB9

Port A MOS pull-up control register PAPCR R/W H'00 H'FE40

Port A open-drain control register PAODR R/W H'00 H'FE47

Note: *Lower 16 bits of the address.

Port A Data Direction Register (PADDR)

Bit:76543210

PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR

Initial value : 0 0 0 0 0 0 0 0

R/W:WWWWWWWW

PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port A. PADDR cannot be read; if it is, an undefined value will be read.

PADDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode. The OPE bit in SBYCR is used to select whether the address output pins

retain their output state or become high-impedance when a transition is made to software standby

mode.

• Modes 4 to 6

These function as segment pins if the values of bits SGS3 to SGS0 of LPCR, the LCD driver,

are other than B'0000. If the value of bits SGS3 to SGS0 is B'0000, the port A pins function as

address outputs as specified by the setting of bits AE3 to AE0 of PFCR, regardless of the

values of bits PA7DDR to PA0DDR. Also, when the pins are not used as address outputs,

setting a PADDR bit to 1 makes the corresponding port A pin an output port, and clearing a bit

to 0 makes the corresponding pin an input port.

• Mode 7

These function as segment pins if the values of bits SGS3 to SGS0 of LPCR, the LCD driver,

are other than B'0000. If the value of bits SGS3 to SGS0 is B'0000, setting a PADDR bit to 1

makes the corresponding port A pin an output port, and clearing a bit to 0 makes the

corresponding pin an input port.

257

Port A Data Register (PADR)

Bit:76543210

PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA7 to

PA0).

PADR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode.

Port A Register (PORTA)

Bit:76543210

PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

Initial value : —*—*—*—*—*—*—*—*

R/W:RRRRRRRR

Note: *Determined by state of pins PA7 to PA0.

PORTA is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of

output data for the port A pins (PA7 to PA0) must always be performed on PADR.

Reading a pin being used as an LCD driver returns an undefined value.

If a port A read is performed while PADDR bits are set to 1, the PADR values are read. If a port A

read is performed while PADDR bits are cleared to 0, the pin states are read.

After a reset and in hardware standby mode, PORTA contents are determined by the pin states, as

PADDR and PADR are initialized. PORTA retains its prior state in software standby mode.

258

Port A MOS Pull-Up Control Register (PAPCR)

Bit:76543210

PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function

incorporated into port A on an individual bit basis.

In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in LPCR,

and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for that

pin.

In mode 7, if a pin is in the input state in accordance with the settings in LPCR and DDR, setting

the corresponding PAPCR bit to 1 turns on the MOS input pull-up for that pin.

PAPCR is initialized by a reset or to H'00, and in hardware standby mode. It retains its prior state

in software standby mode.

Port A Open Drain Control Register (PAODR)

Bit:76543210

PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

PAODR is an 8-bit readable/writable register that controls whether PMOS is on or off for each

port A pin (PA7 to PA0).

When pins are not address and LCD outputs in accordance with the setting of bits AE3 to AE0 in

PFCR, setting a PAODR bit makes the corresponding port A pin an NMOS open-drain output,

while clearing the bit to 0 makes the pin a CMOS output.

PAODR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode.

9.8.3 Pin Functions

Port A pins also function as address bus outputs and LCD driver output pins (SEG21 to SEG24

and COM1 to COM4). The pin functions differ between modes 4 to 6, and mode 7. Port A pin

functions are shown in tables 9-13 and 9-14.

259

Table 9-13 PA7 to PA4 Pin Functions

Pin Selection Method and Pin Functions

H8S/2646

H8S/2646R

H8S/2645

PA7/A23

/SEG24 to

PA4/A20

Switches as follows according to the combinations of bits SGS3 to SGS0 of LCD

driver LPCR, bits AE3 to AE0 of PFGR, and bits PA7DDR to PA4DDR of PADDR.

/SEG21 Setting of Port SEG output

SGS3 to SGS0 H8S/2646,

H8S/2646R,

H8S/2645

H8S/2648,

H8S/2648R,

H8S/2647

H8S/2648

H8S/2648R

H8S/2647

PA7/A23

/SEG40 to

PA4/A20

Operating

mode Modes 4 to 6 Mode 7 ——

/SEG37 Setting of AE3

to AE0 Address

output

enabled

Address output

disabled ———

PAnDDR —0101 ——

Pin function A23 to

A20

output

PA7 to

PA4

input

PA7 to

PA4

output

PA7 to

PA4

input

PA7 to

PA4

output

SEG24 to

SEG21

output

SEG40 to

SEG37

output

n = 7 to 4

Table 9-14 PA3 to PA0 Pin Functions

Pin Selection Method and Pin Functions

PA3/A19/COM4 to

PA0/A16/COM1 Switches as follows according to the combinations of bits SGS3 to SGS0 of

LCD driver LPCR, bits AE3 to AE0 of PFGR, and bits PA3DDR to PA0DDR of

PADDR.

Setting of

SGS3 to SGS0 0000 Other than

0000

Operating

mode Modes 4 to 6 Mode 7 —

Setting of AE3

to AE0 Address

output

enabled

Address output

disabled ——

PAnDDR —0101—

Pin function A19 to

A16

output

PA3 to

PA0 input PA3 to

PA0

output

PA3 to

PA0 input PA3 to

PA0

output

COM1 to

COM4

output

n = 3 to 0

260

9.8.4 MOS Input Pull-Up Function

Port A has a built-in MOS input pull-up function that can be controlled by software. MOS input

pull-up can be specified as on or off on an individual bit basis.

In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in LPCR,

and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for that

pin.

In mode 7, if a pin is in the input state in accordance with the settings in the LPCR and in DDR,

setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for that pin.

The MOS input pull-up function is in the off state after a reset, and in hardware standby mode.

The prior state is retained in software standby mode.

Table 9-15 summarizes the MOS input pull-up states.

Table 9-15 MOS Input Pull-Up States (Port A)

Pin States Reset Hardware

Standby Mode Software

Standby Mode In Other

Operations

Address output or

SCI output OFF OFF OFF OFF

Other than above ON/OFF ON/OFF

Legend:

OFF : MOS input pull-up is always off.

ON/OFF : On when PADDR = 0 and PAPCR = 1; otherwise off.

261

9.9 Port B

9.9.1 Overview

Port B is an 8-bit I/O port. Port B also functions as LCD driver output pins (H8S/2646,

H8S/2646R, H8S/2645: SEG16 to SEG9, H8S/2648, H8S/2648R, H8S/2647: SEG32 to SEG9)

and as address bus outputs. The pin functions are determined by the operating mode.

Port B has a built-in MOS input pull-up function that can be controlled by software.

Figure 9-8 shows the port B pin configuration.

PB7 / A15 / SEG16*1 / SEG32*2

PB6 / A14 / SEG15*1 / SEG31*2

PB5 / A13 / SEG14*1 / SEG30*2

PB4 / A12 / SEG13*1 / SEG29*2

PB3 / A11 / SEG12*1 / SEG28*2

PB2 / A10 / SEG11*1 / SEG27*2

PB1 / A9 / SEG10*1 / SEG26*2

PB0 / A8 / SEG9*1 / SEG25*2

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

(I/O) /

A15

A14

A13

A12

A11

A10

(output) / SEG16*1 (output) / SEG32*2 (output)

(output) / SEG15*1 (output) / SEG31*2 (output)

(output) / SEG14*1 (output) / SEG30*2 (output)

(output) / SEG13*1 (output) / SEG29*2 (output)

(output) / SEG12*1 (output) / SEG28*2 (output)

(output) / SEG11*1 (output) / SEG27*2 (output)

(output) / SEG10*1 (output) / SEG26*2 (output)

(output) / SEG9*1 (output) / SEG25*2 (output)

Port B pins

Mode 7 pins

Pin functions in modes 4 to 6

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

(I/O) / SEG16*1 (output) / SEG32*2 (output)

(I/O) / SEG15*1 (output) / SEG31*2 (output)

(I/O) / SEG14*1 (output) / SEG30*2 (output)

(I/O) / SEG13*1 (output) / SEG29*2 (output)

(I/O) / SEG12*1 (output) / SEG28*2 (output)

(I/O) / SEG11*1 (output) / SEG27*2 (output)

(I/O) / SEG10*1 (output) / SEG26*2 (output)

(I/O) / SEG9*1 (output) / SEG25*2 (output)

Port B

Notes: *1 In the H8S/2646, H8S/2646R, and H8S/2645.

*2 In the H8S/2648, H8S/2648R, and H8S/2647.

Figure 9-8 Port B Pin Functions

262

9.9.2 Register Configuration

Table 9-16 shows the port B register configuration.

Table 9-16 Port B Registers

Name Abbreviation R/W Initial Value Address*

Port B data direction register PBDDR W H'00 H'FE3A

Port B data register PBDR R/W H'00 H'FF0A

Port B register PORTB R Undefined H'FFBA

Port B MOS pull-up control register PBPCR R/W H'00 H'FE41

Port B open-drain control register PBODR R/W H'00 H'FE48

Note: * Lower 16 bits of the address.

Port B Data Direction Register (PBDDR)

Bit:76543210

PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR

Initial value : 0 0 0 0 0 0 0 0

R/W:WWWWWWWW

PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port B. PBDDR cannot be read; if it is, an undefined value will be read.

PBDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode. The OPE bit in SBYCR is used to select whether the address output pins

retain their output state or become high-impedance when a transition is made to software standby

mode.

Port B Data Register (PBDR)

Bit:76543210

PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB7 to

PB0). PBDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior

state in software standby mode.

263

Port B Register (PORTB)

Bit:76543210

PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

Initial value : —*—*—*—*—*—*—*—*

R/W:RRRRRRRR

Note: *Determined by state of pins PB7 to PB0.

PORTB is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of

output data for the port B pins (PB7 to PB0) must always be performed on PBDR.

If a port B read is performed while PBDDR bits are set to 1, the PBDR values are read. If a port B

read is performed while PBDDR bits are cleared to 0, the pin states are read.

Reading a pin being used as an LCD driver returns an undefined value.

After a reset and in hardware standby mode, PORTB contents are determined by the pin states, as

PBDDR and PBDR are initialized. PORTB retains its prior state in software standby mode.

Port B MOS Pull-Up Control Register (PBPCR)

Bit:76543210

PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

PBPCR is an 8-bit readable/writable register that controls the MOS input pull-up function

incorporated into port B on an individual bit basis.

In modes 4 to 6, if a pin is in the input state in accordance with the settings in the LCD driver’s

LPCR and in DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for

that pin.

In mode 7, if a pin is in the input state in accordance with the settings in the DDR, setting the

corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin.

PBPCR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode.

264

Port B Open Drain Control Register (PBODR)

Bit:76543210

PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

PBODR is an 8-bit readable/writable register that controls the PMOS on/off state for each port B

pin (PB7 to PB0).

When pins are not address outputs in accordance with the setting of bits AE3 to AE0 in PFCR,

setting a PBODR bit makes the corresponding port B pin an NMOS open-drain output, while

clearing the bit to 0 makes the pin a CMOS output.

Do not set PBODR to 1 if the pins are being used for LCD driver output.

PBODR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode.

9.9.3 Pin Functions

Port B pins also function as LCD driver output pins (H8S/2646, H8S/2646R, H8S/2645: SEG16 to

SEG9, H8S/2648, H8S/2648R, H8S/2647: SEG32 to SEG25) and address bus outputs. The pin

functions differ between modes 4 to 6 and mode 7. Port B pin functions are shown in table 9-17.

Table 9-17 Port B Pin Functions

Setting of SGS3

to SGS0 Port SEG output

H8S/2646,

H8S/2646R,

H8S/2645

H8S/2648,

H8S/2648R,

H8S/2647

Operating mode Modes 4 to 6 Mode 7 ——

Setting of AE3 to

AE0 Address

output

enabled

Address output

disabled ———

PBnDDR —010 1 ——

Pin function A15 to A8

output PB7 to

PB0 input PB7 to

PB0

output

PB7 to

PB0 input PB7 to

PB0

output

SEG16 to

SEG9

output

SEG32 to

SEG25

output

265

9.9.4 MOS Input Pull-Up Function

Port B has a built-in MOS input pull-up function that can be controlled by software. MOS input

pull-up can be specified as on or off on an individual bit basis.

In modes 4 to 6, if a pin is in the input state in accordance with the settings of PFCR, the LCD

driver LPCR, and DDR, setting PBPCR to 1 turns on MOS input pull-up.

In mode 7, if a pin is in the input state in accordance with the settings of the LCD driver LPCR

and DDR, setting PBPCR to 1 turns on MOS input pull-up.

The MOS input pull-up function is in the off state after a reset, and in hardware standby mode.

The prior state is retained by a manual reset or in software standby mode.

Table 9-18 summarizes the MOS input pull-up states.

Table 9-18 MOS Input Pull-Up States (Port B)

Pin States Reset Hardware

Standby Mode Software

Standby Mode In Other

Operations

Address output or

LCD output OFF OFF OFF OFF

Other than above ON/OFF ON/OFF

Legend:

OFF: MOS input pull-up is always off.

ON/OFF: On when PBDDR = 0 and PBPCR = 1; otherwise off.

266

9.10 Port C

9.10.1 Overview

Port C is an 8-bit I/O port. Port C also functions as LCD driver output pins (H8S/2646,

H8S/2646R, H8S/2645: SEG8 to SEG1, H8S/2648, H8S/2648R, H8S/2647: SEG24 to SEG17)

and as address bus outputs. The pin functions are determined by the operating mode.

Port C has a built-in MOS input pull-up function that can be controlled by software.

Figure 9-9 shows the port C pin configuration.

PC7 / A7 / SEG8*1 / SEG24*2

PC6 / A6 / SEG7*1 / SEG23*2

PC5 / A5 / SEG6*1 / SEG22*2

PC4 / A4 / SEG5*1 / SEG21*2

PC3 / A3 / SEG4*1 / SEG20*2

PC2 / A2 / SEG3*1 / SEG19*2

PC1 / A1 / SEG2*1 / SEG18*2

PC0 / A0 / SEG1*1 / SEG17*2

Port C

Port C pins

Pin functions in mode 7

(output)

(output) / SEG8*1 (output) / SEG24*2 (output)

(output) / SEG7*1 (output) / SEG23*2 (output)

(output) / SEG6*1 (output) / SEG22*2 (output)

(output) / SEG5*1 (output) / SEG21*2 (output)

(output) / SEG4*1 (output) / SEG20*2 (output)

(output) / SEG3*1 (output) / SEG19*2 (output)

(output) / SEG2*1 (output) / SEG18*2 (output)

(output) / SEG1*1 (output) / SEG17*2 (output)

Pin functions in modes 4 and 5

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

(I/O) / SEG8*1 (output) / SEG24*2 (output)

(I/O) / SEG7*1 (output) / SEG23*2 (output)

(I/O) / SEG6*1 (output) / SEG22*2 (output)

(I/O) / SEG5*1 (output) / SEG21*2 (output)

(I/O) / SEG4*1 (output) / SEG20*2 (output)

(I/O) / SEG3*1 (output) / SEG19*2 (output)

(I/O) / SEG2*1 (output) / SEG18*2 (output)

(I/O) / SEG1*1 (output) / SEG17*2 (output)

Pin functions in mode 6

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

(I/O) /

Notes: *1 In the H8S/2646, H8S/2646R, and H8S/2645.

*2 In the H8S/2648, H8S/2648R, and H8S/2647.

Figure 9-9 Port C Pin Functions

267

9.10.2 Register Configuration

Table 9-19 shows the port C register configuration.

Table 9-19 Port C Registers

Name Abbreviation R/W Initial Value Address*

Port C data direction register PCDDR W H'00 H'FE3B

Port C data register PCDR R/W H'00 H'FF0B

Port C register PORTC R Undefined H'FFBB

Port C MOS pull-up control register PCPCR R/W H'00 H'FE42

Port C open-drain control register PCODR R/W H'00 H'FE49

Note: * Lower 16 bits of the address.

Port C Data Direction Register (PCDDR)

Bit:76543210

PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR

Initial value : 0 0 0 0 0 0 0 0

R/W:WWWWWWWW

PCDDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port C. PCDDR cannot be read; if it is, an undefined value will be read.

PCDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode. The OPE bit in SBYCR is used to select whether the address output pins

retain their output state or become high-impedance when the mode is changed to software standby

mode.

Port C Data Register (PCDR)

Bit:76543210

PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

PCDR is an 8-bit readable/writable register that stores output data for the port C pins (PC7 to

PC0).

PCDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode.

268

Port C Register (PORTC)

Bit:76543210

PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

Initial value : —*—*—*—*—*—*—*—*

R/W:RRRRRRRR

Note: *Determined by state of pins PC7 to PC0.

PORTC is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of

output data for the port C pins (PC7 to PC0) must always be performed on PCDR.

If a port C read is performed while PCDDR bits are set to 1, the PCDR values are read. If a port C

read is performed while PCDDR bits are cleared to 0, the pin states are read.

Reading a pin being used as an LCD driver returns an undefined value.

After a reset and in hardware standby mode, PORTC contents are determined by the pin states, as

PCDDR and PCDR are initialized. PORTC retains its prior state in software standby mode.

Port C MOS Pull-Up Control Register (PCPCR)

Bit:76543210

PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

PCPCR is an 8-bit readable/writable register that controls the MOS input pull-up function

incorporated into port C on an individual bit basis.

In modes 6 and 7, if PCPCR is set to 1 when the port is in the input state in accordance with the

settings of the LCD driver LPCR and PCDDR, the MOS input pull-up is set to ON.

PCPCR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state by

a manual reset or in software standby mode.

269

Port C Open Drain Control Register (PCODR)

PC7ODR

R/W

Bit

Initial value

Read/Write

PC6ODR

R/W

PC5ODR

R/W

PC4ODR

R/W

PC3ODR

R/W

PC2ODR

R/W

PC1ODR

R/W

PC0ODR

R/W

PCODR is an 8-bit readable/writable register and controls PMOS On/Off of each pin (PC7 to

PC0) of port C.

If PCODR is set to 1 by setting AE3 to AE0 in PFCR in mode other than address output mode,

port C pins function as NMOS open drain outputs and when the setting is cleared to 0, the pins

function as CMOS outputs.

Do not set PCODR to 1 if the pins are being used for LCD driver output.

PCODR is initialized to H'00 in reset mode or hardware standby mode. PCODR retains the last

state in software standby mode.

9.10.3 Pin Functions

Port C can function as LCD segment output pins (H8S/2646, H8S/2646R, H8S/2645: SEG8 to

SEG1, H8S/2648, H8S/2648R, H8S/2647: SEG24 to SEG17) and as address bus outputs. The pin

functions differ in modes 4, 5, 6, and 7. The port C pin functions are listed in table 9-20.

Table 9-20 Port C Pin Functions

Setting of

SGS3 to Port SEG output

SGS0 H8S/2646,

H8S/2646R,

H8S/2645

H8S/2648,

H8S/2648R,

H8S/2647

Operating

mode Modes

4 and 5 Mode 6 Mode 7 ——

PCnDDR —0101——

Pin function A7 to A0

output PC7 to

PC0 input A7 to A0

output PC7 to

PC0 input PC7 to

PC0 output SEG8 to

SEG1

output

SEG24 to

SEG17

output

Note: Modes 4 and 5 are extended modes in which the internal ROM is disabled. Address output

is disabled when port C is set to segment output, so it is not possible to interface with

external ROM. Therefore port C must not be set to segment output in mode 4 or mode 5.

270

9.10.4 MOS Input Pull-Up Function

Port C has a built-in MOS input pull-up function that can be controlled by software. This MOS

input pull-up function can be used in modes 6 and 7, and can be specified as on or off on an

individual bit basis.

In modes 6 and 7, when PCPCR is set to 1 in the input state by setting of the LCD driver LPCR

and PCDDR, the MOS input pull-up is set to ON.

The MOS input pull-up function is in the off state after a reset, and in hardware standby mode.

The prior state is retained by a manual reset or in software standby mode.

Table 9-21 summarizes the MOS input pull-up states.

Table 9-21 MOS Input Pull-Up States (Port C)

Pin States Reset Hardware

Standby Mode Software

Standby Mode In Other

Operations

Address output OFF OFF OFF OFF

Other than above ON/OFF ON/OFF

Legend:

OFF: MOS input pull-up is always off.

ON/OFF: On when PCDDR = 0 and PCPCR = 1; otherwise off.

271

9.11 Port D

9.11.1 Overview

Port D is an 8-bit I/O port. Port D has a data bus I/O function, and the pin functions change

according to the operating mode. In the H8S/2648, H8S/2648R, H8S/2647, port D pins also

function as LCD driver output pins (SEG16 to SEG9).

Port D has a built-in MOS input pull-up function that can be controlled by software.

Figure 9-10 shows the port D pin configuration.

PD7 / D15 / SEG16*

PD6 / D14 / SEG15*

PD5 / D13 / SEG14*

PD4 / D12 / SEG13*

PD3 / D11 / SEG12*

PD2 / D10 / SEG11*

PD1 / D9 / SEG10*

PD0 / D8 / SEG9*

Port D

D15

D14

D13

D12

D11

D10

(I/O) / SEG16* (output)

(I/O) / SEG15* (output)

(I/O) / SEG14* (output)

(I/O) / SEG13* (output)

(I/O) / SEG12* (output)

(I/O) / SEG11* (output)

(I/O) / SEG10* (output)

(I/O) / SEG9* (output)

Port D pins Pin functions in modes 4 to 6

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

(I/O) / SEG16* (output)

(I/O) / SEG15* (output)

(I/O) / SEG14* (output)

(I/O) / SEG13* (output)

(I/O) / SEG12* (output)

(I/O) / SEG11* (output)

(I/O) / SEG10* (output)

(I/O) / SEG9* (output)

Pin functions in mode 7

Note: * In the H8S/2648, H8S/2648R, and H8S/2647.

Figure 9-10 Port D Pin Functions

272

9.11.2 Register Configuration

Table 9-22 shows the port D register configuration.

Table 9-22 Port D Registers

Name Abbreviation R/W Initial Value Address*

Port D data direction register PDDDR W H'00 H'FE3C

Port D data register PDDR R/W H'00 H'FF0C

Port D register PORTD R Undefined H'FFBC

Port D MOS pull-up control register PDPCR R/W H'00 H'FE43

Note: * Lower 16 bits of the address.

Port D Data Direction Register (PDDDR)

Bit:76543210

PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR

Initial value : 0 0 0 0 0 0 0 0

R/W:WWWWWWWW

PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port D. PDDDR cannot be read; if it is, an undefined value will be read.

PDDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode.

Port D Data Register (PDDR)

Bit:76543210

PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD7 to

PD0).

PDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode.

273

Port D Register (PORTD)

Bit:76543210

PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Initial value : —*—*—*—*—*—*—*—*

R/W:RRRRRRRR

Note: *Determined by state of pins PD7 to PD0.

PORTD is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of

output data for the port D pins (PD7 to PD0) must always be performed on PDDR.

If a port D read is performed while PDDDR bits are set to 1, the PDDR values are read. If a port D

read is performed while PDDDR bits are cleared to 0, the pin states are read.

After a reset and in hardware standby mode, PORTD contents are determined by the pin states, as

PDDDR and PDDR are initialized. PORTD retains its prior state in software standby mode.

Port D MOS Pull-Up Control Register (PDPCR)

Bit:76543210

PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

PDPCR is an 8-bit readable/writable register that controls the MOS input pull-up function

incorporated into port D on an individual bit basis.

In mode 7, if a pin is in the input state in accordance with the settings in PDDDR and LPCR,

setting the corresponding PDPCR bit to 1 turns on the MOS input pull-up for that pin.

PDPCR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode.

274

9.11.3 Pin Functions

In modes 4 to 6, each pin on port D automatically becomes one of the data bus I/O pins (D15 to

D8). In mode 7, each pin on port D functions as an I/O port and can be specified to function as an

input or output bit by bit.

The function of pins on port D are as listed in tables 9-23 (1) and 9-23 (2).

Table 9-23 (1) Port D Pin Functions (H8S/2646, H8S/2646R, H8S/2645)

Pins Method of Selection and Pin Function

PD7/D15, PD6/D14,

PD5/D13, PD4/D12, Pin functions are changed by a combination of the operating mode and the

PDDDR.

PD3/D11, PD2/D10, Operating mode Mode 4 to 6 Mode 7

PD1/D9, PD0/D8 PDnDDR —01

Pin function Data bus I/O (D15 to D8) PDn input PDn output

n = 7 to 0

Table 9-23 (2) Port D Pin Functions (H8S/2648, H8S/2648R, H8S/2647)

Pins Method of Selection and Pin Function

PD7/D15/SEG9 to

PD0/D8/SEG16 Setting of SGS3

to SGS0 Port SEG output

Operating mode Mode 4 to 6 Mode 7 —

PDDDR —01—

Pin function D15 to D8 I/O PD7 to PD0

input PD7 to PD0

output SEG9 to

SEG16

Note: Modes 4 and 5 are expanded modes with on-chip ROM disabled.

If segment output is selected, data input/output and interfacing to external ROM are no

longer possible. Therefore segment output settings should not be made in these modes.

275

9.11.4 MOS Input Pull-Up Function

Port D has a built-in MOS input pull-up function that can be controlled by software. This MOS

input pull-up function can be used in mode 7, and can be specified as on or off on an individual bit

basis.

In mode 7, if a pin is in the input state in accordance with the settings in PDDDR and LPCR,

setting the corresponding PDPCR bit to 1 turns on the MOS input pull-up for that pin.

The MOS input pull-up function is in the off state after a reset, and in hardware standby mode.

The prior state is retained in software standby mode.

Table 9-24 summarizes the MOS input pull-up states.

Table 9-24 MOS Input Pull-Up States (Port D)

Modes Reset Hardware

Standby Mode Software

Standby Mode In Other

Operations

4 to 6 OFF OFF OFF OFF

7 ON/OFF ON/OFF

Legend:

OFF: MOS input pull-up is always off.

ON/OFF: On when PDDDR = 0, PDPCR = 1, and the pin is not used as a segment driver;

otherwise off.

276

9.12 Port E

9.12.1 Overview

Port E is an 8-bit I/O port. Port E has a data bus I/O function, and the pin functions change

according to the operating mode and whether 8-bit or 16-bit bus mode is selected. In the

H8S/2648, H8S/2648R, and H8S/2647, port E pins also function as LCD driver output pins (SEG8

to SEG1).

Port E has a built-in MOS input pull-up function that can be controlled by software.

Figure 9-11 shows the port E pin configuration.

PE7 / D7 / SEG8*

PE6 / D6 / SEG7*

PE5 / D5 / SEG6*

PE4 / D4 / SEG5*

PE3 / D3 / SEG4*

PE2 / D2 / SEG3*

PE1 / D1 / SEG2*

PE0 / D0 / SEG1*

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

(I/O) /

Port E pins Pin functions in modes 4 to 6

Pin functions in mode 7

(I/O) / SEG8* (output)

(I/O) / SEG7* (output)

(I/O) / SEG6* (output)

(I/O) / SEG5* (output)

(I/O) / SEG4* (output)

(I/O) / SEG3* (output)

(I/O) / SEG2* (output)

(I/O) / SEG1* (output)

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

(I/O) / SEG8* (output)

(I/O) / SEG7* (output)

(I/O) / SEG6* (output)

(I/O) / SEG5* (output)

(I/O) / SEG4* (output)

(I/O) / SEG3* (output)

(I/O) / SEG2* (output)

(I/O) / SEG1* (output)

Port E

Note: * In the H8S/2648, H8S/2648R, and H8S/2647.

Figure 9-11 Port E Pin Functions

277

9.12.2 Register Configuration

Table 9-25 shows the port E register configuration.

Table 9-25 Port E Registers

Name Abbreviation R/W Initial Value Address*

Port E data direction register PEDDR W H'00 H'FE3D

Port E data register PEDR R/W H'00 H'FF0D

Port E register PORTE R Undefined H'FFBD

Port E MOS pull-up control register PEPCR R/W H'00 H'FE44

Note: *Lower 16 bits of the address.

Port E Data Direction Register (PEDDR)

Bit:76543210

PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR

Initial value : 0 0 0 0 0 0 0 0

R/W:WWWWWWWW

PEDDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port E. PEDDR cannot be read; if it is, an undefined value will be read.

PEDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state by

a manual reset or in software standby mode.

Port E Data Register (PEDR)

Bit:76543210

PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE7 to PE0).

PEDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode.

278

Port E Register (PORTE)

Bit:76543210

PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0

Initial value : —*—*—*—*—*—*—*—*

R/W:RRRRRRRR

Note: *Determined by state of pins PE7 to PE0.

PORTE is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of

output data for the port E pins (PE7 to PE0) must always be performed on PEDR.

If a port E read is performed while PEDDR bits are set to 1, the PEDR values are read. If a port E

read is performed while PEDDR bits are cleared to 0, the pin states are read.

Pins used as LCD driver pins will return an undefined value if read.

After a reset and in hardware standby mode, PORTE contents are determined by the pin states, as

PEDDR and PEDR are initialized. PORTE retains its prior state in software standby mode.

Port E MOS Pull-Up Control Register (PEPCR)

Bit:76543210

PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

PEPCR is an 8-bit readable/writable register that controls the MOS input pull-up function

incorporated into port E on an individual bit basis.

In modes 4 to 6 with 8-bit-bus mode selected, or in mode 7, if a pin is in the input state in

accordance with the settings in LPCR and PEDDR, setting the corresponding PEPCR bit to 1 turns

on the MOS input pull-up for that pin.

PEPCR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode.

279

9.12.3 Pin Functions

The port E pin functions are listed in tables 9-26 (1) and 9-26 (2).

Table 9-26 (1) Port E Pin Functions (H8S/2646, H8S/2646R, H8S/2645)

Operating mode Modes 4 to 6 Mode 7

Bus width setting 16-bit mode 8-bit mode —

PEDDR —0101

Pin function D7 to D0 I/O PE7 to PE0

input PE7 to PE0

output PE7 to PE0

input PE7 to PE0

output

Table 9-26 (2) Port E Pin Functions (H8S/2648, H8S/2648R, H8S/2647)

Setting of SEG3 to

SEG0 Port SEG

output

Operating mode Modes 4 to 6 Mode 7 —

Bus width setting 16-bit mode 8-bit mode ——

PEDDR —010 1—

Pin function D7 to D0 I/O PE7 to PE0

input PE7 to PE0

output PE7 to PE0

input PE7 to PE0

output SEG1 to

SEG8

output

9.12.4 MOS Input Pull-Up Function

Port E has a built-in MOS input pull-up function that can be controlled by software. This MOS

input pull-up function can be used in modes 4 to 6 when 8-bit bus mode is selected, or in mode 7,

and can be specified as on or off on an individual bit basis.

In modes 4 to 6 with 8-bit-bus mode selected, or in mode 7, if a pin is in the input state in

accordance with the settings in LPCR and PEDDR, setting the corresponding PEPCR bit to 1 turns

on the MOS input pull-up for that pin.

The MOS input pull-up function is in the off state after a reset, and in hardware standby mode.

The prior state is retained in software standby mode.

Table 9-27 summarizes the MOS input pull-up states.

280

Table 9-27 MOS Input Pull-Up States (Port E)

Modes Reset Hardware

Standby Mode Software

Standby Mode In Other

Operations

7 OFF OFF ON/OFF ON/OFF

4 to 6 8-bit bus

16-bit bus OFF OFF

Legend:

OFF: MOS input pull-up is always off.

ON/OFF: On when PEDDR = 0, PEPCR = 1, and the pin is not used as a segment driver;

otherwise off.

281

9.13 Port F

9.13.1 Overview

Port F is a 7-bit I/O port. Port F also functions as LCD driver output pins (SEG20 to SEG17),

external interrupt input pins (IRQ2, IRQ3), the A/D trigger input pin (ADTRG), bus control signal

I/O pins (AS, RD, HWR, LWR, WAIT), and as the system clock output pin (φ).

Figure 9-12 shows the port F pin configuration.

PF7 / ø

PF6 / AS / SEG20 / SEG36*

PF5 / RD / SEG19 / SEG35*

PF4 / HWR / SEG18 / SEG34*

PF3 / LWR / ADTRG / IRQ3

PF2 / WAIT / SEG17 / SEG33*

PF0 / IRQ2

Port F

Port F pins

PF7 (input) / ø (output)

PF6 (I/O) / AS (output) / SEG20 (output) / SEG36* (output)

PF5 (I/O) / RD (output) / SEG19 (output) / SEG35* (output)

PF4 (I/O) / HWR (output) / SEG18 (output) / SEG34* (output)

PF3 (I/O) / LWR (output) / ADTRG (input) / IRQ3 (input)

PF2 (I/O) / WAIT (input) / SEG17 (output) / SEG33* (output)

PF0 (I/O) / IRQ2 (input)

Pin functions in modes 4 to 6

PF7 (I/O) / ø (output)

PF6 (I/O) / SEG20 (output) / SEG36* (output)

PF5 (I/O) / SEG19 (output)) / SEG35* (output)

PF4 (I/O) / SEG18 (output)) / SEG34* (output)

PF3 (I/O) / ADTRG (input) / IRQ3 (input)

PF2 (I/O) / SEG17 (output)) / SEG33* (output)

PF0 (I/O) / IRQ2 (input)

Pin functions in mode 7

Note: * In the H8S/2648, H8S/2648R, and H8S/2647.

Figure 9-12 Port F Pin Functions

282

9.13.2 Register Configuration

Table 9-28 shows the port F register configuration.

Table 9-28 Port F Registers

Name Abbreviation R/W Initial Value Address*1

Port F data direction register PFDDR W H'80/H'00*2H'FE3E

Port F data register PFDR R/W H'00 H'FF0E

Port F register PORTF R Undefined H'FFBE

Notes: *1 Lower 16 bits of the address.

*2 Initial value depends on the mode.

Port F Data Direction Register (PFDDR)

Bit:76543210

PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR —PF0DDR

Modes 4 to 6

Initial value : 1 0 0 0 0 0 undefined 0

R/W:WWWWWW—W

Mode 7

Initial value : 0 0 0 0 0 0 undefined 0

R/W:WWWWWW—W

PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port F. PFDDR cannot be read; if it is, an undefined value will be read.

PFDDR is initialized by a reset, and in hardware standby mode, to H'80 in modes 4 to 6, and to

H'00 in mode 7. It retains its prior state in software standby mode. The OPE bit in SBYCR is used

to select whether the bus control output pins retain their output state or become high-impedance

when a transition is made to software standby mode.

PFDDR bit 1 is reserved.

283

Port F Data Register (PFDR)

Bit:76543210

—PF6DR PF5DR PF4DR PF3DR PF2DR —PF0DR

Initial value : 0 0 0 0 0 0 undefined 0

R/W : R/W R/W R/W R/W R/W R/W —R/W

PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF6 to PF2,

PF0).

PFDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode.

Bits 7 and 1 in PFDR are reserved, and only 0 may be written to it.

Port F Register (PORTF)

Bit:76543210

PF7 PF6 PF5 PF4 PF3 PF2 —PF0

Initial value : —*—*—*—*—*—*undefined —*

R/W:RRRRRR—R

Note: *Determined by state of pins PF7 to PF2, PF0.

PORTF is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of

output data for the port F pins (PF7 to PF2, PF0) must always be performed on PFDR.

If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F

read is performed while PFDDR bits are cleared to 0, the pin states are read.

Pins used as LCD driver pins will return an undefined value if read.

After a reset and in hardware standby mode, PORTF contents are determined by the pin states, as

PFDDR and PFDR are initialized. PORTF retains its prior state in software standby mode.

PORTF bit 1 is reserved.

284

9.13.3 Pin Functions

Port F pins also function as LCD driver output pins (SEG20 to SEG17), external interrupt input

pins (IRQ2, IRQ3), the A/D trigger input pin (ADTRG), bus control signal I/O pins (AS, RD,

HWR, LWR, WAIT), and the system clock output pin (ø). Their functions differ in modes 4 to 6

and in mode 7. Table 9-29 lists the pin functions for port F.

Table 9-29 Port F Pin Functions

Pin Selection Method and Pin Functions

PF7/øSwitches as follows according to bit PF7DDR.

PF7DDR 0 1

Pin function PF7 input ø output

PF6/AS/SEG20

(H8S/2646,

H8S/2646R,

H8S/2645)

Switches as follows according to the operating mode and the setting of SGS3

to SGS0 and bit PF6DDR.

PF6/AS/SEG36

(H8S/2648,

H8S/2648R,

H8S/2647)

Operating Mode Modes 4 to 6 Mode 7

Setting of SGS3 to

SGS0 SEG

output Port SEG

output Port

PF6DDR ——— 01

function H8S/2646,

H8S/2646R,

H8S/2645

SEG20

output AS output SEG20

output PF6 input PF6 output

H8S/2648,

H8S/2648R,

H8S/2647

SEG36

output SEG36

output

285

Pin Selection Method and Pin Functions

PF5/RD/SEG19

(H8S/2646,

H8S/2646R,

H8S/2645)

Switches as follows according to the operating mode and the setting of SGS3

to SGS0 and bit PF5DDR.

PF5/RD/SEG35

(H8S/2648,

H8S/2648R,

H8S/2647)

Operating Mode Modes 4 to 6 Mode 7

Setting of SGS3 to

SGS0 SEG

output Port SEG

output Port

PF5DDR ——— 01

function H8S/2646,

H8S/2646R,

H8S/2645

SEG19

output RD output SEG19

output PF5 input PF5 output

H8S/2648,

H8S/2648R,

H8S/2647

SEG35

output SEG35

output

PF4/HWR/SEG1

8 (H8S/2646,

H8S/2646R,

H8S/2645)

Switches as follows according to the operating mode and the setting of SGS3

to SGS0 and bit PF4DDR.

PF4/HWR/SEG34

(H8S/2648,

H8S/2648R,

H8S/2647)

Operating Mode Modes 4 to 6 Mode 7

Setting of SGS3 to

SGS0 SEG

output Port SEG

output Port

PF4DDR ——— 01

function H8S/2646,

H8S/2646R,

H8S/2645

SEG18

output HWR

output SEG18

output PF4

input PF4

output

H8S/2648,

H8S/2648R,

H8S/2647

SEG34

output SEG34

output

286

Pin Selection Method and Pin Functions

PF3/LWR/

ADTRG/IRQ3 Switches as follows according to the operating mode and the setting of bits

TRGS1, TRGS0, and PF3DDR.

Operating

Mode Modes 4 to 6 Mode 7

Bus mode 16-bit bus

mode 8-bit bus mode —

PF3DDR —0101

Pin function LWR output PF3 input PF3 output PF3 input PF3 output

ADTRG input*1

IRQ3 input*2

Notes: *1ADTRG input when TRGS0 = TRGS1 = 1.

*2 When used as an external interrupt input pin, do not use it as an I/O

pin for other functions.

PF2/WAIT/SEG1

7 (H8S/2646,

H8S/2646R,

H8S/2645)

Switches as follows according to the operating mode, and the setting of bits

SGS3 to SGS0, the WAITE bit, and bit PF2DDR.

PF2/WAIT/SEG33

(H8S/2648,

H8S/2648R,

H8S/2647)

Operating Mode Modes 4 to 6 Mode 7

Setting of SGS3 to

SGS0 SEG

output Port SEG

output Port

WAITE —011—

PF2DDR —01—— 01

function H8S/2646,

H8S/2646R,

H8S/2645

SEG17

output PF2

input PF2

output

WAIT

input SEG17

output PF2

input PF2

output

H8S/2648,

H8S/2648R,

H8S/2647

SEG33

output SEG33

output

PF0/IRQ2 Switches as follows according to the PF0DDR bit.

PF0DDR 0 1

Pin function PF0 input PF0 output

IRQ2 input

287

9.14 Port H

9.14.1 Overview

Port H is an 8-bit I/O port. Port H pins also function as motor control PWM timer output pins

(PWM1A to PWM1H).

Figure 9-13 shows the port H pin configuration.

PH7 (I/O) / PWM1H (output)

PH6 (I/O) / PWM1G (output)

PH5 (I/O) / PWM1F (output)

PH4 (I/O) / PWM1E (output)

PH3 (I/O) / PWM1D (output)

PH2 (I/O) / PWM1C (output)

PH1 (I/O) / PWM1B (output)

PH0 (I/O) / PWM1A (output)

Port H pin

Port H

Figure 9-13 Port H Pin Functions

9.14.2 Register Configuration

Table 9-30 shows the port H register configuration.

Table 9-30 Port H Registers

Name Abbreviation R/W Initial Value Address*

Port H data direction register PHDDR W H'00 H'FC20

Port H data register PHDR R/W H'00 H'FC24

Port H register PORTH R Undefined H'FC28

Note: *Lower 16 bits of the address.

288

Port H Data Direction Register (PHDDR)

Bit:76543210

PH7DDR PH6DDR PH5DDR PH4DDR PH3DDR PH2DDR PH1DDR PH0DDR

Initial value : 0 0 0 0 0 0 0 0

R/W:WWWWWWWW

PHDDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port H. PHDDR cannot be read. If it is, an undefined value will be read.

PHDDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in

software standby mode.

Port H Data Register (PHDR)

Bit:76543210

PH7DR PH6DR PH5DR PH4DR PH3DR PH2DR PH1DR PH0DR

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

PHDR is an 8-bit readable/writeable register that stores output data for the port H pins (PH7 to

PH0).

PHDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in

software standby mode.

Port H Register (PORTH)

Bit:76543210

PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0

Initial value : —*—*—*—*—*—*—*—*

R/W:RRRRRRRR

Note: *Determined by the state of PH7 to PH0

PORTH is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of

output data for the port H pins (PH7 to PH0) must always be performed on PHDR.

If a port H read is performed while PHDDR bits are set to 1, the PHDR values are read. If a port H

read is performed while PHDDR bits are cleared to 0, the pin states are read.

After a reset and in hardware standby mode, PORTH contents are determined by the pin states, as

PHDDR and PHDR are initialized. PORTH retains its prior state in software standby mode.

289

9.14.3 Pin Functions

As shown in Table 9-31, the port H pin functions can be switched, bit by bit, by changing the

values of OE1A to OE1H of motor control PWM timer PWOCR1 and PHDDR.

Table 9-31 Port H Pin Functions

OE1A to OE1H 1 0

PHDDR —01

Pin function Motor control PWM

timer output PH7 to PH0 input PH7 to PH0 output

9.15 Port J

9.15.1 Overview

Port J is an 8-bit I/O port. Port J pins also function as motor control PWM timer output pins

(PWM2A to PWM2H).

Figure 9-14 shows the port J pin configuration.

PJ7 (I/O) / PWM2H (output)

PJ6 (I/O) / PWM2G (output)

PJ5 (I/O) / PWM2F (output)

PJ4 (I/O) / PWM2E (output)

PJ3 (I/O) / PWM2D (output)

PJ2 (I/O) / PWM2C (output)

PJ1 (I/O) / PWM2B (output)

PJ0 (I/O) / PWM2A (output)

Port J

Port J pin

Figure 9-14 Port J Pin Functions

290

9.15.2 Register Configuration

Table 9-32 shows the port J register configuration.

Table 9-32 Port J Registers

Name Abbreviation R/W Initial Value Address*

Port J data direction register PJDDR W H'00 H'FC21

Port J data register PJDR R/W H'00 H'FC25

Port J register PORTJ R Undefined H'FC29

Note: *Lower 16 bits of the address

Port J Data Direction Register (PJDDR)

Bit:76543210

PJ7DDR PJ6DDR PJ5DDR PJ4DDR PJ3DDR PJ2DDR PJ1DDR PJ0DDR

Initial value : 0 0 0 0 0 0 0 0

R/W:WWWWWWWW

PJDDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port J. PJDDR cannot be read. If it is, an undefined value will be read.

PJDDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in

software standby mode.

Port J Data Register (PJDR)

Bit:76543210

PJ7DR PJ6DR PJ5DR PJ4DR PJ3DR PJ2DR PJ1DR PJ0DR

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

PJDR is an 8-bit readable/writeable register that stores output data for the port J pins (PJ7 to PJ0).

PJDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in

software standby mode.

291

Port J Register (PORTJ)

Bit:76543210

PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0

Initial value : —*—*—*—*—*—*—*—*

R/W:RRRRRRRR

Note: * Determined by the state of PJ7 to PJ0.

PORTJ is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of

output data for the port J pins (PJ7 to PJ0) must always be performed on PJDR.

If a port J read is performed while PJDDR bits are set to 1, the PJDR values are read. If a port J

read is performed while PJDDR bits are cleared to 0, the pin states are read.

After a reset and in hardware standby mode, PORTJ contents are determined by the pin states, as

PJDDR and PJDR are initialized. PORTJ retains its prior state in software standby mode.

9.15.3 Pin Functions

As shown in table 9-33, the port J pin functions can be switched, bit by bit, by changing the values

of OE2A to OE2H of motor control PWM timer PWOCR2 and PJDDR.

Table 9-33 Port J Pin Functions

OE2A to OE2H 1 0

PJDDR —01

Pin function Motor control PWM

timer output PJ7 to PJ0 input PJ7 to PJ0 output

292

9.16 Port K

9.16.1 Overview

Port K is a 2-bit I/O port.

Figure 9-15 shows the pin functions for port K.

Port K pins

PK7 (I/O)

PK6 (I/O)

Port K

Figure 9-15 Port K Pin Functions

9.16.2 Register Configuration

Table 9-34 shows the port A register configuration.

Table 9-34 Port K Registers

Name Abbreviation R/W Initial Value Address*

Port K data direction register PKDDR W H'0 H'FC22

Port K data register PKDR R/W H'0 H'FC26

Port K register PORTK R Undefined H'FC2A

Note: *Lower 16 bits of the address.

293

Port K Data Direction Register (PKDDR)

Bit:76543210

PK7DDR PK6DDR ——————

Initial value : 0 0 Undefined Undefined Undefined Undefined Undefined Undefined

R/W : W W ——————

PKDDR is an 8-bit write-only register that specifies whether individual bits are input or output for

each of the pins in port K. It is not possible to read it. An undefined value is returned if an attempt

is made to read it.

PKDDR is initialized to H'00 if a reset occurs and in the hardware standby mode. The previous

values are retained by PKDDR in the software standby mode.

Port K Data Register (PKDR)

Bit:76543210

PK7DR PK6DR ——————

Initial value : 0 0 Undefined Undefined Undefined Undefined Undefined Undefined

R/W : R/W R/W ——————

PKDR is an 8-bit readable/writable register that stores output data for the port K pins (PK7, PK6).

PKDR is initialized to H'00 if a reset occurs and in the hardware standby mode. The previous

values are retained in the software standby mode.

Port K Register (PORTK)

Bit:76543210

PK7 PK6 ——————

Initial value : —*—*Undefined Undefined Undefined Undefined Undefined Undefined

R/W : R R ——————

Note: *Determined by state of pins PF7 to PF6.

PORTK is an 8-bit read-only register that reflects the states of the pins. It is not possible to write

to it. Always write output data from the port K pins (PK7, PK6) to PKDR.

If PKDDR is set to 1, the value of PKDR is returned when port K is read. If PKDDR is cleared to

0, the pin states are returned when port K is read.

294

PKDDR and PKDR are initialized if a reset occurs and in the hardware standby mode, so the

content of PORTK is determined by the pin states. The previous states are retained in the software

standby mode.

9.16.3 Pin Functions

The function of the port K pins changes with the operating mode, in accordance with the value of

PKDDR, as shown in table 9-35.

Table 9-35 Port K Pin Functions

PKDDR 0 1

Pin function PK7, PK6 input PK7, PK6 output

295

Section 10 16-Bit Timer Pulse Unit (TPU)

10.1 Overview

The H8S/2646 Series has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer

channels.

10.1.1 Features

• Maximum 16-pulse input/output

 A total of 16 timer general registers (TGRs) are provided (four each for channels 0 and 3,

and two each for channels 1, 2, 4, and 5), each of which can be set independently as an

output compare/input capture register

 TGRC and TGRD for channels 0 and 3 can also be used as buffer registers

• Selection of 8 counter input clocks for each channel

• The following operations can be set for each channel:

 Waveform output at compare match: Selection of 0, 1, or toggle output

 Input capture function: Selection of rising edge, falling edge, or both edge detection

 Counter clear operation: Counter clearing possible by compare match or input capture

 Synchronous operation: Multiple timer counters (TCNT) can be written to simultaneously,

Simultaneous clearing by compare match and input capture

possible,

synchronous operation

 PWM mode: Any PWM output duty can be set,

Maximum of 15-phase PWM output possible by combination with

synchronous operation

• Buffer operation settable for channels 0 and 3

 Input capture register double-buffering possible

 Automatic rewriting of output compare register possible

• Phase counting mode settable independently for each of channels 1, 2, 4, and 5

 Two-phase encoder pulse up/down-count possible

• Cascaded operation

 Channel 2 (channel 5) input clock operates as 32-bit counter by setting channel 1 (channel

4) overflow/underflow

296

• Fast access via internal 16-bit bus

 Fast access is possible via a 16-bit bus interface

• 26 interrupt sources

 For channels 0 and 3, four compare match/input capture dual-function interrupts and one

overflow interrupt can be requested independently

 For channels 1, 2, 4, and 5, two compare match/input capture dual-function interrupts, one

overflow interrupt, and one underflow interrupt can be requested independently

• Automatic transfer of register data

 Block transfer, 1-word data transfer, and 1-byte data transfer possible by data transfer

controller (DTC)

• Programmable pulse generator (PPG) output trigger can be generated

 Channel 0 to 3 compare match/input capture signals can be used as PPG output trigger

• A/D converter conversion start trigger can be generated

 Channel 0 to 5 compare match A/input capture A signals can be used as A/D converter

conversion start trigger

• Module stop mode can be set

 As the initial setting, TPU operation is halted. Register access is enabled by exiting module

stop mode.

Table 10-1 lists the functions of the TPU.

297

Table 10-1 TPU Functions

Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5

Count clock ø/1

ø/4

ø/16

ø/64

TCLKA

TCLKB

TCLKC

TCLKD

ø/1

ø/4

ø/16

ø/64

ø/256

TCLKA

TCLKB

ø/1

ø/4

ø/16

ø/64

ø/1024

TCLKA

TCLKB

TCLKC

ø/1

ø/4

ø/16

ø/64

ø/256

ø/1024

ø/4096

TCLKA

ø/1

ø/4

ø/16

ø/64

ø/1024

TCLKA

TCLKC

ø/1

ø/4

ø/16

ø/64

ø/256

TCLKA

TCLKC

TCLKD

General registers TGR0A

TGR0B TGR1A

TGR1B TGR2A

TGR2B TGR3A

TGR3B TGR4A

TGR4B TGR5A

TGR5B

General registers/

buffer registers TGR0C

TGR0D — — TGR3C

TGR3D ——

I/O pins TIOCA0

TIOCB0

TIOCC0

TIOCD0

TIOCA1

TIOCB1 TIOCA2

TIOCB2 TIOCA3

TIOCB3

TIOCC3

TIOCD3

TIOCA4

TIOCB4 TIOCA5

TIOCB5

Counter clear

function TGR

compare

match or

input

capture

TGR

compare

match or

input

capture

TGR

compare

match or

input

capture

TGR

compare

match or

input

capture

TGR

compare

match or

input

capture

TGR

compare

match or

input

capture

Compare 0 output

match 1 output

output Toggle

output

Input capture

function

Synchronous

operation

PWM mode

Phase counting

mode — —

Buffer operation —— ——

298

Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5

DTC

activation TGR

compare

match or

input capture

TGR

compare

match or

input capture

TGR

compare

match or

input capture

TGR

compare

match or

input capture

TGR

compare

match or

input capture

TGR

compare

match or

input capture

A/D

converter

trigger

TGR0A

compare

match or

input capture

TGR1A

compare

match or

input capture

TGR2A

compare

match or

input capture

TGR3A

compare

match or

input capture

TGR4A

compare

match or

input capture

TGR5A

compare

match or

input capture

PPG

trigger TGR0A/

TGR0B

compare

match or

input capture

TGR1A/

TGR1B

compare

match or

input capture

TGR2A/

TGR2B

compare

match or

input capture

TGR3A/

TGR3B

compare

match or

input capture

——

Interrupt

sources 5 sources

• Compare

match or

input

capture 0A

• Compare

match or

input

capture 0B

• Compare

match or

input

capture 0C

• Compare

match or

input

capture 0D

• Overflow

4 sources

• Compare

match or

input

capture 1A

• Compare

match or

input

capture 1B

• Overflow

• Underflow

4 sources

• Compare

match or

input

capture 2A

• Compare

match or

input

capture 2B

• Overflow

• Underflow

5 sources

• Compare

match or

input

capture 3A

• Compare

match or

input

capture 3B

• Compare

match or

input

capture 3C

• Compare

match or

input

capture 3D

• Overflow

4 sources

• Compare

match or

input

capture 4A

• Compare

match or

input

capture 4B

• Overflow

• Underflow

4 sources

• Compare

match or

input

capture 5A

• Compare

match or

input

capture 5B

• Overflow

• Underflow

Legend

: Possible

— : Not possible

299

10.1.2 Block Diagram

Figure 10-1 shows a block diagram of the TPU.

Channel 3

TMDR

TIORL

TSR

TCR

TIORH

TIER

TGRA

TCNT

TGRB

TGRC

TGRD

Channel 4

TMDR

TSR

TCR

TIOR

TIER

TGRA

TCNT

TGRB

Control logic TMDR

TSR

TCR

TIOR

TIER

TGRA

TCNT

TGRB

Control logic for channels 3 to 5

TGRA

TCNT

TGRB

TGRC

Channel 1

TMDR

TSR

TCR

TIOR

TIER

TGRA

TCNT

TGRB

Channel 0

TMDR

TSR

TCR

TIORH

TIER

Control logic for channels 0 to 2

TGRD

TSYRTSTR

Input/output pins

TIOCA3

TIOCB3

TIOCC3

TIOCD3

TIOCA4

TIOCB4

TIOCA5

TIOCB5

Clock input

ø/1

ø/4

ø/16

ø/64

ø/256

ø/1024

ø/4096

TCLKA

TCLKB

TCLKC

TCLKD

Input/output pins

TIOCA0

TIOCB0

TIOCC0

TIOCD0

TIOCA1

TIOCB1

TIOCA2

TIOCB2

Interrupt request signals

Channel 3:

Channel 4:

Channel 5:

Interrupt request signals

Channel 0:

Channel 1:

Channel 2:

Internal data bus

PPG output trigger signal

TIORL

Module data bus

TGI3A

TGI3B

TGI3C

TGI3D

TCI3V

TGI4A

TGI4B

TCI4V

TCI4U

TGI5A

TGI5B

TCI5V

TCI5U

TGI0A

TGI0B

TGI0C

TGI0D

TCI0V

TGI1A

TGI1B

TCI1V

TCI1U

TGI2A

TGI2B

TCI2V

TCI2U

Channel 3:

Channel 4:

Channel 5:

Internal clock:

External clock:

Channel 0:

Channel 1:

Channel 2:

Legend

TSTR: Timer start register

TSYR: Timer synchronous register

TCR: Timer control register

TMDR: Timer mode register

TIOR (H, L): Timer I/O control registers (H, L)

TIER: Timer interrupt enable register

TSR: Timer status register

TGR (A, B, C, D): Timer general registers (A, B, C, D)

TMDR

TSR

TCR

TIOR

TIER

TGRA

TCNT

TGRB

Channel 2 Common Channel 5

Bus interface

A/D converter conversion

start signal

Figure 10-1 Block Diagram of TPU

300

10.1.3 Pin Configuration

Table 10-2 summarizes the TPU pins.

Table 10-2 TPU Pins

Channel Name Symbol I/O Function

All Clock input A TCLKA Input External clock A input pin

(Channel 1 and 5 phase counting mode A

phase input)

Clock input B TCLKB Input External clock B input pin

(Channel 1 and 5 phase counting mode B

phase input)

Clock input C TCLKC Input External clock C input pin

(Channel 2 and 4 phase counting mode A

phase input)

Clock input D TCLKD Input External clock D input pin

(Channel 2 and 4 phase counting mode B

phase input)

0 Input capture/out

compare match A0 TIOCA0 I/O TGR0A input capture input/output compare

output/PWM output pin

Input capture/out

compare match B0 TIOCB0 I/O TGR0B input capture input/output compare

output/PWM output pin

Input capture/out

compare match C0 TIOCC0 I/O TGR0C input capture input/output compare

output/PWM output pin

Input capture/out

compare match D0 TIOCD0 I/O TGR0D input capture input/output compare

output/PWM output pin

1 Input capture/out

compare match A1 TIOCA1 I/O TGR1A input capture input/output compare

output/PWM output pin

Input capture/out

compare match B1 TIOCB1 I/O TGR1B input capture input/output compare

output/PWM output pin

2 Input capture/out

compare match A2 TIOCA2 I/O TGR2A input capture input/output compare

output/PWM output pin

Input capture/out

compare match B2 TIOCB2 I/O TGR2B input capture input/output compare

output/PWM output pin

301

Channel Name Symbol I/O Function

3 Input capture/out

compare match A3 TIOCA3 I/O TGR3A input capture input/output compare

output/PWM output pin

Input capture/out

compare match B3 TIOCB3 I/O TGR3B input capture input/output compare

output/PWM output pin

Input capture/out

compare match C3 TIOCC3 I/O TGR3C input capture input/output compare

output/PWM output pin

Input capture/out

compare match D3 TIOCD3 I/O TGR3D input capture input/output compare

output/PWM output pin

4 Input capture/out

compare match A4 TIOCA4 I/O TGR4A input capture input/output compare

output/PWM output pin

Input capture/out

compare match B4 TIOCB4 I/O TGR4B input capture input/output compare

output/PWM output pin

5 Input capture/out

compare match A5 TIOCA5 I/O TGR5A input capture input/output compare

output/PWM output pin

Input capture/out

compare match B5 TIOCB5 I/O TGR5B input capture input/output compare

output/PWM output pin

302

10.1.4 Register Configuration

Table 10-3 summarizes the TPU registers.

Table 10-3 TPU Registers

Channel Name Abbreviation R/W Initial Value Address *1

0 Timer control register 0 TCR0 R/W H'00 H'FF10

Timer mode register 0 TMDR0 R/W H'C0 H'FF11

Timer I/O control register 0H TIOR0H R/W H'00 H'FF12

Timer I/O control register 0L TIOR0L R/W H'00 H'FF13

Timer interrupt enable register 0 TIER0 R/W H'40 H'FF14

Timer status register 0 TSR0 R/(W)*2H'C0 H'FF15

Timer counter 0 TCNT0 R/W H'0000 H'FF16

Timer general register 0A TGR0A R/W H'FFFF H'FF18

Timer general register 0B TGR0B R/W H'FFFF H'FF1A

Timer general register 0C TGR0C R/W H'FFFF H'FF1C

Timer general register 0D TGR0D R/W H'FFFF H'FF1E

1 Timer control register 1 TCR1 R/W H'00 H'FF20

Timer mode register 1 TMDR1 R/W H'C0 H'FF21

Timer I/O control register 1 TIOR1 R/W H'00 H'FF22

Timer interrupt enable register 1 TIER1 R/W H'40 H'FF24

Timer status register 1 TSR1 R/(W) *2H'C0 H'FF25

Timer counter 1 TCNT1 R/W H'0000 H'FF26

Timer general register 1A TGR1A R/W H'FFFF H'FF28

Timer general register 1B TGR1B R/W H'FFFF H'FF2A

2 Timer control register 2 TCR2 R/W H'00 H'FF30

Timer mode register 2 TMDR2 R/W H'C0 H'FF31

Timer I/O control register 2 TIOR2 R/W H'00 H'FF32

Timer interrupt enable register 2 TIER2 R/W H'40 H'FF34

Timer status register 2 TSR2 R/(W) *2H'C0 H'FF35

Timer counter 2 TCNT2 R/W H'0000 H'FF36

Timer general register 2A TGR2A R/W H'FFFF H'FF38

Timer general register 2B TGR2B R/W H'FFFF H'FF3A

303

Channel Name Abbreviation R/W Initial Value Address*1

3 Timer control register 3 TCR3 R/W H'00 H'FE80

Timer mode register 3 TMDR3 R/W H'C0 H'FE81

Timer I/O control register 3H TIOR3H R/W H'00 H'FE82

Timer I/O control register 3L TIOR3L R/W H'00 H'FE83

Timer interrupt enable register 3 TIER3 R/W H'40 H'FE84

Timer status register 3 TSR3 R/(W)*2H'C0 H'FE85

Timer counter 3 TCNT3 R/W H'0000 H'FE86

Timer general register 3A TGR3A R/W H'FFFF H'FE88

Timer general register 3B TGR3B R/W H'FFFF H'FE8A

Timer general register 3C TGR3C R/W H'FFFF H'FE8C

Timer general register 3D TGR3D R/W H'FFFF H'FE8E

4 Timer control register 4 TCR4 R/W H'00 H'FE90

Timer mode register 4 TMDR4 R/W H'C0 H'FE91

Timer I/O control register 4 TIOR4 R/W H'00 H'FE92

Timer interrupt enable register 4 TIER4 R/W H'40 H'FE94

Timer status register 4 TSR4 R/(W) *2H'C0 H'FE95

Timer counter 4 TCNT4 R/W H'0000 H'FE96

Timer general register 4A TGR4A R/W H'FFFF H'FE98

Timer general register 4B TGR4B R/W H'FFFF H'FE9A

5 Timer control register 5 TCR5 R/W H'00 H'FEA0

Timer mode register 5 TMDR5 R/W H'C0 H'FEA1

Timer I/O control register 5 TIOR5 R/W H'00 H'FEA2

Timer interrupt enable register 5 TIER5 R/W H'40 H'FEA4

Timer status register 5 TSR5 R/(W) *2H'C0 H'FEA5

Timer counter 5 TCNT5 R/W H'0000 H'FEA6

Timer general register 5A TGR5A R/W H'FFFF H'FEA8

Timer general register 5B TGR5B R/W H'FFFF H'FEAA

All Timer start register TSTR R/W H'00 H'FEB0

Timer synchro register TSYR R/W H'00 H'FEB1

Module stop control register A MSTPCRA R/W H'3F H'FDE8

Notes: *1 Lower 16 bits of the address.

*2 Can only be written with 0 for flag clearing.

304

10.2 Register Descriptions

10.2.1 Timer Control Register (TCR)

Channel 0: TCR0

Channel 3: TCR3

Bit:76543210

CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

Channel 1: TCR1

Channel 2: TCR2

Channel 4: TCR4

Channel 5: TCR5

Bit:76543210

—CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0

Initial value : 0 0 0 0 0 0 0 0

R/W : —R/W R/W R/W R/W R/W R/W R/W

The TCR registers are 8-bit registers that control the TCNT channels. The TPU has six TCR

registers, one for each of channels 0 to 5. The TCR registers are initialized to H'00 by a reset, and

in hardware standby mode.

TCR register settings should be made only when TCNT operation is stopped.

305

Bits 7 to 5—Counter Clear 2 to 0 (CCLR2 to CCLR0): These bits select the TCNT counter

clearing source.

Channel Bit 7

CCLR2 Bit 6

CCLR1 Bit 5

CCLR0 Description

0, 3 0 0 0 TCNT clearing disabled (Initial value)

1 TCNT cleared by TGRA compare match/input

capture

1 0 TCNT cleared by TGRB compare match/input

capture

1 TCNT cleared by counter clearing for another

channel performing synchronous clearing/

synchronous operation *1

1 0 0 TCNT clearing disabled

1 TCNT cleared by TGRC compare match/input

capture *2

1 0 TCNT cleared by TGRD compare match/input

capture *2

1 TCNT cleared by counter clearing for another

channel performing synchronous clearing/

synchronous operation *1

Channel Bit 7

Reserved*3Bit 6

CCLR1 Bit 5

CCLR0 Description

1, 2, 4, 5 0 0 0 TCNT clearing disabled (Initial value)

1 TCNT cleared by TGRA compare match/input

capture

1 0 TCNT cleared by TGRB compare match/input

capture

1 TCNT cleared by counter clearing for another

channel performing synchronous clearing/

synchronous operation *1

Notes: *1 Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.

*2 When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the

buffer register setting has priority, and compare match/input capture does not occur.

*3 Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be

modified.

306

Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge.

When the input clock is counted using both edges, the input clock period is halved (e.g. ø/4 both

edges = ø/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is

ignored and the phase counting mode setting has priority.

Bit 4

CKEG1 Bit 3

CKEG0 Description

0 0 Count at rising edge (Initial value)

1 Count at falling edge

1—Count at both edges

Note: Internal clock edge selection is valid when the input clock is ø/4 or slower. This setting is

ignored if the input clock is ø/1, or when overflow/underflow of another channel is selected.

Bits 2 to 0—Time Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the TCNT counter

clock. The clock source can be selected independently for each channel. Table 10-4 shows the

clock sources that can be set for each channel.

Table 10-4 TPU Clock Sources

Internal Clock External Clock

Overflow/

Underflow

on Another

Channel ø/1 ø/4 ø/16 ø/64 ø/256 ø/1024 ø/4096 TCLKA TCLKB TCLKC TCLKD Channel

Legend

: Setting

Blank: No setting

307

Channel Bit 2

TPSC2 Bit 1

TPSC1 Bit 0

TPSC0 Description

0000Internal clock: counts on ø/1 (Initial value)

1 Internal clock: counts on ø/4

1 0 Internal clock: counts on ø/16

1 Internal clock: counts on ø/64

1 0 0 External clock: counts on TCLKA pin input

1 External clock: counts on TCLKB pin input

1 0 External clock: counts on TCLKC pin input

1 External clock: counts on TCLKD pin input

Channel Bit 2

TPSC2 Bit 1

TPSC1 Bit 0

TPSC0 Description

1000Internal clock: counts on ø/1 (Initial value)

1 Internal clock: counts on ø/4

1 0 Internal clock: counts on ø/16

1 Internal clock: counts on ø/64

1 0 0 External clock: counts on TCLKA pin input

1 External clock: counts on TCLKB pin input

1 0 Internal clock: counts on ø/256

1 Counts on TCNT2 overflow/underflow

Note: This setting is ignored when channel 1 is in phase counting mode.

Channel Bit 2

TPSC2 Bit 1

TPSC1 Bit 0

TPSC0 Description

2000Internal clock: counts on ø/1 (Initial value)

1 Internal clock: counts on ø/4

1 0 Internal clock: counts on ø/16

1 Internal clock: counts on ø/64

1 0 0 External clock: counts on TCLKA pin input

1 External clock: counts on TCLKB pin input

1 0 External clock: counts on TCLKC pin input

1 Internal clock: counts on ø/1024

Note: This setting is ignored when channel 2 is in phase counting mode.

308

Channel Bit 2

TPSC2 Bit 1

TPSC1 Bit 0

TPSC0 Description

3000Internal clock: counts on ø/1 (Initial value)

1 Internal clock: counts on ø/4

1 0 Internal clock: counts on ø/16

1 Internal clock: counts on ø/64

1 0 0 External clock: counts on TCLKA pin input

1 Internal clock: counts on ø/1024

1 0 Internal clock: counts on ø/256

1 Internal clock: counts on ø/4096

Channel Bit 2

TPSC2 Bit 1

TPSC1 Bit 0

TPSC0 Description

4000Internal clock: counts on ø/1 (Initial value)

1 Internal clock: counts on ø/4

1 0 Internal clock: counts on ø/16

1 Internal clock: counts on ø/64

1 0 0 External clock: counts on TCLKA pin input

1 External clock: counts on TCLKC pin input

1 0 Internal clock: counts on ø/1024

1 Counts on TCNT5 overflow/underflow

Note: This setting is ignored when channel 4 is in phase counting mode.

Channel Bit 2

TPSC2 Bit 1

TPSC1 Bit 0

TPSC0 Description

5000Internal clock: counts on ø/1 (Initial value)

1 Internal clock: counts on ø/4

1 0 Internal clock: counts on ø/16

1 Internal clock: counts on ø/64

1 0 0 External clock: counts on TCLKA pin input

1 External clock: counts on TCLKC pin input

1 0 Internal clock: counts on ø/256

1 External clock: counts on TCLKD pin input

Note: This setting is ignored when channel 5 is in phase counting mode.

309

10.2.2 Timer Mode Register (TMDR)

Channel 0: TMDR0

Channel 3: TMDR3

Bit:76543210

——BFB BFA MD3 MD2 MD1 MD0

Initial value : 1 1 0 0 0 0 0 0

R/W : ——R/W R/W R/W R/W R/W R/W

Channel 1: TMDR1

Channel 2: TMDR2

Channel 4: TMDR4

Channel 5: TMDR5

Bit:76543210

————MD3 MD2 MD1 MD0

Initial value : 1 1 0 0 0 0 0 0

R/W : ————R/W R/W R/W R/W

The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode

for each channel. The TPU has six TMDR registers, one for each channel. The TMDR registers

are initialized to H'C0 by a reset, and in hardware standby mode.

TMDR register settings should be made only when TCNT operation is stopped.

Bits 7 and 6—Reserved: It is always read as 1 and cannot be modified.

Bit 5—Buffer Operation B (BFB): Specifies whether TGRB is to operate in the normal way, or

TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer

In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is always read as 0 and

cannot be modified.

Bit 5

BFB Description

0 TGRB operates normally (Initial value)

1 TGRB and TGRD used together for buffer operation

310

Bit 4—Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or

TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer

In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot

be modified.

Bit 4

BFA Description

0 TGRA operates normally (Initial value)

1 TGRA and TGRC used together for buffer operation

Bits 3 to 0—Modes 3 to 0 (MD3 to MD0): These bits are used to set the timer operating mode.

Bit 3

MD3*1Bit 2

MD2*2Bit 1

MD1 Bit 0

MD0 Description

0000Normal operation (Initial value)

1 Reserved

1 0 PWM mode 1

1 PWM mode 2

1 0 0 Phase counting mode 1

1 Phase counting mode 2

1 0 Phase counting mode 3

1 Phase counting mode 4

1***—

*: Don’t care

Notes: *1 MD3 is a reserved bit. In a write, it should always be written with 0.

*2 Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always

be written to MD2.

311

10.2.3 Timer I/O Control Register (TIOR)

Channel 0: TIOR0H

Channel 1: TIOR1

Channel 2: TIOR2

Channel 3: TIOR3H

Channel 4: TIOR4

Channel 5: TIOR5

Bit:76543210

IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

Channel 0: TIOR0L

Channel 3: TIOR3L

Bit:76543210

IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the

The TIOR registers are 8-bit registers that control the TGR registers. The TPU has eight TIOR

registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. The TIOR

registers are initialized to H'00 by a reset, and in hardware standby mode.

Care is required since TIOR is affected by the TMDR setting. The initial output specified by

TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in

PWM mode 2, the output at the point at which the counter is cleared to 0 is specified.

312

Bits 7 to 4— I/O Control B3 to B0 (IOB3 to IOB0)

I/O Control D3 to D0 (IOD3 to IOD0):

Bits IOB3 to IOB0 specify the function of TGRB.

Bits IOD3 to IOD0 specify the function of TGRD.

Channel Bit 7

IOB3 Bit 6

IOB2 Bit 5

IOB1 Bit 4

IOB0 Description

0 0000TGR0B is Output disabled (Initial value)

output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

100

TGR0B is

input

capture

Capture input

source is

TIOCB0 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

1** Capture input

source is channel

1/count clock

Input capture at TCNT1

count- up/count-down*1

*: Don’t care

Note: *1 When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and ø/1 is used as the TCNT1

count clock, this setting is invalid and input capture is not generated.

313

Channel Bit 7

IOD3 Bit 6

IOD2 Bit 5

IOD1 Bit 4

IOD0 Description

0 0000TGR0D is Output disabled (Initial value)

output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

100

TGR0D is

input

capture

Capture input

source is

TIOCD0 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

1** Capture input

source is channel

1/count clock

Input capture at TCNT1

count-up/count-down*1

*: Don’t care

Notes: *1 When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and ø/1 is used as the TCNT1

count clock, this setting is invalid and input capture is not generated.

*2 When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this

setting is invalid and input capture/output compare is not generated.

314

Channel Bit 7

IOB3 Bit 6

IOB2 Bit 5

IOB1 Bit 4

IOB0 Description

1 0000TGR1B is Output disabled (Initial value)

output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

100

TGR1B is

input

capture

Capture input

source is

TIOCB1 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

1** Capture input

source is TGR0C

compare match/

input capture

Input capture at generation of

TGR0C compare match/input

capture

*: Don’t care

Channel Bit 7

IOB3 Bit 6

IOB2 Bit 5

IOB1 Bit 4

IOB0 Description

2 0000TGR2B is Output disabled (Initial value)

output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

1*0

TGR2B is

input

capture

Capture input

source is

TIOCB2 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

*: Don’t care

315

Channel Bit 7

IOB3 Bit 6

IOB2 Bit 5

IOB1 Bit 4

IOB0 Description

3 0000TGR3B is Output disabled (Initial value)

output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

100

TGR3B is

input

capture

Capture input

source is

TIOCB3 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

1** Capture input

source is channel

4/count clock

Input capture at TCNT4

count-up/count-down*1

*: Don’t care

Note: *1 When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and ø/1 is used as the TCNT4

count clock, this setting is invalid and input capture is not generated.

316

Channel Bit 7

IOD3 Bit 6

IOD2 Bit 5

IOD1 Bit 4

IOD0 Description

3 0000TGR3D is Output disabled (Initial value)

output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

100

TGR3D is

input

capture

Capture input

source is

TIOCD3 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

1** Capture input

source is channel

4/count clock

Input capture at TCNT4

count-up/count-down*1

*: Don’t care

Notes: *1 When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and ø/1 is used as the TCNT4

count clock, this setting is invalid and input capture is not generated.

*2 When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this

setting is invalid and input capture/output compare is not generated.

317

Channel Bit 7

IOB3 Bit 6

IOB2 Bit 5

IOB1 Bit 4

IOB0 Description

4 0000TGR4B is Output disabled (Initial value)

output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

100

TGR4B is

input

capture

Capture input

source is

TIOCB4 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

1** Capture input

source is TGR3C

compare match/

input capture

Input capture at generation of

TGR3C compare match/

input capture

*: Don’t care

Channel Bit 7

IOB3 Bit 6

IOB2 Bit 5

IOB1 Bit 4

IOB0 Description

5 0000TGR5B is Output disabled (Initial value)

output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

1*0

TGR5B is

input

capture

Capture input

source is

TIOCB5 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

*: Don’t care

318

Bits 3 to 0— I/O Control A3 to A0 (IOA3 to IOA0)

I/O Control C3 to C0 (IOC3 to IOC0):

IOA3 to IOA0 specify the function of TGRA.

IOC3 to IOC0 specify the function of TGRC.

Channel Bit 3

IOA3 Bit 2

IOA2 Bit 1

IOA1 Bit 0

IOA0 Description

0 0000TGR0A is Output disabled (Initial value)

output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

100

TGR0A is

input

capture

Capture input

source is

TIOCA0 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

1** Capture input

source is channel

1/ count clock

Input capture at TCNT1

count-up/count-down

*: Don’t care

319

Channel Bit 3

IOC3 Bit 2

IOC2 Bit 1

IOC1 Bit 0

IOC0 Description

0 0000TGR0C is Output disabled (Initial value)

output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

100

TGR0C is

input

capture

Capture input

source is

TIOCC0 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

1** Capture input

source is channel

1/count clock

Input capture at TCNT1

count-up/count-down

*: Don’t care

Note: *1 When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this

setting is invalid and input capture/output compare is not generated.

320

Channel Bit 3

IOA3 Bit 2

IOA2 Bit 1

IOA1 Bit 0

IOA0 Description

1 0000TGR1A is Output disabled (Initial value)

output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

100

TGR1A is

input

capture

Capture input

source is

TIOCA1 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

1** Capture input

source is TGR0A

compare match/

input capture

Input capture at generation of

channel 0/TGR0A compare

match/input capture

*: Don’t care

Channel Bit 3

IOA3 Bit 2

IOA2 Bit 1

IOA1 Bit 0

IOA0 Description

2 0000TGR2A is Output disabled (Initial value)

output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

1*0

TGR2A is

input

capture

Capture input

source is

TIOCA2 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

*: Don’t care

321

Channel Bit 3

IOA3 Bit 2

IOA2 Bit 1

IOA1 Bit 0

IOA0 Description

3 0000TGR3A is Output disabled (Initial value)

output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

100

TGR3A is

input

capture

Capture input

source is

TIOCA3 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

1** Capture input

source is channel

4/count clock

Input capture at TCNT4

count-up/count-down

*: Don’t care

322

Channel Bit 3

IOC3 Bit 2

IOC2 Bit 1

IOC1 Bit 0

IOC0 Description

3 0000TGR3C is Output disabled (Initial value)

output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

100

TGR3C is

input

capture

Capture input

source is

TIOCC3 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

1** Capture input

source is channel

4/count clock

Input capture at TCNT4

count-up/count-down

*: Don’t care

Note: *1 When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register, this

setting is invalid and input capture/output compare is not generated.

323

Channel Bit 3

IOA3 Bit 2

IOA2 Bit 1

IOA1 Bit 0

IOA0 Description

4 0000TGR4A is Output disabled (Initial value)

output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

100

TGR4A is

input

capture

Capture input

source is

TIOCA4 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

1** Capture input

source is TGR3A

compare match/

input capture

Input capture at generation of

TGR3A compare match/input

capture

*: Don’t care

Channel Bit 3

IOA3 Bit 2

IOA2 Bit 1

IOA1 Bit 0

IOA0 Description

5 0000TGR5A is Output disabled (Initial value)

output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

1*0

TGR5A is

input

capture

Capture input

source is

TIOCA5 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

*: Don’t care

324

10.2.4 Timer Interrupt Enable Register (TIER)

Channel 0: TIER0

Channel 3: TIER3

Bit:76543210

TTGE ——TCIEV TGIED TGIEC TGIEB TGIEA

Initial value : 0 1 0 0 0 0 0 0

R/W : R/W ——R/W R/W R/W R/W R/W

Channel 1: TIER1

Channel 2: TIER2

Channel 4: TIER4

Channel 5: TIER5

Bit:76543210

TTGE —TCIEU TCIEV ——TGIEB TGIEA

Initial value : 0 1 0 0 0 0 0 0

R/W : R/W —R/W R/W ——R/W R/W

The TIER registers are 8-bit registers that control enabling or disabling of interrupt requests for

each channel. The TPU has six TIER registers, one for each channel. The TIER registers are

initialized to H'40 by a reset, and in hardware standby mode.

325

Bit 7—A/D Conversion Start Request Enable (TTGE): Enables or disables generation of A/D

conversion start requests by TGRA input capture/compare match.

Bit 7

TTGE Description

0 A/D conversion start request generation disabled (Initial value)

1 A/D conversion start request generation enabled

Bit 6—Reserved: It is always read as 1 and cannot be modified.

Bit 5—Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests (TCIU) by

the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1, 2, 4, and 5.

In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified.

Bit 5

TCIEU Description

0 Interrupt requests (TCIU) by TCFU disabled (Initial value)

1 Interrupt requests (TCIU) by TCFU enabled

Bit 4—Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests (TCIV) by

the TCFV flag when the TCFV flag in TSR is set to 1.

Bit 4

TCIEV Description

0 Interrupt requests (TCIV) by TCFV disabled (Initial value)

1 Interrupt requests (TCIV) by TCFV enabled

Bit 3—TGR Interrupt Enable D (TGIED): Enables or disables interrupt requests (TGID) by the

TGFD bit when the TGFD bit in TSR is set to 1 in channels 0 and 3.

In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified.

Bit 3

TGIED Description

0 Interrupt requests (TGID) by TGFD bit disabled (Initial value)

1 Interrupt requests (TGID) by TGFD bit enabled

326

Bit 2—TGR Interrupt Enable C (TGIEC): Enables or disables interrupt requests (TGIC) by the

TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3.

In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified.

Bit 2

TGIEC Description

0 Interrupt requests (TGIC) by TGFC bit disabled (Initial value)

1 Interrupt requests (TGIC) by TGFC bit enabled

Bit 1—TGR Interrupt Enable B (TGIEB): Enables or disables interrupt requests (TGIB) by the

TGFB bit when the TGFB bit in TSR is set to 1.

Bit 1

TGIEB Description

0 Interrupt requests (TGIB) by TGFB bit disabled (Initial value)

1 Interrupt requests (TGIB) by TGFB bit enabled

Bit 0—TGR Interrupt Enable A (TGIEA): Enables or disables interrupt requests (TGIA) by the

TGFA bit when the TGFA bit in TSR is set to 1.

Bit 0

TGIEA Description

0 Interrupt requests (TGIA) by TGFA bit disabled (Initial value)

1 Interrupt requests (TGIA) by TGFA bit enabled

327

10.2.5 Timer Status Register (TSR)

Channel 0: TSR0

Channel 3: TSR3

Bit:76543210

———TCFV TGFD TGFC TGFB TGFA

Initial value : 1 1 0 0 0 0 0 0

R/W : ———R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*

Note: *Can only be written with 0 for flag clearing.

Channel 1: TSR1

Channel 2: TSR2

Channel 4: TSR4

Channel 5: TSR5

Bit:76543210

TCFD —TCFU TCFV ——TGFB TGFA

Initial value : 1 1 0 0 0 0 0 0

R/W : R —R/(W)*R/(W)*——R/(W)*R/(W)*

Note: *Can only be written with 0 for flag clearing.

The TSR registers are 8-bit registers that indicate the status of each channel. The TPU has six TSR

registers, one for each channel. The TSR registers are initialized to H'C0 by a reset, and in

hardware standby mode.

328

Bit 7—Count Direction Flag (TCFD): Status flag that shows the direction in which TCNT

counts in channels 1, 2, 4, and 5.

In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified.

Bit 7

TCFD Description

0 TCNT counts down

1 TCNT counts up (Initial value)

Bit 6—Reserved: It is always read as 1 and cannot be modified.

Bit 5—Underflow Flag (TCFU): Status flag that indicates that TCNT underflow has occurred

when channels 1, 2, 4, and 5 are set to phase counting mode.

In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified.

Bit 5

TCFU Description

0 [Clearing condition] (Initial value)

When 0 is written to TCFU after reading TCFU = 1

1 [Setting condition]

When the TCNT value underflows (changes from H'0000 to H'FFFF)

Bit 4—Overflow Flag (TCFV): Status flag that indicates that TCNT overflow has occurred.

Bit 4

TCFV Description

0 [Clearing condition] (Initial value)

When 0 is written to TCFV after reading TCFV = 1

1 [Setting condition]

When the TCNT value overflows (changes from H'FFFF to H'0000 )

329

Bit 3—Input Capture/Output Compare Flag D (TGFD): Status flag that indicates the

occurrence of TGRD input capture or compare match in channels 0 and 3.

In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified.

Bit 3

TGFD Description

0 [Clearing conditions] (Initial value)

• When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0

• When 0 is written to TGFD after reading TGFD = 1

1 [Setting conditions]

• When TCNT = TGRD while TGRD is functioning as output compare register

• When TCNT value is transferred to TGRD by input capture signal while TGRD is

functioning as input capture register

Bit 2—Input Capture/Output Compare Flag C (TGFC): Status flag that indicates the

occurrence of TGRC input capture or compare match in channels 0 and 3.

In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified.

Bit 2

TGFC Description

0 [Clearing conditions] (Initial value)

• When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0

• When 0 is written to TGFC after reading TGFC = 1

1 [Setting conditions]

• When TCNT = TGRC while TGRC is functioning as output compare register

• When TCNT value is transferred to TGRC by input capture signal while TGRC is

functioning as input capture register

330

Bit 1—Input Capture/Output Compare Flag B (TGFB): Status flag that indicates the

occurrence of TGRB input capture or compare match.

Bit 1

TGFB Description

0 [Clearing conditions] (Initial value)

• When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0

• When 0 is written to TGFB after reading TGFB = 1

1 [Setting conditions]

• When TCNT = TGRB while TGRB is functioning as output compare register

• When TCNT value is transferred to TGRB by input capture signal while TGRB is

functioning as input capture register

Bit 0—Input Capture/Output Compare Flag A (TGFA): Status flag that indicates the

occurrence of TGRA input capture or compare match.

Bit 0

TGFA Description

0 [Clearing conditions] (Initial value)

• When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0

• When 0 is written to TGFA after reading TGFA = 1

1 [Setting conditions]

• When TCNT = TGRA while TGRA is functioning as output compare register

• When TCNT value is transferred to TGRA by input capture signal while TGRA is

functioning as input capture register

331

10.2.6 Timer Counter (TCNT)

Channel 0: TCNT0 (up-counter)

Channel 1: TCNT1 (up/down-counter*)

Channel 2: TCNT2 (up/down-counter*)

Channel 3: TCNT3 (up-counter)

Channel 4: TCNT4 (up/down-counter*)

Channel 5: TCNT5 (up/down-counter*)

Bit :1514131211109876543210

Initial value : 0 0 0 0000000000000

R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Note: *These counters can be used as up/down-counters only in phase counting mode or when

counting overflow/underflow on another channel. In other cases they function as up-

counters.

The TCNT registers are 16-bit counters. The TPU has six TCNT counters, one for each channel.

The TCNT counters are initialized to H'0000 by a reset, and in hardware standby mode.

The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit

unit.

332

10.2.7 Timer General Register (TGR)

Bit :1514131211109876543210

Initial value : 1 1 1 1111111111111

R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

The TGR registers are 16-bit registers with a dual function as output compare and input capture

registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two each for channels

1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for operation as

buffer registers*. The TGR registers are initialized to H'FFFF by a reset, and in hardware standby

mode.

The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit.

Note: * TGR buffer register combinations are TGRA—TGRC and TGRB—TGRD.

333

10.2.8 Timer Start Register (TSTR)

Bit:76543210

——CST5 CST4 CST3 CST2 CST1 CST0

Initial value : 0 0 0 0 0 0 0 0

R/W : ——R/W R/W R/W R/W R/W R/W

TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5.

TSTR is initialized to H'00 by a reset, and in hardware standby mode. When setting the operating

mode in TMDR or setting the count clock in TCR, first stop the TCNT counter.

Bits 7 and 6—Reserved: Should always be written with 0.

Bits 5 to 0—Counter Start 5 to 0 (CST5 to CST0): These bits select operation or stoppage for

TCNT.

Bit n

CSTn Description

0 TCNTn count operation is stopped (Initial value)

1 TCNTn performs count operation n = 5 to 0

Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the

counter stops but the TIOC pin output compare output level is retained. If TIOR is written to

when the CST bit is cleared to 0, the pin output level will be changed to the set initial output

value.

334

10.2.9 Timer Synchro Register (TSYR)

Bit:76543210

——SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0

Initial value : 0 0 0 0 0 0 0 0

R/W : ——R/W R/W R/W R/W R/W R/W

TSYR is an 8-bit readable/writable register that selects independent operation or synchronous

operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when

the corresponding bit in TSYR is set to 1.

TSYR is initialized to H'00 by a reset, and in hardware standby mode.

Bits 7 and 6—Reserved: Should always be written with 0.

Bits 5 to 0—Timer Synchro 5 to 0 (SYNC5 to SYNC0): These bits select whether operation is

independent of or synchronized with other channels.

When synchronous operation is selected, synchronous presetting of multiple channels*1, and

synchronous clearing through counter clearing on another channel*2 are possible.

Bit n

SYNCn Description

0 TCNTn operates independently (TCNT presetting/clearing is unrelated to

other channels) (Initial value)

1 TCNTn performs synchronous operation

TCNT synchronous presetting/synchronous clearing is possible n = 5 to 0

Notes: *1 To set synchronous operation, the SYNC bits for at least two channels must be set to 1.

*2 To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source

must also be set by means of bits CCLR2 to CCLR0 in TCR.

335

10.2.10 Module Stop Control Register A (MSTPCRA)

Bit:76543210

MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0

Initial value : 0 0 1 1 1 1 1 1

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

MSTPCRA is an 8-bit readable/writable register that performs module stop mode control.

When the MSTPA5 bit in MSTPCRA is set to 1, TPU operation stops at the end of the bus cycle

and a transition is made to module stop mode. Registers cannot be read or written to in module

stop mode. For details, see section 22.5, Module Stop Mode.

MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 5—Module Stop (MSTPA5): Specifies the TPU module stop mode.

Bit 5

MSTPA5 Description

0 TPU module stop mode cleared

1 TPU module stop mode set (Initial value)

336

10.3 Interface to Bus Master

10.3.1 16-Bit Registers

TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these

registers can be read and written to in 16-bit units.

These registers cannot be read or written to in 8-bit units; 16-bit access must always be used.

An example of 16-bit register access operation is shown in figure 10-2.

Bus interface

Internal data bus

Bus

master Module

data bus

TCNTH TCNTL

Figure 10-2 16-Bit Register Access Operation [Bus Master ↔↔

↔↔ TCNT (16 Bits)]

10.3.2 8-Bit Registers

Registers other than TCNT and TGR are 8-bit. As the data bus to the CPU is 16 bits wide, these

registers can be read and written to in 16-bit units. They can also be read and written to in 8-bit

units.

337

Examples of 8-bit register access operation are shown in figures 10-3, 10-4, and 10-5.

Bus interface

Internal data bus

LModule

data bus

TCR

Bus

master

Figure 10-3 8-Bit Register Access Operation [Bus Master ↔↔

↔↔ TCR (Upper 8 Bits)]

Bus interface

Internal data bus

LModule

data bus

TMDR

Bus

master

Figure 10-4 8-Bit Register Access Operation [Bus Master ↔↔

↔↔ TMDR (Lower 8 Bits)]

Bus interface

Internal data bus

LModule

data bus

TCR TMDR

Bus

master

Figure 10-5 8-Bit Register Access Operation [Bus Master ↔↔

↔↔ TCR and TMDR (16 Bits)]

338

10.4 Operation

10.4.1 Overview

Operation in each mode is outlined below.

Normal Operation: Each channel has a TCNT and TGR register. TCNT performs up-counting,

and is also capable of free-running operation, synchronous counting, and external event counting.

Each TGR can be used as an input capture register or output compare register.

Synchronous Operation: When synchronous operation is designated for a channel, TCNT for

that channel performs synchronous presetting. That is, when TCNT for a channel designated for

synchronous operation is rewritten, the TCNT counters for the other channels are also rewritten at

the same time. Synchronous clearing of the TCNT counters is also possible by setting the timer

synchronization bits in TSYR for channels designated for synchronous operation.

Buffer Operation

• When TGR is an output compare register

When a compare match occurs, the value in the buffer register for the relevant channel is

transferred to TGR.

• When TGR is an input capture register

When input capture occurs, the value in TCNT is transfer to TGR and the value previously

held in TGR is transferred to the buffer register.

Cascaded Operation: The channel 1 counter (TCNT1), channel 2 counter (TCNT2), channel 4

counter (TCNT4), and channel 5 counter (TCNT5) can be connected together to operate as a 32-

bit counter.

PWM Mode: In this mode, a PWM waveform is output. The output level can be set by means of

TIOR. A PWM waveform with a duty of between 0% and 100% can be output, according to the

setting of each TGR register.

Phase Counting Mode: In this mode, TCNT is incremented or decremented by detecting the

phases of two clocks input from the external clock input pins in channels 1, 2, 4, and 5. When

phase counting mode is set, the corresponding TCLK pin functions as the clock pin, and TCNT

performs up- or down-counting.

This can be used for two-phase encoder pulse input.

339

10.4.2 Basic Functions

Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for

the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic

counter, and so on.

• Example of count operation setting procedure

Figure 10-6 shows an example of the count operation setting procedure.

Select counter clock

Operation selection

Select counter clearing source

Periodic counter

Set period

Start count operation

[1]

[2]

[4]

[3]

[5]

Free-running counter

Start count operation

<Free-running counter>

[5]

[1]

[2]

[3]

[4]

[5]

Select output compare register

Select the counter

clock with bits

TPSC2 to TPSC0 in

TCR. At the same

time, select the

input clock edge

with bits CKEG1

and CKEG0 in TCR.

For periodic counter

operation, select the

TGR to be used as

the TCNT clearing

source with bits

CCLR2 to CCLR0 in

TCR.

Designate the TGR

selected in [2] as an

output compare

TIOR.

Set the periodic

counter cycle in the

TGR selected in [2].

Set the CST bit in

TSTR to 1 to start

the counter

operation.

Figure 10-6 Example of Counter Operation Setting Procedure

340

• Free-running count operation and periodic count operation

Immediately after a reset, the TPU’s TCNT counters are all designated as free-running

counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-

count operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000),

the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at

this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from

H'0000.

Figure 10-7 illustrates free-running counter operation.

TCNT value

H'FFFF

H'0000

CST bit

TCFV

Time

Figure 10-7 Free-Running Counter Operation

When compare match is selected as the TCNT clearing source, the TCNT counter for the

relevant channel performs periodic count operation. The TGR register for setting the period is

designated as an output compare register, and counter clearing by compare match is selected

by means of bits CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts

up-count operation as periodic counter when the corresponding bit in TSTR is set to 1. When

the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared

to H'0000.

If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an

interrupt. After a compare match, TCNT starts counting up again from H'0000.

341

Figure 10-8 illustrates periodic counter operation.

TCNT value

TGR

H'0000

CST bit

TGF

Time

Counter cleared by TGR

compare match

Flag cleared by software or

DTC activation

Figure 10-8 Periodic Counter Operation

Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the

corresponding output pin using compare match.

• Example of setting procedure for waveform output by compare match

Figure 10-9 shows an example of the setting procedure for waveform output by compare match

Select waveform output mode

Output selection

Set output timing

Start count operation

[1]

[2]

[3]

[1] Select initial value 0 output or 1 output, and

compare match output value 0 output, 1 output,

or toggle output, by means of TIOR. The set

initial value is output at the TIOC pin until the

first compare match occurs.

[2] Set the timing for compare match generation in

TGR.

[3] Set the CST bit in TSTR to 1 to start the count

operation.

Figure 10-9 Example Of Setting Procedure For Waveform Output By Compare Match

342

• Examples of waveform output operation

Figure 10-10 shows an example of 0 output/1 output.

In this example TCNT has been designated as a free-running counter, and settings have been

made so that 1 is output by compare match A, and 0 is output by compare match B. When the

set level and the pin level coincide, the pin level does not change.

TCNT value

H'FFFF

H'0000

TIOCA

TIOCB

Time

TGRA

TGRB

No change No change

1 output

0 output

Figure 10-10 Example of 0 Output/1 Output Operation

Figure 10-11 shows an example of toggle output.

In this example TCNT has been designated as a periodic counter (with counter clearing

performed by compare match B), and settings have been made so that output is toggled by both

compare match A and compare match B.

TCNT value

H'FFFF

H'0000

TIOCB

TIOCA

Time

TGRB

TGRA

Toggle output

Counter cleared by TGRB compare match

Figure 10-11 Example of Toggle Output Operation

343

Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC

pin input edge.

Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0, 1, 3,

and 4, it is also possible to specify another channel’s counter input clock or compare match signal

as the input capture source.

Note: When another channel’s counter input clock is used as the input capture input for channels

0 and 3, ø/1 should not be selected as the counter input clock used for input capture input.

Input capture will not be generated if ø/1 is selected.

• Example of input capture operation setting procedure

Figure 10-12 shows an example of the input capture operation setting procedure.

Select input capture input

Input selection

Start count

[1]

[2]

[1] Designate TGR as an input capture register by

means of TIOR, and select rising edge, falling

edge, or both edges as the input capture source

and input signal edge.

[2] Set the CST bit in TSTR to 1 to start the count

operation.

Figure 10-12 Example of Input Capture Operation Setting Procedure

344

• Example of input capture operation

Figure 10-13 shows an example of input capture operation.

In this example both rising and falling edges have been selected as the TIOCA pin input

capture input edge, falling edge has been selected as the TIOCB pin input capture input edge,

and counter clearing by TGRB input capture has been designated for TCNT.

TCNT value

H'0180

H'0000

TIOCA

TGRA

Time

H'0010

H'0005

Counter cleared by TIOCB

input (falling edge)

H'0160

H'0005 H'0160 H'0010

TGRB H'0180

TIOCB

Figure 10-13 Example of Input Capture Operation

345

10.4.3 Synchronous Operation

In synchronous operation, the values in a number of TCNT counters can be rewritten

simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared

simultaneously by making the appropriate setting in TCR (synchronous clearing).

Synchronous operation enables TGR to be incremented with respect to a single time base.

Channels 0 to 5 can all be designated for synchronous operation.

Example of Synchronous Operation Setting Procedure: Figure 10-14 shows an example of the

synchronous operation setting procedure.

Set synchronous

operation

Synchronous operation

selection

Set TCNT

Synchronous presetting

[1]

[2]

Synchronous clearing

Select counter

clearing source

[3]

Start count [5]

Set synchronous

counter clearing

[4]

Start count [5]

Clearing

sourcegeneration

channel?

Yes

[1]

[2]

[3]

[4]

[5]

Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous

operation.

When the TCNT counter of any of the channels designated for synchronous operation is

written to, the same value is simultaneously written to the other TCNT counters.

Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare,

etc.

Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing

source.

Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation.

Figure 10-14 Example of Synchronous Operation Setting Procedure

346

Example of Synchronous Operation: Figure 10-15 shows an example of synchronous operation.

In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to

2, TGR0B compare match has been set as the channel 0 counter clearing source, and synchronous

clearing has been set for the channel 1 and 2 counter clearing source.

Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this

time, synchronous presetting, and synchronous clearing by TGR0B compare match, is performed

for channel 0 to 2 TCNT counters, and the data set in TGR0B is used as the PWM cycle.

For details of PWM modes, see section 10.4.6, PWM Modes.

TCNT0 to TCNT2 values

H'0000

TIOC0A

TIOC1A

Time

TGR0B

Synchronous clearing by TGR0B compare match

TGR2A

TGR1A

TGR2B

TGR0A

TGR1B

TIOC2A

Figure 10-15 Example of Synchronous Operation

347

10.4.4 Buffer Operation

Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer

registers.

Buffer operation differs depending on whether TGR has been designated as an input capture

Table 10-5 shows the register combinations used in buffer operation.

Table 10-5 Register Combinations in Buffer Operation

Channel Timer General Register Buffer Register

0 TGR0A TGR0C

TGR0B TGR0D

3 TGR3A TGR3C

TGR3B TGR3D

• When TGR is an output compare register

When a compare match occurs, the value in the buffer register for the corresponding channel is

transferred to the timer general register.

This operation is illustrated in figure 10-16.

Buffer register Timer general

Compare match signal

Figure 10-16 Compare Match Buffer Operation

348

• When TGR is an input capture register

When input capture occurs, the value in TCNT is transferred to TGR and the value previously

held in the timer general register is transferred to the buffer register.

This operation is illustrated in figure 10-17.

Buffer register Timer general

Input capture

signal

Figure 10-17 Input Capture Buffer Operation

Example of Buffer Operation Setting Procedure: Figure 10-18 shows an example of the buffer

operation setting procedure.

Select TGR function

Buffer operation

Set buffer operation

Start count

[1]

[2]

[3]

[1] Designate TGR as an input capture register or

output compare register by means of TIOR.

[2] Designate TGR for buffer operation with bits

BFA and BFB in TMDR.

[3] Set the CST bit in TSTR to 1 to start the count

operation.

Figure 10-18 Example of Buffer Operation Setting Procedure

349

Examples of Buffer Operation

• When TGR is an output compare register

Figure 10-19 shows an operation example in which PWM mode 1 has been designated for

channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used

in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0

output at compare match B.

As buffer operation has been set, when compare match A occurs the output changes and the

value in buffer register TGRC is simultaneously transferred to timer general register TGRA.

This operation is repeated each time compare match A occurs.

For details of PWM modes, see section 10.4.6, PWM Modes.

TCNT value

TGR0B

H'0000

TGR0C

Time

TGR0A

H'0200 H'0520

TIOCA

H'0200

H'0450 H'0520

H'0450

TGR0A H'0450H'0200

Transfer

Figure 10-19 Example of Buffer Operation (1)

350

• When TGR is an input capture register

Figure 10-20 shows an operation example in which TGRA has been designated as an input

capture register, and buffer operation has been designated for TGRA and TGRC.

Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling

edges have been selected as the TIOCA pin input capture input edge.

As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of

input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC.

TCNT value

H'09FB

H'0000

TGRC

Time

H'0532

TIOCA

TGRA H'0F07H'0532

H'0F07

H'0532

H'0F07

H'09FB

Figure 10-20 Example of Buffer Operation (2)

351

10.4.5 Cascaded Operation

In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit

counter.

This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow

of TCNT2 (TCNT5) as set in bits TPSC2 to TPSC0 in TCR.

Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.

Table 10-6 shows the register combinations used in cascaded operation.

Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid

and the counter operates independently in phase counting mode.

Table 10-6 Cascaded Combinations

Combination Upper 16 Bits Lower 16 Bits

Channels 1 and 2 TCNT1 TCNT2

Channels 4 and 5 TCNT4 TCNT5

Example of Cascaded Operation Setting Procedure: Figure 10-21 shows an example of the

setting procedure for cascaded operation.

Set cascading

Cascaded operation

Start count

[1]

[2]

[1] Set bits TPSC2 to TPSC0 in the channel 1

(channel 4) TCR to B’111 to select TCNT2

(TCNT5) overflow/underflow counting.

[2] Set the CST bit in TSTR for the upper and lower

channel to 1 to start the count operation.

Figure 10-21 Cascaded Operation Setting Procedure

352

Examples of Cascaded Operation: Figure 10-22 illustrates the operation when counting upon

TCNT2 overflow/underflow has been set for TCNT1, TGR1A and TGR2A have been designated

as input capture registers, and TIOC pin rising edge has been selected.

When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of

the 32-bit data are transferred to TGR1A, and the lower 16 bits to TGR2A.

TCNT2

clock

TCNT2 H'FFFF H'0000 H'0001

TIOCA1,

TIOCA2

TGR1A H'03A2

TGR2A H'0000

TCNT1

clock

TCNT1 H'03A1 H'03A2

Figure 10-22 Example of Cascaded Operation (1)

Figure 10-23 illustrates the operation when counting upon TCNT2 overflow/underflow has been

set for TCNT1, and phase counting mode has been designated for channel 2.

TCNT1 is incremented by TCNT2 overflow and decremented by TCNT2 underflow.

TCLKA

TCNT2 FFFD

TCNT1 0001

TCLKB

FFFE FFFF 0000 0001 0002 0001 0000 FFFF

0000 0000

Figure 10-23 Example of Cascaded Operation (2)

353

10.4.6 PWM Modes

In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be

selected as the output level in response to compare match of each TGR.

Designating TGR compare match as the counter clearing source enables the period to be set in that

also possible.

There are two PWM modes, as described below.

• PWM mode 1

PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and

TGRC with TGRD. The output specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR is

output from the TIOCA and TIOCC pins at compare matches A and C, and the output

specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR is output at compare matches B

and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired

TGRs are identical, the output value does not change when a compare match occurs.

In PWM mode 1, a maximum 8-phase PWM output is possible.

• PWM mode 2

PWM output is generated using one TGR as the cycle register and the others as duty registers.

The output specified in TIOR is performed by means of compare matches. Upon counter

clearing by a synchronization register compare match, the output value of each pin is the initial

value set in TIOR. If the set values of the cycle and duty registers are identical, the output

value does not change when a compare match occurs.

In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with

synchronous operation.

The correspondence between PWM output pins and registers is shown in table 10-7.

354

Table 10-7 PWM Output Registers and Output Pins

Output Pins

Channel Registers PWM Mode 1 PWM Mode 2

0 TGR0A TIOCA0 TIOCA0

TGR0B TIOCB0

TGR0C TIOCC0 TIOCC0

TGR0D TIOCD0

1 TGR1A TIOCA1 TIOCA1

TGR1B TIOCB1

2 TGR2A TIOCA2 TIOCA2

TGR2B TIOCB2

3 TGR3A TIOCA3 TIOCA3

TGR3B TIOCB3

TGR3C TIOCC3 TIOCC3

TGR3D TIOCD3

4 TGR4A TIOCA4 TIOCA4

TGR4B TIOCB4

5 TGR5A TIOCA5 TIOCA5

TGR5B TIOCB5

Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set.

355

Example of PWM Mode Setting Procedure: Figure 10-24 shows an example of the PWM mode

setting procedure.

Select counter clock

PWM mode

Select counter clearing source

Select waveform output level

[1]

[2]

[3]

Set TGR [4]

Set PWM mode [5]

Start count [6]

[1] Select the counter clock with bits TPSC2 to

TPSC0 in TCR. At the same time, select the

input clock edge with bits CKEG1 and CKEG0 in

TCR.

[2] Use bits CCLR2 to CCLR0 in TCR to select the

TGR to be used as the TCNT clearing source.

[3] Use TIOR to designate the TGR as an output

compare register, and select the initial value and

output value.

[4] Set the cycle in the TGR selected in [2], and set

the duty in the other the TGR.

[5] Select the PWM mode with bits MD3 to MD0 in

TMDR.

[6] Set the CST bit in TSTR to 1 to start the count

operation.

Figure 10-24 Example of PWM Mode Setting Procedure

Examples of PWM Mode Operation: Figure 10-25 shows an example of PWM mode 1

operation.

In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA

initial output value and output value, and 1 is set as the TGRB output value.

In this case, the value set in TGRA is used as the period, and the values set in TGRB registers as

the duty.

356

TCNT value

TGRA

H'0000

TIOCA

Time

TGRB

Counter cleared by

TGRA compare match

Figure 10-25 Example of PWM Mode Operation (1)

Figure 10-26 shows an example of PWM mode 2 operation.

In this example, synchronous operation is designated for channels 0 and 1, TGR1B compare match

is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output

value of the other TGR registers (TGR0A to TGR0D, TGR1A), to output a 5-phase PWM

waveform.

In this case, the value set in TGR1B is used as the cycle, and the values set in the other TGRs as

the duty.

TCNT value

TGR1B

H'0000

TIOCA0

Counter cleared by TGR1B

compare match

TGR1A

TGR0D

TGR0C

TGR0B

TGR0A

TIOCB0

TIOCC0

TIOCD0

TIOCA1

Time

Figure 10-26 Example of PWM Mode Operation (2)

357

Figure 10-27 shows examples of PWM waveform output with 0% duty and 100% duty in PWM

mode.

TCNT value

TGRA

H'0000

TIOCA

Time

TGRB

0% duty

TGRB rewritten

TGRB

rewritten

TGRB rewritten

TCNT value

TGRA

H'0000

TIOCA

Time

TGRB

100% duty

TGRB rewritten

Output does not change when cycle register and duty register

compare matches occur simultaneously

TCNT value

TGRA

H'0000

TIOCA

Time

TGRB

100% duty

TGRB rewritten

Output does not change when cycle register and duty

0% duty

Figure 10-27 Example of PWM Mode Operation (3)

358

10.4.7 Phase Counting Mode

In phase counting mode, the phase difference between two external clock inputs is detected and

TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5.

When phase counting mode is set, an external clock is selected as the counter input clock and

TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits

CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of

TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be

used.

When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow

occurs while TCNT is counting down, the TCFU flag is set.

The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of

whether TCNT is counting up or down.

Table 10-8 shows the correspondence between external clock pins and channels.

Table 10-8 Phase Counting Mode Clock Input Pins

External Clock Pins

Channels A-Phase B-Phase

When channel 1 or 5 is set to phase counting mode TCLKA TCLKB

When channel 2 or 4 is set to phase counting mode TCLKC TCLKD

Example of Phase Counting Mode Setting Procedure: Figure 10-28 shows an example of the

phase counting mode setting procedure.

Select phase counting mode

Phase counting mode

Start count

[1]

[2]

[1] Select phase counting mode with bits MD3 to

MD0 in TMDR.

[2] Set the CST bit in TSTR to 1 to start the count

operation.

Figure 10-28 Example of Phase Counting Mode Setting Procedure

359

Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or

down according to the phase difference between two external clocks. There are four modes,

according to the count conditions.

• Phase counting mode 1

Figure 10-29 shows an example of phase counting mode 1 operation, and table 10-9

summarizes the TCNT up/down-count conditions.

TCNT value

Time

Down-countUp-count

TCLKA (channels 1 and 5)

TCLKC (channels 2 and 4)

TCLKB (channels 1 and 5)

TCLKD (channels 2 and 4)

Figure 10-29 Example of Phase Counting Mode 1 Operation

Table 10-9 Up/Down-Count Conditions in Phase Counting Mode 1

TCLKA (Channels 1 and 5)

TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5)

TCLKD (Channels 2 and 4) Operation

High level Up-count

Low level

High level

High level Down-count

Low level

High level

Low level

Legend: Rising edge

: Falling edge

360

• Phase counting mode 2

Figure 10-30 shows an example of phase counting mode 2 operation, and table 10-10

summarizes the TCNT up/down-count conditions.

TCNT value

Time

Down-countUp-count

TCLKA (Channels 1 and 5)

TCLKC (Channels 2 and 4)

TCLKB (Channels 1 and 5)

TCLKD (Channels 2 and 4)

Figure 10-30 Example of Phase Counting Mode 2 Operation

Table 10-10 Up/Down-Count Conditions in Phase Counting Mode 2

TCLKA (Channels 1 and 5)

TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5)

TCLKD (Channels 2 and 4) Operation

High level Don’t care

Low level Don’t care

High level Up-count

High level Don’t care

Low level Don’t care

High level Don’t care

Low level Down-count

Legend: Rising edge

: Falling edge

361

• Phase counting mode 3

Figure 10-31 shows an example of phase counting mode 3 operation, and table 10-11

summarizes the TCNT up/down-count conditions.

TCNT value

Time

Up-count

TCLKA (channels 1 and 5)

TCLKC (channels 2 and 4)

TCLKB (channels 1 and 5)

TCLKD (channels 2 and 4)

Down-count

Figure 10-31 Example of Phase Counting Mode 3 Operation

Table 10-11 Up/Down-Count Conditions in Phase Counting Mode 3

TCLKA (Channels 1 and 5)

TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5)

TCLKD (Channels 2 and 4) Operation

High level Don’t care

Low level Don’t care

High level Up-count

High level Down-count

Low level Don’t care

High level Don’t care

Low level Don’t care

Legend: Rising edge

: Falling edge

362

• Phase counting mode 4

Figure 10-32 shows an example of phase counting mode 4 operation, and table 10-12

summarizes the TCNT up/down-count conditions.

Time

TCLKA (channels 1 and 5)

TCLKC (channels 2 and 4)

TCLKB (channels 1 and 5)

TCLKD (channels 2 and 4)

Up-count Down-count

TCNT value

Figure 10-32 Example of Phase Counting Mode 4 Operation

Table 10-12 Up/Down-Count Conditions in Phase Counting Mode 4

TCLKA (Channels 1 and 5)

TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5)

TCLKD (Channels 2 and 4) Operation

High level Up-count

Low level

Low level Don’t care

High level

High level Down-count

Low level

High level Don’t care

Low level

Legend: Rising edge

: Falling edge

363

Phase Counting Mode Application Example: Figure 10-33 shows an example in which phase

counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo

motor 2-phase encoder pulses in order to detect the position or speed.

Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input

to TCLKA and TCLKB.

Channel 0 operates with TCNT counter clearing by TGR0C compare match; TGR0A and TGR0C

are used for the compare match function, and are set with the speed control period and position

control period. TGR0B is used for input capture, with TGR0B and TGR0D operating in buffer

mode. The channel 1 counter input clock is designated as the TGR0B input capture source, and

detection of the pulse width of 2-phase encoder 4-multiplication pulses is performed.

TGR1A and TGR1B for channel 1 are designated for input capture, channel 0 TGR0A and

TGR0C compare matches are selected as the input capture source, and store the up/down-counter

values for the control periods.

This procedure enables accurate position/speed detection to be achieved.

364

TCNT1

TCNT0

Channel 1

TGR1A

(speed period capture)

TGR0A (speed control period)

TGR1B

(position period capture)

TGR0C

(position control period)

TGR0B (pulse width capture)

TGR0D (buffer operation)

Channel 0

TCLKA

TCLKB

Edge

detection

circuit

–

Figure 10-33 Phase Counting Mode Application Example

365

10.5 Interrupts

10.5.1 Interrupt Sources and Priorities

There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT

overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled

bit, allowing generation of interrupt request signals to be enabled or disabled individually.

When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the

corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The

interrupt request is cleared by clearing the status flag to 0.

Relative channel priorities can be changed by the interrupt controller, but the priority order within

a channel is fixed. For details, see section 5, Interrupt Controller.

Table 10-13 lists the TPU interrupt sources.

366

Table 10-13 TPU Interrupts

Channel Interrupt Source Description DTC Activation Priority

0 TGI0A TGR0A input capture/compare match Possible High

TGI0B TGR0B input capture/compare match Possible

TGI0C TGR0C input capture/compare match Possible

TGI0D TGR0D input capture/compare match Possible

TCI0V TCNT0 overflow Not possible

1 TGI1A TGR1A input capture/compare match Possible

TGI1B TGR1B input capture/compare match Possible

TCI1V TCNT1 overflow Not possible

TCI1U TCNT1 underflow Not possible

2 TGI2A TGR2A input capture/compare match Possible

TGI2B TGR2B input capture/compare match Possible

TCI2V TCNT2 overflow Not possible

TCI2U TCNT2 underflow Not possible

3 TGI3A TGR3A input capture/compare match Possible

TGI3B TGR3B input capture/compare match Possible

TGI3C TGR3C input capture/compare match Possible

TGI3D TGR3D input capture/compare match Possible

TCI3V TCNT3 overflow Not possible

4 TGI4A TGR4A input capture/compare match Possible

TGI4B TGR4B input capture/compare match Possible

TCI4V TCNT4 overflow Not possible

TCI4U TCNT4 underflow Not possible

5 TGI5A TGR5A input capture/compare match Possible

TGI5B TGR5B input capture/compare match Possible

TCI5V TCNT5 overflow Not possible

TCI5U TCNT5 underflow Not possible Low

Note: This table shows the initial state immediately after a reset. The relative channel priorities

can be changed by the interrupt controller.

367

Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is

set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare

match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The

TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each

for channels 1, 2, 4, and 5.

Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the

TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt

request is cleared by clearing the TCFV flag to 0. The TPU has six overflow interrupts, one for

each channel.

Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the

TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt

request is cleared by clearing the TCFU flag to 0. The TPU has four underflow interrupts, one

each for channels 1, 2, 4, and 5.

10.5.2 DTC Activation

DTC Activation: The DTC can be activated by the TGR input capture/compare match interrupt

for a channel. For details, see section 8, Data Transfer Controller (DTC).

A total of 16 TPU input capture/compare match interrupts can be used as DTC activation sources,

four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.

10.5.3 A/D Converter Activation

The A/D converter can be activated by the TGRA input capture/compare match for a channel.

If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a

TGRA input capture/compare match on a particular channel, a request to start A/D conversion is

sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D

converter side at this time, A/D conversion is started.

In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D

converter conversion start sources, one for each channel.

368

10.6 Operation Timing

10.6.1 Input/Output Timing

TCNT Count Timing: Figure 10-34 shows TCNT count timing in internal clock operation, and

figure 10-35 shows TCNT count timing in external clock operation.

TCNT

input clock

Internal clock

N–1 N N+1 N+2

Falling edge Rising edge

Figure 10-34 Count Timing in Internal Clock Operation

TCNT

input clock

External clock

N–1 N N+1 N+2

Rising edge Falling edge

Falling edge

Figure 10-35 Count Timing in External Clock Operation

369

Output Compare Output Timing: A compare match signal is generated in the final state in

which TCNT and TGR match (the point at which the count value matched by TCNT is updated).

When a compare match signal is generated, the output value set in TIOR is output at the output

compare output pin. After a match between TCNT and TGR, the compare match signal is not

generated until the TCNT input clock is generated.

Figure 10-36 shows output compare output timing.

TGR

TCNT

input clock

N N+1

Compare

match signal

TIOC pin

Figure 10-36 Output Compare Output Timing

Input Capture Signal Timing: Figure 10-37 shows input capture signal timing.

TCNT

Input capture

input

N N+1 N+2

NN+2

TGR

Input capture

signal

Figure 10-37 Input Capture Input Signal Timing

370

Timing for Counter Clearing by Compare Match/Input Capture: Figure 10-38 shows the

timing when counter clearing by compare match occurrence is specified, and figure 10-39 shows

the timing when counter clearing by input capture occurrence is specified.

TCNT

Counter

clear signal

Compare

match signal

TGR N

N H'0000

Figure 10-38 Counter Clear Timing (Compare Match)

TCNT

Counter clear

signal

Input capture

signal

TGR

N H'0000

Figure 10-39 Counter Clear Timing (Input Capture)

371

Buffer Operation Timing: Figures 10-40 and 10-41 show the timing in buffer operation.

TGRA,

TGRB

Compare

match signal

TCNT

TGRC,

TGRD

n n+1

Figure 10-40 Buffer Operation Timing (Compare Match)

TGRA,

TGRB

TCNT

Input capture

signal

TGRC,

TGRD

n N+1

N N+1

Figure 10-41 Buffer Operation Timing (Input Capture)

372

10.6.2 Interrupt Signal Timing

TGF Flag Setting Timing in Case of Compare Match: Figure 10-42 shows the timing for

setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal

timing.

TGR

TCNT

TCNT input

clock

N N+1

Compare

match signal

TGF flag

TGI interrupt

Figure 10-42 TGI Interrupt Timing (Compare Match)

373

TGF Flag Setting Timing in Case of Input Capture: Figure 10-43 shows the timing for setting

of the TGF flag in TSR by input capture occurrence, and TGI interrupt request signal timing.

TGR

TCNT

Input capture

signal

TGF flag

TGI interrupt

Figure 10-43 TGI Interrupt Timing (Input Capture)

374

TCFV Flag/TCFU Flag Setting Timing: Figure 10-44 shows the timing for setting of the TCFV

flag in TSR by overflow occurrence, and TCIV interrupt request signal timing.

Figure 10-45 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and

TCIU interrupt request signal timing.

Overflow

signal

TCNT

(overflow)

TCNT input

clock

H'FFFF H'0000

TCFV flag

TCIV interrupt

Figure 10-44 TCIV Interrupt Setting Timing

Underflow signal

TCNT

(underflow)

TCNT

input clock

H'0000 H'FFFF

TCFU flag

TCIU interrupt

Figure 10-45 TCIU Interrupt Setting Timing

375

Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing

0 to it. When the DTC is activated, the flag is cleared automatically. Figure 10-46 shows the

timing for status flag clearing by the CPU, and figure 10-47 shows the timing for status flag

clearing by the DTC.

Status flag

Write signal

Address

TSR address

Interrupt

request

signal

TSR write cycle

T1 T2

Figure 10-46 Timing for Status Flag Clearing by CPU

Interrupt

request

signal

Status flag

Address

Source address

DTC

read cycle

T1 T2

Destination

address

T1 T2

DTC

write cycle

Figure 10-47 Timing for Status Flag Clearing by DTC Activation

376

10.7 Usage Notes

Note that the kinds of operation and contention described below occur during TPU operation.

Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of

single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not

operate properly with a narrower pulse width.

In phase counting mode, the phase difference and overlap between the two input clocks must be at

least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10-48 shows the input clock

conditions in phase counting mode.

Overlap

Phase

differ-

ence

Phase

differ-

ence

Overlap

TCLKA

(TCLKC)

TCLKB

(TCLKD)

Pulse width Pulse width

Notes: Phase difference and overlap

Pulse width : 1.5 states or more

: 2.5 states or more

Figure 10-48 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode

Caution on Period Setting: When counter clearing by compare match is set, TCNT is cleared in

the final state in which it matches the TGR value (the point at which the count value matched by

TCNT is updated). Consequently, the actual counter frequency is given by the following formula:

f = ø

(N + 1)

Where f : Counter frequency

ø : Operating frequency

N : TGR set value

377

Contention between TCNT Write and Clear Operations: If the counter clear signal is

generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT

write is not performed.

Figure 10-49 shows the timing in this case.

Counter clear

signal

Write signal

Address

TCNT address

TCNT

TCNT write cycle

T1 T2

N H'0000

Figure 10-49 Contention between TCNT Write and Clear Operations

378

Contention between TCNT Write and Increment Operations: If incrementing occurs in the T2

state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented.

Figure 10-50 shows the timing in this case.

TCNT input

clock

Write signal

Address

TCNT address

TCNT

TCNT write cycle

T1 T2

N M

TCNT write data

Figure 10-50 Contention between TCNT Write and Increment Operations

379

Contention between TGR Write and Compare Match: If a compare match occurs in the T2

state of a TGR write cycle, the TGR write takes precedence and the compare match signal is

inhibited. A compare match does not occur even if the same value as before is written.

Figure 10-51 shows the timing in this case.

Compare

match signal

Write signal

Address

TGR address

TCNT

TGR write cycle

T1 T2

N M

TGR write data

TGR

N N+1

Inhibited

Figure 10-51 Contention between TGR Write and Compare Match

380

Contention between Buffer Register Write and Compare Match: If a compare match occurs in

the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the

data prior to the write.

Figure 10-52 shows the timing in this case.

Compare

match signal

Write signal

Address

Buffer register

address

Buffer

TGR write cycle

T1 T2

TGR

N M

Buffer register write data

Figure 10-52 Contention between Buffer Register Write and Compare Match

381

Contention between TGR Read and Input Capture: If the input capture signal is generated in

the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer.

Figure 10-53 shows the timing in this case.

Input capture

signal

Read signal

Address

TGR address

TGR

TGR read cycle

T1 T2

Internal

data bus

X M

Figure 10-53 Contention between TGR Read and Input Capture

382

Contention between TGR Write and Input Capture: If the input capture signal is generated in

the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to

TGR is not performed.

Figure 10-54 shows the timing in this case.

Input capture

signal

Write signal

Address

TCNT

TGR write cycle

T1 T2

TGR

TGR address

Figure 10-54 Contention between TGR Write and Input Capture

383

Contention between Buffer Register Write and Input Capture: If the input capture signal is

generated in the T2 state of a buffer write cycle, the buffer operation takes precedence and the

write to the buffer register is not performed.

Figure 10-55 shows the timing in this case.

Input capture

signal

Write signal

Address

TCNT

Buffer register write cycle

T1 T2

TGR

Buffer

Buffer register

address

Figure 10-55 Contention between Buffer Register Write and Input Capture

384

Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and

counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing

takes precedence.

Figure 10-56 shows the operation timing when a TGR compare match is specified as the clearing

source, and H'FFFF is set in TGR.

Counter

clear signal

TCNT input

clock

TCNT

TGF

Disabled

TCFV

H'FFFF H'0000

Figure 10-56 Contention between Overflow and Counter Clearing

385

Contention between TCNT Write and Overflow/Underflow: If there is an up-count or down-

count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write

takes precedence and the TCFV/TCFU flag in TSR is not set.

Figure 10-57 shows the operation timing when there is contention between TCNT write and

overflow.

Write signal

Address

TCNT address

TCNT

TCNT write cycle

T1 T2

H'FFFF M

TCNT write data

TCFV flag

Figure 10-57 Contention between TCNT Write and Overflow

Multiplexing of I/O Pins: In the H8S/2646 Series, the TCLKA input pin is multiplexed with the

TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the

TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is

input, compare match output should not be performed from a multiplexed pin.

Interrupts and Module Stop Mode: If module stop mode is entered when an interrupt has been

requested, it will not be possible to clear the CPU interrupt source or the DTC activation source.

Interrupts should therefore be disabled before entering module stop mode.

386

387

Section 11 Programmable Pulse Generator (PPG)

11.1 Overview

The H8S/2646 Series has a built-in programmable pulse generator (PPG) that provides pulse

outputs by using the 16-bit timer-pulse unit (TPU) as a time base. The PPG pulse outputs are

divided into 4-bit groups (group 3 and group 2) that can operate both simultaneously and

independently.

11.1.1 Features

PPG features are listed below.

• 8-bit output data

 Maximum 8-bit data can be output, and output can be enabled on a bit-by-bit basis

• Two output groups

 Output trigger signals can be selected in 4-bit groups to provide up to two different 4-bit

outputs

• Selectable output trigger signals

 Output trigger signals can be selected for each group from the compare match signals of

four TPU channels

• Non-overlap mode

 A non-overlap margin can be provided between pulse outputs

• Can operate together with the data transfer controller (DTC)

 The compare match signals selected as output trigger signals can activate the DTC for

sequential output of data without CPU intervention

• Settable inverted output

 Inverted data can be output for each group

• Module stop mode can be set

 As the initial setting, PPG operation is halted. Register access is enabled by exiting module

stop mode

388

11.1.2 Block Diagram

Figure 11-1 shows a block diagram of the PPG.

Compare match signals

PO15

PO14

PO13

PO12

PO11

PO10

PO9

PO8

Legend : PPG output mode register

: PPG output control register

: Next data enable register H

: Next data enable register L

: Next data register H

: Next data register L

: Output data register H

: Output data register L

Internal

data bus

PMR

PCR

NDERH

NDERL

NDRH

NDRL

PODRH

PODRL

Pulse output

pins, group 3

Pulse output

pins, group 2

Pulse output

pins, group 1

Pulse output

pins, group 0

PODRH

PODRL

NDRH

NDRL

Control logic

NDERH

PMR

NDERL

PCR

Figure 11-1 Block Diagram of PPG

389

11.1.3 Pin Configuration

Table 11-1 summarizes the PPG pins.

Table 11-1 PPG Pins

Name Symbol I/O Function

Pulse output 8 PO8 Output Group 2 pulse output

Pulse output 9 PO9 Output

Pulse output 10 PO10 Output

Pulse output 11 PO11 Output

Pulse output 12 PO12 Output Group 3 pulse output

Pulse output 13 PO13 Output

Pulse output 14 PO14 Output

Pulse output 15 PO15 Output

390

11.1.4 Registers

Table 11-2 summarizes the PPG registers.

Table 11-2 PPG Registers

Name Abbreviation R/W Initial Value Address*1

PPG output control register PCR R/W H'FF H'FE26

PPG output mode register PMR R/W H'F0 H'FE27

Next data enable register H NDERH R/W H'00 H'FE28

Next data enable register L*4NDERL R/W H'00 H'FE29

Output data register H PODRH R/(W)*2H'00 H'FE2A

Output data register L PODRL R/(W) *2H'00 H'FE2B

Next data register H NDRH R/W H'00 H'FE2C*3

H'FE2E

Next data register L*4NDRL R/W H'00 H'FE2D*3

H'FE2F

Port 1 data direction register P1DDR W H'00 H'FE30

Module stop control register A MSTPCRA R/W H'3F H'FDE8

Notes: *1 Lower 16 bits of the address.

*2 Bits used for pulse output cannot be written to.

*3 When the same output trigger is selected for pulse output groups 2 and 3 by the PCR

setting, the NDRH address is H'FE2C. When the output triggers are different, the

NDRH address is H'FE2E for group 2 and H'FE2C for group 3.

Similarly, when the same output trigger is selected for pulse output groups 0 and 1 by

the PCR setting, the NDRL address is H'FE2D. When the output triggers are different,

the NDRL address is H'FE2F for group 0 and H'FE2D for group 1.

*4 The H8S/2646 Series has no pins corresponding to pulse output groups 0 and 1.

391

11.2 Register Descriptions

11.2.1 Next Data Enable Registers H and L (NDERH, NDERL)

NDERH

Bit:76543210

NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

NDERL

Bit:76543210

NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

NDERH and NDERL are 8-bit readable/writable registers that enable or disable pulse output on a

bit-by-bit basis.

If a bit is enabled for pulse output by NDERH or NDERL, the NDR value is automatically

transferred to the corresponding PODR bit when the TPU compare match event specified by PCR

occurs, updating the output value. If pulse output is disabled, the bit value is not transferred from

NDR to PODR and the output value does not change.

NDERH and NDERL are each initialized to H'00 by a reset and in hardware standby mode. They

are not initialized in software standby mode.

NDERH Bits 7 to 0—Next Data Enable 15 to 8 (NDER15 to NDER8): These bits enable or

disable pulse output on a bit-by-bit basis.

Bits 7 to 0

NDER15 to NDER8 Description

0 Pulse outputs PO15 to PO8 are disabled (NDR15 to NDR8 are not

transferred to POD15 to POD8) (Initial value)

1 Pulse outputs PO15 to PO8 are enabled (NDR15 to NDR8 are transferred

to POD15 to POD8)

392

NDERL Bits 7 to 0—Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or

disable pulse output on a bit-by-bit basis.

Bits 7 to 0

NDER7 to NDER0 Description

0 Pulse outputs PO7 to PO0 are disabled (NDR7 to NDR0 are not

transferred to POD7 to POD0) (Initial value)

1 Pulse outputs PO7 to PO0 are enabled (NDR7 to NDR0 are transferred to

POD7 to POD0)

11.2.2 Output Data Registers H and L (PODRH, PODRL)

PODRH

Bit:76543210

POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8

Initial value : 0 0 0 0 0 0 0 0

R/W : R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*

PODRL

Bit:76543210

POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0

Initial value : 0 0 0 0 0 0 0 0

R/W : R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*

Note: *A bit that has been set for pulse output by NDER is read-only.

PODRH and PODRL are 8-bit readable/writable registers that store output data for use in pulse

output. However, the H8S/2646 Series has no pins corresponding to PODRL.

393

11.2.3 Next Data Registers H and L (NDRH, NDRL)

NDRH and NDRL are 8-bit readable/writable registers that store the next data for pulse output.

During pulse output, the contents of NDRH and NDRL are transferred to the corresponding bits in

PODRH and PODRL when the TPU compare match event specified by PCR occurs. The NDRH

and NDRL addresses differ depending on whether pulse output groups have the same output

trigger or different output triggers. For details see section 11.2.4, Notes on NDR Access.

NDRH and NDRL are each initialized to H'00 by a reset and in hardware standby mode. They are

not initialized in software standby mode.

11.2.4 Notes on NDR Access

The NDRH and NDRL addresses differ depending on whether pulse output groups have the same

output trigger or different output triggers.

Same Trigger for Pulse Output Groups: If pulse output groups 2 and 3 are triggered by the

same compare match event, the NDRH address is H'FE2C. The upper 4 bits belong to group 3

and the lower 4 bits to group 2. Address H'FE2E consists entirely of reserved bits that cannot be

modified and are always read as 1.

Address H'FE2C

Bit:76543210

NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

Address H'FE2E

Bit:76543210

————————

Initial value : 1 1 1 1 1 1 1 1

R/W:————————

If pulse output groups 0 and 1 are triggered by the same compare match event, the NDRL address

is H'FE2D. The upper 4 bits belong to group 1 and the lower 4 bits to group 0. Address H'FE2F

consists entirely of reserved bits that cannot be modified and are always read as 1. However, the

H8S/2646 Series has no output pins corresponding to pulse output groups 0 and 1.

394

Address H'FE2D

Bit:76543210

NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

Address H'FE2F

Bit:76543210

————————

Initial value : 1 1 1 1 1 1 1 1

R/W:————————

Different Triggers for Pulse Output Groups: If pulse output groups 2 and 3 are triggered by

different compare match events, the address of the upper 4 bits in NDRH (group 3) is H'FE2C and

the address of the lower 4 bits (group 2) is H'FE2E. Bits 3 to 0 of address H'FE2C and bits 7 to 4

of address H'FE2E are reserved bits that cannot be modified and are always read as 1.

Address H'FE2C

Bit:76543210

NDR15 NDR14 NDR13 NDR12 — — — —

Initial value : 0 0 0 0 1 1 1 1

R/W : R/W R/W R/W R/W — — — —

Address H'FE2E

Bit:76543210

— — — — NDR11 NDR10 NDR9 NDR8

Initial value : 1 1 1 1 0 0 0 0

R/W : — — — — R/W R/W R/W R/W

If pulse output groups 0 and 1 are triggered by different compare match event, the address of the

upper 4 bits in NDRL (group 1) is H'FE2D and the address of the lower 4 bits (group 0) is

H'FE2F. Bits 3 to 0 of address H'FE2D and bits 7 to 4 of address H'FE2F are reserved bits that

cannot be modified and are always read as 1. However, the H8S/2646 Series has no output pins

corresponding to pulse output groups 0 and 1.

395

Address H'FE2D

Bit:76543210

NDR7 NDR6 NDR5 NDR4 — — — —

Initial value : 0 0 0 0 1 1 1 1

R/W : R/W R/W R/W R/W — — — —

Address H'FE2F

Bit:76543210

— — — — NDR3 NDR2 NDR1 NDR0

Initial value : 1 1 1 1 0 0 0 0

R/W : — — — — R/W R/W R/W R/W

11.2.5 PPG Output Control Register (PCR)

Bit:76543210

G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0

Initial value : 1 1 1 1 1 1 1 1

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

PCR is an 8-bit readable/writable register that selects output trigger signals for PPG outputs on a

group-by-group basis.

PCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits

select the compare match that triggers pulse output group 3 (pins PO15 to PO12).

Description

Bit 7

G3CMS1 Bit 6

G3CMS0 Output Trigger for Pulse Output Group 3

0 0 Compare match in TPU channel 0

1 Compare match in TPU channel 1

1 0 Compare match in TPU channel 2

1 Compare match in TPU channel 3 (Initial value)

396

Bits 5 and 4—Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits

select the compare match that triggers pulse output group 2 (pins PO11 to PO8).

Description

Bit 5

G2CMS1 Bit 4

G2CMS0 Output Trigger for Pulse Output Group 2

0 0 Compare match in TPU channel 0

1 Compare match in TPU channel 1

1 0 Compare match in TPU channel 2

1 Compare match in TPU channel 3 (Initial value)

Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits

select the compare match that triggers pulse output group 1 (pins PO7 to PO4). However, the

H8S/2646 Series has no output pins corresponding to pulse output group 1.

Description

Bit 3

G1CMS1 Bit 2

G1CMS0 Output Trigger for Pulse Output Group 1

0 0 Compare match in TPU channel 0

1 Compare match in TPU channel 1

1 0 Compare match in TPU channel 2

1 Compare match in TPU channel 3 (Initial value)

Bits 1 and 0—Group 0 Compare Match Select 1 and 0 (G0CMS1, G0CMS0): These bits

select the compare match that triggers pulse output group 0 (pins PO3 to PO0). However, the

H8S/2646 Series has no output pins corresponding to pulse output group 0.

Description

Bit 1

G0CMS1 Bit 0

G0CMS0 Output Trigger for Pulse Output Group 0

0 0 Compare match in TPU channel 0

1 Compare match in TPU channel 1

1 0 Compare match in TPU channel 2

1 Compare match in TPU channel 3 (Initial value)

397

11.2.6 PPG Output Mode Register (PMR)

Bit:76543210

G3INV G2INV G1INV G0INV G3NOV G2NOV G1NOV G0NOV

Initial value : 1 1 1 1 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

PMR is an 8-bit readable/writable register that selects pulse output inversion and non-overlapping

operation for each group.

The output trigger period of a non-overlapping operation PPG output waveform is set in TGRB

and the non-overlap margin is set in TGRA. The output values change at compare match A and B.

For details, see section 11.3.4, Non-Overlapping Pulse Output.

PMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—Group 3 Inversion (G3INV): Selects direct output or inverted output for pulse output

group 3 (pins PO15 to PO12).

Bit 7

G3INV Description

0 Inverted output for pulse output group 3 (low-level output at pin for a 1 in PODRH)

1 Direct output for pulse output group 3 (high-level output at pin for a 1 in PODRH)

(Initial value)

Bit 6—Group 2 Inversion (G2INV): Selects direct output or inverted output for pulse output

group 2 (pins PO11 to PO8).

Bit 6

G2INV Description

0 Inverted output for pulse output group 2 (low-level output at pin for a 1 in PODRH)

1 Direct output for pulse output group 2 (high-level output at pin for a 1 in PODRH)

(Initial value)

398

Bit 5—Group 1 Inversion (G1INV): Selects direct output or inverted output for pulse output

group 1 (pins PO7 to PO4). However, the H8S/2646 Series has no pins corresponding to pulse

output group 1.

Bit 5

G1INV Description

0 Inverted output for pulse output group 1 (low-level output at pin for a 1 in PODRL)

1 Direct output for pulse output group 1 (high-level output at pin for a 1 in PODRL)

(Initial value)

Bit 4—Group 0 Inversion (G0INV): Selects direct output or inverted output for pulse output

group 0 (pins PO3 to PO0). However, the H8S/2646 Series has no pins corresponding to pulse

output group 0.

Bit 4

G0INV Description

0 Inverted output for pulse output group 0 (low-level output at pin for a 1 in PODRL)

1 Direct output for pulse output group 0 (high-level output at pin for a 1 in PODRL)

(Initial value)

Bit 3—Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping operation for pulse

output group 3 (pins PO15 to PO12).

Bit 3

G3NOV Description

0 Normal operation in pulse output group 3 (output values updated at compare match A

in the selected TPU channel) (Initial value)

1 Non-overlapping operation in pulse output group 3 (independent 1 and 0 output at

compare match A or B in the selected TPU channel)

Bit 2—Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping operation for pulse

output group 2 (pins PO11 to PO8).

Bit 2

G2NOV Description

0 Normal operation in pulse output group 2 (output values updated at compare match A

in the selected TPU channel) (Initial value)

1 Non-overlapping operation in pulse output group 2 (independent 1 and 0 output at

compare match A or B in the selected TPU channel)

399

Bit 1—Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping operation for pulse

output group 1 (pins PO7 to PO4). However, the H8S/2646 Series has no pins corresponding to

pulse output group 1.

Bit 1

G1NOV Description

0 Normal operation in pulse output group 1 (output values updated at compare match A

in the selected TPU channel) (Initial value)

1 Non-overlapping operation in pulse output group 1 (independent 1 and 0 output at

compare match A or B in the selected TPU channel)

Bit 0—Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping operation for pulse

output group 0 (pins PO3 to PO0). However, the H8S/2646 Series has no pins corresponding to

pulse output group 0.

Bit 0

G0NOV Description

0 Normal operation in pulse output group 0 (output values updated at compare match A

in the selected TPU channel) (Initial value)

1 Non-overlapping operation in pulse output group 0 (independent 1 and 0 output at

compare match A or B in the selected TPU channel)

400

11.2.7 Port 1 Data Direction Register (P1DDR)

Bit:76543210

P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR

Initial value : 0 0 0 0 0 0 0 0

R/W:WWWWWWWW

P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port 1.

Port 1 is multiplexed with pins PO15 to PO8. Bits corresponding to pins used for PPG output must

be set to 1. For further information about P1DDR, see section 9.2, Port 1.

11.2.8 Module Stop Control Register A (MSTPCRA)

Bit:76543210

MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0

Initial value : 0 0 1 1 1 1 1 1

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

MSTPCRA is a 16-bit readable/writable register that performs module stop mode control.

When the MSTPA3 bit in MSTPCRA is set to 1, PPG operation stops at the end of the bus cycle

and a transition is made to module stop mode. Registers cannot be read or written to in module

stop mode. For details, see section 22.5, Module Stop Mode.

MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized by a

manual reset and in software standby mode.

Bit 3—Module Stop (MSTPA3): Specifies the PPG module stop mode.

Bit 3

MSTPA3 Description

0 PPG module stop mode cleared

1 PPG module stop mode set (Initial value)

401

11.3 Operation

11.3.1 Overview

PPG pulse output is enabled when the corresponding bits in P1DDR and NDER are set to 1. In

this state the corresponding PODR contents are output.

When the compare match event specified by PCR occurs, the corresponding NDR bit contents are

transferred to PODR to update the output values.

Figure 11-2 illustrates the PPG output operation and table 11-3 summarizes the PPG operating

conditions.

Output trigger signal

Pulse output pin Internal data bus

Normal output/inverted output

PODRQD

NDER

NDRQD

DDR

Figure 11-2 PPG Output Operation

Table 11-3 PPG Operating Conditions

NDER DDR Pin Function

0 0 Generic input port

1 Generic output port

1 0 Generic input port (but the PODR bit is a read-only bit, and when

compare match occurs, the NDR bit value is transferred to the PODR bit)

1 PPG pulse output

Sequential output of data of up to 16 bits is possible by writing new output data to NDR before

the next compare match. For details of non-overlapping operation, see section 11.3.4, Non-

Overlapping Pulse Output.

402

11.3.2 Output Timing

If pulse output is enabled, NDR contents are transferred to PODR and output when the specified

compare match event occurs. Figure 11-3 shows the timing of these operations for the case of

normal output in groups 2 and 3, triggered by compare match A.

TCNT N N+1

TGRA N

Compare match

A signal

NDRH

PODRH

PO8 to PO15

Figure 11-3 Timing of Transfer and Output of NDR Contents (Example)

403

11.3.3 Normal Pulse Output

Sample Setup Procedure for Normal Pulse Output: Figure 11-4 shows a sample procedure for

setting up normal pulse output.

Select TGR functions [1]

Set TGRA value

Set counting operation

Select interrupt request

Set initial output data

Enable pulse output

Select output trigger

Set next pulse

output data

Start counter

Set next pulse

output data

Normal PPG output

Yes

TPU setup

Port and

PPG setup

TPU setup

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[10]

Compare match?

[1] Set TIOR to make TGRA an output

compare register (with output

disabled)

[2] Set the PPG output trigger period

[3] Select the counter clock source

with bits TPSC2 to TPSC0 in TCR.

Select the counter clear source

with bits CCLR1 and CCLR0.

[4] Enable the TGIA interrupt in TIER.

The DTC can also be set up to

transfer data to NDR.

[5] Set the initial output values in

PODR.

[6]

Set the DDR and NDER bits for the

pins to be used for pulse output to 1.

[7] Select the TPU compare match

event to be used as the output

trigger in PCR.

[8] Set the next pulse output values in

NDR.

[9] Set the CST bit in TSTR to 1 to

start the TCNT counter.

[10]

At each TGIA interrupt, set the next

output values in NDR.

Figure 11-4 Setup Procedure for Normal Pulse Output (Example)

404

Example of Normal Pulse Output (Example of Five-Phase Pulse Output): Figure 11-5 shows

an example in which pulse output is used for cyclic five-phase pulse output.

TCNT value TCNT

TGRA

H'0000

NDRH

00 80 C0 40 60 20 30 10 18 08 88

PODRH

PO15

PO14

PO13

PO12

PO11

Time

Compare match

C080 40 60 20 30 10 18 08 88 80 C0 40

Figure 11-5 Normal Pulse Output Example (Five-Phase Pulse Output)

[1] Set up the TPU channel to be used as the output trigger channel so that TGRA is an output

compare register and the counter will be cleared by compare match A. Set the trigger period in

TGRA and set the TGIEA bit in TIER to 1 to enable the compare match A (TGIA) interrupt.

[2] Write H'F8 in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0

bits in PCR to select compare match in the TPU channel set up in the previous step to be the

output trigger. Write output data H'80 in NDRH.

[3] The timer counter in the TPU channel starts. When compare match A occurs, the NDRH

contents are transferred to PODRH and output. The TGIA interrupt handling routine writes the

next output data (H'C0) in NDRH.

[4] Five-phase overlapping pulse output (one or two phases active at a time) can be obtained

subsequently by writing H'40, H'60, H'20, H'30. H'10, H'18, H'08, H'88... at successive TGIA

interrupts. If the DTC is set for activation by this interrupt, pulse output can be obtained

without imposing a load on the CPU.

405

11.3.4 Non-Overlapping Pulse Output

Sample Setup Procedure for Non-Overlapping Pulse Output: Figure 11-6 shows a sample

procedure for setting up non-overlapping pulse output.

Select TGR functions [1]

Set TGR values

Set counting operation

Select interrupt request

Set initial output data

Enable pulse output

Select output trigger

Set next pulse

output data

Start counter

Set next pulse

output data

Compare match? No

Yes

TPU setup

PPG setup

TPU setup

Non-overlapping

PPG output

Set non-overlapping groups

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[10]

[11]

[1] Set TIOR to make TGRA and

TGRB an output compare registers

(with output disabled)

[2] Set the pulse output trigger period

in TGRB and the non-overlap

margin in TGRA.

[3] Select the counter clock source

with bits TPSC2 to TPSC0 in TCR.

Select the counter clear source

with bits CCLR1 and CCLR0.

[4] Enable the TGIA interrupt in TIER.

The DTC can also be set up to

transfer data to NDR.

[5] Set the initial output values in

PODR.

[6] Set the DDR and NDER bits for the

pins to be used for pulse output to

[7] Select the TPU compare match

event to be used as the pulse

output trigger in PCR.

[8] In PMR, select the groups that will

operate in non-overlap mode.

[9] Set the next pulse output values in

NDR.

[10] Set the CST bit in TSTR to 1 to

start the TCNT counter.

[11] At each TGIA interrupt, set the next

output values in NDR.

Figure 11-6 Setup Procedure for Non-Overlapping Pulse Output (Example)

406

Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-

Overlapping Output): Figure 11-7 shows an example in which pulse output is used for four-

phase complementary non-overlapping pulse output.

TCNT value

TCNT

TGRB

TGRA

H'0000

NDRH 95 65 59 56 95 65

00 95 05 65 41 59 50 56 14 95 05 65

PODRH

PO15

PO14

PO13

PO12

PO11

PO10

PO9

PO8

Time

Non-overlap margin

Figure 11-7 Non-Overlapping Pulse Output Example (Four-Phase Complementary)

407

[1] Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are

output compare registers. Set the trigger period in TGRB and the non-overlap margin in

TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1

to enable the TGIA interrupt.

[2] Write H'FF in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0

bits in PCR to select compare match in the TPU channel set up in the previous step to be the

output trigger. Set the G3NOV and G2NOV bits in PMR to 1 to select non-overlapping output.

Write output data H'95 in NDRH.

[3] The timer counter in the TPU channel starts. When a compare match with TGRB occurs,

outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0

to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt

handling routine writes the next output data (H'65) in NDRH.

[4] Four-phase complementary non-overlapping pulse output can be obtained subsequently by

writing H'59, H'56, H'95... at successive TGIA interrupts. If the DTC is set for activation by

this interrupt, pulse output can be obtained without imposing a load on the CPU.

408

11.3.5 Inverted Pulse Output

If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the

inverse of the PODR contents can be output.

Figure 11-8 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the

settings of figure 11-7.

TCNT value

TCNT

TGRB

TGRA

H'0000

NDRH 95 65 59 56 95 65

00 95 05 65 41 59 50 56 14 95 05 65

PODRL

PO15

PO14

PO13

PO12

PO11

PO10

PO9

PO8

Time

Figure 11-8 Inverted Pulse Output (Example)

409

11.3.6 Pulse Output Triggered by Input Capture

Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA

functions as an input capture register in the TPU channel selected by PCR, pulse output will be

triggered by the input capture signal.

Figure 11-9 shows the timing of this output.

TIOC pin

Input capture

signal

NDR

PODR

Figure 11-9 Pulse Output Triggered by Input Capture (Example)

410

11.4 Usage Notes

Operation of Pulse Output Pins: Pins PO8 to PO15 are also used for other peripheral functions

such as the TPU. When output by another peripheral function is enabled, the corresponding pins

cannot be used for pulse output. Note, however, that data transfer from NDR bits to PODR bits

takes place, regardless of the usage of the pins.

Pin functions should be changed only under conditions in which the output trigger event will not

occur.

Note on Non-Overlapping Output: During non-overlapping operation, the transfer of NDR bit

values to PODR bits takes place as follows.

• NDR bits are always transferred to PODR bits at compare match A.

• At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred

if their value is 1.

Figure 11-10 illustrates the non-overlapping pulse output operation.

Compare match A

Compare match B

Pulse

output

pin Normal output/inverted output

PODRQD

NDER

NDRQD

Internal data bus

DDR

Figure 11-10 Non-Overlapping Pulse Output

411

Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before

compare match A. The NDR contents should not be altered during the interval from compare

match B to compare match A (the non-overlap margin).

This can be accomplished by having the TGIA interrupt handling routine write the next data in

NDR, or by having the TGIA interrupt activate the DTC. Note, however, that the next data must

be written before the next compare match B occurs.

Figure 11-11 shows the timing of this operation.

0/1 output0 output 0/1 output0 output

Do not write

to NDR here

Write to NDR

here

Compare match A

Compare match B

NDR

PODR

Do not write

to NDR here

Write to NDR

here

Write to NDR Write to NDR

Figure 11-11 Non-Overlapping Operation and NDR Write Timing

412

413

Section 12 Watchdog Timer

12.1 Overview

The H8S/2646 Series has an on-chip watchdog timer with two channels (WDT0, WDT1). The

WDT can also generate an internal reset signal for the H8S/2646 Series if a system crash prevents

the CPU from writing to the timer counter, allowing it to overflow.

When this watchdog function is not needed, the WDT can be used as an interval timer. In interval

timer operation, an interval timer interrupt is generated each time the counter overflows.

12.1.1 Features

WDT features are listed below.

• Switchable between watchdog timer mode and interval timer mode

• An internal reset can be issued if the timer counter overflows.

In the watchdog timer mode, the WDT can generate an internal reset.

• Interrupt generation when in interval timer mode

If the counter overflows, the WDT generates an interval timer interrupt.

• WDT0 and WDT1 respectively allow eight and sixteen types of counter input clock to be

selected

The maximum interval of the WDT is given as a system clock cycle × 131072 × 256.

A subclock may be selected for the input counter of WDT1.

Where a subclock is selected, the maximum interval is given as a subclock cycle × 256 × 256.

414

12.1.2 Block Diagram

Figures 12-1 (a) and 12-1 (b) show a block diagram of the WDT.

Overflow

Interrupt

control

WOVI0

(interrupt request

signal)

Internal reset signal*Reset

control

RSTCSR TCNT TSCR

ø/2

ø/64

ø/128

ø/512

ø/2048

ø/8192

ø/32768

ø/131072

Clock Clock

select

Internal clock

sources

Bus

interface

Module bus

Legend

TCSR

TCNT

RSTCSR

Note: *

: Timer control/status register

: Timer counter

: Reset control/status register

Internal bus

WDT

The type of internal reset signal depends on a register setting.

Figure 12-1 (a) Block Diagram of WDT0

415

Overflow

Interrupt

control

Reset

control

WOVI1

(Interrupt request signal)

Internal reset signal*

TCNT TCSR

ø/2

ø/64

ø/128

ø/512

ø/2048

ø/8192

ø/32768

ø/131072

Clock Clock

select

Internal clock

Bus

interface

Internal bus

Module bus

TCSR :

TCNT :

Note: *An internal reset signal can be generated by setting the register.

Timer control/status register

Timer counter

WDT

Legend:

Internal NMI

Interrupt request signal

øSUB/2

øSUB/4

øSUB/8

øSUB/16

øSUB/32

øSUB/64

øSUB/128

øSUB/256

Figure 12-1 (b) Block Diagram of WDT1

416

12.1.3 Pin Configuration

There are no pins related to the WDT.

12.1.4 Register Configuration

The WDT has five registers, as summarized in table 12-1. These registers control clock selection,

WDT mode switching, and the reset signal.

Table 12-1 WDT Registers

Address*1

Channel Name Abbreviation R/W Initial Value Write*2Read

0 Timer control/status register 0 TCSR0 R/(W)*3H'18 H'FF74 H'FF74

Timer counter 0 TCNT0 R/W H'00 H'FF74 H'FF75

Reset control/status register RSTCSR0 R/(W) *3H'1F H'FF76 H'FF77

1 Timer control/status register 1 TCSR1 R/(W) *3H'00 H'FFA2 H'FFA2

Timer counter 1 TCNT1 R/W H'00 H'FFA2 H'FFA3

Notes: *1 Lower 16 bits of the address.

*2 For details of write operations, see section 12.2.4, Notes on Register Access.

*3 Only a write of 0 is permitted to bit 7, to clear the flag.

417

12.2 Register Descriptions

12.2.1 Timer Counter (TCNT)

Bit:76543210

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

TCNT is an 8-bit readable/writable* up-counter.

When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal

clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from

H'FF to H'00), an internal reset, a NMI interrupt (only WDT1), or an interval timer interrupt

(WOVI) is generated, depending on the mode selected by the WT/IT bit in TCSR.

TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared

to 0. It is not initialized in software standby mode.

Note: * TCNT is write-protected by a password to prevent accidental overwriting. For details see

section 12.2.4, Notes on Register Access.

12.2.2 Timer Control/Status Register (TCSR)

TCSR0

Bit:76543210

OVF WT/IT TME ——CKS2 CKS1 CKS0

Initial value : 0 0 0 1 1 0 0 0

R/W : R/(W)*R/W R/W ——R/W R/W R/W

Note: *Only a 0 may be written to this bit to clear the flag.

TCSR1

Bit:76543210

OVF WT/IT TME PSS RST/NMI CKS2 CKS1 CKS0

Initial value : 0 0 0 0 0 0 0 0

R/W : R/(W)*R/W R/W R/W R/W R/W R/W R/W

Note: *Only a 0 may be written to this bit to clear the flag.

418

TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be

input to TCNT, and the timer mode.

TCSR0 (TCSR1) is initialized to H'18 (H'00) by a reset and in hardware standby mode. It is not

initialized in software standby mode.

Note: * TCSR is write-protected by a password to prevent accidental overwriting. For details see

section 12.2.4, Notes on Register Access.

Bit 7—Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00.

Bit 7

OVF Description

0 [Clearing conditions] (Initial value)

• Cleared when 0 is written to the TME bit (Only applies to WDT1)

• Cleared by reading TCSR when OVF = 1, then writing 0 to OVF

1 [Setting condition]

When TCNT overflows (changes from H'FF to H'00)

When internal reset request generation is selected in watchdog timer mode, OVF is

cleared automatically by the internal reset.

In interval timer mode, the OVF flag can be cleared in the interval timer interrupt service routine

by reading TCSR while OVF = 1, then writing 0 to OVF, in accordance with the OVF flag

clearing conditions.

However, if conflict occurs between the OVF flag setting timing and OVF flag read timing when

interval timer interrupts are disabled and the OVF flag is polled, it has been found that in some

cases the read of OVF = 1 is not recognized.

In this case, the OVF flag clearing conditions can be reliably met by reading the OVF = 1 state

two or more times. In the above example, therefore, the OVF = 1 state should be read at least

twice before clearing the OVF flag.

Bit 6—Timer Mode Select (WT/IT): Selects whether the WDT is used as a watchdog timer or

interval timer. When TCNT overflows, WDT0 issues an internal reset if bit RSTE of the reset

control/status register (RSTCSR) is set to 1. In the interval timer mode, WDT0 sends a WOVI

interrupt request to the CPU. WDT1, on the other hand, requests a reset or an NMI interrupt from

the CPU if the watchdog timer mode is chosen, whereas it requests a WOVI interrupt from the

CPU if the interval timer mode is chosen.

419

WDT0 Mode Select

TCSR0

WT/IT Description

0 Interval timer mode: WDT0 requests an interval timer interrupt (WOVI)

from the CPU when the TCNT overflows. (Initial value)

1 Watchdog timer mode: A reset is issued when the TCNT overflows if the RSTE bit of

RSTCSR is set to 1.*

Note: *For details see section 12.2.3, Reset Control/Status Register (RSTCSR).

WDT1 Mode Select

TCSR1

WT/IT Description

0 Interval timer mode: WDT1 requests an interval timer interrupt (WOVI)

from the CPU when the TCNT overflows. (Initial value)

1 Watchdog timer mode: WDT1 requests a reset or an NMI interrupt from

the CPU when the TCNT overflows.

Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted.

Bit 5

TME Description

0 TCNT is initialized to H'00 and halted (Initial value)

1 TCNT counts

WDT0 TCSR Bit 4—Reserved Bit: It is always read as 1 and cannot be modified.

WDT1 TCSR Bit 4—Prescaler Select (PSS): This bit is used to select an input clock source for

the TCNT of WDT1.

See the descriptions of Clock Select 2 to 0 for details.

Bit 4

PSS Description

0 The TCNT counts frequency-division clock pulses of the ø based

prescaler (PSM). (Initial value)

1 The TCNT counts frequency-division clock pulses of the ø SUB-based prescaler

(PSS).

420

WDT0 TCSR Bit 3—Reserved Bit: It is always read as 1 and cannot be modified.

WDT1 TCSR Bit 3—Reset or NMI (RST/NMI): This bit is used to choose between an internal

reset request and an NMI request when the TCNT overflows during the watchdog timer mode.

Bit 3

RTS/NMI Description

0 NMI request. (Initial value)

1 Internal reset request.

Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock

sources, obtained by dividing the system clock (ø) or subclock (ø SUB), for input to TCNT.

WDT0 Input Clock Select

Description

Bit 2

CKS2 Bit 1

CKS1 Bit 0

CKS0 Clock Overflow Period* (where ø = 20 MHz)

000ø/2 (initial value) 25.6 µs

1ø/64 819.2 µs

10ø/128 1.6 ms

1ø/512 6.6 ms

100ø/2048 26.2 ms

1ø/8192 104.9 ms

10ø/32768 419.4 ms

1ø/131072 1.68 s

Note: *An overflow period is the time interval between the start of counting up from H'00 on the

TCNT and the occurrence of a TCNT overflow.

421

WDT1 Input Clock Select

Description

Bit 4

PSS Bit 2

CKS2 Bit 1

CKS1 Bit 0

CKS0 Clock Overflow Period* (where ø = 20 MHz)

(where ø SUB = 32.768 kHz)

0000ø/2 (initial value) 25.6 µs

1ø/64 819.2 µs

10ø/128 1.6 ms

1ø/512 6.6 ms

100ø/2048 26.2 ms

1ø/8192 104.9 ms

10ø/32768 419.4 ms

1ø/131072 1.68 s

1000øSUB/2 15.6 ms

1øSUB/4 31.3 ms

10øSUB/8 62.5 ms

1øSUB/16 125 ms

100øSUB/32 250 ms

1øSUB/64 500 ms

10øSUB/128 1 s

1øSUB/256 2 s

Note: *An overflow period is the time interval between the start of counting up from H'00 on the

TCNT and the occurrence of a TCNT overflow.

422

12.2.3 Reset Control/Status Register (RSTCSR)

Bit:76543210

WOVF RSTE ——————

Initial value : 0 0 0 1 1 1 1 1

R/W : R/(W)*R/W R/W —————

Note: *Can only be written with 0 for flag clearing.

RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset

signal when TCNT overflows, and selects the type of internal reset signal.

RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal

reset signal caused by overflows.

Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details

see section 12.2.4, Notes on Register Access.

Bit 7—Watchdog Overflow Flag (WOVF): Indicates that TCNT has overflowed (changed from

H'FF to H'00) during watchdog timer operation. This bit is not set in interval timer mode.

Bit 7

WOVF Description

0 [Clearing condition] (Initial value)

Cleared by reading TCSR when WOVF = 1, then writing 0 to WOVF

1 [Setting condition]

Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer

operation

Bit 6—Reset Enable (RSTE): Specifies whether or not a reset signal is generated in the

H8S/2646 Series if TCNT overflows during watchdog timer operation.

Bit 6

RSTE Description

0 Reset signal is not generated if TCNT overflows* (Initial value)

1 Reset signal is generated if TCNT overflows

Note: *The modules within the H8S/2646 Series are not reset, but TCNT and TCSR within the

WDT are reset.

Bit 5—Reserved: Always read as 0. Can only be written with 0.

Bits 4 to 0—Reserved: Always read as 1. Not writable.

423

12.2.4 Notes on Register Access

The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being

more difficult to write to. The procedures for writing to and reading these registers are given

below.

Writing to TCNT and TCSR: These registers must be written to by a word transfer instruction.

They cannot be written to with byte instructions.

Figure 12-2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the

same write address. For a write to TCNT, the upper byte of the written word must contain H'5A

and the lower byte must contain the write data. For a write to TCSR, the upper byte of the written

word must contain H'A5 and the lower byte must contain the write data. This transfers the write

data from the lower byte to TCNT or TCSR.

TCNT write

TCSR write

Address: H'FF74

H'5A Write data

15 8 7 0

H'A5 Write data

15 8 7 0

Figure 12-2 Format of Data Written to TCNT and TCSR (WDT0)

424

Writing to RSTCSR: RSTCSR must be written to by word transfer instruction to address

H'FF76. It cannot be written to with byte instructions.

Figure 12-3 shows the format of data written to RSTCSR. The method of writing 0 to the WOVF

bit differs from that for writing to the RSTE bits.

To write 0 to the WOVF bit, the write data must have H'A5 in the upper byte and H'00 in the

lower byte. This clears the WOVF bit to 0, but has no effect on the RSTE bits. To write to the

RSTE bit, the upper byte must contain H'5A and the lower byte must contain the write data. This

writes the values in bit 6 of the lower byte into the RSTE bit, but has no effect on the WOVF bit.

H'A5 H'00

15 8 7 0

H'5A Write data

15 8 7 0

Writing 0 to WOVF bit

Writing to RSTE bit

Address: H'FF76

Figure 12-3 Format of Data Written to RSTCSR (WDT0)

Reading TCNT, TCSR, and RSTCSR: These registers are read in the same way as other

registers. The read addresses are H'FF74 for TCSR, H'FF75 for TCNT, and H'FF77 for RSTCSR.

425

12.3 Operation

12.3.1 Watchdog Timer Operation

To use the WDT as a watchdog timer, set the WT/IT bit in TCSR and the TME bit to 1. Software

must prevent TCNT overflows by rewriting the TCNT value (normally by writing H'00) before

overflow occurs. This ensures that TCNT does not overflow while the system is operating

normally. If TCNT overflows without being rewritten because of a system malfunction or other

error, an internal reset is issued, in the case of WDT0, if the RSTE bit in RSTCSR is set to 1.

The internal reset signal is output for 518 states.

If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a

WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0.

In the case of WDT1, the chip is reset, or an NMI interrupt request is generated, for 516 system

clock periods (516ø) (515 or 516 clock periods when the clock source is øSUB (PSS = 1)). This is

illustrated in figure 12-4 (b).

An NMI request from the watchdog timer and an interrupt request from the NMI pin are both

treated as having the same vector. So, avoid handling an NMI request from the watchdog timer

and an interrupt request from the NMI pin at the same time.

TCNT value

H'00 Time

H'FF

WT/IT=1

TME=1 Write H'00'

to TCNT WT/IT=1

TME=1 Write H'00'

to TCNT

518 states

Internal reset signal*

WT/IT

TME

Note: * The internal reset signal is generated only if the RSTE bit is set to 1.

Overflow

internal reset is

generated

WOVF=1

: Timer mode select bit

: Timer enable bit

Legend

Figure 12-4 (a) WDT0 Watchdog Timer Operation

426

TCNT value

H'00 Time

H'FF

WT/IT= 1

TME= 1 Write H'00'

to TCNT WT/IT= 1

TME= 1 Write H'00'

to TCNT

515/516 states

Internal

reset signal

WT/IT

TME

Legend

Overflow

internal reset

is generated

WOVF= 1*

: Timer mode select bit

: Timer enable bit

Note: *The WOVF bit is set to 1 and then cleared to 0 by an internal reset.

Figure 12-4 (b) WDT1 Watchdog Timer Operation

427

12.3.2 Interval Timer Operation

To use the WDT as an interval timer, clear the WT/IT bit in TCSR to 0 and set the TME bit to 1.

An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the

WDT is operating as an interval timer, as shown in figure 12-5. This function can be used to

generate interrupt requests at regular intervals.

TCNT value

H'00 Time

H'FF

WT/IT=0

TME=1 WOVI

Overflow Overflow Overflow Overflow

Legend

WOVI: Interval timer interrupt request generation

WOVI WOVI WOVI

Figure 12-5 Interval Timer Operation

12.3.3 Timing of Setting Overflow Flag (OVF)

The OVF flag is set to 1 if TCNT overflows during interval timer operation. At the same time, an

interval timer interrupt (WOVI) is requested. This timing is shown in figure 12-6.

With WDT1, the OVF bit of the TCSR is set to 1 and a simultaneous NMI interrupt is requested

when the TCNT overflows if the NMI request has been chosen in the watchdog timer mode.

428

TCNT H'FF H'00

Overflow signal

(internal signal)

OVF

Figure 12-6 Timing of Setting of OVF

12.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF)

In the WDT0, the WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. If

TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated

for the entire H8S/2646 Series chip. Figure 12-7 shows the timing in this case.

TCNT H'FF H'00

Overflow signal

(internal signal)

WOVF

Internal reset

signal 518 states (WDT0)

515/516 states (WDT1)

Figure 12-7 Timing of Setting of WOVF

429

12.4 Interrupts

During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).

The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be

cleared to 0 in the interrupt handling routine.

If an NMI request has been chosen in the watchdog timer mode, an NMI request is generated

when a TCNT overflow occurs.

12.5 Usage Notes

12.5.1 Contention between Timer Counter (TCNT) Write and Increment

If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write

takes priority and the timer counter is not incremented. Figure 12-8 shows this operation.

Address

Internal write signal

TCNT input clock

TCNT NM

T1T2

TCNT write cycle

Counter write data

Figure 12-8 Contention between TCNT Write and Increment

430

12.5.2 Changing Value of PSS and CKS2 to CKS0

If bits PSS and CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could

occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0)

before changing the value of bits PSS and CKS2 to CKS0.

12.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode

If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is

operating, errors could occur in the incrementation. Software must stop the watchdog timer (by

clearing the TME bit to 0) before switching the mode.

12.5.4 Internal Reset in Watchdog Timer Mode

In watchdog timer mode, the H8S/2646 Series will not be reset internally if TCNT overflows

while the RSTE bit is cleared to 0. When this module is used as a watchdog timer, the RSTE bit

must be set to 1 beforehand.

12.5.5 OVF Flag Clearing in Interval Timer Mode

When the OVF flag setting conflicts with the OVF flag reading in interval timer mode, writing 0

to the OVF bit may not clear the flag even though the OVF bit has been read while it is 1. If there

is a possibility that the OVF flag setting and reading will conflict, such as when the OVF flag is

polled with the interval timer interrupt disabled, read the OVF bit while it is 1 at least twice before

writing 0 to the OVF bit to clear the flag.

431

Section 13 Serial Communication Interface (SCI)

13.1 Overview

The H8S/2646 Series is equipped with 2 or 3 independent serial communication interface (SCI)

channels*. The SCI can handle both asynchronous and clocked synchronous serial

communication. A function is also provided for serial communication between processors

(multiprocessor communication function).

Note: * Two channels in the H8S/2646, H8S/2646R, and H8S/2645; three channels in the

H8S/2648, H8S/2648R, and H8S/2647.

13.1.1 Features

SCI features are listed below.

• Choice of asynchronous or clocked synchronous serial communication mode

Asynchronous mode

 Serial data communication executed using asynchronous system in which synchronization

is achieved character by character

Serial data communication can be carried out with standard asynchronous communication

chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous

Communication Interface Adapter (ACIA)

 A multiprocessor communication function is provided that enables serial data

communication with a number of processors

 Choice of 12 serial data transfer formats

Data length : 7 or 8 bits

Stop bit length : 1 or 2 bits

Parity : Even, odd, or none

Multiprocessor bit : 1 or 0

 Receive error detection : Parity, overrun, and framing errors

 Break detection : Break can be detected by reading the RxD pin level directly in

case of a framing error

Clocked Synchronous mode

 Serial data communication synchronized with a clock

Serial data communication can be carried out with other chips that have a synchronous

communication function

 One serial data transfer format

432

Data length : 8 bits

 Receive error detection : Overrun errors detected

• Full-duplex communication capability

 The transmitter and receiver are mutually independent, enabling transmission and reception

to be executed simultaneously

 Double-buffering is used in both the transmitter and the receiver, enabling continuous

transmission and continuous reception of serial data

• Choice of LSB-first or MSB-first transfer

 Can be selected regardless of the communication mode* (except in the case of

asynchronous mode 7-bit data)

Note: * Descriptions in this section refer to LSB-first transfer.

• On-chip baud rate generator allows any bit rate to be selected

• Choice of serial clock source: internal clock from baud rate generator or external clock from

SCK pin

• Four interrupt sources

 Four interrupt sources — transmit-data-empty, transmit-end, receive-data-full, and receive

error — that can issue requests independently

 The transmit-data-empty interrupt and receive data full interrupts can activate the data

transfer controller (DTC) to execute data transfer

• Module stop mode can be set

 As the initial setting, SCI operation is halted. Register access is enabled by exiting module

stop mode.

433

13.1.2 Block Diagram

Figure 13-1 shows a block diagram of the SCI.

Bus interface

TDR

RSR

RDR

Module data bus

TSR

SCMR

SSR

SCR

Transmission/

reception control

BRR

Baud rate

generator

Internal

data bus

RxD

TxD

SCK

Parity generation

Parity check

Clock

External clock

ø/4

ø/16

ø/64

TXI

TEI

RXI

ERI

SMR

Legend

RSR

RDR

TSR

TDR

SMR

SCR

SSR

SCMR

BRR

: Receive shift register

: Receive data register

: Transmit shift register

: Transmit data register

: Serial mode register

: Serial control register

: Serial status register

: Smart card mode register

: Bit rate register

Figure 13-1 Block Diagram of SCI

434

13.1.3 Pin Configuration

Table 13-1 shows the serial pins for each SCI channel.

Table 13-1 SCI Pins

Channel Pin Name Symbol I/O Function

0 Serial clock pin 0 SCK0 I/O SCI0 clock input/output

Receive data pin 0 RxD0 Input SCI0 receive data input

Transmit data pin 0 TxD0 Output SCI0 transmit data output

1 Serial clock pin 1 SCK1 I/O SCI1 clock input/output

Receive data pin 1 RxD1 Input SCI1 receive data input

Transmit data pin 1 TxD1 Output SCI1 transmit data output

2*Serial clock pin 2 SCK2 I/O SCI2 clock input/output

Receive data pin 2 RxD2 Input SCI2 receive data input

Transmit data pin 2 TxD2 Output SCI2 transmit data output

Notes: Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel

designation.

*H8S/2648, H8S/2648R, and H8S/2647 only.

435

13.1.4 Register Configuration

The SCI has the internal registers shown in table 13-2. These registers are used to specify

asynchronous mode or clocked synchronous mode, the data format , and the bit rate, and to control

transmitter/receiver.

Table 13-2 SCI Registers

Channel Name Abbreviation R/W Initial Value Address*1

0 Serial mode register 0 SMR0 R/W H'00 H'FF78

Bit rate register 0 BRR0 R/W H'FF H'FF79

Serial control register 0 SCR0 R/W H'00 H'FF7A

Transmit data register 0 TDR0 R/W H'FF H'FF7B

Serial status register 0 SSR0 R/(W)*2H'84 H'FF7C

Receive data register 0 RDR0 R H'00 H'FF7D

Smart card mode register 0 SCMR0 R/W H'F2 H'FF7E

1 Serial mode register 1 SMR1 R/W H'00 H'FF80

Bit rate register 1 BRR1 R/W H'FF H'FF81

Serial control register 1 SCR1 R/W H'00 H'FF82

Transmit data register 1 TDR1 R/W H'FF H'FF83

Serial status register 1 SSR1 R/(W)*2H'84 H'FF84

Receive data register 1 RDR1 R H'00 H'FF85

Smart card mode register 1 SCMR1 R/W H'F2 H'FF86

(H8S/2648, Serial mode register 2 SMR2 R/W H'00 H'FF88

H8S/2648R,

H8S/2647) Bit rate register 2 BRR2 R/W H'FF H'FF89

Serial control register 2 SCR2 R/W H'00 H'FF8A

Transmit data register 2 TDR2 R/W H'FF H'FF8B

Serial status register 2 SSR2 R/(W)*2H'84 H'FF8C

Receive data register 2 RDR2 R H'00 H'FF8D

Smart card mode register 2 SCMR2 R/W H'F2 H'FF8E

All Module stop control register B MSTPCRB R/W H'FF H'FDE9

Notes: *1 Lower 16 bits of the address.

*2 Can only be written with 0 for flag clearing.

436

13.2 Register Descriptions

13.2.1 Receive Shift Register (RSR)

—

Bit

R/W

RSR is a register used to receive serial data.

The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the

LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is

transferred to RDR automatically.

RSR cannot be directly read or written to by the CPU.

13.2.2 Receive Data Register (RDR)

Bit

Initial value

R/W

RDR is a register that stores received serial data.

When the SCI has received one byte of serial data, it transfers the received serial data from RSR to

RDR where it is stored, and completes the receive operation. After this, RSR is receive-enabled.

Since RSR and RDR function as a double buffer in this way, enables continuous receive

operations to be performed.

RDR is a read-only register, and cannot be written to by the CPU.

RDR is initialized to H'00 by a reset, in standby mode, watch mode, subactive mode, and subsleep

mode or module stop mode.

437

13.2.3 Transmit Shift Register (TSR)

—

Bit

R/W

TSR is a register used to transmit serial data.

To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then

sends the data to the TxD pin starting with the LSB (bit 0).

When transmission of one byte is completed, the next transmit data is transferred from TDR to

TSR, and transmission started, automatically. However, data transfer from TDR to TSR is not

performed if the TDRE bit in SSR is set to 1.

TSR cannot be directly read or written to by the CPU.

13.2.4 Transmit Data Register (TDR)

R/W

Bit

Initial value

R/W

TDR is an 8-bit register that stores data for serial transmission.

When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and

starts serial transmission. Continuous serial transmission can be carried out by writing the next

transmit data to TDR during serial transmission of the data in TSR.

TDR can be read or written to by the CPU at all times.

TDR is initialized to H'FF by a reset, in standby mode, watch mode, subactive mode, and subsleep

mode or module stop mode.

438

13.2.5 Serial Mode Register (SMR)

C/A

R/W

CHR

R/W

O/E

R/W

STOP

R/W

CKS0

R/W

CKS1

R/W

Bit

Initial value

R/W

SMR is an 8-bit register used to set the SCI’s serial transfer format and select the baud rate

generator clock source.

SMR can be read or written to by the CPU at all times.

SMR is initialized to H'00 by a reset and in hardware standby mode.

Bit 7—Communication Mode (C/A): Selects asynchronous mode or clocked synchronous mode

as the SCI operating mode.

Bit 7

C/ADescription

0 Asynchronous mode (Initial value)

1 Clocked synchronous mode

Bit 6—Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In

clocked synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting.

Bit 6

CHR Description

0 8-bit data (Initial value)

1 7-bit data*

Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and it is not possible

to choose between LSB-first or MSB-first transfer.

439

Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is

performed in transmission, and parity bit checking in reception. In clocked synchronous mode

with a multiprocessor format, parity bit addition and checking is not performed, regardless of the

PE bit setting.

Bit 5

PE Description

0 Parity bit addition and checking disabled (Initial value)

1 Parity bit addition and checking enabled*

Note:*When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to

transmit data before transmission. In reception, the parity bit is checked for the parity (even

or odd) specified by the O/E bit.

Bit 4—Parity Mode (O/E): Selects either even or odd parity for use in parity addition and

checking.

The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and

checking, in asynchronous mode. The O/E bit setting is invalid in clocked synchronous mode,

when parity addition and checking is disabled in asynchronous mode, and when a multiprocessor

format is used.

Bit 4

O/EDescription

0 Even parity*1 (Initial value)

1 Odd parity*2

Notes: *1 When even parity is set, parity bit addition is performed in transmission so that the total

number of 1 bits in the transmit character plus the parity bit is even.

In reception, a check is performed to see if the total number of 1 bits in the receive

character plus the parity bit is even.

*2 When odd parity is set, parity bit addition is performed in transmission so that the total

number of 1 bits in the transmit character plus the parity bit is odd.

In reception, a check is performed to see if the total number of 1 bits in the receive

character plus the parity bit is odd.

440

Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode.

The STOP bits setting is only valid in asynchronous mode. If clocked synchronous mode is set the

STOP bit setting is invalid since stop bits are not added.

Bit 3

STOP Description

0 1 stop bit: In transmission, a single 1 bit (stop bit) is added to the end

of a transmit character before it is sent. (Initial value)

1 2 stop bits:In transmission, two 1 bits (stop bits) are added to the end of a transmit

character before it is sent.

In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second

stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit

character.

Bit 2—Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format

is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only valid in

asynchronous mode; it is invalid in clocked synchronous mode.

For details of the multiprocessor communication function, see section 13.3.3, Multiprocessor

Communication Function.

Bit 2

MP Description

0 Multiprocessor function disabled (Initial value)

1 Multiprocessor format selected

441

Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the

baud rate generator. The clock source can be selected from ø, ø/4, ø/16, and ø/64, according to the

setting of bits CKS1 and CKS0.

For the relation between the clock source, the bit rate register setting, and the baud rate, see

section 13.2.8, Bit Rate Register (BRR).

Bit 1 Bit 0

CKS1 CKS0 Description

00ø clock (Initial value)

1ø/4 clock

10ø/16 clock

1ø/64 clock

13.2.6 Serial Control Register (SCR)

TIE

R/W

RIE

R/W

MPIE

R/W

CKE0

R/W

TEIE

R/W

CKE1

R/W

Bit

Initial value

R/W

SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output

in asynchronous mode, and interrupt requests, and selection of the serial clock source.

SCR can be read or written to by the CPU at all times.

SCR is initialized to H'00 by a reset and in standby mode.

Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit data empty interrupt

(TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE

flag in SSR is set to 1.

Bit 7

TIE Description

0 Transmit data empty interrupt (TXI) requests disabled* (Initial value)

1 Transmit data empty interrupt (TXI) requests enabled

Note:*TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then

clearing it to 0, or clearing the TIE bit to 0.

442

Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive data full interrupt (RXI)

request and receive error interrupt (ERI) request generation when serial receive data is transferred

from RSR to RDR and the RDRF flag in SSR is set to 1.

Bit 6

RIE Description

0 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request

disabled* (Initial value)

1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request

enabled

Note:*RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF

flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0.

Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI.

Bit 5

TE Description

0 Transmission disabled*1 (Initial value)

1 Transmission enabled*2

Notes: *1 The TDRE flag in SSR is fixed at 1.

*2 In this state, serial transmission is started when transmit data is written to TDR and the

TDRE flag in SSR is cleared to 0.

SMR setting must be performed to decide the transfer format before setting the TE bit

to 1.

Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCI.

Bit 4

RE Description

0 Reception disabled*1 (Initial value)

1 Reception enabled*2

Notes: *1 Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which

retain their states.

*2 Serial reception is started in this state when a start bit is detected in asynchronous

mode or serial clock input is detected in clocked synchronous mode.

SMR setting must be performed to decide the transfer format before setting the RE bit

to 1.

443

Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.

The MPIE bit setting is only valid in asynchronous mode when the MP bit in SMR is set to 1.

The MPIE bit setting is invalid in clocked synchronous mode or when the MP bit is cleared to 0.

Bit 3

MPIE Description

0 Multiprocessor interrupts disabled (normal reception performed) (Initial value)

[Clearing conditions]

• When the MPIE bit is cleared to 0

• When MPB= 1 data is received

1 Multiprocessor interrupts enabled*

Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting

of the RDRF, FER, and ORER flags in SSR are disabled until data with the

multiprocessor bit set to 1 is received.

Note: *When receive data including MPB = 0 is received, receive data transfer from RSR to RDR,

receive error detection, and setting of the RDRF, FER, and ORER flags in SSR , is not

performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to

1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts

(when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled.

Bit 2—Transmit End Interrupt Enable (TEIE): Enables or disables transmit end interrupt

(TEI) request generation when there is no valid transmit data in TDR in MSB data transmission.

Bit 2

TEIE Description

0 Transmit end interrupt (TEI) request disabled* (Initial value)

1 Transmit end interrupt (TEI) request enabled*

Note: *TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it

to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0.

444

Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock

source and enable or disable clock output from the SCK pin. The combination of the CKE1 and

CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or

the serial clock input pin.

The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in

asynchronous mode. The CKE0 bit setting is invalid in clocked synchronous mode, and in the case

of external clock operation (CKE1 = 1). Note that the SCI’s operating mode must be decided using

SMR before setting the CKE1 and CKE0 bits.

For details of clock source selection, see table 13-9 in section 13.3.1, Overview.

Bit 1 Bit 0

CKE1 CKE0 Description

0 0 Asynchronous mode Internal clock/SCK pin functions as I/O port*1

Clocked synchronous

mode Internal clock/SCK pin functions as serial clock

output*1

1 Asynchronous mode Internal clock/SCK pin functions as clock output*2

Clocked synchronous

mode Internal clock/SCK pin functions as serial clock

output

1 0 Asynchronous mode External clock/SCK pin functions as clock input*3

Clocked synchronous

mode External clock/SCK pin functions as serial clock

input

1 Asynchronous mode External clock/SCK pin functions as clock input*3

Clocked synchronous

mode External clock/SCK pin functions as serial clock

input

Notes: *1 Initial value

*2 Outputs a clock of the same frequency as the bit rate.

*3 Inputs a clock with a frequency 16 times the bit rate.

445

13.2.7 Serial Status Register (SSR)

TDRE

R/(W)*

RDRF

R/(W)*

ORER

R/(W)*

FER

R/(W)*

PER

R/(W)*

MPBT

R/W

TEND

MPB

Bit

Initial value

R/W

Note: * Only 0 can be written, to clear the flag.

SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and

multiprocessor bits.

SSR can be read or written to by the CPU at all times. However, 1 cannot be written to flags

TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be

read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified.

SSR is initialized to H'84 by a reset, in standby mode, watch mode, subactive mode, and subsleep

mode or module stop mode.

Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from

TDR to TSR and the next serial data can be written to TDR.

Bit 7

TDRE Description

0 [Clearing conditions]

• When 0 is written to TDRE after reading TDRE = 1

• When the DTC is activated by a TXI interrupt and writes data to TDR

1 [Setting conditions] (Initial value)

• When the TE bit in SCR is 0

• When data is transferred from TDR to TSR and data can be written to TDR

446

Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR.

Bit 6

RDRF Description

0 [Clearing conditions] (Initial value)

• When 0 is written to RDRF after reading RDRF = 1

• When the DTC is activated by an RXI interrupt and reads data from RDR

1 [Setting condition]

When serial reception ends normally and receive data is transferred from RSR to RDR

Note: RDR and the RDRF flag are not affected and retain their previous values when an error is

detected during reception or when the RE bit in SCR is cleared to 0.

If reception of the next data is completed while the RDRF flag is still set to 1, an overrun

error will occur and the receive data will be lost.

Bit 5—Overrun Error (ORER): Indicates that an overrun error occurred during reception,

causing abnormal termination.

Bit 5

ORER Description

0 [Clearing condition] (Initial value)*1

When 0 is written to ORER after reading ORER = 1

1 [Setting condition]

When the next serial reception is completed while RDRF = 1*2

Notes: *1 The ORER flag is not affected and retains its previous state when the RE bit in SCR is

cleared to 0.

*2 The receive data prior to the overrun error is retained in RDR, and the data received

subsequently is lost. Also, subsequent serial reception cannot be continued while the

ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be

continued, either.

447

Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in

asynchronous mode, causing abnormal termination.

Bit 4

FER Description

0 [Clearing condition] (Initial value)*1

When 0 is written to FER after reading FER = 1

1 [Setting condition]

When the SCI checks whether the stop bit at the end of the receive data when

reception ends, and the stop bit is 0 *2

Notes: *1 The FER flag is not affected and retains its previous state when the RE bit in SCR is

cleared to 0.

*2 In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit

is not checked. If a framing error occurs, the receive data is transferred to RDR but the

RDRF flag is not set. Also, subsequent serial reception cannot be continued while the

FER flag is set to 1. In clocked synchronous mode, serial transmission cannot be

continued, either.

Bit 3—Parity Error (PER): Indicates that a parity error occurred during reception using parity

addition in asynchronous mode, causing abnormal termination.

Bit 3

PER Description

0 [Clearing condition] (Initial value)*1

When 0 is written to PER after reading PER = 1

1 [Setting condition]

When, in reception, the number of 1 bits in the receive data plus the parity bit does not

match the parity setting (even or odd) specified by the O/E bit in SMR*2

Notes: *1 The PER flag is not affected and retains its previous state when the RE bit in SCR is

cleared to 0.

*2 If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not

set. Also, subsequent serial reception cannot be continued while the PER flag is set to

1. In clocked synchronous mode, serial transmission cannot be continued, either.

448

Bit 2—Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of

the transmit character is sent, and transmission has been ended.

The TEND flag is read-only and cannot be modified.

Bit 2

TEND Description

0 [Clearing conditions]

• When 0 is written to TDRE after reading TDRE = 1

• When the DTC is activated by a TXI interrupt and writes data to TDR

1 [Setting conditions] (Initial value)

• When the TE bit in SCR is 0

• When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character

Bit 1—Multiprocessor Bit (MPB): When reception is performed using multiprocessor format in

asynchronous mode, MPB stores the multiprocessor bit in the receive data.

MPB is a read-only bit, and cannot be modified.

Bit 1

MPB Description

0 [Clearing condition] (Initial value)*

When data with a 0 multiprocessor bit is received

1 [Setting condition]

When data with a 1 multiprocessor bit is received

Note: *Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor

format.

Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using

multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to

the transmit data.

The MPBT bit setting is invalid when multiprocessor format is not used, when not transmitting,

and in clocked synchronous mode.

Bit 0

MPBT Description

0 Data with a 0 multiprocessor bit is transmitted (Initial value)

1 Data with a 1 multiprocessor bit is transmitted

449

13.2.8 Bit Rate Register (BRR)

R/W

Bit

Initial value

R/W

BRR is an 8-bit register that sets the serial transmit/receive bit rate in accordance with the baud

rate generator operating clock selected by bits CKS1 and CKS0 in SMR.

BRR can be read or written to by the CPU at all times.

BRR is initialized to H'FF by a reset and in standby mode.

As baud rate generator control is performed independently for each channel, different values can

be set for each channel.

Table 13-3 shows sample BRR settings in asynchronous mode, and table 13-4 shows sample BRR

settings in clocked synchronous mode.

Table 13-3 BRR Settings for Various Bit Rates (Asynchronous Mode)

ø = 4 MHz ø = 4.9152 MHz ø = 5 MHz ø = 6 MHz

Bit Rate

(bit/s) n N Error

(%) n N Error

(%)

110 2 70 0.03 2 86 0.31 2 88 –0.25 2 106 –0.44

150 1 207 0.16 1 255 0.00 2 64 0.16 2 77 0.16

300 1 103 0.16 1 127 0.00 1 129 0.16 1 155 0.16

600 0 207 0.16 0 255 0.00 1 64 0.16 1 77 0.16

1200 0 103 0.16 0 127 0.00 0 129 0.16 0 155 0.16

2400 0 51 0.16 0 63 0.00 0 64 0.16 0 77 0.16

4800 0 25 0.16 0 31 0.00 0 32 –1.36 0 38 0.16

9600 0 12 0.16 0 15 0.00 0 15 1.73 0 19 –2.34

19200 ———0 7 0.00 0 7 1.73 0 9 –2.34

31250 0 3 0.00 0 4 –1.70 0 4 0.00 0 5 0.00

38400 ———0 3 0.00 0 3 1.73 0 4 –2.34

450

ø = 6.144 MHz ø = 7.3728 MHz ø = 8 MHz ø = 9.8304 MHz

Bit Rate

(bit/s) n N Error

(%) n N Error

(%)

110 2 108 0.08 2 130 –0.07 2 141 0.03 2 174 –0.26

150 2 79 0.00 2 95 0.00 2 103 0.16 2 127 0.00

300 1 159 0.00 1 191 0.00 1 207 0.16 1 255 0.00

600 1 79 0.00 1 95 0.00 1 103 0.16 1 127 0.00

1200 0 159 0.00 0 191 0.00 0 207 0.16 0 255 0.00

2400 0 79 0.00 0 95 0.00 0 103 0.16 0 127 0.00

4800 0 39 0.00 0 47 0.00 0 51 0.16 0 63 0.00

9600 0 19 0.00 0 23 0.00 0 25 0.16 0 31 0.00

19200 0 9 0.00 0 11 0.00 0 12 0.16 0 15 0.00

31250 0 5 2.40 ———0 7 0.00 0 9 –1.70

38400 0 4 0.00 0 5 0.00 ———0 7 0.00

ø = 10 MHz ø = 12 MHz ø = 12.288 MHz ø = 14 MHz

Bit Rate

(bit/s) n N Error

(%) n N Error

(%)

110 2 177 –0.25 2 212 0.03 2 217 0.08 2 248 –0.17

150 2 129 0.16 2 155 0.16 2 159 0.00 2 181 0.16

300 2 64 0.16 2 77 0.16 2 79 0.00 2 90 0.16

600 1 129 0.16 1 155 0.16 1 159 0.00 1 181 0.16

1200 1 64 0.16 1 77 0.16 1 79 0.00 1 90 0.16

2400 0 129 0.16 0 155 0.16 0 159 0.00 0 181 0.16

4800 0 64 0.16 0 77 0.16 0 79 0.00 0 90 0.16

9600 0 32 –1.36 0 38 0.16 0 39 0.00 0 45 –0.93

19200 0 15 1.73 0 19 –2.34 0 19 0.00 0 22 –0.93

31250 0 9 0.00 0 11 0.00 0 11 2.40 0 13 0.00

38400 0 7 1.73 0 9 –2.34 0 9 0.00 ———

451

ø = 14.7456 MHz ø = 16 MHz ø = 17.2032 MHz ø = 18 MHz

Bit Rate

(bit/s) n N Error

(%) n N Error

(%)

110 3 64 0.70 3 70 0.03 3 75 0.48 3 79 –0.12

150 2 191 0.00 2 207 0.16 2 223 0.00 2 233 0.16

300 2 95 0.00 2 103 0.16 2 111 0.00 2 116 0.16

600 1 191 0.00 1 207 0.16 1 223 0.00 1 233 0.16

1200 1 95 0.00 1 103 0.16 1 111 0.00 1 116 0.16

2400 0 191 0.00 0 207 0.16 0 223 0.00 0 233 0.16

4800 0 95 0.00 0 103 0.16 0 111 0.00 0 116 0.16

9600 0 47 0.00 0 51 0.16 0 55 0.00 0 58 –0.69

19200 0 23 0.00 0 25 0.16 0 27 0.00 0 28 1.02

31250 0 14 –1.70 0 15 0.00 0 16 1.20 0 17 0.00

38400 0 11 0.00 0 12 0.16 0 13 0.00 0 14 –2.34

ø = 19.6608 MHz ø = 20 MHz

Bit Rate

(bit/s) n N Error

(%) n N Error

(%)

110 3 86 0.31 3 88 –0.25

150 2 255 0.00 3 64 0.16

300 2 127 0.00 2 129 0.16

600 1 255 0.00 2 64 0.16

1200 1 127 0.00 1 129 0.16

2400 0 255 0.00 1 64 0.16

4800 0 127 0.00 0 129 0.16

9600 0 63 0.00 0 64 0.16

19200 0 31 0.00 0 32 –1.36

31250 0 19 –1.70 0 19 0.00

38400 0 15 0.00 0 15 1.73

452

Table 13-4 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)

Bit Rate ø = 4 MHz ø = 8 MHz ø = 10 MHz ø = 16 MHz ø = 20 MHz

(bit/s) n N n N n N n N n N

110 ——

250 2 249 3 124 —— 3 249

500 2 124 2 249 —— 3 124 ——

1 k 1 249 2 124 —— 2 249 ——

2.5 k 1 99 1 199 1 249 2 99 2 124

5 k 0 199 1 99 1 124 1 199 1 249

10 k 0 99 0 199 0 249 1 99 1 124

25 k 0 39 0 79 0 99 0 159 0 199

50 k 0 19 0 39 0 49 0 79 0 99

100 k 0 9 0 19 0 24 0 39 0 49

250 k 0 3 0 7 0 9 0 15 0 19

500 k 0 1 0 3 0 4 0 7 0 9

1 M 0 0*01 03 04

2.5 M 0 0*01

5 M 00*

Note: As far as possible, the setting should be made so that the error is no more than 1%.

Legend

Blank : Cannot be set.

—: Can be set, but there will be a degree of error.

*: Continuous transfer is not possible.

453

The BRR setting is found from the following formulas.

Asynchronous mode:

N = ø

64 × 22n–1 × B × 106 – 1

Clocked synchronous mode:

N = ø

8 × 22n–1 × B × 106 – 1

Where B: Bit rate (bit/s)

N: BRR setting for baud rate generator (0 ≤ N ≤ 255)

ø: Operating frequency (MHz)

n: Baud rate generator input clock (n = 0 to 3)

(See the table below for the relation between n and the clock.)

SMR Setting

n Clock CKS1 CKS0

0ø00

1ø/4 0 1

2ø/16 1 0

3ø/64 1 1

The bit rate error in asynchronous mode is found from the following formula:

Error (%) = { ø × 106

(N + 1) × B × 64 × 22n–1 – 1} × 100

454

Table 13-5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 13-6

and 13-7 show the maximum bit rates with external clock input.

Table 13-5 Maximum Bit Rate for Each Frequency (Asynchronous Mode)

ø (MHz) Maximum Bit Rate (bit/s) n N

4 125000 0 0

4.9152 153600 0 0

5 156250 0 0

6 187500 0 0

6.144 192000 0 0

7.3728 230400 0 0

8 250000 0 0

9.8304 307200 0 0

10 312500 0 0

12 375000 0 0

12.288 384000 0 0

14 437500 0 0

14.7456 460800 0 0

16 500000 0 0

17.2032 537600 0 0

18 562500 0 0

19.6608 614400 0 0

20 625000 0 0

455

Table 13-6 Maximum Bit Rate with External Clock Input (Asynchronous Mode)

ø (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s)

4 1.0000 62500

4.9152 1.2288 76800

5 1.2500 78125

6 1.5000 93750

6.144 1.5360 96000

7.3728 1.8432 115200

8 2.0000 125000

9.8304 2.4576 153600

10 2.5000 156250

12 3.0000 187500

12.288 3.0720 192000

14 3.5000 218750

14.7456 3.6864 230400

16 4.0000 250000

17.2032 4.3008 268800

18 4.5000 281250

19.6608 4.9152 307200

20 5.0000 312500

Table 13-7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)

ø (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s)

4 0.6667 666666.7

6 1.0000 1000000.0

8 1.3333 1333333.3

10 1.6667 1666666.7

12 2.0000 2000000.0

14 2.3333 2333333.3

16 2.6667 2666666.7

18 3.0000 3000000.0

20 3.3333 3333333.3

456

13.2.9 Smart Card Mode Register (SCMR)

—

SDIR

R/W

SMIF

R/W

SINV

R/W

—

Bit

Initial value

R/W

SCMR selects LSB-first or MSB-first by means of bit SDIR. Except in the case of asynchronous

mode 7-bit data, LSB-first or MSB-first can be selected regardless of the serial communication

mode. The descriptions in this chapter refer to LSB-first transfer.

For details of the other bits in SCMR, see section 14.2.1, Smart Card Mode Register (SCMR).

SCMR is initialized to H'F2 by a reset and in standby mode.

Bits 7 to 4—Reserved: It is always read as 1 and cannot be modified.

Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion

format.

This bit is valid when 8-bit data is used as the transmit/receive format.

Bit 3

SDIR Description

0 TDR contents are transmitted LSB-first (Initial value)

Receive data is stored in RDR LSB-first

1 TDR contents are transmitted MSB-first

Receive data is stored in RDR MSB-first

457

Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. The SINV

bit does not affect the logic level of the parity bit(s): parity bit inversion requires inversion of the

O/E bit in SMR.

Bit 2

SINV Description

0 TDR contents are transmitted without modification (Initial value)

Receive data is stored in RDR without modification

1 TDR contents are inverted before being transmitted

Receive data is stored in RDR in inverted form

Bit 1—Reserved: It is always read as 1 and cannot be modified.

Bit 0—Smart Card Interface Mode Select (SMIF): When the smart card interface operates as a

normal SCI, 0 should be written in this bit.

Bit 0

SMIF Description

0 Operates as normal SCI (smart card interface function disabled) (Initial value)

1 Smart card interface function enabled

13.2.10 Module Stop Control Register B (MSTPCRB)

MSTPB7

R/W

MSTPB6

R/W

MSTPB5

R/W

MSTPB4

R/W

MSTPB3

R/W

MSTPB0

R/W

MSTPB2

R/W

MSTPB1

R/W

Bit

Initial value

R/W

MSTPCRB is an 8-bit readable/writable register that perform module stop mode control.

Setting any of bits MSTPB7 to MSTPB6 to 1 stops SCI0 to SCI1 operating and enter module stop

mode on completion of the bus cycle. For details, see section 22.5, Module Stop Mode.

MSTPCRB is initialized to H'FF by a reset and in hardware standby mode. They are not

initialized in software standby mode.

458

Bit 7—Module Stop (MSTPB7): Specifies the SCI0 module stop mode.

Bit 7

MSTPB7 Description

0 SCI0 module stop mode is cleared

1 SCI0 module stop mode is set (Initial value)

Bit 6—Module Stop (MSTPB6): Specifies the SCI1 module stop mode.

Bit 6

MSTPB6 Description

0 SCI1 module stop mode is cleared

1 SCI1 module stop mode is set (Initial value)

Bit 5—Module Stop (MSTPB5): Specifies the SCI2 module stop mode.

Bit 5

MSTPB5 Description

0 SCI2 module stop mode is cleared

1 SCI2 module stop mode is set (Initial value)

Note: H8S/2648, H8S/2648R, and H8S/2647 only.

459

13.3 Operation

13.3.1 Overview

The SCI can carry out serial communication in two modes: asynchronous mode in which

synchronization is achieved character by character, and clocked synchronous mode in which

synchronization is achieved with clock pulses.

Selection of asynchronous or clocked synchronous mode and the transmission format is made

using SMR as shown in table 13-8. The SCI clock is determined by a combination of the C/A bit

in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 13-9.

Asynchronous Mode

• Data length: Choice of 7 or 8 bits

• Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the

combination of these parameters determines the transfer format and character length)

• Detection of framing, parity, and overrun errors, and breaks, during reception

• Choice of internal or external clock as SCI clock source

 When internal clock is selected:

The SCI operates on the baud rate generator clock and a clock with the same frequency as

the bit rate can be output

 When external clock is selected:

A clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate

generator is not used)

Clocked Synchronous Mode

• Transfer format: Fixed 8-bit data

• Detection of overrun errors during reception

• Choice of internal or external clock as SCI clock source

 When internal clock is selected:

The SCI operates on the baud rate generator clock and a serial clock is output off-chip

 When external clock is selected:

The on-chip baud rate generator is not used, and the SCI operates on the input serial clock

460

Table 13-8 SMR Settings and Serial Transfer Format Selection

SMR Settings SCI Transfer Format

Bit 7 Bit 6 Bit 2 Bit 5 Bit 3 Data Multi

Processor Parity Stop Bit

C/ACHR MP PE STOP Mode Length Bit Bit Length

00000Asynchronous 8-bit data No No 1 bit

1mode 2 bits

1 0 Yes 1 bit

1 2 bits

1 0 0 7-bit data No 1 bit

1 2 bits

1 0 Yes 1 bit

1 2 bits

01—0 Asynchronous

mode (multi- 8-bit data Yes No 1 bit

—1processor format) 2 bits

1—0 7-bit data 1 bit

—1 2 bits

1————Clocked

synchronous mode 8-bit data No None

Table 13-9 SMR and SCR Settings and SCI Clock Source Selection

SMR SCR Setting SCI Transmit/Receive Clock

Bit 7 Bit 1 Bit 0 Clock

C/ACKE1 CKE0 Mode Source SCK Pin Function

0 0 0 Asynchronous Internal SCI does not use SCK pin

1mode Outputs clock with same frequency as bit

rate

1 0 External Inputs clock with frequency of 16 times

1the bit rate

1 0 0 Clocked

synchronous Internal Outputs serial clock

1mode

1 0 External Inputs serial clock

461

13.3.2 Operation in Asynchronous Mode

In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the

start of communication and stop bits indicating the end of communication. Serial communication

is thus carried out with synchronization established on a character-by-character basis.

Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex

communication. Both the transmitter and the receiver also have a double-buffered structure, so

that data can be read or written during transmission or reception, enabling continuous data

transfer.

Figure 13-2 shows the general format for asynchronous serial communication.

In asynchronous serial communication, the transmission line is usually held in the mark state (high

level). The SCI monitors the transmission line, and when it goes to the space state (low level),

recognizes a start bit and starts serial communication.

One serial communication character consists of a start bit (low level), followed by data (in LSB-

first order), a parity bit (high or low level), and finally stop bits (high level).

In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in

reception. The SCI samples the data on the 8th pulse of a clock with a frequency of 16 times the

length of one bit, so that the transfer data is latched at the center of each bit.

LSB

Start

bit

MSB

Idle state

(mark state)

Stop bit

Transmit/receive data

D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1

1 1

Serial

data Parity

bit

1 bit 1 or

2 bits

7 or 8 bits 1 bit,

or none

One unit of transfer data (character or frame)

Figure 13-2 Data Format in Asynchronous Communication

(Example with 8-Bit Data, Parity, Two Stop Bits)

462

Data Transfer Format: Table 13-10 shows the data transfer formats that can be used in

asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting.

Table 13-10 Serial Transfer Formats (Asynchronous Mode)

—

S8-bit data

STOP

S7-bit data

STOP

S8-bit data

STOP STOP

S8-bit data P

STOP

S7-bit data

STOP

S8-bit data

MPB STOP

S8-bit data

MPB STOP STOP

S7-bit data

STOPMPB

S7-bit data

STOPMPB STOP

S7-bit data

STOPSTOP

CHR

STOP

SMR Settings

123456789101112

Serial Transfer Format and Frame Length

STOP

S8-bit data P

STOP

S7-bit data

STOP

Legend

S : Start bit

STOP : Stop bit

P : Parity bit

MPB : Multiprocessor bit

463

Clock: Either an internal clock generated by the on-chip baud rate generator or an external clock

input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A

bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see

table 13-9.

When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate

used.

When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The

frequency of the clock output in this case is equal to the bit rate, and the phase is such that the

rising edge of the clock is in the middle of the transmit data, as shown in figure 13-3.

1 frame

D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1

Figure 13-3 Relation between Output Clock and Transfer Data Phase

(Asynchronous Mode)

Data Transfer Operations:

• SCI initialization (asynchronous mode)

Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0,

then initialize the SCI as described below.

When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared

to 0 before making the change using the following procedure. When the TE bit is cleared to 0,

the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not

change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR.

When an external clock is used the clock should not be stopped during operation, including

initialization, since operation is uncertain.

464

Figure 13-4 shows a sample SCI initialization flowchart.

Wait

Start initialization

Set data transfer format in

SMR and SCMR

[1]

Set CKE1 and CKE0 bits in SCR

(TE, RE bits 0)

Yes

Set value in BRR

Clear TE and RE bits in SCR to 0

[2]

[3]

Set TE and RE bits in

SCR to 1, and set RIE, TIE, TEIE,

and MPIE bits [4]

1-bit interval elapsed?

[1] Set the clock selection in SCR.

Be sure to clear bits RIE, TIE,

TEIE, and MPIE, and bits TE and

RE, to 0.

When the clock is selected in

asynchronous mode, it is output

immediately after SCR settings are

made.

[2] Set the data transfer format in SMR

and SCMR.

[3] Write a value corresponding to the

bit rate to BRR. Not necessary if an

external clock is used.

[4] Wait at least one bit interval, then

set the TE bit or RE bit in SCR to 1.

Also set the RIE, TIE, TEIE, and

MPIE bits.

Setting the TE and RE bits enables

the TxD and RxD pins to be used.

Figure 13-4 Sample SCI Initialization Flowchart

465

• Serial data transmission (asynchronous mode)

Figure 13-5 shows a sample flowchart for serial transmission.

The following procedure should be used for serial data transmission.

<End>

[1]

Yes

Initialization

Start transmission

Read TDRE flag in SSR [2]

Write transmit data to TDR

and clear TDRE flag in SSR to 0

Yes

Read TEND flag in SSR

[3]

Yes

[4]

Clear DR to 0 and

set DDR to 1

Clear TE bit in SCR to 0

TDRE=1

All data transmitted?

TEND= 1

Break output?

[1] SCI initialization:

The TxD pin is automatically

designated as the transmit data

output pin.

After the TE bit is set to 1, a frame

of 1s is output, and transmission is

enabled.

[2] SCI status check and transmit data

write:

Read SSR and check that the

TDRE flag is set to 1, then write

transmit data to TDR and clear the

TDRE flag to 0.

[3] Serial transmission continuation

procedure:

To continue serial transmission,

read 1 from the TDRE flag to

confirm that writing is possible,

then write data to TDR, and then

clear the TDRE flag to 0. Checking

and clearing of the TDRE flag is

automatic when the DTC is

activated by a transmit data

empty interrupt (TXI) request, and

date is written to TDR.

[4] Break output at the end of serial

transmission:

To output a break in serial

transmission, set DDR for the port

corresponding to the TxD pin to 1,

clear DR to 0, then clear the TE bit

in SCR to 0.

466

Figure 13-5 Sample Serial Transmission Flowchart

In serial transmission, the SCI operates as described below.

[1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to

TDR, and transfers the data from TDR to TSR.

[2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts

transmission.

If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated.

The serial transmit data is sent from the TxD pin in the following order.

[a] Start bit:

One 0-bit is output.

[b] Transmit data:

8-bit or 7-bit data is output in LSB-first order.

[c] Parity bit or multiprocessor bit:

One parity bit (even or odd parity), or one multiprocessor bit is output.

A format in which neither a parity bit nor a multiprocessor bit is output can also be

selected.

[d] Stop bit(s):

One or two 1-bits (stop bits) are output.

[e] Mark state:

1 is output continuously until the start bit that starts the next transmission is sent.

[3] The SCI checks the TDRE flag at the timing for sending the stop bit.

If the TDRE flag is cleared to 0, the data is transferred from TDR to TSR, the stop bit is sent,

and then serial transmission of the next frame is started.

If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the

“mark state” is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at

this time, a TEI interrupt request is generated.

467

Figure 13-6 shows an example of the operation for transmission in asynchronous mode.

TDRE

TEND

1 frame

D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1

1 1

DataStart

bit Parity

bit Stop

bit Start

bit Data Parity

bit Stop

bit

TXI interrupt

request generated Data written to TDR and

TDRE flag cleared to 0 in

TXI interrupt service routine TEI interrupt

request generated

Idle state

(mark state)

TXI interrupt

request generated

Figure 13-6 Example of Operation in Transmission in Asynchronous Mode

(Example with 8-Bit Data, Parity, One Stop Bit)

468

• Serial data reception (asynchronous mode)

Figure 13-7 shows a sample flowchart for serial reception.

The following procedure should be used for serial data reception.

Yes

<End>

[1]

Initialization

Start reception

[2]

Yes

Read RDRF flag in SSR [4]

[5]

Clear RE bit in SCR to 0

Read ORER, PER, and

FER flags in SSR

Error processing

(Continued on next page)

[3]

Read receive data in RDR, and

clear RDRF flag in SSR to 0

Yes

PER∨FER∨ORER= 1

RDRF= 1

All data received?

SCI initialization:

The RxD pin is automatically

designated as the receive data

input pin.

Receive error processing and

break detection:

If a receive error occurs, read the

ORER, PER, and FER flags in

SSR to identify the error. After

performing the appropriate error

processing, ensure that the

ORER, PER, and FER flags are

all cleared to 0. Reception cannot

be resumed if any of these flags

are set to 1. In the case of a

framing error, a break can be

detected by reading the value of

the input port corresponding to

the RxD pin.

SCI status check and receive

data read :

Read SSR and check that RDRF

= 1, then read the receive data in

RDR and clear the RDRF flag to

0. Transition of the RDRF flag

from 0 to 1 can also be identified

by an RXI interrupt.

Serial reception continuation

procedure:

To continue serial reception,

before the stop bit for the current

frame is received, read the

RDRF flag, read RDR, and clear

the RDRF flag to 0. The RDRF

flag is cleared automatically

when DTC is activated by an RXI

interrupt and the RDR value is

read.

[1]

[2] [3]

[4]

[5]

Figure 13-7 Sample Serial Reception Data Flowchart

469

<End>

[3]

Error processing

Parity error processing

Yes

Clear ORER, PER, and

FER flags in SSR to 0

Yes

Framing error processing

Yes

Overrun error processing

ORER= 1

FER= 1

Break?

PER= 1

Clear RE bit in SCR to 0

Figure 13-7 Sample Serial Reception Data Flowchart (cont)

470

In serial reception, the SCI operates as described below.

[1] The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal

synchronization and starts reception.

[2] The received data is stored in RSR in LSB-to-MSB order.

[3] The parity bit and stop bit are received.

After receiving these bits, the SCI carries out the following checks.

[a] Parity check:

The SCI checks whether the number of 1 bits in the receive data agrees with the parity

(even or odd) set in the O/E bit in SMR.

[b] Stop bit check:

The SCI checks whether the stop bit is 1.

If there are two stop bits, only the first is checked.

[c] Status check:

The SCI checks whether the RDRF flag is 0, indicating that the receive data can be

transferred from RSR to RDR.

If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in

RDR.

If a receive error* is detected in the error check, the operation is as shown in table 13-11.

Note: * Subsequent receive operations cannot be performed when a receive error has occurred.

Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be

cleared to 0.

[4] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive data full interrupt

(RXI) request is generated.

Also, if the RIE bit in SCR is set to 1 when the ORER, PER, or FER flag changes to 1, a

receive error interrupt (ERI) request is generated.

471

Table 13-11 Receive Errors and Conditions for Occurrence

Receive Error Abbreviation Occurrence Condition Data Transfer

Overrun error ORER When the next data reception is

completed while the RDRF flag

in SSR is set to 1

Receive data is not

transferred from RSR to

RDR.

Framing error FER When the stop bit is 0 Receive data is transferred

from RSR to RDR.

Parity error PER When the received data differs

from the parity (even or odd) set

in SMR

Receive data is transferred

from RSR to RDR.

Figure 13-8 shows an example of the operation for reception in asynchronous mode.

RDRF

FER

1 frame

D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 0

1 1

DataStart

bit Parity

bit Stop

bit Start

bit Data Parity

bit Stop

bit

RXI interrupt

request

generated ERI interrupt request

generated by framing

error

Idle state

(mark state)

RDR data read and RDRF

flag cleared to 0 in RXI

interrupt service routine

Figure 13-8 Example of SCI Operation in Reception

(Example with 8-Bit Data, Parity, One Stop Bit)

472

13.3.3 Multiprocessor Communication Function

The multiprocessor communication function performs serial communication using the

multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous

mode. Use of this function enables data transfer to be performed among a number of processors

sharing transmission lines.

When multiprocessor communication is carried out, each receiving station is addressed by a

unique ID code.

The serial communication cycle consists of two component cycles: an ID transmission cycle

which specifies the receiving station , and a data transmission cycle. The multiprocessor bit is used

to differentiate between the ID transmission cycle and the data transmission cycle.

The transmitting station first sends the ID of the receiving station with which it wants to perform

serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data

with a 0 multiprocessor bit added.

The receiving station skips the data until data with a 1 multiprocessor bit is sent.

When data with a 1 multiprocessor bit is received, the receiving station compares that data with its

own ID. The station whose ID matches then receives the data sent next. Stations whose ID does

not match continue to skip the data until data with a 1 multiprocessor bit is again received. In this

way, data communication is carried out among a number of processors.

Figure 13-9 shows an example of inter-processor communication using the multiprocessor format.

Data Transfer Format: There are four data transfer formats.

When the multiprocessor format is specified, the parity bit specification is invalid.

For details, see table 13-10.

Clock: See the section on asynchronous mode.

473

Transmitting

station

Receiving

station A

(ID= 01)

Receiving

station B

(ID= 02)

Receiving

station C

(ID= 03)

Receiving

station D

(ID= 04)

Serial transmission line

Serial

data

ID transmission cycle=

receiving station

specification

Data transmission cycle=

Data transmission to

receiving station specified by ID

(MPB= 1) (MPB= 0)

H'01 H'AA

Legend

MPB: Multiprocessor bit

Figure 13-9 Example of Inter-Processor Communication Using Multiprocessor Format

(Transmission of Data H'AA to Receiving Station A)

Data Transfer Operations:

• Multiprocessor serial data transmission

Figure 13-10 shows a sample flowchart for multiprocessor serial data transmission.

The following procedure should be used for multiprocessor serial data transmission.

474

<End>

[1]

Yes

Initialization

Start transmission

Read TDRE flag in SSR [2]

Write transmit data to TDR and

set MPBT bit in SSR

Yes

Read TEND flag in SSR

[3]

Yes

[4]

Clear DR to 0 and set DDR to 1

Clear TE bit in SCR to 0

TDRE= 1

All data transmitted?

TEND= 1

Break output?

Clear TDRE flag to 0

SCI initialization:

The TxD pin is automatically

designated as the transmit data

output pin.

After the TE bit is set to 1, a

frame of 1s is output, and

transmission is enabled.

SCI status check and transmit

data write:

Read SSR and check that the

TDRE flag is set to 1, then write

transmit data to TDR. Set the

MPBT bit in SSR to 0 or 1.

Finally, clear the TDRE flag to 0.

Serial transmission continuation

procedure:

To continue serial transmission,

be sure to read 1 from the TDRE

flag to confirm that writing is

possible, then write data to TDR,

and then clear the TDRE flag to

0. Checking and clearing of the

TDRE flag is automatic when the

DTC is activated by a transmit

data empty interrupt (TXI)

request, and data is written to

TDR.

Break output at the end of serial

transmission:

To output a break in serial

transmission, set the port DDR to

1, clear DR to 0, then clear the

TE bit in SCR to 0.

[1]

[2]

[3]

[4]

Figure 13-10 Sample Multiprocessor Serial Transmission Flowchart

475

In serial transmission, the SCI operates as described below.

[1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to

TDR, and transfers the data from TDR to TSR.

[2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts

transmission.

If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt (TXI) is generated.

The serial transmit data is sent from the TxD pin in the following order.

[a] Start bit:

One 0-bit is output.

[b] Transmit data:

8-bit or 7-bit data is output in LSB-first order.

[c] Multiprocessor bit

One multiprocessor bit (MPBT value) is output.

[d] Stop bit(s):

One or two 1-bits (stop bits) are output.

[e] Mark state:

1 is output continuously until the start bit that starts the next transmission is sent.

[3] The SCI checks the TDRE flag at the timing for sending the stop bit.

If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, the stop bit is sent, and

then serial transmission of the next frame is started.

If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the

mark state is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this

time, a transmission end interrupt (TEI) request is generated.

476

Figure 13-11 shows an example of SCI operation for transmission using the multiprocessor

format.

TDRE

TEND

1 frame

D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1

1 1

DataStart

bit

Multi-

proce-

ssor

bit Stop

bit Start

bit Data Multi-

proces-

sor bit Stop

bit

TXI interrupt

request generated Data written to TDR

and TDRE flag cleared to

0 in TXI interrupt service

routine

TEI interrupt

request generated

Idle state

(mark state)

TXI interrupt

request generated

Figure 13-11 Example of SCI Operation in Transmission

(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)

• Multiprocessor serial data reception

Figure 13-12 shows a sample flowchart for multiprocessor serial reception.

The following procedure should be used for multiprocessor serial data reception.

477

Yes

<End>

[1]

Initialization

Start reception

Yes

[4]

Clear RE bit in SCR to 0

Error processing

(Continued on

next page)

[5]

Yes

FER∨ORER= 1

RDRF= 1

All data received?

Set MPIE bit in SCR to 1 [2]

Read ORER and FER flags in SSR

Read RDRF flag in SSR [3]

Read receive data in RDR

Yes

This station’s ID?

Read ORER and FER flags in SSR

Yes

Read RDRF flag in SSR

Yes

FER∨ORER= 1

Read receive data in RDR

RDRF= 1

SCI initialization:

The RxD pin is automatically

designated as the receive data

input pin.

ID reception cycle:

Set the MPIE bit in SCR to 1.

SCI status check, ID reception

and comparison:

Read SSR and check that the

RDRF flag is set to 1, then read

the receive data in RDR and

compare it with this station’s ID.

If the data is not this station’s ID,

set the MPIE bit to 1 again, and

clear the RDRF flag to 0.

If the data is this station’s ID,

clear the RDRF flag to 0.

SCI status check and data

reception:

Read SSR and check that the

RDRF flag is set to 1, then read

the data in RDR.

Receive error processing and

break detection:

If a receive error occurs, read the

ORER and FER flags in SSR to

identify the error. After

performing the appropriate error

processing, ensure that the

ORER and FER flags are all

cleared to 0.

Reception cannot be resumed if

either of these flags is set to 1.

In the case of a framing error, a

break can be detected by reading

the RxD pin value.

[1]

[2]

[3]

[4]

[5]

Figure 13-12 Sample Multiprocessor Serial Reception Flowchart

478

<End>

Error processing

Yes

Clear ORER, PER, and

FER flags in SSR to 0

Yes

Framing error processing

Overrun error processing

ORER= 1

FER= 1

Break?

Clear RE bit in SCR to 0

[5]

Figure 13-12 Sample Multiprocessor Serial Reception Flowchart (cont)

479

Figure 13-13 shows an example of SCI operation for multiprocessor format reception.

MPIE

RDR

value

0D0 D1 D7 1 1 0 D0 D1 D7 0 1

Data (ID1)Start

bit MPB Stop

bit Start

bit Data (Data1) MPB Stop

bit

RXI interrupt

request

(multiprocessor

interrupt)

generated

MPIE = 0

Idle state

(mark state)

RDRF

RDR data read

and RDRF flag

cleared to 0 in

RXI interrupt

service routine

If not this station’s ID,

MPIE bit is set to 1

again

RXI interrupt request is

not generated, and RDR

retains its state

ID1

(a) Data does not match station’s ID

MPIE

RDR

value

0D0 D1 D7 1 1 0 D0 D1 D7 0 1

Data (ID2)Start

bit MPB Stop

bit Start

bit Data (Data2) MPB Stop

bit

RXI interrupt

request

(multiprocessor

interrupt)

generated

MPIE = 0

Idle state

(mark state)

RDRF

RDR data read and

RDRF flag cleared

to 0 in RXI interrupt

service routine

Matches this station’s ID,

so reception continues, and

data is received in RXI

interrupt service routine

MPIE bit set to 1

again

ID2

(b) Data matches station’s ID

Data2ID1

Figure 13-13 Example of SCI Operation in Reception

(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)

480

13.3.4 Operation in Clocked Synchronous Mode

In clocked synchronous mode, data is transmitted or received in synchronization with clock

pulses, making it suitable for high-speed serial communication.

Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex

communication by use of a common clock. Both the transmitter and the receiver also have a

double-buffered structure, so that data can be read or written during transmission or reception,

enabling continuous data transfer.

Figure 13-14 shows the general format for clocked synchronous serial communication.

Don’t

care

Don’t

care

One unit of transfer data (character or frame)

Bit 0

Serial

data

Serial

clock

Bit 1 Bit 3 Bit 4 Bit 5

LSB MSB

Bit 2 Bit 6 Bit 7

Note: * High except in continuous transfer

Figure 13-14 Data Format in Synchronous Communication

In clocked synchronous serial communication, data on the transmission line is output from one

falling edge of the serial clock to the next. Data confirmation is guaranteed at the rising edge of

the serial clock.

In clocked serial communication, one character consists of data output starting with the LSB and

ending with the MSB. After the MSB is output, the transmission line holds the MSB state.

In clocked synchronous mode, the SCI receives data in synchronization with the rising edge of the

serial clock.

Data Transfer Format: A fixed 8-bit data format is used.

No parity or multiprocessor bits are added.

Clock: Either an internal clock generated by the on-chip baud rate generator or an external serial

clock input at the SCK pin can be selected, according to the setting of the C/A bit in SMR and the

CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 13-9.

When the SCI is operated on an internal clock, the serial clock is output from the SCK pin.

481

Eight serial clock pulses are output in the transfer of one character, and when no transfer is

performed the clock is fixed high. When only receive operations are performed, however, the

serial clock is output until an overrun error occurs or the RE bit is cleared to 0. If you want to

perform receive operations in units of one character, you should select an external clock as the

clock source.

Data Transfer Operations:

• SCI initialization (clocked synchronous mode)

Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0,

then initialize the SCI as described below.

When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared

to 0 before making the change using the following procedure. When the TE bit is cleared to 0,

the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not

change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR.

Figure 13-15 shows a sample SCI initialization flowchart.

Wait

Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared

to 0 or set to 1 simultaneously.

Start initialization

Set data transfer format in

SMR and SCMR

Yes

Set value in BRR

Clear TE and RE bits in SCR to 0

[2]

[3]

Set TE and RE bits in SCR to 1, and

set RIE, TIE, TEIE, and MPIE bits [4]

1-bit interval elapsed?

[1]

[1] Set the clock selection in SCR. Be sure

to clear bits RIE, TIE, TEIE, and MPIE,

TE and RE, to 0.

[2] Set the data transfer format in SMR

and SCMR.

[3] Write a value corresponding to the bit

rate to BRR. Not necessary if an

external clock is used.

[4] Wait at least one bit interval, then set

the TE bit or RE bit in SCR to 1.

Also set the RIE, TIE, TEIE, and MPIE

bits.

Setting the TE and RE bits enables the

TxD and RxD pins to be used.

Set CKE1 and CKE0 bits in SCR

(TE, RE bits 0)

Figure 13-15 Sample SCI Initialization Flowchart

482

• Serial data transmission (clocked synchronous mode)

Figure 13-16 shows a sample flowchart for serial transmission.

The following procedure should be used for serial data transmission.

<End>

[1]

Yes

Initialization

Start transmission

Read TDRE flag in SSR [2]

Write transmit data to TDR and

clear TDRE flag in SSR to 0

Yes

Read TEND flag in SSR

[3]

Clear TE bit in SCR to 0

TDRE= 1

All data transmitted?

TEND= 1

[1] SCI initialization:

The TxD pin is automatically

designated as the transmit data output

pin.

[2] SCI status check and transmit data

write:

Read SSR and check that the TDRE

flag is set to 1, then write transmit data

to TDR and clear the TDRE flag to 0.

[3] Serial transmission continuation

procedure:

To continue serial transmission, be

sure to read 1 from the TDRE flag to

confirm that writing is possible, then

write data to TDR, and then clear the

TDRE flag to 0.

Checking and clearing of the TDRE

flag is automatic when the DTC is

activated by a transmit data empty

interrupt (TXI) request and data is

written to TDR.

Figure 13-16 Sample Serial Transmission Flowchart

483

In serial transmission, the SCI operates as described below.

[1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to

TDR, and transfers the data from TDR to TSR.

[2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts

transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt

(TXI) is generated.

When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an

external clock has been specified, data is output synchronized with the input clock.

The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with

the MSB (bit 7).

[3] The SCI checks the TDRE flag at the timing for sending the MSB (bit 7).

If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission

of the next frame is started.

If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the MSB (bit 7) is sent, and the

TxD pin maintains its state.

If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated.

[4] After completion of serial transmission, the SCK pin is fixed high.

Figure 13-17 shows an example of SCI operation in transmission.

Transfer direction

Bit 0

Serial data

Serial clock

1 frame

TDRE

TEND

Bit 1 Bit 7 Bit 0 Bit 1 Bit 7Bit 6

Data written to TDR

and TDRE flag

cleared to 0 in TXI

interrupt service routine

TEI interrupt

request generated

TXI interrupt

request generated

TXI interrupt

request generated

Figure 13-17 Example of SCI Operation in Transmission

484

• Serial data reception (clocked synchronous mode)

Figure 13-18 shows a sample flowchart for serial reception.

The following procedure should be used for serial data reception.

When changing the operating mode from asynchronous to clocked synchronous, be sure to

check that the ORER, PER, and FER flags are all cleared to 0.

The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor

receive operations will be possible.

485

Yes

<End>

[1]

Initialization

Start reception

[2]

Yes

Read RDRF flag in SSR [4]

[5]

Clear RE bit in SCR to 0

Error processing

(Continued below)

[3]

Read receive data in RDR, and

clear RDRF flag in SSR to 0

Yes

ORER= 1

RDRF= 1

All data received?

Read ORER flag in SSR

[1]

[2] [3]

[4]

[5]

SCI initialization:

The RxD pin is automatically

designated as the receive data

input pin.

Receive error processing:

If a receive error occurs, read the

ORER flag in SSR , and after

performing the appropriate error

processing, clear the ORER flag

to 0. Transfer cannot be resumed

if the ORER flag is set to 1.

SCI status check and receive

data read:

Read SSR and check that the

RDRF flag is set to 1, then read

the receive data in RDR and

clear the RDRF flag to 0.

Transition of the RDRF flag from

0 to 1 can also be identified by

an RXI interrupt.

Serial reception continuation

procedure:

To continue serial reception,

before the MSB (bit 7) of the

current frame is received, finish

reading the RDRF flag, reading

RDR, and clearing the RDRF flag

to 0. The RDRF flag is cleared

automatically when the DTC is

activated by a receive data full

interrupt (RXI) request and the

RDR value is read.

<End>

Error processing

Overrun error processing

[3]

Clear ORER flag in SSR to 0

Figure 13-18 Sample Serial Reception Flowchart

486

In serial reception, the SCI operates as described below.

[1] The SCI performs internal initialization in synchronization with serial clock input or output.

[2] The received data is stored in RSR in LSB-to-MSB order.

After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be

transferred from RSR to RDR.

If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a

receive error is detected in the error check, the operation is as shown in table 13-11.

Neither transmit nor receive operations can be performed subsequently when a receive error

has been found in the error check.

[3] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive data full interrupt

(RXI) request is generated.

Also, if the RIE bit in SCR is set to 1 when the ORER flag changes to 1, a receive error

interrupt (ERI) request is generated.

Figure 13-19 shows an example of SCI operation in reception.

Bit 7

Serial

data

Serial

clock

1 frame

RDRF

ORER

Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7

RXI interrupt request

generated RDR data read and

RDRF flag cleared to 0

in RXI interrupt service

routine

RXI interrupt request

generated ERI interrupt request

generated by overrun

error

Figure 13-19 Example of SCI Operation in Reception

• Simultaneous serial data transmission and reception (clocked synchronous mode)

Figure 13-20 shows a sample flowchart for simultaneous serial transmit and receive operations.

The following procedure should be used for simultaneous serial data transmit and receive

operations.

487

Yes

<End>

[1]

Initialization

Start transmission/reception

[5]

Error processing

[3]

Read receive data in RDR, and

clear RDRF flag in SSR to 0

Yes

ORER= 1

All data received?

[2]

Read TDRE flag in SSR

Yes

TDRE= 1

Write transmit data to TDR and

clear TDRE flag in SSR to 0

Yes

RDRF= 1

Read ORER flag in SSR

[4]

Read RDRF flag in SSR

Clear TE and RE bits in SCR to 0

Note: When switching from transmit or receive operation to simultaneous

transmit and receive operations, first clear the TE bit and RE bit to

0, then set both these bits to 1 simultaneously.

[1]

[2]

[3]

[4]

[5]

SCI initialization:

The TxD pin is designated as the

transmit data output pin, and the

RxD pin is designated as the

receive data input pin, enabling

simultaneous transmit and receive

operations.

SCI status check and transmit data

write:

Read SSR and check that the

TDRE flag is set to 1, then write

transmit data to TDR and clear the

TDRE flag to 0.

Transition of the TDRE flag from 0

to 1 can also be identified by a TXI

interrupt.

Receive error processing:

If a receive error occurs, read the

ORER flag in SSR , and after

performing the appropriate error

processing, clear the ORER flag to

0. Transmission/reception cannot be

resumed if the ORER flag is set to

SCI status check and receive data

read:

Read SSR and check that the

RDRF flag is set to 1, then read the

receive data in RDR and clear the

RDRF flag to 0. Transition of the

RDRF flag from 0 to 1 can also be

identified by an RXI interrupt.

Serial transmission/reception

continuation procedure:

To continue serial transmission/

reception, before the MSB (bit 7) of

the current frame is received, finish

reading the RDRF flag, reading

RDR, and clearing the RDRF flag to

0. Also, before the MSB (bit 7) of

the current frame is transmitted,

read 1 from the TDRE flag to

confirm that writing is possible.

Then write data to TDR and clear

the TDRE flag to 0.

Checking and clearing of the TDRE

flag is automatic when the DTC is

activated by a transmit data empty

interrupt (TXI) request and data is

written to TDR. Also, the RDRF flag

is cleared automatically when the

DTC is activated by a receive data

full interrupt (RXI) request and the

RDR value is read.

Figure 13-20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations

488

13.4 SCI Interrupts

The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt

(ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI)

request. Table 13-12 shows the interrupt sources and their relative priorities. Individual interrupt

sources can be enabled or disabled with the TIE, RIE, and TEIE bits in the SCR. Each kind of

interrupt request is sent to the interrupt controller independently.

When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag

in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC to

perform data transfer. The TDRE flag is cleared to 0 automatically when data transfer is

performed by the DTC. The DTC cannot be activated by a TEI interrupt request.

When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER,

PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can

activate the DTC to perform data transfer. The RDRF flag is cleared to 0 automatically when data

transfer is performed by the DTC. The DTC cannot be activated by an ERI interrupt request.

Table 13-12 SCI Interrupt Sources

Channel Interrupt

Source Description DTC

Activation Priority*

0 ERI Interrupt due to receive error (ORER, FER, or PER) Not possible High

RXI Interrupt due to receive data full state (RDRF) Possible

TXI Interrupt due to transmit data empty state (TDRE) Possible

TEI Interrupt due to transmission end (TEND) Not possible

1 ERI Interrupt due to receive error (ORER, FER, or PER) Not possible

RXI Interrupt due to receive data full state (RDRF) Possible

TXI Interrupt due to transmit data empty state (TDRE) Possible

TEI Interrupt due to transmission end (TEND) Not possible

(H8S/2648, ERI Interrupt due to receive error (ORER, FER, or PER) Not possible

H8S/2648R,

H8S/2647) RXI Interrupt due to receive data full state (RDRF) Possible

TXI Interrupt due to transmit data empty state (TDRE) Possible

TEI Interrupt due to transmission end (TEND) Not possible Low

Note: *This table shows the initial state immediately after a reset. Relative priorities among

channels can be changed by means of the interrupt controller.

489

A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The

TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a

TXI interrupt are requested simultaneously, the TXI interrupt may have priority for acceptance,

with the result that the TDRE and TEND flags are cleared. Note that the TEI interrupt will not be

accepted in this case.

13.5 Usage Notes

The following points should be noted when using the SCI.

Relation between Writes to TDR and the TDRE Flag

The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from

TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1.

Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is

written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has

not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1

before writing transmit data to TDR.

Operation when Multiple Receive Errors Occur Simultaneously

If a number of receive errors occur at the same time, the state of the status flags in SSR is as

shown in table 13-13. If there is an overrun error, data is not transferred from RSR to RDR, and

the receive data is lost.

Table 13-13 State of SSR Status Flags and Transfer of Receive Data

SSR Status Flags Receive Data Transfer

RDRF ORER FER PER RSR to RDR Receive Error Status

1100X Overrun error

0010 Framing error

0001 Parity error

1110X Overrun error + framing error

1101X Overrun error + parity error

0011 Framing error + parity error

1111X Overrun error + framing error +

parity error

Legend

: Receive data is transferred from RSR to RDR.

X: Receive data is not transferred from RSR to RDR.

490

Break Detection and Processing (Asynchronous Mode Only): When framing error (FER)

detection is performed, a break can be detected by reading the RxD pin value directly. In a break,

the input from the RxD pin becomes all 0s, and so the FER flag is set, and the parity error flag

(PER) may also be set.

Note that, since the SCI continues the receive operation after receiving a break, even if the FER

flag is cleared to 0, it will be set to 1 again.

Sending a Break (Asynchronous Mode Only): The TxD pin has a dual function as an I/O port

whose direction (input or output) is determined by DR and DDR. This can be used to send a break.

Between serial transmission initialization and setting of the TE bit to 1, the mark state is replaced

by the value of DR (the pin does not function as the TxD pin until the TE bit is set to 1).

Consequently, DDR and DR for the port corresponding to the TxD pin are first set to 1.

To send a break during serial transmission, first clear DR to 0, then clear the TE bit to 0.

When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission

state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin.

Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only):

Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if

the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting

transmission.

Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0.

Receive Data Sampling Timing and Reception Margin in Asynchronous Mode:

In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transfer

rate.

In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs

internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the

basic clock. This is illustrated in figure 13-21.

491

Internal basic

clock

16 clocks

8 clocks

Receive data

(RxD)

Synchronization

sampling timing

Start bit D0 D1

Data sampling

timing

15 0 7 15 007

Figure 13-21 Receive Data Sampling Timing in Asynchronous Mode

Thus the reception margin in asynchronous mode is given by formula (1) below.

M = | (0.5 –1

2N ) – (L – 0.5) F –| D – 0.5 |

N (1 + F) | × 100%

... Formula (1)

Where M : Reception margin (%)

N : Ratio of bit rate to clock (N = 16)

D : Clock duty (D = 0 to 1.0)

L : Frame length (L = 9 to 12)

F : Absolute value of clock rate deviation

Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin of 46.875% is given by

formula (2) below.

When D = 0.5 and F = 0,

M = (0.5 –1

2 × 16 ) × 100%

= 46.875% ... Formula (2)

However, this is only the computed value, and a margin of 20% to 30% should be allowed in

system design.

492

Restrictions on Use of DTC

• When an external clock source is used as the serial clock, the transmit clock should not be

input until at least 5 ø clock cycles after TDR is updated by the DTC. Misoperation may occur

if the transmit clock is input within 4 ø clocks after TDR is updated. (Figure 13-22)

• When RDR is read by the DTC, be sure to set the activation source to the relevant SCI

reception end interrupt (RXI).

LSB

Serial data

SCK

D1 D3 D4 D5D2 D6 D7

Note: When operating on an external clock, set t >4 clocks.

TDRE

Figure 13-22 Example of Clocked Synchronous Transmission by DTC

Operation in Case of Mode Transition

• Transmission

Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module

stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition.

TSR, TDR, and SSR are reset. The output pin states in module stop mode, software standby

mode, watch mode, subactive mode, or subsleep mode depend on the port settings, and

becomes high-level output after the relevant mode is cleared. If a transition is made during

transmission, the data being transmitted will be undefined. When transmitting without

changing the transmit mode after the relevant mode is cleared, transmission can be started by

setting TE to 1 again, and performing the following sequence: SSR read → TDR write →

TDRE clearance. To transmit with a different transmit mode after clearing the relevant mode,

the procedure must be started again from initialization. Figure 13-23 shows a sample flowchart

for mode transition during transmission. Port pin states are shown in figures 13-24 and 13-25.

Operation should also be stopped (by clearing TE, TIE, and TEIE to 0) before making a

transition from transmission by DTC transfer to module stop mode, software standby mode,

watch mode, subactive mode, or subsleep mode transition. To perform transmission with the

DTC after the relevant mode is cleared, setting TE and TIE to 1 will set the TXI flag and start

DTC transmission.

493

• Reception

Receive operation should be stopped (by clearing RE to 0) before making a module stop mode,

software standby mode, watch mode, subactive mode, or subsleep mode transition. RSR,

RDR, and SSR are reset. If a transition is made without stopping operation, the data being

received will be invalid.

To continue receiving without changing the reception mode after the relevant mode is cleared,

set RE to 1 before starting reception. To receive with a different receive mode, the procedure

must be started again from initialization.

Figure 13-26 shows a sample flowchart for mode transition during reception.

Read TEND flag in SSR

TE = 0

Transition to software

standby mode, etc.

Exit from software

standby mode, etc.

Change

operating mode? No

All data

transmitted?

TEND = 1

Yes

[1]

[3]

[2]

TE = 1Initialization

[1] Data being transmitted is interrupted.

After exiting software standby mode,

etc., normal CPU transmission is

possible by setting TE to 1, reading

SSR, writing TDR, and clearing

TDRE to 0, but note that if the DTC

has been activated, the remaining

data in DTCRAM will be transmitted

when TE and TIE are set to 1.

[2] If TIE and TEIE are set to 1, clear

them to 0 in the same way.

[3] Includes module stop mode.

Figure 13-23 Sample Flowchart for Mode Transition during Transmission

494

SCK output pin

TE bit

TxD output pin Port input/output High outputPort input/output High output Start Stop

Start of transmission End of

transmission

Port input/output

SCI TxD output Port SCI TxD

output

Port

Transition

to software

standby

Exit from

software

standby

Figure 13-24 Asynchronous Transmission Using Internal Clock

Port input/output

Last TxD bit held

High output*Port input/output Marking output

Port input/output

SCI TxD output PortPort

Note: * Initialized by software standby.

SCK output pin

TE bit

TxD output pin

SCI TxD

output

Start of transmission End of

transmission

Transition

to software

standby

Exit from

software

standby

Figure 13-25 Synchronous Transmission Using Internal Clock

495

RE = 0

Transition to software

standby mode, etc.

Read receive data in RDR

Read RDRF flag in SSR

Exit from software

standby mode, etc.

Change

operating mode? No

RDRF = 1

Yes

No [1]

[2]

RE = 1Initialization

[1] Receive data being received

becomes invalid.

[2] Includes module stop mode.

Figure 13-26 Sample Flowchart for Mode Transition during Reception

496

Switching from SCK Pin Function to Port Pin Function:

• Problem in Operation: When switching the SCK pin function to the output port function (high-

level output) by making the following settings while DDR = 1, DR = 1, C/A = 1, CKE1 = 0,

CKE0 = 0, and TE = 1 (synchronous mode), low-level output occurs for one half-cycle.

1. End of serial data transmission

2. TE bit = 0

3. C/A bit = 0 ... switchover to port output

4. Occurrence of low-level output (see figure 13-27)

SCK/port

Data

C/A

CKE1

CKE0

Bit 7Bit 6

1. End of transmission 4. Low-level output

3. C/A = 0

2. TE = 0

Half-cycle low-level output

Figure 13-27 Operation when Switching from SCK Pin Function to Port Pin Function

497

• Sample Procedure for Avoiding Low-Level Output: As this sample procedure temporarily

places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an

external circuit.

With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following

settings in the order shown.

1. End of serial data transmission

2. TE bit = 0

3. CKE1 bit = 1

4. C/A bit = 0 ... switchover to port output

5. CKE1 bit = 0

SCK/port

Data

C/A

CKE1

CKE0

Bit 7Bit 6

1. End of transmission

3. CKE1 = 1 5. CKE1 = 0

4. C/A = 0

2. TE = 0

High-level output

Figure 13-28 Operation when Switching from SCK Pin Function to Port Pin Function

(Example of Preventing Low-Level Output)

498

499

Section 14 Smart Card Interface

14.1 Overview

SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification

Card) as a serial communication interface extension function.

Switching between the normal serial communication interface and the Smart Card interface is

carried out by means of a register setting.

14.1.1 Features

Features of the Smart Card interface supported by the H8S/2646 Series are as follows.

• Asynchronous mode

 Data length: 8 bits

 Parity bit generation and checking

 Transmission of error signal (parity error) in receive mode

 Error signal detection and automatic data retransmission in transmit mode

 Direct convention and inverse convention both supported

• On-chip baud rate generator allows any bit rate to be selected

• Three interrupt sources

 Three interrupt sources (transmit data empty, receive data full, and transmit/receive error)

that can issue requests independently

 The transmit data empty interrupt and receive data full interrupt can activate the data

transfer controller (DTC) to execute data transfer

500

14.1.2 Block Diagram

Figure 14-1 shows a block diagram of the Smart Card interface.

Bus interface

TDR

RSR

RDR

Module data bus

TSR

SCMR

SSR

SCR

Transmission/

reception control

BRR

Baud rate

generator

Internal

data bus

RxD

TxD

SCK

Parity generation

Parity check

Clock

ø/4

ø/16

ø/64

TXI

RXI

ERI

SMR

Legend

SCMR

RSR

RDR

TSR

TDR

SMR

SCR

SSR

BRR

: Smart Card mode register

: Receive shift register

: Receive data register

: Transmit shift register

: Transmit data register

: Serial mode register

: Serial control register

: Serial status register

: Bit rate register

Figure 14-1 Block Diagram of Smart Card Interface

501

14.1.3 Pin Configuration

Table 14-1 shows the Smart Card interface pin configuration.

Table 14-1 Smart Card Interface Pins

Channel Pin Name Symbol I/O Function

0 Serial clock pin 0 SCK0 I/O SCI0 clock input/output

Receive data pin 0 RxD0 Input SCI0 receive data input

Transmit data pin 0 TxD0 Output SCI0 transmit data output

1 Serial clock pin 1 SCK1 I/O SCI1 clock input/output

Receive data pin 1 RxD1 Input SCI1 receive data input

Transmit data pin 1 TxD1 Output SCI1 transmit data output

(H8S/2648, Serial clock pin 2 SCK2 I/O SCI2 clock input/output

H8S/2648R,

H8S/2647) Receive data pin 2 RxD2 Input SCI2 receive data input

Transmit data pin 2 TxD2 Output SCI2 transmit data output

502

14.1.4 Register Configuration

Table 14-2 shows the registers used by the Smart Card interface. Details of SMR, BRR, SCR,

TDR, RDR, and MSTPCR are the same as for the normal SCI function: see the register

descriptions in section 13, Serial Communication Interface (SCI).

Table 14-2 Smart Card Interface Registers

Channel Name Abbreviation R/W Initial Value Address*1

0 Serial mode register 0 SMR0 R/W H'00 H'FF78

Bit rate register 0 BRR0 R/W H'FF H'FF79

Serial control register 0 SCR0 R/W H'00 H'FF7A

Transmit data register 0 TDR0 R/W H'FF H'FF7B

Serial status register 0 SSR0 R/(W)*2H'84 H'FF7C

Receive data register 0 RDR0 R H'00 H'FF7D

Smart card mode

1 Serial mode register 1 SMR1 R/W H'00 H'FF80

Bit rate register 1 BRR1 R/W H'FF H'FF81

Serial control register 1 SCR1 R/W H'00 H'FF82

Transmit data register 1 TDR1 R/W H'FF H'FF83

Serial status register 1 SSR1 R/(W)*2H'84 H'FF84

Receive data register 1 RDR1 R H'00 H'FF85

Smart card mode register 1 SCMR1 R/W H'F2 H'FF86

(H8S/2648, Serial mode register 2 SMR2 R/W H'00 H'FF88

H8S/2648R,

H8S/2647) Bit rate register 2 BRR2 R/W H'FF H'FF89

Serial control register 2 SCR2 R/W H'00 H'FF8A

Transmit data register 2 TDR2 R/W H'FF H'FF8B

Serial status register 2 SSR2 R/(W)*2H'84 H'FF8C

Receive data register 2 RDR2 R H'00 H'FF8D

Smart card mode register 2 SCMR2 R/W H'F2 H'FF8E

All Module stop control register B MSTPCRB R/W H'FF H'FDE9

Notes: *1 Lower 16 bits of the address.

*2 Can only be written with 0 for flag clearing.

503

14.2 Register Descriptions

Registers added with the Smart Card interface and bits for which the function changes are

described here.

14.2.1 Smart Card Mode Register (SCMR)

Bit:76543210

— — — — SDIR SINV — SMIF

Initial value : 1 1 1 1 0 0 1 0

R/W : — — — — R/W R/W — R/W

SCMR is an 8-bit readable/writable register that selects the Smart Card interface function.

SCMR is initialized to H'F2 by a reset and in standby mode.

Bits 7 to 4—Reserved: It is always read as 1 and cannot be modified.

Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion

format.

Bit 3

SDIR Description

0 TDR contents are transmitted LSB-first (Initial value)

Receive data is stored in RDR LSB-first

1 TDR contents are transmitted MSB-first

Receive data is stored in RDR MSB-first

504

Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This

function is used together with the SDIR bit for communication with an inverse convention card.

The SINV bit does not affect the logic level of the parity bit. For parity-related setting procedures,

see section 14.3.4, Register Settings.

Bit 2

SINV Description

0 TDR contents are transmitted as they are (Initial value)

Receive data is stored as it is in RDR

1 TDR contents are inverted before being transmitted

Receive data is stored in inverted form in RDR

Bit 1—Reserved: It is always read as 1 and cannot be modified.

Bit 0—Smart Card Interface Mode Select (SMIF): Enables or disables the Smart Card interface

function.

Bit 0

SMIF Description

0 Smart Card interface function is disabled (Initial value)

1 Smart Card interface function is enabled

505

14.2.2 Serial Status Register (SSR)

Bit:76543210

TDRE RDRF ORER ERS PER TEND MPB MPBT

Initial value : 1 0 0 0 0 1 0 0

R/W : R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R R R/W

Note: *Only 0 can be written, to clear these flags.

Bit 4 of SSR has a different function in Smart Card interface mode. Coupled with this, the setting

conditions for bit 2, TEND, are also different.

Bits 7 to 5—Operate in the same way as for the normal SCI. For details, see section 13.2.7, Serial

Status Register (SSR).

Bit 4—Error Signal Status (ERS): In Smart Card interface mode, bit 4 indicates the status of the

error signal sent back from the receiving end in transmission. Framing errors are not detected in

Smart Card interface mode.

Bit 4

ERS Description

0 Normal reception, with no error signal

[Clearing conditions] (Initial value)

• Upon reset, and in standby mode or module stop mode

• When 0 is written to ERS after reading ERS = 1

1 Error signal sent from receiver indicating detection of parity error

[Setting condition]

When the low level of the error signal is sampled

Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous

state.

506

Bits 3 to 0—Operate in the same way as for the normal SCI. For details, see section 13.2.7, Serial

Status Register (SSR).

However, the setting conditions for the TEND bit, are as shown below.

Bit 2

TEND Description

0 Transmission is in progress

[Clearing conditions] (Initial value)

• When 0 is written to TDRE after reading TDRE = 1

• When the DTC is activated by a TXI interrupt and write data to TDR

1 Transmission has ended

[Setting conditions]

• Upon reset, and in standby mode or module stop mode

• When the TE bit in SCR is 0 and the ERS bit is also 0

• When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after transmission of a

1-byte serial character when GM = 0 and BLK = 0

• When TDRE = 1 and ERS = 0 (normal transmission) 1.5 etu after transmission of a

1-byte serial character when GM = 0 and BLK = 1

• When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a

1-byte serial character when GM = 1 and BLK = 0

• When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a

1-byte serial character when GM = 1 and BLK = 1

Note: etu: Elementary Time Unit (time for transfer of 1 bit)

507

14.2.3 Serial Mode Register (SMR)

Bit:76543210

GM BLK PE O/EBCP1 BCP0 CKS1 CKS0

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

Note: When the smart card interface is used, be sure to make the 1 setting shown for bit 5.

The function of bits 7, 6, 3, and 2 of SMR changes in Smart Card interface mode.

Bit 7—GSM Mode (GM): Sets the smart card interface function to GSM mode.

This bit is cleared to 0 when the normal smart card interface is used. In GSM mode, this bit is set

to 1, the timing of setting of the TEND flag that indicates transmission completion is advanced

and clock output control mode addition is performed. The contents of the clock output control

mode addition are specified by bits 1 and 0 of the serial control register (SCR).

Bit 7

GM Description

0 Normal smart card interface mode operation (Initial value)

• TEND flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of

start bit

• Clock output ON/OFF control only

1 GSM mode smart card interface mode operation

• TEND flag generation 11.0 etu after beginning of start bit

• High/low fixing control possible in addition to clock output ON/OFF control (set by

SCR)

Note: etu: Elementary time unit (time for transfer of 1 bit)

508

Bit 6—Block Transfer Mode (BLK): Selects block transfer mode.

Bit 6

BLK Description

0 Normal Smart Card interface mode operation

• Error signal transmission/detection and automatic data retransmission performed

• TXI interrupt generated by TEND flag

• TEND flag set 12.5 etu after start of transmission (11.0 etu in GSM mode)

1 Block transfer mode operation

• Error signal transmission/detection and automatic data retransmission not

performed

• TXI interrupt generated by TDRE flag

• TEND flag set 11.5 etu after start of transmission (11.0 etu in GSM mode)

Note: etu : Elementury time unit (time for transfer of 1 bit)

Bits 3 and 2—Basic Clock Pulse 1 and 0 (BCP1, BCP0): These bits specify the number of basic

clock periods in a 1-bit transfer interval on the Smart Card interface.

Bit 3 Bit 2

BCP1 BCP0 Description

0 1 32 clock periods (Initial value)

0 64 clock periods

1 1 372 clock periods

0 256 clock periods

Bits 5, 4, 1, and 0: Operate in the same way as for the normal SCI. For details, see section 13.2.5,

Serial Mode Register (SMR).

509

14.2.4 Serial Control Register (SCR)

Bit:76543210

TIE RIE TE RE MPIE TEIE CKE1 CKE0

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

In smart card interface mode, the function of bits 1 and 0 of SCR changes when bit 7 of the serial

mode register (SMR) is set to 1.

Bits 7 to 2—Operate in the same way as for the normal SCI.

For details, see section 13.2.6, Serial Control Register (SCR).

Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock

source and enable or disable clock output from the SCK pin.

In smart card interface mode, in addition to the normal switching between clock output enabling

and disabling, the clock output can be specified as to be fixed high or low.

SCMR SMR SCR Setting

SMIF C/A, GM CKE1 CKE0 SCK Pin Function

0 See the SCI

1 0 0 0 Operates as port I/O pin

1 0 0 1 Outputs clock as SCK output pin

1 1 0 0 Operates as SCK output pin, with output fixed

low

1 1 0 1 Outputs clock as SCK output pin

1 1 1 0 Operates as SCK output pin, with output fixed

high

1 1 1 1 Outputs clock as SCK output pin

510

14.3 Operation

14.3.1 Overview

The main functions of the Smart Card interface are as follows.

• One frame consists of 8-bit data plus a parity bit.

• In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of 1

bit) is left between the end of the parity bit and the start of the next frame.

• If a parity error is detected during reception, a low error signal level is output for one etu

period, 10.5 etu after the start bit.

• If the error signal is sampled during transmission, the same data is transmitted automatically

after the elapse of 2 etu or longer. (except in block transfer mode)

• Only asynchronous communication is supported; there is no clocked synchronous

communication function.

14.3.2 Pin Connections

Figure 14-2 shows a schematic diagram of Smart Card interface related pin connections.

In communication with an IC card, since both transmission and reception are carried out on a

single data transmission line, the TxD pin and RxD pin should be connected with the LSI pin. The

data transmission line should be pulled up to the VCC power supply with a resistor.

When the clock generated on the Smart Card interface is used by an IC card, the SCK pin output is

input to the CLK pin of the IC card. No connection is needed if the IC card uses an internal clock.

LSI port output is used as the reset signal.

Other pins must normally be connected to the power supply or ground.

511

TxD

RxD

SCK

Rx (port)

H8S/2646 Series

I/O

CLK

RST

VCC

Connected equipment

IC card

Data line

Clock line

Reset line

Figure 14-2 Schematic Diagram of Smart Card Interface Pin Connections

Note: If an IC card is not connected, and the TE and RE bits are both set to 1, closed

transmission/reception is possible, enabling self-diagnosis to be carried out.

512

14.3.3 Data Format

Normal Transfer Mode: Figure 14-3 shows the normal Smart Card interface data format. In

reception in this mode, a parity check is carried out on each frame, and if an error is detected an

error signal is sent back to the transmitting end, and retransmission of the data is requested. If an

error signal is sampled during transmission, the same data is retransmitted.

Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp

When there is no parity error

Transmitting station output

Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp

When a parity error occurs

Transmitting station output

Receiving station

output

: Start bit

: Data bits

: Parity bit

: Error signal

Legend

D0 to D7

Figure 14-3 Normal Smart Card Interface Data Format

The operation sequence is as follows.

[1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pull-

up resistor.

[2] The transmitting station starts transfer of one frame of data. The data frame starts with a start

bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp).

[3] With the Smart Card interface, the data line then returns to the high-impedance state. The data

line is pulled high with a pull-up resistor.

[4] The receiving station carries out a parity check.

If there is no parity error and the data is received normally, the receiving station waits for

reception of the next data.

513

If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level)

to request retransmission of the data. After outputting the error signal for the prescribed length

of time, the receiving station places the signal line in the high-impedance state again. The

signal line is pulled high again by a pull-up resistor.

[5] If the transmitting station does not receive an error signal, it proceeds to transmit the next data

frame.

If it does receive an error signal, however, it returns to step [2] and retransmits the erroneous

data.

Block Transfer Mode: The operation sequence in block transfer mode is as follows.

[1] When the data line in not in use it is in the high-impedance state, and is fixed high with a pull-

up resistor.

[2] The transmitting station starts transfer of one frame of data. The data frame starts with a start

bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp).

[3] With the Smart Card interface, the data line then returns to the high-impedance state. The data

line is pulled high with a pull-up resistor.

[4] After reception, a parity error check is carried out, but an error signal is not output even if an

error has occurred. When an error occurs reception cannot be continued, so the error flag

should be cleared to 0 before the parity bit of the next frame is received.

[5] The transmitting station proceeds to transmit the next data frame.

514

14.3.4 Register Settings

Table 14-3 shows a bit map of the registers used by the smart card interface.

Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described

below.

Table 14-3 Smart Card Interface Register Settings

Bit

SMR GM BLK 1 O/EBCP1 BCP0 CKS1 CKS0

BRR BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0

SCR TIE RIE TE RE 0 0 CKE1*CKE0

TDR TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0

SSR TDRE RDRF ORER ERS PER TEND 0 0

RDR RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0

SCMR ————SDIR SINV —SMIF

Legend

—: Unused bit.

Note: * The CKE1 bit must be cleared to 0 when the GM bit in SMR is cleared to 0.

SMR Setting: The GM bit is cleared to 0 in normal smart card interface mode, and set to 1 in

GSM mode. The O/E bit is cleared to 0 if the IC card is of the direct convention type, and set to 1

if of the inverse convention type.

Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. Bits BCP1 and

BCP0 select the number of basic clock periods in a 1-bit transfer interval. For details, see section

14.3.5, Clock.

The BLK bit is cleared to 0 in normal smart card interface mode, and set to 1 in block transfer

mode.

BRR Setting: BRR is used to set the bit rate. See section 14.3.5, Clock, for the method of

calculating the value to be set.

SCR Setting: The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI.

For details, see section 13, Serial Communication Interface (SCI).

Bits CKE1 and CKE0 specify the clock output. When the GM bit in SMR is cleared to 0, set these

bits to B'00 if a clock is not to be output, or to B'01 if a clock is to be output. When the GM bit in

SMR is set to 1, clock output is performed. The clock output can also be fixed high or low.

515

Smart Card Mode Register (SCMR) Setting: The SDIR bit is cleared to 0 if the IC card is of the

direct convention type, and set to 1 if of the inverse convention type.

The SINV bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the

inverse convention type.

The SMIF bit is set to 1 in the case of the Smart Card interface.

Examples of register settings and the waveform of the start character are shown below for the two

types of IC card (direct convention and inverse convention).

• Direct convention (SDIR = SINV = O/E = 0)

Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp

AZZAZZZAAZ(Z) (Z) State

With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to

state A, and transfer is performed in LSB-first order. The start character data above is H'3B.

The parity bit is 1 since even parity is stipulated for the Smart Card.

• Inverse convention (SDIR = SINV = O/E = 1)

Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp

AZZAAAAAAZ(Z) (Z) State

With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level

to state Z, and transfer is performed in MSB-first order. The start character data above is H'3F.

The parity bit is 0, corresponding to state Z, since even parity is stipulated for the Smart Card.

With the H8S/2646 Series, inversion specified by the SINV bit applies only to the data bits, D7

to D0. For parity bit inversion, the O/E bit in SMR is set to odd parity mode (the same applies

to both transmission and reception).

516

14.3.5 Clock

Only an internal clock generated by the on-chip baud rate generator can be used as the

transmit/receive clock for the smart card interface. The bit rate is set with BRR and the CKS1,

CKS0, BCP1 and BCP0 bits in SMR. The formula for calculating the bit rate is as shown below.

Table 14-5 shows some sample bit rates.

If clock output is selected by setting CKE0 to 1, a clock is output from the SCK pin. The clock

frequency is determined by the bit rate and the setting of bits BCP1 and BCP0.

B = ø

S × 22n+1 × (N + 1) × 106

Where: N = Value set in BRR (0 ≤ N ≤ 255)

B = Bit rate (bit/s)

ø = Operating frequency (MHz)

n = See table 14-4

S = Number of internal clocks in 1-bit period, set by BCP1 and BCP0

Table 14-4 Correspondence between n and CKS1, CKS0

n CKS1 CKS0

000

210

Table 14-5 Examples of Bit Rate B (bit/s) for Various BRR Settings

(When n = 0 and S = 372)

ø (MHz)

N 10.00 10.714 13.00 14.285 16.00 18.00 20.00

0 13441 14400 17473 19200 21505 24194 26882

1 6720 7200 8737 9600 10753 12097 13441

2 4480 4800 5824 6400 7168 8065 8961

Note: Bit rates are rounded to the nearest whole number.

517

The method of calculating the value to be set in the bit rate register (BRR) from the operating

frequency and bit rate, on the other hand, is shown below. N is an integer, 0 ≤ N ≤ 255, and the

smaller error is specified.

N = ø

S × 22n+1 × B × 106 – 1

Table 14-6 Examples of BRR Settings for Bit Rate B (bit/s) (When n = 0 and S = 372)

ø (MHz)

7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 20.00

bit/s N Error N Error N Error N Error N Error N Error N Error N Error

9600 0 0.00 1 30 1 25 1 8.99 1 0.00 1 12.01 2 15.99 2 6.60

Table 14-7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)

(when S = 372)

ø (MHz) Maximum Bit Rate (bit/s) N n

7.1424 9600 0 0

10.00 13441 0 0

10.7136 14400 0 0

13.00 17473 0 0

14.2848 19200 0 0

16.00 21505 0 0

18.00 24194 0 0

20.00 26882 0 0

The bit rate error is given by the following formula:

Error (%) = ( ø

S × 22n+1 × B × (N + 1) × 106 – 1) × 100

518

14.3.6 Data Transfer Operations

Initialization: Before transmitting and receiving data, initialize the SCI as described below.

Initialization is also necessary when switching from transmit mode to receive mode, or vice versa.

[1] Clear the TE and RE bits in SCR to 0.

[2] Clear the error flags ERS, PER, and ORER in SSR to 0.

[3] Set the GM, BLK, O/E, BCP1, BCP0, CKS1, CKS0 bits in SMR. Set the PE bit to 1.

[4] Set the SMIF, SDIR, and SINV bits in SCMR.

When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins,

and are placed in the high-impedance state.

[5] Set the value corresponding to the bit rate in BRR.

[6] Set the CKE0 and CKE1 bits in SCR. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0.

If the CKE0 bit is set to 1, the clock is output from the SCK pin.

[7] Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE

bit and RE bit at the same time, except for self-diagnosis.

519

Serial Data Transmission: As data transmission in smart card mode involves error signal

sampling and retransmission processing, the processing procedure is different from that for the

normal SCI. Figure 14-4 shows a flowchart for transmitting, and figure 14-5 shows the relation

between a transmit operation and the internal registers.

[1] Perform Smart Card interface mode initialization as described above in Initialization.

[2] Check that the ERS error flag in SSR is cleared to 0.

[3] Repeat steps [2] and [3] until it can be confirmed that the TEND flag in SSR is set to 1.

[4] Write the transmit data to TDR, clear the TDRE flag to 0, and perform the transmit operation.

The TEND flag is cleared to 0.

[5] When transmitting data continuously, go back to step [2].

[6] To end transmission, clear the TE bit to 0.

With the above processing, interrupt servicing or data transfer by the DTC is possible.

If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt

requests are enabled, a transmit data empty interrupt (TXI) request will be generated. If an error

occurs in transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt

requests are enabled, a transfer error interrupt (ERI) request will be generated.

The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND

flag set timing is shown in figure 14-6.

If the DTC is activated by a TXI request, the number of bytes set in the DTC can be transmitted

automatically, including automatic retransmission.

For details, see Interrupt Operation and Data Transfer Operation by DTC below.

Note: For block transfer mode, see section 13.3.2, Operation in Asynchronous Mode.

520

Initialization

Yes

Clear TE bit to 0

Start transmission

Start

Yes

End

Write data to TDR,

and clear TDRE flag

in SSR to 0

Error processing

TEND=1?

All data transmitted?

TEND=1?

ERS=0?

Figure 14-4 Example of Transmission Processing Flow

521

(1) Data write

TDR TSR

(shift register)

Data 1

(2) Transfer from

TDR to TSR Data 1 Data 1 ; Data remains in TDR

(3) Serial data output

Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first

transmission, D0 in MSB-first transmission) of the next transfer data to be transmitted has

been completed.

In case of normal transmission: TEND flag is set

In case of transmit error: ERS flag is set

Steps (2) and (3) above are repeated until the TEND flag is set

I/O signal line output

Data 1 Data 1

Figure 14-5 Relation Between Transmit Operation and Internal Registers

Ds D0 D1 D2 D3 D4 D5 D6 D7 DpI/O data

12.5 etu

TXI

(TEND interrupt)

11.0 etu

Guard

time

When GM = 1

Legend

Ds : Start bit

D0 to D7 : Data bits

Dp : Parity bit

DE : Error signal

Note : etu : Elementary time unit (time for fransfer of 1 bit)

When GM = 0

Figure 14-6 TEND Flag Generation Timing in Transmission Operation

522

Serial Data Reception (Except Block Transfer Mode): Data reception in Smart Card mode uses

the same processing procedure as for the normal SCI. Figure 14-7 shows an example of the

transmission processing flow.

[1] Perform Smart Card interface mode initialization as described above in Initialization.

[2] Check that the ORER flag and PER flag in SSR are cleared to 0. If either is set, perform the

appropriate receive error processing, then clear both the ORER and the PER flag to 0.

[3] Repeat steps [2] and [3] until it can be confirmed that the RDRF flag is set to 1.

[4] Read the receive data from RDR.

[5] When receiving data continuously, clear the RDRF flag to 0 and go back to step [2].

[6] To end reception, clear the RE bit to 0.

Initialization

Read RDR and clear

RDRF flag in SSR to 0

Clear RE bit to 0

Start reception

Start

Error processing

Yes

ORER = 0 and

PER = 0

RDRF=1?

All data received?

Yes

Figure 14-7 Example of Reception Processing Flow

523

With the above processing, interrupt servicing or data transfer by the DTC is possible.

If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests

are enabled, a receive data full interrupt (RXI) request will be generated. If an error occurs in

reception and either the ORER flag or the PER flag is set to 1, a transfer error interrupt (ERI)

request will be generated.

If the DTC is activated by an RXI request, the receive data in which the error occurred is skipped,

and only the number of bytes of receive data set in the DTC are transferred.

For details, see Interrupt Operation and Data Transfer Operation by DTC followings.

If a parity error occurs during reception and the PER is set to 1, the received data is still

transferred to RDR, and therefore this data can be read.

Note: For block transfer mode, see section 13.3.2, Operation in Asynchronous Mode.

Mode Switching Operation: When switching from receive mode to transmit mode, first confirm

that the receive operation has been completed, then start from initialization, clearing RE bit to 0

and setting TE bit to 1. The RDRF flag or the PER and ORER flags can be used to check that the

receive operation has been completed.

When switching from transmit mode to receive mode, first confirm that the transmit operation has

been completed, then start from initialization, clearing TE bit to 0 and setting RE bit to 1. The

TEND flag can be used to check that the transmit operation has been completed.

Fixing Clock Output Level: When the GM bit in SMR is set to 1, the clock output level can be

fixed with bits CKE1 and CKE0 in SCR. At this time, the minimum clock pulse width can be

made the specified width.

Figure 14-8 shows the timing for fixing the clock output level. In this example, GM is set to 1,

CKE1 is cleared to 0, and the CKE0 bit is controlled.

SCK

Specified pulse width

SCR write

(CKE0 = 0) SCR write

(CKE0 = 1)

Specified pulse width

Figure 14-8 Timing for Fixing Clock Output Level

Interrupt Operation (Except Block Transfer Mode): There are three interrupt sources in smart

card interface mode: transmit data empty interrupt (TXI) requests, transfer error interrupt (ERI)

524

requests, and receive data full interrupt (RXI) requests. The transmit end interrupt (TEI) request is

not used in this mode.

When the TEND flag in SSR is set to 1, a TXI interrupt request is generated.

When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated.

When any of flags ORER, PER, and ERS in SSR is set to 1, an ERI interrupt request is generated.

The relationship between the operating states and interrupt sources is shown in table 14-8.

Note: For block transfer mode, see section 13.4, SCI Interrupts.

Table 14-8 Smart Card Mode Operating States and Interrupt Sources

Operating State Flag Enable Bit Interrupt

Source DTC Activation

Transmit Mode Normal

operation TEND TIE TXI Possible

Error ERS RIE ERI Not possible

Receive Mode Normal

operation RDRF RIE RXI Possible

Error PER, ORER RIE ERI Not possible

Data Transfer Operation by DTC: In smart card mode, as with the normal SCI, transfer can be

carried out using the DTC. In a transmit operation, the TDRE flag is also set to 1 at the same time

as the TEND flag in SSR, and a TXI interrupt is generated. If the TXI request is designated

beforehand as a DTC activation source, the DTC will be activated by the TXI request, and transfer

of the transmit data will be carried out. The TDRE and TEND flags are automatically cleared to 0

when data transfer is performed by the DTC. In the event of an error, the SCI retransmits the same

data automatically. During this period, TEND remains cleared to 0 and the DTC is not activated.

Therefore, the SCI and DTC will automatically transmit the specified number of bytes, including

retransmission in the event of an error. However, the ERS flag is not cleared automatically when

an error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be

generated in the event of an error, and the ERS flag will be cleared.

When performing transfer using the DTC, it is essential to set and enable the DTC before carrying

out SCI setting. For details of the DTC setting procedures, see section 8, Data Transfer Controller

(DTC).

In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to

1. If the RXI request is designated beforehand as a DTC activation source, the DTC will be

activated by the RXI request, and transfer of the receive data will be carried out. The RDRF flag is

cleared to 0 automatically when data transfer is performed by the DTC. If an error occurs, an error

525

flag is set but the RDRF flag is not. Consequently, the DTC is not activated, but instead, an ERI

interrupt request is sent to the CPU. Therefore, the error flag should be cleared.

Note: For block transfer mode, see section 13.4, SCI Interrupts.

14.3.7 Operation in GSM Mode

Switching the Mode: When switching between smart card interface mode and software standby

mode, the following switching procedure should be followed in order to maintain the clock duty.

• When changing from smart card interface mode to software standby mode

[1] Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to

the value for the fixed output state in software standby mode.

[2] Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive

operation. At the same time, set the CKE1 bit to the value for the fixed output state in software

standby mode.

[3] Write 0 to the CKE0 bit in SCR to halt the clock.

[4] Wait for one serial clock period.

During this interval, clock output is fixed at the specified level, with the duty preserved.

[5] Make the transition to the software standby state.

• When returning to smart card interface mode from software standby mode

[6] Exit the software standby state.

[7] Write 1 to the CKE0 bit in SCR and output the clock. Signal generation is started with the

normal duty.

[1] [2] [3] [4] [5] [6] [7]

Software

standby

Normal operation Normal operation

Figure 14-9 Clock Halt and Restart Procedure

526

Powering On: To secure the clock duty from power-on, the following switching procedure should

be followed.

[1] The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor

to fix the potential.

[2] Fix the SCK pin to the specified output level with the CKE1 bit in SCR.

[3] Set SMR and SCMR, and switch to smart card mode operation.

[4] Set the CKE0 bit in SCR to 1 to start clock output.

14.3.8 Operation in Block Transfer Mode

Operation in block transfer mode is the same as in SCI asynchronous mode, except for the

following points. For details, see section 13.3.2, Operation in Asynchronous Mode.

Data Format: The data format is 8 bits with parity. There is no stop bit, but there is a 2-bit (1-bit

or more in reception) error guard time.

Also, except during transmission (with start bit, data bits, and parity bit), the transmission pins go

to the high-impedance state, so the signal lines must be fixed high with a pull-up resistor.

Transmit/Receive Clock: Only an internal clock generated by the on-chip baud rate generator can

be used as the transmit/receive clock. The number of basic clock periods in a 1-bit transfer

interval can be set to 32, 64, 372, or 256 with bits BCP1 and BCP0. For details, see section

14.3.5, Clock.

ERS (FER) Flag: As with the normal Smart Card interface, the ERS flag indicates the error signal

status, but since error signal transmission and reception is not performed, this flag is always

cleared to 0.

527

14.4 Usage Notes

The following points should be noted when using the SCI as a Smart Card interface.

Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode: In

Smart Card interface mode, the SCI operates on a basic clock with a frequency of 32, 64, 372, or

256 times the transfer rate (as determined by bits BCP1 and BCP0).

In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs

internal synchronization. Receive data is latched internally at the rising edge of the 16th, 32nd,

186th, or 128th pulse of the basic clock. Figure 14-10 shows the receive data sampling timing

when using a clock of 372 times the transfer rate.

Internal

basic

clock

372 clocks

186 clocks

Receive

data (RxD)

Synchro-

nization

sampling

timing

D0 D1

Data

sampling

timing

185 371 0

371

185 0

Start bit

Figure 14-10 Receive Data Sampling Timing in Smart Card Mode

(Using Clock of 372 Times the Transfer Rate)

528

Thus the reception margin in asynchronous mode is given by the following formula.

Formula for reception margin in smart card interface mode

M = (0.5 – 1

2N ) – (L – 0.5) F –  D – 0.5

N (1 + F) × 100%

Where M: Reception margin (%)

N: Ratio of bit rate to clock (N = 32, 64, 372, and 256)

D: Clock duty (D = 0 to 1.0)

L: Frame length (L = 10)

F: Absolute value of clock frequency deviation

Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin

formula is as follows.

When D = 0.5 and F = 0,

M = (0.5 – 1/2 × 372) × 100%

= 49.866%

Retransfer Operations (Except Block Transfer Mode): Retransfer operations are performed by

the SCI in receive mode and transmit mode as described below.

• Retransfer operation when SCI is in receive mode

Figure 14-11 illustrates the retransfer operation when the SCI is in receive mode.

[1] If an error is found when the received parity bit is checked, the PER bit in SSR is automatically

set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The

PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled.

[2] The RDRF bit in SSR is not set for a frame in which an error has occurred.

[3] If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1.

[4] If no error is found when the received parity bit is checked, the receive operation is judged to

have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE

bit in SCR is enabled at this time, an RXI interrupt request is generated.

If DTC data transfer by an RXI source is enabled, the contents of RDR can be read

automatically. When the RDR data is read by the DTC, the RDRF flag is automatically cleared

to 0.

[5] When a normal frame is received, the pin retains the high-impedance state at the timing for

error signal transmission.

529

D0D1D2D3D4D5D6D7Dp DE DsD0D1D2D3D4D5D6D7Dp(DE)DsD0D1D2D3D4Ds

Transfer

frame n+1

Retransferred framenth transfer frame

RDRF

[1]

PER

[2]

[3]

[4]

Figure 14-11 Retransfer Operation in SCI Receive Mode

• Retransfer operation when SCI is in transmit mode

Figure 14-12 illustrates the retransfer operation when the SCI is in transmit mode.

[6] If an error signal is sent back from the receiving end after transmission of one frame is

completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI

interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next

parity bit is sampled.

[7] The TEND bit in SSR is not set for a frame for which an error signal indicating an abnormality

is received.

[8] If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set.

[9] If an error signal is not sent back from the receiving end, transmission of one frame, including

a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1. If the TIE

bit in SCR is enabled at this time, a TXI interrupt request is generated.

If data transfer by the DTC by means of the TXI source is enabled, the next data can be written

to TDR automatically. When data is written to TDR by the DTC, the TDRE bit is

automatically cleared to 0.

D0D1D2D3D4D5D6D7Dp DE DsD0D1D2D3D4D5D6D7Dp (DE) DsD0D1D2D3D4Ds

Transfer

frame n+1

Retransferred framenth transfer frame

TDRE

TEND

[6]

FER/ERS

Transfer to TSR from TDR

[7] [9]

[8]

Transfer to TSR from TDR Transfer to TSR

from TDR

Figure 14-12 Retransfer Operation in SCI Transmit Mode

530

531

Section 15 Hitachi Controller Area Network (HCAN)

15.1 Overview

The HCAN is a module for controlling a controller area network (CAN) for realtime

communication in vehicular and industrial equipment systems, etc. The H8S/2646 Series has a

single-channel on-chip HCAN module.

Reference: BOSCH CAN Specification Version 2.0 1991, Robert Bosch GmbH

15.1.1 Features

• CAN version: Bosch 2.0B active compatible

 Communication systems:

NRZ (Non-Return to Zero) system (with bit-stuffing function)

Broadcast communication system

 Transmission path: Bidirectional 2-wire serial communication

 Communication speed: Max. 1 Mbps

 Data length: 0 to 8 bytes

• Number of channels: 1

• Data buffers: 16 (one receive-only buffer and 15 buffers settable for transmission/reception)

• Data transmission: Choice of two methods:

 Mailbox (buffer) number order (low-to-high)

 Message priority (identifier) high-to-low order

• Data reception: Two methods:

 Message identifier match (transmit/receive-setting buffers)

 Reception with message identifier masked (receive-only)

• CPU interrupts: Two interrupt vectors:

 Error interrupt

 Reset processing interrupt

 Message reception interrupt (mailbox 1 to 15)

 Message reception interrupt (mailbox 0)

 Message transmission interrupt

• HCAN operating modes: Support for various modes:

 Hardware reset

 Software reset

 Normal status (error-active, error-passive)

 Bus off status

532

 HCAN configuration mode

 HCAN sleep mode

 HCAN halt mode

• Other features: DTC can be activated by message reception mailbox (HCAN mailbox 0 only)

15.1.2 Block Diagram

Figure 15-1 shows a block diagram of the HCAN.

Peripheral address bus

Peripheral data bus

HTxD

MBI

Message buffer

HRxD

MPI

Microprocessor interface

(CDLC)

CAN

Data Link Controller

Bosch CAN 2.0B active

CPU interface

Control register

Status register

HCAN

Tx buffer

Rx buffer

Message control

Message data

MC0–MC15, MD0–MD15

LAFM

Mailboxes

Figure 15-1 HCAN Block Diagram

Message Buffer Interface (MBI): The MBI, consisting of mailboxes and a local acceptance filter

mask (LAFM), stores CAN transmit/receive messages (identifiers, data, etc.) Transmit messages

are written by the CPU. For receive messages, the data received by the CDLC is stored

automatically.

Microprocessor Interface (MPI): The MPI, consisting of a bus interface, control register, status

CAN Data Link Controller (CDLC): The CDLC performs transmission and reception of

messages conforming to the Bosch CAN Ver. 2.0B active standard (data frames, remote frames,

error frames, overload frames, inter-frame spacing), as well as CRC checking, bus arbitration, and

other functions.

533

15.1.3 Pin Configuration

Table 15-1 shows the HCAN’s pins.

When using HCAN pins, settings must be made in the HCAN configuration mode (during

initialization: MCR0 = 1 and GSR3 = 1).

Table 15-1 HCAN Pins

Name Abbreviation Input/Output Function

HCAN transmit data pin HTxD Output CAN bus transmission pin

HCAN receive data pin HRxD Input CAN bus reception pin

A bus driver is necessary between the pins and the CAN bus. A Philips PCA82C250 compatible

model is recommended.

15.1.4 Register Configuration

Table 15-2 lists the HCAN’s registers.

Table 15-2 HCAN Registers

Name Abbreviation R/W Initial Value Address*Access Size

Master control register MCR R/W H'01 H'F800 8 bits 16 bits

General status register GSR R/W H'0C H'F801 8 bits

Bit configuration register BCR R/W H'0000 H'F802 8/16 bits

Mailbox configuration register MBCR R/W H'0100 H'F804 8/16 bits

Transmit wait register TXPR R/W H'0000 H'F806 8/16 bits

Transmit wait cancel register TXCR R/W H'0000 H'F808 8/16 bits

Transmit acknowledge register TXACK R/W H'0000 H'F80A 8/16 bits

Abort acknowledge register ABACK R/W H'0000 H'F80C 8/16 bits

Receive complete register RXPR R/W H'0000 H'F80E 8/16 bits

Remote request register RFPR R/W H'0000 H'F810 8/16 bits

Interrupt register IRR R/W H'0100 H'F812 8/16 bits

Mailbox interrupt mask register MBIMR R/W H'FFFF H'F814 8/16 bits

Interrupt mask register IMR R/W H'FEFF H'F816 8/16 bits

Receive error counter REC R H'00 H'F818 8 bits 16 bits

Transmit error counter TEC R H'00 H'F819 8 bits

Unread message status register UMSR R/W H'0000 H'F81A 8/16 bits

534

Name Abbreviation R/W Initial Value Address*Access Size

Local acceptance filter mask L LAFML R/W H'0000 H'F81C 8/16 bits

Local acceptance filter mask H LAFMH R/W H'0000 H'F81E 8/16 bits

Message control 0 [1:8] MC0 [1:8] R/W Undefined H'F820 8/16 bits

Message control 1 [1:8] MC1 [1:8] R/W Undefined H'F828 8/16 bits

Message control 2 [1:8] MC2 [1:8] R/W Undefined H'F830 8/16 bits

Message control 3 [1:8] MC3 [1:8] R/W Undefined H'F838 8/16 bits

Message control 4 [1:8] MC4 [1:8] R/W Undefined H'F840 8/16 bits

Message control 5 [1:8] MC5 [1:8] R/W Undefined H'F848 8/16 bits

Message control 6 [1:8] MC6 [1:8] R/W Undefined H'F850 8/16 bits

Message control 7 [1:8] MC7 [1:8] R/W Undefined H'F858 8/16 bits

Message control 8 [1:8] MC8 [1:8] R/W Undefined H'F860 8/16 bits

Message control 9 [1:8] MC9 [1:8] R/W Undefined H'F868 8/16 bits

Message control 10 [1:8] MC10 [1:8] R/W Undefined H'F870 8/16 bits

Message control 11 [1:8] MC11 [1:8] R/W Undefined H'F878 8/16 bits

Message control 12 [1:8] MC12 [1:8] R/W Undefined H'F880 8/16 bits

Message control 13 [1:8] MC13 [1:8] R/W Undefined H'F888 8/16 bits

Message control 14 [1:8] MC14 [1:8] R/W Undefined H'F890 8/16 bits

Message control 15 [1:8] MC15 [1:8] R/W Undefined H'F898 8/16 bits

Message data 0 [1:8] MD0 [1:8] R/W Undefined H'F8B0 8/16 bits

Message data 1 [1:8] MD1 [1:8] R/W Undefined H'F8B8 8/16 bits

Message data 2 [1:8] MD2 [1:8] R/W Undefined H'F8C0 8/16 bits

Message data 3 [1:8] MD3 [1:8] R/W Undefined H'F8C8 8/16 bits

Message data 4 [1:8] MD4 [1:8] R/W Undefined H'F8D0 8/16 bits

Message data 5 [1:8] MD5 [1:8] R/W Undefined H'F8D8 8/16 bits

Message data 6 [1:8] MD6 [1:8] R/W Undefined H'F8E0 8/16 bits

Message data 7 [1:8] MD7 [1:8] R/W Undefined H'F8E8 8/16 bits

Message data 8 [1:8] MD8 [1:8] R/W Undefined H'F8F0 8/16 bits

Message data 9 [1:8] MD9 [1:8] R/W Undefined H'F8F8 8/16 bits

Message data 10 [1:8] MD10 [1:8] R/W Undefined H'F900 8/16 bits

Message data 11 [1:8] MD11 [1:8] R/W Undefined H'F908 8/16 bits

Message data 12 [1:8] MD12 [1:8] R/W Undefined H'F910 8/16 bits

Message data 13 [1:8] MD13 [1:8] R/W Undefined H'F918 8/16 bits

Message data 14 [1:8] MD14 [1:8] R/W Undefined H'F920 8/16 bits

Message data 15 [1:8] MD15 [1:8] R/W Undefined H'F928 8/16 bits

Module stop control

Note: *Lower 16 bits of the address.

535

15.2 Register Descriptions

15.2.1 Master Control Register (MCR)

The master control register (MCR) is an 8-bit readable/writable register that controls the CAN

interface.

MCR

Bit: 7 6 5 4 3 2 1 0

MCR7 — MCR5 — — MCR2 MCR1 MCR0

Initial value: 0 0 0 0 0 0 0 1

R/W: R/W R R/W R R R/W R/W R/W

Bit 7—HCAN Sleep Mode Release (MCR7): Enables or disables HCAN sleep mode release by

bus operation.

Bit 7: MCR7 Description

0 HCAN sleep mode release by CAN bus operation disabled (Initial value)

1 HCAN sleep mode release by CAN bus operation enabled

Bit 6—Reserved: This bit always reads 0. The write value should always be 0.

Bit 5—HCAN Sleep Mode (MCR5): Enables or disables HCAN sleep mode transition.

Bit 5: MCR5 Description

0 HCAN sleep mode released (Initial value)

1 Transition to HCAN sleep mode enabled

Bits 4 and 3—Reserved: These bits always read 0. The write value should always be 0.

Bit 2—Message Transmission Method (MCR2): Selects the transmission method for transmit

messages.

Bit 2: MCR2 Description

0 Transmission order determined by message identifier priority (Initial value)

1 Transmission order determined by mailbox (buffer) number priority

(TXPR1 > TXPR15)

536

Bit 1—Halt Request (MCR1): Controls halting of the HCAN module.

Bit 1: MCR1 Description

0 HCAN normal operating mode (Initial value)

1 HCAN halt mode transition request

Bit 0—Reset Request (MCR0): Controls resetting of the HCAN module.

Bit 0: MCR0 Description

0 Normal operating mode (MCR0 = 0 and GSR3 = 0)

[Setting condition]

When 0 is written after an HCAN reset

1 HCAN reset mode transition request (Initial value)

In order for GSR3 to change from 1 to 0 after 0 is written to MCR0, time is required before the

HCAN is internally reset. There is consequently a delay before GSR3 is cleared to 0 after MCR0

is cleared to 0.

15.2.2 General Status Register (GSR)

The general status register (GSR) is an 8-bit readable register that indicates the status of the CAN

bus.

GSR

Bit: 7 6 5 4 3 2 1 0

— — — — GSR3 GSR2 GSR1 GSR0

Initial value: 0 0 0 0 1 1 0 0

R/W: R R R R R R R R

Bits 7 to 4—Reserved: These bits always read 0.

537

Bit 3—Reset Status Bit (GSR3): Indicates whether the HCAN module is in the normal operating

state or the reset state. This bit cannot be written to.

Bit 3: GSR3 Description

0 Normal operating state

[Setting condition]

After an HCAN internal reset

1 Configuration mode

[Reset condition]

MCR0 reset mode and sleep mode (Initial value)

Bit 2—Message Transmission Status Flag (GSR2): Flag that indicates whether the module is

currently in the message transmission period. The “message transmission period” is the period

from the start of message transmission (SOF) until the end of a 3-bit intermission interval after

EOF (End of Frame). This bit cannot be written to.

Bit 2: GSR2 Description

0 Message transmission period

1 [Reset Condition]

Idle period (Initial value)

Bit 1—Transmit/Receive Warning Flag (GSR1): Flag that indicates an error warning. This bit

cannot be written to.

Bit 1: GSR1 Description

0 [Reset condition]

When TEC < 96 and REC < 96 or TEC ≥ 256 (Initial value)

1 When TEC ≥ 96 or REC ≥ 96

Bit 0—Bus Off Flag (GSR0): Flag that indicates the bus off state. This bit cannot be written to.

Bit 0: GSR0 Description

0 [Reset condition]

Recovery from bus off state (Initial value)

1 When TEC ≥ 256 (bus off state)

538

15.2.3 Bit Configuration Register (BCR)

The bit configuration register (BCR) is a 16-bit readable/writable register that is used to set CAN

bit timing parameters and the baud rate prescaler.

BCR

Bit: 15 14 13 12 11 10 9 8

BCR7 BCR6 BCR5 BCR4 BCR3 BCR2 BCR1 BCR0

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bit: 7 6 5 4 3 2 1 0

BCR15 BCR14 BCR13 BCR12 BCR11 BCR10 BCR9 BCR8

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bits 15 and 14—Resynchronization Jump Width (SJW): These bits set the bit synchronization

range.

Bit 15:

BCR7 Bit 14:

BCR6 Description

0 0 Bit synchronization width = 1 time quantum (Initial value)

1 Bit synchronization width = 2 time quanta

1 0 Bit synchronization width = 3 time quanta

1 Bit synchronization width = 4 time quanta

Bits 13 to 8—Baud Rate Prescaler (BRP): These bits are used to set the CAN bus baud rate.

Bit 13:

BCR5 Bit 12:

BCR4 Bit 11:

BCR3 Bit 10:

BCR2 Bit 9:

BCR1 Bit 8:

BCR0 Description

0000002 × system clock (Initial value)

0000014 × system clock

0000106 × system clock

⋅

111111128 × system clock

539

Bit 7—Bit Sample Point (BSP): Sets the point at which data is sampled.

Bit 7: BCR15 Description

0 Bit sampling at one point (end of time segment 1 (TSEG1)) (Initial value)

1 Bit sampling at three points (end of TSEG1 and preceding and following

time quantum)

Bits 6 to 4—Time Segment 2 (TSEG2): These bits are used to set the segment for correcting 1-

bit time error. A value from 2 to 8 can be set.

Bit 6:

BCR14 Bit 5:

BCR13 Bit 4:

BCR12 Description

0 0 0 Setting prohibited (Initial value)

1 TSEG2 = 2 time quanta

1 0 TSEG2 = 3 time quanta

1 TSEG2 = 4 time quanta

1 0 0 TSEG2 = 5 time quanta

1 TSEG2 = 6 time quanta

1 0 TSEG2 = 7 time quanta

1 TSEG2 = 8 time quanta

Bits 3 to 0—Time Segment 1 (TSEG1): These bits are used to set the segment for absorbing

output buffer, CAN bus, and input buffer delay. A value of 1 or 4 to 16 can be set.

Bit 3:

BCR11 Bit 2:

BCR10 Bit 1:

BCR9 Bit 0:

BCR8 Description

0000Setting prohibited (Initial value)

0001Setting prohibited

0010Setting prohibited

0011TSEG1 = 4 time quanta

0100TSEG1 = 5 time quanta

⋅

1111TSEG1 = 16 time quanta

540

15.2.4 Mailbox Configuration Register (MBCR)

The mailbox configuration register (MBCR) is a 16-bit readable/writable register that is used to set

mailbox (buffer) transmission/reception.

MBCR

Bit: 15 14 13 12 11 10 9 8

MBCR7 MBCR6 MBCR5 MBCR4 MBCR3 MBCR2 MBCR1 —

Initial value: 0 0 0 0 0 0 0 1

R/W: R/W R/W R/W R/W R/W R/W R/W —

Bit: 7 6 5 4 3 2 1 0

MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 MBCR9 MBCR8

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bits 15 to 9 and 7 to 0—Mailbox Setting Register: These bits set the polarity of the

corresponding mailboxes.

Bit x: MBCRx Description

0 Corresponding mailbox is set for transmission (Initial value)

1 Corresponding mailbox is set for reception

(x = 15 to 0)

Bit 8—Reserved: This bit always reads 1. The write value should always be 1.

541

15.2.5 Transmit Wait Register (TXPR)

The transmit wait register (TXPR) is a 16-bit readable/writable register that is used to set a

transmit wait after a transmit message is stored in a mailbox (buffer) (CAN bus arbitration wait).

TXPR

Bit: 15 14 13 12 11 10 9 8

TXPR7 TXPR6 TXPR5 TXPR4 TXPR3 TXPR2 TXPR1 —

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W —

Bit: 7 6 5 4 3 2 1 0

TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 TXPR9 TXPR8

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bits 15 to 9 and 7 to 0—Transmit Wait Register: These bits set a transmit wait for the

corresponding mailboxes.

Bit x: TXPRx Description

0 Transmit message idle state in corresponding mailbox (Initial value)

[Clearing condition]

Message transmission completion and cancellation completion

1 Transmit message transmit wait in corresponding mailbox (CAN bus

arbitration)

(x = 15 to 0)

Bit 8—Reserved: This bit always reads 0. The write value should always be 0.

542

15.2.6 Transmit Wait Cancel Register (TXCR)

The transmit wait cancel register (TXCR) is a 16-bit readable/writable register that controls

cancellation of transmit wait messages in mailboxes (buffers).

TXCR

Bit: 15 14 13 12 11 10 9 8

TXCR7 TXCR6 TXCR5 TXCR4 TXCR3 TXCR2 TXCR1 —

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W —

Bit: 7 6 5 4 3 2 1 0

TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 TXCR8

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bits 15 to 9 and 7 to 0—Transmit Wait Cancel Register: These bits control cancellation of

transmit wait messages in the corresponding HCAN mailboxes.

Bit x: TXCRx Description

0 Transmit message cancellation idle state in corresponding mailbox

(Initial value)

[Clearing condition]

Completion of TXPR clearing (when transmit message is canceled normally)

1 TXPR cleared for corresponding mailbox (transmit message cancellation)

(x = 15 to 0)

Bit 8—Reserved: This bit always reads 0. The write value should always be 0.

543

15.2.7 Transmit Acknowledge Register (TXACK)

The transmit acknowledge register (TXACK) is a 16-bit readable/writable register containing

status flags that indicate normal transmission of mailbox (buffer) transmit messages.

TXACK

Bit: 15 14 13 12 11 10 9 8

TXACK7 TXACK6 TXACK5 TXACK4 TXACK3 TXACK2 TXACK1 —

Initial value: 0 0 0 0 0 0 0 0

R/W: R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*—

Bit: 7 6 5 4 3 2 1 0

TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 TXACK8

Initial value: 0 0 0 0 0 0 0 0

R/W: R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*

Note: * Only a write of 1 is permitted, to clear the flag.

Bits 15 to 9 and 7 to 0—Transmit Acknowledge Register: These bits indicate that a transmit

message in the corresponding HCAN mailbox has been transmitted normally.

Bit x: TXACKx Description

0 [Clearing condition]

Writing 1 (Initial value)

1 Completion of message transmission for corresponding mailbox

(x = 15 to 0)

Bit 8—Reserved: This bit always reads 0. The write value should always be 0.

544

15.2.8 Abort Acknowledge Register (ABACK)

The abort acknowledge register (ABACK) is a 16-bit readable/writable register containing status

flags that indicate normal cancellation (aborting) of a mailbox (buffer) transmit messages.

ABACK

Bit: 15 14 13 12 11 10 9 8

ABACK7 ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1 —

Initial value: 0 0 0 0 0 0 0 0

R/W: R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*—

Bit: 7 6 5 4 3 2 1 0

ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 ABACK8

Initial value: 0 0 0 0 0 0 0 0

R/W: R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*

Note: * Only a write of 1 is permitted, to clear the flag.

Bits 15 to 9 and 7 to 0—Abort Acknowledge Register: These bits indicate that a transmit

message in the corresponding mailbox has been canceled (aborted) normally.

Bit x: ABACKx Description

0 [Clearing condition]

Writing 1 (Initial value)

1 Completion of transmit message cancellation for corresponding mailbox

(x = 15 to 0)

Bit 8—Reserved: This bit always reads 0. The write value should always be 0.

545

15.2.9 Receive Complete Register (RXPR)

The receive complete register (RXPR) is a 16-bit readable/writable register containing status flags

that indicate normal reception of messages (data frame or remote frame) in mailboxes (buffers).

When receiving a remote frame, the corresponding remote-request register (REPR) is also set at

the same time.

RXPR

Bit: 15 14 13 12 11 10 9 8

RXPR7 RXPR6 RXPR5 RXPR4 RXPR3 RXPR2 RXPR1 RXPR0

Initial value: 0 0 0 0 0 0 0 0

R/W: R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*

Bit: 7 6 5 4 3 2 1 0

RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 RXPR8

Initial value: 0 0 0 0 0 0 0 0

R/W: R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*

Note: * Only a write of 1 is permitted, to clear the flag.

Bits 15 to 0—Receive Complete Register: These bits indicate that a receive message has been

received normally in the corresponding mailbox.

Bit x: RXPRx Description

0 [Clearing condition]

Writing 1 (Initial value)

1 Completion of message (data frame or remote frame) reception in

corresponding mailbox

(x = 15 to 0)

546

15.2.10 Remote Request Register (RFPR)

The remote request register (RFPR) is a 16-bit readable/writable register containing status flags

that indicate normal reception of remote frames in mailboxes (buffers). When this bit is set, the

corresponding receive-completed bit is set the same time.

RFPR

Bit: 15 14 13 12 11 10 9 8

RFPR7 RFPR6 RFPR5 RFPR4 RFPR3 RFPR2 RFPR1 RFPR0

Initial value: 0 0 0 0 0 0 0 0

R/W: R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*

Bit: 7 6 5 4 3 2 1 0

RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 RFPR8

Initial value: 0 0 0 0 0 0 0 0

R/W: R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*

Note: * Only a write of 1 is permitted, to clear the flag.

Bits 15 to 0—Remote Request Register: These bits indicate that a remote frame has been

received normally in the corresponding mailbox.

Bit x: RFPRx Description

0 [Clearing condition]

Writing 1 (Initial value)

1 Completion of remote frame reception in corresponding mailbox

(x = 15 to 0)

547

15.2.11 Interrupt Register (IRR)

The interrupt register (IRR) is a 16-bit readable/writable register containing status flags for the

various interrupt sources.

IRR

Bit: 15 14 13 12 11 10 9 8

IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0

Initial value: 0 0 0 0 0 0 0 1

R/W: R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R R R/(W)*

Bit: 7 6 5 4 3 2 1 0

— — — IRR12 — — IRR9 IRR8

Initial value: 0 0 0 0 0 0 0 0

R/W: — — — R/(W)*— — R R/(W)*

Note: * Only a write of 1 is permitted, to clear the flag.

Bit 15—Overload Frame Interrupt Flag: Status flag indicating that the HCAN has transmitted

an overload frame.

Bit 15: IRR7 Description

0 [Clearing condition]

Writing 1 (Initial value)

1 Overload frame transmission

[Setting conditions]

When overload frame is transmitted

Bit 14—Bus Off Interrupt Flag: Status flag indicating the bus off state caused by the transmit

error counter.

Bit 14: IRR6 Description

0 [Clearing condition]

Writing 1 (Initial value)

1 Bus off state caused by transmit error

[Setting condition]

When TEC ≥ 256

548

Bit 13—Error Passive Interrupt Flag: Status flag indicating the error passive state caused by the

transmit/receive error counter.

Bit 13: IRR5 Description

0 [Clearing condition]

Writing 1 (Initial value)

1 Error passive state caused by transmit/receive error

[Setting condition]

When TEC ≥ 128 or REC ≥ 128

Bit 12—Receive Overload Warning Interrupt Flag: Status flag indicating the error warning

state caused by the receive error counter.

Bit 12: IRR4 Description

0 [Clearing condition]

Writing 1 (Initial value)

1 Error warning state caused by receive error

[Setting condition]

When REC ≥ 96

Bit 11—Transmit Overload Warning Interrupt Flag: Status flag indicating the error warning

state caused by the transmit error counter.

Bit 11: IRR3 Description

0 [Clearing condition]

Writing 1 (Initial value)

1 Error warning state caused by transmit error

[Setting condition]

When TEC ≥ 96

Bit 10—Remote Frame Request Interrupt Flag: Status flag indicating that a remote frame has

been received in a mailbox (buffer).

Bit 10: IRR2 Description

0 [Clearing condition]

Clearing of all bits in RFPR (remote request register) of the mailbox, which

enables the receive interrupt requests in the MBIMR (Initial value)

1 Remote frame received and stored in mailbox

[Setting conditions]

When remote frame reception is completed, when corresponding

MBIMR = 0

549

Bit 9—Receive Message Interrupt Flag: Status flag indicating that a mailbox (buffer) receive

message has been received normally.

Bit 9: IRR1 Description

0 [Clearing condition]

Clearing of all bits in RXPR (receive complete register) of the mailbox, which

enables the receive interrupt requests in the MBIMR (Initial value)

1 Data frame or remote frame received and stored in mailbox

[Setting conditions]

When data frame or remote frame reception is completed, when

corresponding MBIMR = 0

Bit 8—Reset Interrupt Flag: Status flag indicating that the HCAN module has been reset. This

bit cannot be masked by the interrupt mask register (IMR). When this bit is not cleared after a

reset input or recovery from software standby mode, this bit executes the interrupt processing

immediately by enabling an interrupt by the interrupt controller.

Bit 8: IRR0 Description

0 [Clearing condition]

Writing 1

1 Hardware reset (HCAN module stop*, software standby) (Initial value)

[Setting condition]

When reset processing is completed after a hardware reset (HCAN module

stop*, software standby)

Note: *After reset or hardware standby release, the module stop bit is initialized to 1, and so the

HCAN enters the module stop state.

Bits 7 to 5, 3, and 2—Reserved: These bits always read 0. The write value should always be 0.

Bit 4—Bus Operation Interrupt Flag: Status flag indicating detection of a dominant bit due to

bus operation when the HCAN module is in HCAN sleep mode.

Bit 4: IRR12 Description

0 CAN bus idle state (Initial value)

[Clearing condition]

Writing 1

1 CAN bus operation in HCAN sleep mode

[Setting condition]

Bus operation (dominant bit detection) in HCAN sleep mode

550

Bit 1—Unread Interrupt Flag: Status flag indicating that a receive message has been overwritten

while still unread.

Bit 1: IRR9 Description

0 [Clearing condition]

Clearing of all bits in UMSR (unread message status register) (Initial value)

1 Unread message overwrite

[Setting condition]

When UMSR (unread message status register) is set

Bit 0—Mailbox Empty Interrupt Flag: Status flag indicating that the next transmit message can

be stored in the mailbox.

Bit 0: IRR8 Description

0 [Clearing condition]

Writing 1 (Initial value)

1 Transmit message has been transmitted or aborted, and new message can

be stored

[Setting condition]

When TXPR (transmit wait register) is cleared by completion of transmission

or completion of transmission abort

551

15.2.12 Mailbox Interrupt Mask Register (MBIMR)

The mailbox interrupt mask register (MBIMR) is a 16-bit readable/writable register containing

flags that enable or disable individual mailbox (buffer) interrupt requests.

MBIMR

Bit: 15 14 13 12 11 10 9 8

MBIMR7 MBIMR6 MBIMR5 MBIMR4 MBIMR3 MBIMR2 MBIMR1 MBIMR0

Initial value: 1 1 1 1 1 1 1 1

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bit: 7 6 5 4 3 2 1 0

MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 MBIMR8

Initial value: 1 1 1 1 1 1 1 1

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bits 15 to 0—Mailbox Interrupt Mask (MBIMRx): Flags that enable or disable individual

mailbox interrupt requests.

Bit x: MBIMRx Description

0 [Transmitting]

Interrupt request to CPU due to TXPR clearing

[Receiving]

Interrupt request to CPU due to RXPR setting

1 Interrupt requests to CPU disabled (Initial value)

(x = 15 to 0)

552

15.2.13 Interrupt Mask Register (IMR)

The interrupt mask register (IMR) is a 16-bit readable/writable register containing flags that

enable or disable requests by individual interrupt sources.

IMR

Bit: 15 14 13 12 11 10 9 8

IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 —

Initial value: 1 1 1 1 1 1 1 0

R/W: R/W R/W R/W R/W R/W R/W R/W —

Bit: 7 6 5 4 3 2 1 0

— — — IMR12 — — IMR9 IMR8

Initial value: 1 1 1 1 1 1 1 1

R/W: — — — R/W — — R/W R/W

Bit 15—Overload Frame/Bus Off Recovery Interrupt Mask: Enables or disables overload

frame/bus off recovery interrupt requests.

Bit 15: IMR7 Description

0 Overload frame/bus off recovery interrupt request to CPU by IRR7 enabled

1 Overload frame/bus off recovery interrupt request to CPU by IRR7 disabled

(Initial value)

Bit 14—Bus Off Interrupt Mask: Enables or disables bus off interrupt requests caused by the

transmit error counter.

Bit 14: IMR6 Description

0 Bus off interrupt request to CPU by IRR6 enabled

1 Bus off interrupt request to CPU by IRR6 disabled (Initial value)

Bit 13—Error Passive Interrupt Mask: Enables or disables error passive interrupt requests

caused by the transmit/receive error counter.

Bit 13: IMR5 Description

0 Error passive interrupt request to CPU by IRR5 enabled

1 Error passive interrupt request to CPU by IRR5 disabled (Initial value)

553

Bit 12—Receive Overload Warning Interrupt Mask: Enables or disables error warning

interrupt requests caused by the receive error counter.

Bit 12: IMR4 Description

0 REC error warning interrupt request to CPU by IRR4 enabled

1 REC error warning interrupt request to CPU by IRR4 disabled (Initial value)

Bit 11—Transmit Overload Warning Interrupt Mask: Enables or disables error warning

interrupt requests caused by the transmit error counter.

Bit 11: IMR3 Description

0 TEC error warning interrupt request to CPU by IRR3 enabled

1 TEC error warning interrupt request to CPU by IRR3 disabled (Initial value)

Bit 10—Remote Frame Request Interrupt Mask: Enables or disables remote frame reception

interrupt requests.

Bit 10: IMR2 Description

0 Remote frame reception interrupt request to CPU by IRR2 enabled

1 Remote frame reception interrupt request to CPU by IRR2 disabled

(Initial value)

Bit 9—Receive Message Interrupt Mask: Enables or disables message reception interrupt

requests.

Bit 9: IMR1 Description

0 Message reception interrupt request to CPU by IRR1 enabled

1 Message reception interrupt request to CPU by IRR1 disabled (Initial value)

Bit 8—Reserved: This bit always reads 0. The write value should always be 0.

Bits 7 to 5, 3, and 2—Reserved: These bits always read 1. The write value should always be 1.

Bit 4—Bus Operation Interrupt Mask: Enables or disables interrupt requests due to bus

operation in sleep mode.

Bit 4: IMR12 Description

0 Bus operation interrupt request to CPU by IRR12 enabled

1 Bus operation interrupt request to CPU by IRR12 disabled (Initial value)

554

Bit 1—Unread Interrupt Mask: Enables or disables unread receive message overwrite interrupt

requests.

Bit 1: IMR9 Description

0 Unread message overwrite interrupt request to CPU by IRR9 enabled

1 Unread message overwrite interrupt request to CPU by IRR9 disabled

(Initial value)

Bit 0—Mailbox Empty Interrupt Mask: Enables or disables mailbox empty interrupt requests.

Bit 0: IMR8 Description

0 Mailbox empty interrupt request to CPU by IRR8 enabled

1 Mailbox empty interrupt request to CPU by IRR8 disabled (Initial value)

15.2.14 Receive Error Counter (REC)

The receive error counter (REC) is an 8-bit read-only register that functions as a counter indicating

the number of receive message errors on the CAN bus. The count value is stipulated in the CAN

protocol.

REC

Bit: 7 6 5 4 3 2 1 0

Initial value: 0 0 0 0 0 0 0 0

R/W: R R R R R R R R

15.2.15 Transmit Error Counter (TEC)

The transmit error counter (TEC) is an 8-bit read-only register that functions as a counter

indicating the number of transmit message errors on the CAN bus. The count value is stipulated in

the CAN protocol.

TEC

Bit: 7 6 5 4 3 2 1 0

Initial value: 0 0 0 0 0 0 0 0

R/W: R R R R R R R R

555

15.2.16 Unread Message Status Register (UMSR)

The unread message status register (UMSR) is a 16-bit readable/writable register containing status

flags that indicate, for individual mailboxes (buffers), that a received message has been

overwritten by a new receive message before being read. If a previously received message is

overwritten by a newly received message, the old data will be lost.

UMSR

Bit: 15 14 13 12 11 10 9 8

UMSR7 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0

Initial value: 0 0 0 0 0 0 0 0

R/W: R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*

Bit: 7 6 5 4 3 2 1 0

UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 UMSR8

Initial value: 0 0 0 0 0 0 0 0

R/W: R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*

Note: *Only 1 can be written, to clear the flag.

Bits 15 to 0—Unread Message Status Flags (UMSRx): Status flags indicating that an unread

receive message has been overwritten.

Bit x: UMSRx Description

0 [Clearing condition]

Writing 1 (Initial value)

1 Unread receive message is overwritten by a new message

[Setting condition]

When a new message is received before RXPR is cleared

(x = 15 to 0)

556

15.2.17 Local Acceptance Filter Masks (LAFML, LAFMH)

The local acceptance filter masks (LAFML, LAFMH) are 16-bit readable/writable registers that

filter receive messages to be stored in the receive-only mailbox (RX0) according to the identifier.

In these registers, consist of LAFMH15 (MSB) to LAFMH5 (LSB) are 11 standard/extended

identifier bits, and LAFMH1 (MSB) to LAFML0 (LSB) are 18 extended identifier bits.

LAFML

Bit: 15 14 13 12 11 10 9 8

LAFML7 LAFML6 LAFML5 LAFML4 LAFML3 LAFML2 LAFML1 LAFML0

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bit: 7 6 5 4 3 2 1 0

LAFML15 LAFML14 LAFML13 LAFML12 LAFML11 LAFML10 LAFML9 LAFML8

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

LAFMH

Bit: 15 14 13 12 11 10 9 8

LAFMH7 LAFMH6 LAFMH5 ———LAFMH1 LAFMH0

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W — — — R/W R/W

Bit: 7 6 5 4 3 2 1 0

LAFMH15 LAFMH14 LAFMH13 LAFMH12 LAFMH11 LAFMH10 LAFMH9 LAFMH8

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

LAFMH Bits 7 to 0 and 15 to 13–11-Bit Identifier Filter (LAFMHx): Filter mask bits for the

first 11 bits of the receive message identifier (for both standard and extended identifiers).

Bit x: LAFMHx Description

0 Stored in RX0 (receive-only mailbox) depending on bit match between RX0

message identifier and receive message identifier (Initial value)

1 Stored in RX0 (receive-only mailbox) regardless of bit match between RX0

message identifier and receive message identifier

(x = 15 to 0)

557

LAFMH Bits 12 to 10—Reserved: These bits always read 0. The write value should always be 0.

LAFMH Bits 9 and 8, LAFML bits 15 to 0–18-Bit Identifier Filter (LAFMHx, LAFMLx):

Filter mask bits for the 18 bits of the receive message identifier (extended).

Bit x: LAFMHx

LAFMLx Description

0 Stored in RX0 (receive-only mailbox) depending on bit match between RX0

message identifier and receive message identifier (Initial value)

1 Stored in RX0 (receive-only mailbox) regardless of bit match between RX0

message identifier and receive message identifier

(x = 15 to 0)

15.2.18 Message Control (MC0 to MC15)

The message control register sets (MC0 to MC15) consist of eight 8-bit readable/writable registers

(MCx[1] to MCx[8]). The HCAN has 16 sets of these registers (MC0 to MC15).

The initial value of these registers is undefined, so they must be initialized (by writing 0 or 1).

MCx [1]

Bit: 7 6 5 4 3 2 1 0

— — — — DLC3 DLC2 DLC1 DLC0

Initial value: ********

R/W: — — — — — — — —

MCx [2]

Bit: 7 6 5 4 3 2 1 0

————————

Initial value: ********

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

MCx [3]

Bit: 7 6 5 4 3 2 1 0

————————

Initial value: ********

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

*:Undefined

558

MCx [4]

Bit: 7 6 5 4 3 2 1 0

————————

Initial value: ********

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

MCx [5]

Bit: 7 6 5 4 3 2 1 0

STD_ID2 STD_ID1 STD_ID0 RTR IDE —EXD_ID17EXD_ID16

Initial value: ********

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

MCx [6]

Bit: 7 6 5 4 3 2 1 0

STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3

Initial value: ********

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

MCx [7]

Bit: 7 6 5 4 3 2 1 0

EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0

Initial value: ********

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

MCx [8]

Bit: 7 6 5 4 3 2 1 0

EXD _ID 15 EXD _ID 14 EXD _ID 13 EXD _ID 12 EXD _ID 11 EXD _ID 10 EXD _ID 9 EXD _ID8

Initial value: ***** ***

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

*:Undefined

(x = 15 to 0)

MCx[1] Bits 7 to 4—Reserved: The initial value of these bits is undefined; they must be

initialized (by writing 0 or 1).

559

MCx[1] Bits 3 to 0—Data Length Code (DLC): These bits indicate the required length of data

frames and remote frames.

Bit 3:

DLC3 Bit 2:

DLC2 Bit 1:

DLC1 Bit 0:

DLC0 Description

0000Data length = 0 byte

1 Data length = 1 byte

1 0 Data length = 2 bytes

1 Data length = 3 bytes

1 0 0 Data length = 4 bytes

1 Data length = 5 bytes

1 0 Data length = 6 bytes

1 Data length = 7 bytes

1000Data length = 8 bytes

Other than the above Setting prohibited

MCx[2] Bits 7 to 0—Reserved: The initial value of these bits is undefined; they must be

initialized (by writing 0 or 1).

MCx[3] Bits 7 to 0—Reserved: The initial value of these bits is undefined; they must be

initialized (by writing 0 or 1).

MCx[4] Bits 7 to 0—Reserved: The initial value of these bits is undefined; they must be

initialized (by writing 0 or 1).

MCx[6] Bits 7 to 0—Standard Identifier (STD_ID10 to STD_ID3):

MCx[5] Bits 7 to 5—Standard Identifier (STD_ID2 to STD_ID0):

These bits set the identifier (standard identifier) of data frames and remote frames.

Standard identifier

SOF ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR

STD_IDxx

IDE

SRR

Figure 15-2 Standard Indentifier

560

MCx[5] Bit 4—Remote Transmission Request (RTR): Used to distinguish between data frames

and remote frames.

Bit 4: RTR Description

0 Data frame

1 Remote frame

MCx[5] Bit 3—Identifier Extension (IDE): Used to distinguish between the standard format and

extended format of data frames and remote frames.

Bit 3: IDE Description

0 Standard format

1 Extended format

MCx[5] Bit 2—Reserved: The initial value of this bit is undefined; it must be initialized (by

writing 0 or 1).

MCx[5] Bits 1 and 0—Extended Identifier (EXD_ID17, EXD_ID16):

MCx[8] Bits 7 to 0—Extended Identifier (EXD_ID15 to EXD_ID8):

MCx[7] Bits 7 to 0—Extended Identifier (EXD_ID7 to EXD_ID0):

These bits set the identifier (extended identifier) of data frames and remote frames.

Extended Identifier

IDE ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5

EXD_IDxx

ID4 ID3 ID2 ID1 ID0 RTR R1

EXD_IDxx

Figure 15-3 Extended Indentifier

561

15.2.19 Message Data (MD0 to MD15)

The message data register sets (MD0 to MD15) consist of eight 8-bit readable/writable registers

(MDx[1] to MDx[8]). The HCAN has 16 sets of these registers (MD0 to MD15).

The initial value of these registers is undefined, so they must be initialized (by writing 0 or 1).

MDx [1] MSG_DATA_1 (8 bits)

MDx [2] MSG_DATA_2 (8 bits)

MDx [3] MSG_DATA_3 (8 bits)

MDx [4] MSG_DATA_4 (8 bits)

MDx [5] MSG_DATA_5 (8 bits)

MDx [6] MSG_DATA_6 (8 bits)

MDx [7] MSG_DATA_7 (8 bits)

MDx [8] MSG_DATA_8 (8 bits)

(x = 15 to 0)

15.2.20 Module Stop Control Register C (MSTPCRC)

Bit: 7 6 5 4 3 2 1 0

MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0

Initial value: 11111111

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

MSTPCRC is an 8-bit readable/writable register that performs module stop mode control.

When the MSTPC3 bit is set to 1, HCAN operation is stopped at the end of the bus cycle, and

module stop mode is entered. Register read/write accesses are not possible in module stop mode.

For details, see section 22.5, Module Stop Mode.

MSTPCRC is initialized to H'FF by a reset, and in hardware standby mode. It is not initialized in

software standby mode.

Bit 3—Module Stop (MSTPC3): Specifies the HCAN module stop mode.

Bit 3: MSTPC3 Description

0 HCAN module stop mode is cleared

1 HCAN module stop mode is set (Initial value)

562

15.3 Operation

This LSI device is equipped with 2-channel HCAN modules, which are controlled independently.

Both modules have identical specifications, and they are controlled in the same manner.

15.3.1 Hardware and Software Resets

The HCAN can be reset by a hardware reset or software reset.

Hardware Reset (HCAN Module Stop, Reset*, Hardware*/Software Standby): Initialization

is performed by automatic setting of the MCR reset request bit (MCR0) in MCR and the reset state

bit (GSR3) in GSR within the HCAN (hardware reset). At the same time, all internal registers are

initialized. However mailbox contents are retained. A flowchart of this reset is shown in figure

15-4.

Note: * In a reset and in hardware standby mode, the module stop bit is initialized to 1 and the

HCAN enters the module stop state.

Software Reset (Write to MCR0): In normal operation initialization is performed by setting the

MCR reset request bit (MCR0) in MCR (Software reset). With this kind of reset, if the CAN

controller is performing a communication operation (transmission or reception), the initialization

state is not entered until the message has been completed. During initialization, the reset state bit

(GSR3) in GSR is set. In this kind of initialization, the error counters (TEC and REC) are

initialized but other registers and RAM (mailboxes) are not. A flowchart of this reset is shown in

figure 15-5.

15.3.2 Initialization after Hardware Reset

After a hardware reset, the following initialization processing should be carried out:

• IRR0 bit in the interrupt register (IRR) clearing

• Bit rate setting

• Mailbox transmit/receive settings

• Mailbox (RAM) initialization

• Message transmission method setting

These initial settings must be made while the HCAN is in bit configuration mode. Configuration

mode is a state in which the reset request bit (MCR0) in the master control register (MCR) is 1 and

the reset status bit in the general status register (GSR) is also 1 (GSR3 = 1). Configuration mode is

exited by clearing the reset request bit in MCR to 0; when MCR0 is cleared to 0, the HCAN

automatically clears the reset state bit (GSR3) in the general status register (GSR). The power-up

sequence then begins, and communication with the CAN bus is possible as soon as the sequence

ends. The power-up sequence consists of the detection of 11 consecutive recessive bits.

563

IRR0 = 1 (automatic)*1

GSR3 = 1 (automatic)

Initialization of HCAN module

Clear IRR0

BCR setting

MBCR setting

Mailbox (RAM) initialization

Message transmission method initialization

Hardware reset

MCR0 = 1 (automatic)

GSR3 = 0?

GSR3 = 0 & 11

recessive bits received?

CAN bus communication enabled

IMR setting (interrupt mask setting)

MBIMR setting (interrupt mask setting)

MC[x] setting (receive identifier setting)

LAFM setting (receive identifier mask setting)

MCR0 = 0

Bit configuration mode

Period in which BCR, MBCR, etc.,

are initialized

: Settings by user

: Processing by hardware

Yes

Notes: *1 When IRR0 is set to 1 (automatically) due to a hardware reset*2, a "hardware reset

initiated reset processing" interrupt is generated.

*2 In a reset and in hardware standby mode, the module stop bit is initialized to 1 and

the HCAN enters the module stop state.

Figure 15-4 Hardware Reset Flowchart

564

Initialization of REC and TEC only

MCR0 = 1

GSR3 = 1 (automatic)

Bus idle?

CAN bus communication enabled

: Settings by user

: Processing by hardware

Yes

MCR0 = 0

GSR3 = 0? No

IMR setting

MBIMR setting

MC[x] setting

LAFM setting

OK?

Yes

Correction

BCR setting

MBCR setting

Mailbox (RAM) initialization

Message transmission method

initialization

OK?

GSR3 = 0 & 11

recessive bits received?

Figure 15-5 Software Reset Flowchart

565

Clearing the IRR0 bit of the Interrupt Register (IRR): The reset interrupt flag (IRR0) is

always set after a reset or recovery from software standby mode. A HCAN interrupt is

immediately entered if interrupts are enabled, so the IRR0 must be cleared.

Bit Rate and Bit Timing Settings: As bit rate settings, a baud rate setting and bit timing setting

must be made each time a CAN node begins communication. The baud rate and bit timing settings

are made in the bit configuration register (BCR).

Note: BCR can be written to at all times, but should only be modified in configuration mode.

Settings should be made so that all CAN controllers connected to the CAN bus have the

same baud rate and bit width.

Refer to table 15.3 for the range of values that can be used as settings (TSEG1, TSEG2,

BRP, sample point, and SJW) for BCR.

Table 15-3 BCR Register Value Setting Ranges

Name Abbreviation Min.

Value Max.

Value

Time segment 1 TSEG1 B'0011 B'1111

Time segment 2 TSEG2 B'001 B'111

Baud rate prescaler BRP B'000000 B'111111

Sample point SAM B'0 B'1

Re-synchronization jump width SJW B'00 B'11

Value Setting Ranges

• The value of SJW is stipulated in the CAN specifications.

3 ≥ SJW ≥ 0

• The minimum value of TSEG1 is stipulated in the CAN specifications.

TSEG1 > TSEG2

• The minimum value of TSEG2 is stipulated in the CAN specifications.

TSEG2 ≥ SJW

The following formula is used to calculate the baud rate.

fCLK

2 × (BRP + 1) × (3 + TSEG1 + TSEG2)

Bit rate =

Note: fCLK = φ (system clock)

The BCR value is used in the BRP, TSEG1, and TSEG2.

566

Example: With a 1 Mb/s baud rate and a 20 MHz input clock:

20 MHz

2 × (0 + 1) × (3 + 4 + 3)

1 Mb/s =

Set Values Actual Values

fCLK = 20 MHz —

BRP = 0 (B'000000) System clock × 2

TSEG1 = 4 (B'0100) 5TQ

TSEG2 = 3 (B'011) 4TQ

SYNC_SEG PRSEG PHSEG1 PHSEG2

1-bit time 1-bit time (8–25 time quanta)

Quantum

1 TSEG1 (time segment 1)*

2–16

TSEG2 (time segment 2)

2–8

Legend

SYNC_SEG: Segment for establishing synchronization of nodes on the CAN bus. (Normal

bit edge transitions occur in this segment.)

PRSEG: Segment for compensating for physical delay between networks.

PHSEG1: Buffer segment for correcting phase drift (positive). (This segment is extended

when synchronization (resynchronization) is established.)

PHSEG2: Buffer segment for correcting phase drift (negative). (This segment is

shortened when synchronization (resynchronization) is established.)

Note: * The time quanta values of TSEG1 and TSEG2 become the value of TSEG + 1.

Figure 15-6 Detailed Description of Timing within 1 Bit

HCAN bit rate calculation:

fCLK

2 × (BRP + 1) × (3 + TSEG1 + TSEG2)

Bit rate =

Note: fCLK = ø (system clock)

The BCR values are used for BRP, TSEG1, and TSEG2.

BCR Setting Constraints

TSEG1 > TSEG2 ≥ SJW (SJW = 0 to 3)

These constraints allow the setting range shown in table 15-4 for TSEG1 and TSEG2 in BCR.

567

Table 15-4 Setting Range for TSEG1 and TSEG2 in BCR

TSEG2 (BCR [14:12])

001 010 011 100 101 110 111

TSEG1 0011 No Yes No No No No No

(BCR [11:8]) 0100 Yes*Yes Yes No No No No

0101 Yes*Yes Yes Yes No No No

0110 Yes*Yes Yes Yes Yes No No

0111 Yes*Yes Yes Yes Yes Yes No

1000 Yes*Yes Yes Yes Yes Yes Yes

1001 Yes*Yes Yes Yes Yes Yes Yes

1010 Yes*Yes Yes Yes Yes Yes Yes

1011 Yes*Yes Yes Yes Yes Yes Yes

1100 Yes*Yes Yes Yes Yes Yes Yes

1101 Yes*Yes Yes Yes Yes Yes Yes

1110 Yes*Yes Yes Yes Yes Yes Yes

1111 Yes*Yes Yes Yes Yes Yes Yes

Notes: The time quanta value for TSEG1 and TSEG2 is the TSEG value + 1.

*Only a value other than BRP[13:8] = B'000000 can be set.

Mailbox Transmit/Receive Settings: HCAN0, 1 each have 16 mailboxes. Mailbox 0 is receive-

only, while mailboxes 1 to 15 can be set for transmission or reception. Mailboxes that can be set

for transmission or reception must be designated either for transmission use or for reception use

before communication begins. The Initial status of mailboxes 1 to 15 is for transmission (while

mailbox 0 is for reception only). Mailbox transmit/receive settings are not initialized by a software

reset.

• Setting for transmission

Transmit mailbox setting (mailboxes 1 to 15)

Clearing a bit to 0 in the mailbox configuration register (MBCR) designates the corresponding

mailbox for transmission use. After a reset, mailboxes are initialized for transmission use, so

this setting is not necessary.

568

• Setting for reception

Transmit/receive mailbox setting (mailboxes 1 to 15)

Setting a bit to 1 in the mailbox configuration register (MBCR) designates the corresponding

mailbox for reception use. When setting mailboxes for reception, to improve message

transmission efficiency, high-priority messages should be set in low-to-high mailbox order

(priority order: mailbox 1 > mailbox 15).

• Receive-only mailbox (mailbox 0)

No setting is necessary, as this mailbox is always used for reception.

569

Mailbox (Message Control/Data (MCx[x], MDx[x])) Initial Settings: After power is supplied,

all registers and RAM (message control/data, control registers, status registers, etc.) are initialized.

Message control/data (MCx[x], MDx[x]) only are in RAM, and so their values are undefined.

Initial values must therefore be set in all the mailboxes (by writing 0s or 1s).

Setting the Message Transmission Method: Either of the following message transmission

methods can be selected with the message transmission method bit (MCR2) in the master control

a. Transmission order determined by message identifier priority

b. Transmission order determined by mailbox number priority

When a is selected, if a number of messages are designated as waiting for transmission (TXPR =

1), the message with the highest priority set in the message identifier (MCx[5]–MCx[8]) is stored

in the transmit buffer. CAN bus arbitration is then carried out for the message in the transmit

buffer, and message transmission is performed when the transmission right is acquired. When the

TXPR bit is set, internal arbitration is performed again, and the highest-priority message is found

and stored in the transmit buffer.

When b is selected, if a number of messages are designated as waiting for transmission (TXPR =

1), messages are stored in the transmit buffer in low-to-high mailbox order (priority order:

mailbox 1 > mailbox 15). CAN bus arbitration is then carried out for the messages in the transmit

buffer, and message transmission is performed when the bus is acquired.

15.3.3 Transmit Mode

Message transmission is performed using mailboxes 1 to 15. The transmission procedure is

described below, and a transmission flowchart is shown in figure 15-7.

Initialization (after hardware reset only)

a. IRR0 bit in the intereupt register (IRR0) clearing

b. Bit rate settings

c. Mailbox transmit/receive settings

d. Mailbox initialization

e. Message transmission method setting

Interrupt and transmit data settings

a. CPU interrupt source setting

b. Arbitration field setting

c. Control field setting

d. Data field setting

570

Message transmission and interrupts

a. Message transmission wait

b. Message transmission completion and interrupt

c. Message transmission abort

d. Message retransmission

Initialization (After Hardware Reset Only): These settings should be made while the HCAN is

in bit configuration mode.

• IRR0 clearing

The reset interrupt flag (IRR0) is always set after a reset or recovery from software standby

mode. A HCAN interrupt is immediately entered if interrupts are enabled, so that IRR0 must

be cleared.

• Bit rate settings

Set values relating to the CAN bus communication speed and resynchronization. Refer to Bit

Rate and Bit Timing Settings in section 15.3.2, Initialization after Hardware Reset, for details.

• Mailbox transmit/receive settings

Mailbox transmit/receive settings should be made in advance. A total of 15 mailbox can be set

for transmission or reception (mailboxes 1 to 15). To set a mailbox for transmission, clear the

corresponding bit to 0 in the mailbox configuration register (MBCR). Refer to Mailbox

transmit/receive settings in section 15.3.2, Initialization after Hardware Reset, for details.

• Mailbox initialization

As message control/data registers (MCx[x], MDx[x]) are configured in RAM, their initial

values after powering on are undefined, and so bit initialization is necessary. Write 0s or 1s to

the mailboxes. Refer to Mailbox (message control/data (Mcx[x], Mdx[x])) initial settings in

section 15.3.2, Initialization after Hardware Reset, for details.

• Message transmission method setting

Set the transmission method for mailboxes designated for transmission. The following two

transmission methods can be used. Refer to Message transmission method settings in section

15.3.2, Initialization after Hardware Reset, for details.

a. Transmission order determined by message identifier priority

b. Transmission order determined by mailbox number priority

571

Initialization (after hardware reset only)

IRR0 clearing

BCR setting

MBCR setting

Mailbox initialization

Message transmission method setting

Interrupt settings

Transmit data setting

Arbitration field setting

Control field setting

Data field setting

Message transmission wait

TXPR setting

Bus idle? No

Message transmission

GSR2 = 0 (during transmission only)

Transmission completed? No

TXACK = 1

IRR8 = 1

IMR8 = 1? Yes

Interrupt to CPU

Clear TXACK

Clear IRR8

End of transmission

: Settings by user

: Processing by hardware

Yes

Figure 15-7 Transmission Flowchart

572

Interrupt and Transmit Data Settings: When mailbox initialization is finished, CPU interrupt

source settings and data settings must be made. Interrupt source settings are made in the mailbox

interrupt register (MBIMR) and interrupt mask register (IMR), while transmit data settings are

made by writing the necessary data from the arbitration field, control field, and data field,

described below, in the corresponding message control (MCx[1]–MCx[8]) and message data

(MDx[1]–MDx[8]).

• CPU interrupt source settings

Transmission acknowledge and transmission abort acknowledge interrupts can be masked for

individual mailboxes in the mailbox interrupt mask register (MBIMR). Interrupt register (IRR)

interrupts can be masked in the interrupt mask register (IMR).

• Arbitration field setting

In the arbitration field, the 11-bit identifier (STD_ID0–STD_ID10) and RTR bit (standard

format) or 29-bit identifier (STD_ID0–STD_ID10, EXT_ID0–EXT_ID17) and IDE.RTR bit

(extended format) are set. The registers to be set are MCx[5]–MCx[8].

• Control field setting

In the control field, the byte length of the data to be transmitted is set in DLC0–DLC3. The

• Data field setting

In the data field, the data to be transmitted is set in byte units in the range of 0 to 8 bytes. The

registers to be set are MDx[1]–MDx[8].

The number of bytes in the data actually transmitted depends on the data length code (DLC) in the

control field. If a value exceeding the value set in DLC is set in the data field, only the number of

bytes set in DLC will actually be transmitted.

Message Transmission and Interrupts:

• Message transmission wait

If message transmission is to be performed after completion of the message control (MCx[1]–

MCx[8]) and message data (MDx[1]–MDx[8]).settings, transmission is started by setting the

corresponding mailbox transmit wait bit (TXPR1–TXPR15) to 1 in the transmit wait register

(TXPR). The following two transmission methods can be used:

a. Transmission order determined by message identifier priority

b. Transmission order determined by mailbox number priority

When a is selected, if a number of messages are designated as waiting for transmission (TXPR

= 1), messages are stored in the transmit buffer in low-to-high mailbox order (priority order:

mailbox 1 > mailbox 15). CAN bus arbitration is then carried out for the messages in the

transmit buffer, and message transmission is performed when the bus is acquired.

573

When b is selected, if a number of messages are designated as waiting for transmission (TXPR

= 1), the message with the highest priority set in the message identifier (MCx[5]–MCx[8]) is

stored in the transmit buffer. CAN bus arbitration is then carried out for the message in the

transmit buffer, and message transmission is performed when the transmission right is

acquired. When the TXPR bit is set, internal arbitration is performed again, the highest-priority

message is found and stored in the transmit buffer, CAN bus arbitration is carried out in the

same way, and message transmission is performed when the transmission right is acquired.

• Message transmission completion and interrupt

When a message is transmitted error-free using the above procedure, The corresponding

acknowledge bit (TXACK1–TXACK15) in the transmit acknowledge register (TXACK) and

transmit wait bit (TXPR1–TXPR15) in the transmit wait register (TXPR) are automatically

initialized. When the corresponding bits (MBIMR1 to MBIMR15) of the mailbox interrupt

mask register (MBIMR) and the mailbox empty interrupt (IRR8) of the interrupt mask register

(IMR) are set to enable interrupts, they can issue an interrupt to the CPU.

• Message transmission cancellation

Transmission cancellation can be specified for a message stored in a mailbox as a transmit wait

message. A transmit wait message is canceled by setting the bit for the corresponding mailbox

(TXCR1–TXCR15) to 1 in the transmit cancel register (TXCR). When cancellation is

executed, the transmit wait register (TXPR) is automatically reset, and the corresponding bit is

set to 1 in the abort acknowledge register (ABACK). An interrupt to the CPU can be requested.

Also, if the mailbox empty interrupt (IRR8) is enabled for the bits (MBIMR1-MBIMR15)

corresponding to the mailbox interrupt mask register (MBIMR) and interrupt mask register

(IMR), interrupts may be sent to the CPU.

However, a transmit wait message cannot be canceled at the following times:

a. During internal arbitration or CAN bus arbitration

b. During data frame or remote frame transmission

Also, transmission cannot be canceled by clearing the transmit wait register (TXPR). Figure

15-8 shows a flowchart of transmit message cancellation.

• Message retransmission

If transmission of a transmit message is aborted in the following cases, the message is

retransmitted automatically:

a. CAN bus arbitration failure (failure to acquire the bus)

b. Error during transmission (bit error, stuff error, CRC error, frame error, ACK error)

574

Message transmit wait TXPR setting

Set TXCR bit corresponding to message

to be canceled

Cancellation possible? No

Message not sent

Clear TXCR, TXPR

ABACK = 1

IRR8 = 1

IMR8 = 1? Yes

Interrupt to CPU

Clear TXACK

Clear ABACK

Clear IRR8

End of transmission/transmission

cancellation

Completion of message transmission

TXACK = 1

Clear TXCR, TXPR

IRR8 = 1

Yes

: Settings by user

: Processing by hardware

Figure 15-8 Transmit Message Cancellation Flowchart

575

15.3.4 Receive Mode

Message reception is performed using mailboxes 0 and 1 to 15. The reception procedure is

described below, and a reception flowchart is shown in figure 15-9.

Initialization (after hardware reset only)

a. IRR0 bit in the interrupt register (IRR0) clearing

b. Bit rate settings

c. Mailbox transmit/receive settings

d. Mailbox (RAM) initialization

Interrupt and receive message settings

a. CPU interrupt source setting

b. Arbitration field setting

c. Local acceptance filter mask (LAFM) settings

Message reception and interrupts

a. Message reception CRC check

b. Data frame reception

c. Remote frame reception

d. Unread message reception

Initialization (After Hardware Reset Only): These settings should be made while the HCAN is

in bit configuration mode.

• IRR0 clearing

The reset interrupt flag (IRR0) is always set after a reset or recovery from software standby

mode. A HCAN interrupt is immediately entered if interrupts are enabled, so the IRR0 must

be cleared.

• Bit rate settings

Set values relating to the CAN bus communication speed and resynchronization. Refer to Bit

Rate and Bit Timing Settings in section 15.3.2, Initialization after Hardware Reset, for details.

• Mailbox transmit/receive settings

Each channel has one receive-only mailbox (mailbox 0) plus 15 mailboxes that can be set for

reception. Thus a total of 16 mailboxes can be used for reception. To set a mailbox for

reception, set the corresponding bit to 1 in the mailbox configuration register (MBCR). The

initial setting for mailboxes is 0, designating transmission use. Refer to Mailbox

transmit/receive settings in section 15.3.2, Initialization after Hardware Reset, for details.

576

• Mailbox (RAM) initialization

As message control/data registers (MCx[x], MDx[x]) are configured in RAM, their initial

values after powering on are undefined, and so bit initialization is necessary. Write 0s or 1s to

the mailboxes. Refer to Mailbox (message control/data (MCx[x], MDx[x])) initial settings in

section 15.3.2, Initialization after Hardware Reset, for details.

577

Initialization BCR setting

MBCR setting

Mailbox (RAM) initialization

Interrupt settings

Arbitration field setting

Local acceptance filter settings

Receive data setting

Message reception

(Match of identifier

in mailbox?)

Same RXPR = 1? Yes

Data frame? No

RXPR

IRR1 = 1

Yes

IMR1 = 1?

Interrupt to CPU

Message control read

Message data read

Clear IRR1

End of reception

Yes

Unread message

RXPR, RFPR = 1

IRR2 = 1, IRR1 = 1

Yes

IMR2 = 1?

Interrupt to CPU

Message control read

Message data read

Clear all RXPRn and RFPRn bits in the

mailbox, which enables the receive interupt

requests in the MBIMR

Clear all RXPR bit in the mailbox, which

enables the receive interupts

requests in the MBIMR

Clear IRR2, IRR1

Transmission of data frame corresponding

to remote frame

: Settings by user

: Processing by hardware

Figure 15-9 Reception Flowchart

578

Interrupt and Receive Message Settings: When mailbox initialization is finished, CPU interrupt

source settings and receive message specifications must be made. Interrupt source settings are

made in the mailbox interrupt register (MBIMR) and interrupt mask register (IMR). To receive a

message, the identifier must be set in advance in the message control (MCx[1]–MCx[8]) for the

receiving mailbox. When a message is received, all the bits in the receive message identifier are

compared, and if a 100% match is found, the message is stored in the matching mailbox. Mailbox

0 (MB0) has a local acceptance filter mask (LAFM) that allows Don’t Care settings to be made.

• CPU interrupt source settings

When transmitting, transmission acknowledge and transmission abort acknowledge interrupts

can be masked for individual mailboxes in the mailbox interrupt mask register (MBIMR).

When receiving, data frame and remote frame receive wait interrupts can be masked. Interrupt

• Arbitration field setting

In the arbitration field, the identifier (STD_ID0–STD_ID10, EXT_ID0–EXT_ID17) of the

message to be received is set. If all the bits in the set identifier do not match, the message is not

stored in a mailbox.

Example: Mailbox 1 010_1010_1010 (standard identifier)

Only one kind of message identifier can be received by MB1

Identifier 1: 010_1010_1010

• Local acceptance filter mask (LAFM) setting

The local acceptance filter mask is provided for mailbox 0 (MB0) only, enabling a Don’t Care

specification to be made for all bits in the received identifier. This allows various kinds of

messages to be received.

Example: Mailbox 0 010_1010_1010 (standard identifier)

LAFM 000_0000_0011 (0: Care, 1: Don’t Care)

A total of four kinds of message identifiers can be received by MB0

Identifier 1: 010_1010_1000

Identifier 2: 010_1010_1001

Identifier 3: 010_1010_1010

Identifier 4: 010_1010_1011

579

Message Reception and Interrupts:

• Message reception CRC check

When a message is received, a CRC check is performed automatically (by hardware). If the

result of the CRC check is normal, ACK is transmitted in the ACK field irrespective of

whether or not the message can be received.

• Data frame reception

If the received message is confirmed to be error-free by the CRC check, etc., the identifier in

the mailbox (and also LAFM in the case of mailbox 0 only) and the identifier of the receive

message are compared, and if a complete match is found, the message is stored in the mailbox.

The message identifier comparison is carried out on each mailbox in turn, starting with

mailbox 0 and ending with mailbox 15. If a complete match is found, the comparison ends at

that point, the message is stored in the matching mailbox, and the corresponding receive

complete bit (RXPR0–RXPR15) is set in the receive complete register (RXPR). However,

when a mailbox 0 LAFM comparison is carried out, even if the identifier matches, the mailbox

comparison sequence does not end at that point, but continues with mailbox 1 and then the

remaining mailboxes. It is therefore possible for a message matching mailbox 0 to be received

by another mailbox (however, the same message cannot be stored in more than one of

mailboxes 1 to 15). If the corresponding bit (MBIMR0–MBIMR15) in the mailbox interrupt

mask register (MBIMR) and the receive message interrupt mask (IMR1) in the interrupt mask

CPU.

• Remote frame reception

Two kinds of messages—data frames and remote frames—can be stored in mailboxes. A

remote frame differs from a data frame in that the remote reception request bit (RTR) in the

message control register (MC[x]5) and the data field are 0 bytes. The data length to be returned

in a data frame must be stored in the data length code (DLC) in the control field.

When a remote frame (RTR = recessive) is received, the corresponding bit is set in the remote

request wait register (RFPR). If the corresponding bit (MBIMR0–MBIMR15) in the mailbox

interrupt mask register (MBIMR) and the remote frame request interrupt mask (IRR2) in the

interrupt mask register (IMR) are set to the interrupt enable value at this time, an interrupt can

be sent to the CPU.

• Unread message reception

When the identifier in a mailbox matches a receive message, the message is stored in the

mailbox. If a message overwrite occurs before the CPU reads the message, the corresponding

bit (UMSR0–UMSR15) is set in the unread message register (UMSR). In overwriting of an

unread message, when a new message is received before the corresponding bit in the receive

complete register (RXPR) has been cleared, the unread message register (UMSR) is set. If the

unread interrupt flag (IRR9) in the interrupt mask register (IMR) is set to the interrupt enable

580

value at this time, an interrupt can be sent to the CPU. Figure 15-10 shows a flowchart of

unread message overwriting.

UMSR = 1

IRR9 = 1

Unread message overwrite

IMR9 = 1?

End

Yes

Interrupt to CPU

Clear IRR9

Message control/message data read

: Settings by user

: Processing by hardware

Figure 15-10 Unread Message Overwrite Flowchart

581

15.3.5 HCAN Sleep Mode

The HCAN is provided with an HCAN sleep mode that places the HCAN module in the sleep

state to reduce current dissipation. Figure 15-11 shows a flowchart of the HCAN sleep mode.

MCR5 = 1

Bus operation?

IRR12 = 1

Initialize TEC and REC

IMR12 = 1?

Sleep mode clearing method

MCR7 = 0?

MCR5 = 0

CAN bus communication possible

CPU interrupt

MCR5=0

Clear sleep mode?

Yes

Yes (manual)

No (automatic)

Yes

: Settings by user

: Processing by hardware

11 recessive bits?

Bus idle?

Figure 15-11 HCAN Sleep Mode Flowchart

582

HCAN sleep mode is entered by setting the HCAN sleep mode bit (MCR5) to 1 in the master

control register (MCR). If the CAN bus is operating, the transition to HCAN sleep mode is

delayed until the bus becomes idle.

Either of the following methods of clearing HCAN sleep mode can be selected by making a setting

in the MCR7 bit.

1. Clearing by software

2. Clearing by CAN bus operation

Eleven recessive bits must be received after HCAN sleep mode is cleared before CAN bus

communication is enabled again.

Clearing by software: HCAN sleep mode is cleared by writing a 0 to MCR5 from the CPU.

Clearing by CAN bus operation: Clearing by CAN bus operation occurs automatically when the

CAN bus performs an operation and this change is detected. The first message is not received in

the mailbox and normal receiving starts from the next message. When a change is detected on the

CAN bus in HCAN sleep mode, the bus operation interrupt flag (IRR12) is set in the interrupt

interrupt enable value at this time, an interrupt can be sent to the CPU.

15.3.6 HCAN Halt Mode

The HCAN halt mode is provided to enable mailbox settings to be changed without performing an

HCAN hardware or software reset. Figure 15-12 shows a flowchart of the HCAN halt mode.

MCR1 = 1

Bus idle?

CAN bus communication possible

MBCR setting

MCR1 = 0

Yes

: Settings by user

: Processing by hardware

Figure 15-12 HCAN Halt Mode Flowchart

583

HCAN halt mode is entered by setting the halt request bit (MCR1) to 1 in the master control

the bus becomes idle.

HCAN halt mode is cleared by clearing MCR1 to 0.

15.3.7 Interrupt Interface

There are 12 HCAN interrupt sources, to which five independent interrupt vectors are assigned.

Table 15-5 lists the HCAN interrupt sources.

With the exception of the reset processing vector (IRR0), these sources can be masked. Masking is

implemented using the mailbox interrupt mask register (MBIMR) and interrupt mask register

(IMR).

Table 15-5 HCAN Interrupt Sources

IPR Bits Vector Vector Number IRR Bit Description

IPRM (2–0) ERS0 108 IRR5 Error passive interrupt (TEC ≥ 128 or REC ≥

128)

IRR6 Bus off interrupt (TEC ≥ 256)

OVR0 108 IRR0 Reset processing interrupt

IRR2 Remote frame reception interrupt

IRR3 Error warning interrupt (TEC ≥ 96)

IRR4 Error warning interrupt (REC ≥ 96)

IRR7 Overload frame transmission interrupt

IRR9 Unread message overwrite interrupt

IRR12 HCAN sleep mode CAN bus operation

interrupt

RM0 109 IRR1 Mailbox 0 message reception interrupt

RM1 108 IRR1 Mailbox 1-15 message reception interrupt

SLE0 108 IRR8 Message transmission/cancellation interrupt

584

15.3.8 DTC Interface

The DTC can be activated by reception of a message in the HCAN’s mailbox 0. When DTC

transfer ends after DTC activation has been set, the RXPR0 and RFPR0 flags are acknowledge

signal automatically. An interrupt request due to a receive interrupt from the HCAN cannot be sent

to the CPU in this case. Figure 15-13 shows a DTC transfer flowchart.

DTC enable register setting

DTC register information setting

End of DTC transfer?

End

DTC initialization

Message reception in HCAN’s

mailbox 0

DTC activation

Transfer counter = 0

or DISEL = 1? No

Interrupt to CPU

Yes

: Settings by user

: Processing by hardware

RXPR and RFPR clearing

Figure 15-13 DTC Transfer Flowchart

585

15.4 CAN Bus Interface

A bus transceiver IC is necessary to connect the H8S/2646 Series chip to a CAN bus. A Philips

PCA82C250 transceiver IC, or compatible device, is recommended. Figure 15-14 shows a sample

connection diagram.

RxD

TxD

Vref

Vcc

CANH

CANL

GND

HRxD

HTxD

H8S/2646 Series

CAN bus

124 Ω

Vcc

PCA82C250

No connection

Figure 15-14 High-Speed Interface Using PCA82C250

15.5 Usage Notes

1. Reset

The HCAN is reset by a reset, and in hardware standby mode and software standby mode. All

the registers are initialized in a reset, but mailboxes (message control (MCx[x])/message data

(MDx[x]) are not. However, after powering on, mailboxes (message control (MCx[x])/message

data (MDx[x]) are initialized, and their values are undefined. Therefore, mailbox initialization

must always be carried out after a reset or a transition to hardware standby mode or software

standby mode. The reset interrupt flag (IRR0) is always set after a reset or recovery from

software standby mode. This bit cannot be masked by the interrupt mask register (IMR). When

a flag is not cleared and the interrupt controller enables HCAN interrupts, the HCAN interrupts

the CPU. Clear IRR0 during initialization.

2. HCAN sleep mode

The bus operation interrupt flag (IRR12) in the interrupt register (IRR) is set by bus operation

in HCAN sleep mode. Therefore, this flag is not used by the HCAN to indicate sleep mode

release. Also note that the reset status bit (GSR3) in the general status register (GSR) is set in

sleep mode.

3. Interrupts

When the mailbox interrupt mask register (MBIMR) is set, the interrupt register (IRR8,2,1) is

586

not set by reception completion, transmission completion, or transmission cancellation for the

set mailboxes.

4. Error counters

In the case of error active and error passive, REC and TEC normally count up and down. In the

bus off state, 11-bit recessive sequences are counted (REC + 1) using REC. If REC reaches 96

during the count, IRR4 and GSR1 are set.

5. Register access

Byte or word access can be used on all HCAN registers. Longword access cannot be used.

6. HCAN medium-speed mode

In medium-speed mode, the HCAN register cannot be read from or written to.

7. Register hold during standby

All registers in the HCAN are initialized on entering hardware standby or software modes.

8. Usage of bit manipulation instructions

The HCAN status flags are cleared by writing 1, so do not use a bit manipulation instruction to

clear a flag.

When clearing a flag, use the MOV instruction to write 1 to only the bit that is to be cleared.

9. HTxD pin output in error passive state

If the HRxD pin becomes fixed at 1 during message transmission or reception when the HCAN

is in the error active state, the HTxD pin will output 0 continuously while in the error passive

state. To stop continuous 0 output to the CAN bus, disable the HCAN by means of an error

warning interrupt or by setting the HCAN module stop mode through detection of a fixed 1

state by the HxRD pin monitor.

10.Transition to HCAN sleep mode

The HCAN stops (transmission/reception stops) when MCR0 is cleared to 0 immediately after

an HCAN sleep mode transition effected by setting TXPR of the HCAN to 1 and setting

MCR5 to 1. When a transition is made to the HCAN sleep mode by means of the above steps,

a 10-cycle wait should be inserted after the TxPR setting. After an HCAN sleep mode

transition, release the HCAN sleep mode by clearing MCR5 to 0.

11.Message transmission cancellation (TxCR)

If all the following conditions are met when cancellation of a transmission message is

performed by means of TxCR of the HCAN, the TxCR or TxPR bit indicating cancellation is

not cleared even though internal transmission is canceled.

When canceling a message using TxCR, 1 should be written continuously until TxCR or TxPR

becomes 0.

12.TxCR in the bus off state

If TxPR is set before the HCAN goes to the bus off state, and a transition is made to the bus off

state with transmission incomplete, cancellation will be performed even if TxCR is set during

the bus off period, and the message will be transmitted after a transition to the error active

state.

587

Section 16 A/D Converter

16.1 Overview

The H8S/2646 Series incorporates a successive approximation type 10-bit A/D converter that

allows up to twelve analog input channels to be selected.

16.1.1 Features

A/D converter features are listed below.

• 10-bit resolution

• Twelve input channels

• Settable analog conversion voltage range

 Conversion of analog voltages with the reference voltage pin (Vref) as the analog reference

voltage

• High-speed conversion

 Minimum conversion time: 13.3 µs per channel (at 20 MHz operation)

• Choice of single mode or scan mode

 Single mode: Single-channel A/D conversion

 Scan mode: Continuous A/D conversion on 1 to 4 channels

• Four data registers

 Conversion results are held in a 16-bit data register for each channel

• Sample and hold function

• Three kinds of conversion start

 Choice of software or timer conversion start trigger (TPU), or ADTRG pin

• A/D conversion end interrupt generation

 A/D conversion end interrupt (ADI) request can be generated at the end of A/D conversion

• Module stop mode can be set

 As the initial setting, A/D converter operation is halted. Register access is enabled by

exiting module stop mode

588

16.1.2 Block Diagram

Figure 16-1 shows a block diagram of the A/D converter.

Module data bus

Control circuit

Internal data bus

10-bit D/A

Comparator

–

Sample-and-

hold circuit

ø/2

ø/4

ø/8

ADI

interrupt

ø/16

Bus interface

AVCC

Vref

AVSS

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AN8

AN9

AN10

AN11

ADTRG Conversion start

trigger from TPU

Successive approximations

Multiplexer

ADCR

ADCSR

ADDRA

ADDRB

ADDRC

ADDRD

: A/D control register

: A/D control/status register

: A/D data register A

: A/D data register B

: A/D data register C

: A/D data register D

Figure 16-1 Block Diagram of A/D Converter

589

16.1.3 Pin Configuration

Table 16-1 summarizes the input pins used by the A/D converter.

The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. The

Vref pin is the A/D conversion reference voltage pin.

The 12 analog input pins are divided into two channel sets and two groups, with analog input pins

0 to 7 (AN0 to AN7) comprising channel set 0, analog input pins 8 to 11 (AN8 to AN11)

comprising channel set 1, analog input pins 0 to 3 and 8 to 11 (AN0 to AN3, AN8 to AN11)

comprising group 0, and analog input pins 4 to 7 (AN4 to AN7) comprising group 1.

Table 16-1 A/D Converter Pins

Pin Name Symbol I/O Function

Analog power supply pin AVCC Input Analog block power supply

Analog ground pin AVSS Input Analog block ground and reference voltage

Reference voltage pin Vref Input A/D conversion reference voltage

Analog input pin 0 AN0 Input Channel set 0 (CH3 = 0) group 0 analog inputs

Analog input pin 1 AN1 Input

Analog input pin 2 AN2 Input

Analog input pin 3 AN3 Input

Analog input pin 4 AN4 Input Channel set 0 (CH3 = 0) group 1 analog inputs

Analog input pin 5 AN5 Input

Analog input pin 6 AN6 Input

Analog input pin 7 AN7 Input

Analog input pin 8 AN8 Input Channel set 1 (CH3 = 1) group 0 analog inputs

Analog input pin 9 AN9 Input

Analog input pin 10 AN10 Input

Analog input pin 11 AN11 Input

A/D external trigger input

pin ADTRG Input External trigger input for starting A/D

conversion

590

16.1.4 Register Configuration

Table 16-2 summarizes the registers of the A/D converter.

Table 16-2 A/D Converter Registers

Name Abbreviation R/W Initial Value Address*1

A/D data register AH ADDRAH R H'00 H'FF90

A/D data register AL ADDRAL R H'00 H'FF91

A/D data register BH ADDRBH R H'00 H'FF92

A/D data register BL ADDRBL R H'00 H'FF93

A/D data register CH ADDRCH R H'00 H'FF94

A/D data register CL ADDRCL R H'00 H'FF95

A/D data register DH ADDRDH R H'00 H'FF96

A/D data register DL ADDRDL R H'00 H'FF97

A/D control/status register ADCSR R/(W)*2H'00 H'FF98

A/D control register ADCR R/W H'33 H'FF99

Module stop control register A MSTPCRA R/W H'3F H'FDE8

Notes: *1 Lower 16 bits of the address.

*2 Bit 7 can only be written with 0 for flag clearing.

591

16.2 Register Descriptions

16.2.1 A/D Data Registers A to D (ADDRA to ADDRD)

AD9

Bit

Initial value

R/W

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

—

There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of

A/D conversion.

The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected

channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte

(bits 15 to 8) of ADDR, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and

stored. Bits 5 to 0 are always read as 0.

The correspondence between the analog input channels and ADDR registers is shown in

table 16-3.

ADDR can always be read by the CPU. The upper byte can be read directly, but for the lower

byte, data transfer is performed via a temporary register (TEMP). For details, see section 16.3,

Interface to Bus Master.

The ADDR registers are initialized to H'0000 by a reset, and in standby mode or module stop

mode.

Table 16-3 Analog Input Channels and Corresponding ADDR Registers

Analog Input Channel

Channel Set 0 (CH3 = 0) Channel Set 1 (CH3 = 1)

Group 0 Group 1 Group 0 A/D Data Register

AN0 AN4 AN8 ADDRA

AN1 AN5 AN9 ADDRB

AN2 AN6 AN10 ADDRC

AN3 AN7 AN11 ADDRD

592

16.2.2 A/D Control/Status Register (ADCSR)

ADF

R/(W)*

ADIE

R/W

ADST

R/W

SCAN

R/W

CH3

R/W

CH0

R/W

CH2

R/W

CH1

R/W

Bit

Initial value

R/W

Note: * Only 0 can be written to bit 7, to clear this flag.

ADCSR is an 8-bit readable/writable register that controls A/D conversion operations.

ADCSR is initialized to H'00 by a reset, and in hardware standby mode or module stop mode.

Bit 7—A/D End Flag (ADF): Status flag that indicates the end of A/D conversion.

Bit 7

ADF Description

0 [Clearing conditions] (Initial value)

• When 0 is written to the ADF flag after reading ADF = 1

• When the DTC is activated by an ADI interrupt and ADDR is read

1 [Setting conditions]

• Single mode: When A/D conversion ends

• Scan mode: When A/D conversion ends on all specified channels

Bit 6—A/D Interrupt Enable (ADIE): Selects enabling or disabling of interrupt (ADI) requests

at the end of A/D conversion.

Bit 6

ADIE Description

0 A/D conversion end interrupt (ADI) request disabled (Initial value)

1 A/D conversion end interrupt (ADI) request enabled

593

Bit 5—A/D Start (ADST): Selects starting or stopping on A/D conversion. Holds a value of 1

during A/D conversion.

The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external

trigger input pin (ADTRG).

Bit 5

ADST Description

0• A/D conversion stopped (Initial value)

1• Single mode: A/D conversion is started. Cleared to 0 automatically when

conversion on the specified channel ends

• Scan mode: A/D conversion is started. Conversion continues sequentially on the

selected channels until ADST is cleared to 0 by software, a reset, or

a transition to standby mode or module stop mode.

Bit 4—Scan Mode (SCAN): Selects single mode or scan mode as the A/D conversion operating

mode. See section 16.4, Operation, for single mode and scan mode operation. Only set the SCAN

bit while conversion is stopped (ADST = 0).

Bit 4

SCAN Description

0 Single mode (Initial value)

1 Scan mode

Bit 3—Channel Select 3 (CH3): Switches the analog input pins assigned to group 0 or group 1.

Setting CH3 to 1 enables AN8 to AN11 to be used instead of AN0 to AN7.

Bit 3

CH3 Description

0 AN8 to AN11 are group 0 analog input pins

1 AN0 to AN3 are group 0 analog input pins, AN4 to AN7 are group 1 analog input pins

(Initial value)

594

Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): Together with the SCAN bit, these bits select

the analog input channels.

Only set the input channel while conversion is stopped (ADST = 0).

Channel Selection Description

CH3 CH2 CH1 CH0 Single Mode

(SCAN = 0) Scan Mode

(SCAN = 1)

0000 AN0 (Initial value) AN0

1 AN1 AN0, AN1

1 0 AN2 AN0 to AN2

1 AN3 AN0 to AN3

1 0 0 AN4 AN4

1 AN5 AN4, AN5

1 0 AN6 AN4 to AN6

1 AN7 AN4 to AN7

1000 AN8 AN8

1 AN9 AN8, AN9

1 0 AN10 AN8 to AN10

1 AN11 AN8 to AN11

595

16.2.3 A/D Control Register (ADCR)

TRGS1

R/W

TRGS0

R/W

—

CKS1

R/W

—

CKS0

R/W

—

Bit

Initial value

R/W

ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D

conversion operations and sets the A/D conversion time.

ADCR is initialized to H'33 by a reset, and in standby mode or module stop mode.

Bits 7 and 6—Timer Trigger Select 1 and 0 (TRGS1, TRGS0): Select enabling or disabling of

the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0 while conversion

is stopped (ADST = 0).

Bit 7 Bit 6

TRGS1 TRGS0 Description

0 0 A/D conversion start by software is enabled (Initial value)

1 A/D conversion start by TPU conversion start trigger is enabled

1 0 Setting prohibited

1 A/D conversion start by external trigger pin (ADTRG) is enabled

Bits 5, 4, 1, and 0—Reserved: These bits are reserved; they are always read as 1 and cannot be

modified.

Bits 3 and 2—Clock Select 1 and 0 (CKS1, CKS0): These bits select the A/D conversion time.

The conversion time should be changed only when ADST = 0.

Set bits CKS1 and CKS0 to give a conversion time of at least 10 µs.

Bit 3 Bit 2

CKS1 CKS0 Description

0 0 Conversion time = 530 states (max.) (Initial value)

1 Conversion time = 266 states (max.)

1 0 Conversion time = 134 states (max.)

1 Conversion time = 68 states (max.)

596

16.2.4 Module Stop Control Register A (MSTPCRA)

MSTPA7

R/W

MSTPA6

R/W

MSTPA5

R/W

MSTPA4

R/W

MSTPA3

R/W

MSTPA0

R/W

MSTPA2

R/W

MSTPA1

R/W

Bit

Initial value

R/W

MSTPCR is a 8-bit readable/writable register that performs module stop mode control.

When the MSTPA1 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus

cycle and a transition is made to module stop mode. Registers cannot be read or written to in

module stop mode. For details, see section 22.5, Module Stop Mode.

MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized by a

reset and in software standby mode.

Bit 1—Module Stop (MSTPA1): Specifies the A/D converter module stop mode.

Bit 1

MSTPA1 Description

0 A/D converter module stop mode cleared

1 A/D converter module stop mode set (Initial value)

597

16.3 Interface to Bus Master

ADDRA to ADDRD are 16-bit registers, and the data bus to the bus master is 8 bits wide.

Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is

accessed via a temporary register (TEMP).

A data read from ADDR is performed as follows. When the upper byte is read, the upper byte

value is transferred to the CPU and the lower byte value is transferred to TEMP. Next, when the

lower byte is read, the TEMP contents are transferred to the CPU.

When reading ADDR. always read the upper byte before the lower byte. It is possible to read only

the upper byte, but if only the lower byte is read, incorrect data may be obtained.

Figure 16-2 shows the data flow for ADDR access.

Bus master

(H'AA)

ADDRnH

(H'AA) ADDRnL

(H'40)

Lower byte read

ADDRnH

(H'AA) ADDRnL

(H'40)

TEMP

(H'40)

TEMP

(H'40)

(n = A to D)

Module data bus

Bus interface

Upper byte read

Bus master

(H'40) Bus interface

Figure 16-2 ADDR Access Operation (Reading H'AA40)

598

16.4 Operation

The A/D converter operates by successive approximation with 10-bit resolution. It has two

operating modes: single mode and scan mode.

16.4.1 Single Mode (SCAN = 0)

Single mode is selected when A/D conversion is to be performed on a single channel only. A/D

conversion is started when the ADST bit is set to 1, according to the software or external trigger

input. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0

when conversion ends.

On completion of conversion, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an

ADI interrupt request is generated. The ADF flag is cleared by writing 0 after reading ADCSR.

When the operating mode or analog input channel must be changed during analog conversion, to

prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After

making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit

can be set at the same time as the operating mode or input channel is changed.

Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure

16-3 shows a timing diagram for this example.

[1] Single mode is selected (SCAN = 0), input channel AN1 is selected (CH3 = 0, CH2 = 0,

CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started

(ADST = 1).

[2] When A/D conversion is completed, the result is transferred to ADDRB. At the same time the

ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle.

[3] Since ADF = 1 and ADIE = 1, an ADI interrupt is requested.

[4] The A/D interrupt handling routine starts.

[5] The routine reads ADCSR, then writes 0 to the ADF flag.

[6] The routine reads and processes the connection result (ADDRB).

[7] Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1,

A/D conversion starts again and steps [2] to [7] are repeated.

599

ADIE

ADST

ADF

State of channel 0 (AN0)

A/D

conversion

starts

ADDRA

ADDRB

ADDRC

ADDRD

State of channel 1 (AN1)

State of channel 2 (AN2)

State of channel 3 (AN3)

Note:

Vertical arrows ( ) indicate instructions executed by software.

Set

Clear

A/D conversion result 1

A/D conversion

A/D conversion result 2

Read conversion result

Idle

Idle Idle

A/D conversion

Set

Figure 16-3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)

600

16.4.2 Scan Mode (SCAN = 1)

Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the

ADST bit is set to 1 by a software, timer or external trigger input, A/D conversion starts on the

first channel in the group (AN0). When two or more channels are selected, after conversion of the

first channel ends, conversion of the second channel (AN1) starts immediately. A/D conversion

continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion

results are transferred for storage into the ADDR registers corresponding to the channels.

When the operating mode or analog input channel must be changed during analog conversion, to

prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After

making the necessary changes, set the ADST bit to 1 to start A/D conversion again from the first

channel (AN0). The ADST bit can be set at the same time as the operating mode or input channel

is changed.

Typical operations when three channels (AN0 to AN2) are selected in scan mode are described

next. Figure 16-4 shows a timing diagram for this example.

[1] Scan mode is selected (SCAN = 1), channel set 0 is selected (CH3 = 0), scan group 0 is

selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and

A/D conversion is started (ADST = 1).

[2] When A/D conversion of the first channel (AN0) is completed, the result is transferred to

ADDRA. Next, conversion of the second channel (AN1) starts automatically.

[3] Conversion proceeds in the same way through the third channel (AN2).

[4] When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set

to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1 at this

time, an ADI interrupt is requested after A/D conversion ends.

[5] Steps [2] to [4] are repeated as long as the ADST bit remains set to 1. When the ADST bit is

cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion

starts again from the first channel (AN0).

601

ADST

ADF

ADDRA

ADDRB

ADDRC

ADDRD

State of channel 0 (AN0)

State of channel 1 (AN1)

State of channel 2 (AN2)

State of channel 3 (AN3)

Set*1 Clear*1

Idle

Notes: *1 Vertical arrows ( ) indicate instructions executed by software.

*2 Data currently being converted is ignored.

Clear*1

Idle

A/D conversion time

Idle

Continuous A/D conversion execution

A/D conversion 1

Idle Idle

Idle

Transfer

A/D conversion 3

A/D conversion 2

A/D conversion 4

A/D conversion result 1

A/D conversion result 2

A/D conversion result 3

A/D conversion result 4

A/D conversion 5

Figure 16-4 Example of A/D Converter Operation

(Scan Mode, 3 Channels AN0 to AN2 Selected)

602

16.4.3 Input Sampling and A/D Conversion Time

The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog

input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 16-5 shows the A/D

conversion timing. Table 16-4 indicates the A/D conversion time.

As indicated in figure 16-5, the A/D conversion time includes tD and the input sampling time. The

length of tD varies depending on the timing of the write access to ADCSR. The total conversion

time therefore varies within the ranges indicated in table 16-4.

In scan mode, the values given in table 16-4 apply to the first conversion time. The values given

in table 16-5 apply to the second and subsequent conversions. In both cases, set bits CKS1 and

CKS0 in ADCR to give a conversion time of at least 10 µs.

(1)

(2)

tDtSPL tCONV

Input sampling

timing

ADF

Address

Write signal

Legend

(1) : ADCSR write cycle

(2) : ADCSR address

tD: A/D conversion start delay

tSPL : Input sampling time

tCONV : A/D conversion time

Figure 16-5 A/D Conversion Timing

603

Table 16-4 A/D Conversion Time (Single Mode)

CKS1 = 0 CKS1 = 0

CKS0 = 0 CKS0 = 1 CKS0 = 0 CKS0 = 1

Item Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max

A/D conversion start delay tD18 —33 10 —17 6 —94—5

Input sampling time tSPL —127 ——63 ——31 ——15 —

A/D conversion time tCONV 55 —530 259 —266 131 —134 67 —68

Note: Values in the table are the number of states.

Table 16-5 A/D Conversion Time (Scan Mode)

CKS1 CKS0 Conversion Time (State)

0 0 512 (Fixed)

1 256 (Fixed)

1 0 128 (Fixed)

1 64 (Fixed)

16.4.4 External Trigger Input Timing

A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in

ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets

the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan

modes, are the same as if the ADST bit has been set to 1 by software. Figure 16-6 shows the

timing.

ADTRG

Internal trigger signal

ADST

A/D conversion

Figure 16-6 External Trigger Input Timing

604

16.5 Interrupts

The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion.

ADI interrupt requests can be enabled or disabled by means of the ADIE bit in ADCSR.

The DTC can be activated by an ADI interrupt. Having the converted data read by the DTC in

response to an ADI interrupt enables continuous conversion to be achieved without imposing a

load on software.

The A/D converter interrupt source is shown in table 16-6.

Table 16-6 A/D Converter Interrupt Source

Interrupt Source Description DTC Activation

ADI Interrupt due to end of conversion Possible

16.6 Usage Notes

The following points should be noted when using the A/D converter.

Setting Range of Analog Power Supply and Other Pins:

(1) Analog input voltage range

The voltage applied to analog input pin ANn during A/D conversion should be in the range

AVSS ANn Vref .

(2) Relation between AVCC, AVSS and VCC, VSS

As the relationship between AVSS and VSS, set AVSS = VSS. If the A/D converter is not used,

set AVCC = VCC, and do not leave the AVCC and AVSS pins open or no account.

(3) Vref input range

The analog reference voltage input at the Vref pin set in the range Vref AV CC.

If conditions (1), (2), and (3) above are not met, the reliability of the device may be adversely

affected.

Notes on Board Design: In board design, digital circuitry and analog circuitry should be as

mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit

signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so

may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D

conversion values.

605

Also, digital circuitry must be isolated from the analog input signals (AN0 to AN11), analog

reference power supply (Vref), and analog power supply (AVCC) by the analog ground (AVSS).

Also, the analog ground (AVSS) should be connected at one point to a stable digital ground (VSS)

on the board.

Notes on Noise Countermeasures: A protection circuit connected to prevent damage due to an

abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN11) and analog

reference power supply (Vref) should be connected between AVCC and AVSS as shown in

figure 16-7.

Also, the bypass capacitors connected to AVCC and Vref and the filter capacitor connected to AN0

to AN11 must be connected to AVSS.

If a filter capacitor is connected as shown in figure 16-7, the input currents at the analog input pins

(AN0 to AN11) are averaged, and so an error may arise. Also, when A/D conversion is performed

frequently, as in scan mode, if the current charged and discharged by the capacitance of the

sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance

(Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required

when deciding the circuit constants.

AVCC

*1*1

Vref

AN0 to AN11

AVSS

Notes: Values are reference values.

*2 Rin: Input impedance

Rin*2100 Ω

0.1 µF

0.01 µF10 µF

Figure 16-7 Example of Analog Input Protection Circuit

606

Table 16-7 Analog Pin Specifications

Item Min Max Unit

Analog input capacitance —20 pF

Permissible signal source impedance —5k

20 pF

To A/D converterAN0 to AN11 10 kΩ

Note: Values are reference values.

Figure 16-8 Analog Input Pin Equivalent Circuit

A/D Conversion Precision Definitions: H8S/2646 Series A/D conversion precision definitions

are given below.

• Resolution

The number of A/D converter digital output codes

• Offset error

The deviation of the analog input voltage value from the ideal A/D conversion characteristic

when the digital output changes from the minimum voltage value B'0000000000 (H'00) to

B'0000000001 (H'01) (see figure 16-10).

• Full-scale error

The deviation of the analog input voltage value from the ideal A/D conversion characteristic

when the digital output changes from B'1111111110 (H'3E) to B'1111111111 (H'3F) (see

figure 16-10).

• Quantization error

The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 16-9).

• Nonlinearity error

The error with respect to the ideal A/D conversion characteristic between the zero voltage and

the full-scale voltage. Does not include the offset error, full-scale error, or quantization error.

• Absolute precision

The deviation between the digital value and the analog input value. Includes the offset error,

full-scale error, quantization error, and nonlinearity error.

607

111

110

101

100

011

010

001

000 FS

Quantization error

Digital output

Ideal A/D conversion

characteristic

Analog

input voltage

1024 2

1024 1022

1024 1023

1024

Figure 16-9 A/D Conversion Precision Definitions (1)

608

Offset error

Nonlinearity

error

Actual A/D conversion

characteristic

Analog

input voltage

Digital output

Ideal A/D conversion

characteristic

Full-scale error

Figure 16-10 A/D Conversion Precision Definitions (2)

Permissible Signal Source Impedance: H8S/2646 Series analog input is designed so that

conversion precision is guaranteed for an input signal for which the signal source impedance is 10

k or less. This specification is provided to enable the A/D converterÕs sample-and-hold circuit

input capacitance to be charged within the sampling time; if the sensor output impedance exceeds

10 k, charging may be insufficient and it may not be possible to guarantee the A/D conversion

precision.

However, if a large capacitance is provided externally, the input load will essentially comprise

only the internal input resistance of 10 k, and the signal source impedance is ignored.

However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an

analog signal with a large differential coefficient (e.g., 5 mV/µs or greater).

When converting a high-speed analog signal, a low-impedance buffer should be inserted.

609

Influences on Absolute Precision: Adding capacitance results in coupling with GND, and

therefore noise in GND may adversely affect absolute precision. Be sure to make the connection

to an electrically stable GND such as AVSS.

Care is also required to insure that filter circuits do not communicate with digital signals on the

mounting board, so acting as antennas.

A/D converter

equivalent circuit

H8S/2646 Series

20 pF

Cin =

15 pF

10 kΩ

to 5 kΩ

Low-pass

filter

C to 0.1 µF

Sensor output

impedance

Sensor input

Figure 16-11 Example of Analog Input Circuit

610

611

Section 17 Motor Control PWM Timer

17.1 Overview

The H8S/2646 Series has an on-chip motor control PWM (pulse width modulator) with a

maximum capability of 16 pulse outputs.

17.1.1 Features

Features of the motor control PWM are given below.

• Maximum of 16 pulse outputs

 Two 10-bit PWM channels, each with eight outputs.

 Each channel is provided with a 10-bit counter (PWCNT) and cycle register (PWCYR).

 Duty and output polarity can be set for each output.

• Buffered duty registers

 Duty registers (PWDTR) are provided with buffer registers (PWBFR), with data transferred

automatically every cycle.

 Channel 1 has four duty registers and four buffer registers.

 Channel 2 has eight duty registers and four buffer registers.

• 0% to 100% duty

 A duty cycle of 0% to 100% can be set by means of a duty register setting.

• Five operating clocks

 There is a choice of five operating clocks (ø, ø/2, ø/4, ø/8, ø/16).

• On-chip output driver

• High-speed access via internal 16-bit-bus

 High-speed access is possible via a 16-bit bus interface.

• Two interrupt sources

 An interrupt can be requested independently for each channel by a cycle register compare

match.

• Automatic transfer of register data

 Block transfer and one-word data transfer are possible by activating the data transfer

controller (DTC).

612

• Module stop mode

 As the initial setting, PWM operation is halted. Register access is enabled by clearing

module stop mode.

17.1.2 Block Diagram

Figure 17-1 shows a block diagram of PWM channel 1.

PWCNT1

PWCYR1

PWDTR1A

12 9 0

PWPR1

P/N

P/N PWM1A

PWM1B

PWBFR1A

12 9 0

PWDTR1C P/N

P/N PWM1C

PWM1D

PWBFR1C

PWDTR1E P/N

P/N PWM1E

PWM1F

PWBFR1E

PWDTR1G P/N

P/N PWM1G

PWM1H

PWBFR1G

PWCR1 PWOCR1

Compare

match

Interrupt

request

Internal

data bus

Bus interface

Port

control

Legend:

PWCR1: PWM control register 1

PWOCR1: PWM output control register 1

PWPR1: PWM polarity register 1

PWCNT1: PWM counter 1

PWCYR1: PWM cycle register 1

PWDTR1A, 1C, 1E, 1G: PWM duty registers 1A, 1C, 1E, 1G

PWBFR1A, 1C, 1E, 1G: PWM buffer registers 1A, 1C, 1E, 1G

ø, ø/2, ø/4, ø/8, ø/16

Figure 17-1 Block Diagram of PWM Channel 1

613

Figure 17-2 shows a block diagram of PWM channel 2.

PWBFR2A

12 9 0

PWBFR2B

PWBFR2C

PWBFR2D

PWCNT2

PWCYR2

PWOCR2

PWPR2

PWDTR2A

PWDTR2B

PWDTR2C

PWDTR2D

PWDTR2E

PWDTR2F

PWDTR2G

PWDTR2H

P/N

PWCR2

P/N

PWM2A

PWM2B

PWM2C

PWM2D

PWM2E

PWM2F

PWM2G

PWM2H

Compare match

ø, ø/2, ø/4, ø/8, ø/16

Legend:

PWCR2: PWM control register 2

PWOCR2: PWM output control register 2

PWPR2: PWM polarity register 2

PWCNT2: PWM counter 2

PWCYR2: PWM cycle register 2

PWDTR2A to PWDTR2H: PWM duty registers 2A to 2H

PWBFR2A, 2B, 2C, 2D: PWM buffer registers 2A, 2B, 2C, 2D

Internal

data bus

Interrupt

request

Bus interface

Port

control

Figure 17-2 Block Diagram of PWM Channel 2

614

17.1.3 Pin Configuration

Table 17-1 shows the PWM pin configuration.

Table 17-1 PWM Pin Configuration

Name Abbrev. I/O Function

PWM output pin 1A PWM1A Output Channel 1A PWM output

PWM output pin 1B PWM1B Output Channel 1B PWM output

PWM output pin 1C PWM1C Output Channel 1C PWM output

PWM output pin 1D PWM1D Output Channel 1D PWM output

PWM output pin 1E PWM1E Output Channel 1E PWM output

PWM output pin 1F PWM1F Output Channel 1F PWM output

PWM output pin 1G PWM1G Output Channel 1G PWM output

PWM output pin 1H PWM1H Output Channel 1H PWM output

PWM output pin 2A PWM2A Output Channel 2A PWM output

PWM output pin 2B PWM2B Output Channel 2B PWM output

PWM output pin 2C PWM2C Output Channel 2C PWM output

PWM output pin 2D PWM2D Output Channel 2D PWM output

PWM output pin 2E PWM2E Output Channel 2E PWM output

PWM output pin 2F PWM2F Output Channel 2F PWM output

PWM output pin 2G PWM2G Output Channel 2G PWM output

PWM output pin 2H PWM2H Output Channel 2H PWM output

615

17.1.4 Register Configuration

Table 17-2 shows the register configuration of the PWM.

Table 17-2 PWM Registers

Channel Name Abbrev. R/W Initial Value Address*1

1 PWM control register 1 PWCR1 R/W H'C0 H'FC00

PWM output control register 1 PWOCR1 R/W H'00 H'FC02

PWM polarity register 1 PWPR1 R/W H'00 H'FC04

PWM cycle register 1 PWCYR1 R/W H'FFFF H'FC06

PWM buffer register 1A PWBFR1A R/W H'EC00 H'FC08

PWM buffer register 1C PWBFR1C R/W H'EC00 H'FC0A

PWM buffer register 1E PWBFR1E R/W H'EC00 H'FC0C

PWM buffer register 1G PWBFR1G R/W H'EC00 H'FC0E

2 PWM control register 2 PWCR2 R/W H'C0 H'FC10

PWM output control register 2 PWOCR2 R/W H'00 H'FC12

PWM polarity register 2 PWPR2 R/W H'00 H'FC14

PWM cycle register 2 PWCYR2 R/W H'FFFF H'FC16

PWM buffer register 2A PWBFR2A R/W H'EC00 H'FC18

PWM buffer register 2B PWBFR2B R/W H'EC00 H'FC1A

PWM buffer register 2C PWBFR2C R/W H'EC00 H'FC1C

PWM buffer register 2D PWBFR2D R/W H'EC00 H'FC1E

All Module stop control register D MSTPCRD R/W B'11****** H'FC60

Note: *1 Lower 16 bits of the address.

616

17.2 Register Descriptions

17.2.1 PWM Control Registers 1 and 2 (PWCR1, PWCR2)

Bit 76543210

——IE CMF CST CKS2 CKS1 CKS0

Initial value 1 1 0 0 0 0 0 0

Read/Write ——R/W R/(W)*R/W R/W R/W R/W

Note: *Only 0 can be written, to clear the flag.

PWCR is an 8-bit read/write register that performs interrupt enabling, starting/stopping, and

counter (PWCNT) clock selection. It also contains a flag that indicates a compare match with the

cycle register (PWCYR). PWCR1 is the channel 1 register, and PWCR2 is the channel 2 register.

PWCR is initialized to H'C0 upon reset, and in standby mode, watch mode, subactive mode,

subsleep mode, and module stop mode.

Bits 7 and 6—Reserved: Bits 7 and 6 are reserved; they are always read as 1 and cannot be

modified.

Bit 5—Interrupt Enable (IE): Bit 5 selects enabling or disabling of an interrupt in the event of a

compare match with the PWCYR register for the corresponding channel.

Bit 5: IE Description

0 Interrupt disabled (Initial value)

1 Interrupt enabled

Bit 4—Compare Match Flag (CMF): Bit 4 indicates the occurrence of a compare match with the

PWCYR register for the corresponding channel.

Bit 4: CMF Description

0 [Clearing conditions] (Initial value)

• When 0 is written to CMF after reading CMF = 1

• When the DTC is activated by a compare match interrupt, and the DISEL bit in

the DTC’s MRB register is 0

1 [Setting condition]

When PWCNT = PWCYR

617

Bit 3—Counter Start (CST): Bit 3 selects starting or stopping of the PWCNT counter for the

corresponding channel.

Bit 3: CST Description

0 PWCNT is stopped (Initial value)

1 PWCNT is started

Bits 2 to 0—Clock Select (CKS): Bits 2 to 0 select the clock for the PWCNT counter in the

corresponding channel.

Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Description

0 0 0 Internal clock: counts on ø/1 (Initial value)

1 Internal clock: counts on ø/2

1 0 Internal clock: counts on ø/4

1 Internal clock: counts on ø/8

1**Internal clock: counts on ø/16

*: Don’t care

17.2.2 PWM Output Control Registers 1 and 2 (PWOCR1, PWOCR2)

PWOCR1

Bit 76543210

OE1H OE1G OE1F OE1E OE1D OE1C OE1B OE1A

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

PWOCR2

Bit 76543210

OE2H OE2G OE2F OE2E OE2D OE2C OE2B OE2A

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

PWOCR is an 8-bit read/write register that enables or disables PWM output. PWOCR1 controls

outputs PWM1H to PWM1A, and PWOCR2 controls outputs PWM2H to PWM2A.

PWOCR is initialized to H'00 upon reset, and in standby mode, watch mode, subactive mode,

subsleep mode, and module stop mode.

618

Bits 7 to 0—Output Enable (OE): Each of these bits enables or disables the corresponding PWM

output.

Bits 7 to 0:

OE Description

0 PWM output is disabled (Initial value)

1 PWM output is enabled

17.2.3 PWM Polarity Registers 1 and 2 (PWPR1, PWPR2)

PWPR1

Bit 76543210

OPS1H OPS1G OPS1F OPS1E OPS1D OPS1C OPS1B OPS1A

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

PWPR2

Bit 76543210

OPS2H OPS2G OPS2F OPS2E OPS2D OPS2C OPS2B OPS2A

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

PWPR is an 8-bit read/write register that selects the PWM output polarity. PWPR1 controls

outputs PWM1H to PWM1A, and PWPR2 controls outputs PWM2H to PWM2A.

PWPR is initialized to H'00 upon reset, and in standby mode, watch mode, subactive mode,

subsleep mode, and module stop mode.

Bits 7 to 0—Output Polarity Select (OPS): Each of these bits selects the polarity of the

corresponding PWM output.

Bits 7 to 0:

OPS Description

0 PWM direct output (Initial value)

1 PWM inverse output

619

17.2.4 PWM Counters 1 and 2 (PWCNT1, PWCNT2)

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

——————

Initial value 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0

Read/Write ————————————————

PWCNT is a 10-bit up-counter incremented by the input clock. The input clock is selected by

clock select bits 2 to 0 (CKS2 to CKS0) in PWCR.

PWCNT1 is used as the channel 1 time base, and PWCNT2 as the channel 2 time base.

PWCNT is initialized to H'FC00 when the counter start bit (CST) in PWCR is cleared to 0, and

also upon reset and in standby mode, watch mode, subactive mode, subsleep mode, and module

stop mode.

17.2.5 PWM Cycle Registers 1 and 2 (PWCYR1, PWCYR2)

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

——————

Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Read/Write ——————R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

PWCYR is a 16-bit read/write register that sets the PWM conversion cycle. When a PWCYR

compare match occurs, PWCNT is cleared and data is transferred from the buffer register

(PWBFR) to the duty register (PWDTR). PWCYR1 is used for the channel 1 conversion cycle

setting, and PWCYR2 for the channel 2 conversion cycle setting.

PWCYR should be written to only while PWCNT is stopped. A value of H'FC00 must not be set.

PWCYR is initialized to H'FFFF upon reset, and in standby mode, watch mode, subactive mode,

subsleep mode, and module stop mode.

01 01

N–1

PWCNT

(lower 10 bits)

PWCYR

(lower 10 bits)

N–2

Compare matchCompare match

Figure 17-3 Cycle Register Compare Match

620

17.2.6 PWM Duty Registers 1A, 1C, 1E, 1G (PWDTR1A, 1C, 1E, 1G)

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

———OTS ——DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0

Initial value 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0

Read/Write ————————————————

There are four PWDTR1x registers (PWDTR1A, 1C, 1E, 1G). PWDTR1A is used for outputs

PWM1A and PWM1B, PWDTR1C for outputs PWM1C and PWM1D, PWDTR1E for outputs

PWM1E and PWM1F, and PWDTR1G for outputs PWM1G and PWM1H.

PWDTR1 cannot be read or written to directly. When a PWCYR1 compare match occurs, data is

transferred from buffer register 1 (PWBFR1) to PWDTR1.

PWDTR1x is initialized to H'EC00 when the counter start bit (CST) in PWCR1 is cleared to 0,

and also upon reset and in standby mode, watch mode, subactive mode, subsleep mode, and

module stop mode.

Bits 15 to 13—Reserved: These bits cannot be read from or written to.

Bit 12—Output Terminal Select (OTS): Bit 12 selects the pin used for PWM output according

to the value in bit 12 in the buffer register that is transferred by a PWCYR1 compare match.

Unselected pins output a low level (or a high level when the corresponding bit in PWPR1 is set to

1).

PWDTR1A 0 PWM1A output selected (Initial value)

1 PWM1B output selected

PWDTR1C 0 PWM1C output selected (Initial value)

1 PWM1D output selected

PWDTR1E 0 PWM1E output selected (Initial value)

1 PWM1F output selected

PWDTR1G 0 PWM1G output selected (Initial value)

1 PWM1H output selected

Bits 11 and 10—Reserved: These bits cannot be read from or written to.

Bits 9 to 0—Duty (DT): Bits 9 to 0 set the PWM output duty according to the values in bits 9 to 0

in the buffer register that is transferred by a PWCYR1 compare match. A high level (or a low level

when the corresponding bit in PWPR1 is set to 1) is output from the time PWCNT1 is cleared by a

PWCYR1 compare match until a PWDTR1 compare match occurs. When all the bits are 0, there

621

is no high-level output period (no low-level output period when the corresponding bit in PWPR1

is set to 1).

PWCNT1

(lower 10 bits)

PWCYR1

(lower 10 bits)

PWDTR1

(lower 10 bits)

PWM output on

selected pin

PWM output on

unselected pin

Compare match

M–2M–1M N–10

Figure 17-4 Duty Register Compare Match (OPS = 0 in PWPR1)

01 N–10

N–2

PWCNT1

(lower 10 bits)

PWCYR1

(lower 10 bits)

PWDTR1

(lower 10 bits)

PWM output

(M = 0)

PWM output

(0 < M < N)

PWM output

(N ≤ M)

Figure 17-5 Differences in PWM Output According to Duty Register Set Value

(OPS = 0 in PWPR1)

622

17.2.7 PWM Buffer Registers 1A, 1C, 1E, 1G (PWBFR1A, 1C, 1E, 1G)

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

———OTS ——DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0

Initial value 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0

Read/Write ———R/W ——R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

There are four 16-bit read/write PWBFR1 registers (PWBFR1A, 1C, 1E, 1G). When a PWCYR1

compare match occurs, data is transferred from PWBFR1A to PWDTR1A, from PWBFR1C to

PWDTR1C, from PWBFR1E to PWDTR1E, and from PWBFR1G to PWDTR1G.

PWBFR1 is initialized to H'EC00 upon reset, and in standby mode, watch mode, subactive mode,

subsleep mode, and module stop mode.

Bits 15 to 13—Reserved: These bits are always read as 1 and cannot be modified.

Bit 12—Output Terminal Select (OTS): Bit 12 is the data transferred to bit 12 of PWDTR1.

Bits 11 and 10—Reserved: These bits are always read as 1 and cannot be modified.

Bits 9 to 0—Duty (DT): Bits 9 to 0 comprise the data transferred to bits 9 to 0 in PWDTR1.

17.2.8 PWM Duty Registers 2A to 2H (PWDTR2A to PWDTR2H)

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

——————DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0

Initial value 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0

Read/Write ————————————————

There are eight PWDTR2 registers (PWDTR2A to PWDTR2H). PWDTR2A is used for output

PWM2A, PWDTR2B for output PWM2B, PWDTR2C for output PWM2C, PWDTR2D for output

PWM2D, PWDTR2E for output PWM2E, PWDTR2F for output PWM2F, PWDTR2G for output

PWM2G, and PWDTR2H for output PWM2H.

PWDTR2 cannot be read or written to directly. When a PWCYR2 compare match occurs, data is

transferred from buffer register 2 (PWBFR2) to PWDTR2.

PWDTR2 is initialized to H'EC00 when the counter start bit (CST) in PWCR2 is cleared to 0, and

also upon reset and in standby mode, watch mode, subactive mode, subsleep mode, and module

stop mode.

623

Bits 15 to 10—Reserved: These bits cannot be read from or written to.

Bits 9 to 0—Duty (DT): Bits 9 to 0 set the PWM output duty according to the values in bits 9 to 0

in the buffer register that is transferred by a PWCYR2 compare match. A high level (or a low level

when the corresponding bit in PWPR2 is set to 1) is output from the time PWCNT2 is cleared by a

PWCYR2 compare match until a PWDTR2 compare match occurs. When all the bits are 0, there

is no high-level output period (no low-level output period when the corresponding bit in PWPR2

is set to 1).

PWCNT2

(lower 10 bits)

PWCYR2

(lower 10 bits)

PWDTR2

(lower 10 bits)

PWM output

Compare match

M–2M–1M N–10

Figure 17-6 Duty Register Compare Match (OPS = 0 in PWPR2)

01 N–10

N–2

PWCNT2

(lower 10 bits)

PWCYR2

(lower 10 bits)

PWDTR2

(lower 10 bits)

PWM output

(M = 0)

PWM output

(0 < M < N)

PWM output

(N ≤ M)

Figure 17-7 Differences in PWM Output According to Duty Register Set Value

(OPS = 0 in PWPR2)

624

17.2.9 PWM Buffer Registers 2A to 2D (PWBFR2A to PWBFR2D)

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

———TDS ——DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0

Initial value 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0

Read/Write ———R/W ——R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

There are four 16-bit read/write PWBFR2 registers (PWBFR2A to PWBFR2D). When a

PWCYR2 compare match occurs, data is transferred from PWBFR2A to PWDTR2A or

PWDTR2E, from PWBFR2B to PWDTR2B or PWDTR2F, from PWBFR2C to PWDTR2C or

PWDTR2G, and from PWBFR2D to PWDTR2D or PWDTR2H. The transfer destination is

determined by the value of the TDS bit.

PWBFR2 is initialized to H'EC00 upon reset, and in standby mode, watch mode, subactive mode,

subsleep mode, and module stop mode.

Bits 15 to 13—Reserved: These bits are always read as 1 and cannot be modified.

Bit 12—Transfer Destination Select (TDS): Bit 12 selects the PWDTR2 register to which data is

to be transferred.

PWBFR2A 0 PWDTR2A selected (Initial value)

1 PWDTR2E selected

PWBFR2B 0 PWDTR2B selected (Initial value)

1 PWDTR2F selected

PWBFR2C 0 PWDTR2C selected (Initial value)

1 PWDTR2G selected

PWBFR2D 0 PWDTR2D selected (Initial value)

1 PWDTR2H selected

Bits 11 and 10—Reserved: These bits are always read as 1 and cannot be modified.

Bits 9 to 0—Duty (DT): Bits 9 to 0 comprise the data transferred to bits 9 to 0 in PWDTR2.

625

17.2.10 Module Stop Control Register D (MSTPCRD)

Bit 76543210

MSTPD7 MSTPD6 ——————

Initial value 1 1 undefined undefinedundefined undefinedundefined undefined

Read/Write R/W R/W ——————

MSTPCRD is an 8-bit read/write register that performs module stop mode control.

When the MSTPD7 bit is set to 1, PWM timer operation is stopped at the end of the bus cycle, and

module stop mode is entered. For details, see section 22.5, Module Stop Mode.

MSTPCRD is initialized by a reset and in hardware standby mode. It is not initialized by a manual

reset or in software standby mode.

Bit 7—Module Stop (MSTPD7): Bit 7 specifies the PWM module stop mode.

Bit 7: MSTPD7 Description

0 PWM module stop mode is cleared

1 PWM module stop mode is set (Initial value)

626

17.3 Bus Master Interface

17.3.1 16-Bit Data Registers

PWCYR1/2, PWBFR1A/C/E/G, and PWBFR2A/B/C/D are 16-bit registers. These registers are

linked to the bus master by a 16-bit data bus, and can be read or written in 16-bit units. They

cannot be read by 8-bit access; 16-bit access must always be used.

PWCYR1

Bus

master

Internal data bus

Bus

interface Module

data bus

Figure 17-8 16-Bit Register Access Operation (Bus Master ↔↔

↔↔ PWCYR1 (16 Bits))

17.3.2 8-Bit Data Registers

PWCR1/2, PWOCR1/2, and PWPR1/2 are 8-bit registers that can be read and written to in 8-bit

units. These registers are linked to the bus master by a 16-bit data bus, and can be read or written

by 16-bit access; in this case, the lower 8 bits will always be read as H'FF.

PWCR1

Bus

master

Internal data bus

Bus

interface Module

data bus

Figure 17-9 8-Bit Register Access Operation (Bus Master ↔↔

↔↔ PWCR1 (Upper 8 Bits))

627

17.4 Operation

17.4.1 PWM Channel 1 Operation

PWM waveforms are output from pins PWM1A to PWM1H as shown in figure 17-10.

Initial Settings: Set the PWM output polarity in PWPR1; enable the pins for PWM output with

PWOCR1; select the clock to be input to PWCNT1 with bits CKS2 to CKS0 in PWCR1; set the

PWM conversion cycle in PWCYR1; and set the first frame of data in PWBFR1A, PWBFR1C,

PWBFR1E, and PWBFR1G.

Activation: When the CST bit in PWCR1 is set to 1, a compare match between PWCNT1 and

PWCYR1 is generated. Data is transferred from PWBFR1A to PWDTR1A, from PWBFR1C to

PWDTR1C, from PWBFR1E to PWDTR1E, and from PWBFR1G to PWDTR1G. PWCNT1

starts counting up. At the same time the CMF bit in PWCR1 is set, so that, if the IE bit in PWCR1

has been set, an interrupt can be requested or the DTC can be activated.

Waveform Output: The PWM outputs selected by the OTS bits in PWDTR1A/C/E/G go high

when a compare match occurs between PWCNT1 and PWCYR1. The PWM outputs not selected

by the OTS bits are low. When a compare match occurs between PWCNT1 and

PWDTR1A/C/E/G, the corresponding PWM output goes low. If the corresponding bit in PWPR1

is set to 1, the output is inverted.

PWBFR1A

PWCYR1

PWM1A

PWDTR1A

PWM1B

OTS (PWDTR1A) = 1OTS (PWDTR1A) = 0OTS (PWDTR1A) = 1OTS (PWDTR1A) = 0

Figure 17-10 PWM Channel 1 Operation

Next Frame: When a compare match occurs between PWCNT1 and PWCYR1, data is transferred

from PWBFR1A to PWDTR1A, from PWBFR1C to PWDTR1C, from PWBFR1E to PWDTR1E,

and from PWBFR1G to PWDTR1G. PWCNT1 is reset and starts counting up from H'000. The

CMF bit in PWCR1 is set, and if the IE bit in PWCR1 has been set, an interrupt can be requested

or the DTC can be activated.

628

Stopping: When the CST bit in PWCR1 is cleared to 0, PWCNT1 is reset and stops. All PWM

outputs go low (or high if the corresponding bit in PWPR1 is set to 1).

17.4.2 PWM Channel 2 Operation

PWM waveforms are output from pins PWM2A to PWM2H as shown in figure 17-11.

Initial Settings: Set the PWM output polarity in PWPR2; enable the pins for PWM output with

PWOCR2; select the clock to be input to PWCNT2 with bits CKS2 to CKS0 in PWCR2; set the

PWM conversion cycle in PWCYR2; and set the first frame of data in PWBFR2A, PWBFR2B,

PWBFR2C, and PWBFR2D.

Activation: When the CST bit in PWCR2 is set to 1, a compare match between PWCNT2 and

PWCYR2 is generated. Data is transferred from PWBFR2A to PWDTR2A or PWDTR2E, from

PWBFR2B to PWDTR2B or PWDTR2F, from PWBFR2C to PWDTR2C or PWDTR2G, and

from PWBFR2D to PWDTR2D or PWDTR2H, according to the value of the TDS bit. PWCNT2

starts counting up. At the same time the CMF bit in PWCR2 is set, so that, if the IE bit in PWCR2

has been set, an interrupt can be requested or the DTC can be activated.

Waveform Output: The PWM outputs go high when a compare match occurs between PWCNT2

and PWCYR2. When a compare match occurs between PWCNT2 and PWDTR2A-H, the

corresponding PWM output goes low. If the corresponding bit in PWPR2 is set to 1, the output is

inverted.

TDS (PWBFR2A) = 0 TDS (PWBFR2A) = 1 TDS (PWBFR2A) = 0

PWBFR2A

PWCYR2

PWM2A

PWDTR2A

PWM2E

PWDTR2E

Figure 17-11 PWM Channel 2 Operation

Next Frame: When a compare match occurs between PWCNT2 and PWCYR2, data is transferred

from PWBFR2A to PWDTR2A or PWDTR2E, from PWBFR2B to PWDTR2B or PWDTR2F,

from PWBFR2C to PWDTR2C or PWDTR2G, and from PWBFR2D to PWDTR2D or

PWDTR2H, according to the value of the TDS bit. PWCNT2 is reset and starts counting up from

629

H'000. The CMF bit in PWCR2 is set, and if the IE bit in PWCR2 has been set, an interrupt can be

requested or the DTC can be activated.

Stopping: When the CST bit in PWCR2 is cleared to 0, PWCNT2 is reset and stops. PWDTR2A

to PWDTR2H are reset. All PWM outputs go low (or high if the corresponding bit in PWPR2 is

set to 1).

17.5 Usage Note

Contention between Buffer Register Write and Compare Match

If a PWBFR write is performed in the state immediately after a cycle register compare match, the

buffer register and duty register are overwritten. PWM output changed by the cycle register

compare match is not changed in the overwrite of the duty register due to contention. This may

result in unanticipated duty output. In the case of channel 2, the duty register used as the transfer

destination is selected by the TDS bit of the buffer register when an overwrite of the duty register

occurs due to contention. This can also result in an unintended overwrite of the duty register.

Buffer register rewriting must be completed before automatic transfer by the DTC (data transfer

controller), exception handling due to a compare match interrupt, or the occurrence of a cycle

T1 Tw Tw T2

Address

Write signal

PWCNT

(lower 10 bits)

PWBFR

PWDTR

PWM output

CMF

Buffer register address

Compare match

Figure 17-12 PWM Channel 1 Operation

630

631

Section 18 LCD Controller/Driver

18.1 Overview

The H8S/2646 Series has an on-chip segment type LCD control circuit, LCD driver, and power

supply circuit, enabling it to directly drive an LCD panel.

18.1.1 Features

Features of the LCD controller/driver are given below.

• Display capacity

Internal Driver

Duty Cycle H8S/2646, H8S/2646R,

H8S/2645 H8S/2648, H8S/2648R,

H8S/2647

Static 24 SEG 40 SEG

1/2 24 SEG 40 SEG

1/3 24 SEG 40 SEG

1/4 24 SEG 40 SEG

• LCD RAM capacity

 8 bits × 20 bytes (160 bits)

 Byte or word access to LCD RAM

• The segment output pins can be used as ports in groups of four.

• Common output pins not used because of the duty cycle can be used for common double-

buffering (parallel connection).

 With 1/2 duty, parallel connection of COM1 to COM2, and of COM3 to COM4, can be

used

 In static mode, parallel connection of COM1 to COM2, COM3, and COM4 can be used

• Choice of 11 frame frequencies

• A or B waveform selectable by software

• Built-in power supply split-resistance

• Display possible in operating modes other than standby mode and module stop mode

632

• Module stop mode

 As the initial setting, LCD operation is halted. Access to registers and LCD RAM is

enabled by clearing module stop mode.

18.1.2 Block Diagram

Figure 18-1 shows a block diagram of the LCD controller/driver.

ø/8 to ø/1024

SUB

CL2

CL1

SEGn, DO

LPCR

LCR

LCR2

Display timing generator

LCD RAM

20 bytes

Internal data bus

24-bit

shift

40-bit

shift

LCD drive

power supply

Segment

driver

Common

data latch Common

driver

COM1

COM4

SEG24

SEG23

SEG22

SEG21

SEG20

SEG1

Legend:

LPCR: LCD port control register

LCR: LCD control register

LCR2: LCD control register 2

Notes: *1 In the H8S/2646, H8S/2646R, and H8S/2645.

*2 In the H8S/2648, H8S/2648R, and H8S/2647.

LPV

H8S/2646R*

SEG40

SEG39

SEG38

SEG37

SEG36

SEG1

H8S/2648R*

Figure 18-1 Block Diagram of LCD Controller/Driver

633

18.1.3 Pin Configuration

Table 18-1 shows the LCD controller/driver pin configuration.

Table 18-1 Pin Configuration

Name Abbreviation I/O Function

Segment output

pins SEG24 to SEG1

(H8S/2646,

H8S/2646R,

H8S/2645)

Output LCD segment drive pins

All pins are multiplexed as port pins (setting

programmable)

SEG40 to SEG1

(H8S/2648,

H8S/2648R,

H8S/2647)

Common output

pins COM4 to COM1 Output LCD common drive pins

Pins can be used in parallel with static or 1/2 duty

LCD power supply

pins V1, V2, V3 — Used when a bypass capacitor is connected

externally, and when an external power supply

circuit is used

18.1.4 Register Configuration

Table 18-2 shows the register configuration of the LCD controller/driver.

Table 18-2 LCD Controller/Driver Registers

Name Abbreviation R/W Initial Value Address*1

LCD port control register LPCR R/W H'00 H'FC30

LCD control register LCR R/W H'80 H'FC31

LCD control register 2 LCR2 R/W H'60 H'FC32

LCD RAM — R/W Undefined H'FC40 to H'FC53

Module stop control

Note: *1 Lower 16 bits of the address.

634

18.2 Register Descriptions

18.2.1 LCD Port Control Register (LPCR)

Bit 76543210

DTS1 DTS0 CMX — SGS3 SGS2 SGS1 SGS0

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W — R/W R/W R/W R/W

LPCR is an 8-bit read/write register which selects the duty cycle, LCD driver, and pin functions.

LPCR is initialized to H'00 upon reset and in standby mode.

Bits 7 to 5—Duty Cycle Select 1 and 0 (DTS1, DTS0), Common Function Select (CMX): The

combination of DTS1 and DTS0 selects static, 1/2, 1/3, or 1/4 duty. CMX specifies whether or not

the same waveform is to be output from multiple pins to increase the common drive power when

not all common pins are used because of the duty setting.

Bit 7:

DTS1 Bit 6:

DTS0 Bit 5:

CMX Duty Cycle Common Drivers Notes

0 0 0 Static COM1 COM4, COM3, and COM2 can

be used as ports (Initial value)

1 COM4 to COM1 COM4, COM3, and COM2 output

the same waveform as COM1

1 0 1/2 duty COM2 to COM1 COM4 and COM3 can be used

as ports

1 COM4 to COM1 COM4 outputs the same

waveform as COM3, and COM2

outputs the same waveform as

COM1

1 0 0 1/3 duty COM3 to COM1 COM4 can be used as a port

1 COM4 to COM1 Do not use COM4

1*1/4 duty COM4 to COM1 —

*: Don’t care

Note: COM4 to COM1 function as ports when the setting of SGS3 to SGS0 is 0000 (initial value).

Bit 4—Reserved: This bit is always read as 0 and should only be written with 0.

635

Bits 3 to 0—Segment Driver Select 3 to 0 (SGS3 to SGS0): Bits 3 to 0 select the segment

drivers to be used.

• H8S/2646, H8S/2646R, H8S/2645

Function of Pins SEG24 to SEG1

Bit 3:

SGS3 Bit 2:

SGS2 Bit 1:

SGS1 Bit 0:

SGS0 SEG24 to

SEG17 SEG16 to

SEG13 SEG12 to

SEG9 SEG8 to

SEG5 SEG4 to

SEG1 Notes

0000Port Port Port Port Port Initial value (external

expansion enabled)

1 SEG Port Port Port Port External expansion

not possible

1 0 SEG SEG Port Port Port

1 SEG SEG SEG Port Port

1 0 0 SEG SEG SEG SEG Port

1 SEG SEG SEG SEG SEG

1*Setting

prohibited Setting

prohibited

1***Setting

prohibited Setting

prohibited

*: Don’t care

Note: When using external expansion, set a value of 0000 for SGS3 to SGS0. When the setting of

SGS3 to SGS0 is 0000, COM4 to COM1 also function as ports.

636

• H8S/2648, H8S/2648R, H8S/2647

Function of Pins SEG40 to SEG1

Bit 3:

SGS3 Bit 2:

SGS2 Bit 1:

SGS1 Bit 0:

SGS0

SEG40

SEG33

SEG32

SEG29

SEG28

SEG25

SEG24

SEG21

SEG20

SEG17

SEG16

SEG13

SEG12

SEG9

SEG8

SEG5

SEG4

SEG1 Notes

0000Port Port Port Port Port Port Port Port Port Initial value (external

expansion enabled)

1 SEG Port Port Port Port Port Port Port Port External expansion

not possible

1 0 SEG SEG Port Port Port Port Port Port Port

1 SEG SEG SEG Port Port Port Port Port Port

1 0 0 SEG SEG SEG SEG Port Port Port Port Port

1 SEG SEG SEG SEG SEG Port Port Port Port

1 0 SEG SEG SEG SEG SEG SEG Port Port Port

1 SEG SEG SEG SEG SEG SEG SEG Port Port

1**0 SEG SEG SEG SEG SEG SEG SEG SEG Port

1 SEG SEG SEG SEG SEG SEG SEG SEG SEG

*: Don’t care

Note: When using external expansion, set a value of 0000 for SGS3 to SGS0. When the setting of

SGS3 to SGS0 is 0000, COM4 to COM1 also function as ports.

637

18.2.2 LCD Control Register (LCR)

Bit 76543210

— PSW ACT DISP CKS3 CKS2 CKS1 CKS0

Initial value 1 0 0 0 0 0 0 0

Read/Write — R/W R/W R/W R/W R/W R/W R/W

LCR is an 8-bit read/write register which performs LCD power supply split-resistance connection

control and display data control, and selects the frame frequency.

LCR is initialized to H'80 upon reset and in standby mode.

Bit 7—Reserved: This bit is always read as 1 and cannot be modified.

Bit 6—LCD Power Supply Split-Resistance Connection Control (PSW): Bit 6 can be used to

disconnect the LCD power supply split-resistance from VCC when LCD display is not required in a

power-down mode, or when an external power supply is used. When the ACT bit is cleared to 0,

and also in standby mode, the LCD power supply split-resistance is disconnected from VCC

regardless of the setting of this bit.

Bit 6: PSW Description

0 LCD power supply split-resistance is disconnected from VCC (Initial value)

1 LCD power supply split-resistance is connected to VCC

Bit 5—Display Function Activate (ACT): Bit 5 specifies whether or not the LCD

controller/driver is used. Clearing this bit to 0 halts operation of the LCD controller/driver. The

LCD drive power supply ladder resistance is also turned off, regardless of the setting of the PSW

bit. However, register contents are retained.

Bit 5: ACT Description

0 LCD controller/driver operation halted (Initial value)

1 LCD controller/driver operates

Bit 4—Display Data Control (DISP): Bit 4 specifies whether the LCD RAM contents are

displayed or blank data is displayed regardless of the LCD RAM contents.

Bit 4: DISP Description

0 Blank data is displayed (Initial value)

1 LCD RAM data is display

638

Bits 3 to 0—Frame Frequency Select 3 to 0 (CKS3 to CKS0): Bits 3 to 0 select the operating

clock and the frame frequency. In subactive mode, watch mode, and subsleep mode, the system

clock (ø) is halted, and therefore display operations are not performed if one of the clocks from ø/8

to ø/1024 is selected. If LCD display is required in these modes, øSUB, øSUB/2, or øSUB/4 must be

selected as the operating clock.

Bit 3: Bit 2: Bit 1: Bit 0: Frame Frequency*1

CKS3 CKS2 CKS1 CKS0 Operating Clock ø = 20 MHz

0*00ø

SUB 128 Hz*2

(Initial value)

1ø

SUB/2 64 Hz*2

1*øSUB/4 32 Hz*2

1000ø/8 4880 Hz

1 ø/16 2440 Hz

1 0 ø/32 1220 Hz

1 ø/64 610 Hz

1 0 0 ø/128 305 Hz

1 ø/256 152.6 Hz

1 0 ø/512 76.3 Hz

1 ø/1024 38.1 Hz

*: Don’t care

Notes: *1 When 1/3 duty is selected, the frame frequency is 4/3 times the value shown.

*2 This is the frame frequency when øSUB = 32.768 kHz.

639

18.2.3 LCD Control Register 2 (LCR2)

Bit 76543210

LCDAB — — — — — — —

Initial value 0 1 1 0 0 0 0 0

Read/Write R/W — — — — — — —

LCR2 is an 8-bit read/write register which controls switching between the A waveform and B

waveform.

LCR2 is initialized to H'70 upon reset and in standby mode.

Bit 7—A Waveform/B Waveform Switching Control (LCDAB): Bit 7 specifies whether the A

waveform or B waveform is used as the LCD drive waveform.

Bit 7: LCDAB Description

0 Drive using A waveform (Initial value)

1 Drive using B waveform

Bits 6 and 5—Reserved: These bits are always read as 1 and cannot be modified.

Bits 4 to 0—Reserved: These bits are always read as 0 and should only be written with 0.

640

18.2.4 Module Stop Control Register D (MSTPCRD)

Bit 76543210

MSTPD7 MSTPD6 — — — — — —

Initial value 1 1 Undefined Undefined Undefined Undefined Undefined Undefined

Read/Write R/W R/W — — — — — —

MSTPCRD is an 8-bit read/write register that performs module stop mode control.

When the MSTPD6 bit is set to 1, LCD controller/driver operation is stopped at the end of the bus

cycle, and module stop mode is entered. For details, see section 22.5, Module Stop Mode.

MSTPCRD is initialized to H'FF by a reset and in hardware standby mode. It is not initialized

software standby mode.

Bit 6—Module Stop (MSTPD6): Bit 6 specifies the LCD controller/driver module stop mode.

Bit 6: MSTPD6 Description

0 LCD controller/driver module stop mode is cleared

1 LCD controller/driver module stop mode is set (Initial value)

641

18.3 Operation

18.3.1 Settings up to LCD Display

To perform LCD display, the hardware and software related items described below must first be

determined.

Hardware Settings

• Using 1/2 duty

When 1/2 duty is used, interconnect pins V2 and V3 as shown in figure 18-2.

LPVCC

VSS

Figure 18-2 Handling of LCD Drive Power Supply when Using 1/2 Duty

• Panel display

As the impedance of the built-in power supply split-resistance is large, the display may lack

sharpness when driving a panel. In this case, refer to section 18.3.4, Boosting the LCD Drive

Power Supply. When static or 1/2 duty is selected, the common output drive capability can be

increased. Set CMX to 1 when selecting the duty cycle. In this mode, with a static duty cycle

pins COM4 to COM1 output the same waveform, and with 1/2 duty the COM1 waveform is

output from pins COM2 and COM1, and the COM2 waveform is output from pins COM4 and

COM3.

• LCD drive power supply setting

With the H8S/2646 Series, there are two ways of providing LCD power: by using the on-chip

power supply circuit, or by using an external power supply circuit.

When an external power supply circuit is used for the LCD drive power supply, connect the

external power supply to the V1 pin.

642

Software Settings

• Duty selection

Any of four duty cycles—static, 1/2 duty, 1/3 duty, or 1/4 duty—can be selected with bits

DTS1 and DTS0.

• Segment selection

The segment drivers to be used can be selected with bits SGS3 to SGS0.

• Frame frequency selection

The frame frequency can be selected by setting bits CKS3 to CKS0. The frame frequency

should be selected in accordance with the LCD panel specification. For the clock selection

method in watch mode, subactive mode, and subsleep mode, see section 18.3.3, Operation in

Power-Down Modes.

• A or B waveform selection

Either the A or B waveform can be selected as the LCD waveform to be used by means of

LCDAB.

• LCD drive power supply selection

When an external power supply circuit is used, turn the LCD drive power supply off with the

PSW bit.

643

18.3.2 Relationship between LCD RAM and Display

H8S/2646, H8S/2646R, H8S/2645

The relationship between the LCD RAM and the display segments differs according to the duty

cycle. LCD RAM maps for the different duty cycles are shown in figures 18-3 to 18-6.

After setting the registers required for display, data is written to the part corresponding to the duty

using the same kind of instruction as for ordinary RAM, and display is started automatically when

turned on. Word- or byte-access instructions can be used for RAM setting.

Bit 7

H'FC40

H'FC47

COM4

Bit 6

COM3

Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SEG2

H'FC48 SEG2 SEG2 SEG2 SEG1 SEG1 SEG1 SEG1

SEG24 SEG24 SEG24 SEG24 SEG23 SEG23 SEG23 SEG23

H'FC53

COM2 COM1 COM4 COM3 COM2 COM1

Display space

Space not used

for display

Figure 18-3 LCD RAM Map (1/4 Duty)

644

Bit 7

H'FC40

H'FC47

Bit 6

COM3

Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

H'FC48 SEG2 SEG2 SEG2 SEG1 SEG1 SEG1

SEG24 SEG24 SEG24 SEG23 SEG23 SEG23

H'FC53

COM2 COM1 COM3 COM2 COM1

Display space

Space not used

for display

Figure 18-4 LCD RAM Map (1/3 Duty)

Bit 7

SEG24

H'FC40

H'FC49

COM2

Bit 6

SEG24

COM1

Bit 5

SEG23

Bit 4

SEG23

Bit 3

SEG22

Bit 2

SEG22

Bit 1

SEG21

Bit 0

SEG21

SEG4H'FC44

H'FC43 SEG4 SEG3 SEG3 SEG2 SEG2 SEG1 SEG1

H'FC53

COM2 COM1 COM2 COM1 COM2 COM1

Space not used

for display

Space not used

for display

Display space

Figure 18-5 LCD RAM Map (1/2 Duty)

645

Bit 7

COM1

Bit 6

COM1

Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

H'FC40

H'FC41 SEG8H'FC42 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1

SEG24H'FC44 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17

H'FC53

COM1 COM1 COM1 COM1 COM1 COM1

Space not used

for display

Space not

used for

display

Display

space

Figure 18-6 LCD RAM Map (Static Mode)

646

H8S/2648, H8S/2648R, H8S/2647

The relationship between the LCD RAM and the display segments differs according to the duty

cycle. LCD RAM maps for the different duty cycles are shown in figures 18-7 to 18-10.

After setting the registers required for display, data is written to the part corresponding to the duty

using the same kind of instruction as for ordinary RAM, and display is started automatically when

turned on. Word- or byte-access instructions can be used for RAM setting.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

H'FC40

H'FC53 SEG40 SEG40 SEG40 SEG39SEG40 SEG39 SEG39 SEG39

SEG2 SEG2 SEG2 SEG1SEG2 SEG1 SEG1 SEG1

COM3 COM2 COM1 COM3 COM2 COM1

COM4 COM4

Figure 18-7 LCD RAM Map (1/4 Duty)

647

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

H'FC40

H'FC53 SEG40 SEG40 SEG40 SEG39 SEG39 SEG39

SEG2 SEG2 SEG2 SEG1 SEG1 SEG1

COM3

Space not used for display

COM2 COM1 COM3 COM2 COM1

Figure 18-8 LCD RAM Map (1/3 Duty)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

H'FC40

H'FC53

COM2 COM1 COM2 COM1 COM2 COM1 COM2 COM1

SEG40 SEG40 SEG39 SEG39 SEG38 SEG38 SEG37 SEG37

SEG4 SEG4 SEG3 SEG3 SEG2 SEG2 SEG1 SEG1

H'FC49

Display space

Space not used

for display

Figure 18-9 LCD RAM Map (1/2 Duty)

648

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

H'FC40

H'FC53

COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1

SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33

SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1

H'FC44

Display space

Space not used

for display

Figure 18-10 LCD RAM Map (Static Mode)

649

1 frame

Data

COM1

COM2

COM3

COM4

SEGn

(a) Waveform with 1/4 duty

1 frame

Data

COM1

COM2

COM3

SEGn

1 frame

Data

COM1

COM2

SEGn

1 frame

Data

COM1

SEGn

(b) Waveform with 1/3 duty

(d) Waveform with static output

Figure 18-11 Output Waveforms for Each Duty Cycle (A Waveform)

650

Data

COM1

COM2

SEGn

Data

COM1

SEGn

VSS

(d) Waveform with static output

(b) Waveform with 1/3 duty

Data

COM3

SEGn

COM1 V1

VSS

COM2

(a) Waveform with 1/4 duty

Data

COM1

COM2

COM3

COM4

SEGn

1 frame 1 frame 1 frame 1 frame

V2, V3

VSS

V2, V3

VSS

V2, V3

VSS

1 frame 1 frame 1 frame 1 frame

Figure 18-12 Output Waveforms for Each Duty Cycle (B Waveform)

651

Table 18-3 Output Levels

Data 0011

M 0101

Static Common output V1 VSS V1 VSS

Segment output V1 VSS VSS V1

1/2 duty Common output V2, V3 V2, V3 V1 VSS

Segment output V1 VSS VSS V1

1/3 duty Common output V3 V2 V1 VSS

Segment output V2 V3 VSS V1

1/4 duty Common output V3 V2 V1 VSS

Segment output V2 V3 VSS V1

18.3.3 Operation in Power-Down Modes

In the H8S/2646 Series, the LCD controller/driver can be operated even in the power-down

modes. The operating state of the LCD controller/driver in the power-down modes is summarized

in table 18-4.

In subactive mode, watch mode, and subsleep mode, the system clock oscillator stops, and

therefore, unless øSUB, øSUB/2, or øSUB/4 has been selected by bits CKS3 to CKS0, the clock will not

be supplied and display will halt. Since there is a possibility that a direct current will be applied to

the LCD panel in this case, it is essential to ensure that øSUB, øSUB/2, or øSUB/4 is selected. In active

(medium-speed) mode, the system clock is switched, and therefore CKS3 to CKS0 must be

modified to ensure that the frame frequency does not change.

In the software standby mode the segment output and common output pins switch to high-

impedance status. In this case if a port’s DDR or PCR bit is set to 1, a DC voltage could be applied

to the LCD panel. Therefore, DDR and PCR must never be set to 1 for ports being used for

segment output or common output.

652

Table 18-4 Power-Down Modes and Display Operation

Mode Reset Active Sleep Watch Subactive Subsleep Standby Module

Standby

Clock øRuns Runs Runs Stops Stops Stops Stops Stops*4

øSUB Runs Runs Runs Runs Runs Runs Stops*1Stops*4

Display ACT = 0 Stops Stops Stops Stops Stops Stops Stops*2Stops

operation ACT = 1 Stops Functions Functions Functions*3Functions*3Functions*3Stops*2Stops

Notes: *1 The subclock oscillator does not stop, but clock supply is halted.

*2 The LCD drive power supply is turned off regardless of the setting of the PSW bit.

*3 Display operation is performed only if øSUB, øSUB/2, or øSUB/4 is selected as the operating

clock.

*4 The clock supplied to the LCD stops.

18.3.4 Boosting the LCD Drive Power Supply

When a panel is driven, the on-chip power supply capacity may be insufficient. The recommended

solution in this case is to connect bypass capacitors of around 0.1 to 0.3 µF to pins V1 to V3, or to

connect a new split-resistance externally, as shown in figure 18-13.

H8S/2646 Series

LPVCC

VSS

R =

C = 0.1 to 0.3 µF

several kΩ to

several MΩ

Figure 18-13 Connection of External Split-Resistance

653

Section 19 RAM

19.1 Overview

The H8S/2646, H8S/2646R, H8S/2648, and H8S/2648R have 4 kbytes and H8S/2645 and

H8S/2647 have 2 kbytes of on-chip high-speed static RAM. The RAM is connected to the CPU by

a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. This

makes it possible to perform fast word data transfer.

The on-chip RAM can be enabled or disabled by means of the RAM enable bit (RAME) in the

system control register (SYSCR).

19.1.1 Block Diagram

Figure 19-1 shows a block diagram of the on-chip RAM.

Internal data bus (upper 8 bits)

Internal data bus (lower 8 bits)

H'FFE000*

H'FFE002

H'FFE004

H'FFFFC0

H'FFE001

H'FFE003

H'FFE005

H'FFFFC1

H'FFFFFE H'FFFFFF

H'FFEFBE H'FFEFBF

Note: * Addresses starting from H'FFE800 in the H8S/2645 and H8S/2647.

Figure 19-1 Block Diagram of RAM

654

19.1.2 Register Configuration

The on-chip RAM is controlled by SYSCR. Table 19-1 shows the address and initial value of

SYSCR.

Table 19-1 RAM Register

Name Abbreviation R/W Initial Value Address*

System control register SYSCR R/W H'01 H'FDE5

Note: *Lower 16 bits of the address.

19.2 Register Descriptions

19.2.1 System Control Register (SYSCR)

MACS

R/W

—

INTM1

R/W

INTM0

R/W

NMIEG

R/W

RAME

R/W

—

R/W

—

Bit

Initial value

R/W

The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in

SYSCR, see section 3.2.2, System Control Register (SYSCR).

Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is

initialized when the reset state is released. It is not initialized in software standby mode.

Bit 0

RAME Description

0 On-chip RAM is disabled

1 On-chip RAM is enabled (Initial value)

655

19.3 Operation

When the RAME bit is set to 1, accesses to addresses H'FFE000 to H'FFEFBF and H'FFFFC0 to

H'FFFFFF in the H8S/2646, H8S/2646R, H8S/2648, and H8S/2648R to addresses H'FFE7C0 to

H'FFEFBF and H'FFFFC0 to H'FFFFFF in the H8S/2645 and H8S/2647, are directed to the on-

chip RAM. When the RAME bit is cleared to 0, the off-chip address space is accessed.

Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to

and read in byte or word units. Each type of access can be performed in one state.

Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start

at an even address.

19.4 Usage Notes

When Using the DTC: DTC register information can be located in addresses H'FFEBC0 to

H'FFEFBF. When the DTC is used, the RAME bit must not be cleared to 0.

Reserved Areas: Addresses H'FFB000 to H'FFDFFF in the H8S/2646, H8S/2646R, H8S/2648,

and H8S/2648R and addresses H'FFB000 to H'FFE7BF in the H8S/2645 and H8S/2647 are

reserved areas that cannot be read or written to. When the RAME bit is cleared to 0, the off-chip

address space is accessed.

656

657

Section 20 ROM

20.1 Features

The LSI (H8S/2646R, H8S/2648R) has 128 kbytes of on-chip flash memory. The features of the

flash memory are summarized below.

• Four flash memory operating modes

 Program mode

 Erase mode

 Program-verify mode

 Erase-verify mode

• Programming/erase methods

The flash memory is programmed 128 bytes at a time. Block erase (in single-block units) can

be performed. To erase the entire flash memory, each block must be erased in turn. Block

erasing can be performed as required on 1 kB, 8 kB, 16 kB, 28 kB, and 32 kB blocks.

• Programming/erase times

The flash memory programming time is 10 ms (typ.) for simultaneous 128-byte programming,

equivalent to 78 µs (typ.) per byte, and the erase time is 100 ms (typ.).

• Reprogramming capability

The flash memory can be reprogrammed up to 100 times.

• On-board programming modes

There are two modes in which flash memory can be programmed/erased/verified on-board:

 Boot mode

 User program mode

• Automatic bit rate adjustment

With data transfer in boot mode, the LSI’s bit rate can be automatically adjusted to match the

transfer bit rate of the host.

• Flash memory emulation in RAM

Flash memory programming can be emulated in real time by overlapping a part of RAM onto

flash memory.

• Protect modes

There are two protect modes, hardware and software, which allow protected status to be

designated for flash memory program/erase/verify operations.

• Programmer mode

Flash memory can be programmed/erased in programmer mode, using a PROM programmer,

as well as in on-board programming mode.

658

20.2 Overview

20.2.1 Block Diagram

Module bus

Bus interface/controller

Flash memory

(128 kbytes)

Operating

mode

FLMCR2

Internal address bus

Internal data bus (16 bits)

FWE pin

Mode pin

EBR1

EBR2

RAMER

FLPWCR

FLMCR1

Flash memory control register 1

Flash memory control register 2

Erase block register 1

Erase block register 2

RAM emulation register

Flash memory power control register

Legend

FLMCR1:

FLMCR2:

EBR1:

EBR2:

RAMER:

FLPWCR:

Figure 20-1 Block Diagram of Flash Memory

659

20.2.2 Mode Transitions

When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, the

microcomputer enters an operating mode as shown in figure 20-2. In user mode, flash memory can

be read but not programmed or erased.

The boot, user program and programmer modes are provided as modes to write and erase the flash

memory.

Boot mode

On-board programming mode

User

program mode

User mode

(on-chip ROM

enabled)

Reset state

Programmer

mode

RES = 0

FWE = 1 FWE = 0

Notes: Only make a transition between user mode and user program mode when the CPU is

not accessing the flash memory.

*1 RAM emulation possible

*2 MD0 = 0, MD1 = 0, MD2 = 0, P14 = 0, FWE = 1, P16 = 0, PF0 = 1

RES = 0

MD1 = 1

MD2 = 0,

FWE = 1

RES = 0

MD1 = 1,

MD2 = 1,

FWE = 0

MD1 = 1,

MD2 = 1,

FWE = 1

Figure 20-2 Flash Memory State Transitions

660

20.2.3 On-Board Programming Modes

Boot Mode

Flash memory

LSI

RAM

Host

Programming control

program

SCI

Application program

(old version)

;;

New application

program

Flash memory

LSI

RAM

Host

SCI

Application program

(old version)

Boot program area

New application

program

Flash memory

LSI

RAM

Host

SCI

Flash memory

preprogramming

erase

Boot program

New application

program

Flash memory

LSI

Program execution state

RAM

Host

SCI

New application

program

Boot program

Programming control

program

;

1. Initial state

The old program version or data remains written

in the flash memory. The user should prepare the

programming control program and new

application program beforehand in the host.

2. Programming control program transfer

When boot mode is entered, the boot program in

the LSI (originally incorporated in the chip) is

started and the programming control program in

the host is transferred to RAM via SCI

communication. The boot program required for

flash memory erasing is automatically transferred

to the RAM boot program area.

3. Flash memory initialization

The erase program in the boot program area (in

RAM) is executed, and the flash memory is

initialized (to H'FF). In boot mode, total flash

memory erasure is performed, without regard to

blocks.

4. Writing new application program

The programming control program transferred

from the host to RAM is executed, and the new

application program in the host is written into the

flash memory.

Programming control

program

Boot programBoot program

Boot program area Boot program area

Programming control

program

661

User Program Mode

Flash memory

LSI

RAM

Host

Programming/

erase control program

SCI

Boot program

New application

program

Flash memory

LSI

RAM

Host

SCI

New application

program

Flash memory

LSI

RAM

Host

SCI

Flash memory

erase

Boot program

New application

program

Flash memory

LSI

Program execution state

RAM

Host

SCI

Boot program

;

Boot program

FWE assessment

program

Application program

(old version)

;

;;

New application

program

;;

1. Initial state

The FWE assessment program that confirms that

user program mode has been entered, and the

program that will transfer the programming/erase

control program from flash memory to on-chip

RAM should be written into the flash memory by

the user beforehand. The programming/erase

control program should be prepared in the host or

in the flash memory.

2. Programming/erase control program transfer

When user program mode is entered, user

software confirms this fact, executes transfer

program in the flash memory, and transfers the

programming/erase control program to RAM.

3. Flash memory initialization

The programming/erase program in RAM is

executed, and the flash memory is initialized (to

H'FF). Erasing can be performed in block units,

but not in byte units.

4. Writing new application program

Next, the new application program in the host is

written into the erased flash memory blocks. Do

not write to unerased blocks.

Programming/

erase control program

Programming/

erase control program

Programming/

erase control program

Transfer program

Application program

(old version)

Transfer program

FWE assessment

program

FWE assessment

program

Transfer program

FWE assessment

program

Transfer program

662

20.2.4 Flash Memory Emulation in RAM

Emulation should be performed in user mode or user program mode. When the emulation block

set in RAMER is accessed while the emulation function is being executed, data written in the

overlap RAM is read.

Application program

Execution state

Flash memory

Emulation block

RAM

SCI

Overlap RAM

(emulation is performed

on data written in RAM)

Figure 20-3 Reading Overlap RAM Data in User Mode or User Program Mode

When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and

writes should actually be performed to the flash memory.

When the programming control program is transferred to RAM, ensure that the transfer

destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to

be rewritten.

663

Application program

Flash memory

RAM

SCI

Programming control

program execution state

Overlap RAM

(programming data)

Programming data

Figure 20-4 Writing Overlap RAM Data in User Program Mode

20.2.5 Differences between Boot Mode and User Program Mode

Boot Mode User Program Mode

Total erase Yes Yes

Block erase No Yes

Programming control program*(2) (1) (2) (3)

(1) Erase/erase-verify

(2) Program/program-verify

(3) Emulation

Note: *To be provided by the user, in accordance with the recommended algorithm.

664

20.2.6 Block Configuration

The flash memory is divided into two 32 kbytes blocks, one 28 kbytes block, one 16 kbytes block,

two 8 kbytes blocks, and four 1 kbyte blocks.

Address H'00000

Address H'1FFFF

128 kbytes

28 kbytes

32 kbytes

16 kbytes

8 kbytes

1 kbyte × 4

Figure 20-5 Block Configuration

665

20.3 Pin Configuration

The flash memory is controlled by means of the pins shown in table 20-1.

Table 20-1 Pin Configuration

Pin Name Abbreviation I/O Function

Reset RES Input Reset

Flash write enable FWE Input Flash program/erase protection by hardware

Mode 2 MD2 Input Sets LSI operating mode

Mode 1 MD1 Input Sets LSI operating mode

Mode 0 MD0 Input Sets LSI operating mode

Port F0 PF0 Input Sets LSI operating mode when MD2 =

MD1 = MD0 =0

Port 16 P16 Input Sets LSI operating mode when MD2 =

MD1 = MD0 =0

Port 14 P14 Input Sets LSI operating mode when MD2 =

MD1 = MD0 =0

Transmit data TxD1 Output Serial transmit data output

Receive data RxD1 Input Serial receive data input

666

20.4 Register Configuration

The registers used to control the on-chip flash memory when enabled are shown in table 20-2.

Table 20-2 Register Configuration

Flash memory control register 1 FLMCR1*4R/W H'00*2H'FFA8

Flash memory control register 2 FLMCR2*4R H'00 H'FFA9

Erase block register 1 EBR1*4R/W H'00*3H'FFAA

Erase block register 2 EBR2*4R/W H'00*3H'FFAB

RAM emulation register RAMER*4R/W H'00 H'FEDB

Flash memory power control register FLPWCR*4R/W H'00*3H'FFAC

Notes: *1 Lower 16 bits of the address.

*2 When a high level is input to the FWE pin, the initial value is H'80.

*3 When a low level is input to the FWE pin, or if a high level is input and the SWE bit in

FLMCR1 is not set, these registers are initialized to H'00.

*4 FLMCR1, FLMCR2, EBR1, EBR2, RAMER, and FLPWCR are 8-bit registers.

Use byte access on these registers.

20.5 Register Descriptions

20.5.1 Flash Memory Control Register 1 (FLMCR1)

FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode

or erase-verify mode for addresses H'00000 to H'1FFFF is entered by setting SWE bit to 1 when

FWE = 1, then setting the PV or EV bit. Program mode for addresses H'00000 to H'1FFFF is

entered by setting SWE bit to 1 when FWE = 1, then setting the PSU bit, and finally setting the P

bit. Erase mode for addresses H'00000 to H'1FFFF is entered by setting SWE bit to 1 when FWE

= 1, then setting the ESU bit, and finally setting the E bit. FLMCR1 is initialized by a reset, and in

hardware standby mode and software standby mode. Its initial value is H'80 when a high level is

input to the FWE pin, and H'00 when a low level is input. When on-chip flash memory is disabled,

a read will return H'00, and writes are invalid.

Writes are enabled only in the following cases: Writes to bit SWE of FLMCR1 enabled when

FWE = 1, to bits ESU, PSU, EV, and PV when FWE = 1 and SWE = 1, to bit E when FWE = 1,

SWE = 1 and ESU = 1, and to bit P when FWE = 1, SWE = 1, and PSU = 1.

667

Bit: 7 6 5 4 3 2 1 0

FWE SWE ESU PSU EV PV E P

Initial value: —*0000000

R/W: R R/W R/W R/W R/W R/W R/W R/W

Note: * Determined by the state of the FWE pin.

Bit 7—Flash Write Enable Bit (FWE): Sets hardware protection against flash memory

programming/erasing.

Bit 7: FWE Description

0 When a low level is input to the FWE pin (hardware-protected state)

1 When a high level is input to the FWE pin

Bit 6—Software Write Enable Bit (SWE): Enables or disables flash memory programming and

erasing. Set this bit when setting bits 5 to 0, bits 7 to 0 of EBR1, and bits 1 and 0 of EBR2.

Bit 6: SWE Description

0 Writes disabled (Initial value)

1 Writes enabled

[Setting condition]

When FWE = 1

Bit 5—Erase Setup Bit (ESU): Prepares for a transition to erase mode. Set this bit to 1 before

setting the E bit in FLMCR1 to 1. Do not set the SWE, PSU, EV, PV, E, or P bit at the same time.

Bit 5: ESU Description

0 Erase setup cleared (Initial value)

1 Erase setup

[Setting condition]

When FWE = 1 and SWE = 1

668

Bit 4—Program Setup Bit (PSU): Prepares for a transition to program mode. Set this bit to 1

before setting the P bit in FLMCR1 to 1. Do not set the SWE, ESU, EV, PV, E, or P bit at the

same time.

Bit 4: PSU Description

0 Program setup cleared (Initial value)

1 Program setup

[Setting condition]

When FWE = 1 and SWE = 1

Bit 3—Erase-Verify (EV): Selects erase-verify mode transition or clearing. Do not set the SWE,

ESU, PSU, PV, E, or P bit at the same time.

Bit 3: EV Description

0 Erase-verify mode cleared (Initial value)

1 Transition to erase-verify mode

[Setting condition]

When FWE = 1 and SWE = 1

Bit 2—Program-Verify (PV): Selects program-verify mode transition or clearing. Do not set the

SWE, ESU, PSU, EV, E, or P bit at the same time.

Bit 2: PV Description

0 Program-verify mode cleared (Initial value)

1 Transition to program-verify mode

[Setting condition]

When FWE = 1 and SWE = 1

Bit 1—Erase (E): Selects erase mode transition or clearing. Do not set the SWE, ESU, PSU, EV,

PV, or P bit at the same time.

Bit 1: E Description

0 Erase mode cleared (Initial value)

1 Transition to erase mode

[Setting condition]

When FWE = 1, SWE = 1, and ESU = 1

669

Bit 0—Program (P): Selects program mode transition or clearing. Do not set the SWE, PSU,

ESU, EV, PV, or E bit at the same time.

Bit 0: P Description

0 Program mode cleared (Initial value)

1 Transition to program mode

[Setting condition]

When FWE = 1, SWE = 1, and PSU = 1

20.5.2 Flash Memory Control Register 2 (FLMCR2)

FLMCR2 is an 8-bit register used for flash memory operating mode control. FLMCR2 is

initialized to H'00 by a reset, and in hardware standby mode and software standby mode. When

on-chip flash memory is disabled, a read will return H'00.

Bit: 7 6 5 4 3 2 1 0

FLER — — — — — — —

Initial value: 0 0 0 0 0 0 0 0

R/W: R R R R R R R R

Note: FLMCR2 is a read-only register, and should not be written to.

Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on

flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-

protection state.

Bit 7: FLER Description

0 Flash memory is operating normally (Initial value)

Flash memory program/erase protection (error protection) is disabled

[Clearing condition]

Reset or hardware standby mode

1 An error has occurred during flash memory programming/erasing

Flash memory program/erase protection (error protection) is enabled

[Setting condition]

See section 20.8.3 Error Protection

Bits 6 to 0—Reserved: These bits always read 0.

670

20.5.3 Erase Block Register 1 (EBR1)

EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is

initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low

level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in

FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be erased. Other

blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can be set. Do not

set more than one bit, as this will cause all the bits in both EBR1 and EBR2 to be automatically

cleared to 0. When on-chip flash memory is disabled, a read will return H'00, and writes are

invalid.

The flash memory block configuration is shown in table 20-3.

Bit: 7 6 5 4 3 2 1 0

EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

20.5.4 Erase Block Register 2 (EBR2)

EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is

initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low

level is input to the FWE pin. Bit 0 will be initialized to 0 if bit SWE of FLMCR1 is not set, even

though a high level is input to pin FWE. When a bit in EBR2 is set to 1, the corresponding block

can be erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2

combined can be set. Do not set more than one bit, as this will cause all the bits in both EBR1 and

EBR2 to be automatically cleared to 0. Bits 7 to 2 are reserved and must only be written with 0.

When on-chip flash memory is disabled, a read will return H'00, and writes are invalid.

The flash memory block configuration is shown in table 20-3.

Bit: 7 6 5 4 3 2 1 0

——————EB9EB8

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

671

Table 20-3 Flash Memory Erase Blocks

Block (Size) Addresses

EB0 (1 kbyte) H'000000–H'0003FF

EB1 (1 kbyte) H'000400–H'0007FF

EB2 (1 kbyte) H'000800–H'000BFF

EB3 (1 kbyte) H'000C00–H'000FFF

EB4 (28 kbytes) H'001000–H'007FFF

EB5 (16 kbytes) H'008000–H'00BFFF

EB6 (8 kbytes) H'00C000–H'00DFFF

EB7 (8 kbytes) H'00E000–H'00FFFF

EB8 (32 kbytes) H'010000–H'017FFF

EB9 (32 kbytes) H'018000–H'01FFFF

20.5.5 RAM Emulation Register (RAMER)

RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating

real-time flash memory programming. RAMER initialized to H'00 by a reset and in hardware

standby mode. It is not initialized by software standby mode. RAMER settings should be made in

user mode or user program mode.

Flash memory area divisions are shown in table 20-4. To ensure correct operation of the emulation

function, the ROM for which RAM emulation is performed should not be accessed immediately

after this register has been modified. Normal execution of an access immediately after register

modification is not guaranteed.

Bit: 7 6 5 4 3 2 1 0

— — — — RAMS RAM2 RAM1 RAM0

Initial value: 0 0 0 0 0 0 0 0

R/W: R R R/W R/W R/W R/W R/W R/W

Bits 7 and 6—Reserved: These bits always read 0.

Bits 5 and 4—Reserved: Only 0 may be written to these bits.

672

Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in

RAM. When RAMS = 1, all flash memory block are program/erase-protected.

Bit 3: RAMS Description

0 Emulation not selected (Initial value)

Program/erase-protection of all flash memory blocks is disabled

1 Emulation selected

Program/erase-protection of all flash memory blocks is enabled

Bits 2 to 0—Flash Memory Area Selection (RAM2 to RAM0): These bits are used together

with bit 3 to select the flash memory area to be overlapped with RAM. (See table 20-4.)

Table 20-4 Flash Memory Area Divisions

Addresses Block Name RAMS RAM2 RAM1 RAM0

H'FFE000–H'FFE3FF RAM area 1 kB 0 ***

H'000000–H'0003FF EB0 (1 kB) 1 0 0 *

H'000400–H'0007FF EB1 (1 kB) 1 0 1 *

H'000800–H'000BFF EB2 (1 kB) 1 1 0 *

H'000C00–H'000FFF EB3 (1 kB) 1 1 1 *

*: Don't care

20.5.6 Flash Memory Power Control Register (FLPWCR)

Bit: 7 6 5 4 3 2 1 0

PDWND — — — — — — —

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R R R R R R R

FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI

switches to subactive mode.

Bit 7—Power-Down Disable (PDWND): Enables or disables a transition to the flash memory

power-down mode when the LSI switches to subactive mode. For details, see section 20.12, Flash

Memory and Power-Down States.

673

Bit 7: PDWND Description

0 Transition to flash memory power-down mode enabled (Initial value)

1 Transition to flash memory power-down mode disabled

Bits 6 to 0—Reserved: These bits always read 0.

20.6 On-Board Programming Modes

When pins are set to on-board programming mode and a reset-start is executed, a transition is

made to the on-board programming state in which program/erase/verify operations can be

performed on the on-chip flash memory. There are two on-board programming modes: boot mode

and user program mode. The pin settings for transition to each of these modes are shown in table

20-5. For a diagram of the transitions to the various flash memory modes, see figure 20-2.

Table 20-5 Setting On-Board Programming Modes

Mode FWE MD2 MD1 MD0

Boot mode Expanded mode 1010

Single-chip mode 0 1 1

User program mode Expanded mode 1110

Single-chip mode 1 1 1

20.6.1 Boot Mode

When boot mode is used, the flash memory programming control program must be prepared in the

host beforehand. The SCI channel to be used is set to asynchronous mode.

When a reset-start is executed after the LSI’s pins have been set to boot mode, the boot program

built into the LSI is started and the programming control program prepared in the host is serially

transmitted to the LSI via the SCI. In the LSI, the programming control program received via the

SCI is written into the programming control program area in on-chip RAM. After the transfer is

completed, control branches to the start address of the programming control program area and the

programming control program execution state is entered (flash memory programming is

performed).

The transferred programming control program must therefore include coding that follows the

programming algorithm given later.

The system configuration in boot mode is shown in figure 20-6, and the boot mode execution

procedure in figure 20-7.

674

RxD1

TxD1 SCI1

LSI

Flash memory

Write data reception

Verify data transmission

Host

On-chip RAM

Figure 20-6 System Configuration in Boot Mode

675

Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is

transmitted as an erase error, and the erase operation and subsequent operations

are halted.

Start

Set pins to boot mode

and execute reset-start

Host transfers data (H'00)

continuously at prescribed bit rate

LSI measures low period

of H'00 data transmitted by host

LSI calculates bit rate and

sets value in bit rate register

After bit rate adjustment, LSI

transmits one H'00 data byte to

host to indicate end of adjustment

Host confirms normal reception

of bit rate adjustment end

indication (H'00), and transmits

one H'55 data byte

After receiving H'55,

LSI transmits one H'AA

data byte to host

Host transmits number

of programming control program

bytes (N), upper byte followed

by lower byte

LSI transmits received

number of bytes to host as verify

data (echo-back)

n = 1

Host transmits programming control

program sequentially in byte units

LSI transmits received

programming control program to

host as verify data (echo-back)

Transfer received programming

control program to on-chip RAM

n = N? No

Yes

End of transmission

Check flash memory data, and

if data has already been written,

erase all blocks

After confirming that all flash

memory data has been erased,

LSI transmits one H'AA data

byte to host

Execute programming control

program transferred to on-chip RAM

n + 1 → n

Figure 20-7 Boot Mode Execution Procedure

676

Automatic SCI Bit Rate Adjustment

Start

bit

Stop

bit

D0 D1 D2 D3 D4 D5 D6 D7

Low period (9 bits) measured (H'00 data) High period

(1 or more bits)

When boot mode is initiated, the LSI measures the low period of the asynchronous SCI

communication data (H'00) transmitted continuously from the host. The SCI transmit/receive

format should be set as follows: 8-bit data, 1 stop bit, no parity. The LSI calculates the bit rate of

the transmission from the host from the measured low period, and transmits one H'00 byte to the

host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end

indication (H'00) has been received normally, and transmit one H'55 byte to the LSI. If reception

cannot be performed normally, initiate boot mode again (reset), and repeat the above operations.

Depending on the host’s transmission bit rate and the LSI’s system clock frequency, there will be

a discrepancy between the bit rates of the host and the LSI. Set the host transfer bit rate at 19,200,

9,600 or 4,800 bps to operate the SCI properly.

Table 20-6 shows host transfer bit rates and system clock frequencies for which automatic

adjustment of the LSI bit rate is possible. The boot program should be executed within this system

clock range.

Table 20-6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is

Possible

Host Bit Rate System Clock Frequency for Which Automatic Adjustment

of LSI Bit Rate is Possible

19,200 bps 16–20 MHz

9,600 bps 8–20 MHz

4,800 bps 4–20 MHz

Note: The system clock frequency used in boot mode is generated by an external crystal oscillator

element. PLL frequency multiplication is not used.

677

On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an

area used by the boot program and an area to which the programming control program is

transferred via the SCI, as shown in figure 20-8. The boot program area cannot be used until the

execution state in boot mode switches to the programming control program transferred from the

host.

H'FFEFBF

H'FFE000

H'FFE7FF

Programming

control program area

(1.9 kbytes)

Boot program area

(2 kbytes)

Note: The boot program area cannot be used until a transition is made to the execution state for

the programming control program transferred to RAM. Note also that the boot program

remains in this area of the on-chip RAM even after control branches to the programming

control program.

Figure 20-8 RAM Areas in Boot Mode

Notes on Use of Boot Mode:

• When the chip comes out of reset in boot mode, it measures the low-level period of the input at

the SCI’s RxD1 pin. The reset should end with RxD1 high. After the reset ends, it takes

approximately 100 states before the chip is ready to measure the low-level period of the RxD1

pin.

• In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all

flash memory blocks are erased. Boot mode is for use when user program mode is unavailable,

such as the first time on-board programming is performed, or if the program activated in user

program mode is accidentally erased.

• Interrupts cannot be used while the flash memory is being programmed or erased.

• The RxD1 and TxD1 pins should be pulled up on the board.

• Before branching to the programming control program (RAM area H'FFE7FF), the chip

terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE

and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data

output pin, TxD1, goes to the high-level output state (PA1DDR = 1, PA1DR = 1).

678

The contents of the CPU’s internal general registers are undefined at this time, so these

registers must be initialized immediately after branching to the programming control program.

In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area

must be specified for use by the programming control program.

The initial values of other on-chip registers are not changed.

• Boot mode can be entered by making the pin settings shown in table 20-5 and executing a

reset-start.

Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting

the FWE pin and mode pins, and executing reset release*1. Boot mode can also be cleared by a

WDT overflow reset.

Do not change the mode pin input levels in boot mode, and do not drive the FWE pin low

while the boot program is being executed or while flash memory is being programmed or

erased*2.

• If the mode pin input levels are changed (for example, from low to high) during a reset, the

state of ports with multiplexed address functions and bus control output pins (AS, RD, HWR)

will change according to the change in the microcomputer’s operating mode*3.

Therefore, care must be taken to make pin settings to prevent these pins from becoming output

signal pins during a reset, or to prevent collision with signals outside the microcomputer.

Notes: *1 Mode pin and FWE pin input must satisfy the mode programming setup time (tMDS = 4

states) with respect to the reset release timing.

*2 For more information on FWE application/cancel, refer to section 20.13, Flash

Memory Programming and Erasing Precautions.

*3 See Appendix D, Pin States.

20.6.2 User Program Mode

When set to user program mode, the chip can program and erase its flash memory by executing a

user program/erase control program. Therefore, on-board reprogramming of the on-chip flash

memory can be carried out by providing on-board means of FWE control and supply of

programming data, and storing a program/erase control program in part of the program area as

necessary.

To select user program mode, select a mode that enables the on-chip flash memory (modes 6 or 7),

and apply a high level to the FWE pin. In this mode, on-chip supporting modules other than flash

memory operate as they normally would in modes 6 and 7.

The flash memory itself cannot be read while the SWE bit is set to 1 to perform programming or

erasing, so the control program that performs programming and erasing should be run in on-chip

RAM or external memory. When a program is in external memory, an instruction for writing to

flash memory and the following instruction must be in the on-chip RAM.

679

Figure 20-9 shows the procedure for executing the program/erase control program when

transferred to on-chip RAM.

Clear FWE

FWE = high*

Branch to flash memory application

program

Branch to program/erase control

program in RAM area

Execute program/erase control

program (flash memory rewriting)

Transfer program/erase control

program to RAM

MD2, MD1, MD0 = 110, 111

Reset-start

Write the FWE assessment program and

transfer program (and the program/erase

control program if necessary) beforehand

Note: *Do not apply a constant high level to the FWE pin. Apply a high level to the FWE pin

only when the flash memory is programmed or erased. Also, while a high level is

applied to the FWE pin, the watchdog timer should be activated to prevent

overprogramming or overerasing due to program runaway, etc.

For more information on FWE application/cancel, refer to section 20.13, Flash

Memory Programming and Erasing Precautions.

Figure 20-9 User Program Mode Execution Procedure

680

20.7 Flash Memory Programming/Erasing

A software method, using the CPU, is employed to program and erase flash memory in the on-

board programming modes. There are four flash memory operating modes: program mode, erase

mode, program-verify mode, and erase-verify mode. Transitions to these modes for addresses

H'000000 to H'01FFFF are made by setting the PSU, ESU, P, E, PV, and EV bits in FLMCR1.

The flash memory cannot be read while being programmed or erased. Therefore, the program

(user program) that controls flash memory programming/erasing should be located and executed in

on-chip RAM or external memory.

When a program is in external memory, an instruction for writing to flash memory and the

following instruction must be in the on-chip RAM. The DTC must not be activated before or after

execution of an instruction for writing to flash memory.

In the following operation descriptions, wait times after setting or clearing individual bits in

FLMCR1 are given as parameters; for details of the wait times, see section 23.7, Flash Memory

Characteristics.

Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, ESU, PSU, EV, PV, E, and

P bits in FLMCR1 is executed by a program in flash memory.

2. When programming or erasing, set FWE to 1 (programming/erasing will not be

executed if FWE = 0).

3. Programming must be executed in the erased state. Do not perform additional

programming on addresses that have already been programmed.

681

Normal mode

On-board

programming mode

Software programming

disable state

Erase setup

state Erase mode

Program mode

Erase-verify

mode

Program

setup state

Program-verify

mode

SWE = 1

SWE = 0

FWE = 1 FWE = 0

E = 1

E = 0

P = 1

P = 0

Software

programming

enable

state

Notes: In order to perform a normal read of flash memory, SWE must be cleared to 0. Also note that verify-reads

can be performed during the programming/erasing process.

*1 : Normal mode : On-board programming mode

*2 Do not make a state transition by setting or clearing multiple bits simultaneously.

*3 After a transition from erase mode to the erase setup state, do not enter erase mode without passing

through the software programming enable state.

*4 After a transition from program mode to the program setup state, do not enter program mode without

passing through the software programming enable state.

ESU = 0

ESU = 1

PSU = 1

PSU = 0

PV = 1

PV = 0

EV = 0

EV = 1

Figure 20-10 FLMCR1 Bit Settings and State Transitions

682

20.7.1 Program Mode

When writing data or programs to flash memory, the program/program-verify flowchart shown in

figure 20-11 should be followed. Performing programming operations according to this flowchart

will enable data or programs to be written to flash memory without subjecting the device to

voltage stress or sacrificing program data reliability. Programming should be carried out 128 bytes

at a time.

The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and

the maximum number of programming operations (N) are shown in table 23-10 in section 23.7,

Flash Memory Characteristics.

Following the elapse of (tsswe) µs or more after the SWE bit is set to 1 in FLMCR1, 128-byte data

is written consecutively to the write addresses. The lower 8 bits of the first address written to must

be H'00 and H'80, 128 consecutive byte data transfers are performed. The program address and

program data are latched in the flash memory. A 128-byte data transfer must be performed even if

writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.

Next, the watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.

Set a value greater than (tspsu + tsp + tcp + tcpsu) µs as the WDT overflow period. Preparation for

entering program mode (program setup) is performed next by setting the PSU bit in FLMCR1.

The operating mode is then switched to program mode by setting the P bit in FLMCR1 after the

elapse of at least (tspsu) µs. The time during which the P bit is set is the flash memory

programming time. Make a program setting so that the time for one programming operation is

within the range of (tsp) µs.

The wait time after P bit setting must be changed according to the degree of progress through the

programming operation. For details see “Notes on Program/Program-Verify Procedure.”

683

20.7.2 Program-Verify Mode

In program-verify mode, the data written in program mode is read to check whether it has been

correctly written in the flash memory.

After the elapse of the given programming time, clear the P bit in FLMCR1, then wait for at least

(tcp) µs before clearing the PSU bit to exit program mode. After exiting program mode, the

watchdog timer setting is also cleared. The operating mode is then switched to program-verify

mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy write

of H'FF data should be made to the addresses to be read. The dummy write should be executed

after the elapse of (tspv) µs or more. When the flash memory is read in this state (verify data is read

in 16-bit units), the data at the latched address is read. Wait at least (tspvr) µs after the dummy write

before performing this read operation. Next, the originally written data is compared with the verify

data, and reprogram data is computed (see figure 20-11) and transferred to RAM. After

verification of 128 bytes of data has been completed, exit program-verify mode, wait for at least

(tcpv) µs, then clear the SWE bit in FLMCR1. If reprogramming is necessary, set program mode

again, and repeat the program/program-verify sequence as before. The maximum number of

repetitions of the program/program-verify sequence is indicated by the maximum programming

count (N). Leave a wait time of at least (tcswe) µs after clearing SWE.

Notes on Program/Program-Verify Procedure

1. In order to perform 128-byte-unit programming, the lower 8 bits of the write start address must

be H'00 or H'80.

2. When performing continuous writing of 128-byte data to flash memory, byte-unit transfer

should be used.

128-byte data transfer is necessary even when writing fewer than 128 bytes of data. Write H'FF

data to the extra addresses.

3. Verify data is read in word units.

4. The write pulse is applied and a flash memory write executed while the P bit in FLMCR1 is

set. In the H8S/2646, write pulses should be applied as follows in the program/program-verify

procedure to prevent voltage stress on the device and loss of write data reliability.

a. After write pulse application, perform a verify-read in program-verify mode and apply a

write pulse again for any bits read as 1 (reprogramming processing). When all the 0-write

bits in the 128-byte write data are read as 0 in the verify-read operation, the

program/program-verify procedure is completed. In the H8S/2646, the number of loops in

reprogramming processing is guaranteed not to exceed the maximum value of the

maximum programming count (N).

b. After write pulse application, a verify-read is performed in program-verify mode, and

programming is judged to have been completed for bits read as 0. The following processing

is necessary for programmed bits.

684

When programming is completed at an early stage in the program/program-verify

procedure:

If programming is completed in the 1st to 6th reprogramming processing loop, additional

programming should be performed on the relevant bits. Additional programming should

only be performed on bits which first return 0 in a verify-read in certain reprogramming

processing.

When programming is completed at a late stage in the program/program-verify procedure:

If programming is completed in the 7th or later reprogramming processing loop, additional

programming is not necessary for the relevant bits.

c. If programming of other bits is incomplete in the 128 bytes, reprogramming processing

should be executed. If a bit for which programming has been judged to be completed is

read as 1 in a subsequent verify-read, a write pulse should again be applied to that bit.

5. The period for which the P bit in FLMCR1 is set (the write pulse width) should be changed

according to the degree of progress through the program/program-verify procedure. For

detailed wait time specifications, see section 23.7, Flash Memory Characteristics.

Item Symbol Item Symbol

Wait time after tsp When reprogramming loop count (n) is 1 to 6 tsp30

P bit setting When reprogramming loop count (n) is 7 or more tsp200

In case of additional programming processing*tsp10

Note: *Additional programming processing is necessary only when the reprogramming loop count

(n) is 1 to 6.

6. The program/program-verify flowchart for the LSI is shown in figure 20-11.

To cover the points noted above, bits on which reprogramming processing is to be executed,

and bits on which additional programming is to be executed, must be determined as shown

below.

Since reprogram data and additional-programming data vary according to the progress of the

programming procedure, it is recommended that the following data storage areas (128 bytes

each) be provided in RAM.

685

Reprogram Data Computation Table

(D)

Result of Verify-Read

after Write Pulse

Application (V) (X)

Result of Operation Comments

0 0 1 Programming completed: reprogramming

processing not to be executed

0 1 0 Programming incomplete: reprogramming

processing to be executed

10 1 

1 1 1 Still in erased state: no action

Legend

(D): Source data of bits on which programming is executed

(X): Source data of bits on which reprogramming is executed

Additional-Programming Data Computation Table

(X')

Result of Verify-Read

after Write Pulse

Application (V) (Y)

Result of Operation Comments

0 0 0 Programming by write pulse application

judged to be completed: additional

programming processing to be executed

0 1 1 Programming by write pulse application

incomplete: additional programming

processing not to be executed

1 0 1 Programming already completed: additional

programming processing not to be executed

1 1 1 Still in erased state: no action

Legend

(Y): Data of bits on which additional programming is executed

(X'): Data of bits on which reprogramming is executed in a certain reprogramming loop

7. It is necessary to execute additional programming processing during the course of the LSI

program/program-verify procedure. However, once 128-byte-unit programming is finished,

additional programming should not be carried out on the same address area. When executing

reprogramming, an erase must be executed first. Note that normal operation of reads, etc., is

not guaranteed if additional programming is performed on addresses for which a

program/program-verify operation has finished.

686

START

End of programming

Set SWE bit in FLMCR1

Start of programming

Write pulse application subroutine

Wait (tsswe) µs

Sub-Routine Write Pulse

End Sub

Set PSU bit in FLMCR1

WDT enable

Disable WDT

Number of Writes n

998

999

1000

Note *6: Write Pulse Width

Write Time (tsp) µsec

200

Wait (tspsu) µs

Set P bit in FLMCR1

Wait (tsp) µs

Clear P bit in FLMCR1

Wait (tcp) µs

Clear PSU bit in FLMCR1

Wait (tcpsu) µs

n= 1

m= 0

No No

Yes

Wait (tspv) µs

Wait (tspvr) µs

Start of programming

End of programming

*5*7

Wait (tcpv) µs

Write pulse

Sub-Routine-Call

Set PV bit in FLMCR1

H'FF dummy write to verify address

Read verify data

Write data =

verify data?

Transfer reprogram data to reprogram data area

Reprogram data computation

Transfer additional-programming data to

additional-programming data area

Additional-programming data computation

Clear PV bit in FLMCR1

Clear SWE bit in FLMCR1

m = 1

Reprogram

See Note *6 for pulse width

m= 0 ?

Increment address

Programming failure

Yes

Clear SWE bit in FLMCR1

Wait (tcswe) µs

Yes

6 ≥ n?

Yes

6 ≥ n ?

Wait (tcswe) µs

n ≥ (N)?

n ← n + 1

Original Data

(D) Verify Data

(V) Reprogram Data

(X) Comments

Programming completed

Still in erased state; no action

Programming incomplete;

reprogram

Note: Use a 10 µs write pulse for additional programming.

Write 128-byte data in RAM reprogram

data area consecutively to flash memory

RAM

Program data storage

area (128 bytes)

Reprogram data storage

area (128 bytes)

Additional-programming

data storage area

(128 bytes)

Store 128-byte program data in program

data area and reprogram data area

Write Pulse (Additional programming)

Sub-Routine-Call

128-byte

data verification completed?

Successively write 128-byte data from additional-

programming data area in RAM to flash memory

Reprogram Data Computation Table

Reprogram Data

(X')

Verify Data

(V)

Additional-

Programming Data

(Y)

000

Comments

Additional programming

to be executed

Additional programming

not to be executed

Additional programming

not to be executed

Additional programming

not to be executed

100

Additional-Programming Data Computation Table

Perform programming in the erased state.

Do not perform additional programming

on previously programmed addresses.

Notes: *1 Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80.

A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.

*2 Verify data is read in 16-bit (word) units.

*3 Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). Bits for

which the reprogram data is 0 are programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be subjected to

programming once again if the result of the subsequent verify operation is NG.

*4 A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM.

The contents of the reprogram data area and additional data area are modified as programming proceeds.

*5 A write pulse of 30 µs or 200 µs is applied according to the progress of the programming operation. See Note *6 for details of the pulse widths. When writing of

additional-programming data is executed, a 10 µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.

*7 The wait times and value of N are shown in section 23.7, Flash Memory characteristics.

Figure 20-11 Program/Program-Verify Flowchart (128-Byte Programming)

687

20.7.3 Erase Mode

When erasing flash memory, the single-block erase flowchart shown in figure 20-12 should be

followed.

The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and

the maximum number of erase operations (N) are shown in table 23-10 in section 23.7, Flash

Memory Characteristics.

To erase flash memory contents, make a 1-bit setting for the flash memory area to be erased in

erase block register 1 and 2 (EBR1, EBR2) at least (tsswe) µs after setting the SWE bit to 1 in

FLMCR1. Next, the watchdog timer (WDT) is set to prevent overerasing due to program

runaway, etc. Set a value greater than (tse) ms + (tsesu + tce + tcesu

) µs as the WDT overflow period.

Preparation for entering erase mode (erase setup) is performed next by setting the ESU bit in

FLMCR1. The operating mode is then switched to erase mode by setting the E bit in FLMCR1

after the elapse of at least (tsesu) µs. The time during which the E bit is set is the flash memory

erase time. Ensure that the erase time does not exceed (tse) ms.

Note: With flash memory erasing, preprogramming (setting all memory data in the memory to

be erased to all 0) is not necessary before starting the erase procedure.

20.7.4 Erase-Verify Mode

In erase-verify mode, data is read after memory has been erased to check whether it has been

correctly erased.

After the elapse of the fixed erase time, clear the E bit in FLMCR1, then wait for at least (tce) µs

before clearing the ESU bit to exit erase mode. After exiting erase mode, the watchdog timer

setting is also cleared. The operating mode is then switched to erase-verify mode by setting the

EV bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be

made to the addresses to be read. The dummy write should be executed after the elapse of (tsev) µs

or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at

the latched address is read. Wait at least (tsevr) µs after the dummy write before performing this

read operation. If the read data has been erased (all 1), a dummy write is performed to the next

address, and erase-verify is performed. If the read data is unerased, set erase mode again, and

repeat the erase/erase-verify sequence as before. The maximum number of repetitions of the

erase/erase-verify sequence is indicated by the maximum erase count (N). When verification is

completed, exit erase-verify mode, and wait for at least (tcev) µs. If erasure has been completed on

all the erase blocks, clear the SWE bit in FLMCR1, and leave a wait time of at least (tcswe) µs.

If erasing multiple blocks, set a single bit in EBR1/EBR2 for the next block to be erased, and

repeat the erase/erase-verify sequence as before.

688

End of erasing

Start

Set SWE bit in FLMCR1

Set ESU bit in FLMCR1

Set E bit in FLMCR1

Wait (tsswe) µs

Wait (tsesu) µs

n = 1

Set EBR1 or EBR2

Enable WDT

*3, *4

*5*5

Wait (tse) ms

Wait (tce) µs

Wait (tcesu) µs

Wait (tsev) µs

Set block start address as verify address

Wait (tsevr) µs

Wait (tcev) µs

Start of erase

Clear E bit in FLMCR1

Clear ESU bit in FLMCR1

Set EV bit in FLMCR1

H'FF dummy write to verify address

Read verify data

Clear EV bit in FLMCR1

Wait (tcev) µs

Clear EV bit in FLMCR1

Clear SWE bit in FLMCR1

Disable WDT

Erase halted

Verify data = all 1s?

Last address of block?

Erase failure

Clear SWE bit in FLMCR1

n ≥ (N)?

Yes

n ← n + 1

Increment

address

Wait (tcswe) µs Wait (tcswe) µs

Notes: *1 Prewriting (setting erase block data to all 0s) is not necessary.

*2 Verify data is read in 16-bit (word) units.

*3 Make only a single-bit specification in the erase block registers (EBR1 and EBR2). Two or more bits must not be set simultaneously.

*4 Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn.

*5 The wait times and the value of N are shown in section 23.7, Flash Memory Characteristics.

Perform erasing in block units.

Figure 20-12 Erase/Erase-Verify Flowchart (Single Block Erase)

689

20.8 Protection

There are three kinds of flash memory program/erase protection: hardware protection, software

protection, and error protection.

20.8.1 Hardware Protection

Hardware protection refers to a state in which programming/erasing of flash memory is forcibly

disabled or aborted. Hardware protection is reset by settings in flash memory control register 1

(FLMCR1), flash memory control register 2 (FLMCR2), erase block register 1 (EBR1), and erase

block register 2 (EBR2). The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained in the

error-protected state. (See table 20-7.)

Table 20-7 Hardware Protection

Functions

Item Description Program Erase

FWE pin protection • When a low level is input to the FWE pin,

FLMCR1, FLMCR2, (except bit FLER)

EBR1, and EBR2 are initialized, and the

program/erase-protected state is entered.

Yes Yes

Reset/standby

protection • In a reset (including a WDT reset) and in

standby mode, FLMCR1, FLMCR2, EBR1,

and EBR2 are initialized, and the

program/erase-protected state is entered.

• In a reset via the RES pin, the reset state

is not entered unless the RES pin is held

low until oscillation stabilizes after

powering on. In the case of a reset during

operation, hold the RES pin low for the

RES pulse width specified in the AC

Characteristics section.

Yes Yes

690

20.8.2 Software Protection

Software protection can be implemented by setting the SWE bit in FLMCR1, erase block register

1 (EBR1), erase block register 2 (EBR2), and the RAMS bit in the RAM emulation register

(RAMER). When software protection is in effect, setting the P or E bit in flash memory control

8.)

Table 20-8 Software Protection

Functions

Item Description Program Erase

SWE bit protection • Setting bit SWE in FLMCR1 to 0 will place

area H'000000 to H'01FFFF in the

program/erase-protected state. (Execute

the program in the on-chip RAM, external

memory)

Yes Yes

Block specification

protection • Erase protection can be set for individual

blocks by settings in erase block register 1

(EBR1) and erase block register 2 (EBR2).

• Setting EBR1 and EBR2 to H'00 places all

blocks in the erase-protected state.

—Yes

Emulation protection • Setting the RAMS bit to 1 in the RAM

emulation register (RAMER) places all

blocks in the program/erase-protected

state.

Yes Yes

691

20.8.3 Error Protection

In error protection, an error is detected when H8S/2646 runaway occurs during flash memory

programming/erasing, or operation is not performed in accordance with the program/erase

algorithm, and the program/erase operation is aborted. Aborting the program/erase operation

prevents damage to the flash memory due to overprogramming or overerasing.

If the LSI malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in

FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2

settings are retained, but program mode or erase mode is aborted at the point at which the error

occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However,

PV and EV bit setting is enabled, and a transition can be made to verify mode.

FLER bit setting conditions are as follows:

1. When the flash memory of the relevant address area is read during programming/erasing

(including vector read and instruction fetch)

2. Immediately after exception handling (excluding a reset) during programming/erasing

3. When a SLEEP instruction (including software standby) is executed during

programming/erasing

4. When the CPU releases the bus to the DTC

Error protection is released only by a reset and in hardware standby mode.

692

Figure 20-13 shows the flash memory state transition diagram.

RD VF PR ER FLER = 0

Error

occurrence

RES = 0 or HSTBY = 0

RES = 0 or

HSTBY = 0

RD VF PR ER FLER = 0

Program mode

Erase mode Reset or standby

(hardware protection)

RD VF PR ER FLER = 1 RD VF PR ER FLER = 1

Error protection mode Error protection mode

(software standby)

Software

standby mode

FLMCR1, FLMCR2, (except bit FLER)

EBR1, EBR2 initialization state

FLMCR1, FLMCR2,

EBR1, EBR2

initialization state

Software standby

mode release

RD: Memory read possible

VF: Verify-read possible

PR: Programming possible

ER: Erasing possible

RD: Memory read not possible

VF: Verify-read not possible

PR: Programming not possible

ER: Erasing not possible

Legend

RES = 0 or

HSTBY = 0

Error occurrence

(software standby)

Figure 20-13 Flash Memory State Transitions

693

20.9 Flash Memory Emulation in RAM

Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped

onto the flash memory area so that data to be written to flash memory can be emulated in RAM in

real time. After the RAMER setting has been made, accesses cannot be made from the flash

memory area or the RAM area overlapping flash memory. Emulation can be performed in user

mode and user program mode. Figure 20-14 shows an example of emulation of real-time flash

memory programming.

Start of emulation program

End of emulation program

Tuning OK?

Yes

Set RAMER

Write tuning data to overlap

RAM

Execute application program

Clear RAMER

Write to flash memory emulation

block

Figure 20-14 Flowchart for Flash Memory Emulation in RAM

694

H'000000

H'000400

H'000800

H'000C00

H'001000

H'01FFFF

Flash memory

EB4 to EB9

EB0

EB1

EB2

EB3

H'FFE000

H'FFE3FF

H'FFEFBF

On-chip RAM

This area can be accessed

from both the RAM area

and flash memory area

Figure 20-15 Example of RAM Overlap Operation

Example in which Flash Memory Block Area EB0 is Overlapped

1. Set bits RAMS, RAM2 to RAM0 in RAMER to 1, 0, 0, 0, to overlap part of RAM onto the

area (EB0) for which real-time programming is required.

2. Real-time programming is performed using the overlapping RAM.

3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap.

4. The data written in the overlapping RAM is written into the flash memory space (EB0).

Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks

regardless of the value of RAM2 to RAM0 (emulation protection). In this state, setting

the P or E bit in flash memory control register 1 (FLMCR1), will not cause a transition

to program mode or erase mode. When actually programming or erasing a flash

memory area, the RAMS bit should be cleared to 0.

2. A RAM area cannot be erased by execution of software in accordance with the erase

algorithm while flash memory emulation in RAM is being used.

3. Block area EB0 contains the vector table. When performing RAM emulation, the

vector table is needed in the overlap RAM.

695

20.10 Interrupt Handling when Programming/Erasing Flash Memory

All interrupts, including NMI interrupt is disabled when flash memory is being programmed or

erased (when the P or E bit is set in FLMCR1), and while the boot program is executing in boot

mode*1, to give priority to the program or erase operation. There are three reasons for this:

1. Interrupt during programming or erasing might cause a violation of the programming or

erasing algorithm, with the result that normal operation could not be assured.

2. In the interrupt exception handling sequence during programming or erasing, the vector would

not be read correctly*2, possibly resulting in MCU runaway.

3. If interrupt occurred during boot program execution, it would not be possible to execute the

normal boot mode sequence.

For these reasons, in on-board programming mode alone there are conditions for disabling

interrupt, as an exception to the general rule. However, this provision does not guarantee normal

erasing and programming or MCU operation. All requests, including NMI interrupt, must

therefore be restricted inside and outside the MCU when programming or erasing flash memory.

NMI interrupt is also disabled in the error-protection state while the P or E bit remains set in

FLMCR1.

Notes: *1 Interrupt requests must be disabled inside and outside the MCU until the programming

control program has completed programming.

*2 The vector may not be read correctly in this case for the following two reasons:

• If flash memory is read while being programmed or erased (while the P or E bit is

set in FLMCR1), correct read data will not be obtained (undetermined values will

be returned).

• If the interrupt entry in the vector table has not been programmed yet, interrupt

exception handling will not be executed correctly.

20.11 Flash Memory Programmer Mode

Programs and data can be written and erased in programmer mode as well as in the on-board

programming modes. In programmer mode, flash memory read mode, auto-program mode, auto-

erase mode, and status read mode are supported. In auto-program mode, auto-erase mode, and

status read mode, a status polling procedure is used, and in status read mode, detailed internal

signals are output after execution of an auto-program or auto-erase operation.

In programmer mode, set the mode pins to programmer mode (see table 20-9) and input a 12 MHz

input clock.

Table 20-9 shows the pin settings for programmer mode. For the pin names in programmer mode,

see figure 20-17.

696

Table 20-9 Programmer Mode Pin Settings

Pin Names Settings

Mode pins: MD2, MD1, MD0 Low level input to MD2, MD1, and MD0.

Mode setting pins: PF0, P16, P14 High level input to PF0, low level input to P16 and P14

FWE pin High level input (in auto-program and auto-erase

modes)

RES pin Reset circuit

XTAL, EXTAL, PLLCAP, PLLVSS pins Oscillator circuit

VCL Internal step-down circuit

20.11.1 Socket Adapter Pin Correspondence Diagram

Connect the socket adapter to the chip as shown in figure 20-17. This will enable conversion to a

40-pin arrangement. The on-chip ROM memory map is shown in figure 20-16, and the socket

adapter pin correspondence diagram in figure 20-17.

'000000

ddresses in

CU mode Addresses in

programmer mode

'01FFFF

H'00000

H'1FFFF

On-chip ROM space

128 kbytes

Figure 20-16 On-Chip ROM Memory Map

697

H8S/2646F-ZTAT, H8S/2648F-ZTAT Socket Adapter

(Conversion to

40-Pin

Arrangement)

Pin No. FP-144 Pin Name

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

D10

D11

D12

D13

D14

D15

PE7

PE5

PE6

FWE

40-Pin Socket on Writer

Pin No. Pin Name

1, 40

11, 30

5, 6, 7

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

FWE

VCC

VSS

A20

PE3

RES

XTAL

EXTAL

PLLCAP

PLLVSS

VCL

N.C.(OPEN)

Other than the above

1, 21, 56, 66, 84, 85, 91, 92, 98, 119,

126, 127

8, 12, 40, 51, 61, 71, 72, 73, 74, 88,

89, 95, 105, 107, 123, 144

VCC

, LPVcc, AVcc,

Vref, PWMVcc etc

VSS, AVss,

PWMVss etc

Oscillator

circuit

PLL circuit

Legend

FWE:

I/O0 to 7:

A20 to 0:

OE:

CE:

WE:

Flash write enable

Data input/output

Address input

Output enable

Chip enable

Write enable

Capacitor

Power-on

reset circuit

Note: This drawing indicates pin correspondences and does not show the entire circuitry of the socket adapter.

698

Figure 20-17 Socket Adapter Pin Correspondence Diagram

20.11.2 Programmer Mode Operation

Table 20-10 shows how the different operating modes are set when using programmer mode, and

table 20-11 lists the commands used in programmer mode. Details of each mode are given below.

• Memory Read Mode

Memory read mode supports byte reads.

• Auto-Program Mode

Auto-program mode supports programming of 128 bytes at a time. Status polling is used to

confirm the end of auto-programming.

• Auto-Erase Mode

Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used

to confirm the end of auto-programming.

• Status Read Mode

Status polling is used for auto-programming and auto-erasing, and normal termination can be

confirmed by reading the I/O6 signal. In status read mode, error information is output if an

error occurs.

Table 20-10 Settings for Various Operating Modes in Programmer Mode

Pin Names

Mode FWE CE OE WE I/O7– I/O0 A18–A0

Read H or L L L H Data output Ain

Output disable H or L L H H Hi-Z X

Command write H or L*3L H L Data input Ain*2

Chip disable*1H or L H X X Hi-Z X

Notes: *1 Chip disable is not a standby state; internally, it is an operation state.

*2 Ain indicates that there is also address input in auto-program mode.

*3 For command writes in auto-program and auto-erase modes, input a high level to the

FWE pin.

699

Table 20-11 Programmer Mode Commands

Number 1st Cycle 2nd Cycle

Command Name of Cycles Mode Address Data Mode Address Data

Memory read mode 1 + n Write X H'00 Read RA Dout

Auto-program mode 129 Write X H'40 Write WA Din

Auto-erase mode 2 Write X H'20 Write X H'20

Status read mode 2 Write X H'71 Write X H'71

Notes: 1. In auto-program mode, 129 cycles are required for command writing by a simultaneous

128-byte write.

2. In memory read mode, the number of cycles depends on the number of address write

cycles (n).

20.11.3 Memory Read Mode

1. After completion of auto-program/auto-erase/status read operations, a transition is made to the

command wait state. When reading memory contents, a transition to memory read mode must

first be made with a command write, after which the memory contents are read.

2. In memory read mode, command writes can be performed in the same way as in the command

wait state.

3. Once memory read mode has been entered, consecutive reads can be performed.

4. After powering on, memory read mode is entered.

Table 20-12 AC Characteristics in Transition to Memory Read Mode

(Conditions: VCC = 5.0 V ±0.5 V, VSS = 0 V, Ta = 25°C ±5°C)

Item Symbol Min Max Unit

Command write cycle tnxtc 20 —µs

CE hold time tceh 0—ns

CE setup time tces 0—ns

Data hold time tdh 50 —ns

Data setup time tds 50 —ns

Write pulse width twep 70 —ns

WE rise time tr—30 ns

WE fall time tf—30 ns

700

A18–A0

I/O7–I/O0

Note: Data is latched on the rising edge of WE.

tceh

twep

tftr

tces tnxtc

Address stable

tds tdh

Command write Memory read mode

Figure 20-18 Timing Waveforms for Memory Read after Memory Write

Table 20-13 AC Characteristics in Transition from Memory Read Mode to Another Mode

(Conditions: VCC = 5.0 V ±0.5 V, VSS = 0 V, Ta = 25°C ±5°C)

Item Symbol Min Max Unit

Command write cycle tnxtc 20 —µs

CE hold time tceh 0—ns

CE setup time tces 0—ns

Data hold time tdh 50 —ns

Data setup time tds 50 —ns

Write pulse width twep 70 —ns

WE rise time tr—30 ns

WE fall time tf—30 ns

701

A18–A0

I/O7–I/O0

Note: Do not enable WE and OE at the same time.

tceh

twep

tftr

tces

tnxtc

Address stable

tds tdh

Other mode command writeMemory read mode

Figure 20-19 Timing Waveforms in Transition from Memory Read Mode to Another Mode

Table 20-14 AC Characteristics in Memory Read Mode (Conditions: VCC = 5.0 V ±0.5 V,

VSS = 0 V, Ta = 25°C ±5°C)

Item Symbol Min Max Unit

Access time tacc —20 µs

CE output delay time tce —150 ns

OE output delay time toe —150 ns

Output disable delay time tdf —100 ns

Data output hold time toh 5—ns

A18–A0

I/O7–I/O0

VIL

VIH tacc tacc

toh toh

Address stableAddress stable

Figure 20-20 CE and OE Enable State Read Timing Waveforms

702

A18–A0

I/O7–I/O0

VIH tacc

tce

toe toe

tce

tacc

toh tdf tdf

toh

Address stableAddress stable

Figure 20-21 CE and OE Clock System Read Timing Waveforms

20.11.4 Auto-Program Mode

1. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out

by executing 128 consecutive byte transfers.

2. A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this

case, H'FF data must be written to the extra addresses.

3. The lower 7 bits of the transfer address must be low. If a value other than an effective address

is input, processing will switch to a memory write operation but a write error will be flagged.

4. Memory address transfer is performed in the second cycle (figure 20-22). Do not perform

transfer after the third cycle.

5. Do not perform a command write during a programming operation.

6. Perform one auto-program operation for a 128-byte block for each address. Two or more

additional programming operations cannot be performed on a previously programmed address

block.

7. Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode

can also be used for this purpose (I/O7 status polling uses the auto-program operation end

decision pin).

8. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long

as the next command write has not been performed, reading is possible by enabling CE and

OE.

703

Table 20-15 AC Characteristics in Auto-Program Mode (Conditions: VCC = 5.0 V ±0.5 V,

VSS = 0 V, Ta = 25°C ±5°C)

Item Symbol Min Max Unit

Command write cycle tnxtc 20 —µs

CE hold time tceh 0—ns

CE setup time tces 0—ns

Data hold time tdh 50 —ns

Data setup time tds 50 —ns

Write pulse width twep 70 —ns

Status polling start time twsts 1—ms

Status polling access time tspa —150 ns

Address setup time tas 0—ns

Address hold time tah 60 —ns

Memory write time twrite 1 3000 ms

Write setup time tpns 100 —ns

Write end setup time tpnh 100 —ns

WE rise time tr—30 ns

WE fall time tf—30 ns

A18–A0

FWE

I/O7

I/O6

I/O5–I/O0

tpns

twep

tds tdh

tftrtas tah twsts

twrite

tspa

tces tceh tnxtc tnxtc

tpnh

Address

stable

H'40 H'00

Data transfer

1 to 128 bytes

Write operation end decision signal

Write normal end decision signal

Figure 20-22 Auto-Program Mode Timing Waveforms

704

20.11.5 Auto-Erase Mode

1. Auto-erase mode supports only entire memory erasing.

2. Do not perform a command write during auto-erasing.

3. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also

be used for this purpose (I/O7 status polling uses the auto-erase operation end decision pin).

4. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long

as the next command write has not been performed, reading is possible by enabling CE and

OE.

Table 20-16 AC Characteristics in Auto-Erase Mode (Conditions: VCC = 5.0 V ±0.5 V,

VSS = 0 V, Ta = 25°C ±5°C)

Item Symbol Min Max Unit

Command write cycle tnxtc 20 —µs

CE hold time tceh 0—ns

CE setup time tces 0—ns

Data hold time tdh 50 —ns

Data setup time tds 50 —ns

Write pulse width twep 70 —ns

Status polling start time tests 1—ms

Status polling access time tspa —150 ns

Memory erase time terase 100 40000 ms

Erase setup time tens 100 —ns

Erase end setup time tenh 100 —ns

WE rise time tr—30 ns

WE fall time tf—30 ns

705

A18–A0

FWE

I/O7

I/O6

I/O5–I/O0

tens

twep

tds tdh

tftrtests

terase

tspa

tces tceh tnxtc tnxtc

tenh

H'20 H'20 H'00

;;;;

Erase end

decision signal

Erase normal

end

decision signal

Figure 20-23 Auto-Erase Mode Timing Waveforms

706

20.11.6 Status Read Mode

1. Status read mode is provided to identify the kind of abnormal end. Use this mode when an

abnormal end occurs in auto-program mode or auto-erase mode.

2. The return code is retained until a command write other than a status read mode command

write is executed.

Table 20-17 AC Characteristics in Status Read Mode (Conditions: VCC = 5.0 V ±0.5 V,

VSS = 0 V, Ta = 25°C ±5°C)

Item Symbol Min Max Unit

Read time after command write tnxtc 20 —µs

CE hold time tceh 0—ns

CE setup time tces 0—ns

Data hold time tdh 50 —ns

Data setup time tds 50 —ns

Write pulse width twep 70 —ns

OE output delay time toe —150 ns

Disable delay time tdf —100 ns

CE output delay time tce —150 ns

WE rise time tr—30 ns

WE fall time tf—30 ns

A18–A0

I/O7–I/O0

wep

ces

ceh

nxtc

ces

H'71

;;;;

wep

H'71

Note: I/O2 and I/O3 are undefined.

Figure 20-24 Status Read Mode Timing Waveforms

707

Table 20-18 Status Read Mode Return Commands

Pin Name I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

Attribute Normal

end

decision

Command

error Program-

ming error Erase

error ——Program-

ming or

erase count

exceeded

Effective

address error

Initial value 00000000

Indications Normal

end: 0

Abnormal

end: 1

Command

error: 1

Otherwise: 0

Program-

ming

error: 1

Otherwise: 0

Erasing

error: 1

Otherwise: 0

——Count

exceeded: 1

Otherwise: 0

Effective

address

error: 1

Otherwise: 0

Note: I/O2 and I/O3 are undefined.

20.11.7 Status Polling

1. The I/O7 status polling flag indicates the operating status in auto-program/auto-erase mode.

2. The I/O6 status polling flag indicates a normal or abnormal end in auto-program/auto-erase

mode.

Table 20-19 Status Polling Output Truth Table

Pin Name During Internal

Operation Abnormal End — Normal End

I/O7 0101

I/O6 0011

I/O0–I/O5 0000

20.11.8 Programmer Mode Transition Time

Commands cannot be accepted during the oscillation stabilization period or the programmer mode

setup period. After the programmer mode setup time, a transition is made to memory read mode.

Table 20-20 Stipulated Transition Times to Command Wait State

Item Symbol Min Max Unit

Standby release (oscillation

stabilization time) tosc1 30 —ms

Programmer mode setup time tbmv 10 —ms

VCC hold time tdwn 0—ms

708

tosc1 tbmv tdwn

VCC

RES

FWE

Memory read

mode

Command

wait state Auto-program mode

Auto-erase mode

Command wait state

Normal/abnormal

end decision

Note: When using other than the automatic write mode and automatic erase mode, drive the FWE

input pin low.

Figure 20-25 Oscillation Stabilization Time, Boot Program Transfer Time, and

Power-Down Sequence

20.11.9 Notes on Memory Programming

1. When programming addresses which have previously been programmed, carry out auto-

erasing before auto-programming.

2. When performing programming using programmer mode on a chip that has been

programmed/erased in an on-board programming mode, auto-erasing is recommended before

carrying out auto-programming.

Notes: 1. The flash memory is initially in the erased state when the device is shipped by Hitachi.

For other chips for which the erasure history is unknown, it is recommended that auto-

erasing be executed to check and supplement the initialization (erase) level.

2. Auto-programming should be performed once only on the same address block.

Additional programming cannot be performed on previously programmed address

blocks.

709

20.12 Flash Memory and Power-Down States

In addition to its normal operating state, the flash memory has power-down states in which power

consumption is reduced by halting part or all of the internal power supply circuitry.

There are three flash memory operating states:

(1) Normal operating mode: The flash memory can be read and written to.

(2) Power-down mode: Part of the power supply circuitry is halted, and the flash memory can be

read when the LSI is operating on the subclock.

(3) Standby mode: All flash memory circuits are halted, and the flash memory cannot be read or

written to.

States (2) and (3) are flash memory power-down states. Table 20-21 shows the correspondence

between the operating states of the LSI and the flash memory.

Table 20-21 Flash Memory Operating States

LSI Operating State Flash Memory Operating State

High-speed mode

Medium-speed mode

Sleep mode

Normal mode (read/write)

Subactive mode

Subsleep mode When PDWND = 0: Power-down mode (read-only)

When PDWND = 1: Normal mode (read-only)

Watch mode

Software standby mode

Hardware standby mode

Standby mode

20.12.1 Notes on Power-Down States

1. When the flash memory is in a power-down state, part or all of the internal power supply

circuitry is halted. Therefore, a power supply circuit stabilization period must be provided

when returning to normal operation. When the flash memory returns to its normal operating

state from a power-down state, bits STS2 to STS0 in SBYCR must be set to provide a wait

time of at least 20 µs (power supply stabilization time), even if an oscillation stabilization

period is not necessary.

2. In a power-down state, FLMCR1, FLMCR2, EBR1, EBR2, RAMER, and FLPWCR cannot be

read from or written to.

710

20.13 Flash Memory Programming and Erasing Precautions

Precautions concerning the use of on-board programming mode, the RAM emulation function, and

programmer mode are summarized below.

1. Use the specified voltages and timing for programming and erasing.

Applied voltages in excess of the rating can permanently damage the device. Use a PROM

programmer that supports the Hitachi microcomputer device type with 128-kbyte on-chip flash

memory (FZTAT256V3A).

Do not select the HN27C4096 setting for the PROM programmer, and only use the specified

socket adapter. Failure to observe these points may result in damage to the device.

2. Powering on and off (see figures 20-26 to 20-28)

Do not apply a high level to the FWE pin until VCC has stabilized. Also, drive the FWE pin low

before turning off VCC.

When applying or disconnecting VCC power, fix the FWE pin low and place the flash memory

in the hardware protection state.

The power-on and power-off timing requirements should also be satisfied in the event of a

power failure and subsequent recovery.

3. FWE application/disconnection (see figures 20-26 to 20-28)

FWE application should be carried out when MCU operation is in a stable condition. If MCU

operation is not stable, fix the FWE pin low and set the protection state.

The following points must be observed concerning FWE application and disconnection to

prevent unintentional programming or erasing of flash memory:

•Apply FWE when the VCC voltage has stabilized within its rated voltage range.

Apply FWE when oscillation has stabilized (after the elapse of the oscillation settling

time).

•In boot mode, apply and disconnect FWE during a reset.

•In user program mode, FWE can be switched between high and low level regardless of a

reset state.

FWE input can also be switched during execution of a program in flash memory.

•Do not apply FWE if program runaway has occurred.

•Disconnect FWE only when the SWE, ESU, PSU, EV, PV, P, and E bits in FLMCR1 are

cleared.

Make sure that the SWE, ESU, PSU, EV, PV, P, and E bits are not set by mistake when

applying or disconnecting FWE.

711

4. Do not apply a constant high level to the FWE pin.

Apply a high level to the FWE pin only when programming or erasing flash memory. A system

configuration in which a high level is constantly applied to the FWE pin should be avoided.

Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to

prevent overprogramming or overerasing due to program runaway, etc.

5. Use the recommended algorithm when programming and erasing flash memory.

The recommended algorithm enables programming and erasing to be carried out without

subjecting the device to voltage stress or sacrificing program data reliability. When setting the

P or E bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against

program runaway, etc.

6. Do not set or clear the SWE bit during execution of a program in flash memory.

Do not set or clear the SWE bit during execution of a program in flash memory. Wait for at

least 100 µs after clearing the SWE bit before executing a program or reading data in flash

memory. When the SWE bit is set, data in flash memory can be rewritten, but when SWE = 1,

flash memory can only be read in program-verify or erase-verify mode. Access flash memory

only for verify operations (verification during programming/erasing). Do not clear the SWE bit

during programming, erasing, or verifying.

Similarly, when using the RAM emulation function while a high level is being input to the

FWE pin, the SWE bit must be cleared before executing a program or reading data in flash

memory. However, the RAM area overlapping flash memory space can be read and written to

regardless of whether the SWE bit is set or cleared.

7. Do not use interrupts while flash memory is being programmed or erased.

All interrupt requests, including NMI, should be disabled during FWE application to give

priority to program/erase operations.

8. Do not perform additional programming. Erase the memory before reprogramming.

In on-board programming, perform only one programming operation on a 128-byte

programming unit block. In programmer mode, also, perform only one programming operation

on a 128-byte programming unit block. Further programming must only be executed after this

programming unit block has been erased.

9. Before programming, check that the chip is correctly mounted in the PROM

programmer.

Overcurrent damage to the device can result if the index marks on the PROM programmer

socket, socket adapter, and chip are not correctly aligned.

10.Do not touch the socket adapter or chip during programming.

Touching either of these can cause contact faults and write errors.

712

Period during which flash memory access is prohibited

(x: Wait time after setting SWE bit)*2

Period during which flash memory can be programmed

(Execution of program in flash memory prohibited, and data reads other than verify operations

prohibited)

VCC

FWE

tOSC1 Min 0 µs

tMDS*3

MD2 to MD0*1

RES

SWE bit

SWE set SWE cleared

Program-

ming/

erasing

possible

Wait time:

xWait time:

100 µs

Min 0 µs

Notes: *1 Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until power-

off by pulling the pins up or down.

*2 See section 23.7, Flash Memory Characteristics.

*3 Mode programming setup time tMDS (min) = 200 ns

Figure 20-26 Power-On/Off Timing (Boot Mode)

713

Period during which flash memory access is prohibited

(x: Wait time after setting SWE bit)*2

Period during which flash memory can be programmed

(Execution of program in flash memory prohibited, and data reads other than verify operations

prohibited)

VCC

FWE

tOSC1 Min 0 µs

MD2 to MD0*1

RES

SWE bit

SWE set SWE cleared

Program-

ming/

erasing

possible

Wait time:

xWait time:

100 µs

tMDS*3

Notes: *1 Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until power-

off by pulling the pins up or down.

*2 See section 23.7, Flash Memory Characteristics.

*3 Mode programming setup time tMDS (min) = 200 ns

Figure 20-27 Power-On/Off Timing (User Program Mode)

714

Period during which flash memory access is prohibited

(x: Wait time after setting SWE bit)*3

Period during which flash memory can be programmed

(Execution of program in flash memory prohibited, and data reads other than verify operations prohibited)

VCC

FWE

tOSC1

Min 0µs

tMDS tMDS*2

tMDS

tRESW

MD2 to MD0

RES

SWE bit

Mode

change*1User

mode

Boot

mode User program mode

SWE set SWE

cleared

Programming/

erasing possible

Wait time: x

Wait time: 100 µs

Programming/

erasing possible

Wait time: x

Wait time: 100 µs

Programming/

erasing possible

Wait time: x

Programming/

erasing possible

Wait time: x

Wait time: 100 µs

Mode

change*1User

mode User program

mode

Notes: *1 When entering boot mode or making a transition from boot mode to another mode, mode switching must be carried

out by means of RES input. The state of ports with multiplexed address functions and bus control output pins

(AS, RD, WR) will change during this switchover interval (the interval during which the RES pin input is low),

and therefore these pins should not be used as output signals during this time.

*2 When making a transition from boot mode to another mode, a mode programming setup time, tMDS (min), of 200 ns

is necessary with respect to the RES clearance timing.

*3 See section 23.7, Flash Memory Characteristics.

Figure 20-28 Mode Transition Timing

(Example: Boot Mode →→

→→ User Mode ↔↔

↔↔ User Program Mode)

715

Section 21 Clock Pulse Generator

21.1 Overview

The H8S/2646 Series has a built-in clock pulse generator (CPG) that generates the system clock

(ø), the bus master clock, and internal clocks.

The clock pulse generator consists of an oscillator, PLL (phase-locked loop) circuit, clock

selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock

oscillator, and waveform shaping circuit. The frequency can be changed by means of the PLL

circuit in the CPG. Frequency changes are performed by software by means of settings in the

system clock control register (SCKCR) and low-power control register (LPWRCR).

21.1.1 Block Diagram

Figure 21-1 shows a block diagram of the clock pulse generator.

Legend:

LPWRCR:

SCKCR:

Low-power control register

System clock control register

EXTAL

XTAL

PLL circuit

(×1, ×2, ×4) Medium-

speed

clock divider

System

clock

oscillator Clock

selection

circuit

ø SUB

WDT1 count clock

System clock

to ø pin Internal clock to

supporting modules Bus master clock

to CPU and DTC

ø/2 to

ø/32

SCK2 to SCK0

SCKCR

STC1, STC0

OSC1

OSC2

Waveform

Generation

Circuit

Subclock

oscillator

LPWRCR

Bus

master

clock

selection

circuit

Figure 21-1 Block Diagram of Clock Pulse Generator

716

21.1.2 Register Configuration

The clock pulse generator is controlled by SCKCR and LPWRCR. Table 21-1 shows the register

configuration.

Table 21-1 Clock Pulse Generator Register

Name Abbreviation R/W Initial Value Address*

System clock control register SCKCR R/W H'00 H'FDE6

Low-power control register LPWRCR R/W H'00 H'FDEC

Note:*Lower 16 bits of the address.

21.2 Register Descriptions

21.2.1 System Clock Control Register (SCKCR)

PSTOP

R/W

—

STCS

R/W

SCK0

R/W

SCK2

R/W

SCK1

R/W

Bit

Initial value

R/W

SCKCR is an 8-bit readable/writable register that performs ø clock output control and medium-

speed mode control, selection of operation when the PLL circuit frequency multiplication factor is

changed, and medium-speed mode control.

SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—ø Clock Output Disable (PSTOP): Controls ø output.

Bit 7 Description

PSTOP

High Speed Mode,

Medium Speed Mode,

Sub-Active Mode Sleep Mode,

Sub-Sleep Mode

Software Standby

Mode, Watch Mode,

and Direct Transition Hardware

Standby Mode

0ø output (initial value) ø output Fixed high High impedance

1 Fixed high Fixed high Fixed high High impedance

Bits 6 to 4—Reserved: These bits are always read as 0 and cannot be modified.

717

Bit 3—Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation

when the PLL circuit frequency multiplication factor is changed.

Bit 3

STCS Description

0 Specified multiplication factor is valid after recovery from software standby mode,

watch mode, or subactive mode (Initial value)

1 Specified multiplication factor is valid immediately after STC bits are rewritten

Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the bus master

clock.

Bit 2 Bit 1 Bit 0

SCK2 SCK1 SCK0 Description

0 0 0 Bus master is in high-speed mode (Initial value)

1 Medium-speed clock is ø/2

1 0 Medium-speed clock is ø/4

1 Medium-speed clock is ø/8

1 0 0 Medium-speed clock is ø/16

1 Medium-speed clock is ø/32

1——

21.2.2 Low-Power Control Register (LPWRCR)

DTON

R/W

LSON

R/W

NESEL

R/W

SUBSTP

R/W

RFCUT

R/W

STC0

R/W

—

R/W

STC1

R/W

Bit

Initial value

Read/Write

LPWRCR is an 8-bit readable/writable register that performs power-down mode control. The

following pertains to bits 1 and 0. For details of the other bits, see section 22.2.3, Low-Power

Control Register (LPWRCR). LPWRCR is initialized to H'00 by a reset and in hardware standby

mode. It is not initialized in software standby mode.

718

Bits 1 and 0—Frequency Multiplication Factor (STC1, STC0): The STC bits specify the

frequency multiplication factor of the PLL circuit.

Bit 1 Bit 0

STC1 STC0 Description

00×1 (Initial value)

1×2

10×4

1 Setting prohibited

Note: Make this setting so that the clock frequency both before and after multiplication is within

the operating frequency range of the LSI.

Note: A system clock frequency multiplied by the multiplication factor (STC1 and STC0) should

not exceed the maximum operating frequency defined in section 23, Electrical

Characteristics.

21.3 Oscillator

A crystal oscillator is used to supply clock pulses.

In either case, the input clock should be from 4 MHz to 20 MHz.

21.3.1 Connecting a Crystal Resonator

Circuit Configuration: A crystal resonator can be connected as shown in the example in figure

21-2. Select the damping resistance Rd according to table 21-2. An AT-cut parallel-resonance

crystal should be used.

EXTAL

XTAL RdCL2

CL1

CL1 = CL2 = 10 to 22pF

ote: CL1 and CL2 are reference values. The capacitance which is used must be decided

by the parasitic capacitance of the board and the results of crystal resonator

evaluation.

Figure 21-2 Connection of Crystal Resonator (Example)

719

Table 21-2 Damping Resistance Value

Frequency (MHz) 4 8 12 16 20

Rd () 500 200 0 0 0

Crystal Resonator: Figure 21-3 shows the equivalent circuit of the crystal resonator. Use a

crystal resonator that has the characteristics shown in table 18-3. The crystal resonator frequency

should not exceed 20 MHz.

XTAL

AT-cut parallel-resonance type

EXTAL

Figure 21-3 Crystal Resonator Equivalent Circuit

Table 21-3 Crystal Resonator Parameters

Frequency (MHz) 4 8 12 16 20

RS max () 120 80 60 50 40

C0 max (pF) 77777

Note on Board Design: When a crystal resonator is connected, the following points should be

noted:

Other signal lines should be routed away from the oscillator circuit to prevent induction from

interfering with correct oscillation. See figure 21-4.

When designing the board, place the crystal resonator and its load capacitors as close as possible

to the XTAL and EXTAL pins.

CL2

Signal A Signal B

CL1

H8S/2646 Series

XTAL

EXTAL

Avoid

Figure 21-4 Example of Incorrect Board Design

720

External circuitry such as that shown below is recommended around the PLL.

PLLCAP

PLLVSS

VCC

VSS

R1: 3 kΩC1: 470 pF

CB: 0.1 µF*

Note: * CB is laminated ceramic capacitors.

(Values are preliminary recommended values.)

Figure 21-5 Points for Attention when Using PLL Oscillation Circuit

Place oscillation stabilization capacitor C1 and resistor R1 close to the PLLCAP pin, and ensure

that no other signal lines cross this line. Supply the C1 ground from PLLVSS.

Separate PLLVSS from the other VSS lines at the board power supply source, and be sure to insert

bypass capacitors CB close to the pins.

721

21.4 PLL Circuit

The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a

factor of 1, 2, or 4. The multiplication factor is set with the STC bits in SCKCR. The phase of the

rising edge of the internal clock is controlled so as to match that at the EXTAL pin. The clock

frequency before and after multiplication must not exceed the maximum operating frequency

range of this LSI.

When the multiplication factor of the PLL circuit is changed, the operation varies according to the

setting of the STCS bit in SCKCR.

When STCS = 0 (initial value), the setting becomes valid after a transition to software standby

mode, watch mode, or subactive mode. The transition time count is performed in accordance with

the setting of bits STS2 to STS0 in SBYCR.

[1] The initial PLL circuit multiplication factor is 1.

[2] A value is set in bits STS2 to STS0 to give the specified transition time.

[3] The target value is set in STC1 and STC0, and a transition is made to software standby mode,

watch mode, or subactive mode.

[4] The clock pulse generator stops and the value set in STC1 and STC0 becomes valid.

[5] Software standby mode, watch mode, or subactive mode is cleared, and a transition time is

secured in accordance with the setting in STS2 to STS0.

[6] After the set transition time has elapsed, the LSI resumes operation using the target

multiplication factor.

If a PC break is set for the SLEEP instruction that causes a transition to software standby mode in

[1], software standby mode is entered and break exception handling is executed after the

oscillation stabilization time. In this case, the instruction following the SLEEP instruction is

executed after execution of the RTE instruction.

When STCS = 1, the LSI operates on the changed multiplication factor immediately after bits

STC1 and STC0 are rewritten.

21.5 Medium-Speed Clock Divider

The medium-speed clock divider divides the system clock to generate ø/2, ø/4, ø/8, ø/16, and ø/32.

21.6 Bus Master Clock Selection Circuit

The bus master clock selection circuit selects the system clock (ø) or one of the medium-speed

clocks (ø/2, ø/4, or ø/8, ø/16, and ø/32) to be supplied to the bus master, according to the settings

of the SCK2 to SCK0 bits in SCKCR.

722

21.7 Subclock Oscillator

Connecting 32.768kHz Quartz Oscillator: To supply a clock to the subclock divider, connect a

32.768kHz quartz oscillator, as shown in figure 21-6. See section 21.3.1, “Notes on Board Design”

for notes on connecting quartz oscillators.

OSC1

OSC2

C1=C2=15pF (typ)*

Note: *C1 and C2 are reference values that include the wiring capacity.

Figure 21-6 Example Connection of 32.768kHz Quartz Oscillator

Figure 21-7 shows the equivalence circuit for a 32.768kHz oscillator.

OSC1 OSC2

CsLsRs

Figure 21-7 Equivalence Circuit for 32.768kHz Oscillator

Handling pins when subclock not required: If no subclock is required, connect the OSC1 pin to

Vss and leave OSC2 open, as shown in figure 21-8.

OSC1

OSC2 Open

Figure 21-8 Pin Handling When Subclock Not Required

723

21.8 Subclock Waveform Generation Circuit

To eliminate noise from the subclock input to OSCI, the subclock is sampled using the dividing

clock ø. The sampling frequency is set using the NESEL bit of LPWRCR. For details, see section

22.2.3, Low-Power Control Register (LPWRCR).

No sampling is performed in sub-active mode, sub-sleep mode, or watch mode.

21.9 Note on Crystal Resonator

Since various characteristics related to the crystal resonator are closely linked to the user’s board

design, thorough evaluation is necessary on the user’s part, for the F-ZTAT version, using the

resonator connection examples shown in this section as a guide. As the resonator circuit ratings

will depend on the floating capacitance of the resonator and the mounting circuit, the ratings

should be determined in consultation with the resonator manufacturer. The design must ensure that

a voltage exceeding the maximum rating is not applied to the oscillator pin.

724

725

Section 22 Power-Down Modes

22.1 Overview

In addition to the normal program execution state, the H8S/2646 Series has nine power-down

modes in which operation of the CPU and oscillator is halted and power dissipation is reduced.

Low-power operation can be achieved by individually controlling the CPU, on-chip supporting

modules, and so on.

The H8S/2646 Series operating modes are as follows:

(1) High-speed mode

(2) Medium-speed mode

(3) Subactive mode

(4) Sleep mode

(5) Subsleep mode

(6) Watch mode

(7) Module stop mode

(8) Software standby mode

(9) Hardware standby mode

(2) to (9) are low power dissipation states. Sleep mode and sub-sleep mode are CPU states,

medium-speed mode is a CPU and bus master state, sub-active mode is a CPU and bus master and

internal peripheral function state, and module stop mode is an internal peripheral function

(including bus masters other than the CPU) state. Some of these states can be combined.

After a reset, the LSI is in high-speed mode with modules other than the DTC in module stop

mode.

Table 22-1 shows the internal state of the LSI in the respective modes. Table 22-2 shows the

conditions for shifting between the low power dissipation modes.

Figure 22-1 is a mode transition diagram.

726

Table 22-1 LSI Internal States in Each Mode

Function High-

Speed Medium-

Speed Sleep Module

Stop Watch Sub-

active Subsleep Software

Standby Hardware

Standby

System clock pulse

generator Function-

ing Function-

ing Halted Halted Halted Halted Halted

Subclock pulse

generator Function-

ing Function-

ing Halted

CPU Instructions

Registers Function-

ing Medium-

speed

operation

Halted

(retained) High/

medium-

speed

operation

Halted

(retained) Subclock

operation Halted

(retained) Halted

(undefined)

External NMI Function- Function- Function- Function- Function- Function- Function- Function- Halted

interrupts IRQ0–IRQ5 ing ing ing ing ing ing ing ing

Peripheral

functions WDT1 Function-

ing Function-

ing Subclock

operation Subclock

operation Halted

(retained) Halted

(reset)

WDT0 Function- Function- Function Halted Subclock Subclock Halted Halted

ing ing ing (retained) operation operation (retained) (reset)

DTC Function- Medium- Function- Halted Halted Halted Halted Halted Halted

ing speed

operation ing (retained) (retained) (retained) (retained) (retained) (reset)

PBC Function-

ing Medium-

speed

operation

Function-

ing Halted

(retained) Halted

(retained) Subclock

operation Halted

(retained) Halted

(reset)

TPU Function- Function- Function- Halted Halted Halted Halted Halted Halted

PPG ing ing ing (retained) (retained) (retained) (retained) (retained) (reset)

SCI0 Function- Function- Function- Halted Halted Halted Halted Halted Halted

SCI1 ing ing ing (reset) (reset) (reset) (reset) (reset) (reset)

PWM

HCAN

A/D

LCD Function-

ing Function-

ing Halted

(retained) Function-

ing*Function-

ing*Halted

(retained) Halted

(reset)

RAM Function-

ing Function-

ing (DTC) Function-

ing Retained Function-

ing Retained Retained Retained

I/O Function-

ing Function-

ing Retained Function-

ing Retained Retained High

impedance

Notes: “Halted (retained)” means that internal register values are retained. The internal state is

“operation suspended.”

“Halted (reset)” means that internal register values and internal states are initialized.

In module stop mode, only modules for which a stop setting has been made are halted

(reset or retained).

*When the LCD is operated in watch, subactive, or subsleep mode, select the subclock as

the clock to be used.

727

Program-halted state

Program execution state

SCK2 to

SCK0= 0 SCK2 to

SCK0≠ 0

SLEEP instruction

SSBY = 1, PSS = 1

DTON = 1, LSON = 1

Clock switching

exception processing

SLEEP instruction

SSBY = 1, PSS = 1

DTON = 1, LSON = 0

After the oscillation

stabilization time

(STS2 to 0), clock

switching exception

processing

SLEEP instruction

SLEEP

instruction

External

interrupt *4

Any interrupt *3

SLEEP

instruction

SLEEP

instruction

SLEEP instruction

Interrupt *1

LSON bit = 0

Interrupt *2

Interrupt *1

LSON bit = 1

STBY pin = High

RES pin = Low

STBY pin = Low

SSBY= 0, LSON= 0

SSBY= 1,

PSS= 0, LSON= 0

SSBY= 0,

PSS= 1, LSON= 1

SSBY= 1,

PSS= 1, DTON= 0

RES pin = High

: Transition after exception processing : Low power dissipation mode

Reset state

High-speed mode

(main clock)

Medium-speed

mode

(main clock)

Sub-active mode

(subclock) Sub-sleep mode

(subclock)

Hardware

standby mode

Software

standby mode

Sleep mode

(main clock)

Watch mode

(subclock)

Notes: *1 NMI, IRQ0 to IRQ5, and WDT1 interrupts

*2 NMI, IRQ0 to IRQ5, IWDT0 interrupts, and WDT1 interrupt.

*3 All interrupts

*4 NMI and IRQ0 to IRQ5

•When a transition is made between modes by means of an interrupt, the transition cannot be made

on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the

interrupt request.

•From any state except hardware standby mode, a transition to the reset state occurs when RES is

driven Low.

•From any state, a transition to hardware standby mode occurs when STBY is driven low.

•Always select high-speed mode before making a transition to watch mode or sub-active mode.

Figure 22-1 Mode Transition Diagram

728

Table 22.2 Low Power Dissipation Mode Transition Conditions

Pre-Transition

Status of Control Bit at

Transition State After Transition

Invoked by SLEEP

State After Transition

Back from Low Power

Mode Invoked by

State SSBY PSS LSON DTON Instruction Interrupt

High-speed/ 0 *0*Sleep High-speed/Medium-speed

Medium-speed 0*1*——

100*Software standby High-speed/Medium-speed

101*——

1100Watch High-speed

1110Watch Sub-active

1101——

1111Sub-active —

Sub-active 0 0 **——

010*——

011*Sub-sleep Sub-active

10**——

1100Watch High-speed

1110Watch Sub-active

1101High-speed —

1111——

* : Don’t care

—: Do not set

729

22.1.1 Register Configuration

Power-down modes are controlled by the SBYCR, SCKCR, LPWRCR, TCSR (WDT1), and

MSTPCR registers. Table 22-3 summarizes these registers.

Table 22-3 Power-Down Mode Registers

Name Abbreviation R/W Initial Value Address*1

Standby control register SBYCR R/W H'58 H'FDE4

System clock control register SCKCR R/W H'00 H'FDE6

Low-power control register LPWRCR R/W H'00 H'FDEC

Timer control/status register (WDT1) TCSR1 R/W H'00 H'FFA2

Module stop control register MSTPCRA R/W H'3F H'FDE8

A, B, C, D MSTPCRB R/W H'FF H'FDE9

MSTPCRC R/W H'FF H'FDEA

MSTPCRD R/W B'11****** H'FC60

Note: *1 Lower 16 bits of the address.

730

22.2 Register Descriptions

22.2.1 Standby Control Register (SBYCR)

SSBY

R/W

STS2

R/W

STS1

R/W

STS0

R/W

OPE

R/W

—

Bit

Initial value

R/W

SBYCR is an 8-bit readable/writable register that performs power-down mode control.

SBYCR is initialized to H'58 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—Software Standby (SSBY): When making a low power dissipation mode transition by

executing the SLEEP instruction, the operating mode is determined in combination with other

control bits.

Note that the value of the SSBY bit does not change even when shifting between modes using

interrupts.

Bit 7

SSBY Description

0 Shifts to sleep mode when the SLEEP instruction is executed in high-speed

mode or medium-speed mode.

Shifts to sub-sleep mode when the SLEEP instruction is executed in

sub-active mode. (Initial value)

1 Shifts to software standby mode, sub-active mode, and watch mode when the SLEEP

instruction is executed in high-speed mode or medium-speed mode.

Shifts to watch mode or high-speed mode when the SLEEP instruction is executed in

sub-active mode.

731

Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the MCU wait time

for clock stabilization when shifting to high-speed mode or medium-speed mode by using a

specific interrupt or command to cancel software standby mode, watch mode, or sub-active mode.

With a quartz oscillator (table 22-5), select a wait time of 8ms (oscillation stabilization time) or

more, depending on the operating frequency. With an external clock, there are no specific wait

requirements.

Bit 6 Bit 5 Bit 4

STS2 STS1 STS0 Description

0 0 0 Standby time = 8192 states

1 Standby time = 16384 states

1 0 Standby time = 32768 states

1 Standby time = 65536 states

1 0 0 Standby time = 131072 states

1 Standby time = 262144 states (Initial value)

1 0 Reserved

1 Standby time = 16 states

Bit 3—Output Port Enable (OPE): This bit specifies whether the output of the address bus and

bus control signals (AS, RD, HWR, LWR) is retained or set to high-impedance state in the

software standby mode, watch mode, and when making a direct transition.

Bit 3

OPE Description

0 In software standby mode, watch mode, and when making a direct transition, address

bus and bus control signals are high-impedance.

1 In software standby mode, watch mode, and when making a direct transition, the

output state of the address bus and bus control signals is retained. (Initial value)

Bits 2 to 0—Reserved: These bits always return 0 when read, and cannot be written to.

732

22.2.2 System Clock Control Register (SCKCR)

PSTOP

R/W

—

STCS

R/W

SCK0

R/W

SCK2

R/W

SCK1

R/W

Bit

Initial value

R/W

SCKCR is an 8-bit readable/writable register that performs ø clock output control and medium-

speed mode control.

SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—ø Clock Output Disable (PSTOP): In combination with the DDR of the applicable port,

this bit controls ø output. See section 22.12, ø Clock Output Disable Function, for details.

Bit 7 Description

PSTOP

High Speed Mode,

Medium Speed Mode,

Sub-Active Mode Sleep Mode,

Sub-Sleep Mode

Software Standby

Mode, Watch Mode,

and Direct Transition Hardware

Standby Mode

0ø output (initial value) ø output Fixed high High impedance

1 Fixed high Fixed high Fixed high High impedance

Bits 6 to 4—Reserved: These bits are always read as 0 and cannot be modified.

Bit 3—Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation

when the PLL circuit frequency multiplication factor is changed.

Bit 3

STCS Description

0 Specified multiplication factor is valid after transition to software standby mode, watch

mode, or sub-active mode (Initial value)

1 Specified multiplication factor is valid immediately after STC bits are rewritten

733

Bits 2 to 0—System clock select (SCK2 to SCK0): These bits select the bus master clock in

high-speed mode, medium-speed mode, and sub-active mode.

Set SCK2 to SCK0 all to 0 when shifting to operation in watch mode or sub-active mode.

Bit 2 Bit 1 Bit 0

SCK2 SCK1 SCK0 Description

0 0 0 Bus master in high-speed mode (Initial value)

1 Medium-speed clock is ø/2

1 0 Medium-speed clock is ø/4

1 Medium-speed clock is ø/8

1 0 0 Medium-speed clock is ø/16

1 Medium-speed clock is ø/32

1——

22.2.3 Low-Power Control Register (LPWRCR)

DTON

R/W

LSON

R/W

NESEL

R/W

SUBSTP

R/W

RFCUT

R/W

STC0

R/W

—

R/W

STC1

R/W

Bit

Initial value

R/W

The LPWRCR is an 8-bit read/write register that controls the low power dissipation modes.

The LPWRCR is initialized to H'00 at a reset and when in hardware standby mode. It is not

initialized in software standby mode. The following describes bits 7 to 2. For details of other bits,

see section 21.2.2, Low-Power Control Register (LPWRCR).

Bit 7—Direct Transition ON Flag (DTON): When shifting to low power dissipation mode by

executing the SLEEP instruction, this bit specifies whether or not to make a direct transition

between high-speed mode or medium-speed mode and the sub-active modes. The selected

operating mode after executing the SLEEP instruction is determined by the combination of other

control bits.

734

Bit 7

DTON Description

0• When the SLEEP instruction is executed in high-speed mode or medium-speed

mode, operation shifts to sleep mode, software standby mode, or watch mode*.

• When the SLEEP instruction is executed in sub-active mode, operation shifts

to sub-sleep mode or watch mode. (Initial value)

1• When the SLEEP instruction is executed in high-speed mode or medium-speed

mode, operation shifts directly to sub-active mode*, or shifts to sleep mode or

software standby mode.

• When the SLEEP instruction is executed in sub-active mode, operation shifts directly

to high-speed mode, or shifts to sub-sleep mode.

Note: *Always set high-speed mode when shifting to watch mode or sub-active mode.

Bit 6—Low-Speed ON Flag (LSON): When shifting to low power dissipation mode by executing

the SLEEP instruction, this bit specifies the operating mode, in combination with other control

bits. This bit also controls whether to shift to high-speed mode or sub-active mode when watch

mode is cancelled.

Bit 6

LSON Description

0• When the SLEEP instruction is executed in high-speed mode or medium-speed

mode, operation shifts to sleep mode, software standby mode, or watch mode*.

• When the SLEEP instruction is executed in sub-active mode, operation shifts to

watch mode or shifts directly to high-speed mode.

• Operation shifts to high-speed mode when watch mode is cancelled. (Initial value)

1• When the SLEEP instruction is executed in high-speed mode, operation shifts to

watch mode or sub-active mode.

• When the SLEEP instruction is executed in sub-active mode, operation shifts to sub-

sleep mode or watch mode.

• Operation shifts to sub-active mode when watch mode is cancelled.

Note: *Always set high-speed mode when shifting to watch mode or sub-active mode.

735

Bit 5—Noise Elimination Sampling Frequency Select (NESEL): This bit selects the sampling

frequency of the subclock (øSUB) generated by the subclock oscillator is sampled by the clock (ø)

generated by the system clock oscillator. Set this bit to 0 when ø=5MHz or more. This setting is

disabled in sub-active mode, sub-sleep mode, and watch mode.

Bit 5

NESEL Description

0 Sampling using 1/32 xø (Initial value)

1 Sampling using 1/4 xø

Bit 4—Subclock enable (SUBSTP): This bit enables/disables subclock generation.

Bit 4

SUBSTP Description

0 Enables subclock generation (Initial value)

1 Disables subclock generation

Bit 3—Oscillation Circuit Feedback Resistance Control Bit (RFCUT): This bit turns the

internal feedback resistance of the main clock oscillation circuit ON/OFF.

Bit 3

RFCUT Description

0 When the main clock is oscillating, sets the feedback resistance ON. When the main

clock is stopped, sets the feedback resistance OFF. (Initial value)

1 Sets the feedback resistance OFF.

Bit 2—Reserved: Only write 0 to this bit.

736

22.2.4 Timer Control/Status Register (TCSR)

OVF

R/(W)*

WT/IT

R/W

TME

R/W

PSS

R/W

RST/NMI

R/W

CKS0

R/W

CKS2

R/W

CKS1

R/W

Bit

Initial value

R/W

Note: *Only write 0 to clear the flag.

TCSR is an 8-bit read/write register that selects the clock input to WDT1 TCNT and the mode.

Here, we describe bit 4. For details of the other bits in this register, see section 12.2.2, Timer

Control/Status Register (TCSR).

The TCSR is initialized to H'00 at a reset and when in hardware standby mode. It is not initialized

in software standby mode.

Bit 4—Prescaler select (PSS): This bit selects the clock source input to WDT1 TCNT.

It also controls operation when shifting low power dissipation modes. The operating mode

selected after the SLEEP instruction is executed is determined in combination with other control

bits.

For details, see the description for clock selection in section 12.2.2, Timer Control/Status Register

(TCSR), and this section.

Bit 4

PSS Description

0• TCNT counts the divided clock from the ø-based prescaler (PSM).

• When the SLEEP instruction is executed in high-speed mode or medium-speed

mode, operation shifts to sleep mode or software standby mode. (Initial value)

1• TCNT counts the divided clock from the øsubclock-based prescaler (PSS).

• When the SLEEP instruction is executed in high-speed mode or medium-speed

mode, operation shifts to sleep mode, watch mode*, or sub-active mode*.

• When the SLEEP instruction is executed in sub-active mode, operation shifts to sub-

sleep mode, watch mode, or high-speed mode.

Note: *Always set high-speed mode when shifting to watch mode or sub-active mode.

737

22.2.5 Module Stop Control Register (MSTPCR)

MSTPCRA

Bit:76543210

MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0

Initial value : 0 0 1 1 1 1 1 1

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

MSTPCRB (H8S/2646, H8S/2646R, H8S/2645)

Bit:76543210

MSTPB7 MSTPB6 —MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0

Initial value : 1 1 1 1 1 1 1 1

R/W : R/W R/W —R/W R/W R/W R/W R/W

MSTPCRB (H8S/2648, H8S/2648R, H8S/2647)

Bit:76543210

MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0

Initial value : 1 1 1 1 1 1 1 1

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

MSTPCRC

Bit:76543210

MSTPC7 —MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0

Initial value : 1 1 1 1 1 1 1 1

R/W : R/W —R/W R/W R/W R/W R/W R/W

MSTPCRD

Bit:76543210

MSTPD7 MSTPD6 ——————

Initial value : 1 1 Undefined Undefined Undefined Undefined Undefined Undefined

R/W : R/W R/W ——————

MSTPCR, comprising four 8-bit readable/writable registers, performs module stop mode control.

MSTPCRA to MSTPCRC are initialized to H'3FFFFF by a reset and in hardware standby mode.

MSTPCRD is initialized to B'11****** by a reset and in hardware standby mode. They are not

initialized in software standby mode.

738

Empty bits in these registers (bits with no corresponding module, see table 22-4, should always be

written with 1.

MSTPCRA Bits 7 to 0, MSTPCRB Bits 7 to 0, MSTPCRC Bits 7 and 5 to 0, MSTPCRD Bits

7 and 6—Module Stop (MSTPA7 to MSTPA0, MSTPB7, MSTPB6, and MSTPB4 to

MSTPB0, MSTPC7, and MSTPC5 to MSTPC0, MSTPD7, and MSTPD6): These bits specify

module stop mode. See table 22-4 for the method of selecting the on-chip peripheral functions.

MSTPA7 to MSTPA0,

MSTPB7, MSTPB6, and

MSTPB4 to MSTPB0

MSTPC7, and MSTPC5

to MSTPC0

MSTPD7 and MSTPD6 Description (H8S/2646, H8S/2646R, H8S/2645)

0 Module stop mode is cleared (initial value of MSTPA7 and MSTPA6)

1 Module stop mode is set (initial value of MSTPA5 to 0, MSTPB7 to 0,

MSTPC7 to 0, and MSTPD7, 6)

MSTPA7 to MSTPA0,

MSTPB7 to MSTPB0

MSTPC7, and MSTPC5

to MSTPC0

MSTPD7 and MSTPD6 Description (H8S/2648, H8S/2648R, H8S/2647)

0 Module stop mode is cleared (initial value of MSTPA7 and MSTPA6)

1 Module stop mode is set (initial value of MSTPA5 to 0, MSTPB7 to 0,

MSTPC7 to 0, and MSTPD7, 6)

22.3 Medium-Speed Mode

In high-speed mode, when the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode

changes to medium-speed mode as soon as the current bus cycle ends. In medium-speed mode, the

CPU operates on the operating clock (ø/2, ø/4, ø/8, ø/16, or ø/32) specified by the SCK2 to SCK0

bits. The bus masters other than the CPU (DTC) also operate in medium-speed mode. On-chip

supporting modules other than the bus masters always operate on the high-speed clock (ø).

In medium-speed mode, a bus access is executed in the specified number of states with respect to

the bus master operating clock. For example, if ø/4 is selected as the operating clock, on-chip

memory is accessed in 4 states, and internal I/O registers in 8 states.

Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to

high-speed mode and medium-speed mode is cleared at the end of the current bus cycle.

739

If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, and LSON bit in

LPWRCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an

interrupt, medium-speed mode is restored.

When the SLEEP instruction is executed with the SSBY bit = 1, LPWRCR LSON bit = 0, and

TCSR (WDT1) PSS bit = 0, operation shifts to the software standby mode. When software

standby mode is cleared by an external interrupt, medium-speed mode is restored.

When the RES pin is set low and medium-speed mode is cancelled, operation shifts to the reset

state. The same applies in the case of a reset caused by overflow of the watchdog timer.

When the STBY pin is driven low, a transition is made to hardware standby mode.

Figure 22-2 shows the timing for transition to and clearance of medium-speed mode.

ø,

Bus master clock

supporting module clock

Internal address bus

Internal write signal

Medium-speed mode

SBYCRSBYCR

Figure 22-2 Medium-Speed Mode Transition and Clearance Timing

22.4 Sleep Mode

22.4.1 Sleep Mode

When the SLEEP instruction is executed when the SBYCR SSBY bit = 0 and the LPWRCR

LSON bit = 0, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the

contents of the CPU’s internal registers are retained. Other supporting modules do not stop.

22.4.2 Exiting Sleep Mode

Sleep mode is exited by any interrupt, or signals at the RES, or STBY pins.

740

Exiting Sleep Mode by Interrupts: When an interrupt occurs, sleep mode is exited and interrupt

exception processing starts. Sleep mode is not exited if the interrupt is disabled, or interrupts other

than NMI are masked by the CPU.

Exiting Sleep Mode by RES pin: Setting the RES pin level Low selects the reset state. After the

stipulated reset input duration, driving the RES pin High starts the CPU performing reset

exception processing.

Exiting Sleep Mode by STBY Pin: When the STBY pin level is driven Low, a transition is made

to hardware standby mode.

22.5 Module Stop Mode

22.5.1 Module Stop Mode

Module stop mode can be set for individual on-chip supporting modules.

When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of

the bus cycle and a transition is made to module stop mode. The CPU continues operating

independently.

Table 22-4 shows MSTP bits and the corresponding on-chip supporting modules.

When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module

starts operating at the end of the bus cycle. In module stop mode, the internal states of modules

other than the SCI, Motor control PWM, A/D converter and HCAN are retained.

After reset clearance, all modules other than DTC are in module stop mode.

When an on-chip supporting module is in module stop mode, read/write access to its registers is

disabled.

741

Table 22-4 MSTP Bits and Corresponding On-Chip Supporting Modules

MSTPCRA MSTPA6 Data transfer controller (DTC)

MSTPA5 16-bit timer pulse unit (TPU)

MSTPA3 Programmable pulse generator (PPG)

MSTPA1 A/D converter

MSTPCRB MSTPB7 Serial communication interface 0 (SCI0)

MSTPB6 Serial communication interface 1 (SCI1)

MSTPB5 Serial communication interface 2 (SCI2)

(H8S/2648, H8S/2648R, H8S/2647)

MSTPCRC MSTPC4 PC break controller (PBC)

MSTPC3 Hitachi controller area network (HCAN)

MSTPCRD MSTPD7 Motor control PWM (PWM)

MSTPD6 LCD controller/driver

Note: Unlisted bits of the registers are reserved.

The write value must always be 1.

22.5.2 Usage Notes

DTC Module Stop: Depending on the operating status of the DTC, the MSTPA7 and MSTPA6

bits may not be set to 1. Setting of the DTC module stop mode should be carried out only when

the respective module is not activated.

For details, refer to section 8, Data Transfer Controller (DTC).

On-Chip Supporting Module Interrupt: Relevant interrupt operations cannot be performed in

module stop mode. Consequently, if module stop mode is entered when an interrupt has been

requested, it will not be possible to clear the CPU interrupt source or the DTC activation source.

Interrupts should therefore be disabled before entering module stop mode.

Writing to MSTPCR: MSTPCR should only be written to by the CPU.

Restrictions on Use in Medium-speed Mode: In medium-speed mode, registers of the HCAN,

LCD controller, and motor control PWM timer musts not be written to.

742

22.6 Software Standby Mode

22.6.1 Software Standby Mode

A transition is made to software standby mode when the SLEEP instruction is executed when the

SBYCR SSBY bit = 1 and the LPWRCR LSON bit = 0, and the TCSR (WDT1) PSS bit = 0. In

this mode, the CPU, on-chip supporting modules, and oscillator all stop. However, the contents of

the CPU’s internal registers, RAM data, and the states of on-chip supporting modules other than

the SCI, A/D converter, Motor control PWM, HCAN and I/O ports, are retained. Whether the

address bus and bus control signals are placed in the high-impedance state.

In this mode the oscillator stops, and therefore power dissipation is significantly reduced.

22.6.2 Clearing Software Standby Mode

Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ5), or by

means of the RES pin or STBY pin.

• Clearing with an interrupt

When an NMI or IRQ0 to IRQ5 interrupt request signal is input, clock oscillation starts, and

after the elapse of the time set in bits STS2 to STS0 in SYSCR, stable clocks are supplied to

the entire H8S/2646 Series chip, software standby mode is cleared, and interrupt exception

handling is started.

When clearing software standby mode with an IRQ0 to IRQ5 interrupt, set the corresponding

enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ5

is generated. Software standby mode cannot be cleared if the interrupt has been masked on the

CPU side or has been designated as a DTC activation source.

• Clearing with the RES pin

When the RES pin is driven low, clock oscillation is started. At the same time as clock

oscillation starts, clocks are supplied to the entire H8S/2646 Series chip. Note that the RES

pin must be held low until clock oscillation stabilizes. When the RES pin goes high, the CPU

begins reset exception handling.

• Clearing with the STBY pin

When the STBY pin is driven low, a transition is made to hardware standby mode.

743

22.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode

Bits STS2 to STS0 in SBYCR should be set as described below.

Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least 8 ms (the

oscillation stabilization time).

Table 22-5 shows the standby times for different operating frequencies and settings of bits STS2

to STS0.

Table 22-5 Oscillation Stabilization Time Settings

STS2 STS1 STS0 Standby Time 20

MHz 16

MHz 12

MHz 10

MHz 8

MHz 6

MHz 4

MHz Unit

0 0 0 8192 states 0.41 0.51 0.65 0.8 1.0 1.3 2.0 ms

1 16384 states 0.82 1.0 1.3 1.6 2.0 2.7 4.1

1 0 32768 states 1.6 2.0 2.7 3.3 4.1 5.5 8.2

1 65536 states 3.3 4.1 5.5 6.6 8.2 10.9 16.4

1 0 0 131072 states 6.6 8.2 10.9 13.1 16.4 21.8 32.8

1 262144 states 13.1 16.4 21.8 26.2 32.8 43.6 65.6

10Reserved ———————µs

1 16 states*0.8 1.0 1.3 1.6 2.0 1.7 4.0

: Recommended time setting

Note: *Do not use this setting.

Using an External Clock: The PLL circuit requires a time for stabilization. Insert a wait of 2 ms

min.

22.6.4 Software Standby Mode Application Example

Figure 22-3 shows an example in which a transition is made to software standby mode at the

falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI

pin.

In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling

edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set

to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.

Software standby mode is then cleared at the rising edge on the NMI pin.

744

Oscillator

NMI

NMIEG

SSBY

NMI exception

handling

NMIEG=1

SSBY=1

SLEEP instruction

Software standby mode

(power-down mode) Oscillation

stabilization

time tOSC2

NMI exception

handling

Figure 22-3 Software Standby Mode Application Example

22.6.5 Usage Notes

I/O Port Status: In software standby mode, I/O port states are retained. If the OPE bit is set to 1,

the address bus and bus control signal output is also retained. Therefore, there is no reduction in

current dissipation for the output current when a high-level signal is output.

Current Dissipation during Oscillation Stabilization Wait Period: Current dissipation

increases during the oscillation stabilization wait period.

Write Data Buffer Function: The write data buffer function and software standby mode cannot

be used at the same time. When the write data buffer function is used, the WDBE bit in BCRL

should be cleared to 0 to cancel the write data buffer function before entering software standby

mode. Also check that external writes have finished, by reading external addresses, etc., before

executing a SLEEP instruction to enter software standby mode. See section 7.7, Write Data Buffer

Function, for details of the write data buffer function.

745

22.7 Hardware Standby Mode

22.7.1 Hardware Standby Mode

When the STBY pin is driven low, a transition is made to hardware standby mode from any mode.

In hardware standby mode, all functions enter the reset state and stop operation, resulting in a

significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip

RAM data is retained. I/O ports are set to the high-impedance state.

In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before

driving the STBY pin low.

Do not change the state of the mode pins (MD2 to MD0) while the H8S/2646 Series is in hardware

standby mode.

Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY

pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started.

Ensure that the RES pin is held low until the clock oscillator stabilizes (at least 8 ms—the

oscillation stabilization time—when using a crystal oscillator). When the RES pin is subsequently

driven high, a transition is made to the program execution state via the reset exception handling

state.

746

22.7.2 Hardware Standby Mode Timing

Figure 22-4 shows an example of hardware standby mode timing.

When the STBY pin is driven low after the RES pin has been driven low, a transition is made to

hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high,

waiting for the oscillation stabilization time, then changing the RES pin from low to high.

Oscillator

RES

STBY

Oscillation

stabilization

time

Reset

exception

handling

Figure 22-4 Hardware Standby Mode Timing

22.8 Watch Mode

22.8.1 Watch Mode

CPU operation makes a transition to watch mode when the SLEEP instruction is executed in high-

speed mode or sub-active mode with SBYCR SSBY=1, LPWRCR DTON = 0, and TCSR

(WDT1) PSS = 1.

In watch mode, the CPU is stopped and supporting modules other than WDT1 are also stopped.

The contents of the CPU is internal registers, the data in internal RAM, and the statuses of the

internal supporting modules (excluding the SCI, ADC, HCAN, and Motor control PWM) and I/O

ports are retained.

747

22.8.2 Exiting Watch Mode

Watch mode is exited by any interrupt (WOVI interrupt, NMI pin, or IRQ0 to IRQ5), or signals at

the RES, or STBY pins.

Exiting Watch Mode by Interrupts: When an interrupt occurs, watch mode is exited and a

transition is made to high-speed mode or medium-speed mode when the LPWRCR LSON bit = 0

or to sub-active mode when the LSON bit = 1. When a transition is made to high-speed mode, a

stable clock is supplied to all LSI circuits and interrupt exception processing starts after the time

set in SBYCR STS2 to STS0 has elapsed. In the case of IRQ0 to IRQ5 interrupts, no transition is

made from watch mode if the corresponding enable bit has been cleared to 0, and, in the case of

interrupts from the internal supporting modules, the interrupt enable register has been set to

disable the reception of that interrupt, or is masked by the CPU.

See section 22.6.3, Setting Oscillation Stabilization Time after Clearing Software Standby Mode,

for how to set the oscillation stabilization time when making a transition from watch mode to

high-speed mode.

Exiting Watch Mode by RES pins: For exiting watch mode by the RES pins, see, Clearing with

the RES pins in section 22.6.2, Clearing Software Standby Mode.

Exiting Watch Mode by STBY pin: When the STBY pin level is driven Low, a transition is

made to hardware standby mode.

22.8.3 Notes

I/O Port Status: The status of the I/O ports is retained in watch mode. Also, when the OPE bit is

set to 1, the address bus and bus control signals continue to be output. Therefore, when a High

level is output, the current consumption is not diminished by the amount of current to support the

High level output.

Current Consumption when Waiting for Oscillation Stabilization: The current consumption

increases during stabilization of oscillation.

748

22.9 Sub-Sleep Mode

22.9.1 Sub-Sleep Mode

When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR LSON bit = 1,

and TCSR (WDT1) PSS bit = 1, CPU operation shifts to sub-sleep mode.

In sub-sleep mode, the CPU is stopped. Supporting modules other than WDT0, and WDT1 are

also stopped. The contents of the CPU’s internal registers, the data in internal RAM, and the

statuses of the internal supporting modules (excluding the SCI, ADC, HCAN, and Motor control

PWM) and I/O ports are retained.

22.9.2 Exiting Sub-Sleep Mode

Sub-sleep mode is exited by an interrupt (interrupts from internal supporting modules, NMI pin, or

IRQ0 to IRQ5), or signals at the RES or STBY pins.

Exiting Sub-Sleep Mode by Interrupts: When an interrupt occurs, sub-sleep mode is exited and

interrupt exception processing starts.

In the case of IRQ0 to IRQ5 interrupts, sub-sleep mode is not cancelled if the corresponding

enable bit has been cleared to 0, and, in the case of interrupts from the internal supporting

modules, the interrupt enable register has been set to disable the reception of that interrupt, or is

masked by the CPU.

Exiting Sub-Sleep Mode by RES: For exiting sub-sleep mode by the RES pins, see, Clearing

with the RES pins in section 22.6.2, Clearing Software Standby Mode.

Exiting Sub-Sleep Mode by STBY Pin: When the STBY pin level is driven Low, a transition is

made to hardware standby mode.

749

22.10 Sub-Active Mode

22.10.1 Sub-Active Mode

When the SLEEP instruction is executed in high-speed mode with the SBYCR SSBY bit = 1,

LPWRCR DTON bit = 1, LSON bit = 1, and TCSR (WDT1) PSS bit = 1, CPU operation shifts to

sub-active mode. When an interrupt occurs in watch mode, and if the LSON bit of LPWRCR is 1,

a transition is made to sub-active mode. And if an interrupt occurs in sub-sleep mode, a transition

is made to sub-active mode.

In sub-active mode, the CPU operates at low speed on the subclock, and the program is executed

step by step. Supporting modules other than WDT0, and WDT1 are also stopped.

When operating the CPU in sub-active mode, the SCKCR SCK2 to SCK0 bits must be set to 0.

22.10.2 Exiting Sub-Active Mode

Sub-active mode is exited by the SLEEP instruction or the RES or STBY pins.

Exiting Sub-Active Mode by SLEEP Instruction: When the SLEEP instruction is executed with

the SBYCR SSBY bit = 1, LPWRCR DTON bit = 0, and TCSR (WDT1) PSS bit = 1, the CPU

exits sub-active mode and a transition is made to watch mode. When the SLEEP instruction is

executed with the SBYCR SSBY bit = 0, LPWRCR LSON bit = 1, and TCSR (WDT1) PSS bit =

1, a transition is made to sub-sleep mode. Finally, when the SLEEP instruction is executed with

the SBYCR SSBY bit = 1, LPWRCR DTON bit = 1, LSON bit = 0, and TCSR (WDT1) PSS bit =

1, a direct transition is made to high-speed mode (SCK0 to SCK2 all 0).

See section 22.11, Direct Transitions, for details of direct transitions.

Exiting Sub-Active Mode by RES Pins: For exiting sub-active mode by the RES pins, see,

Claering with the RES pins in section 22.6.2, Clearing Software Standby Mode.

Exiting Sub-Active Mode by STBY Pin: When the STBY pin level is driven Low, a transition is

made to hardware standby mode.

750

22.11 Direct Transitions

22.11.1 Overview of Direct Transitions

There are three modes, high-speed, medium-speed, and sub-active, in which the CPU executes

programs. When a direct transition is made, there is no interruption of program execution when

shifting between high-speed and sub-active modes. Direct transitions are enabled by setting the

LPWRCR DTON bit to 1, then executing the SLEEP instruction. After a transition, direct

transition interrupt exception processing starts.

Direct Transitions from High-Speed Mode to Sub-Active Mode: Execute the SLEEP

instruction in high-speed mode when the SBYCR SSBY bit = 1, LPWRCR LSON bit = 1, and

DTON bit = 1, and TSCR (WDT1) PSS bit = 1 to make a transition to sub-active mode.

Direct Transitions from Sub-Active Mode to High-Speed Mode: Execute the SLEEP

instruction in sub-active mode when the SBYCR SSBY bit = 1, LPWRCR LSON bit = 0, and

DTON bit = 1, and TSCR (WDT1) PSS bit = 1 to make a direct transition to high-speed mode

after the time set in SBYCR STS2 to STS0 has elapsed.

22.12 ø Clock Output Disabling Function

Output of the ø clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the

corresponding port. When the PSTOP bit is set to 1, the ø clock stops at the end of the bus cycle,

and ø output goes high. ø clock output is enabled when the PSTOP bit is cleared to 0. When DDR

for the corresponding port is cleared to 0, ø clock output is disabled and input port mode is set.

Table 22-6 shows the state of the ø pin in each processing state.

Table 22-6 ø Pin State in Each Processing State

DDR 0 1 1

PSTOP —01

Hardware standby mode High impedance High impedance High impedance

Software standby mode, watch

mode, and direct transition High impedance Fixed high Fixed high

Sleep mode and sub-sleep mode High impedance ø output Fixed high

High-speed mode, medium-speed

mode High impedance ø output Fixed high

Sub-active mode High impedance øSUB output Fixed high

751

22.13 Usage Notes

1. When making a transition to sub-active mode or watch mode, set the DTC to enter module stop

mode (write 1 to the relevant bits in MSTPCR), and then read the relevant bits to confirm that

they are set to 1 before mode transition. Do not clear module stop mode (write 0 to the relevant

bits in MSTPCR) until a transition from sub-active mode to high-speed mode or medium-speed

mode has been performed.

If a DTC activation source occurs in sub-active mode, the DTC will be activated only after

module stop mode has been cleared and high-speed mode or medium-speed mode has been

entered.

2. The on-chip peripheral modules (DTC and TPU) which halt operation in sub-active mode

cannot clear an interrupt in sub-active mode. Therefore, if a transition is made to sub-active

mode while an interrupt is requested, the CPU interrupt source cannot be cleared. Disable the

interrupts of each on-chip peripheral module before executing a SLEEP instruction to enter

sub-active mode or watch mode.

752

753

Section 23 Electrical Characteristics

23.1 Absolute Maximum Ratings

Table 23-1 lists the absolute maximum ratings.

Table 23-1 Absolute Maximum Ratings

Item Symbol Value Unit

Power supply voltage VCC

PMWVCC

–0.3 to +7.0 V

LPVCC

Input voltage (OSC1, OSC2) Vin –0.3 +3.5 V

lnput voltage (XTAL, EXTAL) Vin –0.3 to ACC +0.3 V

Input voltage (ports 4 and 9) Vin –0.3 to AVCC +0.3 V

Input voltage (ports A, B, C, D, E,

ports PF2, PF4 to PF6) Vin –0.3 to LPVCC +0.3 V

Input voltage (ports H and J) Vin –0.3 to PWMVCC +0.3 V

Input voltage (except ports 4, 9, A,

B, C, D, E, ports PF2, PF4 to PF6,

H and J)

Vin –0.3 to VCC +0.3 V

Reference voltage Vref –0.3 to AVCC +0.3 V

Analog power supply voltage AVCC –0.3 to +7.0 V

Analog input voltage VAN –0.3 to AVCC +0.3 V

Operating temperature Topr Regular specifications: –20 to +75 °C

Wide-range specifications: –40 to +85 °C

Storage temperature Tstg –55 to +125 °C

Caution: Permanent damage to the chip may result if absolute maximum rating are exceeded.

754

23.2 Power Supply Voltage and Operating Frequency Range

Power supply voltage and operating frequency ranges (shaded areas) are shown in figure 23-1.

3 3.5 4 4.5 5 5.5 6

Operating range in high-speed, medium-speed,

and sleep modes

Frequency (MHz)

Power supply voltage (V)

3 3.5 4 4.5 5 5.5 6

32.768

Operating range in watch, sub-active,

and sub-sleep modes

Frequency (MHz)

Power supply voltage (V)

Figure 23-1 Power Supply Voltage and Operating Ranges

755

23.3 DC Characteristics

Table 23-2 lists the DC characteristics. Table 23-3 lists the permissible output currents.

Table 23-2 DC Characteristics

Conditions: VCC = PWMVCC = 4.5 V to 5.5 V, LPVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V,

Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = –20°C to +75°C

(regular specifications), Ta = –40°C to +85°C (wide-range specifications)*1

Item Symbol Min Typ Max Unit Test Conditions

Schmitt IRQ0 to IRQ5 VT–1.0 —— V

trigger input VT+——VCC × 0.7

voltage VT+ – VT–0.4 ——

Input high

voltage RES, STBY,

NMI, FWE,

MD2 to MD0

VIH VCC – 0.7 —VCC + 0.3 V

EXTAL VCC × 0.7 —VCC + 0.3

Ports 1 to 3, 5,

H, J, K

Ports PF0,

PF3, PF7

2.2 —VCC + 0.3

HRxD 2.2 —VCC + 0.3

Ports A to E,

Ports PF2,

PF4 to PF6

2.2 —LPVCC + 0.3

Ports 4, 9 AVCC × 0.7 —AVCC + 0.3

Input low

voltage RES, STBY,

NMI, FWE,

MD2 to MD0

VIL –0.3 —0.5 V

EXTAL –0.3 —0.8

Ports 1 to 3, 5,

A to F, H, J, K –0.3 —0.8

HRxD –0.3 —VCC + 0.2

756

Item Symbol Min Typ Max Unit Test Conditions

Output high

voltage Ports 1 to 3, 5,

H, J, K

Ports PF0,

PF3, PF7,

HTxD

VOH VCC – 0.5 —— VI

OH = –200 µA

Ports A, B, C,

D, E

Ports PF2,

PF4 to PF6

LPVCC – 0.5 —— IOH = –200 µA

Ports 1 to 3, 5,

H, J, K

Ports PF0,

PF3, PF7,

HTxD

3.5 —— IOH = –1 mA

Ports A, B, C,

D, E

Ports PF2,

PF4 to PF6

3.5 —— IOH = –1 mA

PWM1A to 1H,

PWM2A to 2H PWMVCC

– 0.5 —— IOH = –15 mA

Output low

voltage All output pins

except

PWM1A to

PWM1H and

PWM2A to

PWM2H

VOL ——0.4 V IOL = 1.6 mA

PWM1A to 1H,

PWM2A to 2H ——0.5 V IOL = 15 mA

Input leakage RES | Iin | ——1.0 µAV

in =

current STBY, NMI,

MD2 to MD0 ——1.0 0.5 to VCC – 0.5

HRxD, FWE ——1.0

Ports 4, 9 ——1.0 Vin = 0.5 to

AVCC – 0.5

Three-state

leakage

current

(off state)

Ports 1 to 3, 5,

H, J, K

Ports PF0,

PF3, PF7,

HTxD

ITSI——1.0 µAV

in =

0.5 to VCC – 0.5

Ports A to E,

PF2, PF4 to

PF6

——1.0 Vin =

0.5 to LPVCC –

0.5

757

Item Symbol Min Typ Max Unit Test Conditions

MOS input

pull-up currentPorts A to E –IP50 —300 µAV

in = 0 V

Input RES Cin —— 30 pF Vin = 0 V

capacitance NMI —— 30 f = 1 MHz

All input pins

except RES

and NMI

—— 15 Ta = 25°C

Current

dissipation*2Normal

operation ICC*4—60 80 mA f = 20 MHz

Sleep mode —50 65 mA f = 20 MHz

All modules

stopped —40 —mA f = 20 MHz,

(reference values)

Medium-

speed mode

(ø/32)

—40 —mA f = 20 MHz,

(reference values)

Subactive

mode —130 220 µA Using 32.768 kHz

crystal resonator

Subsleep

mode —95 160 µA Using 32.768 kHz

crystal resonator

Watch mode —15 60 µA Using 32.768 kHz

crystal resonator

Standby —2.0 10 µA Ta 50°C

mode*3—— 80 50°C < Ta

LCD power

supply port

power supply

current

During

operation LPlCC —10 20 mA

Standby —0.1 10 µA Ta 50°C

mode*3—— 80 50°C < Ta

Analog

power supply

current

During A/D

conversion AlCC —1.0 2.0 mA AVCC = 5.0 V

Idle —— 5.0 µA

Reference

current During A/D

conversion AlCC —2.5 4.0 mA AVref = 5.0 V

Idle —— 5.0 µA

RAM standby voltage VRAM 2.0 ——V

758

Notes: *1 If the A/D converter is not used, do not leave the AVCC, Vref , and AVSS pins open. Apply

a voltage between 4.5 V and 5.5 V to the AVCC and Vref pins by connecting them to VCC,

for instance. Set Vref AV CC.

*2 Current dissipation values are for VIH min = VCC – 0.5 V, VIL max = 0.5 V with all output

pins unloaded and the on-chip pull-up resistors in the off state.

*3 The values are for VRAM LPV CC < 3.0 V, VIH min = VCC × 0.9, and VIL max = 0.3 V.

*4I

CC depends on VCC and f as follows:

ICCmax = 0.18 (mA/(MHz × V)) × VCC × f + 2.87 (mA/MHz) × f + 0.52 (mA/V) × VCC +

0.8 (mA) (at normal operation)

ICCmax = 0.17 (mA/(MHz × V)) × VCC × f + 2.13 (mA/MHz) × f + 0.75 (mA/V) × VCC +

0.3 (mA) (at sleep)

759

Table 23-3 Permissible Output Currents

Conditions: VCC = PWMVCC = 4.5 V to 5.5 V, LPVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V,

Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = –20°C to +75°C

(regular specifications) , Ta = –40°C to +85°C (wide-range specifications)*

Item Symbol Min Typ Max Unit Test

condition

Permissible output

low current (per pin) All output pins except

PWM1A to PWM1H,

PWM2A to PWM2H

IOL ——10 mA

PWM1A to PWM1H,

PWM2A to PWM2H IOL ——25 mA Ta = 75°C to

85°C

——30 mA Ta = 25°C

——40 mA Ta =-40°C

Permissible output

low current (total) Total of all output pins

except PWM1A to

PWM1H, PWM2A to

PWM2H

∑ IOL ——80 mA

Total of PWM1A to

PWM1H, PWM2A to

PWM2H

∑ IOL ——150 mA Ta = 75°C to

85°C

——180 mA Ta = 25°C

——220 mA Ta =-40°C

Permissible output

high current (per pin)All output pins except

PWM1A to PWM1H,

PWM2A to PWM2H

–IOH ——2.0 mA

PWM1A to PWM1H,

PWM2A to PWM2H –IOH ——25 mA Ta = 75°C to

85°C

——30 mA Ta = 25°C

——40 mA Ta =-40°C

Permissible output

high current (total) Total of all output pins

except PWM1A to

PWM1H, PWM2A to

PWM2H

–∑ IOH ——40 mA

Total of PWM1A to

PWM1H, PWM2A to

PWM2H

–∑ IOL ——150 mA Ta = 75°C to

85°C

——180 mA Ta = 25°C

——220 mA Ta =-40°C

Note: *To protect chip reliability, do not exceed the output current values in table 23-3.

760

23.4 AC Characteristics

Figure 23-2 show, the test conditions for the AC characteristics.

5 V

LSI output pin

C = 50 pF: Ports A to F

(In case of expansion bus control signal output pin setting)

C = 30 pF: All ports except ports A to F

RL = 2.4 kΩ

RH = 12 kΩ

Input/output timing measurement levels

· Low level : 0.8 V

· High level : 2.0 V

Figure 23-2 Output Load Circuit

761

23.4.1 Clock Timing

Table 23-4 lists the clock timing

Table 23-4 Clock Timing

Condition : VCC = PWMVCC = 4.5 V to 5.5 V, LPVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V,

Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = –20°C to

+75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications)

Condition

Item Symbol Min Max Unit Test Conditions

Clock cycle time tcyc 50 250 ns Figure 23-3

Clock high pulse width tCH 25 —ns

Clock low pulse width tCL 25 —ns

Clock rise time tCr —10 ns

Clock fall time tCf —10 ns

Clock oscillator settling

time at reset (crystal) tOSC1 20 —ms Figure 23-4

Clock oscillator settling time in

software standby (crystal) tOSC2 8—ms Figure 22-3

Sub clock oscillator settling time tOSC3 —2 s Figure 23-4

Sub clock oscillator frequency fSUB 32.768 kHz

Sub clock (øSUB) cycle time fSUB 30.5 µs

762

tCH tCf

tcyc

tCL tCr

Figure 23-3 System Clock Timing

tOSC1

VCC

STBY

RES

Figure 23-4 Oscillator Settling Timing

763

23.4.2 Control Signal Timing

Table 23-5 lists the control signal timing.

Table 23-5 Control Signal Timing

Condition : VCC = PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC,

VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = –20°C to +75°C (regular

specifications), Ta = –40°C to +85°C (wide-range specifications)

Condition

Item Symbol Min Max Unit Test Conditions

RES setup time tRESS 200 —ns Figure 23-5

RES pulse width tRESW 20 —tcyc

NMI setup time tNMIS 150 —ns Figure 23-6

NMI hold time tNMIH 10 —

NMI pulse width (exiting

software standby mode) tNMIW 200 —ns

IRQ setup time tIRQS 150 —ns

IRQ hold time tIRQH 10 —ns

IRQ pulse width (exiting

software standby mode) tIRQW 200 —ns

764

tRESW

tRESS

RES

Figure 23-5 Reset Input Timing

tIRQS

IRQ

Edge input

tIRQH

tNMIS tNMIH

tIRQS

IRQ

Level input

NMI

IRQ

tNMIW

tIRQW

Figure 23-6 Interrupt Input Timing

765

23.4.3 Bus Timing

Table 23-6 lists the bus timing.

Table 23-6 Bus Timing

Condition : VCC = PWMVCC = 4.5 V to 5.5 V, LPVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V,

Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = –20°C to

+75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications)

Condition

Item Symbol Min Max Unit Test Conditions

Address delay time tAD —45 ns Figure 23-7 to

Address setup time tAS 0.5 × tcyc – 32 —ns Figure 23-11

Address hold time tAH 0.5 × tcyc – 15 —ns

AS delay time tASD —45 ns

RD delay time 1 tRSD1 —45 ns

RD delay time 2 tRSD2 —45 ns

Read data setup time tRDS 20 —ns

Read data hold time tRDH 10 —ns

Read data access time 1 tACC1 —1.0 × tcyc – 60 ns

Read data access time 2 tACC2 —1.5 × tcyc – 50 ns

Read data access time 3 tACC3 —2.0 × tcyc – 60 ns

Read data access time 4 tACC4 —2.5 × tcyc – 50 ns

Read data access time 5 tACC5 —3.0 × tcyc – 60 ns

WR delay time 1 tWRD1 —35 ns

WR delay time 2 tWRD2 —45 ns

WR pulse width 1 tWSW1 1.0 × tcyc – 40 —ns

WR pulse width 2 tWSW2 1.5 × tcyc – 30 —ns

Write data delay time tWDD —45 ns

Write data setup time tWDS 0.5 × tcyc – 20 —ns

Write data hold time tWDH 0.5 × tcyc – 10 —ns

WAIT setup time tWTS 30 —ns

WAIT hold time tWTH 5—ns

766

tRSD2

tAH

tACC2

tRSD1

tASD tASD

tAD

tACC3 tRDH

tWRD2

tWSW1

tWDD tWDH

T1T2

tAS

tAH

A23 to A0

(read)

D15 to D0

(read)

HWR, LWR

(write)

D15 to D0

(write)

tRDS

Figure 23-7 Basic Bus Timing (Two-State Access)

767

tRSD2

tAS tAH

tACC4

tRSD1

tASD tASD

tAD

tACC5 tRDH

tWRD2

tWRD1

tWSW2

tWDD tWDH

T1T3

tWDS

tRDS

tAS

tAH

A23 to A0

(read)

D15 to D0

(read)

HWR, LWR

(write)

D15 to D0

(write)

Figure 23-8 Basic Bus Timing (Three-State Access)

768

tWTH

T1T2

WAIT

TwT3

tWTS tWTH

tWTS

A23 to A0

(read)

D15 to D0

(read)

HWR, LWR

(write)

D15 to D0

(write)

Figure 23-9 Basic Bus Timing (Three-State Access with One Wait State)

769

tRSD2

tAS tAH

tASD tASD

tAD

tACC3 tRDS tRDH

T1T2

T2 or T3

A23 to A0

D15 to D0

(read)

Figure 23-10 Burst ROM Access Timing (Two-State Access)

770

A23 to A0

tACC1

D15 to D0

(read)

T2 or T3

tRDH

tAD

(read) tRDS

tRSD2

Figure 23-11 Burst ROM Access Timing (One-State Access)

771

23.4.4 Timing of On-Chip Supporting Modules

Table 23-7 lists the timing of on-chip supporting modules.

Table 23-7 Timing of On-Chip Supporting Modules

Condition : VCC = PWMVCC = 4.5 V to 5.5 V, LPVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V,

Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = –20°C to

+75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications)

Condition

Item Symbol Min Max Unit Test Conditions

I/O port Output data

delay time tF—50 ns Figure 23-12

Input data

setup time tPRS 30 —

Input data

hold time tPRH 30 —

PPG Pulse output

delay time tPOD —50 ns Figure 23-13

TPU Timer output

delay time tTOCD —50 ns Figure 23-14

Timer input

setup time tTICD 30 —

Timer clock

input setup

time

tTCKS 30 —ns Figure 23-15

Timer clock Single edge tTCKWH 1.5 —tcyc

pulse width Both edges tTCKWL 2.5 —

PWM Pulse output

delay time tMPWMOD —50 ns Figure 23-16

772

Condition

Item Symbol Min Max Unit Test Conditions

SCI Input clock

cycle Asynchro-

nous tScyc 4—tcyc Figure 23-17

Synchronous 6 —

Input clock pulse width tSCKW 0.4 0.6 tScyc

Input clock rise time tSCKr —1.5 tcyc

Input clock fall time tSCKf —1.5

Transmit data delay time tTXD —50 ns Figure 23-18

Receive data setup time

(synchronous) tRXS 50 —

Receive data hold time

(synchronous) tRXH 50 —

A/D

converter Trigger input setup time tTRGS 50 —ns Figure 23-19

HCAN Transmit data delay time tHTXD —100 ns Figure 23-20

Transmit data setup time tHRXS 100 —

Transmit data hold time tHRXH 100 —

773

Port 1 to 5, 9,

A to F, K

(read)

tPRS

T1T2

tPWD

tPRH

Port 1 to 3, 5,

A to F, K

(write)

Port H, J

(read)

Port H, J

(write)

tPRS

T3T4

tPWD

tPRH

T1T2

Figure 23-12 I/O Port Input/Output Timing

PO15 to 8

tPOD

Figure 23-13 PPG Output Timing

774

tTICS

tTOCD

Output compare

output*

Input capture

input*

Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3

Figure 23-14 TPU Input/Output Timing

TCKS

TCLKA to TCLKD

TCKWH

TCKWL

Figure 23-15 TPU Clock Input Timing

PWM1A to PWM1H,

PWM2A to PWM2H

tMPWMOD

Figure 23-16 Motor Control PWM Output Timing

H8S/2646, H8S/2646R, H8S/2645:

SCK0, SCK1

H8S/2648, H8S/2648R, H8S/2647:

SCK0 to SCK2

tSCKW tSCKr tSCKf

tScyc

Figure 23-17 SCK Clock Input Timing

775

TxD0, TxD1

(transmit data)

RxD0, RxD1

(receive data)

SCK0, SCK1

tRXS tRXH

tTXD

Figure 23-18 SCI Input/Output Timing (Clock Synchronous Mode)

ADTRG

tTRGS

Figure 23-19 A/D Converter External Trigger Input Timing

HTxD

(transmit data)

HRxD

(receive data)

tHTXD

VOL VOL

tHRXH

tHRXS

—Preliminary—

Figure 23-20 HCAN Input/Output Timing

776

23.5 A/D Conversion Characteristics

Table 23-8 lists the A/D conversion characteristics.

Table 23-8 A/D Conversion Characteristics

Condition : VCC = PWMVCC = 4.5 V to 5.5 V, LPVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V,

Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = –20°C to

+75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications)

Condition

Item Min Typ Max Unit

Resolution 10 10 10 bits

Conversion time ——13.3 µs

Analog input capacitance ——20 pF

Permissible signal-source impedance ——5k

Nonlinearity error ——±3.5 LSB

Offset error ——±3.5 LSB

Full-scale error ——±3.5 LSB

Quantization —±0.5 —LSB

Absolute accuracy ——±4.0 LSB

777

23.6 LCD Characteristics

Table 23-9 LCD Characteristics

Condition : VCC = PWMVCC = 4.5 V to 5.5 V, LPVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V,

Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = –20 to +75ºC

(regular specifications), Ta = –40 to +85ºC (wide-range specifications)

Standard Value

Item Symbol Applicable Pins Test

Conditions Min Typ Max Unit Notes

Segment driver

step-down voltage VDS SEG1 to SEG24

(H8S/2646,

H8S/2646R,

H8S/2645)

ID = 2 µA ——0.6 V *1

SEG1 to SEG40

(H8S/2648,

H8S/2648R,

H8S/2647)

Common driver

step-down voltage VDC COM1 to COM4 ID = 2 µA ——0.3 V *1

LCD power supply

division resistor RLCD Between V1

and VSS

40 300 1000 k

LCD voltage VLCD V1 4.5 —LPVC

V*2

Notes: *1 Voltage step-down between power supply pins V1, V2, V3, and VSS and segment pins.

*2 If the LCD voltage is provided by an external power supply, the following relationship

must be maintained: LPVCC V1 V2 V3 V SS.

778

23.7 Flash Memory Characteristics

Table 23-10 shows the flash memory characteristics.

Table 23-10 Flash Memory Characteristics

Conditions: VCC = PWMVCC = 4.5 V to 5.5 V, LPVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V,

Vref = 4.5 V to AVCC, VSS PWMVSS = PLLVSS, AVSS = 0 V

Ta = 0 to +75°C (Programming/erasing operating temperature range: regular

specification)

Item Symbol Min Typ Max Unit Test Condition

Programming time*1*2 *4tP—10 200 ms/

128 bytes

Erase time*1 *3 *5tE—100 1200 ms/block

Reprogramming count NWEC ——100 Times

Programming Wait time after SWE bit setting*1tsswe 11—µs

Wait time after PSU bit setting*1tspsu 50 50 —µs

Wait time after P bit setting*1*4tsp30 28 30 32 µs Programming

time wait

tsp200 198 200 202 µs Programming

time wait

tsp10 8 10 12 µs Additional-

programming

time wait

Wait time after P bit clear*1tcp 55—µs

Wait time after PSU bit clear*1tcpsu 55—µs

Wait time after PV bit setting*1tspv 44—µs

Wait time after H'FF dummy

write*1tspvr 22—µs

Wait time after PV bit clear*1tcpv 22—µs

Wait time after SWE bit clear*1tcswe 100 100 —µs

Maximum programming count*1*4N——1000 Times

Erase Wait time after SWE bit setting*1tsswe 11—µs

Wait time after ESU bit setting*1tsesu 100 100 —µs

Wait time after E bit setting*1*5tse 10 10 100 ms Erase time wait

Wait time after E bit clear*1tce 10 10 —µs

Wait time after ESU bit clear*1tcesu 10 10 —µs

Wait time after EV bit setting*1tsev 20 20 —µs

779

Item Symbol Min Typ Max Unit Test Condition

Erase Wait time after H'FF dummy

write*1tsevr 22—µs

Wait time after EV bit clear*1tcev 44—µs

Wait time after SWE bit clear*1tcswe 100 100 —µs

Maximum erase count*1*5N12—120 Times

Notes: *1 Make each time setting in accordance with the program or erase algorithm.

*2 Programming time per 128 bytes (Shows the total period for which the P-bit in the flash

memory control register (FLMCR1) is set. It does not include the programming

verification time.)

*3 Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does

not include the erase verification time.)

*4 To specify the maximum programming time value (tP(max)) in the 128-byte

programming algorithm, set the max. value (1000) for the maximum programming count

(N).

The wait time after P bit setting should be changed as follows according to the value of

the programming counter (n).

Programming counter (n) = 1 to 6: tsp30 = 30 µs

Programming counter (n) = 7 to 1000: tsp200 = 200 µs

[In additional programming]

Programming counter (n)= 1 to 6: tsp10 = 10 µs

*5 For the maximum erase time (tE(max)), the following relationship applies between the

wait time after E bit setting (tse) and the maximum erase count (N):

tE(max) = Wait time after E bit setting (tse) x maximum erase count (N)

To set the maximum erase time, the values of (tse) and (N) should be set so as to satisfy

the above formula.

Examples: When tse = 100 [ms], N = 12 times

When tse = 10 [ms], N = 120 times

780

781

Appendix A Instruction Set

A.1 Instruction List

Operand Notation

Rd General register (destination)*

Rs General register (source)*

Rn General register*

ERn General register (32-bit register)

MAC Multiply-and-accumulate register (32-bit register)

(EAd) Destination operand

(EAs) Source operand

EXR Extended control register

CCR Condition-code register

N N (negative) flag in CCR

Z Z (zero) flag in CCR

V V (overflow) flag in CCR

C C (carry) flag in CCR

PC Program counter

SP Stack pointer

#IMM Immediate data

disp Displacement

+ Add

– Subtract

×Multiply

÷ Divide

∧Logical AND

∨Logical OR

⊕Logical exclusive OR

→Transfer from the operand on the left to the operand on the right, or

transition from the state on the left to the state on the right

¬ Logical NOT (logical complement)

( ) < > Contents of operand

:8/:16/:24/:32 8-, 16-, 24-, or 32-bit length

Note: *General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to

R7, E0 to E7), and 32-bit registers (ER0 to ER7).

782

Condition Code Notation

Symbol

Changes according to the result of instruction

*Undetermined (no guaranteed value)

0 Always cleared to 0

1 Always set to 1

— Not affected by execution of the instruction

783

Table A-1 Instruction Set

(1) Data Transfer Instructions

Addressing Mode/

Instruction Length (Bytes)

Operand Size

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

Mnemonic

MOV MOV.B #xx:8,Rd B 2

MOV.B Rs,Rd B 2

MOV.B @ERs,Rd B 2

MOV.B @(d:16,ERs),Rd B 4

MOV.B @(d:32,ERs),Rd B 8

MOV.B @ERs+,Rd B 2

MOV.B @aa:8,Rd B 2

MOV.B @aa:16,Rd B 4

MOV.B @aa:32,Rd B 6

MOV.B Rs,@ERd B 2

MOV.B Rs,@(d:16,ERd) B 4

MOV.B Rs,@(d:32,ERd) B 8

MOV.B Rs,@-ERd B 2

MOV.B Rs,@aa:8 B 2

MOV.B Rs,@aa:16 B 4

MOV.B Rs,@aa:32 B 6

MOV.W #xx:16,Rd W 4

MOV.W Rs,Rd W 2

MOV.W @ERs,Rd W 2

#xx:8→Rd8 —— 0—1

Rs8→Rd8 —— 0—1

@ERs→Rd8 —— 0—2

@(d:16,ERs)→Rd8 —— 0—3

@(d:32,ERs)→Rd8 —— 0—5

@ERs→Rd8,ERs32+1→ERs32 —— 0—3

@aa:8→Rd8 —— 0—2

@aa:16→Rd8 —— 0—3

@aa:32→Rd8 —— 0—4

Rs8→@ERd —— 0—2

Rs8→@(d:16,ERd) —— 0—3

Rs8→@(d:32,ERd) —— 0—5

ERd32-1→ERd32,Rs8→@ERd —— 0—3

Rs8→@aa:8 —— 0—2

Rs8→@aa:16 —— 0—3

Rs8→@aa:32 —— 0—4

#xx:16→Rd16 —— 0—2

Rs16→Rd16 —— 0—1

@ERs→Rd16 —— 0—2

Operation

Condition Code

IHNZVC Advanced

No. of States

↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔

784

Addressing Mode/

Instruction Length (Bytes)

Operand Size

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

Mnemonic

MOV MOV.W @(d:16,ERs),Rd W 4

MOV.W @(d:32,ERs),Rd W 8

MOV.W @ERs+,Rd W 2

MOV.W @aa:16,Rd W 4

MOV.W @aa:32,Rd W 6

MOV.W Rs,@ERd W 2

MOV.W Rs,@(d:16,ERd) W 4

MOV.W Rs,@(d:32,ERd) W 8

MOV.W Rs,@-ERd W 2

MOV.W Rs,@aa:16 W 4

MOV.W Rs,@aa:32 W 6

MOV.L #xx:32,ERd L 6

MOV.L ERs,ERd L 2

MOV.L @ERs,ERd L 4

MOV.L @(d:16,ERs),ERd L 6

MOV.L @(d:32,ERs),ERd L 10

MOV.L @ERs+,ERd L 4

MOV.L @aa:16,ERd L 6

MOV.L @aa:32,ERd L 8

@(d:16,ERs)→Rd16 —— 0—3

@(d:32,ERs)→Rd16 —— 0—5

@ERs→Rd16,ERs32+2→ERs32 —— 0—3

@aa:16→Rd16 —— 0—3

@aa:32→Rd16 —— 0—4

Rs16→@ERd —— 0—2

Rs16→@(d:16,ERd) —— 0—3

Rs16→@(d:32,ERd) —— 0—5

ERd32-2→ERd32,Rs16→@ERd —— 0—3

Rs16→@aa:16 —— 0—3

Rs16→@aa:32 —— 0—4

#xx:32→ERd32 —— 0—3

ERs32→ERd32 —— 0—1

@ERs→ERd32 —— 0—4

@(d:16,ERs)→ERd32 —— 0—5

@(d:32,ERs)→ERd32 —— 0—7

@ERs→

ERd32,ERs32+4

→

@ERs32

—— 0—5

@aa:16→ERd32 —— 0—5

@aa:32→ERd32 —— 0—6

Operation

Condition Code

IHNZVC Advanced

No. of States

↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔

785

Addressing Mode/

Instruction Length (Bytes)

Operand Size

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

Mnemonic

MOV

POP

PUSH

LDM

STM

MOVFPE

MOVTPE

MOV.L ERs,@ERd L 4

MOV.L ERs,@(d:16,ERd) L 6

MOV.L ERs,@(d:32,ERd) L 10

MOV.L ERs,@-ERd L 4

MOV.L ERs,@aa:16 L 6

MOV.L ERs,@aa:32 L 8

POP.W Rn W 2

POP.L ERn L 4

PUSH.W Rn W 2

PUSH.L ERn L 4

LDM @SP+,(ERm-ERn) L 4

STM (ERm-ERn),@-SP L 4

MOVFPE @aa:16,Rd

MOVTPE Rs,@aa:16

ERs32→@ERd —— 0—4

ERs32→@(d:16,ERd) —— 0—5

ERs32→@(d:32,ERd) —— 0—7

ERd32-4

→

ERd32,ERs32

→@

ERd

—— 0—5

ERs32→@aa:16 —— 0—5

ERs32→@aa:32 —— 0—6

@SP→Rn16,SP+2→SP —— 0—3

@SP→ERn32,SP+4→SP —— 0—5

SP-2→SP,Rn16→@SP —— 0—3

SP-4→SP,ERn32→@SP —— 0—5

(@SP→ERn32,SP+4→SP) —————— 7/9/11 [1]

Repeated for each register restored

(SP-4→SP,ERn32→@SP) —————— 7/9/11 [1]

Repeated for each register saved

[2]

Operation

Condition Code

IHNZVC Advanced

No. of States*1

↔↔↔↔↔↔↔↔↔↔

Cannot be used in this LSI

786

(2) Arithmetic Instructions

Addressing Mode/

Instruction Length (Bytes)

Operand Size

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

Mnemonic

ADD

ADDX

ADDS

INC

DAA

SUB

ADD.B #xx:8,Rd B 2

ADD.B Rs,Rd B 2

ADD.W #xx:16,Rd W 4

ADD.W Rs,Rd W 2

ADD.L #xx:32,ERd L 6

ADD.L ERs,ERd L 2

ADDX #xx:8,Rd B 2

ADDX Rs,Rd B 2

ADDS #1,ERd L 2

ADDS #2,ERd L 2

ADDS #4,ERd L 2

INC.B Rd B 2

INC.W #1,Rd W 2

INC.W #2,Rd W 2

INC.L #1,ERd L 2

INC.L #2,ERd L 2

DAA Rd B 2

SUB.B Rs,Rd B 2

SUB.W #xx:16,Rd W 4

Rd8+#xx:8→Rd8 —1

Rd8+Rs8→Rd8 —1

Rd16+#xx:16→Rd16 — [3] 2

Rd16+Rs16→Rd16 — [3] 1

ERd32+#xx:32→ERd32 — [4] 3

ERd32+ERs32→ERd32 — [4] 1

Rd8+#xx:8+C→Rd8 —[5] 1

Rd8+Rs8+C→Rd8 —[5] 1

ERd32+1→ERd32 —— ——— — 1

ERd32+2→ERd32 —— ——— — 1

ERd32+4→ERd32 —— ——— — 1

Rd8+1→Rd8 —— — 1

Rd16+1→Rd16 —— — 1

Rd16+2→Rd16 —— — 1

ERd32+1→ERd32 —— — 1

ERd32+2→ERd32 —— — 1

Rd8 decimal adjust→Rd8 —** 1

Rd8-Rs8→Rd8 —1

Rd16-#xx:16→Rd16 — [3] 2

Operation

Condition Code

IHNZVC Advanced

No. of States*1

↔↔↔

↔

↔↔↔↔↔↔↔↔

↔↔ ↔↔↔↔↔

↔↔↔↔↔↔↔↔

↔↔↔↔↔↔

↔↔↔↔↔↔↔↔

↔↔ ↔↔

787

Addressing Mode/

Instruction Length (Bytes)

Operand Size

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

Mnemonic

SUB

SUBX

SUBS

DEC

DAS

MULXU

MULXS

SUB.W Rs,Rd W 2

SUB.L #xx:32,ERd L 6

SUB.L ERs,ERd L 2

SUBX #xx:8,Rd B 2

SUBX Rs,Rd B 2

SUBS #1,ERd L 2

SUBS #2,ERd L 2

SUBS #4,ERd L 2

DEC.B Rd B 2

DEC.W #1,Rd W 2

DEC.W #2,Rd W 2

DEC.L #1,ERd L 2

DEC.L #2,ERd L 2

DAS Rd B 2

MULXU.B Rs,Rd B 2

MULXU.W Rs,ERd W 2

MULXS.B Rs,Rd B 4

MULXS.W Rs,ERd W 4

Rd16-Rs16→Rd16 —[3] 1

ERd32-#xx:32→ERd32 —[4] 3

ERd32-ERs32→ERd32 —[4] 1

Rd8-#xx:8-C→Rd8 —[5] 1

Rd8-Rs8-C→Rd8 —[5] 1

ERd32-1→ERd32 —————— 1

ERd32-2→ERd32 —————— 1

ERd32-4→ERd32 —————— 1

Rd8-1→Rd8 —— — 1

Rd16-1→Rd16 —— — 1

Rd16-2→Rd16 —— — 1

ERd32-1→ERd32 —— — 1

ERd32-2→ERd32 —— — 1

Rd8 decimal adjust→Rd8 — * *—1

Rd8

Rs8

→

Rd16 (unsigned multiplication)

—————— 12

Rd16×Rs16→ERd32 —————— 20

(unsigned multiplication)

Rd8

Rs8

→

Rd16 (signed multiplication)

—— —— 13

Rd16×Rs16→ERd32 —— —— 21

(signed multiplication)

Operation

Condition Code

IHNZVC Advanced

No. of States

↔↔

↔↔ ↔↔↔↔↔↔

↔↔↔↔↔↔

↔↔↔↔↔ ↔↔↔

↔↔↔↔↔

↔↔

788

Addressing Mode/

Instruction Length (Bytes)

Operand Size

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

Mnemonic

DIVXU

DIVXS

CMP

NEG

EXTU

DIVXU.B Rs,Rd B 2

DIVXU.W Rs,ERd W 2

divxs.B Rs,Rd B 4

DIVXS.W Rs,ERd W 4

CMP.B #xx:8,Rd B 2

CMP.B Rs,Rd B 2

CMP.W #xx:16,Rd W 4

CMP.W Rs,Rd W 2

CMP.L #xx:32,ERd L 6

CMP.L ERs,ERd L 2

NEG.B Rd B 2

NEG.W Rd W 2

NEG.L ERd L 2

EXTU.W Rd W 2

EXTU.L ERd L 2

Rd16÷Rs8→

Rd16 (RdH: remainder,

——[6] [7] —— 12

RdL: quotient) (unsigned division)

ERd32÷Rs16

→

ERd32 (Ed: remainder,

——[6] [7] —— 20

Rd: quotient) (unsigned division)

Rd16÷Rs8→

Rd16 (RdH: remainder,

——[8] [7] —— 13

RdL: quotient) (signed division)

ERd32

÷Rs16→

ERd32 (Ed: remainder,

——[8] [7] —— 21

Rd: quotient) (signed division)

Rd8-#xx:8 —1

Rd8-Rs8 —1

Rd16-#xx:16 —[3] 2

Rd16-Rs16 —[3] 1

ERd32-#xx:32 —[4] 3

ERd32-ERs32 —[4] 1

0-Rd8→Rd8 —1

0-Rd16→Rd16 —1

0-ERd32→ERd32 —1

0→(<bit 15 to 8> of Rd16) —— 00—1

0→(<bit 31 to 16> of ERd32) —— 00—1

Operation

Condition Code

IHNZVC Advanced

No. of States*1

↔↔↔ ↔↔

↔↔↔↔↔↔↔↔↔↔↔

↔↔↔↔↔↔↔↔↔

789

Addressing Mode/

Instruction Length (Bytes)

Operand Size

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

Mnemonic

EXTS

TAS

MAC

CLRMAC

LDMAC

STMAC

EXTS.W Rd W 2

EXTS.L ERd L 2

TAS @ERd*

MAC @ERn+, @ERm+ 4

CLRMAC

LDMAC ERs,MACH

LDMAC ERs,MACL

STMAC MACH,ERd

STMAC MACL,ERd

(<bit 7> of Rd16)→—— 0—1

(<bit 15 to 8> of Rd16)

(<bit 15> of ERd32)→—— 0—1

(<bit 31 to 16> of ERd32)

@ERd-0→CCR set, (1)→—— 0—4

(<bit 7> of @ERd)

@ERnx@ERm+MAC→MAC —————— 4

(signal multiplication)

[11] [11] [11]

@ERn+2→ERn, ERm+2→ERm

0→MACH, MACL —————— 2 [12]

ERs→MACH —————— 2 [12]

ERs→MACL —————— 2 [12]

MACH→ERd —— — 1 [12]

MACL→ERd —— — 1 [12]

Operation

Condition Code

IHNZVC Advanced

No. of States

↔ ↔ ↔

↔

↔↔

↔

—

790

(3) Logical Instructions

Addressing Mode/

Instruction Length (Bytes)

Operand Size

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

Mnemonic

AND

XOR

NOT

AND.B #xx:8,Rd B 2

AND.B Rs,Rd B 2

AND.W #xx:16,Rd W 4

AND.W Rs,Rd W 2

AND.L #xx:32,ERd L 6

AND.L ERs,ERd L 4

OR.B #xx:8,Rd B 2

OR.B Rs,Rd B 2

OR.W #xx:16,Rd W 4

OR.W Rs,Rd W 2

OR.L #xx:32,ERd L 6

OR.L ERs,ERd L 4

XOR.B #xx:8,Rd B 2

XOR.B Rs,Rd B 2

XOR.W #xx:16,Rd W 4

XOR.W Rs,Rd W 2

XOR.L #xx:32,ERd L 6

XOR.L ERs,ERd L 4

NOT.B Rd B 2

NOT.W Rd W 2

NOT.L ERd L 2

Rd8∧#xx:8→Rd8 —— 0—1

Rd8∧Rs8→Rd8 —— 0—1

Rd16∧#xx:16→Rd16 —— 0—2

Rd16∧Rs16→Rd16 —— 0—1

ERd32∧#xx:32→ERd32 —— 0—3

ERd32∧ERs32→ERd32 —— 0—2

Rd8∨#xx:8→Rd8 —— 0—1

Rd8∨Rs8→Rd8 —— 0—1

Rd16∨#xx:16→Rd16 —— 0—2

Rd16∨Rs16→Rd16 —— 0—1

ERd32∨#xx:32→ERd32 —— 0—3

ERd32∨ERs32→ERd32 —— 0—2

Rd8⊕#xx:8→Rd8 —— 0—1

Rd8⊕Rs8→Rd8 —— 0—1

Rd16⊕#xx:16→Rd16 —— 0—2

Rd16⊕Rs16→Rd16 —— 0—1

ERd32⊕#xx:32→ERd32 —— 0—3

ERd32⊕ERs32→ERd32 —— 0—2

¬ Rd8→Rd8 —— 0—1

¬ Rd16→Rd16 —— 0—1

¬ ERd32→ERd32 —— 0—1

Operation

Condition Code

IHNZVC Advanced

No. of States*1

↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔

791

(4) Shift Instructions

Addressing Mode/

Instruction Length (Bytes)

Operand Size

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

Mnemonic

SHAL

SHAR

SHLL

SHAL.B Rd B 2

SHAL.B #2,Rd B 2

SHAL.W Rd W 2

SHAL.W #2,Rd W 2

SHAL.L ERd L 2

SHAL.L #2,ERd L 2

SHAR.B Rd B 2

SHAR.B #2,Rd B 2

SHAR.W Rd W 2

SHAR.W #2,Rd W 2

SHAR.L ERd L 2

SHAR.L #2,ERd L 2

SHLL.B Rd B 2

SHLL.B #2,Rd B 2

SHLL.W Rd W 2

SHLL.W #2,Rd W 2

SHLL.L ERd L 2

SHLL.L #2,ERd L 2

—— 1

—— 01

Operation

Condition Code

IHNZVC Advanced

No. of States*1

↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔

↔↔↔↔↔↔

↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔

CMSB LSB

MSB LSB

792

Addressing Mode/

Instruction Length (Bytes)

Operand Size

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

Mnemonic

SHLR

ROTXL

ROTXR

SHLR.B Rd B 2

SHLR.B #2,Rd B 2

SHLR.W Rd W 2

SHLR.W #2,Rd W 2

SHLR.L ERd L 2

SHLR.L #2,ERd L 2

ROTXL.B Rd B 2

ROTXL.B #2,Rd B 2

ROTXL.W Rd W 2

ROTXL.W #2,Rd W 2

ROTXL.L ERd L 2

ROTXL.L #2,ERd L 2

ROTXR.B Rd B 2

ROTXR.B #2,Rd B 2

ROTXR.W Rd W 2

ROTXR.W #2,Rd W 2

ROTXR.L ERd L 2

ROTXR.L #2,ERd L 2

———00 1

———01

Operation

Condition Code

IHNZVC Advanced

No. of States

↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔

↔↔↔↔↔↔↔↔↔↔↔↔

MSB LSB

CMSB LSB

MSB LSB

793

—— 01

———01

—— 01

———01

1—— 01

Addressing Mode/

Instruction Length (Bytes)

Operand Size

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

Mnemonic

ROTL

ROTR

ROTL.B Rd B 2

ROTL.B #2,Rd B 2

ROTL.W Rd W 2

ROTL.W #2,Rd W 2

ROTL.L ERd L 2

ROTL.L #2,ERd L 2

ROTR.B Rd B 2

ROTR.B #2,Rd B 2

ROTR.W Rd W 2

ROTR.W #2,Rd W 2

ROTR.L ERd L 2

ROTR.L #2,ERd L 2

Operation

Condition Code

IHNZVC Advanced

No. of States

↔↔↔↔↔↔↔↔↔↔↔↔

MSB LSB

CMSB LSB

794

(5) Bit-Manipulation Instructions

Addressing Mode/

Instruction Length (Bytes)

Operand Size

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

Mnemonic

BSET

BCLR

BSET #xx:3,Rd B 2

BSET #xx:3,@ERd B 4

BSET #xx:3,@aa:8 B 4

BSET #xx:3,@aa:16 B 6

BSET #xx:3,@aa:32 B 8

BSET Rn,Rd B 2

BSET Rn,@ERd B 4

BSET Rn,@aa:8 B 4

BSET Rn,@aa:16 B 6

BSET Rn,@aa:32 B 8

BCLR #xx:3,Rd B 2

BCLR #xx:3,@ERd B 4

BCLR #xx:3,@aa:8 B 4

BCLR #xx:3,@aa:16 B 6

BCLR #xx:3,@aa:32 B 8

BCLR Rn,Rd B 2

BCLR Rn,@ERd B 4

BCLR Rn,@aa:8 B 4

BCLR Rn,@aa:16 B 6

(#xx:3 of Rd8)←1—————— 1

(#xx:3 of @ERd)←1—————— 4

(#xx:3 of @aa:8)←1—————— 4

(#xx:3 of @aa:16)←1—————— 5

(#xx:3 of @aa:32)←1—————— 6

(Rn8 of Rd8)←1—————— 1

(Rn8 of @ERd)←1—————— 4

(Rn8 of @aa:8)←1—————— 4

(Rn8 of @aa:16)←1—————— 5

(Rn8 of @aa:32)←1—————— 6

(#xx:3 of Rd8)←0—————— 1

(#xx:3 of @ERd)←0—————— 4

(#xx:3 of @aa:8)←0—————— 4

(#xx:3 of @aa:16)←0—————— 5

(#xx:3 of @aa:32)←0—————— 6

(Rn8 of Rd8)←0—————— 1

(Rn8 of @ERd)←0—————— 4

(Rn8 of @aa:8)←0—————— 4

(Rn8 of @aa:16)←0—————— 5

Operation

Condition Code

IHNZVC Advanced

No. of States

795

Addressing Mode/

Instruction Length (Bytes)

Operand Size

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

Mnemonic

BCLR

BNOT

BTST

BCLR Rn,@aa:32 B 8

BNOT #xx:3,Rd B 2

BNOT #xx:3,@ERd B 4

BNOT #xx:3,@aa:8 B 4

BNOT #xx:3,@aa:16 B 6

BNOT #xx:3,@aa:32 B 8

BNOT Rn,Rd B 2

BNOT Rn,@ERd B 4

BNOT Rn,@aa:8 B 4

BNOT Rn,@aa:16 B 6

BNOT Rn,@aa:32 B 8

BTST #xx:3,Rd B 2

BTST #xx:3,@ERd B 4

BTST #xx:3,@aa:8 B 4

BTST #xx:3,@aa:16 B 6

(Rn8 of @aa:32)←0—————— 6

(#xx:3 of Rd8)←[¬ (#xx:3 of Rd8)] —————— 1

(#xx:3 of @ERd)←—————— 4

[¬ (#xx:3 of @ERd)]

(#xx:3 of @aa:8)←—————— 4

[¬ (#xx:3 of @aa:8)]

(#xx:3 of @aa:16)←—————— 5

[¬ (#xx:3 of @aa:16)]

(#xx:3 of @aa:32)←—————— 6

[¬ (#xx:3 of @aa:32)]

(Rn8 of Rd8)←[¬ (Rn8 of Rd8)] —————— 1

(Rn8 of @ERd)

←

[¬ (Rn8 of @ERd)]

—————— 4

(Rn8 of @aa:8)

←

[¬ (Rn8 of @aa:8)]

—————— 4

(Rn8 of @aa:16)←—————— 5

[¬ (Rn8 of @aa:16)]

(Rn8 of @aa:32)←—————— 6

[¬ (Rn8 of @aa:32)]

¬ (#xx:3 of Rd8)→Z——— —— 1

¬ (#xx:3 of @ERd)→Z——— —— 3

¬ (#xx:3 of @aa:8)→Z——— —— 3

¬ (#xx:3 of @aa:16)→Z——— —— 4

Operation

Condition Code

IHNZVC Advanced

No. of States

↔↔↔↔

796

Addressing Mode/

Instruction Length (Bytes)

Operand Size

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

Mnemonic

BTST

BLD

BILD

BST

BTST #xx:3,@aa:32 B 8

BTST Rn,Rd B 2

BTST Rn,@ERd B 4

BTST Rn,@aa:8 B 4

BTST Rn,@aa:16 B 6

BTST Rn,@aa:32 B 8

BLD #xx:3,Rd B 2

BLD #xx:3,@ERd B 4

BLD #xx:3,@aa:8 B 4

BLD #xx:3,@aa:16 B 6

BLD #xx:3,@aa:32 B 8

BILD #xx:3,Rd B 2

BILD #xx:3,@ERd B 4

BILD #xx:3,@aa:8 B 4

BILD #xx:3,@aa:16 B 6

BILD #xx:3,@aa:32 B 8

BST #xx:3,Rd B 2

BST #xx:3,@ERd B 4

BST #xx:3,@aa:8 B 4

¬ (#xx:3 of @aa:32)→Z——— —— 5

¬ (Rn8 of Rd8)→Z——— —— 1

¬ (Rn8 of @ERd)→Z——— —— 3

¬ (Rn8 of @aa:8)→Z——— —— 3

¬ (Rn8 of @aa:16)→Z——— —— 4

¬ (Rn8 of @aa:32)→Z——— —— 5

(#xx:3 of Rd8)→C————— 1

(#xx:3 of @ERd)→C————— 3

(#xx:3 of @aa:8)→C————— 3

(#xx:3 of @aa:16)→C————— 4

(#xx:3 of @aa:32)→C————— 5

¬ (#xx:3 of Rd8)→C————— 1

¬ (#xx:3 of @ERd)→C————— 3

¬ (#xx:3 of @aa:8)→C————— 3

¬ (#xx:3 of @aa:16)→C————— 4

¬ (#xx:3 of @aa:32)→C————— 5

C→(#xx:3 of Rd8) —————— 1

C→(#xx:3 of @ERd) —————— 4

C→(#xx:3 of @aa:8) —————— 4

Operation

Condition Code

IHNZVC Advanced

No. of States

↔↔↔↔↔↔↔↔↔↔

↔↔↔↔↔↔

797

Addressing Mode/

Instruction Length (Bytes)

Operand Size

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

Mnemonic

BST

BIST

BAND

BIAND

BOR

BST #xx:3,@aa:16 B 6

BST #xx:3,@aa:32 B 8

BIST #xx:3,Rd B 2

BIST #xx:3,@ERd B 4

BIST #xx:3,@aa:8 B 4

BIST #xx:3,@aa:16 B 6

BIST #xx:3,@aa:32 B 8

BAND #xx:3,Rd B 2

BAND #xx:3,@ERd B 4

BAND #xx:3,@aa:8 B 4

BAND #xx:3,@aa:16 B 6

BAND #xx:3,@aa:32 B 8

BIAND #xx:3,Rd B 2

BIAND #xx:3,@ERd B 4

BIAND #xx:3,@aa:8 B 4

BIAND #xx:3,@aa:16 B 6

BIAND #xx:3,@aa:32 B 8

BOR #xx:3,Rd B 2

BOR #xx:3,@ERd B 4

C→(#xx:3 of @aa:16) —————— 5

C→(#xx:3 of @aa:32) —————— 6

¬ C→(#xx:3 of Rd8) —————— 1

¬ C→(#xx:3 of @ERd) —————— 4

¬ C→(#xx:3 of @aa:8) —————— 4

¬ C→(#xx:3 of @aa:16) —————— 5

¬ C→(#xx:3 of @aa:32) —————— 6

C∧(#xx:3 of Rd8)→C————— 1

C∧(#xx:3 of @ERd)→C————— 3

C∧(#xx:3 of @aa:8)→C————— 3

C∧(#xx:3 of @aa:16)→C————— 4

C∧(#xx:3 of @aa:32)→C————— 5

C∧[¬ (#xx:3 of Rd8)]→C————— 1

C∧[¬ (#xx:3 of @ERd)]→C————— 3

C∧[¬ (#xx:3 of @aa:8)]→C————— 3

C∧[¬ (#xx:3 of @aa:16)]→C————— 4

C∧[¬ (#xx:3 of @aa:32)]→C————— 5

C∨(#xx:3 of Rd8)→C————— 1

C∨(#xx:3 of @ERd)→C————— 3

Operation

Condition Code

IHNZVC Advanced

No. of States

↔↔↔↔↔↔↔↔↔↔↔↔

798

Addressing Mode/

Instruction Length (Bytes)

Operand Size

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

Mnemonic

BOR

BIOR

BXOR

BIXOR

BOR #xx:3,@aa:8 B 4

BOR #xx:3,@aa:16 B 6

BOR #xx:3,@aa:32 B 8

BIOR #xx:3,Rd B 2

BIOR #xx:3,@ERd B 4

BIOR #xx:3,@aa:8 B 4

BIOR #xx:3,@aa:16 B 6

BIOR #xx:3,@aa:32 B 8

BXOR #xx:3,Rd B 2

BXOR #xx:3,@ERd B 4

BXOR #xx:3,@aa:8 B 4

BXOR #xx:3,@aa:16 B 6

BXOR #xx:3,@aa:32 B 8

BIXOR #xx:3,Rd B 2

BIXOR #xx:3,@ERd B 4

BIXOR #xx:3,@aa:8 B 4

BIXOR #xx:3,@aa:16 B 6

BIXOR #xx:3,@aa:32 B 8

C∨(#xx:3 of @aa:8)→C————— 3

C∨(#xx:3 of @aa:16)→C————— 4

C∨(#xx:3 of @aa:32)→C————— 5

C∨[¬ (#xx:3 of Rd8)]→C————— 1

C∨[¬ (#xx:3 of @ERd)]→C————— 3

C∨[¬ (#xx:3 of @aa:8)]→C————— 3

C∨[¬ (#xx:3 of @aa:16)]→C————— 4

C∨[¬ (#xx:3 of @aa:32)]→C————— 5

C⊕(#xx:3 of Rd8)→C————— 1

C⊕(#xx:3 of @ERd)→C————— 3

C⊕(#xx:3 of @aa:8)→C————— 3

C⊕(#xx:3 of @aa:16)→C————— 4

C⊕(#xx:3 of @aa:32)→C————— 5

C⊕[¬ (#xx:3 of Rd8)]→C————— 1

C⊕[¬ (#xx:3 of @ERd)]→C————— 3

C⊕[¬ (#xx:3 of @aa:8)]→C————— 3

C⊕[¬ (#xx:3 of @aa:16)]→C————— 4

C⊕[¬ (#xx:3 of @aa:32)]→C————— 5

Operation

Condition Code

IHNZVC Advanced

No. of States

↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔

799

(6) Branch Instructions

Addressing Mode/

Instruction Length (Bytes)

Operand Size

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

Mnemonic

Bcc Always —————— 2

—————— 3

Never —————— 2

—————— 3

C∨Z=0 —————— 2

—————— 3

C∨Z=1 —————— 2

—————— 3

C=0 —————— 2

—————— 3

C=1 —————— 2

—————— 3

Z=0 —————— 2

—————— 3

Z=1 —————— 2

—————— 3

V=0 —————— 2

—————— 3

Operation Condition Code

Branching

Condition IHNZVC Advanced

No. of States*1

BRA d:8(BT d:8) —2 if condition is true then

BRA d:16(BT d:16) —4 PC←PC+d

BRN d:8(BF d:8) —2 else next;

BRN d:16(BF d:16) —4

BHI d:8 —2

BHI d:16 —4

BLS d:8 —2

BLS d:16 —4

BCC d:B(BHS d:8) —2

BCC d:16(BHS d:16) —4

BCS d:8(BLO d:8) —2

BCS d:16(BLO d:16) —4

BNE d:8 —2

BNE d:16 —4

BEQ d:8 —2

BEQ d:16 —4

BVC d:8 —2

BVC d:16 —4

800

Addressing Mode/

Instruction Length (Bytes)

Operand Size

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

Mnemonic

Bcc V=1 —————— 2

—————— 3

N=0 —————— 2

—————— 3

N=1 —————— 2

—————— 3

N⊕V=0 —————— 2

—————— 3

N⊕V=1 —————— 2

—————— 3

Z∨(N⊕V)=0

—————— 2

—————— 3

Z∨(N⊕V)=1

—————— 2

—————— 3

Operation Condition Code

Branching

Condition

IHNZVC Advanced

No. of States

BVS d:8 —2

BVS d:16 —4

BPL d:8 —2

BPL d:16 —4

BMI d:8 —2

BMI d:16 —4

BGE d:8 —2

BGE d:16 —4

BLT d:8 —2

BLT d:16 —4

BGT d:8 —2

BGT d:16 —4

BLE d:8 —2

BLE d:16 —4

801

Addressing Mode/

Instruction Length (Bytes)

Operand Size

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

Mnemonic

JMP

BSR

JSR

RTS

JMP @ERn —2

JMP @aa:24 —4

JMP @@aa:8 —2

BSR d:8 —2

BSR d:16 —4

JSR @ERn —2

JSR @aa:24 —4

JSR @@aa:8 —2

RTS —2

PC←ERn —————— 2

PC←aa:24 —————— 3

PC←@aa:8 —————— 5

PC→@-SP,PC←PC+d:8 —————— 4

PC→@-SP,PC←PC+d:16 —————— 5

PC→@-SP,PC←ERn —————— 4

PC→@-SP,PC←aa:24 —————— 5

PC→@-SP,PC←@aa:8 —————— 6

PC←@SP+ —————— 5

Operation

Condition Code

IHNZVC Advanced

No. of States*1

802

(7) System Control Instructions

Addressing Mode/

Instruction Length (Bytes)

Operand Size

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

Mnemonic

TRAPA

RTE

SLEEP

LDC

TRAPA #xx:2 —

RTE —

SLEEP —

LDC #xx:8,CCR B 2

LDC #xx:8,EXR B 4

LDC Rs,CCR B 2

LDC Rs,EXR B 2

LDC @ERs,CCR W 4

LDC @ERs,EXR W 4

LDC @(d:16,ERs),CCR W 6

LDC @(d:16,ERs),EXR W 6

LDC @(d:32,ERs),CCR W 10

LDC @(d:32,ERs),EXR W 10

LDC @ERs+,CCR W 4

LDC @ERs+,EXR W 4

LDC @aa:16,CCR W 6

LDC @aa:16,EXR W 6

LDC @aa:32,CCR W 8

LDC @aa:32,EXR W 8

PC→@-SP,CCR→@-SP, 1 ————— 8 [9]

EXR→@-SP,<vector>→PC

EXR←@SP+,CCR←@SP+, 5 [9]

PC←@SP+

Transition to power-down state —————— 2

#xx:8→CCR 1

#xx:8→EXR —————— 2

Rs8→CCR 1

Rs8→EXR —————— 1

@ERs→CCR 3

@ERs→EXR —————— 3

@(d:16,ERs)→CCR 4

@(d:16,ERs)→EXR —————— 4

@(d:32,ERs)→CCR 6

@(d:32,ERs)→EXR —————— 6

@ERs→CCR,ERs32+2→ERs32 4

@ERs→EXR,ERs32+2→ERs32 —————— 4

@aa:16→CCR 4

@aa:16→EXR —————— 4

@aa:32→CCR 5

@aa:32→EXR —————— 5

Operation

Condition Code

IHNZVC Advanced

No. of States*1

↔ ↔ ↔ ↔ ↔

↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔

↔ ↔ ↔ ↔

803

Addressing Mode/

Instruction Length (Bytes)

Operand Size

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

Mnemonic

STC

ANDC

ORC

XORC

NOP

STC CCR,Rd B 2

STC EXR,Rd B 2

STC CCR,@ERd W 4

STC EXR,@ERd W 4

STC CCR,@(d:16,ERd) W 6

STC EXR,@(d:16,ERd) W 6

STC CCR,@(d:32,ERd) W 10

STC EXR,@(d:32,ERd) W 10

STC CCR,@-ERd W 4

STC EXR,@-ERd W 4

STC CCR,@aa:16 W 6

STC EXR,@aa:16 W 6

STC CCR,@aa:32 W 8

STC EXR,@aa:32 W 8

ANDC #xx:8,CCR B 2

ANDC #xx:8,EXR B 4

ORC #xx:8,CCR B 2

ORC #xx:8,EXR B 4

XORC #xx:8,CCR B 2

XORC #xx:8,EXR B 4

NOP —2

CCR→Rd8 —————— 1

EXR→Rd8 —————— 1

CCR→@ERd —————— 3

EXR→@ERd —————— 3

CCR→@(d:16,ERd) —————— 4

EXR→@(d:16,ERd) —————— 4

CCR→@(d:32,ERd) —————— 6

EXR→@(d:32,ERd) —————— 6

ERd32-2→ERd32,CCR→@ERd —————— 4

ERd32-2→ERd32,EXR→@ERd —————— 4

CCR→@aa:16 —————— 4

EXR→@aa:16 —————— 4

CCR→@aa:32 —————— 5

EXR→@aa:32 —————— 5

CCR∧#xx:8→CCR 1

EXR∧#xx:8→EXR —————— 2

CCR∨#xx:8→CCR 1

EXR∨#xx:8→EXR —————— 2

CCR⊕#xx:8→CCR 1

EXR⊕#xx:8→EXR —————— 2

PC←PC+2 —————— 1

Operation

Condition Code

IHNZVC Advanced

No. of States

↔ ↔ ↔

804

(8) Block Transfer Instructions

Addressing Mode/

Instruction Length (Bytes)

Operand Size

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

Mnemonic

EEPMOV

Notes: *1 The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory.

*2 Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

*3 n is the initial value of R4L or R4.

[1] Seven states for saving or restoring two registers, nine states for three registers, or eleven states for four registers.

[2] Cannot be used in this LSI.

[3] Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0.

[4] Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0.

[5] Retains its previous value when the result is zero; otherwise cleared to 0.

[6] Set to 1 when the divisor is negative; otherwise cleared to 0.

[7] Set to 1 when the divisor is zero; otherwise cleared to 0.

[8] Set to 1 when the quotient is negative; otherwise cleared to 0.

[9] One additional state is required for execution when EXR is valid.

EEPMOV.B —4

EEPMOV.W —4

if R4L≠0—————— 4+2n*3

Repeat @ER5→@ER6

ER5+1→ER5

ER6+1→ER6

R4L-1→R4L

Until R4L=0

else next;

if R4≠0—————— 4+2n*3

Repeat @ER5→@ER6

ER5+1→ER5

ER6+1→ER6

R4-1→R4

Until R4=0

else next;

Operation

Condition Code

IHNZVC Advanced

No. of States*1

805

A.2 Instruction Codes

Table A-2 shows the instruction codes.

806

Table A-2 Instruction Codes

ADD.B #xx:8,Rd

ADD.B Rs,Rd

ADD.W #xx:16,Rd

ADD.W Rs,Rd

ADD.L #xx:32,ERd

ADD.L ERs,ERd

ADDS #1,ERd

ADDS #2,ERd

ADDS #4,ERd

ADDX #xx:8,Rd

ADDX Rs,Rd

AND.B #xx:8,Rd

AND.B Rs,Rd

AND.W #xx:16,Rd

AND.W Rs,Rd

AND.L #xx:32,ERd

AND.L ERs,ERd

ANDC #xx:8,CCR

ANDC #xx:8,EXR

BAND #xx:3,Rd

BAND #xx:3,@ERd

BAND #xx:3,@aa:8

BAND #xx:3,@aa:16

BAND #xx:3,@aa:32

BRA d:8 (BT d:8)

BRA d:16 (BT d:16)

BRN d:8 (BF d:8)

BRN d:16 (BF d:16)

Mnemonic Size Instruction Format

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

Instruc-

tion

ADD

ADDS

ADDX

AND

ANDC

BAND

Bcc

—

ers

IMM

erd

ers

IMM

0 erd

0 IMM

76 0

IMM

abs

disp

IMM

abs

disp

IMM

abs

IMM

807

BHI d:8

BHI d:16

BLS d:8

BLS d:16

BCC d:8 (BHS d:8)

BCC d:16 (BHS d:16)

BCS d:8 (BLO d:8)

BCS d:16 (BLO d:16)

BNE d:8

BNE d:16

BEQ d:8

BEQ d:16

BVC d:8

BVC d:16

BVS d:8

BVS d:16

BPL d:8

BPL d:16

BMI d:8

BMI d:16

BGE d:8

BGE d:16

BLT d:8

BLT d:16

BGT d:8

BGT d:16

BLE d:8

BLE d:16

Mnemonic Size Instruction Format

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

Instruc-

tion

Bcc —

—

disp

808

BCLR #xx:3,Rd

BCLR #xx:3,@ERd

BCLR #xx:3,@aa:8

BCLR #xx:3,@aa:16

BCLR #xx:3,@aa:32

BCLR Rn,Rd

BCLR Rn,@ERd

BCLR Rn,@aa:8

BCLR Rn,@aa:16

BCLR Rn,@aa:32

BIAND #xx:3,Rd

BIAND #xx:3,@ERd

BIAND #xx:3,@aa:8

BIAND #xx:3,@aa:16

BIAND #xx:3,@aa:32

BILD #xx:3,Rd

BILD #xx:3,@ERd

BILD #xx:3,@aa:8

BILD #xx:3,@aa:16

BILD #xx:3,@aa:32

BIOR #xx:3,Rd

BIOR #xx:3,@ERd

BIOR #xx:3,@aa:8

BIOR #xx:3,@aa:16

BIOR #xx:3,@aa:32

Mnemonic Size Instruction Format

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

Instruc-

tion

BCLR

BIAND

BILD

BIOR

IMM

erd

IMM

erd

IMM

erd

IMM

erd

IMM

abs

IMM

809

BIST #xx:3,Rd

BIST #xx:3,@ERd

BIST #xx:3,@aa:8

BIST #xx:3,@aa:16

BIST #xx:3,@aa:32

BIXOR #xx:3,Rd

BIXOR #xx:3,@ERd

BIXOR #xx:3,@aa:8

BIXOR #xx:3,@aa:16

BIXOR #xx:3,@aa:32

BLD #xx:3,Rd

BLD #xx:3,@ERd

BLD #xx:3,@aa:8

BLD #xx:3,@aa:16

BLD #xx:3,@aa:32

BNOT #xx:3,Rd

BNOT #xx:3,@ERd

BNOT #xx:3,@aa:8

BNOT #xx:3,@aa:16

BNOT #xx:3,@aa:32

BNOT Rn,Rd

BNOT Rn,@ERd

BNOT Rn,@aa:8

BNOT Rn,@aa:16

BNOT Rn,@aa:32

Mnemonic Size Instruction Format

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

Instruc-

tion

BIST

BIXOR

BLD

BNOT

IMM

erd

IMM

erd

IMM

erd

IMM

erd

IMM

1rn

abs

810

BOR #xx:3,Rd

BOR #xx:3,@ERd

BOR #xx:3,@aa:8

BOR #xx:3,@aa:16

BOR #xx:3,@aa:32

BSET #xx:3,Rd

BSET #xx:3,@ERd

BSET #xx:3,@aa:8

BSET #xx:3,@aa:16

BSET #xx:3,@aa:32

BSET Rn,Rd

BSET Rn,@ERd

BSET Rn,@aa:8

BSET Rn,@aa:16

BSET Rn,@aa:32

BSR d:8

BSR d:16

BST #xx:3,Rd

BST #xx:3,@ERd

BST #xx:3,@aa:8

BST #xx:3,@aa:16

BST #xx:3,@aa:32

BTST #xx:3,Rd

BTST #xx:3,@ERd

BTST #xx:3,@aa:8

BTST #xx:3,@aa:16

BTST #xx:3,@aa:32

BTST Rn,Rd

BTST Rn,@ERd

Mnemonic Size Instruction Format

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

Instruc-

tion

BOR

BSET

BSR

BST

BTST

—

IMM

erd

IMM

erd

IMM

erd

IMM

erd

abs

disp

abs

IMM

abs

disp

abs

811

BTST Rn,@aa:8

BTST Rn,@aa:16

BTST Rn,@aa:32

BXOR #xx:3,Rd

BXOR #xx:3,@ERd

BXOR #xx:3,@aa:8

BXOR #xx:3,@aa:16

BXOR #xx:3,@aa:32

CLRMAC

CMP.B #xx:8,Rd

CMP.B Rs,Rd

CMP.W #xx:16,Rd

CMP.W Rs,Rd

CMP.L #xx:32,ERd

CMP.L ERs,ERd

DAA Rd

DAS Rd

DEC.B Rd

DEC.W #1,Rd

DEC.W #2,Rd

DEC.L #1,ERd

DEC.L #2,ERd

DIVXS.B Rs,Rd

DIVXS.W Rs,ERd

DIVXU.B Rs,Rd

DIVXU.W Rs,ERd

EEPMOV.B

EEPMOV.W

Mnemonic Size Instruction Format

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

Instruc-

tion

BTST

BXOR

CLRMAC

CMP

DAA

DAS

DEC

DIVXS

DIVXU

EEPMOV

—

IMM

erd

ers

erd

IMM

0 erd

0 IMM

rn 0

abs

IMM

abs

IMM

abs

IMM

812

EXTS.W Rd

EXTS.L ERd

EXTU.W Rd

EXTU.L ERd

INC.B Rd

INC.W #1,Rd

INC.W #2,Rd

INC.L #1,ERd

INC.L #2,ERd

JMP @ERn

JMP @aa:24

JMP @@aa:8

JSR @ERn

JSR @aa:24

JSR @@aa:8

LDC #xx:8,CCR

LDC #xx:8,EXR

LDC Rs,CCR

LDC Rs,EXR

LDC @ERs,CCR

LDC @ERs,EXR

LDC @(d:16,ERs),CCR

LDC @(d:16,ERs),EXR

LDC @(d:32,ERs),CCR

LDC @(d:32,ERs),EXR

LDC @ERs+,CCR

LDC @ERs+,EXR

LDC @aa:16,CCR

LDC @aa:16,EXR

Mnemonic Size Instruction Format

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

Instruc-

tion

EXTS

EXTU

INC

JMP

JSR

LDC

—

ern

erd

ers

abs

IMM

disp

abs

disp

813

abs

LDC @aa:32,CCR

LDC @aa:32,EXR

LDM.L @SP+, (ERn-ERn+1)

LDM.L @SP+, (ERn-ERn+2)

LDM.L @SP+, (ERn-ERn+3)

LDMAC ERs,MACH

LDMAC ERs,MACL

MAC @ERn+,@ERm+

MOV.B #xx:8,Rd

MOV.B Rs,Rd

MOV.B @ERs,Rd

MOV.B @(d:16,ERs),Rd

MOV.B @(d:32,ERs),Rd

MOV.B @ERs+,Rd

MOV.B @aa:8,Rd

MOV.B @aa:16,Rd

MOV.B @aa:32,Rd

MOV.B Rs,@ERd

MOV.B Rs,@(d:16,ERd)

MOV.B Rs,@(d:32,ERd)

MOV.B Rs,@-ERd

MOV.B Rs,@aa:8

MOV.B Rs,@aa :16

MOV.B Rs,@aa:32

MOV.W #xx:16,Rd

MOV.W Rs,Rd

MOV.W @ERs,Rd

MOV.W @(d:16,ERs),Rd

MOV.W @(d:32,ERs),Rd

Mnemonic Size Instruction Format

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

Instruc-

tion

LDC

LDM

LDMAC

MAC

MOV

—

ers

erd

ers

erm

ern+1

ern+2

ern+3

erm0

IMM

abs

disp

abs

disp

abs

IMM

disp

abs

disp

814

MOV.W @ERs+,Rd

MOV.W @aa:16,Rd

MOV.W @aa:32,Rd

MOV.W Rs,@ERd

MOV.W Rs,@(d:16,ERd)

MOV.W Rs,@(d:32,ERd)

MOV.W Rs,@-ERd

MOV.W Rs,@aa:16

MOV.W Rs,@aa:32

MOV.L #xx:32,Rd

MOV.L ERs,ERd

MOV.L @ERs,ERd

MOV.L @(d:16,ERs),ERd

MOV.L @(d:32,ERs),ERd

MOV.L @ERs+,ERd

MOV.L @aa:16 ,ERd

MOV.L @aa:32 ,ERd

MOV.L ERs,@ERd

MOV.L ERs,@(d:16,ERd)

MOV.L ERs,@(d:32,ERd)

MOV.L ERs,@-ERd

MOV.L ERs,@aa:16

MOV.L ERs,@aa:32

MOVFPE @aa:16,Rd

MOVTPE Rs,@aa:16

MULXS.B Rs,Rd

MULXS.W Rs,ERd

MULXU.B Rs,Rd

MULXU.W Rs,ERd

Mnemonic Size Instruction Format

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

Instruc-

tion

MOV

MOVFPE

MOVTPE

MULXS

MULXU

ers

erd

ers

erd

ers

erd

ers

erd

ers

abs

disp

abs

IMM

disp

abs

disp

abs

disp

abs

Cannot be used in this LSI

disp

815

NEG.B Rd

NEG.W Rd

NEG.L ERd

NOP

NOT.B Rd

NOT.W Rd

NOT.L ERd

OR.B #xx:8,Rd

OR.B Rs,Rd

OR.W #xx:16,Rd

OR.W Rs,Rd

OR.L #xx:32,ERd

OR.L ERs,ERd

ORC #xx:8,CCR

ORC #xx:8,EXR

POP.W Rn

POP.L ERn

PUSH.W Rn

PUSH.L ERn

ROTL.B Rd

ROTL.B #2, Rd

ROTL.W Rd

ROTL.W #2, Rd

ROTL.L ERd

ROTL.L #2, ERd

Mnemonic Size Instruction Format

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

Instruc-

tion

NEG

NOP

NOT

ORC

POP

PUSH

ROTL

—

erd

IMM

ers 0

erd

ern

IMM

816

ROTR.B Rd

ROTR.B #2, Rd

ROTR.W Rd

ROTR.W #2, Rd

ROTR.L ERd

ROTR.L #2, ERd

ROTXL.B Rd

ROTXL.B #2, Rd

ROTXL.W Rd

ROTXL.W #2, Rd

ROTXL.L ERd

ROTXL.L #2, ERd

ROTXR.B Rd

ROTXR.B #2, Rd

ROTXR.W Rd

ROTXR.W #2, Rd

ROTXR.L ERd

ROTXR.L #2, ERd

RTE

RTS

SHAL.B Rd

SHAL.B #2, Rd

SHAL.W Rd

SHAL.W #2, Rd

SHAL.L ERd

SHAL.L #2, ERd

Mnemonic Size Instruction Format

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

Instruc-

tion

ROTR

ROTXL

ROTXR

RTE

RTS

SHAL

—

erd

817

SHAR.B Rd

SHAR.B #2, Rd

SHAR.W Rd

SHAR.W #2, Rd

SHAR.L ERd

SHAR.L #2, ERd

SHLL.B Rd

SHLL.B #2, Rd

SHLL.W Rd

SHLL.W #2, Rd

SHLL.L ERd

SHLL.L #2, ERd

SHLR.B Rd

SHLR.B #2, Rd

SHLR.W Rd

SHLR.W #2, Rd

SHLR.L ERd

SHLR.L #2, ERd

SLEEP

STC.B CCR,Rd

STC.B EXR,Rd

STC.W CCR,@ERd

STC.W EXR,@ERd

STC.W CCR,@(d:16,ERd)

STC.W EXR,@(d:16,ERd)

STC.W CCR,@(d:32,ERd)

STC.W EXR,@(d:32,ERd)

STC.W CCR,@-ERd

STC.W EXR,@-ERd

Mnemonic Size Instruction Format

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

Instruc-

tion

SHAR

SHLL

SHLR

SLEEP

STC

—

erd

disp

818

STC.W CCR,@aa:16

STC.W EXR,@aa:16

STC.W CCR,@aa:32

STC.W EXR,@aa:32

STM.L(ERn-ERn+1), @-SP

STM.L (ERn-ERn+2), @-SP

STM.L (ERn-ERn+3), @-SP

STMAC MACH,ERd

STMAC MACL,ERd

SUB.B Rs,Rd

SUB.W #xx:16,Rd

SUB.W Rs,Rd

SUB.L #xx:32,ERd

SUB.L ERs,ERd

SUBS #1,ERd

SUBS #2,ERd

SUBS #4,ERd

SUBX #xx:8,Rd

SUBX Rs,Rd

TAS @ERd*2

TRAPA #x:2

XOR.B #xx:8,Rd

XOR.B Rs,Rd

XOR.W #xx:16,Rd

XOR.W Rs,Rd

XOR.L #xx:32,ERd

XOR.L ERs,ERd

XORC #xx:8,CCR

XORC #xx:8,EXR

Mnemonic Size Instruction Format

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

Instruc-

tion

STC

STM

STMAC

SUB

SUBS

SUBX

TAS

TRAPA

XOR

XORC

—

ers

IMM

ers

erd

ers

ern

erd

abs

IMM

4IMM

819

Legend

Address Register

32-Bit Register

Field General

000

001

•

111

ER0

ER1

•

ER7

0000

0001

•

0111

1000

1001

•

1111

•

0000

0001

•

0111

1000

1001

•

1111

R0H

R1H

•

R7H

R0L

R1L

•

R7L

16-Bit Register 8-Bit Register

IMM:

abs:

disp:

rs, rd, rn:

ers, erd, ern, erm:

The register fields specify general registers as follows.

Immediate data (2, 3, 8, 16, or 32 bits)

Absolute address (8, 16, 24, or 32 bits)

Displacement (8, 16, or 32 bits)

Register field (4 bits specifying an 8-bit or 16-bit register. The symbols rs, rd, and rn correspond to operand symbols Rs, Rd,and Rn.)

Register field (3 bits specifying an address register or 32-bit register. The symbols ers, erd, ern, and erm correspond to operand

symbols ERs, ERd, ERn, and ERm.)

Notes: *1 Bit 7 of the 4th byte of the MOV.L ERs, @(d:32,ERd) instruction can be either 1 or 0.

*2 Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

820

A.3 Operation Code Map

Table A-3 shows the operation code map.

Instruction code 1st byte 2nd byte

AH AL BH BL

Instruction when most significant bit of BH is 0.

Instruction when most significant bit of BH is 1.

NOP

BRA

MULXU

BSET

Note: * Cannot be used in this LSI.

BRN

DIVXU

BNOT

BHI

MULXU

BCLR

BLS

DIVXU

BTST

STC

STMAC

LDC

LDMAC

ORC

BCC

RTS

BORBIOR

ANDC

AND

BNE

RTE

AND

XORC

XOR

BCS

BSR

XOR

BXOR

BIXOR

BAND

BIAND

LDC

BEQ

TRAPA

BST BIST

BLD BILD

BVC

MOV

BVS

BPL

JMP

BMI

EEPMOV

BGE

BSR

BLT

MOV

ADDX

SUBX

BGT

JSR

BLE

MOV.B

ADD

ADDX

CMP

SUBX

XOR

AND

MOV

ADD

SUB

MOV

CMP

Table

A.3(2)

Table

A.3(2)

Table

A.3(2) Table

A.3(2)

Table

A.3(2) Table

A.3(2)

Table

A.3(2) Table

A.3(2)

Table

A.3(2)

Table

A.3(2)

Table

A.3(2)

Table

A.3(2)

Table

A.3(2)

Table A.3(3)

Table A-3 Operation Code Map (1)

821

Instruction code 1st byte 2nd byte

AH AL BH BL

MOV

INC

ADDS

DAA

DEC

SUBS

DAS

BRA

MOV

SHLL

SHLR

ROTXL

ROTXR

NOT

LDM

BRN

ADD

BHI

MOV

CMP

STM

NOT

BLS

SUB

SHLL

SHLR

ROTXL

ROTXR

BCC

MOVFPE

INC

EXTU

DEC

BCS

XOR

MAC

BNE

AND

INC

SHLL

SHLR

ROTXL

ROTXR

EXTU

DEC

BEQ

LDCSTC

SLEEP

BVC

MOV

ADDS

SHAL

SHAR

ROTL

ROTR

NEG

SUBS

BVS

CLRMAC

BPL

MOV

NEG

BMI

ADD

MOV

SUB

CMP

SHAL

SHAR

ROTL

ROTR

BGE

MOVTPE

INC

EXTS

DEC

BLT

TAS

BGT

INC

SHAL

SHAR

ROTL

ROTR

EXTS

DEC

BLE

AH AL

Table

A.3(3) Table

A.3(3)

Table

A.3(4) Table

A.3(4)

Table A-3 Operation Code Map (2)

Note: * Cannot be used in this LSI.

822

nstruction code 1st byte 2nd byte

AH AL BH BL

3rd byte 4th byte

CH CL DH DL

r is the register specification field.

aa is the absolute address specification.

Instruction when most significant bit of DH is 0.

Instruction when most significant bit of DH is 1.

Notes:

AH AL BH BL CH

01C05

01D05

01F06

7Cr06 *1

7Cr07 *1

7Dr06 *1

7Dr07 *1

7Eaa6 *2

7Eaa7 *2

7Faa6 *2

7Faa7 *2

MULXS

BSET

DIVXS

BNOT

MULXS

BCLR

DIVXS

BTST

XOR

AND

789ABCDEF

BOR

BIOR

BXOR

BIXOR BAND

BIAND

BLDBILD

BSTBIST

BOR

BIOR

BXOR

BIXOR BAND

BIAND

BLDBILD

BSTBIST

Table A-3 Operation Code Map (3)

823

Instruction code 1st byte 2nd byte

AH AL BH BL

3rd byte 4th byte

CH CL DH DL

Instruction when most significant bit of FH is 0.

Instruction when most significant bit of FH is 1.

5th byte 6th byte

EH EL FH FL

Instruction code 1st byte 2nd byte

AH AL BH BL

3rd byte 4th byte

CH CL DH DL

Instruction when most significant bit of HH is 0.

Instruction when most significant bit of HH is 1.

Note: * aa is the absolute address specification.

5th byte 6th byte

EH EL FH FL

7th byte 8th byte

GH GL HH HL

6A10aaaa6*

6A10aaaa7*

6A18aaaa6*

6A18aaaa7*

AHALBHBLCHCLDHDLEH

EL 0

BSET

BNOT

BCLR

BTST BOR

BIOR

BXOR

BIXORBAND

BIAND

BLDBILD

BSTBIST

456789ABCDEF

6A30aaaaaaaa6

6A30aaaaaaaa7

6A38aaaaaaaa6

6A38aaaaaaaa7

AHALBHBL ... FHFLGH

GL 0

BSET

BNOT

BCLR

BTST BOR

BIOR

BXOR

BIXORBAND

BIAND

BLDBILD

BSTBIST

456789ABCDEF

Table A-3 Operation Code Map (4)

824

A.4 Number of States Required for Instruction Execution

The tables in this section can be used to calculate the number of states required for instruction

execution by the CPU. Table A-5 indicates the number of instruction fetch, data read/write, and

other cycles occurring in each instruction. Table A-4 indicates the number of states required for

each cycle. The number of states required for execution of an instruction can be calculated from

these two tables as follows:

Execution states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN

Examples: Advanced mode, program code and stack located in external memory, on-chip

supporting modules accessed in two states with 8-bit bus width, external devices accessed in three

states with one wait state and 16-bit bus width.

1. BSET #0, @FFFFC7:8

From table A-5:

I = L = 2, J = K = M = N = 0

From table A-4:

SI = 4, SL = 2

Number of states required for execution = 2 × 4 + 2 × 2 = 12

2. JSR @@30

From table A-5:

I = J = K = 2, L = M = N = 0

From table A-4:

SI = SJ = SK = 4

Number of states required for execution = 2 × 4 + 2 × 4 + 2 × 4 = 24

825

Table A-4 Number of States per Cycle

Access Conditions

On-Chip Supporting External Device

Module 8-Bit Bus 16-Bit Bus

Cycle On-Chip

Memory 8-Bit

Bus 16-Bit

Bus 2-State

Access 3-State

Access 2-State

Access 3-State

Access

Instruction fetch SI1 4 2 4 6 + 2m 2 3 + m

Branch address read SJ

Stack operation SK

Byte data access SL2 2 3 + m

Word data access SM4 4 6 + 2m

Internal operation SN11 1 1111

Legend

m: Number of wait states inserted into external device access

826

Table A-5 Number of Cycles in Instruction Execution

Instruction

Fetch

Branch

Address

Read Stack

Operation

Byte

Data

Access

Word

Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

ADD ADD.B #xx:8,Rd 1

ADD.B Rs,Rd 1

ADD.W #xx:16,Rd 2

ADD.W Rs,Rd 1

ADD.L #xx:32,ERd 3

ADD.L ERs,ERd 1

ADDS ADDS #1/2/4,ERd 1

ADDX ADDX #xx:8,Rd 1

ADDX Rs,Rd 1

AND AND.B #xx:8,Rd 1

AND.B Rs,Rd 1

AND.W #xx:16,Rd 2

AND.W Rs,Rd 1

AND.L #xx:32,ERd 3

AND.L ERs,ERd 2

ANDC ANDC #xx:8,CCR 1

ANDC #xx:8,EXR 2

BAND BAND #xx:3,Rd 1

BAND #xx:3,@ERd 2 1

BAND #xx:3,@aa:8 2 1

BAND #xx:3,@aa:16 3 1

BAND #xx:3,@aa:32 4 1

Bcc BRA d:8 (BT d:8) 2

BRN d:8 (BF d:8) 2

BHI d:8 2

BLS d:8 2

BCC d:8 (BHS d:8) 2

BCS d:8 (BLO d:8) 2

BNE d:8 2

BEQ d:8 2

BVC d:8 2

BVS d:8 2

BPL d:8 2

827

Instruction

Fetch

Branch

Address

Read Stack

Operation

Byte

Data

Access

Word

Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

Bcc BMI d:8 2

BGE d:8 2

BLT d:8 2

BGT d:8 2

BLE d:8 2

BRA d:16 (BT d:16) 2 1

BRN d:16 (BF d:16) 2 1

BHI d:16 2 1

BLS d:16 2 1

BCC d:16 (BHS d:16) 2 1

BCS d:16 (BLO d:16) 2 1

BNE d:16 2 1

BEQ d:16 2 1

BVC d:16 2 1

BVS d:16 2 1

BPL d:16 2 1

BMI d:16 2 1

BGE d:16 2 1

BLT d:16 2 1

BGT d:16 2 1

BLE d:16 2 1

BCLR BCLR #xx:3,Rd 1

BCLR #xx:3,@ERd 2 2

BCLR #xx:3,@aa:8 2 2

BCLR #xx:3,@aa:16 3 2

BCLR #xx:3,@aa:32 4 2

BCLR Rn,Rd 1

BCLR Rn,@ERd 2 2

BCLR Rn,@aa:8 2 2

BCLR Rn,@aa:16 3 2

BCLR Rn,@aa:32 4 2

828

Instruction

Fetch

Branch

Address

Read Stack

Operation

Byte

Data

Access

Word

Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

BIAND BIAND #xx:3,Rd 1

BIAND #xx:3,@ERd 2 1

BIAND #xx:3,@aa:8 2 1

BIAND #xx:3,@aa:16 3 1

BIAND #xx:3,@aa:32 4 1

BILD BILD #xx:3,Rd 1

BILD #xx:3,@ERd 2 1

BILD #xx:3,@aa:8 2 1

BILD #xx:3,@aa:16 3 1

BILD #xx:3,@aa:32 4 1

BIOR BIOR #xx:8,Rd 1

BIOR #xx:8,@ERd 2 1

BIOR #xx:8,@aa:8 2 1

BIOR #xx:8,@aa:16 3 1

BIOR #xx:8,@aa:32 4 1

BIST BIST #xx:3,Rd 1

BIST #xx:3,@ERd 2 2

BIST #xx:3,@aa:8 2 2

BIST #xx:3,@aa:16 3 2

BIST #xx:3,@aa:32 4 2

BIXOR BIXOR #xx:3,Rd 1

BIXOR #xx:3,@ERd 2 1

BIXOR #xx:3,@aa:8 2 1

BIXOR #xx:3,@aa:16 3 1

BIXOR #xx:3,@aa:32 4 1

BLD BLD #xx:3,Rd 1

BLD #xx:3,@ERd 2 1

BLD #xx:3,@aa:8 2 1

BLD #xx:3,@aa:16 3 1

BLD #xx:3,@aa:32 4 1

829

Instruction

Fetch

Branch

Address

Read Stack

Operation

Byte

Data

Access

Word

Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

BNOT BNOT #xx:3,Rd 1

BNOT #xx:3,@ERd 2 2

BNOT #xx:3,@aa:8 2 2

BNOT #xx:3,@aa:16 3 2

BNOT #xx:3,@aa:32 4 2

BNOT Rn,Rd 1

BNOT Rn,@ERd 2 2

BNOT Rn,@aa:8 2 2

BNOT Rn,@aa:16 3 2

BNOT Rn,@aa:32 4 2

BOR BOR #xx:3,Rd 1

BOR #xx:3,@ERd 2 1

BOR #xx:3,@aa:8 2 1

BOR #xx:3,@aa:16 3 1

BOR #xx:3,@aa:32 4 1

BSET BSET #xx:3,Rd 1

BSET #xx:3,@ERd 2 2

BSET #xx:3,@aa:8 2 2

BSET #xx:3,@aa:16 3 2

BSET #xx:3,@aa:32 4 2

BSET Rn,Rd 1

BSET Rn,@ERd 2 2

BSET Rn,@aa:8 2 2

BSET Rn,@aa:16 3 2

BSET Rn,@aa:32 4 2

BSR BSR d:8 2 2

BSR d:16 2 2 1

BST BST #xx:3,Rd 1

BST #xx:3,@ERd 2 2

BST #xx:3,@aa:8 2 2

BST #xx:3,@aa:16 3 2

BST #xx:3,@aa:32 4 2

830

Instruction

Fetch

Branch

Address

Read Stack

Operation

Byte

Data

Access

Word

Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

BTST BTST #xx:3,Rd 1

BTST #xx:3,@ERd 2 1

BTST #xx:3,@aa:8 2 1

BTST #xx:3,@aa:16 3 1

BTST #xx:3,@aa:32 4 1

BTST Rn,Rd 1

BTST Rn,@ERd 2 1

BTST Rn,@aa:8 2 1

BTST Rn,@aa:16 3 1

BTST Rn,@aa:32 4 1

BXOR BXOR #xx:3,Rd 1

BXOR #xx:3,@ERd 2 1

BXOR #xx:3,@aa:8 2 1

BXOR #xx:3,@aa:16 3 1

BXOR #xx:3,@aa:32 4 1

CLRMAC CLRMAC 1 1*1

CMP CMP.B #xx:8,Rd 1

CMP.B Rs,Rd 1

CMP.W #xx:16,Rd 2

CMP.W Rs,Rd 1

CMP.L #xx:32,ERd 3

CMP.L ERs,ERd 1

DAA DAA Rd 1

DAS DAS Rd 1

DEC DEC.B Rd 1

DEC.W #1/2,Rd 1

DEC.L #1/2,ERd 1

DIVXS DIVXS.B Rs,Rd 2 11

DIVXS.W Rs,ERd 2 19

DIVXU DIVXU.B Rs,Rd 1 11

DIVXU.W Rs,ERd 1 19

831

Instruction

Fetch

Branch

Address

Read Stack

Operation

Byte

Data

Access

Word

Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

EEPMOV EEPMOV.B 2 2n+2*2

EEPMOV.W 2 2n+2*2

EXTS EXTS.W Rd 1

EXTS.L ERd 1

EXTU EXTU.W Rd 1

EXTU.L ERd 1

INC INC.B Rd 1

INC.W #1/2,Rd 1

INC.L #1/2,ERd 1

JMP JMP @ERn 2

JMP @aa:24 2 1

JMP @@aa:8 2 2 1

JSR JSR @ERn 2 2

JSR @aa:24 2 2 1

JSR @@aa:8 2 2 2

LDC LDC #xx:8,CCR 1

LDC #xx:8,EXR 2

LDC Rs,CCR 1

LDC Rs,EXR 1

LDC @ERs,CCR 2 1

LDC @ERs,EXR 2 1

LDC @(d:16,ERs),CCR 3 1

LDC @(d:16,ERs),EXR 3 1

LDC @(d:32,ERs),CCR 5 1

LDC @(d:32,ERs),EXR 5 1

LDC @ERs+,CCR 2 1 1

LDC @ERs+,EXR 2 1 1

LDC @aa:16,CCR 3 1

LDC @aa:16,EXR 3 1

LDC @aa:32,CCR 4 1

LDC @aa:32,EXR 4 1

832

Instruction

Fetch

Branch

Address

Read Stack

Operation

Byte

Data

Access

Word

Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

LDM LDM.L @SP+,

(ERn-ERn+1) 24 1

LDM.L @SP+,

(ERn-ERn+2) 26 1

LDM.L @SP+,

(ERn-ERn+3) 28 1

LDMAC LDMAC ERs,MACH 1 1*1

LDMAC ERs,MACL 1 1*1

MAC MAC @ERn+,@ERm+ 2 2

MOV MOV.B #xx:8,Rd 1

MOV.B Rs,Rd 1

MOV.B @ERs,Rd 1 1

MOV.B @(d:16,ERs),Rd 2 1

MOV.B @(d:32,ERs),Rd 4 1

MOV.B @ERs+,Rd 1 1 1

MOV.B @aa:8,Rd 1 1

MOV.B @aa:16,Rd 2 1

MOV.B @aa:32,Rd 3 1

MOV.B Rs,@ERd 1 1

MOV.B Rs,@(d:16,ERd) 2 1

MOV.B Rs,@(d:32,ERd) 4 1

MOV.B Rs,@-ERd 1 1 1

MOV.B Rs,@aa:8 1 1

MOV.B Rs,@aa:16 2 1

MOV.B Rs,@aa:32 3 1

MOV.W #xx:16,Rd 2

MOV.W Rs,Rd 1

MOV.W @ERs,Rd 1 1

MOV.W @(d:16,ERs),Rd 2 1

MOV.W @(d:32,ERs),Rd 4 1

MOV.W @ERs+,Rd 1 1 1

MOV.W @aa:16,Rd 2 1

MOV.W @aa:32,Rd 3 1

MOV.W Rs,@ERd 1 1

833

Instruction

Fetch

Branch

Address

Read Stack

Operation

Byte

Data

Access

Word

Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

MOV MOV.W Rs,@(d:16,ERd) 2 1

MOV.W Rs,@(d:32,ERd) 4 1

MOV.W Rs,@-ERd 1 1 1

MOV.W Rs,@aa:16 2 1

MOV.W Rs,@aa:32 3 1

MOV.L #xx:32,ERd 3

MOV.L ERs,ERd 1

MOV.L @ERs,ERd 2 2

MOV.L @(d:16,ERs),ERd 3 2

MOV.L @(d:32,ERs),ERd 5 2

MOV.L @ERs+,ERd 2 2 1

MOV.L @aa:16,ERd 3 2

MOV.L @aa:32,ERd 4 2

MOV.L ERs,@ERd 2 2

MOV.L ERs,@(d:16,ERd) 3 2

MOV.L ERs,@(d:32,ERd) 5 2

MOV.L ERs,@-ERd 2 2 1

MOV.L ERs,@aa:16 3 2

MOV.L ERs,@aa:32 4 2

MOVFPE MOVFPE @:aa:16,Rd Can not be used in this LSI

MOVTPE MOVTPE Rs,@:aa:16

MULXS MULXS.B Rs,Rd 2 2

MULXS.W Rs,ERd 2 3

MULXU MULXU.B Rs,Rd 1 2

MULXU.W Rs,ERd 1 3

NEG NEG.B Rd 1

NEG.W Rd 1

NEG.L ERd 1

NOP NOP 1

NOT NOT.B Rd 1

NOT.W Rd 1

NOT.L ERd 1

834

Instruction

Fetch

Branch

Address

Read Stack

Operation

Byte

Data

Access

Word

Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

OR OR.B #xx:8,Rd 1

OR.B Rs,Rd 1

OR.W #xx:16,Rd 2

OR.W Rs,Rd 1

OR.L #xx:32,ERd 3

OR.L ERs,ERd 2

ORC ORC #xx:8,CCR 1

ORC #xx:8,EXR 2

POP POP.W Rn 1 1 1

POP.L ERn 2 2 1

PUSH PUSH.W Rn 1 1 1

PUSH.L ERn 2 2 1

ROTL ROTL.B Rd 1

ROTL.B #2,Rd 1

ROTL.W Rd 1

ROTL.W #2,Rd 1

ROTL.L ERd 1

ROTL.L #2,ERd 1

ROTR ROTR.B Rd 1

ROTR.B #2,Rd 1

ROTR.W Rd 1

ROTR.W #2,Rd 1

ROTR.L ERd 1

ROTR.L #2,ERd 1

ROTXL ROTXL.B Rd 1

ROTXL.B #2,Rd 1

ROTXL.W Rd 1

ROTXL.W #2,Rd 1

ROTXL.L ERd 1

ROTXL.L #2,ERd 1

835

Instruction

Fetch

Branch

Address

Read Stack

Operation

Byte

Data

Access

Word

Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

ROTXR ROTXR.B Rd 1

ROTXR.B #2,Rd 1

ROTXR.W Rd 1

ROTXR.W #2,Rd 1

ROTXR.L ERd 1

ROTXR.L #2,ERd 1

RTE RTE 2 2/3*31

RTS RTS 2 2 1

SHAL SHAL.B Rd 1

SHAL.B #2,Rd 1

SHAL.W Rd 1

SHAL.W #2,Rd 1

SHAL.L ERd 1

SHAL.L #2,ERd 1

SHAR SHAR.B Rd 1

SHAR.B #2,Rd 1

SHAR.W Rd 1

SHAR.W #2,Rd 1

SHAR.L ERd 1

SHAR.L #2,ERd 1

SHLL SHLL.B Rd 1

SHLL.B #2,Rd 1

SHLL.W Rd 1

SHLL.W #2,Rd 1

SHLL.L ERd 1

SHLL.L #2,ERd 1

SHLR SHLR.B Rd 1

SHLR.B #2,Rd 1

SHLR.W Rd 1

SHLR.W #2,Rd 1

SHLR.L ERd 1

SHLR.L #2,ERd 1

SLEEP SLEEP 1 1

836

Instruction

Fetch

Branch

Address

Read Stack

Operation

Byte

Data

Access

Word

Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

STC STC.B CCR,Rd 1

STC.B EXR,Rd 1

STC.W CCR,@ERd 2 1

STC.W EXR,@ERd 2 1

STC.W CCR,@(d:16,ERd) 3 1

STC.W EXR,@(d:16,ERd) 3 1

STC.W CCR,@(d:32,ERd) 5 1

STC.W EXR,@(d:32,ERd) 5 1

STC.W CCR,@-ERd 2 1 1

STC.W EXR,@-ERd 2 1 1

STC.W CCR,@aa:16 3 1

STC.W EXR,@aa:16 3 1

STC.W CCR,@aa:32 4 1

STC.W EXR,@aa:32 4 1

STM STM.L (ERn-ERn+1),

@-SP 24 1

STM.L (ERn-ERn+2),

@-SP 26 1

STM.L (ERn-ERn+3),

@-SP 28 1

STMAC STMAC MACH,ERd 1 *1

STMAC MACL,ERd 1 *1

SUB SUB.B Rs,Rd 1

SUB.W #xx:16,Rd 2

SUB.W Rs,Rd 1

SUB.L #xx:32,ERd 3

SUB.L ERs,ERd 1

SUBS SUBS #1/2/4,ERd 1

SUBX SUBX #xx:8,Rd 1

SUBX Rs,Rd 1

TAS TAS @ERd*422

TRAPA TRAPA #x:2 2 2 2/3*32

837

Instruction

Fetch

Branch

Address

Read Stack

Operation

Byte

Data

Access

Word

Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

XOR XOR.B #xx:8,Rd 1

XOR.B Rs,Rd 1

XOR.W #xx:16,Rd 2

XOR.W Rs,Rd 1

XOR.L #xx:32,ERd 3

XOR.L ERs,ERd 2

XORC XORC #xx:8,CCR 1

XORC #xx:8,EXR 2

Notes: *1 An internal operation may require between 0 and 3 additional states, depending on the

preceding instruction.

*2 When n bytes of data are transferred.

*3 2 when EXR is invalid, 3 when EXR is valid.

*4 Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

838

A.5 Bus States During Instruction Execution

Table A-6 indicates the types of cycles that occur during instruction execution by the CPU. See

table A-4 for the number of states per cycle.

How to Read the Table:

Instruction

JMP@aa:24 R:W 2nd

Internal operation,

1 state

R:W EA

12345678

End of instruction

Order of execution

Read effective address (word-size read)

No read or write

Read 2nd word of current instruction

(word-size read)

Legend

R:B Byte-size read

R:W Word-size read

W:B Byte-size write

W:W Word-size write

:M Transfer of the bus is not performed immediately after this cycle

2nd Address of 2nd word (3rd and 4th bytes)

3rd Address of 3rd word (5th and 6th bytes)

4th Address of 4th word (7th and 8th bytes)

5th Address of 5th word (9th and 10th bytes)

NEXT Address of next instruction

EA Effective address

VEC Vector address

839

Figure A-1 shows timing waveforms for the address bus and the RD, HWR, and LWR signals

during execution of the above instruction with an 8-bit bus, using three-state access with no wait

states.

ddress bus

WR, LWR

R:W 2nd

Fetching

2nd byte of

instruction at

jump address

Fetching

1nd byte of

instruction at

jump address

Fetching

4th byte

of instruction

Fetching

3rd byte

of instruction

R:W EA

High level

Internal

operation

Figure A-1 Address Bus, RD, HWR, and LWR Timing

(8-Bit Bus, Three-State Access, No Wait States)

840

Instruction

ADD.B #xx:8,Rd R:W NEXT

ADD.B Rs,Rd R:W NEXT

ADD.W #xx:16,Rd R:W 2nd R:W NEXT

ADD.W Rs,Rd R:W NEXT

ADD.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT

ADD.L ERs,ERd R:W NEXT

ADDS #1/2/4,ERd R:W NEXT

ADDX #xx:8,Rd R:W NEXT

ADDX Rs,Rd R:W NEXT

AND.B #xx:8,Rd R:W NEXT

AND.B Rs,Rd R:W NEXT

AND.W #xx:16,Rd R:W 2nd R:W NEXT

AND.W Rs,Rd R:W NEXT

AND.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT

AND.L ERs,ERd R:W 2nd R:W NEXT

ANDC #xx:8,CCR R:W NEXT

ANDC #xx:8,EXR R:W 2nd R:W NEXT

BAND #xx:3,Rd R:W NEXT

BAND #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT

BAND #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT

BAND #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT

BAND #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT

BRA d:8 (BT d:8) R:W NEXT R:W EA

BRN d:8 (BF d:8) R:W NEXT R:W EA

BHI d:8 R:W NEXT R:W EA

BLS d:8 R:W NEXT R:W EA

BCC d:8 (BHS d:8) R:W NEXT R:W EA

BCS d:8 (BLO d:8) R:W NEXT R:W EA

BNE d:8 R:W NEXT R:W EA

BEQ d:8 R:W NEXT R:W EA

BVC d:8 R:W NEXT R:W EA

BVS d:8 R:W NEXT R:W EA

BPL d:8 R:W NEXT R:W EA

BMI d:8 R:W NEXT R:W EA

BGE d:8 R:W NEXT R:W EA

BLT d:8 R:W NEXT R:W EA

BGT d:8 R:W NEXT R:W EA

1234 56789

Table A-6 Instruction Execution Cycles

841

Instruction

BLE d:8 R:W NEXT R:W EA

BRA d:16 (BT d:16) R:W 2nd

Internal operation,

R:W EA

1 state

BRN d:16 (BF d:16) R:W 2nd

Internal operation,

R:W EA

1 state

BHI d:16 R:W 2nd

Internal operation,

R:W EA

1 state

BLS d:16 R:W 2nd

Internal operation,

R:W EA

1 state

BCC d:16 (BHS d:16) R:W 2nd

Internal operation,

R:W EA

1 state

BCS d:16 (BLO d:16) R:W 2nd

Internal operation,

R:W EA

1 state

BNE d:16 R:W 2nd

Internal operation,

R:W EA

1 state

BEQ d:16 R:W 2nd

Internal operation,

R:W EA

1 state

BVC d:16 R:W 2nd

Internal operation,

R:W EA

1 state

BVS d:16 R:W 2nd

Internal operation,

R:W EA

1 state

BPL d:16 R:W 2nd

Internal operation,

R:W EA

1 state

BMI d:16 R:W 2nd

Internal operation,

R:W EA

1 state

BGE d:16 R:W 2nd

Internal operation,

R:W EA

1 state

BLT d:16 R:W 2nd

Internal operation,

R:W EA

1 state

BGT d:16 R:W 2nd

Internal operation,

R:W EA

1 state

BLE d:16 R:W 2nd

Internal operation,

R:W EA

1 state

BCLR #xx:3,Rd R:W NEXT

BCLR #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA

BCLR #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA

BCLR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA

1234 56789

842

Instruction

BCLR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA

BCLR Rn,Rd R:W NEXT

BCLR Rn,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA

BCLR Rn,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA

BCLR Rn,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA

BCLR Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA

BIAND #xx:3,Rd R:W NEXT

BIAND #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT

BIAND #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT

BIAND #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT

BIAND #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT

BILD #xx:3,Rd R:W NEXT

BILD #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT

BILD #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT

BILD #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT

BILD #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT

BIOR #xx:3,Rd R:W NEXT

BIOR #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT

BIOR #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT

BIOR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT

BIOR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT

BIST #xx:3,Rd R:W NEXT

BIST #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA

BIST #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA

BIST #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA

BIST #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA

BIXOR #xx:3,Rd R:W NEXT

BIXOR #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT

BIXOR #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT

BIXOR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT

BIXOR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT

BLD #xx:3,Rd R:W NEXT

BLD #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT

BLD #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT

BLD #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT

BLD #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT

BNOT #xx:3,Rd R:W NEXT

1234 56789

843

Instruction

BNOT #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA

BNOT #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA

BNOT #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA

BNOT #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA

BNOT Rn,Rd R:W NEXT

BNOT Rn,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA

BNOT Rn,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA

BNOT Rn,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA

BNOT Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA

BOR #xx:3,Rd R:W NEXT

BOR #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT

BOR #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT

BOR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT

BOR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT

BSET #xx:3,Rd R:W NEXT

BSET #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA

BSET #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA

BSET #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA

BSET #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA

BSET Rn,Rd R:W NEXT

BSET Rn,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA

BSET Rn,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA

BSET Rn,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA

BSET Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA

BSR d:8 R:W NEXT R:W EA

W:W

stack (H)

W:W stack (L)

BSR d:16 R:W 2nd

Internal operation,

R:W EA

W:W

stack (H)

W:W stack (L)

1 state

BST #xx:3,Rd R:W NEXT

BST #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA

BST #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA

BST #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA

BST #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA

BTST #xx:3,Rd R:W NEXT

BTST #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT

1234 56789

844

Instruction 1234 56789

BTST #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT

BTST #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT

BTST #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT

BTST Rn,Rd R:W NEXT

BTST Rn,@ERd R:W 2nd R:B EA R:W:M NEXT

BTST Rn,@aa:8 R:W 2nd R:B EA R:W:M NEXT

BTST Rn,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT

BTST Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT

BXOR #xx:3,Rd R:W NEXT

BXOR #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT

BXOR #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT

BXOR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT

BXOR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT

CLRMAC R:W NEXT

Internal operation,

1 state

CMP.B #xx:8,Rd R:W NEXT

CMP.B Rs,Rd R:W NEXT

CMP.W #xx:16,Rd R:W 2nd R:W NEXT

CMP.W Rs,Rd R:W NEXT

CMP.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT

CMP.L ERs,ERd R:W NEXT

DAA Rd R:W NEXT

DAS Rd R:W NEXT

DEC.B Rd R:W NEXT

DEC.W #1/2,Rd R:W NEXT

DEC.L #1/2,ERd R:W NEXT

DIVXS.B Rs,Rd R:W 2nd R:W NEXT Internal operation, 11 states

DIVXS.W Rs,ERd R:W 2nd R:W NEXT Internal operation, 19 states

DIVXU.B Rs,Rd R:W NEXT Internal operation, 11 states

DIVXU.W Rs,ERd R:W NEXT Internal operation, 19 states

EEPMOV.B R:W 2nd R:B EAs*1R:B EAd*1R:B EAs*2W:B EAd*2R:W NEXT

EEPMOV.W R:W 2nd R:B EAs*1R:B EAd*1R:B EAs*2W:B EAd*2R:W NEXT

EXTS.W Rd R:W NEXT ← Repeated n times*2 →

EXTS.L ERd R:W NEXT

EXTU.W Rd R:W NEXT

EXTU.L ERd R:W NEXT

INC.B Rd R:W NEXT

845

Instruction

INC.W #1/2,Rd R:W NEXT

INC.L #1/2,ERd R:W NEXT

JMP @ERn R:W NEXT R:W EA

JMP @aa:24 R:W 2nd

Internal operation,

R:W EA

1 state

JMP @@aa:8 R:W NEXT R:W:M aa:8 R:W aa:8

Internal operation,

R:W EA

1 state

JSR @ERn R:W NEXT R:W EA

W:W

stack (H) W:W stack (L)

JSR @aa:24 R:W 2nd

Internal operation,

R:W EA

W:W

stack (H) W:W stack (L)

1 state

JSR @@aa:8 R:W NEXT R:W:M aa:8 R:W aa:8

W:W

stack (H) W:W stack (L)

R:W EA

LDC #xx:8,CCR R:W NEXT

LDC #xx:8,EXR R:W 2nd R:W NEXT

LDC Rs,CCR R:W NEXT

LDC Rs,EXR R:W NEXT

LDC @ERs,CCR R:W 2nd R:W NEXT R:W EA

LDC @ERs,EXR R:W 2nd R:W NEXT R:W EA

LDC @(d:16,ERs),CCR R:W 2nd R:W 3rd R:W NEXT R:W EA

LDC @(d:16,ERs),EXR R:W 2nd R:W 3rd R:W NEXT R:W EA

LDC @(d:32,ERs),CCR R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT R:W EA

LDC @(d:32,ERs),EXR R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT R:W EA

LDC @ERs+,CCR R:W 2nd R:W NEXT

Internal operation,

R:W EA

1 state

LDC @ERs+,EXR R:W 2nd R:W NEXT

Internal operation,

R:W EA

1 state

LDC @aa:16,CCR R:W 2nd R:W 3rd R:W NEXT R:W EA

LDC @aa:16,EXR R:W 2nd R:W 3rd R:W NEXT R:W EA

LDC @aa:32,CCR R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA

LDC @aa:32,EXR R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA

LDM.L @SP+, R:W 2nd R:W:M NEXT

Internal operation,

R:W:M stack (H)

R:W stack (L)

(ERn–ERn+1)

1 state

LDM.L @SP+,(ERn–ERn+2)

R:W 2nd R:W NEXT

Internal operation,

R:W:M stack (H)

R:W stack (L)

1 state

LDM.L @SP+,(ERn–ERn+3)

R:W 2nd R:W NEXT

Internal operation,

R:W:M stack (H)

R:W stack (L)

1 state

LDMAC ERs,MACH R:W NEXT

Internal operation, ←Repeated n times

→

1 state

1234 56789

846

Instruction

LDMAC ERs,MACL R:W NEXT

Internal operation,

1 state

MAC @ERn+,@ERm+ R:W 2nd R:W NEXT R:W EAh R:W EAm

MOV.B #xx:8,Rd R:W NEXT

MOV.B Rs,Rd R:W NEXT

MOV.B @ERs,Rd R:W NEXT R:B EA

MOV.B @(d:16,ERs),Rd R:W 2nd R:W NEXT R:B EA

MOV.B @(d:32,ERs),Rd R:W 2nd R:W 3rd R:W 4th R:W NEXT R:B EA

MOV.B @ERs+,Rd R:W NEXT

Internal operation,

R:B EA

1 state

MOV.B @aa:8,Rd R:W NEXT R:B EA

MOV.B @aa:16,Rd R:W 2nd R:W NEXT R:B EA

MOV.B @aa:32,Rd R:W 2nd R:W 3rd R:W NEXT R:B EA

MOV.B Rs,@ERd R:W NEXT W:B EA

MOV.B Rs,@(d:16,ERd) R:W 2nd R:W NEXT W:B EA

MOV.B Rs,@(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W NEXT W:B EA

MOV.B Rs,@–ERd R:W NEXT

Internal operation,

W:B EA

1 state

MOV.B Rs,@aa:8 R:W NEXT W:B EA

MOV.B Rs,@aa:16 R:W 2nd R:W NEXT W:B EA

MOV.B Rs,@aa:32 R:W 2nd R:W 3rd R:W NEXT W:B EA

MOV.W #xx:16,Rd R:W 2nd R:W NEXT

MOV.W Rs,Rd R:W NEXT

MOV.W @ERs,Rd R:W NEXT R:W EA

MOV.W @(d:16,ERs),Rd R:W 2nd R:W NEXT R:W EA

MOV.W @(d:32,ERs),Rd R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA

MOV.W @ERs+, Rd R:W NEXT

Internal operation,

R:W EA

1 state

MOV.W @aa:16,Rd R:W 2nd R:W NEXT R:W EA

MOV.W @aa:32,Rd R:W 2nd R:W 3rd R:W NEXT R:B EA

MOV.W Rs,@ERd R:W NEXT W:W EA

MOV.W Rs,@(d:16,ERd) R:W 2nd R:W NEXT W:W EA

MOV.W Rs,@(d:32,ERd) R:W 2nd R:W 3rd R:E 4th R:W NEXT W:W EA

MOV.W Rs,@–ERd R:W NEXT

Internal operation,

W:W EA

1 state

MOV.W Rs,@aa:16 R:W 2nd R:W NEXT W:W EA

MOV.W Rs,@aa:32 R:W 2nd R:W 3rd R:W NEXT W:W EA

1234 56789

847

Instruction 1234 56789

MOV.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT

MOV.L ERs,ERd R:W NEXT

MOV.L @ERs,ERd R:W 2nd R:W:M NEXT R:W:M EA R:W EA+2

MOV.L @(d:16,ERs),ERd R:W 2nd R:W:M 3rd R:W NEXT R:W:M EA R:W EA+2

MOV.L @(d:32,ERs),ERd R:W 2nd R:W:M 3rd R:W:M 4th R:W 5th R:W NEXT R:W:M EA R:W EA+2

MOV.L @ERs+,ERd R:W 2nd R:W:M NEXT

Internal operation,

R:W:M EA R:W EA+2

1 state

MOV.L @aa:16,ERd R:W 2nd R:W:M 3rd R:W NEXT R:W:M EA R:W EA+2

MOV.L @aa:32,ERd R:W 2nd R:W:M 3rd R:W 4th R:W NEXT R:W:M EA R:W EA+2

MOV.L ERs,@ERd R:W 2nd R:W:M NEXT W:W:M EA W:W EA+2

MOV.L ERs,@(d:16,ERd) R:W 2nd R:W:M 3rd R:W NEXT W:W:M EA W:W EA+2

MOV.L ERs,@(d:32,ERd) R:W 2nd R:W:M 3rd R:W:M 4th R:W 5th R:W NEXT W:W:M EA W:W EA+2

MOV.L ERs,@–ERd R:W 2nd R:W:M NEXT

Internal operation,

W:W:M EA W:W EA+2

1 state

MOV.L ERs,@aa:16 R:W 2nd R:W:M 3rd R:W NEXT W:W:M EA W:W EA+2

MOV.L ERs,@aa:32 R:W 2nd R:W:M 3rd R:W 4th R:W NEXT W:W:M EA W:W EA+2

MOVFPE @aa:16,Rd Cannot be used in this LSI

MOVTPE Rs,@aa:16

MULXS.B Rs,Rd R:W 2nd R:W NEXT Internal operation, 2 states

MULXS.W Rs,ERd R:W 2nd R:W NEXT Internal operation, 3 states

MULXU.B Rs,Rd R:W NEXT Internal operation, 2 states

MULXU.W Rs,ERd R:W NEXT Internal operation, 3 states

NEG.B Rd R:W NEXT

NEG.W Rd R:W NEXT

NEG.L ERd R:W NEXT

NOP R:W NEXT

NOT.B Rd R:W NEXT

NOT.W Rd R:W NEXT

NOT.L ERd R:W NEXT

OR.B #xx:8,Rd R:W NEXT

OR.B Rs,Rd R:W NEXT

OR.W #xx:16,Rd R:W 2nd R:W NEXT

OR.W Rs,Rd R:W NEXT

OR.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT

OR.L ERs,ERd R:W 2nd R:W NEXT

ORC #xx:8,CCR R:W NEXT

ORC #xx:8,EXR R:W 2nd R:W NEXT

848

Instruction

POP.W Rn R:W NEXT

Internal operation,

R:W EA

1 state

POP.L ERn R:W 2nd R:W:M NEXT

Internal operation,

R:W:M EA R:W EA+2

1 state

PUSH.W Rn R:W NEXT

Internal operation,

W:W EA

1 state

PUSH.L ERn R:W 2nd R:W:M NEXT

Internal operation,

W:W:M EA W:W EA+2

1 state

ROTL.B Rd R:W NEXT

ROTL.B #2,Rd R:W NEXT

ROTL.W Rd R:W NEXT

ROTL.W #2,Rd R:W NEXT

ROTL.L ERd R:W NEXT

ROTL.L #2,ERd R:W NEXT

ROTR.B Rd R:W NEXT

ROTR.B #2,Rd R:W NEXT

ROTR.W Rd R:W NEXT

ROTR.W #2,Rd R:W NEXT

ROTR.L ERd R:W NEXT

ROTR.L #2,ERd R:W NEXT

ROTXL.B Rd R:W NEXT

ROTXL.B #2,Rd R:W NEXT

ROTXL.W Rd R:W NEXT

ROTXL.W #2,Rd R:W NEXT

ROTXL.L ERd R:W NEXT

ROTXL.L #2,ERd R:W NEXT

ROTXR.B Rd R:W NEXT

ROTXR.B #2,Rd R:W NEXT

ROTXR.W Rd R:W NEXT

ROTXR.W #2,Rd R:W NEXT

ROTXR.L ERd R:W NEXT

ROTXR.L #2,ERd R:W NEXT

RTE R:W NEXT

R:W stack (EXR) R:W stack (H) R:W stack (L)

Internal operation,

R:W*4

1 state

RTS R:W NEXT

R:W:M stack (H) R:W stack (L)

Internal operation,

R:W*4

1 state

SHAL.B Rd R:W NEXT

1234 56789

849

Instruction

SHAL.B #2,Rd R:W NEXT

SHAL.W Rd R:W NEXT

SHAL.W #2,Rd R:W NEXT

SHAL.L ERd R:W NEXT

SHAL.L #2,ERd R:W NEXT

SHAR.B Rd R:W NEXT

SHAR.B #2,Rd R:W NEXT

SHAR.W Rd R:W NEXT

SHAR.W #2,Rd R:W NEXT

SHAR.L ERd R:W NEXT

SHAR.L #2,ERd R:W NEXT

SHLL.B Rd R:W NEXT

SHLL.B #2,Rd R:W NEXT

SHLL.W Rd R:W NEXT

SHLL.W #2,Rd R:W NEXT

SHLL.L ERd R:W NEXT

SHLL.L #2,ERd R:W NEXT

SHLR.B Rd R:W NEXT

SHLR.B #2,Rd R:W NEXT

SHLR.W Rd R:W NEXT

SHLR.W #2,Rd R:W NEXT

SHLR.L ERd R:W NEXT

SHLR.L #2,ERd R:W NEXT

SLEEP R:W NEXT

Internal operation:M

STC CCR,Rd R:W NEXT

STC EXR,Rd R:W NEXT

STC CCR,@ERd R:W 2nd R:W NEXT W:W EA

STC EXR,@ERd R:W 2nd R:W NEXT W:W EA

STC CCR,@(d:16,ERd) R:W 2nd R:W 3rd R:W NEXT W:W EA

STC EXR,@(d:16,ERd)

R:W 2nd R:W 3rd R:W NEXT W:W EA

STC CCR,@(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT W:W EA

STC EXR,@(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT W:W EA

STC CCR,@–ERd R:W 2nd R:W NEXT

Internal operation,

W:W EA

1 state

STC EXR,@–ERd R:W 2nd R:W NEXT

Internal operation,

W:W EA

1 state

STC CCR,@aa:16 R:W 2nd R:W 3rd R:W NEXT W:W EA

STC EXR,@aa:16 R:W 2nd R:W 3rd R:W NEXT W:W EA

1234 56789

850

Instruction

STC CCR,@aa:32 R:W 2nd R:W 3rd R:W 4th R:W NEXT W:W EA

STC EXR,@aa:32 R:W 2nd R:W 3rd R:W 4th R:W NEXT W:W EA

STM.L(ERn–ERn+1),@–SP

R:W 2nd R:W:M NEXT

Internal operation,

W:W:M stack (H)

W:W stack (L)

1 state

STM.L(ERn–ERn+2),@–SP

R:W 2nd R:W:M NEXT

Internal operation,

W:W:M stack (H)

W:W stack (L)

1 state

STM.L(ERn–ERn+3),@–SP

R:W 2nd R:W:M NEXT

Internal operation,

W:W:M stack (H)

W:W stack (L)

1 state

STMAC MACH,ERd R:W NEXT

STMAC MACL,ERd R:W NEXT

SUB.B Rs,Rd R:W NEXT

SUB.W #xx:16,Rd R:W 2nd R:W NEXT

SUB.W Rs,Rd R:W NEXT

SUB.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT

SUB.L ERs,ERd R:W NEXT

SUBS #1/2/4,ERd R:W NEXT

SUBX #xx:8,Rd R:W NEXT

SUBX Rs,Rd R:W NEXT

TAS @ERd*8R:W 2nd R:W NEXT R:B:M EA W:B EA

TRAPA #x:2 R:W NEXT

Internal operation,

W:W stack (L) W:W stack (H) W:W stack (EXR)

R:W:M VEC R:W VEC+2

Internal operation,

R:W*7

1 state 1 state

XOR.B #xx8,Rd R:W NEXT

XOR.B Rs,Rd R:W NEXT

XOR.W #xx:16,Rd R:W 2nd R:W NEXT

XOR.W Rs,Rd R:W NEXT

XOR.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT

XOR.L ERs,ERd R:W 2nd R:W NEXT

XORC #xx:8,CCR R:W NEXT

XORC #xx:8,EXR R:W 2nd R:W NEXT

1234 56789

851

Instruction

Reset exception handling

R:W VEC R:W VEC+2

Internal operation,

R:W*5

1 state

Interrupt exception handling

R:W*6

Internal operation,

W:W stack (L) W:W stack (H)

W:W stack (EXR)

R:W:M VEC R:W VEC+2

Internal operation,

R:W*7

1 state 1 state

Notes: *1 EAs is the contents of ER5. EAd is the contents of ER6.

*2 EAs is the contents of ER5. EAd is the contents of ER6. Both registers are incremented by 1 after execution of the instruction. n is the initial

value of R4L or R4. If n = 0, these bus cycles are not executed.

*3 Repeated two times to save or restore two registers, three times for three registers, or four times for four registers.

*4 Start address after return.

*5 Start address of the program.

*6 Prefetch address, equal to two plus the PC value pushed onto the stack. In recovery from sleep mode or software standby mode the read

operation is replaced by an internal operation.

*7 Start address of the interrupt-handling routine.

*8 Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

1234 56789

852

A.6 Condition Code Modification

This section indicates the effect of each CPU instruction on the condition code. The notation used

in the table is defined below.

m = 31 for longword operands

15 for word operands

7 for byte operands

—

The i-th bit of the source operand

The i-th bit of the destination operand

The i-th bit of the result

The specified bit in the destination operand

Not affected

Modified according to the result of the instruction (see definition)

Always cleared to 0

Always set to 1

Undetermined (no guaranteed value)

Z flag before instruction execution

C flag before instruction execution

853

Table A-7 Condition Code Modification

Instruction H N Z V C Definition

ADD H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4

N = Rm

Z = Rm · Rm–1 · ...... · R0

V = Sm · Dm · Rm + Sm · Dm · Rm

C = Sm · Dm + Dm · Rm + Sm · Rm

ADDS —————

ADDX H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4

N = Rm

Z = Z' · Rm · ...... · R0

V = Sm · Dm · Rm + Sm · Dm · Rm

C = Sm · Dm + Dm · Rm + Sm · Rm

AND —0—N = Rm

Z = Rm · Rm–1 · ...... · R0

ANDC Stores the corresponding bits of the result.

No flags change when the operand is EXR.

BAND ———— C = C' · Dn

Bcc —————

BCLR —————

BIAND ———— C = C' · Dn

BILD ———— C = Dn

BIOR ———— C = C' + Dn

BIST —————

BIXOR ———— C = C' · Dn + C' · Dn

BLD ———— C = Dn

BNOT —————

BOR ———— C = C' + Dn

BSET —————

BSR —————

BST —————

BTST —— —— Z = Dn

BXOR ———— C = C' · Dn + C' · Dn

CLRMAC —————

854

Instruction H N Z V C Definition

CMP H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4

N = Rm

Z = Rm · Rm–1 · ...... · R0

V = Sm · Dm · Rm + Sm · Dm · Rm

C = Sm · Dm + Dm · Rm + Sm · Rm

DAA * * N = Rm

Z = Rm · Rm–1 · ...... · R0

C: decimal arithmetic carry

DAS * * N = Rm

Z = Rm · Rm–1 · ...... · R0

C: decimal arithmetic borrow

DEC — — N = Rm

Z = Rm · Rm–1 · ...... · R0

V = Dm · Rm

DIVXS ——— N = Sm · Dm + Sm · Dm

Z = Sm · Sm–1 · ...... · S0

DIVXU ——— N = Sm

Z = Sm · Sm–1 · ...... · S0

EEPMOV —————

EXTS —0—N = Rm

Z = Rm · Rm–1 · ...... · R0

EXTU —0 0 —Z = Rm · Rm–1 · ...... · R0

INC — — N = Rm

Z = Rm · Rm–1 · ...... · R0

V = Dm · Rm

JMP —————

JSR —————

LDC Stores the corresponding bits of the result.

No flags change when the operand is EXR.

LDM —————

LDMAC —————

MAC —————

855

Instruction H N Z V C Definition

MOV —0—N = Rm

Z = Rm · Rm–1 · ...... · R0

MOVFPE Can not be used in this LSI

MOVTPE

MULXS ——— N = R2m

Z = R2m · R2m–1 · ...... · R0

MULXU —————

NEG H = Dm–4 + Rm–4

N = Rm

Z = Rm · Rm–1 · ...... · R0

V = Dm · Rm

C = Dm + Rm

NOP —————

NOT —0—N = Rm

Z = Rm · Rm–1 · ...... · R0

OR —0—N = Rm

Z = Rm · Rm–1 · ...... · R0

ORC Stores the corresponding bits of the result.

No flags change when the operand is EXR.

POP —0—N = Rm

Z = Rm · Rm–1 · ...... · R0

PUSH —0—N = Rm

Z = Rm · Rm–1 · ...... · R0

ROTL —0 N = Rm

Z = Rm · Rm–1 · ...... · R0

C = Dm (1-bit shift) or C = Dm–1 (2-bit shift)

ROTR —0 N = Rm

Z = Rm · Rm–1 · ...... · R0

C = D0 (1-bit shift) or C = D1 (2-bit shift)

856

Instruction H N Z V C Definition

ROTXL —0 N = Rm

Z = Rm · Rm–1 · ...... · R0

C = Dm (1-bit shift) or C = Dm–1 (2-bit shift)

ROTXR —0 N = Rm

Z = Rm · Rm–1 · ...... · R0

C = D0 (1-bit shift) or C = D1 (2-bit shift)

RTE Stores the corresponding bits of the result.

RTS —————

SHAL —N = Rm

Z = Rm · Rm–1 · ...... · R0

V =Dm · Dm–1 + Dm · Dm–1 (1-bit shift)

V =Dm · Dm–1 · Dm–2 · Dm · Dm–1 · Dm–2 (2-bit shift)

C = Dm (1-bit shift) or C = Dm–1 (2-bit shift)

SHAR —0 N = Rm

Z = Rm · Rm–1 · ...... · R0

C = D0 (1-bit shift) or C = D1 (2-bit shift)

SHLL —0 N = Rm

Z = Rm · Rm–1 · ...... · R0

C = Dm (1-bit shift) or C = Dm–1 (2-bit shift)

SHLR —0 0 N = Rm

Z = Rm · Rm–1 · ...... · R0

C = D0 (1-bit shift) or C = D1 (2-bit shift)

SLEEP —————

STC —————

STM —————

STMAC — — N = 1 if MAC instruction resulted in negative value in MAC

Z = 1 if MAC instruction resulted in zero value in MAC

V = 1 if MAC instruction resulted in overflow

857

Instruction H N Z V C Definition

SUB H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4

N = Rm

Z = Rm · Rm–1 · ...... · R0

V = Sm · Dm · Rm + Sm · Dm · Rm

C = Sm · Dm + Dm · Rm + Sm · Rm

SUBS —————

SUBX H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4

N = Rm

Z = Z' · Rm · ...... · R0

V = Sm · Dm · Rm + Sm · Dm · Rm

C = Sm · Dm + Dm · Rm + Sm · Rm

TAS —0—N = Dm

Z = Dm · Dm–1 · ...... · D0

TRAPA —————

XOR —0—N = Rm

Z = Rm · Rm–1 · ...... · R0

XORC Stores the corresponding bits of the result.

No flags change when the operand is EXR.

858

Appendix B Internal I/O Register

B.1 Address

Address Register

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name Data Bus

Width

H'EBC0 to MRA SM1 SM0 DM1 DM0 MD1 MD0 DTS Sz DTC 8/16/32*

H'EFBF MRB CHNE DISEL ——————

SAR

DAR

CRA

CRB

H'F800 MCR MCR7 — MCR5 — — MCR2 MCR1 MCR0 HCAN 8/16

H'F801 GSR ————GSR3 GSR2 GSR1 GSR0

H'F802 BCR BCR7 BCR6 BCR5 BCR4 BCR3 BCR2 BCR1 BCR0

H'F803 BCR15 BCR14 BCR13 BCR12 BCR11 BCR10 BCR9 BCR8

H'F804 MBCR MBCR7 MBCR6 MBCR5 MBCR4 MBCR3 MBCR2 MBCR1 —

H'F805 MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 MBCR9 MBCR8

H'F806 TXPR TXPR7 TXPR6 TXPR5 TXPR4 TXPR3 TXPR2 TXPR1 —

H'F807 TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 TXPR9 TXPR8

H'F808 TXCR TXCR7 TXCR6 TXCR5 TXCR4 TXCR3 TXCR2 TXCR1 —

H'F809 TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 TXCR8

H'F80A TXACK TXACK7 TXACK6 TXACK5 TXACK4 TXACK3 TXACK2 TXACK1 —

H'F80B TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 TXACK8

H'F80C ABACK ABACK7 ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1 —

H'F80D ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 ABACK8

H'F80E RXPR RXPR7 RXPR6 RXPR5 RXPR4 RXPR3 RXPR2 RXPR1 RXPR0

H'F80F RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 RXPR8

H'F810 RFPR RFPR7 RFPR6 RFPR5 RFPR4 RFPR3 RFPR2 RFPR1 RFPR0

H'F811 RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 RFPR8

H'F812 IRR IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0

H'F813 — — — IRR12 — — IRR9 IRR8

859

Address Register

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name Data Bus

Width

H'F814 MBIMR MBIMR7 MBIMR6 MBIMR5 MBIMR4 MBIMR3 MBIMR2 MBIMR1 MBIMR0 HCAN 8/16

H'F815 MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 MBIMR8

H'F816 IMR IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 —

H'F817 — — — IMR12 — — IMR9 IMR8

H'F818 REC

H'F819 TEC

H'F81A UMSR UMSR7 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0

H'F81B UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 UMSR8

H'F81C LAFML LAFML7 LAFML6 LAFML5 LAFML4 LAFML3 LAFML2 LAFML1 LAFML0

H'F81D LAFML15 LAFML14 LAFML13 LAFML12 LAFML11 LAFML10 LAFML9 LAFML8

H'F81E LAFMH LAFMH7 LAFMH6 LAFMH5 — — — LAFMH1 LAFMH0

H'F81F LAFMH15 LAFMH14 LAFMH13 LAFMH12 LAFMH11 LAFMH10 LAFMH9 LAFMH8

H'F820 MC0[1] ————DLC3 DLC2 DLC1 DLC0

H'F821 MC0[2] ————————

H'F822 MC0[3] ————————

H'F823 MC0[4] ————————

H'F824 MC0[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16

H'F825 MC0[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3

H'F826 MC0[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0

H'F827 MC0[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8

H'F828 MC1[1] ————DLC3 DLC2 DLC1 DLC0

H'F829 MC1[2] ————————

H'F82A MC1[3] ————————

H'F82B MC1[4] ————————

H'F82C MC1[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16

H'F82D MC1[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3

H'F82E MC1[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0

H'F82F MC1[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8

H'F830 MC2[1] ————DLC3 DLC2 DLC1 DLC0

H'F831 MC2[2] ————————

H'F832 MC2[3] ————————

H'F833 MC2[4] ————————

H'F834 MC2[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16

H'F835 MC2[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3

H'F836 MC2[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0

H'F837 MC2[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8

860

Address Register

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name Data Bus

Width

H'F838 MC3[1] ————DLC3 DLC2 DLC1 DLC0 HCAN 8/16

H'F839 MC3[2] ————————

H'F83A MC3[3] ————————

H'F83B MC3[4] ————————

H'F83C MC3[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16

H'F83D MC3[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3

H'F83E MC3[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0

H'F83F MC3[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8

H'F840 MC4[1] ————DLC3 DLC2 DLC1 DLC0

H'F841 MC4[2] ————————

H'F842 MC4[3] ————————

H'F843 MC4[4] ————————

H'F844 MC4[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16

H'F845 MC4[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3

H'F846 MC4[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0

H'F847 MC4[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8

H'F848 MC5[1] ————DLC3 DLC2 DLC1 DLC0

H'F849 MC5[2] ————————

H'F84A MC5[3] ————————

H'F84B MC5[4] ————————

H'F84C MC5[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16

H'F84D MC5[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3

H'F84E MC5[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0

H'F84F MC5[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8

H'F850 MC6[1] ————DLC3 DLC2 DLC1 DLC0

H'F851 MC6[2] ————————

H'F852 MC6[3] ————————

H'F853 MC6[4] ————————

H'F854 MC6[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16

H'F855 MC6[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3

H'F856 MC6[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0

H'F857 MC6[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8

H'F858 MC7[1] ————DLC3 DLC2 DLC1 DLC0

H'F859 MC7[2] ————————

H'F85A MC7[3] ————————

H'F85B MC7[4] ————————

H'F85C MC7[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16

H'F85D MC7[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3

H'F85E MC7[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0

H'F85F MC7[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8

861

Address Register

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name Data Bus

Width

H'F860 MC8[1] ————DLC3 DLC2 DLC1 DLC0 HCAN 8/16

H'F861 MC8[2] ————————

H'F862 MC8[3] ————————

H'F863 MC8[4] ————————

H'F864 MC8[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16

H'F865 MC8[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3

H'F866 MC8[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0

H'F867 MC8[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8

H'F868 MC9[1] ————DLC3 DLC2 DLC1 DLC0

H'F869 MC9[2] ————————

H'F86A MC9[3] ————————

H'F86B MC9[4] ————————

H'F86C MC9[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16

H'F86D MC9[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3

H'F86E MC9[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0

H'F86F MC9[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8

H'F870 MC10[1] ————DLC3 DLC2 DLC1 DLC0

H'F871 MC10[2] ————————

H'F872 MC10[3] ————————

H'F873 MC10[4] ————————

H'F874 MC10[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16

H'F875 MC10[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3

H'F876 MC10[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0

H'F877 MC10[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8

H'F878 MC11[1] ————DLC3 DLC2 DLC1 DLC0

H'F879 MC11[2] ————————

H'F87A MC11[3] ————————

H'F87B MC11[4] ————————

H'F87C MC11[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16

H'F87D MC11[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3

H'F87E MC11[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0

H'F87F MC11[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8

H'F880 MC12[1] ————DLC3 DLC2 DLC1 DLC0

H'F881 MC12[2] ————————

H'F882 MC12[3] ————————

H'F883 MC12[4] ————————

H'F884 MC12[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16

H'F885 MC12[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3

H'F886 MC12[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0

H'F887 MC12[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8

862

Address Register

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name Data Bus

Width

H'F888 MC13[1] ————DLC3 DLC2 DLC1 DLC0 HCAN 8/16

H'F889 MC13[2] ————————

H'F88A MC13[3] ————————

H'F88B MC13[4] ————————

H'F88C MC13[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16

H'F88D MC13[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3

H'F88E MC13[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0

H'F88F MC13[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8

H'F890 MC14[1] ————DLC3 DLC2 DLC1 DLC0

H'F891 MC14[2] ————————

H'F892 MC14[3] ————————

H'F893 MC14[4] ————————

H'F894 MC14[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16

H'F895 MC14[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3

H'F896 MC14[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0

H'F897 MC14[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8

H'F898 MC15[1] ————DLC3 DLC2 DLC1 DLC0

H'F899 MC15[2] ————————

H'F89A MC15[3] ————————

H'F89B MC15[4] ————————

H'F89C MC15[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16

H'F89D MC15[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3

H'F89E MC15[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0

H'F89F MC15[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8

H'F8B0 MD0[1] MSG_DATA_1 (8 bits)

H'F8B1 MD0[2] MSG_DATA_2 (8 bits)

H'F8B2 MD0[3] MSG_DATA_3 (8 bits)

H'F8B3 MD0[4] MSG_DATA_4 (8 bits)

H'F8B4 MD0[5] MSG_DATA_5 (8 bits)

H'F8B5 MD0[6] MSG_DATA_6 (8 bits)

H'F8B6 MD0[7] MSG_DATA_7 (8 bits)

H'F8B7 MD0[8] MSG_DATA_8 (8 bits)

H'F8B8 MD1[1] MSG_DATA_1 (8 bits)

H'F8B9 MD1[2] MSG_DATA_2 (8 bits)

H'F8BA MD1[3] MSG_DATA_3 (8 bits)

H'F8BB MD1[4] MSG_DATA_4 (8 bits)

H'F8BC MD1[5] MSG_DATA_5 (8 bits)

H'F8BD MD1[6] MSG_DATA_6 (8 bits)

H'F8BE MD1[7] MSG_DATA_7 (8 bits)

H'F8BF MD1[8] MSG_DATA_8 (8 bits)

863

Address Register

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name Data Bus

Width

H'F8C0 MD2[1] MSG_DATA_1 (8 bits) HCAN 8/16

H'F8C1 MD2[2] MSG_DATA_2 (8 bits)

H'F8C2 MD2[3] MSG_DATA_3 (8 bits)

H'F8C3 MD2[4] MSG_DATA_4 (8 bits)

H'F8C4 MD2[5] MSG_DATA_5 (8 bits)

H'F8C5 MD2[6] MSG_DATA_6 (8 bits)

H'F8C6 MD2[7] MSG_DATA_7 (8 bits)

H'F8C7 MD2[8] MSG_DATA_8 (8 bits)

H'F8C8 MD3[1] MSG_DATA_1 (8 bits)

H'F8C9 MD3[2] MSG_DATA_2 (8 bits)

H'F8CA MD3[3] MSG_DATA_3 (8 bits)

H'F8CB MD3[4] MSG_DATA_4 (8 bits)

H'F8CC MD3[5] MSG_DATA_5 (8 bits)

H'F8CD MD3[6] MSG_DATA_6 (8 bits)

H'F8CE MD3[7] MSG_DATA_7 (8 bits)

H'F8CF MD3[8] MSG_DATA_8 (8 bits)

H'F8D0 MD4[1] MSG_DATA_1 (8 bits)

H'F8D1 MD4[2] MSG_DATA_2 (8 bits)

H'F8D2 MD4[3] MSG_DATA_3 (8 bits)

H'F8D3 MD4[4] MSG_DATA_4 (8 bits)

H'F8D4 MD4[5] MSG_DATA_5 (8 bits)

H'F8D5 MD4[6] MSG_DATA_6 (8 bits)

H'F8D6 MD4[7] MSG_DATA_7 (8 bits)

H'F8D7 MD4[8] MSG_DATA_8 (8 bits)

H'F8D8 MD5[1] MSG_DATA_1 (8 bits)

H'F8D9 MD5[2] MSG_DATA_2 (8 bits)

H'F8DA MD5[3] MSG_DATA_3 (8 bits)

H'F8DB MD5[4] MSG_DATA_4 (8 bits)

H'F8DC MD5[5] MSG_DATA_5 (8 bits)

H'F8DD MD5[6] MSG_DATA_6 (8 bits)

H'F8DE MD5[7] MSG_DATA_7 (8 bits)

H'F8DF MD5[8] MSG_DATA_8 (8 bits)

H'F8E0 MD6[1] MSG_DATA_1 (8 bits)

H'F8E1 MD6[2] MSG_DATA_2 (8 bits)

H'F8E2 MD6[3] MSG_DATA_3 (8 bits)

H'F8E3 MD6[4] MSG_DATA_4 (8 bits)

H'F8E4 MD6[5] MSG_DATA_5 (8 bits)

H'F8E5 MD6[6] MSG_DATA_6 (8 bits)

H'F8E6 MD6[7] MSG_DATA_7 (8 bits)

H'F8E7 MD6[8] MSG_DATA_8 (8 bits)

864

Address Register

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name Data Bus

Width

H'F8E8 MD7[1] MSG_DATA_1 (8 bits) HCAN 8/16

H'F8E9 MD7[2] MSG_DATA_2 (8 bits)

H'F8EA MD7[3] MSG_DATA_3 (8 bits)

H'F8EB MD7[4] MSG_DATA_4 (8 bits)

H'F8EC MD7[5] MSG_DATA_5 (8 bits)

H'F8ED MD7[6] MSG_DATA_6 (8 bits)

H'F8EE MD7[7] MSG_DATA_7 (8 bits)

H'F8EF MD7[8] MSG_DATA_8 (8 bits)

H'F8F0 MD8[1] MSG_DATA_1 (8 bits)

H'F8F1 MD8[2] MSG_DATA_2 (8 bits)

H'F8F2 MD8[3] MSG_DATA_3 (8 bits)

H'F8F3 MD8[4] MSG_DATA_4 (8 bits)

H'F8F4 MD8[5] MSG_DATA_5 (8 bits)

H'F8F5 MD8[6] MSG_DATA_6 (8 bits)

H'F8F6 MD8[7] MSG_DATA_7 (8 bits)

H'F8F7 MD8[8] MSG_DATA_8 (8 bits)

H'F8F8 MD9[1] MSG_DATA_1 (8 bits)

H'F8F9 MD9[2] MSG_DATA_2 (8 bits)

H'F8FA MD9[3] MSG_DATA_3 (8 bits)

H'F8FB MD9[4] MSG_DATA_4 (8 bits)

H'F8FC MD9[5] MSG_DATA_5 (8 bits)

H'F8FD MD9[6] MSG_DATA_6 (8 bits)

H'F8FE MD9[7] MSG_DATA_7 (8 bits)

H'F8FF MD9[8] MSG_DATA_8 (8 bits)

H'F900 MD10[1] MSG_DATA_1 (8 bits)

H'F901 MD10[2] MSG_DATA_2 (8 bits)

H'F902 MD10[3] MSG_DATA_3 (8 bits)

H'F903 MD10[4] MSG_DATA_4 (8 bits)

H'F904 MD10[5] MSG_DATA_5 (8 bits)

H'F905 MD10[6] MSG_DATA_6 (8 bits)

H'F906 MD10[7] MSG_DATA_7 (8 bits)

H'F907 MD10[8] MSG_DATA_8 (8 bits)

H'F908 MD11[1] MSG_DATA_1 (8 bits)

H'F909 MD11[2] MSG_DATA_2 (8 bits)

H'F90A MD11[3] MSG_DATA_3 (8 bits)

H'F90B MD11[4] MSG_DATA_4 (8 bits)

H'F90C MD11[5] MSG_DATA_5 (8 bits)

H'F90D MD11[6] MSG_DATA_6 (8 bits)

H'F90E MD11[7] MSG_DATA_7 (8 bits)

H'F90F MD11[8] MSG_DATA_8 (8 bits)

865

Address Register

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name Data Bus

Width

H'F910 MD12[1] MSG_DATA_1 (8 bits) HCAN 8/16

H'F911 MD12[2] MSG_DATA_2 (8 bits)

H'F912 MD12[3] MSG_DATA_3 (8 bits)

H'F913 MD12[4] MSG_DATA_4 (8 bits)

H'F914 MD12[5] MSG_DATA_5 (8 bits)

H'F915 MD12[6] MSG_DATA_6 (8 bits)

H'F916 MD12[7] MSG_DATA_7 (8 bits)

H'F917 MD12[8] MSG_DATA_8 (8 bits)

H'F918 MD13[1] MSG_DATA_1 (8 bits)

H'F919 MD13[2] MSG_DATA_2 (8 bits)

H'F91A MD13[3] MSG_DATA_3 (8 bits)

H'F91B MD13[4] MSG_DATA_4 (8 bits)

H'F91C MD13[5] MSG_DATA_5 (8 bits)

H'F91D MD13[6] MSG_DATA_6 (8 bits)

H'F91E MD13[7] MSG_DATA_7 (8 bits)

H'F91F MD13[8] MSG_DATA_8 (8 bits)

H'F920 MD14[1] MSG_DATA_1 (8 bits)

H'F921 MD14[2] MSG_DATA_2 (8 bits)

H'F922 MD14[3] MSG_DATA_3 (8 bits)

H'F923 MD14[4] MSG_DATA_4 (8 bits)

H'F924 MD14[5] MSG_DATA_5 (8 bits)

H'F925 MD14[6] MSG_DATA_6 (8 bits)

H'F926 MD14[7] MSG_DATA_7 (8 bits)

H'F927 MD14[8] MSG_DATA_8 (8 bits)

H'F928 MD15[1] MSG_DATA_1 (8 bits)

H'F929 MD15[2] MSG_DATA_2 (8 bits)

H'F92A MD15[3] MSG_DATA_3 (8 bits)

H'F92B MD15[4] MSG_DATA_4 (8 bits)

H'F92C MD15[5] MSG_DATA_5 (8 bits)

H'F92D MD15[6] MSG_DATA_6 (8 bits)

H'F92E MD15[7] MSG_DATA_7 (8 bits)

H'F92F MD15[8] MSG_DATA_8 (8 bits)

866

Address Register

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name Data Bus

Width

H'FC00 PWCR1 — — IE CMF CST CKS2 CKS1 CKS0 Motor

control 8

H'FC02 PWOCR1 OE1H OE1G OE1F OE1E OE1D OE1C OE1B OE1A PWM timer

H'FC04 PWPR1 OPS1H OPS1G OPS1F OPS1E OPS1D OPS1C OPS1B OPS1A

H'FC06 PWCYR1 —————— 16

H'FC08 PWBFR1A — — — OTS — — DT9 DT8

DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0

H'FC0A PWBFR1C — — — OTS — — DT9 DT8

DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0

H'FC0C PWBFR1E — — — OTS — — DT9 DT8

DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0

H'FC0E PWBFR1G — — — OTS — — DT9 DT8

DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0

H'FC10 PWCR2 — — IE CMF CST CKS2 CKS1 CKS0 Motor

control 8

H'FC12 PWOCR2 OE2H OE2G OE2F OE2E OE2D OE2C OE2B OE2A PWM timer

H'FC14 PWPR2 OPS2H OPS2G OPS2F OPS2E OPS2D OPS2C OPS2B OPS2A

H'FC16 PWCYR2 —————— 16

H'FC18 PWBFR2A — — — TDS — — DT9 DT8

DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0

H'FC1A PWBFR2B — — — TDS — — DT9 DT8

DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0

H'FC1C PWBFR2C — — — TDS — — DT9 DT8

DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0

H'FC1E PWBFR2D — — — TDS — — DT9 DT8

DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0

H'FC20 PHDDR PH7DDR PH6DDR PH5DDR PH4DDR PH3DDR PH2DDR PH1DDR PH0DDR PORT 8

H'FC21 PJDDR PJ7DDR PJ6DDR PJ5DDR PJ4DDR PJ3DDR PJ2DDR PJ1DDR PJ0DDR

H'FC22 PKDDR PK7DDR PK6DDR ——————

H'FC24 PHDR PH7DR PH6DR PH5DR PH4DR PH3DR PH2DR PH1DR PH0DR

H'FC25 PJDR PJ7DR PJ6DR PJ5DR PJ4DR PJ3DR PJ2DR PJ1DR PJ0DR

H'FC26 PKDR PK7DR PK6DR ——————

H'FC28 PORTH PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0

H'FC29 PORTJ PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0

867

Address Register

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name Data Bus

Width

H'FC2A PORTK PK7 PK6 ——————PORT 8

H'FC30 LPCR DTS1 DTS0 CMX — SGS3 SGS2 SGS1 SGS0 LCDC 8

H'FC31 LCR — PSW ACT DISP CKS3 CKS2 CKS1 CKS0

H'FC32 LCR2 LCDAB ———————

H'FC40 to

H’FC53 LCDRAM

H'FC60 MSTPCRD MSTPD7 MSTPD6 ——————SYSTEM 8

H'FC62 Reserved

H'FC64 Reserved

H'FDD8 Reserved

H'FDD9 Reserved

H'FDDA Reserved

H'FDDB Reserved

H'FDDC Reserved

H'FDDD Reserved

H'FDDE Reserved

H'FDE4 SBYCR SSBY STS2 STS1 STS0 OPE — — — SYSTEM 8

H'FDE5 SYSCR MACS — INTM1 INTM0 NMIEG — — RAME

H'FDE6 SCKCR PSTOP — — — STCS SCK2 SCK1 SCK0

H'FDE7 MDCR —————MDS2 MDS1 MDS0

H'FDE8 MSTPCRA MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0

H'FDE9 MSTPCRB MSTPB7 MSTPB6 — MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0

H'FDEA MSTPCRC MSTPC7 — MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0

H'FDEB PFCR ————AE3AE2AE1AE0

H'FDEC LPWRCR DTON LSON NESEL SUBSTP RFCUT — STC1 STC0

H'FE00 BARA ————————PBC32

H'FE01 BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16

H'FE02 BAA15 BAA14 BAA13 BAA12 BAA11 BAA10 BAA9 BAA8

H'FE03 BAA7 BAA6 BAA5 BAA4 BAA3 BAA2 BAA1 BAA0

H'FE04 BARB ————————

H'FE05 BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16

H'FE06 BAA15 BAA14 BAA13 BAA12 BAA11 BAA10 BAA9 BAA8

H'FE07 BAA7 BAA6 BAA5 BAA4 BAA3 BAA2 BAA1 BAA0

H'FE08 BCRA CMFA CDA BAMRA2 BAMRA1 BAMRA0 CSELA1 CSELA0 BIEA 8

H'FE09 BCRB CMFB CDB BAMRB2 BAMRB1 BAMRB0 CSELB1 CSELB0 BIEB

H'FE12 ISCRH ————IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA INT 8

H'FE13 ISCRL IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA

H'FE14 IER — — IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E

H'FE15 ISR — — IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F

868

Address Register

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name Data Bus

Width

H'FE16 DTCERA DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 DTC 8

H'FE17 DTCERB DTCEB7 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0

H'FE18 DTCERC DTCEC7 DTCEC6 DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCEC1 DTCEC0

H'FE19 DTCERD DTCED7 DTCED6 DTCED5 DTCED4 DTCED3 DTCED2 DTCED1 DTCED0

H'FE1A DTCERE DTCEE7 DTCEE6 DTCEE5 DTCEE4 DTCEE3 DTCEE2 DTCEE1 DTCEE0

H'FE1B DTCERF DTCEF7 DTCEF6 DTCEF5 DTCEF4 DTCEF3 DTCEF2 DTCEF1 DTCEF0

H'FE1C DTCERG DTCEG7 DTCEG6 DTCEG5 DTCEG4 DTCEG3 DTCEG2 DTCEG1 DTCEG0

H'FE1E DTCERI DTCEI7 DTCEI6 DTCEI5 DTCEI4 DTCEI3 DTCEI2 DTCEI1 DTCEI0

H'FE1F DTVECR SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0

H'FE26 PCR G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 PPG 8

H'FE27 PMR G3INV G2INV G1INV G0INV G3NOV G2NOV G1NOV G0NOV

H'FE28 NDERH NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8

H'FE29 NDERL NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0

H'FE2A PODRH POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8

H'FE2B PODRL POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0

H'FE2C NDRH NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8

H'FE2D NDRL NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0

H'FE2E NDRH ————NDR11 NDR10 NDR9 NDR8

H'FE2F NDRL ————NDR3 NDR2 NDR1 NDR0

H'FE30 P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR PORT 8

H'FE30 P2DDR P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR

H'FE32 P3DDR P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR

H'FE34 P5DDR —————P52DDR P51DDR P50DDR

H'FE39 PADDR PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR

H'FE3A PBDDR PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR

H'FE3B PCDDR PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR

H'FE3C PDDDR PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR

H'FE3D PEDDR PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR

H'FE3E PFDDR PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR — PF0DDR

H'FE40 PAPCR PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR

H'FE41 PBPCR PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR

H'FE42 PCPCR PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR

H'FE43 PDPCR PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR

H'FE44 PEPCR PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR

H'FE46 P3ODR P37ODR P36ODR P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR

H'FE47 PAODR PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR

H'FE48 PBODR PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR

H'FE49 PCODR PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR

869

Address Register

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name Data Bus

Width

H'FE80 TCR3 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU3 8/16

H'FE81 TMDR3 — — BFB BFA MD3 MD2 MD1 MD0

H'FE82 TIOR3H IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0

H'FE83 TIOR3L IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0

H'FE84 TIER3 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA

H'FE85 TSR3 — — — TCFV TGFD TGFC TGFB TGFA

H'FE86 TCNT3

H'FE87

H'FE88 TGR3A

H'FE89

H'FE8A TGR3B

H'FE8B

H'FE8C TGR3C

H'FE8D

H'FE8E TGR3D

H'FE8F

H'FE90 TCR4 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU4 8/16

H'FE91 TMDR4 ————MD3MD2MD1MD0

H'FE92 TIOR4 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0

H'FE94 TIER4 TTGE — TCIEU TCIEV — — TGIEB TGIEA

H'FE95 TSR4 TCFD — TCFU TCFV — — TGFB TGFA

H'FE96 TCNT4

H'FE97

H'FE98 TGR4A

H'FE99

H'FE9A TGR4B

H'FE9B

H'FEA0 TCR5 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU5 8/16

H'FEA1 TMDR5 ————MD3MD2MD1MD0

H'FEA2 TIOR5 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0

H'FEA4 TIER5 TTGE — TCIEU TCIEV — — TGIEB TGIEA

H'FEA5 TSR5 TCFD — TCFU TCFV — — TGFB TGFA

H'FEA6 TCNT5

H'FEA7

H'FEA8 TGR5A

H'FEA9

H'FEAA TGR5B

H'FEAB

H'FEB0 TSTR — — CST5 CST4 CST3 CST2 CST1 CST0 TPU All 8

H'FEB1 TSYR — — SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0

870

Address Register

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name Data Bus

Width

H'FEC0 IPRA — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 INT 8

H'FEC1 IPRB — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 (*:

H8S/2648,

H'FEC2 IPRC —————IPR2 IPR1 IPR0 H8S/2648R,

H8S/2647)

H'FEC3 IPRD — IPR6 IPR5 IPR4 ————

H'FEC4 IPRE — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0

H'FEC5 IPRF — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0

H'FEC6 IPRG — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0

H'FEC7 IPRH — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0

H'FEC9 IPRJ —————IPR2 IPR1 IPR0

H'FECA IPRK — IPR6 IPR5 IPR4 — IPR2*IPR1*IPR0*

H'FECC IPRM — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0

H'FECE reserved

H'FED0 ABWCR ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Bus

controller 8

H'FED1 ASTCR AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0

H'FED2 WCRH W71 W70 W61 W60 W51 W50 W41 W40

H'FED3 WCRL W31 W30 W21 W20 W11 W10 W01 W00

H'FED4 BCRH ICIS1 ICIS0 BRSTRM BRSTS1 BRSTS0 — — —

H'FED5 BCRL ——————WDBE WAITE

H'FEDB RAMER ————RAMS RAM2 RAM1 RAM0 ROM 8

H'FF00 P1DR P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR PORT 8

H'FF01 P2DR P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR

H'FF02 P3DR P37DR P36DR P35DR P34DR P33DR P32DR P31DR P30DR

H'FF04 P5DR —————P52DR P51DR P50DR

H'FF09 PADR PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR

H'FF0A PBDR PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR

H'FF0B PCDR PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR

H'FF0C PDDR PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR

H'FF0D PEDR PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR

H'FF0E PFDR PF7DR PF6DR PF5DR PF4DR PF3DR PF2DR — PF0DR

871

Address Register

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name Data Bus

Width

H'FF10 TCR0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU0 8/16

H'FF11 TMDR0 — — BFB BFA MD3 MD2 MD1 MD0

H'FF12 TIOR0H IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0

H'FF13 TIOR0L IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0

H'FF14 TIER0 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA

H'FF15 TSR0 — — — TCFV TGFD TGFC TGFB TGFA

H'FF16 TCNT0

H'FF17

H'FF18 TGR0A

H'FF19

H'FF1A TGR0B

H'FF1B

H'FF1C TGR0C

H'FF1D

H'FF1E TGR0D

H'FF1F

H'FF20 TCR1 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU1 8/16

H'FF21 TMDR1 ————MD3MD2MD1MD0

H'FF22 TIOR1 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0

H'FF24 TIER1 TTGE — TCIEU TCIEV — — TGIEB TGIEA

H'FF25 TSR1 TCFD — TCFU TCFV — — TGFB TGFA

H'FF26 TNCT1

H'FF27

H'FF28 TGR1A

H'FF29

H'FF2A TGR1B

H'FF2B

H'FF30 TCR2 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU2 8/16

H'FF31 TMDR2 ————MD3MD2MD1MD0

H'FF32 TIOR2 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0

H'FF34 TIER2 TTGE — TCIEU TCIEV — — TGIEB TGIEA

H'FF35 TSR2 TCFD — TCFU TCFV — — TGFB TGFA

H'FF36 TCNT2

H'FF37

H'FF38 TGR2A

H'FF39

H'FF3A TGR2B

H'FF3B

872

Address Register

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name Data Bus

Width

H'FF74

(read/write) TCSR0 OVF WT/IT TME — — CKS2 CKS1 CKS0 WDT 8

H'FF75

(read) TCNT0

H'FF76 — ————————

H'FF77 RSTCSR0 WOVF RSTE ——————

H'FF78 SMR0 C/ACHR PE O/ESTOP MP CKS1 CKS0 SCI0/

smart card

interface 0

SMR0 GM BLK PE O/EBCP1 BCP0 CKS1 CKS0

H'FF79 BRR0

H'FF7A SCR0 TIE RIE TE RE MPIE TEIE CKE1 CKE0

H'FF7B TDR0

H'FF7C SSR0 TDRE RDRF ORER FER PER TEND MPB MPBT

SSR0 TDRE RDRF ORER ERS PER TEND MPB MPBT

H'FF7D RDR0

H'FF7E SCMR0 ————SDIR SINV — SMIF

H'FF80 SMR1 C/ACHR PE O/ESTOP MP CKS1 CKS0 SCI1/

smart card

interface 1

SMR1 GM BLK PE O/EBCP1 BCP0 CKS1 CKS0

H'FF81 BRR1

H'FF82 SCR1 TIE RIE TE RE MPIE TEIE CKE1 CKE0

H'FF83 TDR1

H'FF84 SSR1 TDRE RDRF ORER FER PER TEND MPB MPBT

SSR1 TDRE RDRF ORER ERS PER TEND MPB MPBT

H'FF85 RDR1

H'FF86 SCMR1 ————SDIR SINV — SMIF

873

Address Register

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name Data Bus

Width

H'FF88 SMR2 C/ACHR PE O/ESTOP MP CKS1 CKS0 SCI2/ smart

card interface

H'FF88 SMR2 GM BLK PE O/EBCP1 BCP0 CKS1 CKS0 2

(H8S/2648,

H'FF89 BRR2 H8S/2648R,

H8S/2647)

H'FF8A SCR2 TIE RIE TE RE MPIE TEIE CKE1 CKE0

H'FF8B TDR2

H'FF8C SSR2 TDRE RDRF ORER FER PER TEND MPB MPBT

H'FF8C SSR2 TDRE RDRF ORER ERS PER TEND MPB MPBT

H'FF8D SDR2

H'FF8E SCMR2 ————SDIR SINV — SMIF

H'FF90 ADDRAH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 A/D 8

H'FF91 ADDRAL AD1 AD0 ——————

H'FF92 ADDRBH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2

H'FF93 ADDRBL AD1 AD0 ——————

H'FF94 ADDRCH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2

H'FF95 ADDRCL AD1 AD0 ——————

H'FF96 ADDRDH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2

H'FF97 ADDRDL AD1 AD0 ——————

H'FF98 ADCSR ADF ADIE ADST SCAN CH3 CH2 CH1 CH0

H'FF99 ADCR TRGS1 TRGS0 — — CKS1 CKS0 — —

H'FFA2

(read/write) TCSR1 OVF WT/IT TME PSS RST/NMI CKS2 CKS1 CKS0 WDT1 8

H'FFA3

(read) TCNT1

H'FFA8 FLMCR1 FWE SWE ESU PSU EV PV E P ROM 8

H'FFA9 FLMCR2 FLER ———————

H'FFAA EBR1 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0

H'FFAB EBR2 ——————EB9EB8

H'FFAC FLPWCR PDWND ———————

H'FFB0 PORT1 P17 P16 P15 P14 P13 P12 P11 P10 PORT 8

H'FFB1 PORT2 P27 P26 P25 P24 P23 P22 P21 P20

H'FFB2 PORT3 P37 P36 P35 P34 P33 P32 P31 P30

H'FFB3 PORT4 P47 P46 P45 P44 P43 P42 P41 P40

H'FFB4 PORT5 —————P52P51P50

H'FFB8 PORT9 P97 P96 P95 P94 P93 P92 P91 P90

H'FFB9 PORTA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

H'FFBA PORTB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

H'FFBB PORTC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

H'FFBC PORTD PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

H'FFBD PORTE PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0

H'FFBE PORTF PF7 PF6 PF5 PF4 PF3 PF2 — PF0

Note: *These registers are in the on-chip RAM area. When the DTC is accessed as register

information, the data-bus width becomes 32 bits and is otherwise 8 or 16 bits.

874

B.2 Functions

DACR—D/A Control Register H'FFFA D/A Converter

name Address to which the

on-chip

supporting

module

acronym

Bit

numbers

Initial bit

values Names of the

bits. Dashes

(—) indicate

reserved bits.

Full name

of bit

Descriptions

of bit settings

Read only

Write only

Read and write

R/W

Possible types of access

Bit

Initial value

Read/Write

DAOE1

R/W

DAOE0

R/W

DAE

R/W

—

D/A Enabled

DAOE1

Conversion resultDAE

DAOE0

Channel 0 and 1 D/A conversion disabled

Channel 0 D/A conversion enabled

Channel 1 D/A conversion disabled

Channel 0 and 1 D/A conversion enabled

Channel 0 D/A conversion disabled

Channel 1 D/A conversion enabled

Channel 0 and 1 D/A conversion enabled

D/A Output Enable 0

0 Analog output DA0 disabled

1 Channel 0 D/A conversion enabled.

Analog output DA0 enabled

D/A Output Enable 1

0 Analog output DA1 disabled

1 Channel 1 D/A conversion enabled.

Analog output DA1 enabled

875

MRA—DTC Mode Register A H'EBC0–H'EFBF DTC

SM1

Undefined

—

SM0

Undefined

—

DM1

Undefined

—

DM0

Undefined

—

MD1

Undefined

—

Undefined

—

MD0

Undefined

—

DTS

Undefined

—

Bit

Initial value

Read/Write

DTC Data Transfer Size

0 Byte-size transfer

1 Word-size transfer

DTC Transfer Mode Select

0 Destination side is repeat

area or block area

1 Source side is repeat area

or block area

DTC Mode

0 Normal mode

Repeat mode

1 Block transfer mode0 —1

Destination Address Mode

0 DAR is fixed

DAR is incremented after a transfer

(by +1 when Sz = 0; by +2 when Sz = 1)

—

DAR is decremented after a transfer

(by -1 when Sz = 0; by -2 when Sz = 1)

Source Address Mode

0 SAR is fixed

SAR is incremented after a transfer

(by +1 when Sz = 0; by +2 when Sz = 1)

—

SAR is decremented after a transfer

(by -1 when Sz = 0; by -2 when Sz = 1)

876

MRB—DTC Mode Register B H'EBC0–H'EFBF DTC

CHNE

Undefined

—

DISEL

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Bit

Initial value

Read/Write

DTC Interrupt Select

0 After a data transfer ends, the CPU interrupt is

disabled unless the transfer counter is 0

1 After a data transfer ends, the CPU interrupt is

enabled

DTC Chain Transfer Enable

0 End of DTC data transfer

1 DTC chain transfer

SAR—DTC Source Address Register H'EBC0–H'EFBF DTC

Unde-

fined

—

Bit

Initial value

Read/Write

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

- - -

Specify DTC transfer data source address

DAR—DTC Destination Address Register H'EBC0–H'EFBF DTC

Unde-

fined

—

Bit

Initial value

Read/Write

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

- - -

Specify DTC transfer data destination address

877

CRA—DTC Transfer Count Register A H'EBC0–H'EFBF DTC

Unde-

fined

—

Bit

Initial value

Read/Write

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

CRAH CRAL

Specify the number of DTC data transfers

CRB—DTC Transfer Count Register B H'EBC0–H'EFBF DTC

Unde-

fined

—

Bit

Initial value

Read/Write

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Specify the number of DTC block data transfers

878

MCR—Master Control Register H'F800 HCAN

HCAN Sleep Mode

0HCAN sleep mode released

1 Transition to HCAN sleep mode enabled

Message T ransmission Method

0Transmission order determined by message

identifier priority

Transmission order determined by mailbox

(buffer) number priority

(TXPR1 > TXPR15)

Halt Request

HCAN normal operating mode

HCAN halt mode transition request

HCAN Sleep Mode Release

0HCAN sleep mode release by CAN bus operation disabled

1 HCAN sleep mode release by CAN bus operation enabled

MCR7

R/W

—

MCR5

R/W

—

MCR0

R/W

MCR2

R/W

MCR1

R/W

Bit

Initial value

Read/Write

Reset Request

0Normal operating mode

(MCR0 = 0 and GSR3 = 0)

[Setting condition]

When 0 is written after an

HCAN reset

1HCAN reset mode transition

request

879

GSR—General Status Register H'F801 HCAN

—

GSR3

GSR0

GSR2

GSR1

Bit

Initial value

Read/Write

Transmit/Receive Warning Flag

0 [Reset condition]

When TEC < 96 and REC < 96 or TEC ≥ 256

1 When TEC ≥ 96 or REC ≥ 96

Bus Off Flag

0 [Reset condition]

Recovery from bus off state

1 When TEC ≥ 256 (bus off state)

Reset Status Bit

0 Normal operating state

[Setting condition]

After an HCAN internal reset

1 Configuration mode

[Reset condition]

MCR0 reset mode and sleep mode

Message Transmission Status Flag

0 Message transmission period

1 [Reset condition]

Idle period

880

BCR—Bit Configuration Register H'F802 HCAN

BCR7

R/W

BCR6

R/W

BCR5

R/W

BCR4

R/W

BCR3

R/W

BCR0

R/W

BCR2

R/W

BCR1

R/W

Bit

Initial value

Read/Write

Resynchronization Jump Width

0 Bit synchronization width = 1 time quantum

Bit synchronization width = 2 time quanta

1 Bit synchronization width = 3 time quanta0 Bit synchronization width = 4 time quanta1

Baud Rate Prescale

02 × system clock

4 × system clock

06 × system clock0

128 × system clock11

BCR15

R/W

BCR14

R/W

BCR13

R/W

BCR12

R/W

BCR11

R/W

BCR8

R/W

BCR10

R/W

BCR9

R/W

Bit

Initial value

Read/Write

Time Segment 2

0 Setting prohibited

TSEG2 = 2 time quanta

1TSEG2 = 3 time quanta0 TSEG2 = 4 time quanta1

1 TSEG2 = 5 time quanta

TSEG2 = 6 time quanta

1TSEG2 = 7 time quanta0 TSEG2 = 8 time quanta1

Time Segment 1

0 Setting prohibited

Setting prohibited

0 Setting prohibited

TSEG1 = 4 time quanta

TSEG1 = 5 time quanta

TSEG1 = 16 time quanta

011

Bit Sample Point

0 Bit sampling at one point (end of time segment 1)

1 Bit sampling at three points (end of time segment 1 and preceding and following time quantum)

881

MBCR—Mailbox Configuration Register H'F804 HCAN

MBCR7

R/W

MBCR6

R/W

MBCR5

R/W

MBCR4

R/W

MBCR3

R/W

—

MBCR2

R/W

MBCR1

R/W

MBCR15

R/W

MBCR14

R/W

MBCR13

R/W

MBCR12

R/W

MBCR11

R/W

MBCR8

R/W

MBCR10

R/W

MBCR9

R/W

Bit

Initial value

Read/Write

Bit

Initial value

Read/Write

Mailbox Setting Register

0 Corresponding mailbox is set for transmission

1 Corresponding mailbox is set for reception

TXPR—Transmit Wait Register H'F806 HCAN

TXPR7

R/W

TXPR6

R/W

TXPR5

R/W

TXPR4

R/W

TXPR3

R/W

—

TXPR2

R/W

TXPR1

R/W

TXPR15

R/W

TXPR14

R/W

TXPR13

R/W

TXPR12

R/W

TXPR11

R/W

TXPR8

R/W

TXPR10

R/W

TXPR9

R/W

Bit

Initial value

Read/Write

Bit

Initial value

Read/Write

Transmit Wait Register

0 Transmit message idle state in corresponding mailbox

[Clearing condition]

Message transmission completion and cancellation completion

1 Transmit message transmit wait in corresponding mailbox

(CAN bus arbitration)

882

TXCR—Transmit Wait Cancel Register H'F808 HCAN

TXCR7

R/W

TXCR6

R/W

TXCR5

R/W

TXCR4

R/W

TXCR3

R/W

—

TXCR2

R/W

TXCR1

R/W

TXCR15

R/W

TXCR14

R/W

TXCR13

R/W

TXCR12

R/W

TXCR11

R/W

TXCR8

R/W

TXCR10

R/W

TXCR9

R/W

Bit

Initial value

Read/Write

Bit

Initial value

Read/Write

Transmit Wait Cancel Register

0 Transmit message cancellation idle state in corresponding mailbox

[Clearing condition]

Completion of TXPR clearing

(when transmit message is canceled normally)

1 TXPR cleared for corresponding mailbox

(transmit message cancellation)

TXACK—Transmit Acknowledge Register H'F80A HCAN

TXACK7

R/(W)*

TXACK6

R/(W)*

TXACK5

R/(W)*

TXACK4

R/(W)*

TXACK3

R/(W)*

—

TXACK2

R/(W)*

TXACK1

R/(W)*

TXACK15

R/(W)*

TXACK14

R/(W)*

TXACK13

R/(W)*

TXACK12

R/(W)*

TXACK11

R/(W)*

TXACK8

R/(W)*

TXACK10

R/(W)*

TXACK9

R/(W)*

Bit

Initial value

Read/Write

Bit

Initial value

Read/Write

Note: * Only 1 can be written, to clear the flag.

Transmit Acknowledge Register

0 [Clearing condition]

Writing 1

1 Completion of message transmission for

corresponding mailbox

883

ABACK—Abort Acknowledge Register H'F80C HCAN

ABACK7

R/(W)*

ABACK6

R/(W)*

ABACK5

R/(W)*

ABACK4

R/(W)*

ABACK3

R/(W)*

—

ABACK2

R/(W)*

ABACK1

R/(W)*

ABACK15

R/(W)*

ABACK14

R/(W)*

ABACK13

R/(W)*

ABACK12

R/(W)*

ABACK11

R/(W)*

ABACK8

R/(W)*

ABACK10

R/(W)*

ABACK9

R/(W)*

Bit

Initial value

Read/Write

Bit

Initial value

Read/Write

Abort Acknowledge Register

0 [Clearing condition]

Writing 1

1 Completion of transmit message cancellation

for corresponding mailbox

Note: * Only 1 can be written, to clear the flag.

RXPR—Receive Complete Register H'F80E HCAN

RXPR7

R/(W)*

RXPR6

R/(W)*

RXPR5

R/(W)*

RXPR4

R/(W)*

RXPR3

R/(W)*

RXPR0

R/(W)*

RXPR2

R/(W)*

RXPR1

R/(W)*

RXPR15

R/(W)*

RXPR14

R/(W)*

RXPR13

R/(W)*

RXPR12

R/(W)*

RXPR11

R/(W)*

RXPR8

R/(W)*

RXPR10

R/(W)*

RXPR9

R/(W)*

Bit

Initial value

Read/Write

Bit

Initial value

Read/Write

Receive Complete Register

0 [Clearing condition]

Writing 1

1 Completion of message (data frame or remote

frame) reception in corresponding mailbox

Note: * Only 1 can be written, to clear the flag.

884

RFPR—Remote Request Register H'F810 HCAN

RFPR7

R/(W)*

RFPR6

R/(W)*

RFPR5

R/(W)*

RFPR4

R/(W)*

RFPR3

R/(W)*

RFPR0

R/(W)*

RFPR2

R/(W)*

RFPR1

R/(W)*

RFPR15

R/(W)*

RFPR14

R/(W)*

RFPR13

R/(W)*

RFPR12

R/(W)*

RFPR11

R/(W)*

RFPR8

R/(W)*

RFPR10

R/(W)*

RFPR9

R/(W)*

Bit

Initial value

Read/Write

Bit

Initial value

Read/Write

Remote Request Register

0 [Clearing condition]

Writing 1

1 Completion of remote frame reception in

corresponding mailbox

Note: * Only 1 can be written, to clear the flag.

885

IRR—Interrupt Register H'F812 HCAN

IRR7

R/(W)*

IRR6

R/(W)*

IRR5

R/(W)*

IRR4

R/(W)*

IRR3

R/(W)*

IRR0

R/(W)*

IRR2

R/(W)*

IRR1

R/(W)*

Bit

Initial value

Read/Write

Reset Interrupt Flag

0[Clearing condition]

Writing 1

1 Transition to hardware reset (HCAN module stop, software

standby)

[Setting condition]

When reset processing is completed after hardware reset

transition (HCAN module stop, software standby)

Receive Message Interrupt Flag

0[Clearing condition]

Clearing of all bits in RXPR (receive complete register) in the mailbox,

which enables the receive interrupt requests in MBIMR

1 Data frame or remote frame received and stored in mailbox

[Setting conditions]

When data frame or remote frame reception is completed, when

corresponding MBIMR = 0

Remote Frame Request Interrupt Flag

0[Clearing condition]

Clearing of all bits in RFPR (remote request wait register) in the mailbox,

which enables the receive interrupt requests in MBIMR

1 Remote frame received and stored in mailbox

[Setting conditions]

When remote frame reception is completed, when corresponding MBIMR = 0

0[Clearing condition]

Writing 1

1 Error warning state caused by transmit error

[Setting condition]

When TEC ≥ 96

Transmit Overload Warning Interrupt Flag

0 [Clearing condition]

Writing 1

1 Error warning state caused by receive error

[Setting condition]

When REC ≥ 96

Receive Overload Warning Interrupt Flag

0 [Clearing condition]

Writing 1

1 Error passive state caused by transmit/receive error

[Setting condition]

When TEC ≥ 128 or REC ≥ 128

Error Passive Interrupt Flag

0[Clearing condition]

Writing 1

1Bus off state caused by transmit error

[Setting condition]

When TEC ≥ 256

Bus Off Interrupt Flag

0[Clearing condition]

Writing 1

1 Overload frame transmission

[Setting conditions]

When overload frame is transmitted

Overload Frame Interrupt Flag

Note: After canceling a reset or returning from hardware standby

mode, the module stop bit is initialized yo 1. HCAN then

enters a module-stopped state.

Note: * Only 1 can be written, to clear the flag.

886

—

IRR12

R/(W)*

—

IRR8

R/(W)*

—

IRR9

R/(W)*

Bit

Initial value

Read/Write

Mailbox Empty Interrupt Flag

0[Clearing condition]

Writing 1

Transmit message has been transmitted or aborted, and new message

can be stored

[Setting condition]

When TXPR (transmit wait register) is cleared by completion of

transmission or completion of transmission abort

Unread Interrupt Flag

[Clearing condition]

Clearing of all bits in UMSR (unread message status register)

Unread message overwrite

[Setting condition]

When UMSR (unread message status register) is set

CAN bus idle state

[Clearing condition]

Writing 1

CAN bus operation in HCAN sleep mode

[Setting condition]

Bus operation (dominant bit detection) in HCAN sleep mode

Bus Operation Interrupt Flag

Note: * Only 1 can be written, to clear the flag.

887

MBIMR—Mailbox Interrupt Mask Register H'F814 HCAN

MBIMR7

R/W

MBIMR6

R/W

MBIMR5

R/W

MBIMR4

R/W

MBIMR3

R/W

MBIMR0

R/W

MBIMR2

R/W

MBIMR1

R/W

MBIMR15

R/W

MBIMR14

R/W

MBIMR13

R/W

MBIMR12

R/W

MBIMR11

R/W

MBIMR8

R/W

MBIMR10

R/W

MBIMR9

R/W

Bit

Initial value

Read/Write

Bit

Initial value

Read/Write

Mailbox Interrupt Mask

0 [Transmitting]

Interrupt request to CPU due to TXPR clearing

[Receiving]

Interrupt request to CPU due to RXPR setting

1 Interrupt requests to CPU disabled

888

IMR—Interrupt Mask Register H'F816 HCAN

IMR7

R/W

IMR6

R/W

IMR5

R/W

IMR4

R/W

IMR3

R/W

—

IMR2

R/W

IMR1

R/W

Bit

Initial value

Read/Write

Overload Frame/Bus Off Recovery Interrupt Mask

Bus Off Interrupt Mask

0Bus off interrupt request to CPU by IRR6 enabled

Bus off interrupt request to CPU by IRR6 disabled

0Overload frame/bus off recovery interrupt request to CPU by IRR7 enabled

1 Overload frame/bus off recovery interrupt request to CPU by IRR7 disabled

Error Passive Interrupt Mask

0 Error passive interrupt request to CPU by IRR5 enabled

1 Error passive interrupt request to CPU by IRR5 disabled

Receive Overload Warning Interrupt Mask

0REC error warning interrupt request to CPU by IRR4 enabled

1 REC error warning interrupt request to CPU by IRR4 disabled

Transmit Overload Warning Interrupt Mask

0TEC error warning interrupt request to CPU by IRR3 enabled

1 TEC error warning interrupt request to CPU by IRR3 disabled

Remote Frame Request Interrupt Mask

0Remote frame reception interrupt request to CPU by IRR2 enabled

1 Remote frame reception interrupt request to CPU by IRR2 disabled

Receive Message Interrupt Mask

Message reception interrupt request to CPU by IRR1 enabled

Message reception interrupt request to CPU by IRR1 disabled

889

—

IMR12

R/W

—

IMR8

R/W

—

IMR9

R/W

Bit

Initial value

Read/Write

Mailbox Empty Interrupt Mask

0Mailbox empty interrupt request to CPU by IRR8 enabled

1 Mailbox empty interrupt request to CPU by IRR8 disabled

Unread Interrupt Mask

0 Unread message overwrite interrupt request to CPU by IRR9 enabled

1 Unread message overwrite interrupt request to CPU by IRR9 disabled

Bus Operation Interrupt Mask

0 Bus operation interrupt request to CPU by IRR12 enabled

1 Bus operation interrupt request to CPU by IRR12 disabled

890

REC—Receive Error Counter H'F818 HCAN

Bit

Initial value

Read/Write

TEC—Transmit Error Counter H'F819 HCAN

Bit

Initial value

Read/Write

UMSR—Unread Message Status Register H'F81A HCAN

UMSR7

R/(W)*

UMSR6

R/(W)*

UMSR5

R/(W)*

UMSR4

R/(W)*

UMSR3

R/(W)*

UMSR0

R/(W)*

UMSR2

R/(W)*

UMSR1

R/(W)*

UMSR15

R/(W)*

UMSR14

R/(W)*

UMSR13

R/(W)*

UMSR12

R/(W)*

UMSR11

R/(W)*

UMSR8

R/(W)*

UMSR10

R/(W)*

UMSR9

R/(W)*

Bit

Initial value

Read/Write

Bit

Initial value

Read/Write

Note: * Only 1 can be written, to clear the flag.

Unread Message Status Flags

0 [Clearing condition]

Writing 1

(x = 15 to 0)

1 Unread receive message is overwritten by a new message

[Setting condition]

When a new message is received before RXPR is cleared

891

LAFML—Local Acceptance Filter Masks L H'F81C HCAN

LAFMH—Local Acceptance Filter Masks H H'F81E HCAN

LAFML7

R/W

LAFML6

R/W

LAFML5

R/W

LAFML4

R/W

LAFML3

R/W

LAFML0

R/W

LAFML2

R/W

LAFML1

R/W

LAFML15

R/W

LAFML14

R/W

LAFML13

R/W

LAFML12

R/W

LAFML11

R/W

LAFML8

R/W

LAFML10

R/W

LAFML9

R/W

Bit

Initial value

Read/Write

Bit

Initial value

Read/Write

LAFMH7

R/W

LAFMH6

R/W

LAFMH5

R/W

—

LAFMH0

R/W

—

LAFMH1

R/W

LAFMH15

R/W

LAFMH14

R/W

LAFMH13

R/W

LAFMH12

R/W

LAFMH11

R/W

LAFMH8

R/W

LAFMH10

R/W

LAFMH9

R/W

Bit

Initial value

Read/Write

LAFMH

Bit

Initial value

Read/Write

LAFMH Bits 7 to 0 and 15 to 13–11-Bit Identifier Filter

0 Stored in RX0 (receive-only mailbox) depending on bit match between

RX0 message identifier and receive message identifier (Care)

1 Stored in RX0 (receive-only mailbox) regardless of bit match between

RX0 message identifier and receive message identifier (Don’t Care)

LAFMH Bits 9 and 8, LAFML bits 15 to 0–18-Bit Identifier Filter

0 Stored in RX0 (receive-only mailbox) depending on bit match between

RX0 message identifier and receive message identifier (Care)

1 Stored in RX0 (receive-only mailbox) regardless of bit match between

RX0 message identifier and receive message identifier (Don’t Care)

892

MC01—Message Control 01 H'F820 HCAN

MC02—Message Control 02 H'F821 HCAN

MC03—Message Control 03 H'F822 HCAN

MC04—Message Control 04 H'F823 HCAN

MC05—Message Control 05 H'F824 HCAN

MC06—Message Control 06 H'F825 HCAN

MC07—Message Control 07 H'F826 HCAN

MC08—Message Control 08 H'F827 HCAN

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

DLC3

Undefined

—

DLC0

Undefined

—

DLC2

Undefined

—

DLC1

Undefined

—

Bit

Initial value

Read/Write

MC01

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC02

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC03

Data Length Code

0Data length = 0 byte

Data length = 1 byte

Data length = 2 bytes

Data length = 3 bytes

Data length = 4 bytes

Data length = 5 bytes

Data length = 6 bytes

Data length = 7 bytes

1 Data length = 8 bytes

Other than

the above

0Setting prohibited

893

STD_ID2

Undefined

R/W

STD_ID1

Undefined

R/W

STD_ID0

Undefined

R/W

RTR

Undefined

R/W

IDE

Undefined

R/W

EXD_ID16

Undefined

R/W

—

Undefined

R/W

EXD_ID17

Undefined

R/W

Bit

Initial value

Read/Write

MC05

STD_ID10

Undefined

R/W

STD_ID9

Undefined

R/W

STD_ID8

Undefined

R/W

STD_ID7

Undefined

R/W

STD_ID6

Undefined

R/W

STD_ID3

Undefined

R/W

STD_ID5

Undefined

R/W

STD_ID4

Undefined

R/W

Bit

Initial value

Read/Write

MC06

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

Extended Identifier

Set the identifier (extended identifier)

of data frames and remote frames

Remote Transmission Request

0 Data frame

1 Remote frame

Identifier Extension

0 Standard format

1 Extended format

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC04

894

EXD_ID15

Undefined

R/W

EXD_ID14

Undefined

R/W

EXD_ID13

Undefined

R/W

EXD_ID12

Undefined

R/W

EXD_ID11

Undefined

R/W

EXD_ID8

Undefined

R/W

EXD_ID10

Undefined

R/W

EXD_ID9

Undefined

R/W

Bit

Initial value

Read/Write

MC08

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

EXD_ID7

Undefined

R/W

EXD_ID6

Undefined

R/W

EXD_ID5

Undefined

R/W

EXD_ID4

Undefined

R/W

EXD_ID3

Undefined

R/W

EXD_ID0

Undefined

R/W

EXD_ID2

Undefined

R/W

EXD_ID1

Undefined

R/W

Bit

Initial value

Read/Write

MC07

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

895

MC11—Message Control 11 H'F828 HCAN

MC12—Message Control 12 H'F829 HCAN

MC13—Message Control 13 H'F82A HCAN

MC14—Message Control 14 H'F82B HCAN

MC15—Message Control 15 H'F82C HCAN

MC16—Message Control 16 H'F82D HCAN

MC17—Message Control 17 H'F82E HCAN

MC18—Message Control 18 H'F82F HCAN

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

DLC3

Undefined

—

DLC0

Undefined

—

DLC2

Undefined

—

DLC1

Undefined

—

Bit

Initial value

Read/Write

MC11

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC12

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC13

Data Length Code

0Data length = 0 byte

Data length = 1 byte

Data length = 2 bytes

Data length = 3 bytes

Data length = 4 bytes

Data length = 5 bytes

Data length = 6 bytes

Data length = 7 bytes

1 Data length = 8 bytes

Other than

the above

0Setting prohibited

896

STD_ID2

Undefined

R/W

STD_ID1

Undefined

R/W

STD_ID0

Undefined

R/W

RTR

Undefined

R/W

IDE

Undefined

R/W

EXD_ID16

Undefined

R/W

—

Undefined

R/W

EXD_ID17

Undefined

R/W

Bit

Initial value

Read/Write

MC15

STD_ID10

Undefined

R/W

STD_ID9

Undefined

R/W

STD_ID8

Undefined

R/W

STD_ID7

Undefined

R/W

STD_ID6

Undefined

R/W

STD_ID3

Undefined

R/W

STD_ID5

Undefined

R/W

STD_ID4

Undefined

R/W

Bit

Initial value

Read/Write

MC16

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

Extended Identifier

Set the identifier (extended identifier)

of data frames and remote frames

Remote Transmission Request

0 Data frame

1 Remote frame

Identifier Extension

0 Standard format

1 Extended format

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC14

897

EXD_ID15

Undefined

R/W

EXD_ID14

Undefined

R/W

EXD_ID13

Undefined

R/W

EXD_ID12

Undefined

R/W

EXD_ID11

Undefined

R/W

EXD_ID8

Undefined

R/W

EXD_ID10

Undefined

R/W

EXD_ID9

Undefined

R/W

Bit

Initial value

Read/Write

MC18

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

Bit

Initial value

Read/Write

MC17

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

EXD_ID7

Undefined

R/W

EXD_ID6

Undefined

R/W

EXD_ID5

Undefined

R/W

EXD_ID4

Undefined

R/W

EXD_ID3

Undefined

R/W

EXD_ID0

Undefined

R/W

EXD_ID2

Undefined

R/W

EXD_ID1

Undefined

R/W

898

MC21—Message Control 21 H'F830 HCAN

MC22—Message Control 22 H'F831 HCAN

MC23—Message Control 23 H'F832 HCAN

MC24—Message Control 24 H'F833 HCAN

MC25—Message Control 25 H'F834 HCAN

MC26—Message Control 26 H'F835 HCAN

MC27—Message Control 27 H'F836 HCAN

MC28—Message Control 28 H'F837 HCAN

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

DLC3

Undefined

—

DLC0

Undefined

—

DLC2

Undefined

—

DLC1

Undefined

—

Bit

Initial value

Read/Write

MC21

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC22

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC23

Data Length Code

0Data length = 0 byte

Data length = 1 byte

Data length = 2 bytes

Data length = 3 bytes

Data length = 4 bytes

Data length = 5 bytes

Data length = 6 bytes

Data length = 7 bytes

1 Data length = 8 bytes

Other than

the above

0Setting prohibited

899

STD_ID2

Undefined

R/W

STD_ID1

Undefined

R/W

STD_ID0

Undefined

R/W

RTR

Undefined

R/W

IDE

Undefined

R/W

EXD_ID16

Undefined

R/W

—

Undefined

R/W

EXD_ID17

Undefined

R/W

Bit

Initial value

Read/Write

MC25

STD_ID10

Undefined

R/W

STD_ID9

Undefined

R/W

STD_ID8

Undefined

R/W

STD_ID7

Undefined

R/W

STD_ID6

Undefined

R/W

STD_ID3

Undefined

R/W

STD_ID5

Undefined

R/W

STD_ID4

Undefined

R/W

Bit

Initial value

Read/Write

MC26

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

Extended Identifier

Set the identifier (extended identifier)

of data frames and remote frames

Remote Transmission Request

0 Data frame

1 Remote frame

Identifier Extension

0 Standard format

1 Extended format

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC24

900

EXD_ID15

Undefined

R/W

EXD_ID14

Undefined

R/W

EXD_ID13

Undefined

R/W

EXD_ID12

Undefined

R/W

EXD_ID11

Undefined

R/W

EXD_ID8

Undefined

R/W

EXD_ID10

Undefined

R/W

EXD_ID9

Undefined

R/W

Bit

Initial value

Read/Write

MC28

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

Bit

Initial value

Read/Write

MC27

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

EXD_ID7

Undefined

R/W

EXD_ID6

Undefined

R/W

EXD_ID5

Undefined

R/W

EXD_ID4

Undefined

R/W

EXD_ID3

Undefined

R/W

EXD_ID0

Undefined

R/W

EXD_ID2

Undefined

R/W

EXD_ID1

Undefined

R/W

901

MC31—Message Control 31 H'F838 HCAN

MC32—Message Control 32 H'F839 HCAN

MC33—Message Control 33 H'F83A HCAN

MC34—Message Control 34 H'F83B HCAN

MC35—Message Control 35 H'F83C HCAN

MC36—Message Control 36 H'F83D HCAN

MC37—Message Control 37 H'F83E HCAN

MC38—Message Control 38 H'F83F HCAN

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

DLC3

Undefined

—

DLC0

Undefined

—

DLC2

Undefined

—

DLC1

Undefined

—

Bit

Initial value

Read/Write

MC31

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC32

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC33

Data Length Code

0Data length = 0 byte

Data length = 1 byte

Data length = 2 bytes

Data length = 3 bytes

Data length = 4 bytes

Data length = 5 bytes

Data length = 6 bytes

Data length = 7 bytes

1 Data length = 8 bytes

Other than

the above

0Setting prohibited

902

STD_ID2

Undefined

R/W

STD_ID1

Undefined

R/W

STD_ID0

Undefined

R/W

RTR

Undefined

R/W

IDE

Undefined

R/W

EXD_ID16

Undefined

R/W

—

Undefined

R/W

EXD_ID17

Undefined

R/W

Bit

Initial value

Read/Write

MC35

STD_ID10

Undefined

R/W

STD_ID9

Undefined

R/W

STD_ID8

Undefined

R/W

STD_ID7

Undefined

R/W

STD_ID6

Undefined

R/W

STD_ID3

Undefined

R/W

STD_ID5

Undefined

R/W

STD_ID4

Undefined

R/W

Bit

Initial value

Read/Write

MC36

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

Extended Identifier

Set the identifier (extended identifier)

of data frames and remote frames

Remote Transmission Request

0 Data frame

1 Remote frame

Identifier Extension

0 Standard format

1 Extended format

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC34

903

EXD_ID15

Undefined

R/W

EXD_ID14

Undefined

R/W

EXD_ID13

Undefined

R/W

EXD_ID12

Undefined

R/W

EXD_ID11

Undefined

R/W

EXD_ID8

Undefined

R/W

EXD_ID10

Undefined

R/W

EXD_ID9

Undefined

R/W

Bit

Initial value

Read/Write

MC38

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

Bit

Initial value

Read/Write

MC37

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

EXD_ID7

Undefined

R/W

EXD_ID6

Undefined

R/W

EXD_ID5

Undefined

R/W

EXD_ID4

Undefined

R/W

EXD_ID3

Undefined

R/W

EXD_ID0

Undefined

R/W

EXD_ID2

Undefined

R/W

EXD_ID1

Undefined

R/W

904

MC41—Message Control 41 H'F840 HCAN

MC42—Message Control 42 H'F841 HCAN

MC43—Message Control 43 H'F842 HCAN

MC44—Message Control 44 H'F843 HCAN

MC45—Message Control 45 H'F844 HCAN

MC46—Message Control 46 H'F845 HCAN

MC47—Message Control 47 H'F846 HCAN

MC48—Message Control 48 H'F847 HCAN

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

DLC3

Undefined

—

DLC0

Undefined

—

DLC2

Undefined

—

DLC1

Undefined

—

Bit

Initial value

Read/Write

MC41

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC42

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC43

Data Length Code

0Data length = 0 byte

Data length = 1 byte

Data length = 2 bytes

Data length = 3 bytes

Data length = 4 bytes

Data length = 5 bytes

Data length = 6 bytes

Data length = 7 bytes

1 Data length = 8 bytes

Other than

the above

0Setting prohibited

905

STD_ID2

Undefined

R/W

STD_ID1

Undefined

R/W

STD_ID0

Undefined

R/W

RTR

Undefined

R/W

IDE

Undefined

R/W

EXD_ID16

Undefined

R/W

—

Undefined

R/W

EXD_ID17

Undefined

R/W

Bit

Initial value

Read/Write

MC45

STD_ID10

Undefined

R/W

STD_ID9

Undefined

R/W

STD_ID8

Undefined

R/W

STD_ID7

Undefined

R/W

STD_ID6

Undefined

R/W

STD_ID3

Undefined

R/W

STD_ID5

Undefined

R/W

STD_ID4

Undefined

R/W

Bit

Initial value

Read/Write

MC46

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

Extended Identifier

Set the identifier (extended identifier)

of data frames and remote frames

Remote Transmission Request

0 Data frame

1 Remote frame

Identifier Extension

0 Standard format

1 Extended format

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC44

906

EXD_ID15

Undefined

R/W

EXD_ID14

Undefined

R/W

EXD_ID13

Undefined

R/W

EXD_ID12

Undefined

R/W

EXD_ID11

Undefined

R/W

EXD_ID8

Undefined

R/W

EXD_ID10

Undefined

R/W

EXD_ID9

Undefined

R/W

Bit

Initial value

Read/Write

MC48

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

Bit

Initial value

Read/Write

MC47

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

EXD_ID7

Undefined

R/W

EXD_ID6

Undefined

R/W

EXD_ID5

Undefined

R/W

EXD_ID4

Undefined

R/W

EXD_ID3

Undefined

R/W

EXD_ID0

Undefined

R/W

EXD_ID2

Undefined

R/W

EXD_ID1

Undefined

R/W

907

MC51—Message Control 51 H'F848 HCAN

MC52—Message Control 52 H'F849 HCAN

MC53—Message Control 53 H'F84A HCAN

MC54—Message Control 54 H'F84B HCAN

MC55—Message Control 55 H'F84C HCAN

MC56—Message Control 56 H'F84D HCAN

MC57—Message Control 57 H'F84E HCAN

MC58—Message Control 58 H'F84F HCAN

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

DLC3

Undefined

—

DLC0

Undefined

—

DLC2

Undefined

—

DLC1

Undefined

—

Bit

Initial value

Read/Write

MC51

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC52

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC53

Data Length Code

0Data length = 0 byte

Data length = 1 byte

Data length = 2 bytes

Data length = 3 bytes

Data length = 4 bytes

Data length = 5 bytes

Data length = 6 bytes

Data length = 7 bytes

1 Data length = 8 bytes

Other than

the above

0Setting prohibited

908

STD_ID2

Undefined

R/W

STD_ID1

Undefined

R/W

STD_ID0

Undefined

R/W

RTR

Undefined

R/W

IDE

Undefined

R/W

EXD_ID16

Undefined

R/W

—

Undefined

R/W

EXD_ID17

Undefined

R/W

Bit

Initial value

Read/Write

MC55

STD_ID10

Undefined

R/W

STD_ID9

Undefined

R/W

STD_ID8

Undefined

R/W

STD_ID7

Undefined

R/W

STD_ID6

Undefined

R/W

STD_ID3

Undefined

R/W

STD_ID5

Undefined

R/W

STD_ID4

Undefined

R/W

Bit

Initial value

Read/Write

MC56

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

Extended Identifier

Set the identifier (extended identifier)

of data frames and remote frames

Remote Transmission Request

0 Data frame

1 Remote frame

Identifier Extension

0 Standard format

1 Extended format

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC54

909

EXD_ID15

Undefined

R/W

EXD_ID14

Undefined

R/W

EXD_ID13

Undefined

R/W

EXD_ID12

Undefined

R/W

EXD_ID11

Undefined

R/W

EXD_ID8

Undefined

R/W

EXD_ID10

Undefined

R/W

EXD_ID9

Undefined

R/W

Bit

Initial value

Read/Write

MC58

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

Bit

Initial value

Read/Write

MC57

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

EXD_ID7

Undefined

R/W

EXD_ID6

Undefined

R/W

EXD_ID5

Undefined

R/W

EXD_ID4

Undefined

R/W

EXD_ID3

Undefined

R/W

EXD_ID0

Undefined

R/W

EXD_ID2

Undefined

R/W

EXD_ID1

Undefined

R/W

910

MC61—Message Control 61 H'F850 HCAN

MC62—Message Control 62 H'F851 HCAN

MC63—Message Control 63 H'F852 HCAN

MC64—Message Control 64 H'F853 HCAN

MC65—Message Control 65 H'F854 HCAN

MC66—Message Control 66 H'F855 HCAN

MC67—Message Control 67 H'F856 HCAN

MC68—Message Control 68 H'F857 HCAN

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

DLC3

Undefined

—

DLC0

Undefined

—

DLC2

Undefined

—

DLC1

Undefined

—

Bit

Initial value

Read/Write

MC61

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC62

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC63

Data Length Code

0Data length = 0 byte

Data length = 1 byte

Data length = 2 bytes

Data length = 3 bytes

Data length = 4 bytes

Data length = 5 bytes

Data length = 6 bytes

Data length = 7 bytes

1 Data length = 8 bytes

Other than

the above

0Setting prohibited

911

STD_ID2

Undefined

R/W

STD_ID1

Undefined

R/W

STD_ID0

Undefined

R/W

RTR

Undefined

R/W

IDE

Undefined

R/W

EXD_ID16

Undefined

R/W

—

Undefined

R/W

EXD_ID17

Undefined

R/W

Bit

Initial value

Read/Write

MC65

STD_ID10

Undefined

R/W

STD_ID9

Undefined

R/W

STD_ID8

Undefined

R/W

STD_ID7

Undefined

R/W

STD_ID6

Undefined

R/W

STD_ID3

Undefined

R/W

STD_ID5

Undefined

R/W

STD_ID4

Undefined

R/W

Bit

Initial value

Read/Write

MC66

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

Extended Identifier

Set the identifier (extended identifier)

of data frames and remote frames

Remote Transmission Request

0 Data frame

1 Remote frame

Identifier Extension

0 Standard format

1 Extended format

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC64

912

EXD_ID15

Undefined

R/W

EXD_ID14

Undefined

R/W

EXD_ID13

Undefined

R/W

EXD_ID12

Undefined

R/W

EXD_ID11

Undefined

R/W

EXD_ID8

Undefined

R/W

EXD_ID10

Undefined

R/W

EXD_ID9

Undefined

R/W

Bit

Initial value

Read/Write

MC68

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

Bit

Initial value

Read/Write

MC67

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

EXD_ID7

Undefined

R/W

EXD_ID6

Undefined

R/W

EXD_ID5

Undefined

R/W

EXD_ID4

Undefined

R/W

EXD_ID3

Undefined

R/W

EXD_ID0

Undefined

R/W

EXD_ID2

Undefined

R/W

EXD_ID1

Undefined

R/W

913

MC71—Message Control 71 H'F858 HCAN

MC72—Message Control 72 H'F859 HCAN

MC73—Message Control 73 H'F85A HCAN

MC74—Message Control 74 H'F85B HCAN

MC75—Message Control 75 H'F85C HCAN

MC76—Message Control 76 H'F85D HCAN

MC77—Message Control 77 H'F85E HCAN

MC78—Message Control 78 H'F85F HCAN

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

DLC3

Undefined

—

DLC0

Undefined

—

DLC2

Undefined

—

DLC1

Undefined

—

Bit

Initial value

Read/Write

MC71

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC72

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC73

Data Length Code

0Data length = 0 byte

Data length = 1 byte

Data length = 2 bytes

Data length = 3 bytes

Data length = 4 bytes

Data length = 5 bytes

Data length = 6 bytes

Data length = 7 bytes

1 Data length = 8 bytes

Other than

the above

0Setting prohibited

914

STD_ID2

Undefined

R/W

STD_ID1

Undefined

R/W

STD_ID0

Undefined

R/W

RTR

Undefined

R/W

IDE

Undefined

R/W

EXD_ID16

Undefined

R/W

—

Undefined

R/W

EXD_ID17

Undefined

R/W

Bit

Initial value

Read/Write

MC75

STD_ID10

Undefined

R/W

STD_ID9

Undefined

R/W

STD_ID8

Undefined

R/W

STD_ID7

Undefined

R/W

STD_ID6

Undefined

R/W

STD_ID3

Undefined

R/W

STD_ID5

Undefined

R/W

STD_ID4

Undefined

R/W

Bit

Initial value

Read/Write

MC76

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

Extended Identifier

Set the identifier (extended identifier)

of data frames and remote frames

Remote Transmission Request

0 Data frame

1 Remote frame

Identifier Extension

0 Standard format

1 Extended format

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC74

915

EXD_ID15

Undefined

R/W

EXD_ID14

Undefined

R/W

EXD_ID13

Undefined

R/W

EXD_ID12

Undefined

R/W

EXD_ID11

Undefined

R/W

EXD_ID8

Undefined

R/W

EXD_ID10

Undefined

R/W

EXD_ID9

Undefined

R/W

Bit

Initial value

Read/Write

MC78

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

Bit

Initial value

Read/Write

MC77

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

EXD_ID7

Undefined

R/W

EXD_ID6

Undefined

R/W

EXD_ID5

Undefined

R/W

EXD_ID4

Undefined

R/W

EXD_ID3

Undefined

R/W

EXD_ID0

Undefined

R/W

EXD_ID2

Undefined

R/W

EXD_ID1

Undefined

R/W

916

MC81—Message Control 81 H'F860 HCAN

MC82—Message Control 82 H'F861 HCAN

MC83—Message Control 83 H'F862 HCAN

MC84—Message Control 84 H'F863 HCAN

MC85—Message Control 85 H'F864 HCAN

MC86—Message Control 86 H'F865 HCAN

MC87—Message Control 87 H'F866 HCAN

MC88—Message Control 88 H'F867 HCAN

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

DLC3

Undefined

—

DLC0

Undefined

—

DLC2

Undefined

—

DLC1

Undefined

—

Bit

Initial value

Read/Write

MC81

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC82

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC83

Data Length Code

0Data length = 0 byte

Data length = 1 byte

Data length = 2 bytes

Data length = 3 bytes

Data length = 4 bytes

Data length = 5 bytes

Data length = 6 bytes

Data length = 7 bytes

1 Data length = 8 bytes

Other than

the above

0Setting prohibited

917

STD_ID2

Undefined

R/W

STD_ID1

Undefined

R/W

STD_ID0

Undefined

R/W

RTR

Undefined

R/W

IDE

Undefined

R/W

EXD_ID16

Undefined

R/W

—

Undefined

R/W

EXD_ID17

Undefined

R/W

Bit

Initial value

Read/Write

MC85

STD_ID10

Undefined

R/W

STD_ID9

Undefined

R/W

STD_ID8

Undefined

R/W

STD_ID7

Undefined

R/W

STD_ID6

Undefined

R/W

STD_ID3

Undefined

R/W

STD_ID5

Undefined

R/W

STD_ID4

Undefined

R/W

Bit

Initial value

Read/Write

MC86

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

Extended Identifier

Set the identifier (extended identifier)

of data frames and remote frames

Remote Transmission Request

0 Data frame

1 Remote frame

Identifier Extension

0 Standard format

1 Extended format

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC84

918

EXD_ID15

Undefined

R/W

EXD_ID14

Undefined

R/W

EXD_ID13

Undefined

R/W

EXD_ID12

Undefined

R/W

EXD_ID11

Undefined

R/W

EXD_ID8

Undefined

R/W

EXD_ID10

Undefined

R/W

EXD_ID9

Undefined

R/W

Bit

Initial value

Read/Write

MC88

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

Bit

Initial value

Read/Write

MC87

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

EXD_ID7

Undefined

R/W

EXD_ID6

Undefined

R/W

EXD_ID5

Undefined

R/W

EXD_ID4

Undefined

R/W

EXD_ID3

Undefined

R/W

EXD_ID0

Undefined

R/W

EXD_ID2

Undefined

R/W

EXD_ID1

Undefined

R/W

919

MC91—Message Control 91 H'F868 HCAN

MC92—Message Control 92 H'F869 HCAN

MC93—Message Control 93 H'F86A HCAN

MC94—Message Control 94 H'F86B HCAN

MC95—Message Control 95 H'F86C HCAN

MC96—Message Control 96 H'F86D HCAN

MC97—Message Control 97 H'F86E HCAN

MC98—Message Control 98 H'F86F HCAN

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

DLC3

Undefined

—

DLC0

Undefined

—

DLC2

Undefined

—

DLC1

Undefined

—

Bit

Initial value

Read/Write

MC91

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC92

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC93

Data Length Code

0Data length = 0 byte

Data length = 1 byte

Data length = 2 bytes

Data length = 3 bytes

Data length = 4 bytes

Data length = 5 bytes

Data length = 6 bytes

Data length = 7 bytes

1 Data length = 8 bytes

Other than

the above

0Setting prohibited

920

STD_ID2

Undefined

R/W

STD_ID1

Undefined

R/W

STD_ID0

Undefined

R/W

RTR

Undefined

R/W

IDE

Undefined

R/W

EXD_ID16

Undefined

R/W

—

Undefined

R/W

EXD_ID17

Undefined

R/W

Bit

Initial value

Read/Write

MC95

STD_ID10

Undefined

R/W

STD_ID9

Undefined

R/W

STD_ID8

Undefined

R/W

STD_ID7

Undefined

R/W

STD_ID6

Undefined

R/W

STD_ID3

Undefined

R/W

STD_ID5

Undefined

R/W

STD_ID4

Undefined

R/W

Bit

Initial value

Read/Write

MC96

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

Extended Identifier

Set the identifier (extended identifier)

of data frames and remote frames

Remote Transmission Request

0 Data frame

1 Remote frame

Identifier Extension

0 Standard format

1 Extended format

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC94

921

EXD_ID15

Undefined

R/W

EXD_ID14

Undefined

R/W

EXD_ID13

Undefined

R/W

EXD_ID12

Undefined

R/W

EXD_ID11

Undefined

R/W

EXD_ID8

Undefined

R/W

EXD_ID10

Undefined

R/W

EXD_ID9

Undefined

R/W

Bit

Initial value

Read/Write

MC98

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

Bit

Initial value

Read/Write

MC97

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

EXD_ID7

Undefined

R/W

EXD_ID6

Undefined

R/W

EXD_ID5

Undefined

R/W

EXD_ID4

Undefined

R/W

EXD_ID3

Undefined

R/W

EXD_ID0

Undefined

R/W

EXD_ID2

Undefined

R/W

EXD_ID1

Undefined

R/W

922

MC101—Message Control 101 H'F870 HCAN

MC102—Message Control 102 H'F871 HCAN

MC103—Message Control 103 H'F872 HCAN

MC104—Message Control 104 H'F873 HCAN

MC105—Message Control 105 H'F874 HCAN

MC106—Message Control 106 H'F875 HCAN

MC107—Message Control 107 H'F876 HCAN

MC108—Message Control 108 H'F877 HCAN

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

DLC3

Undefined

—

DLC0

Undefined

—

DLC2

Undefined

—

DLC1

Undefined

—

Bit

Initial value

Read/Write

MC101

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC102

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC103

Data Length Code

0Data length = 0 byte

Data length = 1 byte

Data length = 2 bytes

Data length = 3 bytes

Data length = 4 bytes

Data length = 5 bytes

Data length = 6 bytes

Data length = 7 bytes

1 Data length = 8 bytes

Other than

the above

0Setting prohibited

923

STD_ID2

Undefined

R/W

STD_ID1

Undefined

R/W

STD_ID0

Undefined

R/W

RTR

Undefined

R/W

IDE

Undefined

R/W

EXD_ID16

Undefined

R/W

—

Undefined

R/W

EXD_ID17

Undefined

R/W

Bit

Initial value

Read/Write

MC105

STD_ID10

Undefined

R/W

STD_ID9

Undefined

R/W

STD_ID8

Undefined

R/W

STD_ID7

Undefined

R/W

STD_ID6

Undefined

R/W

STD_ID3

Undefined

R/W

STD_ID5

Undefined

R/W

STD_ID4

Undefined

R/W

Bit

Initial value

Read/Write

MC106

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

Extended Identifier

Set the identifier (extended identifier)

of data frames and remote frames

Remote Transmission Request

0 Data frame

1 Remote frame

Identifier Extension

0 Standard format

1 Extended format

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC104

924

EXD_ID15

Undefined

R/W

EXD_ID14

Undefined

R/W

EXD_ID13

Undefined

R/W

EXD_ID12

Undefined

R/W

EXD_ID11

Undefined

R/W

EXD_ID8

Undefined

R/W

EXD_ID10

Undefined

R/W

EXD_ID9

Undefined

R/W

Bit

Initial value

Read/Write

MC108

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

Bit

Initial value

Read/Write

MC107

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

EXD_ID7

Undefined

R/W

EXD_ID6

Undefined

R/W

EXD_ID5

Undefined

R/W

EXD_ID4

Undefined

R/W

EXD_ID3

Undefined

R/W

EXD_ID0

Undefined

R/W

EXD_ID2

Undefined

R/W

EXD_ID1

Undefined

R/W

925

MC111—Message Control 111 H'F878 HCAN

MC112—Message Control 112 H'F879 HCAN

MC113—Message Control 113 H'F87A HCAN

MC114—Message Control 114 H'F87B HCAN

MC115—Message Control 115 H'F87C HCAN

MC116—Message Control 116 H'F87D HCAN

MC117—Message Control 117 H'F87E HCAN

MC118—Message Control 118 H'F87F HCAN

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

DLC3

Undefined

—

DLC0

Undefined

—

DLC2

Undefined

—

DLC1

Undefined

—

Bit

Initial value

Read/Write

MC111

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC112

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC113

Data Length Code

0Data length = 0 byte

Data length = 1 byte

Data length = 2 bytes

Data length = 3 bytes

Data length = 4 bytes

Data length = 5 bytes

Data length = 6 bytes

Data length = 7 bytes

1 Data length = 8 bytes

Other than

the above

0Setting prohibited

926

STD_ID2

Undefined

R/W

STD_ID1

Undefined

R/W

STD_ID0

Undefined

R/W

RTR

Undefined

R/W

IDE

Undefined

R/W

EXD_ID16

Undefined

R/W

—

Undefined

R/W

EXD_ID17

Undefined

R/W

Bit

Initial value

Read/Write

MC115

STD_ID10

Undefined

R/W

STD_ID9

Undefined

R/W

STD_ID8

Undefined

R/W

STD_ID7

Undefined

R/W

STD_ID6

Undefined

R/W

STD_ID3

Undefined

R/W

STD_ID5

Undefined

R/W

STD_ID4

Undefined

R/W

Bit

Initial value

Read/Write

MC116

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

Extended Identifier

Set the identifier (extended identifier)

of data frames and remote frames

Remote Transmission Request

0 Data frame

1 Remote frame

Identifier Extension

0 Standard format

1 Extended format

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC114

927

EXD_ID15

Undefined

R/W

EXD_ID14

Undefined

R/W

EXD_ID13

Undefined

R/W

EXD_ID12

Undefined

R/W

EXD_ID11

Undefined

R/W

EXD_ID8

Undefined

R/W

EXD_ID10

Undefined

R/W

EXD_ID9

Undefined

R/W

Bit

Initial value

Read/Write

MC118

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

Bit

Initial value

Read/Write

MC117

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

EXD_ID7

Undefined

R/W

EXD_ID6

Undefined

R/W

EXD_ID5

Undefined

R/W

EXD_ID4

Undefined

R/W

EXD_ID3

Undefined

R/W

EXD_ID0

Undefined

R/W

EXD_ID2

Undefined

R/W

EXD_ID1

Undefined

R/W

928

MC121—Message Control 121 H'F880 HCAN

MC122—Message Control 122 H'F881 HCAN

MC123—Message Control 123 H'F882 HCAN

MC124—Message Control 124 H'F883 HCAN

MC125—Message Control 125 H'F884 HCAN

MC126—Message Control 126 H'F885 HCAN

MC127—Message Control 127 H'F886 HCAN

MC128—Message Control 128 H'F887 HCAN

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

DLC3

Undefined

—

DLC0

Undefined

—

DLC2

Undefined

—

DLC1

Undefined

—

Bit

Initial value

Read/Write

MC121

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC122

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC123

Data Length Code

0Data length = 0 byte

Data length = 1 byte

Data length = 2 bytes

Data length = 3 bytes

Data length = 4 bytes

Data length = 5 bytes

Data length = 6 bytes

Data length = 7 bytes

1 Data length = 8 bytes

Other than

the above

0Setting prohibited

929

STD_ID2

Undefined

R/W

STD_ID1

Undefined

R/W

STD_ID0

Undefined

R/W

RTR

Undefined

R/W

IDE

Undefined

R/W

EXD_ID16

Undefined

R/W

—

Undefined

R/W

EXD_ID17

Undefined

R/W

Bit

Initial value

Read/Write

MC125

STD_ID10

Undefined

R/W

STD_ID9

Undefined

R/W

STD_ID8

Undefined

R/W

STD_ID7

Undefined

R/W

STD_ID6

Undefined

R/W

STD_ID3

Undefined

R/W

STD_ID5

Undefined

R/W

STD_ID4

Undefined

R/W

Bit

Initial value

Read/Write

MC126

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

Extended Identifier

Set the identifier (extended identifier)

of data frames and remote frames

Remote Transmission Request

0 Data frame

1 Remote frame

Identifier Extension

0 Standard format

1 Extended format

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC124

930

EXD_ID15

Undefined

R/W

EXD_ID14

Undefined

R/W

EXD_ID13

Undefined

R/W

EXD_ID12

Undefined

R/W

EXD_ID11

Undefined

R/W

EXD_ID8

Undefined

R/W

EXD_ID10

Undefined

R/W

EXD_ID9

Undefined

R/W

Bit

Initial value

Read/Write

MC128

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

Bit

Initial value

Read/Write

MC127

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

EXD_ID7

Undefined

R/W

EXD_ID6

Undefined

R/W

EXD_ID5

Undefined

R/W

EXD_ID4

Undefined

R/W

EXD_ID3

Undefined

R/W

EXD_ID0

Undefined

R/W

EXD_ID2

Undefined

R/W

EXD_ID1

Undefined

R/W

931

MC131—Message Control 131 H'F888 HCAN

MC132—Message Control 132 H'F889 HCAN

MC133—Message Control 133 H'F88A HCAN

MC134—Message Control 134 H'F88B HCAN

MC135—Message Control 135 H'F88C HCAN

MC136—Message Control 136 H'F88D HCAN

MC137—Message Control 137 H'F88E HCAN

MC138—Message Control 138 H'F88F HCAN

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

DLC3

Undefined

—

DLC0

Undefined

—

DLC2

Undefined

—

DLC1

Undefined

—

Bit

Initial value

Read/Write

MC131

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC132

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC133

Data Length Code

0Data length = 0 byte

Data length = 1 byte

Data length = 2 bytes

Data length = 3 bytes

Data length = 4 bytes

Data length = 5 bytes

Data length = 6 bytes

Data length = 7 bytes

1 Data length = 8 bytes

Other than

the above

0Setting prohibited

932

STD_ID2

Undefined

R/W

STD_ID1

Undefined

R/W

STD_ID0

Undefined

R/W

RTR

Undefined

R/W

IDE

Undefined

R/W

EXD_ID16

Undefined

R/W

—

Undefined

R/W

EXD_ID17

Undefined

R/W

Bit

Initial value

Read/Write

MC135

STD_ID10

Undefined

R/W

STD_ID9

Undefined

R/W

STD_ID8

Undefined

R/W

STD_ID7

Undefined

R/W

STD_ID6

Undefined

R/W

STD_ID3

Undefined

R/W

STD_ID5

Undefined

R/W

STD_ID4

Undefined

R/W

Bit

Initial value

Read/Write

MC136

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

Extended Identifier

Set the identifier (extended identifier)

of data frames and remote frames

Remote Transmission Request

0 Data frame

1 Remote frame

Identifier Extension

0 Standard format

1 Extended format

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC134

933

EXD_ID15

Undefined

R/W

EXD_ID14

Undefined

R/W

EXD_ID13

Undefined

R/W

EXD_ID12

Undefined

R/W

EXD_ID11

Undefined

R/W

EXD_ID8

Undefined

R/W

EXD_ID10

Undefined

R/W

EXD_ID9

Undefined

R/W

Bit

Initial value

Read/Write

MC138

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

Bit

Initial value

Read/Write

MC137

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

EXD_ID7

Undefined

R/W

EXD_ID6

Undefined

R/W

EXD_ID5

Undefined

R/W

EXD_ID4

Undefined

R/W

EXD_ID3

Undefined

R/W

EXD_ID0

Undefined

R/W

EXD_ID2

Undefined

R/W

EXD_ID1

Undefined

R/W

934

MC141—Message Control 141 H'F890 HCAN

MC142—Message Control 142 H'F891 HCAN

MC143—Message Control 143 H'F892 HCAN

MC144—Message Control 144 H'F893 HCAN

MC145—Message Control 145 H'F894 HCAN

MC146—Message Control 146 H'F895 HCAN

MC147—Message Control 147 H'F896 HCAN

MC148—Message Control 148 H'F897 HCAN

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

DLC3

Undefined

—

DLC0

Undefined

—

DLC2

Undefined

—

DLC1

Undefined

—

Bit

Initial value

Read/Write

MC141

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC142

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC143

Data Length Code

0Data length = 0 byte

Data length = 1 byte

Data length = 2 bytes

Data length = 3 bytes

Data length = 4 bytes

Data length = 5 bytes

Data length = 6 bytes

Data length = 7 bytes

1 Data length = 8 bytes

Other than

the above

0Setting prohibited

935

STD_ID2

Undefined

R/W

STD_ID1

Undefined

R/W

STD_ID0

Undefined

R/W

RTR

Undefined

R/W

IDE

Undefined

R/W

EXD_ID16

Undefined

R/W

—

Undefined

R/W

EXD_ID17

Undefined

R/W

Bit

Initial value

Read/Write

MC145

STD_ID10

Undefined

R/W

STD_ID9

Undefined

R/W

STD_ID8

Undefined

R/W

STD_ID7

Undefined

R/W

STD_ID6

Undefined

R/W

STD_ID3

Undefined

R/W

STD_ID5

Undefined

R/W

STD_ID4

Undefined

R/W

Bit

Initial value

Read/Write

MC146

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

Extended Identifier

Set the identifier (extended identifier)

of data frames and remote frames

Remote Transmission Request

0 Data frame

1 Remote frame

Identifier Extension

0 Standard format

1 Extended format

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC144

936

EXD_ID15

Undefined

R/W

EXD_ID14

Undefined

R/W

EXD_ID13

Undefined

R/W

EXD_ID12

Undefined

R/W

EXD_ID11

Undefined

R/W

EXD_ID8

Undefined

R/W

EXD_ID10

Undefined

R/W

EXD_ID9

Undefined

R/W

Bit

Initial value

Read/Write

MC148

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

Bit

Initial value

Read/Write

MC147

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

EXD_ID7

Undefined

R/W

EXD_ID6

Undefined

R/W

EXD_ID5

Undefined

R/W

EXD_ID4

Undefined

R/W

EXD_ID3

Undefined

R/W

EXD_ID0

Undefined

R/W

EXD_ID2

Undefined

R/W

EXD_ID1

Undefined

R/W

937

MC151—Message Control 151 H'F898 HCAN

MC152—Message Control 152 H'F899 HCAN

MC153—Message Control 153 H'F89A HCAN

MC154—Message Control 154 H'F89B HCAN

MC155—Message Control 155 H'F89C HCAN

MC156—Message Control 156 H'F89D HCAN

MC157—Message Control 157 H'F89E HCAN

MC158—Message Control 158 H'F89F HCAN

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

DLC3

Undefined

—

DLC0

Undefined

—

DLC2

Undefined

—

DLC1

Undefined

—

Bit

Initial value

Read/Write

MC151

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC152

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC153

Data Length Code

0Data length = 0 byte

Data length = 1 byte

Data length = 2 bytes

Data length = 3 bytes

Data length = 4 bytes

Data length = 5 bytes

Data length = 6 bytes

Data length = 7 bytes

1 Data length = 8 bytes

Other than

the above

0Setting prohibited

938

STD_ID2

Undefined

R/W

STD_ID1

Undefined

R/W

STD_ID0

Undefined

R/W

RTR

Undefined

R/W

IDE

Undefined

R/W

EXD_ID16

Undefined

R/W

—

Undefined

R/W

EXD_ID17

Undefined

R/W

Bit

Initial value

Read/Write

MC155

STD_ID10

Undefined

R/W

STD_ID9

Undefined

R/W

STD_ID8

Undefined

R/W

STD_ID7

Undefined

R/W

STD_ID6

Undefined

R/W

STD_ID3

Undefined

R/W

STD_ID5

Undefined

R/W

STD_ID4

Undefined

R/W

Bit

Initial value

Read/Write

MC156

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

Extended Identifier

Set the identifier (extended identifier)

of data frames and remote frames

Remote Transmission Request

0 Data frame

1 Remote frame

Identifier Extension

0 Standard format

1 Extended format

Standard Identifier

Set the identifier (standard identifier) of data frames and remote frames

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

—

Undefined

R/W

Bit

Initial value

Read/Write

MC154

939

EXD_ID15

Undefined

R/W

EXD_ID14

Undefined

R/W

EXD_ID13

Undefined

R/W

EXD_ID12

Undefined

R/W

EXD_ID11

Undefined

R/W

EXD_ID8

Undefined

R/W

EXD_ID10

Undefined

R/W

EXD_ID9

Undefined

R/W

Bit

Initial value

Read/Write

MC158

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

Bit

Initial value

Read/Write

MC157

Extended Identifier

Set the identifier (extended identifier) of data frames and remote frames

EXD_ID7

Undefined

R/W

EXD_ID6

Undefined

R/W

EXD_ID5

Undefined

R/W

EXD_ID4

Undefined

R/W

EXD_ID3

Undefined

R/W

EXD_ID0

Undefined

R/W

EXD_ID2

Undefined

R/W

EXD_ID1

Undefined

R/W

940

MD01—Message Data 01 H'F8B0 HCAN

MD02—Message Data 02 H'F8B1 HCAN

MD03—Message Data 03 H'F8B2 HCAN

MD04—Message Data 04 H'F8B3 HCAN

MD05—Message Data 05 H'F8B4 HCAN

MD06—Message Data 06 H'F8B5 HCAN

MD07—Message Data 07 H'F8B6 HCAN

MD08—Message Data 08 H'F8B7 HCAN

MD01

MD02

MD03

MD04

MD05

MD06

MD07

MD08

MSG_DATA_1 (8 bits)

MSG_DATA_2 (8 bits)

MSG_DATA_3 (8 bits)

MSG_DATA_4 (8 bits)

MSG_DATA_5 (8 bits)

MSG_DATA_6 (8 bits)

MSG_DATA_7 (8 bits)

MSG_DATA_8 (8 bits)

MD11—Message Data 11 H'F8B8 HCAN

MD12—Message Data 12 H'F8B9 HCAN

MD13—Message Data 13 H'F8BA HCAN

MD14—Message Data 14 H'F8BB HCAN

MD15—Message Data 15 H'F8BC HCAN

MD16—Message Data 16 H'F8BD HCAN

MD17—Message Data 17 H'F8BE HCAN

MD18—Message Data 18 H'F8BF HCAN

MD11

MD12

MD13

MD14

MD15

MD16

MD17

MD18

MSG_DATA_1 (8 bits)

MSG_DATA_2 (8 bits)

MSG_DATA_3 (8 bits)

MSG_DATA_4 (8 bits)

MSG_DATA_5 (8 bits)

MSG_DATA_6 (8 bits)

MSG_DATA_7 (8 bits)

MSG_DATA_8 (8 bits)

941

MD21—Message Data 21 H'F8C0 HCAN

MD22—Message Data 22 H'F8C1 HCAN

MD23—Message Data 23 H'F8C2 HCAN

MD24—Message Data 24 H'F8C3 HCAN

MD25—Message Data 25 H'F8C4 HCAN

MD26—Message Data 26 H'F8C5 HCAN

MD27—Message Data 27 H'F8C6 HCAN

MD28—Message Data 28 H'F8C7 HCAN

MD21

MD22

MD23

MD24

MD25

MD26

MD27

MD28

MSG_DATA_1 (8 bits)

MSG_DATA_2 (8 bits)

MSG_DATA_3 (8 bits)

MSG_DATA_4 (8 bits)

MSG_DATA_5 (8 bits)

MSG_DATA_6 (8 bits)

MSG_DATA_7 (8 bits)

MSG_DATA_8 (8 bits)

MD31—Message Data 31 H'F8C8 HCAN

MD32—Message Data 32 H'F8C9 HCAN

MD33—Message Data 33 H'F8CA HCAN

MD34—Message Data 34 H'F8CB HCAN

MD35—Message Data 35 H'F8CC HCAN

MD36—Message Data 36 H'F8CD HCAN

MD37—Message Data 37 H'F8CE HCAN

MD38—Message Data 38 H'F8CF HCAN

MD31

MD32

MD33

MD34

MD35

MD36

MD37

MD38

MSG_DATA_1 (8 bits)

MSG_DATA_2 (8 bits)

MSG_DATA_3 (8 bits)

MSG_DATA_4 (8 bits)

MSG_DATA_5 (8 bits)

MSG_DATA_6 (8 bits)

MSG_DATA_7 (8 bits)

MSG_DATA_8 (8 bits)

942

MD41—Message Data 41 H'F8D0 HCAN

MD42—Message Data 42 H'F8D1 HCAN

MD43—Message Data 43 H'F8D2 HCAN

MD44—Message Data 44 H'F8D3 HCAN

MD45—Message Data 45 H'F8D4 HCAN

MD46—Message Data 46 H'F8D5 HCAN

MD47—Message Data 47 H'F8D6 HCAN

MD48—Message Data 48 H'F8D7 HCAN

MD41

MD42

MD43

MD44

MD45

MD46

MD47

MD48

MSG_DATA_1 (8 bits)

MSG_DATA_2 (8 bits)

MSG_DATA_3 (8 bits)

MSG_DATA_4 (8 bits)

MSG_DATA_5 (8 bits)

MSG_DATA_6 (8 bits)

MSG_DATA_7 (8 bits)

MSG_DATA_8 (8 bits)

MD51—Message Data 51 H'F8D8 HCAN

MD52—Message Data 52 H'F8D9 HCAN

MD53—Message Data 53 H'F8DA HCAN

MD54—Message Data 54 H'F8DB HCAN

MD55—Message Data 55 H'F8DC HCAN

MD56—Message Data 56 H'F8DD HCAN

MD57—Message Data 57 H'F8DE HCAN

MD58—Message Data 58 H'F8DF HCAN

MD51

MD52

MD53

MD54

MD55

MD56

MD57

MD58

MSG_DATA_1 (8 bits)

MSG_DATA_2 (8 bits)

MSG_DATA_3 (8 bits)

MSG_DATA_4 (8 bits)

MSG_DATA_5 (8 bits)

MSG_DATA_6 (8 bits)

MSG_DATA_7 (8 bits)

MSG_DATA_8 (8 bits)

943

MD61—Message Data 61 H'F8E0 HCAN

MD62—Message Data 62 H'F8E1 HCAN

MD63—Message Data 63 H'F8E2 HCAN

MD64—Message Data 64 H'F8E3 HCAN

MD65—Message Data 65 H'F8E4 HCAN

MD66—Message Data 66 H'F8E5 HCAN

MD67—Message Data 67 H'F8E6 HCAN

MD68—Message Data 68 H'F8E7 HCAN

MD61

MD62

MD63

MD64

MD65

MD66

MD67

MD68

MSG_DATA_1 (8 bits)

MSG_DATA_2 (8 bits)

MSG_DATA_3 (8 bits)

MSG_DATA_4 (8 bits)

MSG_DATA_5 (8 bits)

MSG_DATA_6 (8 bits)

MSG_DATA_7 (8 bits)

MSG_DATA_8 (8 bits)

MD71—Message Data 71 H'F8E8 HCAN

MD72—Message Data 72 H'F8E9 HCAN

MD73—Message Data 73 H'F8EA HCAN

MD74—Message Data 74 H'F8EB HCAN

MD75—Message Data 75 H'F8EC HCAN

MD76—Message Data 76 H'F8ED HCAN

MD77—Message Data 77 H'F8EE HCAN

MD78—Message Data 78 H'F8EF HCAN

MD71

MD72

MD73

MD74

MD75

MD76

MD77

MD78

MSG_DATA_1 (8 bits)

MSG_DATA_2 (8 bits)

MSG_DATA_3 (8 bits)

MSG_DATA_4 (8 bits)

MSG_DATA_5 (8 bits)

MSG_DATA_6 (8 bits)

MSG_DATA_7 (8 bits)

MSG_DATA_8 (8 bits)

944

MD81—Message Data 81 H'F8F0 HCAN

MD82—Message Data 82 H'F8F1 HCAN

MD83—Message Data 83 H'F8F2 HCAN

MD84—Message Data 84 H'F8F3 HCAN

MD85—Message Data 85 H'F8F4 HCAN

MD86—Message Data 86 H'F8F5 HCAN

MD87—Message Data 87 H'F8F6 HCAN

MD88—Message Data 88 H'F8F7 HCAN

MD81

MD82

MD83

MD84

MD85

MD86

MD87

MD88

MSG_DATA_1 (8 bits)

MSG_DATA_2 (8 bits)

MSG_DATA_3 (8 bits)

MSG_DATA_4 (8 bits)

MSG_DATA_5 (8 bits)

MSG_DATA_6 (8 bits)

MSG_DATA_7 (8 bits)

MSG_DATA_8 (8 bits)

MD91—Message Data 91 H'F8F8 HCAN

MD92—Message Data 92 H'F8F9 HCAN

MD93—Message Data 93 H'F8FA HCAN

MD94—Message Data 94 H'F8FB HCAN

MD95—Message Data 95 H'F8FC HCAN

MD96—Message Data 96 H'F8FD HCAN

MD97—Message Data 97 H'F8FE HCAN

MD98—Message Data 98 H'F8FF HCAN

MD91

MD92

MD93

MD94

MD95

MD96

MD97

MD98

MSG_DATA_1 (8 bits)

MSG_DATA_2 (8 bits)

MSG_DATA_3 (8 bits)

MSG_DATA_4 (8 bits)

MSG_DATA_5 (8 bits)

MSG_DATA_6 (8 bits)

MSG_DATA_7 (8 bits)

MSG_DATA_8 (8 bits)

945

MD101—Message Data 101 H'F900 HCAN

MD102—Message Data 102 H'F901 HCAN

MD103—Message Data 103 H'F902 HCAN

MD104—Message Data 104 H'F903 HCAN

MD105—Message Data 105 H'F904 HCAN

MD106—Message Data 106 H'F905 HCAN

MD107—Message Data 107 H'F906 HCAN

MD108—Message Data 108 H'F907 HCAN

MD101

MD102

MD103

MD104

MD105

MD106

MD107

MD108

MSG_DATA_1 (8 bits)

MSG_DATA_2 (8 bits)

MSG_DATA_3 (8 bits)

MSG_DATA_4 (8 bits)

MSG_DATA_5 (8 bits)

MSG_DATA_6 (8 bits)

MSG_DATA_7 (8 bits)

MSG_DATA_8 (8 bits)

MD111—Message Data 111 H'F908 HCAN

MD112—Message Data 112 H'F909 HCAN

MD113—Message Data 113 H'F90A HCAN

MD114—Message Data 114 H'F90B HCAN

MD115—Message Data 115 H'F90C HCAN

MD116—Message Data 116 H'F90D HCAN

MD117—Message Data 117 H'F90E HCAN

MD118—Message Data 118 H'F90F HCAN

MD111

MD112

MD113

MD114

MD115

MD116

MD117

MD118

MSG_DATA_1 (8 bits)

MSG_DATA_2 (8 bits)

MSG_DATA_3 (8 bits)

MSG_DATA_4 (8 bits)

MSG_DATA_5 (8 bits)

MSG_DATA_6 (8 bits)

MSG_DATA_7 (8 bits)

MSG_DATA_8 (8 bits)

946

MD121—Message Data 121 H'F910 HCAN

MD122—Message Data 122 H'F911 HCAN

MD123—Message Data 123 H'F912 HCAN

MD124—Message Data 124 H'F913 HCAN

MD125—Message Data 125 H'F914 HCAN

MD126—Message Data 126 H'F915 HCAN

MD127—Message Data 127 H'F916 HCAN

MD128—Message Data 128 H'F917 HCAN

MD121

MD122

MD123

MD124

MD125

MD126

MD127

MD128

MSG_DATA_1 (8 bits)

MSG_DATA_2 (8 bits)

MSG_DATA_3 (8 bits)

MSG_DATA_4 (8 bits)

MSG_DATA_5 (8 bits)

MSG_DATA_6 (8 bits)

MSG_DATA_7 (8 bits)

MSG_DATA_8 (8 bits)

MD131—Message Data 131 H'F918 HCAN

MD132—Message Data 132 H'F919 HCAN

MD133—Message Data 133 H'F91A HCAN

MD134—Message Data 134 H'F91B HCAN

MD135—Message Data 135 H'F91C HCAN

MD136—Message Data 136 H'F91D HCAN

MD137—Message Data 137 H'F91E HCAN

MD138—Message Data 138 H'F91F HCAN

MD131

MD132

MD133

MD134

MD135

MD136

MD137

MD138

MSG_DATA_1 (8 bits)

MSG_DATA_2 (8 bits)

MSG_DATA_3 (8 bits)

MSG_DATA_4 (8 bits)

MSG_DATA_5 (8 bits)

MSG_DATA_6 (8 bits)

MSG_DATA_7 (8 bits)

MSG_DATA_8 (8 bits)

947

MD141—Message Data 141 H'F920 HCAN

MD142—Message Data 142 H'F921 HCAN

MD143—Message Data 143 H'F922 HCAN

MD144—Message Data 144 H'F923 HCAN

MD145—Message Data 145 H'F924 HCAN

MD146—Message Data 146 H'F925 HCAN

MD147—Message Data 147 H'F926 HCAN

MD148—Message Data 148 H'F927 HCAN

MD141

MD142

MD143

MD144

MD145

MD146

MD147

MD148

MSG_DATA_1 (8 bits)

MSG_DATA_2 (8 bits)

MSG_DATA_3 (8 bits)

MSG_DATA_4 (8 bits)

MSG_DATA_5 (8 bits)

MSG_DATA_6 (8 bits)

MSG_DATA_7 (8 bits)

MSG_DATA_8 (8 bits)

MD151—Message Data 151 H'F928 HCAN

MD152—Message Data 152 H'F929 HCAN

MD153—Message Data 153 H'F92A HCAN

MD154—Message Data 154 H'F92B HCAN

MD155—Message Data 155 H'F92C HCAN

MD156—Message Data 156 H'F92D HCAN

MD157—Message Data 157 H'F92E HCAN

MD158—Message Data 158 H'F92F HCAN

MD151

MD152

MD153

MD154

MD155

MD156

MD157

MD158

MSG_DATA_1 (8 bits)

MSG_DATA_2 (8 bits)

MSG_DATA_3 (8 bits)

MSG_DATA_4 (8 bits)

MSG_DATA_5 (8 bits)

MSG_DATA_6 (8 bits)

MSG_DATA_7 (8 bits)

MSG_DATA_8 (8 bits)

948

PWCR1—PWM Control Register 1 H'FC00 PWM1

—

R/W

CMF

R/(W)*

CST

R/W

CKS0

R/W

CKS2

R/W

CKS1

R/W

Bit

Initial value

Read/Write

Compare Match Flag

0 [Clearing conditions]

• When 0 is written to CMF after reading CMF = 1

• When the DTC is activated by a compare match interrupt,

and the DISEL bit in the DTC’s MRB register is 0

1 [Setting condition]

When PWCNT = PWCYR

Note: * Only 0 can be written, to clear the flag.

*: Don't care

Clock Select

0 Internal clock: counts on ø/1

Internal clock: counts on ø/2

1Internal clock: counts on ø/40 Internal clock: counts on ø/81

1 Internal clock: counts on ø/16**

Counter Start

0 PWCNT is stopped

1 PWCNT is started

Interrupt Enable

0 Interrupt disabled

1 Interrupt enabled

949

PWOCR1—PWM Output Control Register 1 H'FC02 PWM1

OE1H

R/W

OE1G

R/W

OE1F

R/W

OE1E

R/W

OE1D

R/W

OE1A

R/W

OE1C

R/W

OE1B

R/W

Bit

Initial value

Read/Write

Output Enable

0 PWM output is disabled

1 PWM output is enabled

PWPR1—PWM Polarity Register 1 H'FC04 PWM1

OPS1H

R/W

OPS1G

R/W

OPS1F

R/W

OPS1E

R/W

OPS1D

R/W

OPS1A

R/W

OPS1C

R/W

OPS1B

R/W

Bit

Initial value

Read/Write

Output Polarity Select

0 PWM direct output

1 PWM inverse output

PWCYR1—PWM Cycle Register 1 H'FC06 PWM1

—

Bit

Initial value

Read/Write

Set the PWM conversion cycle

—

R/W

950

PWBFR1A—PWM Buffer Register 1A H'FC08 PWM1

PWBFR1C—PWM Buffer Register 1C H'FC0A PWM1

PWBFR1E—PWM Buffer Register 1E H'FC0C PWM1

PWBFR1G—PWM Buffer Register 1G H'FC0E PWM1

—

Bit

Initial value

Read/Write

Note: When a PWCYR1 compare match occurs, data is transferred from PWBFR1A to PWDTR1A,

from PWBFR1C to PWDTR1C, from PWBFR1E to PWDTR1E, and from PWBFR1G to

PWDTR1G.

—

OTS

R/W

—

DT9

R/W

DT8

R/W

DT7

R/W

DT6

R/W

DT5

R/W

DT4

R/W

DT3

R/W

DT2

R/W

DT1

R/W

DT0

R/W

Duty

The data transferred to bits 9 to 0 in PWDTR1

Output Terminal Select

The data transferred to bit 12 of PWDTR1

Description

PWM1A output selected

OTS

0PWM1B output selected1 PWM1C output selected0

PWM1D output selected

PWM1E output selected

0PWM1F output selected1 PWM1G output selected

PWDTR1A

PWDTR1C

PWDTR1E

PWDTR1G 0

PWM1H output selected1

951

PWCR2—PWM Control Register 2 H'FC10 PWM2

—

R/W

CMF

R/(W)*

CST

R/W

CKS0

R/W

CKS2

R/W

CKS1

R/W

Bit

Initial value

Read/Write

Compare Match Flag

0 [Clearing conditions]

• When 0 is written to CMF after reading CMF = 1

• When the DTC is activated by a compare match interrupt,

and the DISEL bit in the DTC’s MRB register is 0

1 [Setting condition]

When PWCNT = PWCYR

Note: * Only 0 can be written, to clear the flag.

*: Don't care

Clock Select

0 Internal clock: counts on ø/1

Internal clock: counts on ø/2

1Internal clock: counts on ø/40 Internal clock: counts on ø/81

1 Internal clock: counts on ø/16**

Counter Start

0 PWCNT is stopped

1 PWCNT is started

Interrupt Enable

0 Interrupt disabled

1 Interrupt enabled

952

PWOCR2—PWM Output Control Register 2 H'FC12 PWM2

OE2H

R/W

OE2G

R/W

OE2F

R/W

OE2E

R/W

OE2D

R/W

OE2A

R/W

OE2C

R/W

OE2B

R/W

Bit

Initial value

Read/Write

Output Enable

0 PWM output is disabled

1 PWM output is enabled

PWPR2—PWM Polarity Register 2 H'FC14 PWM2

OPS2H

R/W

OPS2G

R/W

OPS2F

R/W

OPS2E

R/W

OPS2D

R/W

OPS2A

R/W

OPS2C

R/W

OPS2B

R/W

Bit

Initial value

Read/Write

Output Polarity Select

0 PWM direct output

1 PWM inverse output

PWCYR2—PWM Cycle Register 2 H'FC16 PWM2

—

Bit

Initial value

Read/Write

Set the PWM conversion cycle

—

R/W

953

PWBFR2A—PWM Buffer Register 2A H'FC18 PWM2

PWBFR2B—PWM Buffer Register 2B H'FC1A PWM2

PWBFR2C—PWM Buffer Register 2C H'FC1C PWM2

PWBFR2D—PWM Buffer Register 2D H'FC1E PWM2

—

Bit

Initial value

Read/Write

Note: When a PWCYR2 compare match occurs, data is transferred from PWBFR2A to PWDTR2A or

PWDTR2E, from PWBFR2B to PWDTR2B or PWDTR2F, from PWBFR2C to PWDTR2C or

PWDTR2G, and from PWBFR2D to PWDTR2D or PWDTR2H.

—

TDS

R/W

—

DT9

R/W

DT8

R/W

DT7

R/W

DT6

R/W

DT5

R/W

DT4

R/W

DT3

R/W

DT2

R/W

DT1

R/W

DT0

R/W

Duty

Comprise the data transferred to bits 9 to 0

in PWDTR2

Transfer Destination Select

Selects the PWDTR2 register to which data is to be transferred

Description

PWDTR2A selected

TDS

0PWDTR2E selected1 PWDTR2B selected0

PWDTR2F selected

PWDTR2C selected

0PWDTR2G selected1 PWDTR2D selected

PWBFR2A

PWBFR2B

PWBFR2C

PWBFR2D 0

PWDTR2H selected1

PHDDR—Port H Data Direction Register H'FC20 Port

PH7DDR

PH6DDR

PH5DDR

PH4DDR

PH3DDR

PH0DDR

PH2DDR

PH1DDR

Bit

Initial value

Read/Write

PJDDR—Port J Data Direction Register H'FC21 Port

PJ7DDR

PJ6DDR

PJ5DDR

PJ4DDR

PJ3DDR

PJ0DDR

PJ2DDR

PJ1DDR

Bit

Initial value

Read/Write

954

PKDDR—Port K Data Direction Register H'FC22 Port

PK7DDR

PK6DDR

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Bit

Initial value

Read/Write

PHDR—Port H Data Register H'FC24 Port

PH7DR

R/W

PH6DR

R/W

PH5DR

R/W

PH4DR

R/W

PH3DR

R/W

PH0DR

R/W

PH2DR

R/W

PH1DR

R/W

Bit

Initial value

Read/Write

PJDR—Port J Data Register H'FC25 Port

PJ7DR

R/W

PJ6DR

R/W

PJ5DR

R/W

PJ4DR

R/W

PJ3DR

R/W

PJ0DR

R/W

PJ2DR

R/W

PJ1DR

R/W

Bit

Initial value

Read/Write

PKDR—Port K Data Register H'FC26 Port

PK7DR

R/W

PK6DR

R/W

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Bit

Initial value

Read/Write

PORTH—Port H Register H'FC28 Port

PH7

—*

PH6

—*

PH5

—*

PH4

—*

PH3

—*

PH0

—*

PH2

—*

PH1

—*

Bit

Initial value

Read/Write

Note: * Determined by the state of PH7 to PH0.

955

PORTJ—Port J Register H'FC29 Port

PJ7

—*

PJ6

—*

PJ5

—*

PJ4

—*

PJ3

—*

PJ0

—*

PJ2

—*

PJ1

—*

Bit

Initial value

Read/Write

Note: * Determined by the state of PJ7 to PJ0.

PORTK—Port K Register H'FC2A Port

PK7

—*

PK6

—*

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Bit

Initial value

Read/Write

Note: * Determined by state of pins PF7 and PF6.

956

LPCR—LCD Port Control Register H'FC30 LCD

DTS1

R/W

DTS0

R/W

CMX

R/W

—

SGS3

R/W

SGS0

R/W

SGS2

R/W

SGS1

R/W

Bit

Initial value

Read/Write

Segment Driver Select (H8S/2646, H8S/2646R, H8S/2645)

Bit 3 Bit 2 Bit 1 Bit 0

SGS3 SGS2 SGS1 SGS0 SEG24 to

SEG17 SEG16 to

SEG13 SEG12 to

SEG9 SEG8 to

SEG5 SEG4 to

SEG1 Notes

Port Port Port Port Port Initial value (external

expansion enabled)

External expansion

not possible

Function of Pins SEG24 to SEG1

0000

SEG Port Port Port Port

1SEG SEG Port Port Port

SEG SEG SEG Port Port

1SEG SEG SEG SEG Port

100

SEG SEG SEG SEG SEG

1Settting

prohibited Settting

prohibited

Settting

prohibited Settting

prohibited

1***

Duty Cycle Select/Common Function Select

Note: COM4 to COM1 function as ports when the setting of SGS3 to SGS0 is 0000 (initial value).

*: Don't care

Bit 7

DTS1

Bit 6

DTS0

Bit 5

CMX

Duty Cycle

Static

1/2 duty

1/3 duty

1/4 duty

COM1

COM4 to COM1

COM2 to COM1

COM4 to COM1

COM3 to COM1

COM4 to COM1

COM4, COM3, and COM2 can be used as ports (Initial value)

COM4, COM3, and COM2 output the same waveform as COM1

COM4 and COM3 can be used as ports

COM4 outputs the same waveform as COM3, and COM2 outputs

the same waveform as COM1

COM4 can be used as a port

Do not use COM4

—

Common Drivers Notes

Note: When using external expansion, set a value of 0000 for SGS3 to SGS0. When the setting of SGS3

to SGS0 is 0000, COM4 to COM1 also function as ports.

Segment Driver Select (H8S/2648, H8S/2648R, H8S/2647)

Bit 3 Bit 2 Bit 1 Bit 0

SGS3 SGS2 SGS1 SGS0 SEG40

SEG33 Notes

Port Initial value (external

expansion enabled)

External expansion

not possible

Function of Pins SEG40 to SEG1

0000

SEG

1SEG

SEG

1SEG

100

SEG

SEG32

SEG29

Port

SEG

SEG28

SEG25

Port

SEG

SEG24

SEG21

Port

SEG

SEG20

SEG17

Port

SEG

SEG16

SEG13

Port

SEG

SEG12

SEG9

Port

SEG

SEG8

SEG5

Port

SEG

SEG4

SEG1

Port

SEG

1**0

*: Don't care

Note: When using external expansion, set a value of 0000 for SGS3 to SGS0. When the setting of SGS3

to SGS0 is 0000, COM4 to COM1 also function as ports.

957

LCR—LCD Control Register H'FC31 LCD

—

PSW

R/W

ACT

R/W

DISP

R/W

CKS3

R/W

CKS0

R/W

CKS2

R/W

CKS1

R/W

Bit

Initial value

Read/Write

Frame Frequency Select

Bit 3

CKS3

SUB

ø/8

ø/16

ø/32

ø/64

ø/128

ø/256

ø/512

ø/1024

128 Hz

64 Hz

32 Hz

4880 Hz

2440 Hz

1220 Hz

610 Hz

305 Hz

152.6 Hz

76.3 Hz

38.1 Hz

Bit 2

CKS2

Bit 1

CKS1

Bit 0

CKS0

Notes: *1 When 1/3 duty is selected, the frame frequency is 4/3 times the

value shown.

*2 This is the frame frequency when ø

SUB

= 32.768 kHz.

*: Don't care

Operating Clock Frame Frequency

ø = 20 MHz

Display Data Control

0 Blank data is displayed

1 LCD RAM data is display

Display Function Activate

0 LCD controller/driver operation halted

1 LCD controller/driver operates

LCD Power Supply Split-Resistance Connection Control

0 LCD power supply split-resistance is disconnected from VCC

1 LCD power supply split-resistance is connected to VCC

958

LCR2—LCD Control Register 2 H'FC32 LCD

LCDAB

R/W

—

Bit

Initial value

Read/Write

A Waveform/B Waveform Switching Control

0 Drive using A waveform

1 Drive using B waveform

LCD—LCD RAM H'FC40 to H'FC53 LCD

MSTPCRD—Module Stop Control Register D H'FC60 System

MSTPD7

R/W

MSTPD6

R/W

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Bit

Initial value

Read/Write

Module Stop

0 Module stop mode is cleared

1 Module stop mode is set

959

SBYCR—Standby Control Register H'FDE4 System

SSBY

R/W

STS2

R/W

STS1

R/W

STS0

R/W

OPE

R/W

—

Bit

Initial value

Read/Write

Output Port Enable

0 In software standby mode, watch mode, and when making a direct

transition, address bus and bus control signals are high-impedance

1 In software standby mode, watch mode, and when making a direct

transition, the output state of the address bus and bus control

signals is retained

Software Standby

0 Shifts to sleep mode when the SLEEP instruction is executed in high-speed mode or

medium-speed mode

Shifts to sub-sleep mode when the SLEEP instruction is executed in sub-active mode

1 Shifts to software standby mode, sub-active mode, and watch mode when the SLEEP

instruction is executed in high-speed mode or medium-speed mode

Shifts to watch mode or high-speed mode when the SLEEP instruction is executed in

sub-active mode

Standby Timer Select 2 to 0

Standby time = 8192 states

Standby time = 16384 states

Standby time = 32768 states

Standby time = 65536 states

Standby time = 131072 states

Standby time = 262144 states

Reserved

Standby time = 16 states

960

SYSCR—System Control Register H'FDE5 System

MACS

R/W

—

INTM1

R/W

INTM0

R/W

NMIEG

R/W

RAME

R/W

—

R/W

—

Bit

Initial value

Read/Write

RAM Enable

0 On-chip RAM is disabled

1 On-chip RAM is enabled

0 Control of interrupts by I bit

Setting prohibited

1 Control of interrupts by I2 to I0 bits and IPR

Setting prohibited

—

NMI Edge Select

0 An interrupt is requested at the falling edge of NMI input

1 An interrupt is requested at the rising edge of NMI input

Interrupt Control Mode 1 and 0

Interrupt

Control Mode

INTM1 INTM0 Description

MAC Saturation

0 Non-saturating calculation for MAC instruction

1 Saturating calculation for MAC instruction

961

SCKCR—System Clock Control Register H'FDE6 System

PSTOP

R/W

—

STCS

R/W

SCK0

R/W

SCK2

R/W

SCK1

R/W

Bit

Initial value

Read/Write

Bus master in high-speed mode

Medium-speed clock is ø/2

Medium-speed clock is ø/4

Medium-speed clock is ø/8

Medium-speed clock is ø/16

Medium-speed clock is ø/32

—

Frequency Multiplication Factor Switching Mode Select

0Specified multiplication factor is valid after transition to software

standby mode, watch mode, or subactive mode

1 Specified multiplication factor is valid immediately after STC

bits are rewritten

ø Clock Output Disable

System Clock Select

—

DDR

PSTOP

Hardware standby mode

Software standby mode,

watch mode, and direct transition

Sleep mode and sub-sleep mode

High-speed mode, medium-speed

mode, and sub-active mode

—

High impedance

Fixed high

ø output

High impedance

Fixed high

962

MDCR—Mode Control Register H'FDE7 System

—

MDS0

—*

MDS2

—*

MDS1

—*

Bit

Initial value

Read/Write

Mode Select 2 to 0

Indicate the input levels at

pins MD2 to MD0

Note: * Determined by pins MD2 to MD0.

MSTPCRA—Module Stop Control Register A H'FDE8 System

MSTPA7

R/W

MSTPA6

R/W

MSTPA5

R/W

MSTPA4

R/W

MSTPA3

R/W

MSTPA0

R/W

MSTPA2

R/W

MSTPA1

R/W

Bit

Initial value

Read/Write

Module Stop

0 Module stop mode is cleared

Module stop mode is set1

MSTPCRB—Module Stop Control Register B H'FDE9 System

MSTPB7

R/W

MSTPB6

R/W

—

MSTPB4

R/W

MSTPB3

R/W

MSTPB0

R/W

MSTPB2

R/W

MSTPB1

R/W

Bit

Initial value

Read/Write

Module Stop

0 Module stop mode is cleared

Module stop mode is set1

963

MSTPCRC—Module Stop Control Register C H'FDEA System

MSTPC7

R/W

—

MSTPC5

R/W

MSTPC4

R/W

MSTPC3

R/W

MSTPC0

R/W

MSTPC2

R/W

MSTPC1

R/W

Bit

Initial value

Read/Write

Module Stop

0 Module stop mode is cleared

Module stop mode is set1

PFCR—Pin Function Control Register H'FDEB System

—

R/W

—

R/W

—

R/W

—

R/W

AE3

1/0

R/W

AE0

1/0

R/W

AE2

1/0

R/W

AE1

R/W

Bit

Initial value

Read/Write

Note: * In expanded mode of on-chip ROM validity, bits AE3 to AE0 are initialized to B'0000.

In expanded mode of on-chip ROM invalidity, bits AE3 to AE0 are initialized to B'1101.

Address pins A0 to A7 are made address outputs by setting the corresponding DDR bits to 1.

Address Output Enable 3 to 0

A8–A23 address output disabled (Initial value*)

A8 address output enabled; A9–A23 address output disabled

A8, A9 address output enabled; A10–A23 address output disabled

A8–A10 address output enabled; A11–A23 address output disabled

A8–A11 address output enabled; A12–A23 address output disabled

A8–A12 address output enabled; A13–A23 address output disabled

A8–A13 address output enabled; A14–A23 address output disabled

A8–A14 address output enabled; A15–A23 address output disabled

A8–A15 address output enabled; A16–A23 address output disabled

A8–A16 address output enabled; A17–A23 address output disabled

A8–A17 address output enabled; A18–A23 address output disabled

A8–A18 address output enabled; A19–A23 address output disabled

A8–A19 address output enabled; A20–A23 address output disabled

A8–A20 address output enabled; A21–A23 address output disabled (Initial value*)

A8–A21 address output enabled; A22, A23 address output disabled

A8–A23 address output enabled

964

LPWRCR—Low-Power Control Register H'FDEC System

DTON

R/W

LSON

R/W

NESEL

R/W

SUBSTP

R/W

RFCUT

R/W

STC0

R/W

—

R/W

STC1

R/W

Bit

Initial value

Read/Write

Frequency Multiplication Factor

0×1

×2

×4

Setting prohibited

Oscillation Circuit Feedback Resistance Control Bit

0 When the main clock is oscillating, sets the feedback

resistance ON. When the main clock is stopped, sets

the feedback resistance OFF

1 Sets the feedback resistance OFF

Subclock Enable

0 Enables subclock generation

Disables subclock generation1

Noise Elimination Sampling Frequency Select

0 Sampling using 1/32 ×ø

Sampling using 1/4 ×ø1

Low-Speed ON Flag

0• When the SLEEP instruction is executed in high-speed mode or medium-speed mode,

operation shifts to sleep mode, software standby mode, or watch mode*

• When the SLEEP instruction is executed in sub-active mode, operation shifts to watch

mode or shifts directly to high-speed mode

• Operation shifts to high-speed mode when watch mode is cancelled

• When the SLEEP instruction is executed in high-speed mode, operation shifts to watch

mode or sub-active mode

• When the SLEEP instruction is executed in sub-active mode, operation shifts to sub-

sleep mode or watch mode

• Operation shifts to sub-active mode when watch mode is cancelled

Direct Transition ON Flag

0• When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts

to sleep mode, software standby mode, or watch mode*

• When the SLEEP instruction is executed in sub-active mode, operation shifts to sub-sleep mode or

watch mode

• When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts

directly to sub-active mode*, or shifts to sleep mode or software standby mode

• When the SLEEP instruction is executed in sub-active mode, operation shifts directly to high-speed

mode, or shifts to sub-sleep mode

Note: * Always set high-speed mode when shifting to watch mode or sub-active mode.

Note: The clock frequency after a

multiplication must not exceed

the maximum operating

frequency of this LSI.

965

BARA—Break Address Register A H'FE00 PBC

BARB—Break Address Register B H'FE04 PBC

Bit

Initial value

Read/Write —

—

Unde-

fined —

—

Unde-

fined R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

Break Address 23 to 0

Specify the channel A or B break address

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

• • •

966

BCRA—Break Control Register A H'FE08 PBC

BCRB—Break Control Register B H'FE09 PBC

Break Condition Select

0Instruction fetch is used as break condition

Data read cycle is used as break condition

Data write cycle is used as break condition

Data read/write cycle is used as break condition

CMFA

R/(W)*

CDA

R/W

BAMRA2

R/W

BAMRA1

R/W

BAMRA0

R/W

BIEA

R/W

CSELA1

R/W

CSELA0

R/W

Bit

Initial value

Read/Write

Break Address Mask Register

0 All BARA bits are unmasked and included in break conditions

BAA0 (lowest bit) is masked, and not included in break conditions

BAA1–0 (lower 2 bits) are masked, and not included in break conditions

BAA2–0 (lower 3 bits) are masked, and not included in break conditions

BAA3–0 (lower 4 bits) are masked, and not included in break conditions

BAA7–0 (lower 8 bits) are masked, and not included in break conditions

BAA11–0 (lower 12 bits) are masked, and not included in break conditions

BAA15–0 (lower 16 bits) are masked, and not included in break conditions

Break Interrupt Enable

0 PC break interrupts are disabled

PC break interrupts are enabled1

CPU Cycle/DTC Cycle Select A

0 PC break is performed when CPU is bus master

PC break is performed when CPU or DTC is bus master1

Condition Match Flag A

0 [Clearing condition]

When 0 is written to CMFA after reading CMFA = 1

[Setting condition]

When a condition set for channel A is satisfied

Notes: BCRB is the channel B break control register.

The bit configuration is the same as for BCRA.

* Only a 0 may be written to this bit to clear the flag.

967

ISCRH—IRQ Sence Control Register H H'FE12 Interrupt Controller

ISCRL—IRQ Sence Control Register L H'FE13 Interrupt Controller

—

R/W

—

R/W

—

R/W

—

R/W

IRQ5SCB

R/W

IRQ4SCA

R/W

IRQ5SCA

R/W

IRQ4SCB

R/W

Bit

Initial value

Read/Write

ISCRH

IRQ3SCB

R/W

IRQ3SCA

R/W

IRQ2SCB

R/W

IRQ2SCA

R/W

IRQ1SCB

R/W

IRQ0SCA

R/W

IRQ1SCA

R/W

IRQ0SCB

R/W

Bit

Initial value

Read/Write

ISCRL

IRQ5 to IRQ0 sense control A and B

Description

IRQ5SCB to

IRQ0SCB IRQ5SCA to

IRQ0SCA

Interrupt request generated at IRQ5 to IRQ0

input at low level

Interrupt request generated at falling edge

of IRQ5 to IRQ0 input

Interrupt request generated at rising edge

of IRQ5 to IRQ0 input

Interrupt request generated at both falling

and rising edges of IRQ5 to IRQ0 input

968

IER—IRQ Enable Register H'FE14 Interrupt Controller

—

R/W

—

R/W

IRQ5E

R/W

IRQ4E

R/W

IRQ3E

R/W

IRQ0E

R/W

IRQ2E

R/W

IRQ1E

R/W

Bit

Initial value

Read/Write

IRQ5 to IRQ0 Enable

(n = 5 to 0)

0 IRQn interrupts disabled

IRQn interrupts enabled1

ISR—IRQ Status Register H'FE15 Interrupt Controller

—

R/(W)*

—

R/(W)*

IRQ5F

R/(W)*

IRQ4F

R/(W)*

IRQ3F

R/(W)*

IRQ0F

R/(W)*

IRQ2F

R/(W)*

IRQ1F

R/(W)*

Bit

Initial value

Read/Write

IRQ5 to IRQ0 Flags

0 [Clearing conditions]

• Cleared by reading IRQnF when IRQnF = 1, then writing 0 to IRQnF flag

• When interrupt exception handling is executed while low-level detection

is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high

• When IRQn interrupt exception handling is executed while falling, rising,

or both-edge detection is set (IRQnSCB = 1 or IRQnSCA = 1)

• When the DTC is activated by an IRQn interrupt, and the DISEL bit in

MRB of the DTC is cleared to 0

1 [Setting conditions]

• When IRQn input goes low when low-level detection is set

(IRQnSCB = IRQnSCA = 0)

• When a falling edge occurs in IRQn input when falling edge detection is

set (IRQnSCB = 0, IRQnSCA = 1)

• When a rising edge occurs in IRQn input when rising edge detection is

set (IRQnSCB = 1, IRQnSCA = 0)

• When a falling or rising edge occurs in IRQn input when both-edge

detection is set (IRQnSCB = IRQnSCA = 1)

Note: * Only 0 can be written, to clear the flag.

(n = 5 to 0)

969

DTCER—DTC Enable Register A

DTCER—DTC Enable Register B

DTCER—DTC Enable Register C

DTCER—DTC Enable Register D

DTCER—DTC Enable Register E

DTCER—DTC Enable Register F

DTCER—DTC Enable Register G

DTCER—DTC Enable Register I

H'FE16

H'FE17

H'FE18

H'FE19

H'FE1A

H'FE1B

H'FE1C

H'FE1E

DTC

DTCE7

R/W

DTCE6

R/W

DTCE5

R/W

DTCE4

R/W

DTCE3

R/W

DTCE0

R/W

DTCE2

R/W

DTCE1

R/W

Bit

Initial value

Read/Write

DTC Activation Enable

0 DTC activation by interrupt is disabled

[Clearing conditions]

• When the DISEL bit is 1 and the data transfer has ended

• When the specified number of transfers have ended

1 DTC activation by interrupt is enabled

[Holding condition]

When the DISEL bit is 0 and the specified number of transfers

have not ended

970

DTVECR—DTC Vector Register H'FE1F DTC

SWDTE

R/(W)*1

DTVEC6

R/W*2

DTVEC5

R/W*2

DTVEC4

R/W*2

DTVEC3

R/W*2

DTVEC0

R/W*2

DTVEC2

R/W*2

DTVEC1

R/W*2

Bit

Initial value

Read/Write

Notes:

Specify a number for DTC software activation

DTC Software Activation Enable

0 DTC software activation is disabled

[Clearing condition]

• When the DISEL bit is 0 and the specified number of transfers

have not ended

• When 0s written to the DISEL bit after a software-activated data

transfer end interrupt (SWDTEND) request has been sent to

the CPU

1 DTC software activation is enabled

[Holding conditions]

• When the DISEL bit is 1 and data transfer has ended

• When the specified number of transfers have ended

• During data transfer due to software activation

*1 Only 1 can be written to the SWDTE bit.

*2 Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0.

971

PCR—PPG Output Control Register H'FE26 PPG

G3CMS1

R/W

G3CMS0

R/W

G2CMS1

R/W

G2CMS0

R/W

G1CMS1

R/W

G0CMS0

R/W

G1CMS0

R/W

G0CMS1

R/W

Bit

Initial value

Read/Write

Group 0 Compare Match Select

Compare match in TPU channel 0

Compare match in TPU channel 1

Compare match in TPU channel 2

Compare match in TPU channel 3

Group 1 Compare Match Select

Compare match in TPU channel 0

Compare match in TPU channel 1

Compare match in TPU channel 2

Compare match in TPU channel 3

Group 2 Compare Match Select

Compare match in TPU channel 0

Compare match in TPU channel 1

Compare match in TPU channel 2

Compare match in TPU channel 3

Group 3 Compare Match Select

Compare match in TPU channel 0

Compare match in TPU channel 1

Compare match in TPU channel 2

Compare match in TPU channel 3

972

PMR—PPG Output Mode Register H'FE27 PPG

G3INV

R/W

G2INV

R/W

G1INV

R/W

G0INV

R/W

G3NOV

R/W

G0NOV

R/W

G2NOV

R/W

G1NOV

R/W

Bit

Initial value

Read/Write

Group 0 Non-Overlap

0 Normal operation in pulse output group 0 (output

values updated at compare match A in the selected

TPU channel)

Non-overlapping operation in pulse output group 0

(independent 1 and 0 output at compare match A

or B in the selected TPU channel)

Group 1 Non-Overlap

0 Normal operation in pulse output group 1 (output

values updated at compare match A in the selected

TPU channel)

Non-overlapping operation in pulse output group 1

(independent 1 and 0 output at compare match A

or B in the selected TPU channel)

Group 2 Non-Overlap

0 Normal operation in pulse output group 2 (output

values updated at compare match A in the selected

TPU channel)

Non-overlapping operation in pulse output group 2

(independent 1 and 0 output at compare match A

or B in the selected TPU channel)

Group 3 Non-Overlap

0 Normal operation in pulse output group 3 (output

values updated at compare match A in the selected

TPU channel)

Non-overlapping operation in pulse output group 3

(independent 1 and 0 output at compare match A

or B in the selected TPU channel)

Group 3 Inversion

0 Inverted output for pulse output group 3 (low-level output at pin for a 1 in PODRH)

Direct output for pulse output group 3 (high-level output at pin for a 1 in PODRH)

Group 2 Inversion

0 Inverted output for pulse output group 2 (low-level output at pin for a 1 in PODRH)

Direct output for pulse output group 2 (high-level output at pin for a 1 in PODRH)

Group 1 Inversion

0 Inverted output for pulse output group 1 (low-level output at pin for a 1 in PODRL)

Direct output for pulse output group 1 (high-level output at pin for a 1 in PODRL)

Group 0 Inversion

0 Inverted output for pulse output group 0 (low-level output at pin for a 1 in PODRL)

Direct output for pulse output group 0 (high-level output at pin for a 1 in PODRL)

973

NDERH—Next Data Enable Register H H'FE28 PPG

NDER15

R/W

NDER14

R/W

NDER13

R/W

NDER12

R/W

NDER11

R/W

NDER8

R/W

NDER10

R/W

NDER9

R/W

Bit

Initial value

Read/Write

Next Data Enable

0 Pulse outputs PO15 to PO8 are disabled

(NDR15 to NDR8 are not transferred to POD15 to POD8)

Pulse outputs PO15 to PO8 are enabled

(NDR15 to NDR8 are transferred to POD15 to POD8)

NDERL—Next Data Enable Register L H'FE29 PPG

NDER7

R/W

NDER6

R/W

NDER5

R/W

NDER4

R/W

NDER3

R/W

NDER0

R/W

NDER2

R/W

NDER1

R/W

Bit

Initial value

Read/Write

Next Data Enable

0 Pulse outputs PO7 to PO0 are disabled

(NDR7 to NDR0 are not transferred to POD7 to POD0

Pulse outputs PO7 to PO0 are enabled

(NDR7 to NDR0 are transferred to POD7 to POD0)

PODRH—Output Data Register H H'FE2A PPG

POD15

R/(W)*

POD14

R/(W)*

POD13

R/(W)*

POD12

R/(W)*

POD11

R/(W)*

POD8

R/(W)*

POD10

R/(W)*

POD9

R/(W)*

Bit

Initial value

Read/Write

Note: * A bit that has been set for pulse output by NDER is read-only.

974

PODRL—Output Data Register L H'FE2B PPG

POD7

R/(W)*

POD6

R/(W)*

POD5

R/(W)*

POD4

R/(W)*

POD3

R/(W)*

POD0

R/(W)*

POD2

R/(W)*

POD1

R/(W)*

Bit

Initial value

Read/Write

Note: * A bit that has been set for pulse output by NDER is read-only.

975

NDRH—Next Data Register H H'FE2C, H'FE2E PPG

NDR15

R/W

NDR14

R/W

NDR13

R/W

NDR12

R/W

NDR11

R/W

NDR8

R/W

NDR10

R/W

NDR9

R/W

Bit

Initial value

Read/Write

Address H'FE2C

—

Bit

Initial value

Read/Write

Address H'FE2E

Same Trigger for Pulse Output Groups

NDR15

R/W

NDR14

R/W

NDR13

R/W

NDR12

R/W

—

Bit

Initial value

Read/Write

Address H'FE2C

—

NDR11

R/W

NDR8

R/W

NDR10

R/W

NDR9

R/W

Bit

Initial value

Read/Write

Address H'FE2E

Different Triggers for Pulse Output Groups

Note: For details, see section 11.2.4, Notes on NDR Access.

976

NDRL—Next Data Register L H'FE2D, H'FE2F PPG

NDR7

R/W

NDR6

R/W

NDR5

R/W

NDR4

R/W

NDR3

R/W

NDR0

R/W

NDR2

R/W

NDR1

R/W

Bit

Initial value

Read/Write

Address H'FE2D

—

Bit

Initial value

Read/Write

Address H'FE2F

Same Trigger for Pulse Output Groups

NDR7

R/W

NDR6

R/W

NDR5

R/W

NDR4

R/W

—

Bit

Initial value

Read/Write

Address H'FE2D

—

NDR3

R/W

NDR0

R/W

NDR2

R/W

NDR1

R/W

Bit

Initial value

Read/Write

Address H'FE2F

Different Triggers for Pulse Output Groups

Note: For details, see section 11.2.4, Notes on NDR Access.

977

P1DDR—Port 1 Data Direction Register H'FE30 Port

P17DDR

P16DDR

P15DDR

P14DDR

P13DDR

P10DDR

P12DDR

P11DDR

Bit

Initial value

Read/Write

Specify input or output for each of the pins in port 1

P2DDR—Port 2 Data Direction Register H'FE31 Port

P27DDR

P26DDR

P25DDR

P24DDR

P23DDR

P20DDR

P22DDR

P21DDR

Bit

Initial value

Read/Write

Specify input or output for each of the pins in port 2

P3DDR—Port 3 Data Direction Register H'FE32 Port

P37DDR

P36DDR

P35DDR

P34DDR

P33DDR

P30DDR

P32DDR

P31DDR

Bit

Initial value

Read/Write

Specify input or output for each of the pins in port 3

P5DDR—Port 5 Data Direction Register H'FE34 Port

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

P50DDR

P52DDR

P51DDR

Bit

Initial value

Read/Write

Specify input or output for

each of the pins in port 5.

978

PADDR—Port A Data Direction Register H'FE39 Port

PA7DDR

PA6DDR

PA5DDR

PA4DDR

PA3DDR

PA0DDR

PA2DDR

PA1DDR

Bit

Initial value

Read/Write

Specify input or output for each of the pins in port A

PBDDR—Port B Data Direction Register H'FE3A Port

PB7DDR

PB6DDR

PB5DDR

PB4DDR

PB3DDR

PB0DDR

PB2DDR

PB1DDR

Bit

Initial value

Read/Write

Specify input or output for each of the pins in port B

PCDDR—Port C Data Direction Register H'FE3B Port

PC7DDR

PC6DDR

PC5DDR

PC4DDR

PC3DDR

PC0DDR

PC2DDR

PC1DDR

Bit

Initial value

Read/Write

Specify input or output for each of the pins in port C

PDDDR—Port D Data Direction Register H'FE3C Port

PD7DDR

PD6DDR

PD5DDR

PD4DDR

PD3DDR

PD0DDR

PD2DDR

PD1DDR

Bit

Initial value

Read/Write

Specify input or output for each of the pins in port D

979

PEDDR—Port E Data Direction Register H'FE3D Port

PE7DDR

PE6DDR

PE5DDR

PE4DDR

PE3DDR

PE0DDR

PE2DDR

PE1DDR

Bit

Initial value

Read/Write

Specify input or output for each of the pins in port E

PFDDR—Port F Data Direction Register H'FE3E Port

PF7DDR

PF6DDR

PF5DDR

PF4DDR

PF3DDR

PF0DDR

PF2DDR

—

Undefined

—

Undefined

—

Bit

Modes 4, 5, 6

Initial value

Read/Write

Mode 7

Initial value

Read/Write

Specify input or output for each of the pins in port F

PAPCR—Port A MOS Pull-Up Control Register H'FE40 Port

PA7PCR

R/W

PA6PCR

R/W

PA5PCR

R/W

PA4PCR

R/W

PA3PCR

R/W

PA0PCR

R/W

PA2PCR

R/W

PA1PCR

R/W

Bit

Initial value

Read/Write

Control the MOS input pull-up function incorporated into port A

PBPCR—Port B MOS Pull-Up Control Register H'FE41 Port

PB7PCR

R/W

PB6PCR

R/W

PB5PCR

R/W

PB4PCR

R/W

PB3PCR

R/W

PB0PCR

R/W

PB2PCR

R/W

PB1PCR

R/W

Bit

Initial value

Read/Write

Control the MOS input pull-up function incorporated into port B

980

PCPCR—Port C MOS Pull-Up Control Register H'FE42 Port

PC7PCR

R/W

PC6PCR

R/W

PC5PCR

R/W

PC4PCR

R/W

PC3PCR

R/W

PC0PCR

R/W

PC2PCR

R/W

PC1PCR

R/W

Bit

Initial value

Read/Write

Control the MOS input pull-up function incorporated into port C

PDPCR—Port D MOS Pull-Up Control Register H'FE43 Port

PD7PCR

R/W

PD6PCR

R/W

PD5PCR

R/W

PD4PCR

R/W

PD3PCR

R/W

PD0PCR

R/W

PD2PCR

R/W

PD1PCR

R/W

Bit

Initial value

Read/Write

Control the MOS input pull-up function incorporated into port D

PEPCR—Port E MOS Pull-Up Control Register H'FE44 Port

PE7PCR

R/W

PE6PCR

R/W

PE5PCR

R/W

PE4PCR

R/W

PE3PCR

R/W

PE0PCR

R/W

PE2PCR

R/W

PE1PCR

R/W

Bit

Initial value

Read/Write

Control the MOS input pull-up function incorporated into port E

P3ODR—Port 3 Open Drain Control Register H'FE46 Port

P37ODR

R/W

P36ODR

R/W

P35ODR

R/W

P34ODR

R/W

P33ODR

R/W

P30ODR

R/W

P32ODR

R/W

P31ODR

R/W

Bit

Initial value

Read/Write

Control whether PMOS is on or off for each port 3 pin

981

PAODR—Port A Open Drain Control Register H'FE47 Port

PA7ODR

R/W

PA6ODR

R/W

PA5ODR

R/W

PA4ODR

R/W

PA3ODR

R/W

PA0ODR

R/W

PA2ODR

R/W

PA1ODR

R/W

Bit

Initial value

Read/Write

Control whether PMOS is on or off for each port A pin

PBODR—Port B Open Drain Control Register H'FE48 Port

PB7ODR

R/W

PB6ODR

R/W

PB5ODR

R/W

PB4ODR

R/W

PB3ODR

R/W

PB0ODR

R/W

PB2ODR

R/W

PB1ODR

R/W

Bit

Initial value

Read/Write

Control whether PMOS is on or off for each port B pin

PCODR—Port C Open Drain Control Register H'FE49 Port

PC7ODR

R/W

PC6ODR

R/W

PC5ODR

R/W

PC4ODR

R/W

PC3ODR

R/W

PC0ODR

R/W

PC2ODR

R/W

PC1ODR

R/W

Bit

Initial value

Read/Write

Control whether PMOS is on or off for each port C pin

982

TCR3—Timer Control Register 3 H'FE80 TPU3

CCLR2

R/W

CCLR1

R/W

CCLR0

R/W

CKEG1

R/W

CKEG0

R/W

TPSC0

R/W

TPSC2

R/W

TPSC1

R/W

Bit

Initial value

Read/Write

Time Prescaler

0 Internal clock: counts on ø/1

Internal clock: counts on ø/4

Internal clock: counts on ø/16

Internal clock: counts on ø/64

External clock: counts on TCLKA pin input

Internal clock: counts on ø/1024

Internal clock: counts on ø/256

Internal clock: counts on ø/4096

Counter Clear

0 TCNT clearing disabled

TCNT cleared by TGRA compare match/input capture

TCNT cleared by TGRB compare match/input capture

TCNT cleared by counter clearing for another channel

performing synchronous clearing/synchronous operation*1

TCNT clearing disabled

TCNT cleared by TGRC compare match/input capture*2

TCNT cleared by TGRD compare match/input capture*2

TCNT cleared by counter clearing for another channel

performing synchronous clearing/synchronous operation*1

Notes: *1

Synchronous operation setting is performed by setting the

SYNC bit in TSYR to 1.

When TGRC or TGRD is used as a buffer register, TCNT is

not cleared because the buffer register setting has priority,

and compare match/input capture does not occur.

Clock Edge

Count at rising edge

Count at falling edge

Count at both edges

—

Note: Internal clock edge selection is valid when the input clock

is ø/4 or slower. This setting is ignored if the input clock is ø/1,

or when overflow/underflow of another channel is selected.

983

TMDR3—Timer Mode Register 3 H'FE81 TPU3

—

BFB

R/W

BFA

R/W

MD3

R/W

MD0

R/W

MD2

R/W

MD1

R/W

Bit

Initial value

Read/Write

Buffer Operation A

*: Don't care

0 TGRA operates normally

TGRA and TGRC used together for buffer operation1

Buffer Operation B

0 TGRB operates normally

TGRB and TGRD used together for buffer operation1

Notes: 1.

MD3 is a reserved bit. In a write,

it should always be written with 0.

Phase counting mode cannot be

set for channel 3. In this case, 0

should always be written to MD2.

Mode

0Normal operation

Reserved

PWM mode 1

PWM mode 2

Phase counting mode 1

Phase counting mode 2

Phase counting mode 3

Phase counting mode 4

—

984

TIOR3H—Timer I/O Control Register 3H H'FE82 TPU3

IOB3

R/W

IOB2

R/W

IOB1

R/W

IOB0

R/W

IOA3

R/W

IOA0

R/W

IOA2

R/W

IOA1

R/W

Bit

Initial value

Read/Write

*: Don't care

TGR3A I/O Control

0 output at compare match

1 output at compare match

Toggle output at compare match

0 output at compare match

1 output at compare match

Toggle output at compare match

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

Input capture at TCNT4 count-up/

count-down

TGR3A is

output

compare

TGR3A is

input

capture

Output disabled

Initial output is 0

output

Output disabled

Initial output is 1

output

Capture input

source is

TIOCA3 pin

Capture input

source is channel

4/count clock

*: Don't care

TGR3B I/O Control

0 output at compare match

1 output at compare match

Toggle output at compare match

0 output at compare match

1 output at compare match

Toggle output at compare match

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

Input capture at TCNT4 count-up/

count-down*1

TGR3B is

output

compare

TGR3B is

input

capture

Output disabled

Initial output is 0

output

Output disabled

Initial output is 1

output

Capture input

source is

TIOCB3 pin

Capture input

source is channel

4/count clock

Note: *1 When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and ø/1 is used as the

TCNT4 count clock, this setting is invalid and input capture is not generated.

985

TIOR3L—Timer I/O Control Register 3L H'FE83 TPU3

IOD3

R/W

IOD2

R/W

IOD1

R/W

IOD0

R/W

IOC3

R/W

IOC0

R/W

IOC2

R/W

IOC1

R/W

Bit

Initial value

Read/Write

*: Don't care

TGR3C I/O Control

0 output at compare match

1 output at compare match

Toggle output at compare match

0 output at compare match

1 output at compare match

Toggle output at compare match

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

Input capture at TCNT4 count-up/

count-down

TGR3C is

output

compare

TGR3C is

input

capture

Output disabled

Initial output is 0

output

Output disabled

Initial output is 1

output

Capture input

source is

TIOCC3 pin

Capture input

source is channel

4/count clock

*: Don't care

TGR3D I/O Control

0 output at compare match

1 output at compare match

Toggle output at compare match

0 output at compare match

1 output at compare match

Toggle output at compare match

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

Input capture at TCNT4 count-up/

count-down*1

TGR3D is

output

compare

TGR3D is

input

capture

Output disabled

Initial output is 0

output

Output disabled

Initial output is 1

output

Capture input

source is

TIOCD3 pin

Capture input

source is channel

4/count clock

Notes: *1

When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and ø/1 is used as the

TCNT4 count clock, this setting is invalid and input capture is not generated.

When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register,

this setting is invalid and input capture/output compare is not generated.

Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the

Note: *1 When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register,

this setting is invalid and input capture/output compare is not generated.

986

TIER3—Timer Interrupt Enable Register 3 H'FE84 TPU3

TTGE

R/W

—

TCIEV

R/W

TGIED

R/W

TGIEA

R/W

TGIEC

R/W

TGIEB

R/W

Bit

Initial value

Read/Write

TGR Interrupt Enable A

0 Interrupt requests (TGIA) by TGFA bit disabled

Interrupt requests (TGIA) by TGFA bit enabled1

TGR Interrupt Enable B

0 Interrupt requests (TGIB) by TGFB bit disabled

Interrupt requests (TGIB) by TGFB bit enabled1

TGR Interrupt Enable C

0 Interrupt requests (TGIC) by TGFC bit disabled

Interrupt requests (TGIC) by TGFC bit enabled1

TGR Interrupt Enable D

0 Interrupt requests (TGID) by TGFD bit disabled

Interrupt requests (TGID) by TGFD bit enabled1

Overflow Interrupt Enable

0 Interrupt requests (TCIV) by TCFV disabled

Interrupt requests (TCIV) by TCFV enabled1

A/D Conversion Start Request Enable

0 A/D conversion start request generation disabled

A/D conversion start request generation enabled1

987

TSR3—Timer Status Register 3 H'FE85 TPU3

—

TCFV

R/(W)*

TGFD

R/(W)*

TGFA

R/(W)*

TGFC

R/(W)*

TGFB

R/(W)*

Bit

Initial value

Read/Write

Input Capture/Output Compare Flag A

0 [Clearing conditions]

• When DTC is activated by TGIA interrupt while DISEL bit

of MRB in DTC is 0

• When 0 is written to TGFA after reading TGFA = 1

1 [Setting conditions]

• When TCNT = TGRA while TGRA is functioning as output

compare register

• When TCNT value is transferred to TGRA by input capture

signal while TGRA is functioning as input capture register

Input Capture/Output Compare Flag B

0 [Clearing conditions]

• When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0

• When 0 is written to TGFB after reading TGFB = 1

1 [Setting conditions]

• When TCNT = TGRB while TGRB is functioning as output compare register

• When TCNT value is transferred to TGRB by input capture signal while

TGRB is functioning as input capture register

Input Capture/Output Compare Flag C

0 [Clearing conditions]

• When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0

• When 0 is written to TGFC after reading TGFC = 1

1 [Setting conditions]

• When TCNT = TGRC while TGRC is functioning as output compare register

• When TCNT value is transferred to TGRC by input capture signal while

TGRC is functioning as input capture register

Input Capture/Output Compare Flag D

0 [Clearing conditions]

• When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0

• When 0 is written to TGFD after reading TGFD = 1

1 [Setting conditions]

• When TCNT = TGRD while TGRD is functioning as output compare register

• When TCNT value is transferred to TGRD by input capture signal while

TGRD is functioning as input capture register

Overflow Flag

0 [Clearing condition]

When 0 is written to TCFV after reading TCFV = 1

1 [Setting condition]

When the TCNT value overflows (changes from H'FFFF to H'0000)

Note: * Can only be written with 0 for flag clearing.

988

TCNT3—Timer Counter 3 H'FE86 TPU3

R/W

Bit

Initial value

Read/Write

R/W

Up-counter

TGR3A—Timer General Register 3A H'FE88 TPU3

TGR3B—Timer General Register 3B H'FE8A TPU3

TGR3C—Timer General Register 3C H'FE8C TPU3

TGR3D—Timer General Register 3D H'FE8E TPU3

R/W

Bit

Initial value

Read/Write

R/W

989

TCR4—Timer Control Register 4 H'FE90 TPU4

Bit

Initial value

Read/Write

Clock Edge

Count at rising edge

Count at falling edge

Count at both edges

—

Time Prescaler

0 Internal clock: counts on ø/1

Internal clock: counts on ø/4

Internal clock: counts on ø/16

Internal clock: counts on ø/64

External clock: counts on TCLKA pin input

External clock: counts on TCLKC pin input

Internal clock: counts on ø/1024

Counts on TCNT5 overflow/underflow

Counter Clear

TCNT clearing disabled

TCNT cleared by TGRA compare match/input capture

TCNT cleared by TGRB compare match/input capture

TCNT cleared by counter clearing for another channel

performing synchronous clearing/synchronous operation*

Note: *Synchronous operation setting is performed by setting the

SYNC bit in TSYR to 1.

Note: Bit 7 is reserved in channel 4.

It is always read as 0 and cannot be modified.

Note: This setting is ignored when channel 4 is in phase

counting mode.

Note: Internal clock edge selection is valid when the input

clock is ø/4 or slower. This setting is ignored if the

input clock is ø/1, or when overflow/underflow of

another channel is selected.

—

CCLR1

R/W

CCLR0

R/W

CKEG1

R/W

CKEG0

R/W

TPSC0

R/W

TPSC2

R/W

TPSC1

R/W

990

TMDR4—Timer Mode Register 4 H'FE91 TPU4

—

MD3

R/W

MD0

R/W

MD2

R/W

MD1

R/W

Bit

Initial value

Read/Write

*: Don't care

Note: MD3 is a reserved bit. In a write, it

should always be written with 0.

Mode

0Normal operation

Reserved

PWM mode 1

PWM mode 2

Phase counting mode 1

Phase counting mode 2

Phase counting mode 3

Phase counting mode 4

—

991

TIOR4—Timer I/O Control Register 4 H'FE92 TPU4

IOB3

R/W

IOB2

R/W

IOB1

R/W

IOB0

R/W

IOA3

R/W

IOA0

R/W

IOA2

R/W

IOA1

R/W

Bit

Initial value

Read/Write

*: Don't care

TGR4A I/O Control

0 output at compare match

1 output at compare match

Toggle output at compare match

0 output at compare match

1 output at compare match

Toggle output at compare match

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

Input capture at generation of TGR3A

compare match/input capture

TGR4A is

output

compare

TGR4A is

input

capture

Output disabled

Initial output is 0

output

Output disabled

Initial output is 1

output

Capture input

source is

TIOCA4 pin

Capture input

source is TGR3A

compare match/

input capture

*: Don't care

TGR4B I/O Control

0 output at compare match

1 output at compare match

Toggle output at compare match

0 output at compare match

1 output at compare match

Toggle output at compare match

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

Input capture at generation of TGR3C

compare match/input capture

TGR4B is

output

compare

TGR4B is

input

capture

Output disabled

Initial output is 0

output

Output disabled

Initial output is 1

output

Capture input

source is

TIOCB4 pin

Capture input

source is TGR3C

compare match/

input capture

992

TIER4—Timer Interrupt Enable Register 4 H'FE94 TPU4

TTGE

R/W

—

TCIEU

R/W

TCIEV

R/W

—

TGIEA

R/W

—

TGIEB

R/W

Bit

Initial value

Read/Write

TGR Interrupt Enable A

0 Interrupt requests (TGIA) by TGFA bit disabled

Interrupt requests (TGIA) by TGFA bit enabled1

TGR Interrupt Enable B

0 Interrupt requests (TGIB) by TGFB bit disabled

Interrupt requests (TGIB) by TGFB bit enabled1

Overflow Interrupt Enable

0 Interrupt requests (TCIV) by TCFV disabled

Interrupt requests (TCIV) by TCFV enabled1

Underflow Interrupt Enable

0 Interrupt requests (TCIU) by TCFU disabled

Interrupt requests (TCIU) by TCFU enabled1

A/D Conversion Start Request Enable

0 A/D conversion start request generation disabled

A/D conversion start request generation enabled1

993

TSR4—Timer Status Register 4 H'FE95 TPU4

TCFD

—

TCFU

R/(W)*

TCFV

R/(W)*

—

TGFA

R/(W)*

—

TGFB

R/(W)*

Bit

Initial value

Read/Write

Input Capture/Output Compare Flag A

0 [Clearing conditions]

• When DTC is activated by TGIA interrupt while DISEL bit

of MRB in DTC is 0

• When 0 is written to TGFA after reading TGFA = 1

1 [Setting conditions]

• When TCNT = TGRA while TGRA is functioning as output

compare register

• When TCNT value is transferred to TGRA by input capture

signal while TGRA is functioning as input capture register

Input Capture/Output Compare Flag B

0 [Clearing conditions]

• When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0

• When 0 is written to TGFB after reading TGFB = 1

1 [Setting conditions]

• When TCNT = TGRB while TGRB is functioning as output compare register

• When TCNT value is transferred to TGRB by input capture signal while

TGRB is functioning as input capture register

Overflow Flag

0 [Clearing condition]

When 0 is written to TCFV after reading TCFV = 1

1 [Setting condition]

When the TCNT value overflows (changes from H'FFFF to H'0000)

Underflow Flag

0 [Clearing condition]

When 0 is written to TCFU after reading TCFU = 1

1 [Setting condition]

When the TCNT value underflows (changes from H'0000 to H'FFFF)

Count Direction Flag

0 TCNT counts down

TCNT counts up

Note: * Can only be written with 0 for flag clearing.

994

TCNT4—Timer Counter 4 H'FE96 TPU4

R/W

Bit

Initial value

Read/Write

R/W

Up/down-counter*

Note: * These counters can be used as up/down-counters only in phase counting mode or

when counting overflow/underflow on another channel. In other cases they function

as up-counters.

TGR4A—Timer General Register 4A H'FE98 TPU4

TGR4B—Timer General Register 4B H'FE9A TPU4

R/W

Bit

Initial value

Read/Write

R/W

995

TCR5—Timer Control Register 5 H'FEA0 TPU5

Bit

Initial value

Read/Write

Time Prescaler

0 Internal clock: counts on ø/1

Internal clock: counts on ø/4

Internal clock: counts on ø/16

Internal clock: counts on ø/64

External clock: counts on TCLKA pin input

External clock: counts on TCLKC pin input

Internal clock: counts on ø/256

External clock: counts on TCLKD pin input

Note: This setting is ignored when channel 5 is in phase

counting mode.

—

CCLR1

R/W

CCLR0

R/W

CKEG1

R/W

CKEG0

R/W

TPSC0

R/W

TPSC2

R/W

TPSC1

R/W

Clock Edge

Count at rising edge

Count at falling edge

Count at both edges

—

Counter Clear

TCNT clearing disabled

TCNT cleared by TGRA compare match/input capture

TCNT cleared by TGRB compare match/input capture

TCNT cleared by counter clearing for another channel

performing synchronous clearing/synchronous operation*

Note: *Synchronous operation setting is performed by setting the

SYNC bit in TSYR to 1.

Note: Internal clock edge selection is valid when the input

clock is ø/4 or slower. This setting is ignored if the

input clock is ø/1, or when overflow/underflow of

another channel is selected.

Note: Bit 7 is reserved in channel 5.

It is always read as 0 and cannot be modified.

996

TMDR5—Timer Mode Register 5 H'FEA1 TPU5

—

MD3

R/W

MD0

R/W

MD2

R/W

MD1

R/W

Bit

Initial value

Read/Write

*: Don't care

Note: MD3 is a reserved bit. In a write, it

should always be written with 0.

Mode

0Normal operation

Reserved

PWM mode 1

PWM mode 2

Phase counting mode 1

Phase counting mode 2

Phase counting mode 3

Phase counting mode 4

—

997

TIOR5—Timer I/O Control Register 5 H'FEA2 TPU5

IOB3

R/W

IOB2

R/W

IOB1

R/W

IOB0

R/W

IOA3

R/W

IOA0

R/W

IOA2

R/W

IOA1

R/W

Bit

Initial value

Read/Write

*: Don't care

TGR5A I/O Control

0 output at compare match

1 output at compare match

Toggle output at compare match

0 output at compare match

1 output at compare match

Toggle output at compare match

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

TGR5A is

output

compare

TGR5A is

input

capture

Output disabled

Initial output is 0

output

Output disabled

Initial output is 1

output

Capture input

source is

TIOCA5 pin

*: Don't care

TGR5B I/O Control

0 output at compare match

1 output at compare match

Toggle output at compare match

0 output at compare match

1 output at compare match

Toggle output at compare match

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

TGR5B is

output

compare

TGR5B is

input

capture

Output disabled

Initial output is 0

output

Output disabled

Initial output is 1

output

Capture input

source is

TIOCB5 pin

998

TIER5—Timer Interrupt Enable Register 5 H'FEA4 TPU5

TTGE

R/W

—

TCIEU

R/W

TCIEV

R/W

—

TGIEA

R/W

—

TGIEB

R/W

Bit

Initial value

Read/Write

TGR Interrupt Enable A

0 Interrupt requests (TGIA) by TGFA bit disabled

Interrupt requests (TGIA) by TGFA bit enabled1

TGR Interrupt Enable B

0 Interrupt requests (TGIB) by TGFB bit disabled

Interrupt requests (TGIB) by TGFB bit enabled1

Overflow Interrupt Enable

0 Interrupt requests (TCIV) by TCFV disabled

Interrupt requests (TCIV) by TCFV enabled1

Underflow Interrupt Enable

0 Interrupt requests (TCIU) by TCFU disabled

Interrupt requests (TCIU) by TCFU enabled1

A/D Conversion Start Request Enable

0 A/D conversion start request generation disabled

A/D conversion start request generation enabled1

999

TSR5—Timer Status Register 5 H'FEA5 TPU5

TCFD

—

TCFU

R/(W)*

TCFV

R/(W)*

—

TGFA

R/(W)*

—

TGFB

R/(W)*

Bit

Initial value

Read/Write

Input Capture/Output Compare Flag A

0 [Clearing conditions]

• When DTC is activated by TGIA interrupt while DISEL bit

of MRB in DTC is 0

• When 0 is written to TGFA after reading TGFA = 1

1 [Setting conditions]

• When TCNT = TGRA while TGRA is functioning as output

compare register

• When TCNT value is transferred to TGRA by input capture

signal while TGRA is functioning as input capture register

Input Capture/Output Compare Flag B

0 [Clearing conditions]

• When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0

• When 0 is written to TGFB after reading TGFB = 1

1 [Setting conditions]

• When TCNT = TGRB while TGRB is functioning as output compare register

• When TCNT value is transferred to TGRB by input capture signal while

TGRB is functioning as input capture register

Overflow Flag

0 [Clearing condition]

When 0 is written to TCFV after reading TCFV = 1

1 [Setting condition]

When the TCNT value overflows (changes from H'FFFF to H'0000)

Underflow Flag

0 [Clearing condition]

When 0 is written to TCFU after reading TCFU = 1

1 [Setting condition]

When the TCNT value underflows (changes from H'0000 to H'FFFF)

Count Direction Flag

0 TCNT counts down

TCNT counts up

Note: * Can only be written with 0 for flag clearing.

1000

TCNT5—Timer Counter 5 H'FEA6 TPU5

R/W

Bit

Initial value

Read/Write

R/W

Up/down-counter*

Note: * These counters can be used as up/down-counters only in phase counting mode or

when counting overflow/underflow on another channel. In other cases they function

as up-counters.

TGR5A—Timer General Register 5A H'FEA8 TPU5

TGR5B—Timer General Register 5B H'FEAA TPU5

R/W

Bit

Initial value

Read/Write

R/W

TSTR—Timer Start Register H'FEB0 TPU

—

CST5

R/W

CST4

R/W

CST3

R/W

CST0

R/W

CST2

R/W

CST1

R/W

Bit

Initial value

Read/Write

(n = 5 to 0)

Counter Start

0 TCNTn count operation is stopped

TCNTn performs count operation1

Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output,

the counter stops but the TIOC pin output compare output level is retained. If TIOR is

written to when the CST bit is cleared to 0, the pin output level will be changed to the

set initial output value.

1001

TSYR—Timer Synchro Register H'FEB1 TPU

—

SYNC5

R/W

SYNC4

R/W

SYNC3

R/W

SYNC0

R/W

SYNC2

R/W

SYNC1

R/W

Bit

Initial value

Read/Write

(n = 5 to 0)

Timer Synchro

0 TCNTn operates independently (TCNT presetting/

clearing is unrelated to other channels)

TCNTn performs synchronous operation

TCNT synchronous presetting/synchronous clearing

is possible

Notes: 1.

2. To set synchronous operation, the SYNC bits for at least two channels must be set to 1.

To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source

must also be set by means of bits CCLR2 to CCLR0 in TCR.

1002

IPRA—Interrupt Priority Register A

IPRB—Interrupt Priority Register B

IPRC—Interrupt Priority Register C

IPRD—Interrupt Priority Register D

IPRE—Interrupt Priority Register E

IPRF—Interrupt Priority Register F

IPRG—Interrupt Priority Register G

IPRH—Interrupt Priority Register H

IPRJ—Interrupt Priority Register J

IPRK—Interrupt Priority Register K

IPRM—Interrupt Priority Register M

H'FEC0

H'FEC1

H'FEC2

H'FEC3

H'FEC4

H'FEC5

H'FEC6

H'FEC7

H'FEC9

H'FECA

H'FECC

INT

—

IPR6

R/W

IPR5

R/W

IPR4

R/W

—

IPR0

R/W

IPR2

R/W

IPR1

R/W

Bit

Initial value

Read/Write

Correspondence between Interrupt Sources and IPR Settings

IPRA

IPRB

IPRC

IPRD

IPRE

IPRF

IPRG

IPRH

IPRJ

IPRK

IPRM

Bits

6 to 4

IRQ0

IRQ2

IRQ3

—*1

Watchdog timer 0

PC break

TPU channel 0

TPU channel 2

TPU channel 4

—*1

SCI channel 1

PWM channel 1, 2

IRQ1

IRQ4

IRQ5

DTC

—*1

A/D converter, watchdog timer 1

TPU channel 1

TPU channel 3

TPU channel 5

SCI channel 0

—*2

HCAN

2 to 0

Notes: *1

*2Reserved. These bits are always read as 1 and cannot be modified.

Reserved. These bits are always read as 1 and should only be

written with H'7.

1003

ABWCR—Bus Width Control Register H'FED0 Bus Controller

ABW7

R/W

ABW6

R/W

ABW5

R/W

ABW4

R/W

ABW3

R/W

ABW0

R/W

ABW2

R/W

ABW1

R/W

Bit

Modes 5 to 7

Initial value

Read/Write

Mode 4

Initial value

Read/Write

Area 7 to 0 Bus Width Control

0 Area n is designated for 16-bit access

Area n is designated for 8-bit access1

(n = 7 to 0)

ASTCR—Access State Control Register H'FED1 Bus Controller

AST7

R/W

AST6

R/W

AST5

R/W

AST4

R/W

AST3

R/W

AST0

R/W

AST2

R/W

AST1

R/W

Bit

Initial value

Read/Write

Area 7 to 0 Access State Control

0 Area n is designated for 2-state access

Wait state insertion in area n external space is disabled

Area n is designated for 3-state access

Wait state insertion in area n external space is enabled

(n = 7 to 0)

1004

WCRH—Wait Control Register H H'FED2 Bus Controller

W71

R/W

W70

R/W

W61

R/W

W60

R/W

W51

R/W

W40

R/W

W50

R/W

W41

R/W

Bit

Initial value

Read/Write

Area 4 Wait Control 1 and 0

0 Program wait not inserted when external

space area 4 is accessed

1 program wait state inserted when external

space area 4 is accessed

1 2 program wait states inserted when external

space area 4 is accessed

3 program wait states inserted when external

space area 4 is accessed

Area 6 Wait Control 1 and 0

Area 7 Wait Control 1 and 0

0 Program wait not inserted when external space area 7 is accessed0

1 program wait state inserted when external space area 7 is accessed1

1 2 program wait states inserted when external space area 7 is accessed0

3 program wait states inserted when external space area 7 is accessed 1

0 Program wait not inserted when external space area 6 is accessed0

1 program wait state inserted when external space area 6 is accessed1

1 2 program wait states inserted when external space area 6 is accessed0

3 program wait states inserted when external space area 6 is accessed 1

Area 5 Wait Control 1 and 0

0 Program wait not inserted when external space area 5 is accessed0

1 program wait state inserted when external space area 5 is accessed1

1 2 program wait states inserted when external space area 5 is accessed0

3 program wait states inserted when external space area 5 is accessed 1

1005

WCRL—Wait Control Register L H'FED3 Bus Controller

W31

R/W

W30

R/W

W21

R/W

W20

R/W

W11

R/W

W00

R/W

W10

R/W

W01

R/W

Bit

Initial value

Read/Write

Area 0 Wait Control 1 and 0

0 Program wait not inserted when external

space area 0 is accessed

1 program wait state inserted when external

space area 0 is accessed

1 2 program wait states inserted when external

space area 0 is accessed

3 program wait states inserted when external

space area 0 is accessed

Area 2 Wait Control 1 and 0

Area 3 Wait Control 1 and 0

0 Program wait not inserted when external space area 3 is accessed0

1 program wait state inserted when external space area 3 is accessed1

1 2 program wait states inserted when external space area 3 is accessed0

3 program wait states inserted when external space area 3 is accessed 1

0 Program wait not inserted when external space area 2 is accessed0

1 program wait state inserted when external space area 2 is accessed1

1 2 program wait states inserted when external space area 2 is accessed0

3 program wait states inserted when external space area 2 is accessed 1

Area 1 Wait Control 1 and 0

0 Program wait not inserted when external space area 1 is accessed0

1 program wait state inserted when external space area 1 is accessed1

1 2 program wait states inserted when external space area 1 is accessed0

3 program wait states inserted when external space area 1 is accessed 1

1006

BCRH—Bus Control Register H H'FED4 Bus Controller

ICIS1

R/W

ICIS0

R/W

BRSTRM

R/W

BRSTS1

R/W

BRSTS0

R/W

—

R/W

—

R/W

—

R/W

Bit

Initial value

Read/Write

Burst Cycle Select 0

0 Max. 4 words in burst access

Max. 8 words in burst access1

Burst Cycle Select 1

0 Burst cycle comprises 1 state

Burst cycle comprises 2 states1

Burst ROM Enable

0 Area 0 is basic bus interface

Area 0 is burst ROM interface1

Idle Cycle Insert 0

0 Idle cycle not inserted in case of successive external

read and external write cycles

Idle cycle inserted in case of successive external

read and external write cycles

Idle Cycle Insert 1

Idle cycle not inserted in case of successive external

read cycles in different areas

Idle cycle inserted in case of successive external

read cycles in different areas

1007

BCRL—Bus Control Register L H'FED5 Bus Controller

—

R/W

—

R/W

—

R/W

—

R/W

WAITE

R/W

—

R/W

WDBE

R/W

Bit

Initial value

Read/Write

Wait Enable

0 Wait input by WAIT pin disabled.

WAIT pin can be used as I/O port.

Wait input by WAIT pin enabled

Write Data Buffer Enable

0 Write data buffer function not used

Write data buffer function used1

RAMER—RAM Emulation Register H'FEDB Flash Memory

—

R/W

—

R/W

RAMS

R/W

RAM0

R/W

RAM2

R/W

RAM1

R/W

Bit

Initial value

Read/Write

RAM Select

0 Emulation not selected

Program/erase-protection of all flash memory blocks is disabled

1 Emulation selected

Program/erase-protection of all flash memory blocks is enabled

Flash Memory Area Selection

H'FFE000–H'FFE3FF

H'000000–H'0003FF

H'000400–H'0007FF

H'000800–H'000BFF

H'000C00–H'000FFF

RAM area 1 kB

EB0 (1 kB)

EB1 (1 kB)

EB2 (1 kB)

EB3 (1 kB)

RAM2

RAMS

Addresses

*: Don't care

Block Name RAM1

RAM0

1008

P1DR—Port 1 Data Register H'FF00 Port

P17DR

R/W

P16DR

R/W

P15DR

R/W

P14DR

R/W

P13DR

R/W

P10DR

R/W

P12DR

R/W

P11DR

R/W

Bit

Initial value

Read/Write

P2DR—Port 2 Data Register H'FF01 Port

P27DR

R/W

P26DR

R/W

P25DR

R/W

P24DR

R/W

P23DR

R/W

P20DR

R/W

P22DR

R/W

P21DR

R/W

Bit

Initial value

Read/Write

P3DR—Port 3 Data Register H'FF02 Port

P37DR

R/W

P36DR

R/W

P35DR

R/W

P34DR

R/W

P33DR

R/W

P30DR

R/W

P32DR

R/W

P31DR

R/W

Bit

Initial value

Read/Write

P5DR—Port 5 Data Register H'FF04 Port

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

P50DR

R/W

P52DR

R/W

P51DR

R/W

Bit

Initial value

Read/Write

PADR—Port A Data Register H'FF09 Port

PA7DR

R/W

PA6DR

R/W

PA5DR

R/W

PA4DR

R/W

PA3DR

R/W

PA0DR

R/W

PA2DR

R/W

PA1DR

R/W

Bit

Initial value

Read/Write

1009

PBDR—Port B Data Register H'FF0A Port

PB7DR

R/W

PB6DR

R/W

PB5DR

R/W

PB4DR

R/W

PB3DR

R/W

PB0DR

R/W

PB2DR

R/W

PB1DR

R/W

Bit

Initial value

Read/Write

PCDR—Port C Data Register H'FF0B Port

PC7DR

R/W

PC6DR

R/W

PC5DR

R/W

PC4DR

R/W

PC3DR

R/W

PC0DR

R/W

PC2DR

R/W

PC1DR

R/W

Bit

Initial value

Read/Write

PDDR—Port D Data Register H'FF0C Port

PD7DR

R/W

PD6DR

R/W

PD5DR

R/W

PD4DR

R/W

PD3DR

R/W

PD0DR

R/W

PD2DR

R/W

PD1DR

R/W

Bit

Initial value

Read/Write

PEDR—Port E Data Register H'FF0D Port

PE7DR

R/W

PE6DR

R/W

PE5DR

R/W

PE4DR

R/W

PE3DR

R/W

PE0DR

R/W

PE2DR

R/W

PE1DR

R/W

Bit

Initial value

Read/Write

PFDR—Port F Data Register H'FF0E Port

—

R/W

PF6DR

R/W

PF5DR

R/W

PF4DR

R/W

PF3DR

R/W

PF0DR

R/W

PF2DR

R/W

—

Undefined

—

Bit

Initial value

Read/Write

1010

TCR0—Timer Control Register 0 H'FF10 TPU0

CCLR2

R/W

CCLR1

R/W

CCLR0

R/W

CKEG1

R/W

CKEG0

R/W

TPSC0

R/W

TPSC2

R/W

TPSC1

R/W

Bit

Initial value

Read/Write

Time Prescaler

0 Internal clock: counts on ø/1

Internal clock: counts on ø/4

Internal clock: counts on ø/16

Internal clock: counts on ø/64

External clock: counts on TCLKA pin input

External clock: counts on TCLKB pin input

External clock: counts on TCLKC pin input

External clock: counts on TCLKD pin input

Counter Clear

0 TCNT clearing disabled

TCNT cleared by TGRA compare match/input capture

TCNT cleared by TGRB compare match/input capture

TCNT cleared by counter clearing for another channel

performing synchronous clearing/synchronous operation*1

TCNT clearing disabled

TCNT cleared by TGRC compare match/input capture*2

TCNT cleared by TGRD compare match/input capture*2

TCNT cleared by counter clearing for another channel

performing synchronous clearing/synchronous operation*1

Notes: *1

Synchronous operation setting is performed by setting the

SYNC bit in TSYR to 1.

When TGRC or TGRD is used as a buffer register, TCNT is

not cleared because the buffer register setting has priority,

and compare match/input capture does not occur.

Clock Edge

Count at rising edge

Count at falling edge

Count at both edges

—

Note: Internal clock edge selection is valid when the input clock

is ø/4 or slower. This setting is ignored if the input clock is ø/1,

or when overflow/underflow of another channel is selected.

1011

TMDR0—Timer Mode Register 0 H'FF11 TPU0

—

BFB

R/W

BFA

R/W

MD3

R/W

MD0

R/W

MD2

R/W

MD1

R/W

Bit

Initial value

Read/Write

Buffer Operation A

*: Don't care

0 TGRA operates normally

TGRA and TGRC used together for buffer operation1

Buffer Operation B

0 TGRB operates normally

TGRB and TGRD used together for buffer operation1

Notes: 1.

MD3 is a reserved bit. In a write,

it should always be written with 0.

Phase counting mode cannot be

set for channel 0. In this case, 0

should always be written to MD2.

Mode

0Normal operation

Reserved

PWM mode 1

PWM mode 2

Phase counting mode 1

Phase counting mode 2

Phase counting mode 3

Phase counting mode 4

—

1012

TIOR0H—Timer I/O Control Register 0H H'FF12 TPU0

IOB3

R/W

IOB2

R/W

IOB1

R/W

IOB0

R/W

IOA3

R/W

IOA0

R/W

IOA2

R/W

IOA1

R/W

Bit

Initial value

Read/Write

*: Don't care

TGR0A I/O Control

0 output at compare match

1 output at compare match

Toggle output at compare match

0 output at compare match

1 output at compare match

Toggle output at compare match

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

Input capture at TCNT1 count-up/

count-down

TGR0A is

output

compare

TGR0A is

input

capture

Output disabled

Initial output is 0

output

Output disabled

Initial output is 1

output

Capture input

source is

TIOCA0 pin

Capture input

source is channel

1/count clock

*: Don't care

TGR0B I/O Control

0 output at compare match

1 output at compare match

Toggle output at compare match

0 output at compare match

1 output at compare match

Toggle output at compare match

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

Input capture at TCNT1 count-up/

count-down*1

TGR0B is

output

compare

TGR0B is

input

capture

Output disabled

Initial output is 0

output

Output disabled

Initial output is 1

output

Capture input

source is

TIOCB0 pin

Capture input

source is channel

1/count clock

Note: *1 When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and ø/1 is used as the

TCNT1 count clock, this setting is invalid and input capture is not generated.

1013

TIOR0L—Timer I/O Control Register 0L H'FF13 TPU0

IOD3

R/W

IOD2

R/W

IOD1

R/W

IOD0

R/W

IOC3

R/W

IOC0

R/W

IOC2

R/W

IOC1

R/W

Bit

Initial value

Read/Write

*: Don't care

TGR0C I/O Control

0 output at compare match

1 output at compare match

Toggle output at compare match

0 output at compare match

1 output at compare match

Toggle output at compare match

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

Input capture at TCNT1 count-up/

count-down

TGR0C is

output

compare

TGR0C is

input

capture

Output disabled

Initial output is 0

output

Output disabled

Initial output is 1

output

Capture input

source is

TIOCC0 pin

Capture input

source is channel

1/count clock

*: Don't care

TGR0D I/O Control

0 output at compare match

1 output at compare match

Toggle output at compare match

0 output at compare match

1 output at compare match

Toggle output at compare match

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

Input capture at TCNT1 count-up/

count-down*1

TGR0D is

output

compare

TGR0D is

input

capture

Output disabled

Initial output is 0

output

Output disabled

Initial output is 1

output

Capture input

source is

TIOCD0 pin

Capture input

source is channel

1/count clock

Notes: *1

When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and ø/1 is used as the

TCNT1 count clock, this setting is invalid and input capture is not generated.

When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register,

this setting is invalid and input capture/output compare is not generated.

Note: *1When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register,

this setting is invalid and input capture/output compare is not generated.

Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the

1014

TIER0—Timer Interrupt Enable Register 0 H'FF14 TPU0

TTGE

R/W

—

TCIEV

R/W

TGIED

R/W

TGIEA

R/W

TGIEC

R/W

TGIEB

R/W

Bit

Initial value

Read/Write

TGR Interrupt Enable A

0 Interrupt requests (TGIA) by TGFA bit disabled

Interrupt requests (TGIA) by TGFA bit enabled1

TGR Interrupt Enable B

0 Interrupt requests (TGIB) by TGFB bit disabled

Interrupt requests (TGIB) by TGFB bit enabled1

TGR Interrupt Enable C

0 Interrupt requests (TGIC) by TGFC bit disabled

Interrupt requests (TGIC) by TGFC bit enabled1

TGR Interrupt Enable D

0 Interrupt requests (TGID) by TGFD bit disabled

Interrupt requests (TGID) by TGFD bit enabled1

Overflow Interrupt Enable

0 Interrupt requests (TCIV) by TCFV disabled

Interrupt requests (TCIV) by TCFV enabled1

A/D Conversion Start Request Enable

0 A/D conversion start request generation disabled

A/D conversion start request generation enabled1

1015

TSR0—Timer Status Register 0 H'FF15 TPU0

—

TCFV

R/(W)*

TGFD

R/(W)*

TGFA

R/(W)*

TGFC

R/(W)*

TGFB

R/(W)*

Bit

Initial value

Read/Write

Input Capture/Output Compare Flag A

0 [Clearing conditions]

• When DTC is activated by TGIA interrupt while DISEL bit

of MRB in DTC is 0

• When 0 is written to TGFA after reading TGFA = 1

1 [Setting conditions]

• When TCNT = TGRA while TGRA is functioning as output

compare register

• When TCNT value is transferred to TGRA by input capture

signal while TGRA is functioning as input capture register

Input Capture/Output Compare Flag B

0 [Clearing conditions]

• When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0

• When 0 is written to TGFB after reading TGFB = 1

1 [Setting conditions]

• When TCNT = TGRB while TGRB is functioning as output compare register

• When TCNT value is transferred to TGRB by input capture signal while

TGRB is functioning as input capture register

Input Capture/Output Compare Flag C

0 [Clearing conditions]

• When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0

• When 0 is written to TGFC after reading TGFC = 1

1 [Setting conditions]

• When TCNT = TGRC while TGRC is functioning as output compare register

• When TCNT value is transferred to TGRC by input capture signal while

TGRC is functioning as input capture register

Input Capture/Output Compare Flag D

0 [Clearing conditions]

• When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0

• When 0 is written to TGFD after reading TGFD = 1

1 [Setting conditions]

• When TCNT = TGRD while TGRD is functioning as output compare register

• When TCNT value is transferred to TGRD by input capture signal while

TGRD is functioning as input capture register

Overflow Flag

0 [Clearing condition]

When 0 is written to TCFV after reading TCFV = 1

1 [Setting condition]

When the TCNT value overflows (changes from H'FFFF to H'0000)

Note: * Can only be written with 0 for flag clearing.

1016

TCNT0—Timer Counter 0 H'FF16 TPU0

R/W

Bit

Initial value

Read/Write

R/W

Up-counter

TGR0A—Timer General Register 0A H'FF18 TPU0

TGR0B—Timer General Register 0B H'FF1A TPU0

TGR0C—Timer General Register 0C H'FF1C TPU0

TGR0D—Timer General Register 0D H'FF1E TPU0

R/W

Bit

Initial value

Read/Write

R/W

1017

TCR1—Timer Control Register 1 H'FF20 TPU1

Bit

Initial value

Read/Write

Clock Edge

Count at rising edge

Count at falling edge

Count at both edges

—

Time Prescaler

0 Internal clock: counts on ø/1

Internal clock: counts on ø/4

Internal clock: counts on ø/16

Internal clock: counts on ø/64

External clock: counts on TCLKA pin input

External clock: counts on TCLKB pin input

Internal clock: counts on ø/256

Counts on TCNT2 overflow/underflow

Counter Clear

TCNT clearing disabled

TCNT cleared by TGRA compare match/input capture

TCNT cleared by TGRB compare match/input capture

TCNT cleared by counter clearing for another channel

performing synchronous clearing/synchronous operation*

Note: *Synchronous operation setting is performed by setting the

SYNC bit in TSYR to 1.

Note: This setting is ignored when channel 1 is in phase

counting mode.

—

CCLR1

R/W

CCLR0

R/W

CKEG1

R/W

CKEG0

R/W

TPSC0

R/W

TPSC2

R/W

TPSC1

R/W

Note: Internal clock edge selection is valid when the input

clock is ø/4 or slower. This setting is ignored if the

input clock is ø/1, or when overflow/underflow of

another channel is selected.

Note: Bit 7 is reserved in channel 1.

It is always read as 0 and cannot be modified.

1018

TMDR1—Timer Mode Register 1 H'FF21 TPU1

—

MD3

R/W

MD0

R/W

MD2

R/W

MD1

R/W

Bit

Initial value

Read/Write

*: Don't care

Note: MD3 is a reserved bit. In a write, it

should always be written with 0.

Mode

0Normal operation

Reserved

PWM mode 1

PWM mode 2

Phase counting mode 1

Phase counting mode 2

Phase counting mode 3

Phase counting mode 4

—

1019

TIOR1—Timer I/O Control Register 1 H'FF22 TPU1

IOB3

R/W

IOB2

R/W

IOB1

R/W

IOB0

R/W

IOA3

R/W

IOA0

R/W

IOA2

R/W

IOA1

R/W

Bit

Initial value

Read/Write

*: Don't care

TGR1A I/O Control

0 output at compare match

1 output at compare match

Toggle output at compare match

0 output at compare match

1 output at compare match

Toggle output at compare match

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

Input capture at generation of

channel 0/TGR0A compare match/

input capture

TGR1A is

output

compare

TGR1A is

input

capture

Output disabled

Initial output is 0

output

Output disabled

Initial output is 1

output

Capture input

source is

TIOCA1 pin

Capture input

source is TGR0A

compare match/

input capture

*: Don't care

TGR1B I/O Control

0 output at compare match

1 output at compare match

Toggle output at compare match

0 output at compare match

1 output at compare match

Toggle output at compare match

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

Input capture at generation of TGR0C

compare match/input capture

TGR1B is

output

compare

TGR1B is

input

capture

Output disabled

Initial output is 0

output

Output disabled

Initial output is 1

output

Capture input

source is

TIOCB1 pin

Capture input

source is TGR0C

compare match/

input capture

1020

TIER1—Timer Interrupt Enable Register 1 H'FF24 TPU1

TTGE

R/W

—

TCIEU

R/W

TCIEV

R/W

—

TGIEA

R/W

—

TGIEB

R/W

Bit

Initial value

Read/Write

TGR Interrupt Enable A

0 Interrupt requests (TGIA) by TGFA bit disabled

Interrupt requests (TGIA) by TGFA bit enabled1

TGR Interrupt Enable B

0 Interrupt requests (TGIB) by TGFB bit disabled

Interrupt requests (TGIB) by TGFB bit enabled1

Overflow Interrupt Enable

0 Interrupt requests (TCIV) by TCFV disabled

Interrupt requests (TCIV) by TCFV enabled1

Underflow Interrupt Enable

0 Interrupt requests (TCIU) by TCFU disabled

Interrupt requests (TCIU) by TCFU enabled1

A/D Conversion Start Request Enable

0 A/D conversion start request generation disabled

A/D conversion start request generation enabled1

1021

TSR1—Timer Status Register 1 H'FF25 TPU1

TCFD

—

TCFU

R/(W)*

TCFV

R/(W)*

—

TGFA

R/(W)*

—

TGFB

R/(W)*

Bit

Initial value

Read/Write

Input Capture/Output Compare Flag A

0 [Clearing conditions]

• When DTC is activated by TGIA interrupt while DISEL bit

of MRB in DTC is 0

• When 0 is written to TGFA after reading TGFA = 1

1 [Setting conditions]

• When TCNT = TGRA while TGRA is functioning as output

compare register

• When TCNT value is transferred to TGRA by input capture

signal while TGRA is functioning as input capture register

Input Capture/Output Compare Flag B

0 [Clearing conditions]

• When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0

• When 0 is written to TGFB after reading TGFB = 1

1 [Setting conditions]

• When TCNT = TGRB while TGRB is functioning as output compare register

• When TCNT value is transferred to TGRB by input capture signal while

TGRB is functioning as input capture register

Overflow Flag

0 [Clearing condition]

When 0 is written to TCFV after reading TCFV = 1

1 [Setting condition]

When the TCNT value overflows (changes from H'FFFF to H'0000)

Underflow Flag

0 [Clearing condition]

When 0 is written to TCFU after reading TCFU = 1

1 [Setting condition]

When the TCNT value underflows (changes from H'0000 to H'FFFF)

Count Direction Flag

0 TCNT counts down

TCNT counts up

Note: * Can only be written with 0 for flag clearing.

1022

TCNT1—Timer Counter 1 H'FF26 TPU1

R/W

Bit

Initial value

Read/Write

R/W

Up/down-counter*

Note: * These counters can be used as up/down-counters only in phase counting mode or

when counting overflow/underflow on another channel. In other cases they function

as up-counters.

TGR1A—Timer General Register 1A H'FF28 TPU1

TGR1B—Timer General Register 1B H'FF2A TPU1

R/W

Bit

Initial value

Read/Write

R/W

1023

TCR2—Timer Control Register 2 H'FF30 TPU2

Bit

Initial value

Read/Write

Clock Edge

Count at rising edge

Count at falling edge

Count at both edges

—

Time Prescaler

0 Internal clock: counts on ø/1

Internal clock: counts on ø/4

Internal clock: counts on ø/16

Internal clock: counts on ø/64

External clock: counts on TCLKA pin input

External clock: counts on TCLKB pin input

External clock: counts on TCLKC pin input

Internal clock: counts on ø/1024

Counter Clear

TCNT clearing disabled

TCNT cleared by TGRA compare match/input capture

TCNT cleared by TGRB compare match/input capture

TCNT cleared by counter clearing for another channel

performing synchronous clearing/synchronous operation*

Note: *Synchronous operation setting is performed by setting the

SYNC bit in TSYR to 1.

Note: This setting is ignored when channel 2 is in phase

counting mode.

—

CCLR1

R/W

CCLR0

R/W

CKEG1

R/W

CKEG0

R/W

TPSC0

R/W

TPSC2

R/W

TPSC1

R/W

Note: Internal clock edge selection is valid when the input

clock is ø/4 or slower. This setting is ignored if the

input clock is ø/1, or when overflow/underflow of

another channel is selected.

Note: Bit 7 is reserved in channel 2.

It is always read as 0 and cannot be modified.

1024

TMDR2—Timer Mode Register 2 H'FF31 TPU2

—

MD3

R/W

MD0

R/W

MD2

R/W

MD1

R/W

Bit

Initial value

Read/Write

*: Don't care

Note: MD3 is a reserved bit. In a write, it

should always be written with 0.

Mode

0Normal operation

Reserved

PWM mode 1

PWM mode 2

Phase counting mode 1

Phase counting mode 2

Phase counting mode 3

Phase counting mode 4

—

1025

TIOR2—Timer I/O Control Register 2 H'FF32 TPU2

IOB3

R/W

IOB2

R/W

IOB1

R/W

IOB0

R/W

IOA3

R/W

IOA0

R/W

IOA2

R/W

IOA1

R/W

Bit

Initial value

Read/Write

*: Don't care

TGR2A I/O Control

0 output at compare match

1 output at compare match

Toggle output at compare match

0 output at compare match

1 output at compare match

Toggle output at compare match

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

TGR2A is

output

compare

TGR2A is

input

capture

Output disabled

Initial output is 0

output

Output disabled

Initial output is 1

output

Capture input

source is

TIOCA2 pin

*: Don't care

TGR2B I/O Control

0 output at compare match

1 output at compare match

Toggle output at compare match

0 output at compare match

1 output at compare match

Toggle output at compare match

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

TGR2B is

output

compare

TGR2B is

input

capture

Output disabled

Initial output is 0

output

Output disabled

Initial output is 1

output

Capture input

source is

TIOCB2 pin

1026

TIER2—Timer Interrupt Enable Register 2 H'FF34 TPU2

TTGE

R/W

—

TCIEU

R/W

TCIEV

R/W

—

TGIEA

R/W

—

TGIEB

R/W

Bit

Initial value

Read/Write

TGR Interrupt Enable A

0 Interrupt requests (TGIA) by TGFA bit disabled

Interrupt requests (TGIA) by TGFA bit enabled1

TGR Interrupt Enable B

0 Interrupt requests (TGIB) by TGFB bit disabled

Interrupt requests (TGIB) by TGFB bit enabled1

Overflow Interrupt Enable

0 Interrupt requests (TCIV) by TCFV disabled

Interrupt requests (TCIV) by TCFV enabled1

Underflow Interrupt Enable

0 Interrupt requests (TCIU) by TCFU disabled

Interrupt requests (TCIU) by TCFU enabled1

A/D Conversion Start Request Enable

0 A/D conversion start request generation disabled

A/D conversion start request generation enabled1

1027

TSR2—Timer Status Register 2 H'FF35 TPU2

TCFD

—

TCFU

R/(W)*

TCFV

R/(W)*

—

TGFA

R/(W)*

—

TGFB

R/(W)*

Bit

Initial value

Read/Write

Input Capture/Output Compare Flag A

0 [Clearing conditions]

• When DTC is activated by TGIA interrupt while DISEL bit

of MRB in DTC is 0

• When 0 is written to TGFA after reading TGFA = 1

1 [Setting conditions]

• When TCNT = TGRA while TGRA is functioning as output

compare register

• When TCNT value is transferred to TGRA by input capture

signal while TGRA is functioning as input capture register

Input Capture/Output Compare Flag B

0 [Clearing conditions]

• When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0

• When 0 is written to TGFB after reading TGFB = 1

1 [Setting conditions]

• When TCNT = TGRB while TGRB is functioning as output compare register

• When TCNT value is transferred to TGRB by input capture signal while

TGRB is functioning as input capture register

Overflow Flag

0 [Clearing condition]

When 0 is written to TCFV after reading TCFV = 1

1 [Setting condition]

When the TCNT value overflows (changes from H'FFFF to H'0000)

Underflow Flag

0 [Clearing condition]

When 0 is written to TCFU after reading TCFU = 1

1 [Setting condition]

When the TCNT value underflows (changes from H'0000 to H'FFFF)

Count Direction Flag

0 TCNT counts down

TCNT counts up

Note: * Can only be written with 0 for flag clearing.

1028

TCNT2—Timer Counter 2 H'FF36 TPU2

R/W

Bit

Initial value

Read/Write

R/W

Up/down-counter*

Note: * These counters can be used as up/down-counters only in phase counting mode or

when counting overflow/underflow on another channel. In other cases they function

as up-counters.

TGR2A—Timer General Register 2A H'FF38 TPU2

TGR2B—Timer General Register 2B H'FF3A TPU2

R/W

Bit

Initial value

Read/Write

R/W

1029

TCSR0—Timer Control/Status Register 0 H'FF74(W), H'FF74(R) WDT0

Bit

Initial value

Read/Write

Clock Select 2 to 0

ø/2

ø/64

ø/128

ø/512

ø/2048

ø/8192

ø/32768

ø/131072

25.6 µs

819.2 µs

1.6 ms

6.6 ms

26.2 ms

104.9 ms

419.4 ms

1.68 s

CKS2 CKS1 CKS0 Clock Overflow Period*

(where ø = 20 MHz)

OVF

R/(W)*

WT/IT

R/W

TME

R/W

—

CKS0

R/W

CKS2

R/W

CKS1

R/W

Note: *An overflow period is the time interval between the

start of counting up from H'00 on the TCNT and the

occurrence of a TCNT overflow.

Note: * For details see section 12.2.3, Reset Control/Status Register (RSTCSR).

Timer Enable

0 TCNT is initialized to H'00 and halted

TCNT counts1

Timer Mode Select

0 Interval timer mode: WDT0 requests an interval timer interrupt (WOVI) from

the CPU when the TCNT overflows

Watchdog timer mode: A reset is issued when the TCNT overflows if the

RSTE bit of RSTCSR is set to 1*

Overflow Flag

0 [Clearing conditions]

• Cleared when 0 is written to the TME bit (Only applies to WDT1)

• Cleared by reading TCSR when OVF = 1, then write 0 in OVF

[Setting condition]

When TCNT overflows (changes from H'FF to H'00)

(When internal reset request generation is selected in watchdog timer mode,

OVF is cleared automatically by the internal reset)

Note: * Only a 0 may be written to this bit to clear the flag.

TCSR0 register differs from other registers in being more difficult to write to.

For details see section 12.2.4, Notes on Register Access.

1030

TCNT0—Timer Counter 0 H'FF74(W), H'FF75(R) WDT0

R/W

Bit

Initial value

Read/Write

Up-counter

Note: TCNT is write-protected by a password to prevent accidental overwriting.

For details see section 12.2.4, Notes on Register Access.

RSTCSR—Reset Control/Status Register H'FF76(W), H'FF77(R) WDT0

Bit

Initial value

Read/Write

WOVF

R/(W)*

RSTE

R/W

—

Reset Enable

0 Reset signal is not generated if TCNT overflows*

Reset signal is generated if TCNT overflows1

Watchdog Overflow Flag

0 [Clearing condition]

Cleared by reading TCSR when WOVF = 1, then writing 0 to WOVF

[Setting condition]

Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer

operation

Note: *Can only be written with 0 for flag clearing.

RSTCSR is write-protected by a password to prevent accidential overwriting.

For details see section 12.2.4, Notes on Register Access.

Note: *The modules within the H8S/2646 are not reset,

but TCNT and TCSR within the WDT are reset.

1031

SMR0—Serial Mode Register 0 H'FF78 SCI0

C/A

R/W

CHR

R/W

O/E

R/W

STOP

R/W

CKS0

R/W

CKS1

R/W

Bit

Initial value

Read/Write

Clock Select 1 and 0

0ø clock

ø/4 clock

ø/16 clock

ø/64 clock

Stop Bit Length

Multiprocessor Mode

0 Multiprocessor function disabled

1 Multiprocessor format selected

Parity Mode

0 Even parity*3

Odd parity*4

Parity Enable

0 Parity bit addition and checking disabled

Parity bit addition and checking enabled*2

Character Length

0 8-bit data

7-bit data*1

Communication Mode

0 Asynchronous mode

Synchronous mode1

1 stop bit: In transmission, a single 1 bit (stop bit)

is added to the end of a transmit character before

it is sent.

2 stop bits: In transmission, two 1 bits (stop bits)

are added to the end of a transmit character

before it is sent.

1032

Notes: *1 When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and it is not

possible to choose between LSB-first or MSB-first transfer.

*2 When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to

transmit data before transmission. In reception, the parity bit is checked for the parity

(even or odd) specified by the O/E bit.

*3 When even parity is set, parity bit addition is performed in transmission so that the total

number of 1 bits in the transmit character plus the parity bit is even.

In reception, a check is performed to see if the total number of 1 bits in the receive

character plus the parity bit is even.

*4 When odd parity is set, parity bit addition is performed in transmission so that the total

number of 1 bits in the transmit character plus the parity bit is odd.

In reception, a check is performed to see if the total number of 1 bits in the receive

character plus the parity bit is odd.

1033

SMR0—Serial Mode Register 0 H'FF78 SCI0, Smart Card Interface 0

R/W

BLK

R/W

O/E

R/W

BCP1

R/W

CKS0

R/W

BCP0

R/W

CKS1

R/W

Bit

Initial value

Read/Write

Clock Select 1 and 0

0ø clock

ø/4 clock

ø/16 clock

ø/64 clock

Basic Clock Pulse

0 32 clock periods

64 clock periods

372 clock periods

256 clock periods

Parity Mode

0 Even parity*2

Odd parity*3

Parity Enable

0 Parity bit addition and checking disabled

Parity bit addition and checking enabled*1

Block Transfer Mode

0 Normal Smart Card interface mode operation

• Error signal transmission/detection and automatic data retransmission performed

• TXI interrupt generated by TEND flag

• TEND flag set 12.5 etu after start of transmission (11.0 etu in GSM mode)

Block transfer mode operation

• Error signal transmission/detection and automatic data retransmission not performed

• TXI interrupt generated by TDRE flag

• TEND flag set 11.5 etu after start of transmission (11.0 etu in GSM mode)

GSM Mode

0 Normal smart card interface mode operation

• TEND flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit

• Clock output ON/OFF control only

GSM mode smart card interface mode operation

• TEND flag generation 11.0 etu after beginning of start bit

• High/low fixing control possible in addition to clock output ON/OFF control (set by SCR)

Note: etu: Elementary time unit (time for transfer of 1 bit)

1034

Notes: When the smart card interface is used, be sure to make the 1 setting shown for bit 5.

*1 When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to

transmit data before transmission. In reception, the parity bit is checked for the parity

(even or odd) specified by the O/E bit.

*2 When even parity is set, parity bit addition is performed in transmission so that the total

number of 1 bits in the transmit character plus the parity bit is even.

In reception, a check is performed to see if the total number of 1 bits in the receive

character plus the parity bit is even.

*3 When odd parity is set, parity bit addition is performed in transmission so that the total

number of 1 bits in the transmit character plus the parity bit is odd.

In reception, a check is performed to see if the total number of 1 bits in the receive

character plus the parity bit is odd.

BRR0—Bit Rate Register 0 H'FF79 SCI0, Smart Card Interface 0

R/W

Bit

Initial value

Read/Write

Set the serial transmit/receive bit rate

Note: For details see section 13.2.8, Bit Rate Register (BRR).

1035

SCR0—Serial Control Register 0 H'FF7A SCI0

TIE

R/W

RIE

R/W

MPIE

R/W

CKE0

R/W

TEIE

R/W

CKE1

R/W

Bit

Initial value

Read/Write

Clock Enable 1 and 0

0Asynchronous

mode

Clocked

synchronous mode

Asynchronous

mode

Clocked

synchronous mode

1 Asynchronous

mode

Clocked

synchronous mode

Asynchronous

mode

Clocked

synchronous mode

Internal clock/SCK pin

functions as I/O port

Internal clock/SCK pin

functions as serial clock output

Internal clock/SCK pin

functions as clock output*9

Internal clock/SCK pin

functions as serial clock output

External clock/SCK pin

functions as clock input*10

External clock/SCK pin

functions as serial clock input

External clock/SCK pin

functions as clock input*10

External clock/SCK pin

functions as serial clock input

Transmit End Interrupt Enable

0Transmit-end interrupt (TEI) request disabled*8

1 Transmit-end interrupt (TEI) request enabled*8

Multiprocessor Interrupt Enable

0Multiprocessor interrupts disabled

(normal reception mode performed)

[Clearing conditions]

• When the MPIE bit is cleared to 0

• When MPB = 1 data is received

1 Multiprocessor interrupts enabled*7

Receive interrupt (RXI) requests, receive-error interrupt (ERI)

requests, and setting of the RDRF, FER, and ORER flags in

SSR are disabled until data with the multiprocessor bit set to

1 is received

Receive Enable

0Reception disabled*5

1 Reception enabled*6

Transmit Enable

0Transmission disabled*3

1 Transmission enabled*4

Receive Interrupt Enable

0Receive-data-full interrupt (RXI)

request and receive-error interrupt

(ERI) request disabled*2

1 Receive-data-full interrupt (RXI)

request and receive-error interrupt

(ERI) request enabled

Transmit Interrupt Enable

0Transmit-data-empty interrupt

(TXI) request disabled*1

1 Transmit-data-empty interrupt

(TXI) request enabled

1036

Notes: *1 TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag,

then clearing it to 0, or clearing the TIE bit to 0.

*2 RXI and ERI interrupt request cancellation can be performed by reading 1 from the

RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or clearing the

RIE bit to 0.

*3 The TDRE flag in SSR is fixed at 1.

*4 In this state, serial transmission is started when transmit data is written to TDR and the

TDRE flag in SSR is cleared to 0.

SMR setting must be performed to decide the transfer format before setting the TE bit

to 1.

*5 Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which

retain their states.

*6 Serial reception is started in this state when a start bit is detected in asynchronous

mode or serial clock input is detected in clocked synchronous mode.

SMR setting must be performed to decide the transfer format before setting the RE bit

to 1.

*7 When receive data including MPB = 0 is received, receive data transfer from RSR to

RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR ,

is not performed. When receive data including MPB = 1 is received, the MPB bit in

SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and

ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER

flag setting is enabled.

*8 TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then

clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0.

*9 Outputs a clock of the same frequency as the bit rate.

*10 Inputs a clock with a frequency 16 times the bit rate.

1037

SCR0—Serial Control Register 0 H'FF7A SCI0, Smart Card Interface 0

TIE

R/W

RIE

R/W

MPIE

R/W

CKE0

R/W

TEIE

R/W

CKE1

R/W

Bit

Initial value

Read/Write

Clock Enable 1 and 0

SCMR

SMIF CKE1 CKE0

SCR Setting SCK Pin FunctionSMR

C/A, GM

Operates as port I/O pin

Outputs clock as SCK

output pin

Operates as SCK output

pin, with output fixed low

Outputs clock as SCK

output pin

Operates as SCK output

pin, with output fixed high

Outputs clock as SCK

output pin

See the SCI

Operate in the same way as for the nomal SCI.

TDR0—Transmit Data Register 0 H'FF7B SCI0, Smart Card Interface 0

R/W

Bit

Initial value

Read/Write

Store serial transmit data

1038

SSR0—Serial Status Register 0 H'FF7C SCI0

TDRE

R/(W)*9

RDRF

R/(W)*9

ORER

R/(W)*9

FER

R/(W)*9

PER

R/(W)*9

MPBT

R/W

TEND

MPB

Bit

Initial value

Read/Write

Multiprocessor Bit Transfer

0Data with a 0 multi-processor

bit is transmitted

1 Data with a 1 multi-processor

bit is transmitted

Multiprocessor Bit

0[Clearing condition]

When data with a 0 multiprocessor

bit is received

1 [Setting condition]

When data with a 1 multiprocessor

bit is received

Transmit End

0[Clearing conditions]

• When 0 is written in TDRE after reading TDRE = 1

• When the DTC is activated by a TXI interrupt and

writes data to TDR

1 [Setting conditions]

• When the TE bit in SCR is 0

• When TDRE = 1 at transmission of the last bit of

a 1-byte serial transmit character

Parity Error

0[Clearing condition]

When 0 is written in PER after reading PER = 1

1 [Setting condition]

When, in reception, the number of 1 bits in the receive

data plus the parity bit does not match the parity setting

(even or odd) specified by the O/E bit in SMR*6

Framing Error

0[Clearing condition]

When 0 is written in FER after reading FER = 1

1 [Setting condition]

When the SCI checks whether the stop bit at the end of the receive

data when reception ends, and the stop bit is 0*4

Overrun Error

0[Clearing condition]

When 0 is written in ORER after reading ORER = 1

1 [Setting condition]

When the next serial reception is completed while RDRF = 1*2

Receive Data Register Full *8

0 [Clearing conditions]

• When 0 is written in RDRF after reading RDRF = 1

• When the DTC is activated by an RXI interrupt and reads data from RDR

1 [Setting condition]

When serial reception ends normally and receive data is transferred from RSR to RDR

Transmit Data Register Empty

0[Clearing conditions]

• When 0 is written in TDRE after reading TDRE = 1

• When the DTC is activated by a TXI interrupt and writes data to TDR

1[Setting conditions]

• When the TE bit in SCR is 0

• When data is transferred from TDR to TSR and data can be written in TDR

1039

Notes: *1 The ORER flag is not affected and retains its previous state when the RE bit in SCR is

cleared to 0.

*2 The receive data prior to the overrun error is retained in RDR, and the data received

subsequently is lost. Also, subsequent serial reception cannot be continued while the

ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be

continued, either.

*3 The FER flag is not affected and retains its previous state when the RE bit in SCR is

cleared to 0.

*4 In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit

is not checked. If a framing error occurs, the receive data is transferred to RDR but the

RDRF flag is not set. Also, subsequent serial reception cannot be continued while the

FER flag is set to 1. In clocked synchronous mode, serial transmission cannot be

continued, either.

*5 The PER flag is not affected and retains its previous state when the RE bit in SCR is

cleared to 0.

*6 If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not

set. Also, subsequent serial reception cannot be continued while the PER flag is set to

1. In clocked synchronous mode, serial transmission cannot be continued, either.

*7 Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor

format.

*8 RDR and the RDRF flag are not affected and retain their previous values when an error

is detected during reception or when the RE bit in SCR is cleared to 0.

If reception of the next data is completed while the RDRF flag is still set to 1, an overrun

error will occur and the receive data will be lost.

*9 Only 0 can be written, to clear the flag.

1040

SSR0—Serial Status Register 0 H'FF7C SCI0, Smart Card Interface 0

TDRE

R/(W)*

RDRF

R/(W)*

ORER

R/(W)*

ERS

R/(W)*

PER

R/(W)*

MPBT

R/W

TEND

MPB

Bit

Initial value

Read/Write

Note: * Only 0 can be written, to clear the flag.

Operate in the same way as for

the normal SCI.

Operate in the same way as for

the normal SCI.

Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag,

which retains its previous state.

Error Signal Status

0Normal reception, with no error signal

[Clearing condition]

• Upon reset, and in standby mode or module stop mode

• When 0 is written to ERS after reading ERS = 1

1 Error signal sent from receiver indicating detection of parity error

[Setting condition]

When the low level of the error signal is sampled

RDR0—Receive Data Register 0 H'FF7D SCI0, Smart Card Interface 0

Bit

Initial value

Read/Write

Store serial receive data

1041

SCMR0—Smart Card Mode Register 0 H'FF7E SCI0, Smart Card Interface 0

—

SDIR

R/W

SMIF

R/W

SINV

R/W

—

Bit

Initial value

Read/Write

Smart Card Interface Mode Select

0 Operates as normal SCI (smart card interface function disabled)

1 Smart card interface function enabled

Smart Card Data Invert

0 TDR contents are transmitted without modification

Receive data is stored in RDR without modification

1 TDR contents are inverted before being transmitted

Receive data is stored in RDR in inverted form

Smart Card Data Transfer Direction

0 TDR contents are transmitted LSB-first

Receive data is stored in RDR LSB-first

1 TDR contents are transmitted MSB-first

Receive data is stored in RDR MSB-first

1042

SMR1—Serial Mode Register 1 H'FF80 SCI1

C/A

R/W

CHR

R/W

O/E

R/W

STOP

R/W

CKS0

R/W

CKS1

R/W

Bit

Initial value

Read/Write

Clock Select 1 and 0

0ø clock

ø/4 clock

ø/16 clock

ø/64 clock

Multiprocessor Mode

0 Multiprocessor function disabled

1 Multiprocessor format selected

Parity Mode

0 Even parity

Odd parity

Parity Enable

0 Parity bit addition and checking disabled

Parity bit addition and checking enabled

Character Length

0 8-bit data

7-bit data

Communication Mode

0 Asynchronous mode

Clocked synchronous mode1

Stop Bit Length

1 stop bit: In transmission, a single 1 bit (stop bit)

is added to the end of a transmit character before

it is sent.

2 stop bits: In transmission, two 1 bits (stop bits)

are added to the end of a transmit character

before it is sent.

1043

Notes: *1 When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted and it is not

possible to choose between LSB-first or MSB-first transfer.

*2 When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to

transmit data before transmission. In reception, the parity bit is checked for the parity

(even or odd) specified by the O/E bit.

*3 When even parity is set, parity bit addition is performed in transmission so that the total

number of 1 bits in the transmit character plus the parity bit is even.

In reception, a check is performed to see if the total number of 1 bits in the receive

character plus the parity bit is even.

*4 When odd parity is set, parity bit addition is performed in transmission so that the total

number of 1 bits in the transmit character plus the parity bit is odd.

In reception, a check is performed to see if the total number of 1 bits in the receive

character plus the parity bit is odd.

1044

SMR1—Serial Mode Register 1 H'FF80 SCI1, Smart Card Interface 1

R/W

BLK

R/W

O/E

R/W

BCP1

R/W

CKS0

R/W

BCP0

R/W

CKS1

R/W

Bit

Initial value

Read/Write

Clock Select 1 and 0

0ø clock

ø/4 clock

ø/16 clock

ø/64 clock

Basic Clock Pulse

0 32 clock periods

64 clock periods

372 clock periods

256 clock periods

Parity Mode

0 Even parity*2

Odd parity*3

Parity Enable

0 Parity bit addition and checking disabled

Parity bit addition and checking enabled*1

Block Transfer Mode

0 Normal Smart Card interface mode operation

• Error signal transmission/detection and automatic data retransmission performed

• TXI interrupt generated by TEND flag

• TEND flag set 12.5 etu after start of transmission (11.0 etu in GSM mode)

Block transfer mode operation

• Error signal transmission/detection and automatic data retransmission not performed

• TXI interrupt generated by TDRE flag

• TEND flag set 11.5 etu after start of transmission (11.0 etu in GSM mode)

GSM Mode

0 Normal smart card interface mode operation

• TEND flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit

• Clock output ON/OFF control only

GSM mode smart card interface mode operation

• TEND flag generation 11.0 etu after beginning of start bit

• High/low fixing control possible in addition to clock output ON/OFF control (set by SCR)

Note: etu: Elementary time unit (time for transfer of 1 bit)

1045

Notes: When the smart card interface is used, be sure to make the 1 setting shown for bit 5.

*1 When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to

transmit data before transmission. In reception, the parity bit is checked for the parity

(even or odd) specified by the O/E bit.

*2 When even parity is set, parity bit addition is performed in transmission so that the total

number of 1 bits in the transmit character plus the parity bit is even.

In reception, a check is performed to see if the total number of 1 bits in the receive

character plus the parity bit is even.

*3 When odd parity is set, parity bit addition is performed in transmission so that the total

number of 1 bits in the transmit character plus the parity bit is odd.

In reception, a check is performed to see if the total number of 1 bits in the receive

character plus the parity bit is odd.

BRR1—Bit Rate Register 1 H'FF81 SCI1, Smart Card Interface 1

R/W

Bit

Initial value

Read/Write

Set the serial transmit/receive bit rate

Note: For details see section 13.2.8, Bit Rate Register (BRR).

1046

SCR1—Serial Control Register 1 H'FF82 SCI1

TIE

R/W

RIE

R/W

MPIE

R/W

CKE0

R/W

TEIE

R/W

CKE1

R/W

Bit

Initial value

Read/Write

Clock Enable 1 and 0

0Asynchronous

mode

Clocked

synchronous mode

Asynchronous

mode

Clocked

synchronous mode

1 Asynchronous

mode

Clocked

synchronous mode

Asynchronous

mode

Clocked

synchronous mode

Internal clock/SCK pin

functions as I/O port

Internal clock/SCK pin

functions as serial clock output

Internal clock/SCK pin

functions as clock output*9

Internal clock/SCK pin

functions as serial clock output

External clock/SCK pin

functions as clock input*10

External clock/SCK pin

functions as serial clock input

External clock/SCK pin

functions as clock input*10

External clock/SCK pin

functions as serial clock input

Transmit End Interrupt Enable

0Transmit-end interrupt (TEI) request disabled*8

1 Transmit-end interrupt (TEI) request enabled*8

Multiprocessor Interrupt Enable

0Multiprocessor interrupts disabled

(normal reception mode performed)

[Clearing conditions]

• When the MPIE bit is cleared to 0

• When MPB = 1 data is received

1 Multiprocessor interrupts enabled*7

Receive interrupt (RXI) requests, receive-error interrupt (ERI)

requests, and setting of the RDRF, FER, and ORER flags in

SSR are disabled until data with the multiprocessor bit set to

1 is received

Receive Enable

0Reception disabled*5

1 Reception enabled*6

Transmit Enable

0 Transmission disabled*3

1 Transmission enabled*4

Receive Interrupt Enable

0Receive-data-full interrupt (RXI)

request and receive-error interrupt

(ERI) request disabled*2

1 Receive-data-full interrupt (RXI)

request and receive-error interrupt

(ERI) request enabled

Transmit Interrupt Enable

0Transmit-data-empty interrupt

(TXI) request disabled*1

1 Transmit-data-empty interrupt

(TXI) request enabled

1047

Notes: *1 TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag,

then clearing it to 0, or clearing the TIE bit to 0.

*2 RXI and ERI interrupt request cancellation can be performed by reading 1 from the

RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or clearing the

RIE bit to 0.

*3 The TDRE flag in SSR is fixed at 1.

*4 In this state, serial transmission is started when transmit data is written to TDR and the

TDRE flag in SSR is cleared to 0.

SMR setting must be performed to decide the transfer format before setting the TE bit

to 1.

*5 Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which

retain their states.

*6 Serial reception is started in this state when a start bit is detected in asynchronous

mode or serial clock input is detected in clocked synchronous mode.

SMR setting must be performed to decide the transfer format before setting the RE bit

to 1.

*7 When receive data including MPB = 0 is received, receive data transfer from RSR to

RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR ,

is not performed. When receive data including MPB = 1 is received, the MPB bit in

SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and

ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER

flag setting is enabled.

*8 TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then

clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0.

*9 Outputs a clock of the same frequency as the bit rate.

*10 Inputs a clock with a frequency 16 times the bit rate.

1048

SCR1—Serial Control Register 1 H'FF82 SCI1, Smart Card Interface 1

TIE

R/W

RIE

R/W

MPIE

R/W

CKE0

R/W

TEIE

R/W

CKE1

R/W

Bit

Initial value

Read/Write

Clock Enable 1 and 0

SCMR

SMIF CKE1 CKE0

SCR Setting SCK Pin FunctionSMR

C/A, GM

Operates as port I/O pin

Outputs clock as SCK

output pin

Operates as SCK output

pin, with output fixed low

Outputs clock as SCK

output pin

Operates as SCK output

pin, with output fixed high

Outputs clock as SCK

output pin

See the SCI

Operate in the same way as for the normal SCI.

TDR1—Transmit Data Register 1 H'FF83 SCI1, Smart Card Interface 1

R/W

Bit

Initial value

Read/Write

Store serial transmit data

1049

SSR1—Serial Status Register 1 H'FF84 SCI1

TDRE

R/(W)*9

RDRF

R/(W)*9

ORER

R/(W)*9

FER

R/(W)*9

PER

R/(W)*9

MPBT

R/W

TEND

MPB

Bit

Initial value

Read/Write

Multiprocessor Bit Transfer

0Data with a 0 multi-processor

bit is transmitted

1 Data with a 1 multi-processor

bit is transmitted

Multiprocessor Bit

0[Clearing condition]

When data with a 0 multiprocessor

bit is received

1 [Setting condition]

When data with a 1 multiprocessor

bit is received

Transmit End

0[Clearing conditions]

• When 0 is written in TDRE after reading TDRE = 1

• When the DTC is activated by a TXI interrupt and

writes data to TDR

1 [Setting conditions]

• When the TE bit in SCR is 0

• When TDRE = 1 at transmission of the last bit of

a 1-byte serial transmit character

Parity Error

0[Clearing condition]

When 0 is written in PER after reading PER = 1

1 [Setting condition]

When, in reception, the number of 1 bits in the receive

data plus the parity bit does not match the parity setting

(even or odd) specified by the O/E bit in SMR*6

Framing Error

0[Clearing condition]

When 0 is written in FER after reading FER = 1

1 [Setting condition]

When the SCI checks whether the stop bit at the end of the receive

data when reception ends, and the stop bit is 0

Overrun Error

0[Clearing condition]

When 0 is written in ORER after reading ORER = 1

1 [Setting condition]

When the next serial reception is completed while RDRF = 1*2

Receive Data Register Full *8

0[Clearing conditions]

• When 0 is written in RDRF after reading RDRF = 1

• When the DTC is activated by an RXI interrupt and reads data from RDR

1 [Setting condition]

When serial reception ends normally and receive data is transferred from RSR to RDR

Transmit Data Register Empty

0[Clearing conditions]

• When 0 is written in TDRE after reading TDRE = 1

• When the DTC is activated by a TXI interrupt and writes data to TDR

1[Setting conditions]

• When the TE bit in SCR is 0

• When data is transferred from TDR to TSR and data can be written in TDR

1050

Notes: *1 The ORER flag is not affected and retains its previous state when the RE bit in SCR is

cleared to 0.

*2 The receive data prior to the overrun error is retained in RDR, and the data received

subsequently is lost. Also, subsequent serial reception cannot be continued while the

ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be

continued, either.

*3 The FER flag is not affected and retains its previous state when the RE bit in SCR is

cleared to 0.

*4 In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit

is not checked. If a framing error occurs, the receive data is transferred to RDR but the

RDRF flag is not set. Also, subsequent serial reception cannot be continued while the

FER flag is set to 1. In clocked synchronous mode, serial transmission cannot be

continued, either.

*5 The PER flag is not affected and retains its previous state when the RE bit in SCR is

cleared to 0.

*6 If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not

set. Also, subsequent serial reception cannot be continued while the PER flag is set to

1. In clocked synchronous mode, serial transmission cannot be continued, either.

*7 Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor

format.

*8 RDR and the RDRF flag are not affected and retain their previous values when an error

is detected during reception or when the RE bit in SCR is cleared to 0.

If reception of the next data is completed while the RDRF flag is still set to 1, an overrun

error will occur and the receive data will be lost.

*9 Only 0 can be written, to clear the flag.

1051

SSR1—Serial Status Register 1 H'FF84 SCI1, Smart Card Interface 1

TDRE

R/(W)*

RDRF

R/(W)*

ORER

R/(W)*

ERS

R/(W)*

PER

R/(W)*

MPBT

R/W

TEND

MPB

Bit

Initial value

Read/Write

Note: * Only 0 can be written, to clear the flag.

Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag,

which retains its previous state.

Error Signal Status

0Normal reception, with no error signal

[Clearing condition]

• Upon reset, and in standby mode or module stop mode

• When 0 is written to ERS after reading ERS = 1

1 Error signal sent from receiver indicating detection of parity error

[Setting condition]

When the low level of the error signal is sampled

Operate in the same way as for

the normal SCI.

Operate in the same way as for

the normal SCI.

RDR1—Receive Data Register 1 H'FF85 SCI1, Smart Card Interface 1

Bit

Initial value

Read/Write

Store serial receive data

1052

SCMR1—Smart Card Mode Register 1 H'FF86 SCI1, Smart Card Interface 1

—

SDIR

R/W

SMIF

R/W

SINV

R/W

—

Bit

Initial value

Read/Write

Smart Card Interface Mode Select

0 Operates as normal SCI (smart card interface function disabled)

1 Smart card interface function enabled

Smart Card Data Invert

0 TDR contents are transmitted without modification

Receive data is stored in RDR without modification

1 TDR contents are inverted before being transmitted

Receive data is stored in RDR in inverted form

Smart Card Data Transfer Direction

0 TDR contents are transmitted LSB-first

Receive data is stored in RDR LSB-first

1 TDR contents are transmitted MSB-first

Receive data is stored in RDR MSB-first

1053

SMR2—Serial Mode Register 2 H'FF88 SCI2

C/A

R/W

CHR

R/W

O/E

R/W

STOP

R/W

CKS0

R/W

CKS1

R/W

Bit

Initial value

Read/Write

Clock Select 1 and 0

0ø clock

ø/4 clock

ø/16 clock

ø/64 clock

Multiprocessor Mode

0 Multiprocessor function disabled

1 Multiprocessor format selected

Parity Mode

0 Even parity

Odd parity

Parity Enable

0 Parity bit addition and checking disabled

Parity bit addition and checking enabled

Character Length

0 8-bit data

7-bit data

Communication Mode

0 Asynchronous mode

Clocked synchronous mode1

Stop Bit Length

1 stop bit: In transmission, a single 1 bit (stop bit)

is added to the end of a transmit character before

it is sent.

2 stop bits: In transmission, two 1 bits (stop bits)

are added to the end of a transmit character

before it is sent.

1054

Notes: *1 When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted and it is not

possible to choose between LSB-first or MSB-first transfer.

*2 When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to

transmit data before transmission. In reception, the parity bit is checked for the parity

(even or odd) specified by the O/E bit.

*3 When even parity is set, parity bit addition is performed in transmission so that the total

number of 1 bits in the transmit character plus the parity bit is even.

In reception, a check is performed to see if the total number of 1 bits in the receive

character plus the parity bit is even.

*4 When odd parity is set, parity bit addition is performed in transmission so that the total

number of 1 bits in the transmit character plus the parity bit is odd.

In reception, a check is performed to see if the total number of 1 bits in the receive

character plus the parity bit is odd.

1055

SMR2—Serial Mode Register 2 H'FF88 SCI2, Smart Card Interface 2

R/W

BLK

R/W

O/E

R/W

BCP1

R/W

CKS0

R/W

BCP0

R/W

CKS1

R/W

Bit

Initial value

Read/Write

Clock Select 1 and 0

0ø clock

ø/4 clock

ø/16 clock

ø/64 clock

Basic Clock Pulse

0 32 clock periods

64 clock periods

372 clock periods

256 clock periods

Parity Mode

0 Even parity*2

Odd parity*3

Parity Enable

0 Parity bit addition and checking disabled

Parity bit addition and checking enabled*1

Block Transfer Mode

0 Normal Smart Card interface mode operation

• Error signal transmission/detection and automatic data retransmission performed

• TXI interrupt generated by TEND flag

• TEND flag set 12.5 etu after start of transmission (11.0 etu in GSM mode)

Block transfer mode operation

• Error signal transmission/detection and automatic data retransmission not performed

• TXI interrupt generated by TDRE flag

• TEND flag set 11.5 etu after start of transmission (11.0 etu in GSM mode)

GSM Mode

0 Normal smart card interface mode operation

• TEND flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit

• Clock output ON/OFF control only

GSM mode smart card interface mode operation

• TEND flag generation 11.0 etu after beginning of start bit

• High/low fixing control possible in addition to clock output ON/OFF control (set by SCR)

Note: etu: Elementary time unit (time for transfer of 1 bit)

1056

Notes: When the smart card interface is used, be sure to make the 1 setting shown for bit 5.

*1 When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to

transmit data before transmission. In reception, the parity bit is checked for the parity

(even or odd) specified by the O/E bit.

*2 When even parity is set, parity bit addition is performed in transmission so that the total

number of 1 bits in the transmit character plus the parity bit is even.

In reception, a check is performed to see if the total number of 1 bits in the receive

character plus the parity bit is even.

*3 When odd parity is set, parity bit addition is performed in transmission so that the total

number of 1 bits in the transmit character plus the parity bit is odd.

In reception, a check is performed to see if the total number of 1 bits in the receive

character plus the parity bit is odd.

BRR2—Bit Rate Register 2 H'FF89 SCI2, Smart Card Interface 2

R/W

Bit

Initial value

Read/Write

Set the serial transmit/receive bit rate

Note: For details see section 13.2.8, Bit Rate Register (BRR).

1057

SCR2—Serial Control Register 2 H'FF8A SCI2

TIE

R/W

RIE

R/W

MPIE

R/W

CKE0

R/W

TEIE

R/W

CKE1

R/W

Bit

Initial value

Read/Write

Clock Enable 1 and 0

0Asynchronous

mode

Clocked

synchronous mode

Asynchronous

mode

Clocked

synchronous mode

1 Asynchronous

mode

Clocked

synchronous mode

Asynchronous

mode

Clocked

synchronous mode

Internal clock/SCK pin

functions as I/O port

Internal clock/SCK pin

functions as serial clock output

Internal clock/SCK pin

functions as clock output*9

Internal clock/SCK pin

functions as serial clock output

External clock/SCK pin

functions as clock input*10

External clock/SCK pin

functions as serial clock input

External clock/SCK pin

functions as clock input*10

External clock/SCK pin

functions as serial clock input

Transmit End Interrupt Enable

0Transmit-end interrupt (TEI) request disabled*8

1 Transmit-end interrupt (TEI) request enabled*8

Multiprocessor Interrupt Enable

0Multiprocessor interrupts disabled

(normal reception mode performed)

[Clearing conditions]

• When the MPIE bit is cleared to 0

• When MPB = 1 data is received

1 Multiprocessor interrupts enabled*7

Receive interrupt (RXI) requests, receive-error interrupt (ERI)

requests, and setting of the RDRF, FER, and ORER flags in

SSR are disabled until data with the multiprocessor bit set to

1 is received

Receive Enable

0Reception disabled*5

1 Reception enabled*6

Transmit Enable

0 Transmission disabled*3

1 Transmission enabled*4

Receive Interrupt Enable

0Receive-data-full interrupt (RXI)

request and receive-error interrupt

(ERI) request disabled*2

1 Receive-data-full interrupt (RXI)

request and receive-error interrupt

(ERI) request enabled

Transmit Interrupt Enable

0Transmit-data-empty interrupt

(TXI) request disabled*1

1 Transmit-data-empty interrupt

(TXI) request enabled

1058

Notes: *1 TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag,

then clearing it to 0, or clearing the TIE bit to 0.

*2 RXI and ERI interrupt request cancellation can be performed by reading 1 from the

RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or clearing the

RIE bit to 0.

*3 The TDRE flag in SSR is fixed at 1.

*4 In this state, serial transmission is started when transmit data is written to TDR and the

TDRE flag in SSR is cleared to 0.

SMR setting must be performed to decide the transfer format before setting the TE bit

to 1.

*5 Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which

retain their states.

*6 Serial reception is started in this state when a start bit is detected in asynchronous

mode or serial clock input is detected in clocked synchronous mode.

SMR setting must be performed to decide the transfer format before setting the RE bit

to 1.

*7 When receive data including MPB = 0 is received, receive data transfer from RSR to

RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR ,

is not performed. When receive data including MPB = 1 is received, the MPB bit in

SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and

ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER

flag setting is enabled.

*8 TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then

clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0.

*9 Outputs a clock of the same frequency as the bit rate.

*10 Inputs a clock with a frequency 16 times the bit rate.

1059

SCR2—Serial Control Register 2 H'FF8A SCI2, Smart Card Interface 2

TIE

R/W

RIE

R/W

MPIE

R/W

CKE0

R/W

TEIE

R/W

CKE1

R/W

Bit

Initial value

Read/Write

Clock Enable 1 and 0

SCMR

SMIF CKE1 CKE0

SCR Setting SCK Pin FunctionSMR

C/A, GM

Operates as port I/O pin

Outputs clock as SCK

output pin

Operates as SCK output

pin, with output fixed low

Outputs clock as SCK

output pin

Operates as SCK output

pin, with output fixed high

Outputs clock as SCK

output pin

See the SCI

Operate in the same way as for the normal SCI.

TDR2—Transmit Data Register 2 H'FF8B SCI2, Smart Card Interface 2

R/W

Bit

Initial value

Read/Write

Store serial transmit data

1060

SSR2—Serial Status Register 2 H'FF8C SCI2

TDRE

R/(W)*9

RDRF

R/(W)*9

ORER

R/(W)*9

FER

R/(W)*9

PER

R/(W)*9

MPBT

R/W

TEND

MPB

Bit

Initial value

Read/Write

Multiprocessor Bit Transfer

0Data with a 0 multi-processor

bit is transmitted

1 Data with a 1 multi-processor

bit is transmitted

Multiprocessor Bit

0[Clearing condition]

When data with a 0 multiprocessor

bit is received

1 [Setting condition]

When data with a 1 multiprocessor

bit is received

Transmit End

0[Clearing conditions]

• When 0 is written in TDRE after reading TDRE = 1

• When the DTC is activated by a TXI interrupt and

writes data to TDR

1 [Setting conditions]

• When the TE bit in SCR is 0

• When TDRE = 1 at transmission of the last bit of

a 1-byte serial transmit character

Parity Error

0[Clearing condition]

When 0 is written in PER after reading PER = 1

1 [Setting condition]

When, in reception, the number of 1 bits in the receive

data plus the parity bit does not match the parity setting

(even or odd) specified by the O/E bit in SMR*6

Framing Error

0[Clearing condition]

When 0 is written in FER after reading FER = 1

1 [Setting condition]

When the SCI checks whether the stop bit at the end of the receive

data when reception ends, and the stop bit is 0

Overrun Error

0[Clearing condition]

When 0 is written in ORER after reading ORER = 1

1 [Setting condition]

When the next serial reception is completed while RDRF = 1*2

Receive Data Register Full *8

0 [Clearing conditions]

• When 0 is written in RDRF after reading RDRF = 1

• When the DTC is activated by an RXI interrupt and reads data from RDR

1 [Setting condition]

When serial reception ends normally and receive data is transferred from RSR to RDR

Transmit Data Register Empty

0[Clearing conditions]

• When 0 is written in TDRE after reading TDRE = 1

• When the DTC is activated by a TXI interrupt and writes data to TDR

1[Setting conditions]

• When the TE bit in SCR is 0

• When data is transferred from TDR to TSR and data can be written in TDR

1061

Notes: *1 The ORER flag is not affected and retains its previous state when the RE bit in SCR is

cleared to 0.

*2 The receive data prior to the overrun error is retained in RDR, and the data received

subsequently is lost. Also, subsequent serial reception cannot be continued while the

ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be

continued, either.

*3 The FER flag is not affected and retains its previous state when the RE bit in SCR is

cleared to 0.

*4 In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit

is not checked. If a framing error occurs, the receive data is transferred to RDR but the

RDRF flag is not set. Also, subsequent serial reception cannot be continued while the

FER flag is set to 1. In clocked synchronous mode, serial transmission cannot be

continued, either.

*5 The PER flag is not affected and retains its previous state when the RE bit in SCR is

cleared to 0.

*6 If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not

set. Also, subsequent serial reception cannot be continued while the PER flag is set to

1. In clocked synchronous mode, serial transmission cannot be continued, either.

*7 Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor

format.

*8 RDR and the RDRF flag are not affected and retain their previous values when an error

is detected during reception or when the RE bit in SCR is cleared to 0.

If reception of the next data is completed while the RDRF flag is still set to 1, an overrun

error will occur and the receive data will be lost.

*9 Only 0 can be written, to clear the flag.

1062

SSR2—Serial Status Register 2 H'FF8C SCI2, Smart Card Interface 2

TDRE

R/(W)*

RDRF

R/(W)*

ORER

R/(W)*

ERS

R/(W)*

PER

R/(W)*

MPBT

R/W

TEND

MPB

Bit

Initial value

Read/Write

Note: * Only 0 can be written, to clear the flag.

Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag,

which retains its previous state.

Error Signal Status

0Normal reception, with no error signal

[Clearing condition]

• Upon reset, and in standby mode or module stop mode

• When 0 is written to ERS after reading ERS = 1

1 Error signal sent from receiver indicating detection of parity error

[Setting condition]

When the low level of the error signal is sampled

Operate in the same way as for

the normal SCI.

Operate in the same way as for

the normal SCI.

RDR2—Receive Data Register 2 H'FF8D SCI2, Smart Card Interface 2

Bit

Initial value

Read/Write

Store serial receive data

1063

SCMR2—Smart Card Mode Register 2 H'FF8E SCI2, Smart Card Interface 2

—

SDIR

R/W

SMIF

R/W

SINV

R/W

—

Bit

Initial value

Read/Write

Smart Card Interface Mode Select

0 Operates as normal SCI (smart card interface function disabled)

1 Smart card interface function enabled

Smart Card Data Invert

0 TDR contents are transmitted without modification

Receive data is stored in RDR without modification

1 TDR contents are inverted before being transmitted

Receive data is stored in RDR in inverted form

Smart Card Data Transfer Direction

0 TDR contents are transmitted LSB-first

Receive data is stored in RDR LSB-first

1 TDR contents are transmitted MSB-first

Receive data is stored in RDR MSB-first

ADDRA—A/D Data Register A H'FF90 A/D Converter

ADDRB—A/D Data Register B H'FF92 A/D Converter

ADDRC—A/D Data Register C H'FF94 A/D Converter

ADDRD—A/D Data Register D H'FF96 A/D Converter

AD9

AD8

AD7

AD6

AD5

AD2

AD4

AD3

Bit

Initial value

Read/Write

AD1

AD0

—

1064

ADCSR—A/D Control/Status Register H'FF98 A/D Converter

ADF

R/(W)

ADIE

R/W

ADST

R/W

SCAN

R/W

CH3

R/W

CH0

R/W

CH2

R/W

CH1

R/W*

Bit

Initial value

Read/Write

Note: * Only 0 can be written, to clear the flag.

Scan Mode

0Single mode

1 Scan mode

A/D Interrupt Enable

0A/D conversion end interrupt (ADI) request disabled

1 A/D conversion end interrupt (ADI) request enabled

A/D End Flag

0[Clearing conditions]

• When 0 is written in the to ADF flag after reading ADF = 1

• When the DTC is activated by an ADI interrupt and ADDR is read

1 [Setting conditions]

• Single mode: When A/D conversion ends

• Scan mode: When A/D conversion ends on all specified channels

A/D Start

0A/D conversion stopped

1• Single mode: A/D conversion is started. Cleared to 0 automatically

when conversion on the specified channel ends

• Scan mode: A/D conversion is started. Conversion continues

sequentially on the selected channels until ADST is cleared to

0 by software, a reset, or a transition to standby mode or module

stop mode

Channel Select 2 to 0

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AN8

AN9

AN10

AN11

AN0

AN0, AN1

AN0 to AN2

AN0 to AN3

AN4

AN4, AN5

AN4 to AN6

AN4 to AN7

AN8

AN8, AN9

AN8 to AN10

AN8 to AN11

CH1 CH0 Single Mode

(SCAN = 0) Scan Mode

(SCAN = 1)

CH3

CH2

Channel Select 3

0AN8 to AN11 are group 0 analog input pins

1 AN0 to AN3 are group 0 analog input pins,

AN4 to AN7 are group 1 analog input pins

1065

ADCR—A/D Control Register H'FF99 A/D Converter

TRGS1

R/W

TRGS0

R/W

—

CKS1

R/W

—

CKS0

R/W

—

Bit

Initial value

Read/Write

Timer Trigger Select

0 A/D conversion start by software is enabled

A/D conversion start by TPU conversion start trigger is enabled

Setting prohibited

A/D conversion start by external trigger pin (ADTRG) is enabled

Clock Select

0 Conversion time = 530 states (max.)

Conversion time = 266 states (max.)

Conversion time = 134 states (max.)

Conversion time = 68 states (max.)

1066

TCSR1—Timer Control/Status Register 1 H'FFA2(W), H'FFA2(R) WDT1

Bit

Initial value

Read/Write

OVF

R/(W)*

WT/IT

R/W

TME

R/W

PSS

R/W

RST/NMI

R/W

CKS0

R/W

CKS2

R/W

CKS1

R/W

Timer Enable

0 TCNT is initialized to H'00 and halted

TCNT counts1

Overflow Flag

Note: * Only a 0 may be written to this bit to clear the flag.

TCSR1 register differs from other registers in being more difficult to write to.

For details see section 12.2.4, Notes on Register Access.

Timer Mode Select

0 Interval timer mode: WDT1 requests an interval timer interrupt (WOVI) from the CPU when the TCNT overflows

Watchdog timer mode: WDT1 requests a reset or an NMI interrupt from the CPU when the TCNT overflows

Prescaler Select

0 The TCNT counts frequency-

division clock pulses of the

ø based prescaler (PSM)

The TCNT counts frequency-

division clock pulses of the

ø SUB-based prescaler (PSS)

Reset or NMI

0 NMI request

Internal reset request1

Clock Select 2 to 0

ø/2

ø/64

ø/128

ø/512

ø/2048

ø/8192

ø/32768

ø/131072

øSUB/2

øSUB/4

øSUB/8

øSUB/16

øSUB/32

øSUB/64

øSUB/128

øSUB/256

25.6 µs

819.2 µs

1.6 ms

6.6 ms

26.2 ms

104.9 ms

419.4 ms

1.68 s

15.6 ms

31.3 ms

62.5 ms

125 ms

250 ms

500 ms

1 s

2 s

CKS2

PSS CKS1 CKS0 Clock Overflow Period*

(where ø = 20 MHz)

(where ø SUB = 32.768 kHz)

Note: *An overflow period is the time interval between the start of

counting up from H'00 on the TCNT and the occurrence of a

TCNT overflow.

[Clearing conditions]

• Cleared when 0 is written to the TME bit (Only applies to WDT1)

• Cleared by reading TCSR when OVF = 1, then write 0 in OVF

[Setting condition]

When TCNT overflows (changes from H'FF to H'00)

(When internal reset request generation is selected in watchdog timer mode,

OVF is cleared automatically by the internal reset)

1067

TCNT1—Timer Counter 1 H'FFA2(W), H'FFA3(R) WDT1

R/W

Bit

Initial value

Read/Write

Up-counter

Note: TCNT is write-protected by a password to prevent accidental overwriting.

For details see section 12.2.4, Notes on Register Access.

1068

FLMCR1—Flash Memory Control Register 1 H'FFA8 Flash Memory

FWE

—*

SWE

R/W

ESU

R/W

PSU

R/W

Bit

Initial value

Read/Write

Program

0 Program mode cleared

1 Transition to program mode

[Setting condition]

When FWE = 1, SWE = 1, and PSU = 1

Erase

0 Erase mode cleared

1 Transition to erase mode

[Setting condition]

When FWE = 1, SWE = 1, and ESU = 1

Program-Verify

0 Program-verify mode cleared

1 Transition to program-verify mode

[Setting condition]

When FWE = 1 and SWE = 1

Erase-verify

0 Erase-verify mode cleared

1 Transition to erase-verify mode

[Setting condition]

When FWE = 1 and SWE = 1

Note: * Determined by the state of the FWE pin.

Program Setup Bit

0 Program setup cleared

Program setup

[Setting condition]

When FWE = 1 and SWE = 1

Erase Setup Bit

0 Erase setup cleared

Erase setup

[Setting condition]

When FWE = 1 and SWE = 1

Software Write Enable Bit

0 Writes disabled

Writes enabled

[Setting condition]

When FWE = 1

Flash Write Enable Bit

0 When a low level is input to the FWE pin (hardware-protected state)

When a high level is input to the FWE pin

1069

FLMCR2—Flash Memory Control Register 2 H'FFA9 Flash Memory

FLER

—

Bit

Initial value

Read/Write

Flash Memory Error

0 Flash memory is operating normally

Flash memory program/erase protection (error protection) is disabled

[Clearing condition]

Power-on reset or hardware standby mode

1 An error has occurred during flash memory programming/erasing

Flash memory program/erase protection (error protection) is enabled

[Setting condition]

See section 20.8.3, Error Protection

1070

EBR1—Erase Block Register 1 H'FFAA Flash Memory

EBR2—Erase Block Register 2 H'FFAB Flash Memory

EB7

R/W

EB6

R/W

EB5

R/W

EB4

R/W

EB3

R/W

EB0

R/W

EB2

R/W

EB1

R/W

—

R/W

—

R/W

—

R/W

—

R/W

—

R/W

EB8

R/W

—

R/W

EB9

R/W

Bit

Initial value

Read/Write

EBR1

Bit

Initial value

Read/Write

EBR2

Specify the flash memory erase area

Block (Size) Addresses

EB0 (1 kB)

EB1 (1 kB)

EB2 (1 kB)

EB3 (1 kB)

EB4 (28 kB)

EB5 (16 kB)

EB6 (8 kB)

EB7 (8 kB)

EB8 (32 kB)

EB9 (32 kB)

H'000000–H'0003FF

H'000400–H'0007FF

H'000800–H'000BFF

H'000C00–H'000FFF

H'001000–H'007FFF

H'008000–H'00BFFF

H'00C000–H'00DFFF

H'00E000–H'00FFFF

H'010000–H'017FFF

H'018000–H'01FFFF

FLPWCR—Flash Memory Power Control Register H'FFAC Flash Memory

PDWND

R/W

—

Bit

Initial value

Read/Write

Power-Down Disable

0 Transition to flash memory power-down mode enabled

1 Transition to flash memory power-down mode disabled

1071

PORT1—Port 1 Register H'FFB0 Port

P17

—*

P16

—*

P15

—*

P14

—*

P13

—*

P10

—*

P12

—*

P11

—*

Bit

Initial value

Read/Write

Note: * Determined by state of pins P17 to P10.

State of the port 1 pins

PORT2—Port 2 Register H'FFB1 Port

P27

—*

P26

—*

P25

—*

P24

—*

P23

—*

P20

—*

P22

—*

P21

—*

Bit

Initial value

Read/Write

Note: * Determined by state of pins P27 to P20.

State of the port 2 pins

PORT3—Port 3 Register H'FFB2 Port

P37

—*

P36

—*

P35

—*

P34

—*

P33

—*

P30

—*

P32

—*

P31

—*

Bit

Initial value

Read/Write

Note: * Determined by state of pins P37 to P30.

State of the port 3 pins

1072

PORT4—Port 4 Register H'FFB3 Port

P47

—*

P46

—*

P45

—*

P44

—*

P43

—*

P40

—*

P42

—*

P41

—*

Bit

Initial value

Read/Write

Note: * Determined by state of pins P47 to P40.

State of the port 4 pins

PORT5—Port 5 Register H'FFB4 Port

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

P50

—*

P52

—*

P51

—*

Bit

Initial value

Read/Write

Note: * Determined by state of pins P52 to P50.

State of the port 5 pins

PORT9—Port 9 Register H'FFB8 Port

P97

—*

P96

—*

P95

—*

P94

—*

P93

—*

P90

—*

P92

—*

P91

—*

Bit

Initial value

Read/Write

Note: * Determined by state of pins P97 to P90.

State of the port 9 pins

1073

PORTA—Port A Register H'FFB9 Port

PA7

—*

PA6

—*

PA5

—*

PA4

—*

PA3

—*

PA0

—*

PA2

—*

PA1

—*

Bit

Initial value

Read/Write

Note: * Determined by state of pins PA7 to PA0.

State of the port A pins

PORTB—Port B Register H'FFBA Port

PB7

—*

PB6

—*

PB5

—*

PB4

—*

PB3

—*

PB0

—*

PB2

—*

PB1

—*

Bit

Initial value

Read/Write

Note: * Determined by state of pins PB7 to PB0.

State of the port B pins

PORTC—Port C Register H'FFBB Port

PC7

—*

PC6

—*

PC5

—*

PC4

—*

PC3

—*

PC0

—*

PC2

—*

PC1

—*

Bit

Initial value

Read/Write

Note: * Determined by state of pins PC7 to PC0.

State of the port C pins

1074

PORTD—Port D Register H'FFBC Port

PD7

—*

PD6

—*

PD5

—*

PD4

—*

PD3

—*

PD0

—*

PD2

—*

PD1

—*

Bit

Initial value

Read/Write

Note: * Determined by state of pins PD7 to PD0.

State of the port D pins

PORTE—Port E Register H'FFBD Port

PE7

—*

PE6

—*

PE5

—*

PE4

—*

PE3

—*

PE0

—*

PE2

—*

PE1

—*

Bit

Initial value

Read/Write

Note: * Determined by state of pins PE7 to PE0.

State of the port E pins

PORTF—Port F Register H'FFBE Port

PF7

—*

PF6

—*

PF5

—*

PF4

—*

PF3

—*

PF0

—*

PF2

—*

—

Undefined

—

Bit

Initial value

Read/Write

Note: * Determined by state of pins PF7 to PF2, PF0.

State of the port F pins

1075

Appendix C I/O Port Block Diagrams

C.1 Port 1 Block Diagrams

P1nDDR

Reset

Internal data bus

Internal address bus

WDDR1

Reset

WDR1

P1nDR

P1n *

RDR1

RPOR1

PPG module

TPU module

Pulse output enable

Pulse output

Output compare

Output/PWM output enable

Output compare output/

PWM output

Input capture input

WDDR1

WDR1

RDR1

RPOR1

n= 0 or 1

Note: *

: Write to P1DDR

: Write to P1DR

: Read P1DR

: Read port 1

Legend

Priority order: Output compare output > PWM output

pulse output > DR output

Figure C-1 (a) Port 1 Block Diagram (Pins P10 and P11)

1076

P1nDDR

Reset

WDDR1

Reset

WDR1

P1nDR

P1n

RDR1

RPOR1

PPG module

TPU module

Pulse output enable

Output compare output/

PWM output enable

Output compare output/

PWM output

Pulse output

External clock input

Input capture input

Legend

WDDR1: Write to P1DDR

WDR1: Write to P1DR

RDR1: Read P1DR

RPOR1: Read port 1

n = 2 or 3

Note: * Priority order: output compare output/PWM output > pulse output > DR output

Internal data bus

Internal address bus

Figure C-1 (b) Port 1 Block Diagram (Pins P12 and P13)

1077

P14DDR

Reset

WDDR1

Reset

WDR1

P14DR

P14

RDR1

RPOR1

PPG module

TPU module

Pulse output enable

Interrupt controller

IRQ0 interrupt input

Output compare output/

PWM output enable

Output compare output/

PWM output

Pulse output

Input capture input

Legend

WDDR1: Write to P1DDR

WDR1: Write to P1DR

RDR1: Read P1DR

RPOR1: Read port 1

Note: * Priority order: output compare output/PWM output > pulse output > DR output

Internal data bus

Figure C-1 (c) Port 1 Block Diagram (Pin P14)

1078

P15DDR

Reset

WDDR1

Reset

WDR1

P15DR

P15

RDR1

RPOR1

PPG module

TPU module

Pulse output enable

Output compare output/

PWM output enable

Output compare output/

PWM output

Pulse output

Input capture input

External clock input

Legend

WDDR1: Write to P1DDR

WDR1: Write to P1DR

RDR1: Read P1DR

RPOR1: Read port 1

Note: * Priority order: output compare output/PWM output > pulse output > DR output

Internal data bus

Figure C-1 (d) Port 1 Block Diagram (Pin P15)

1079

P16DDR

Reset

WDDR1

Reset

Internal data bus

WDR1

P16DR

P16

RDR1

RPOR1

PPG module

TPU module

Pulse output enable

Output compare

Output/PWM output enable

Output compare output/

PWM output

Pulse output

Input capture input

Input controller

IRQ1 interrupt input

Legend

WDDR1

WDR1

RDR1

RPOR1

: Write to P1DDR

: Write to P1DR

: Read P1DR

: Read port 1

Note: *Priority order: output compare output/PWM output > pulse output > DR output

Figure C-1 (e) Port 1 Block Diagram (Pin P16)

1080

P17DDR

Reset

WDDR1

Reset

Internal data bus

WDR1

P17DR

P17

RDR1

RPOR1

PPG module

TPU module

Pulse output enable

Output compare output/

PWM output enable

Output compare output/

PWM output

Pulse output

Input capture input

External clock input

Legend

WDDR1

WDR1

RDR1

RPOR1

: Write to P1DDR

: Write to P1DR

: Read P1DR

: Read port 1

Note: * Priority order: output compare output/PWM output > pulse output > DR output

Figure C-1 (f) Port 1 Block Diagram (Pin P17)

1081

C.2 Port 2 Block Diagrams

P2nDDR

Reset

WDDR2

Reset

WDR2

P2nDR

P2n

RDR2

RPOR2

TPU module

Output compare output/

PWM output enable

Output compare output/

PWM output

Input capture input

Internal data bus

Legend

WDDR2

WDR2

RDR2

RPOR2

n = 0 to 3, 5, and 7

: Write to P2DDR

: Write to P2DR

: Read P2DR

: Read port 2

Note: * Priority order: output compare output/PWM output > pulse output > DR output

Figure C-2 (a) Port 2 Block Diagram (Pins P20 to P23, P25, and P27)

1082

P2nDDR

Reset

WDDR2

Reset

WDR2

P2nDR

P2n

RDR2

RPOR2

TPU module

Comparator

Analog input

Output compare output/

PWM output enable

Output compare output/

PWM output

Input capture input

Internal data bus

Legend

WDDR2

WDR2

RDR2

RPOR2

n = 4 or 6

: Write to P2DDR

: Write to P2DR

: Read P2DR

: Read port 2

Note: * Priority order: output compare output/PWM output > pulse output > DR output

Figure C-2 (b) Port 2 Block Diagram (Pins P24 and P26)

1083

C.3 Port 3 Block Diagrams

P30DDR

Reset

Internal data bus

WDDR3

Reset

WDR3

P30

RDR3

RODR3

RPOR3

TxD0

SCI module

Serial transmit enable

Serial transmit data

Notes: *1 Output enable signal

*2 Open drain control signal

P30DR

Reset

WODR3

P30ODR

Legend

WDDR3

WDR3

WODR3

RDR3

RPOR3

RODR3

: Write to P3DDR

: Write to P3DR

: Write to P3ODR

: Read P3DR

: Read port 3

: Read P3ODR

Figure C-3 (a) Port 3 Block Diagram (Pin P30)

1084

P31DDR

Reset

Internal data bus

WDDR3

Reset

WDR3

P31

RDR3

RODR3

RPOR3

SCI module

Serial receive data

enable

Serial receive data

RxD0

P31DR

Reset

WODR3

P31ODR

Notes: *1 Output enable signal

*2 Open drain control signal

Legend

WDDR3

WDR3

WODR3

RDR3

RPOR3

RODR3

: Write to P3DDR

: Write to P3DR

: Write to P3ODR

: Read P3DR

: Read port 3

: Read P3ODR

Figure C-3 (b) Port 3 Block Diagram (Pin P31)

1085

P32DDR

Reset

Internal data bus

WDDR3

Reset

WDR3

P32

RDR3

RODR3

RPOR3

SCI module

Serial clock output

enable

Serial clock input

enable

Serial clock output

SCK0

Interrupt controller

IRQ4 interrupt input

P32DR

Reset

WODR3

P32ODR

Serial clock input

SCK0

Notes: *1 Priority order: Serial clock output > DR output

*2 Output enable signal

*3 Open drain control signal

Legend

WDDR3

WDR3

WODR3

RDR3

RPOR3

RODR3

: Write to P3DDR

: Write to P3DR

: Write to P3ODR

: Read P3DR

: Read port 3

: Read P3ODR

Figure C-3 (c) Port 3 Block Diagram (Pin P32)

1086

P33DDR

Reset

Internal data bus

WDDR3

Reset

WDR3

P33

RDR3

RODR3

RPOR3

SCI module

Serial transmit enable

Serial transmit data

P33DR

Reset

WODR3

P33ODR

TxD1

Notes: *1 Output enable signal

*2 Open drain control signal

Legend

WDDR3

WDR3

WODR3

RDR3

RPOR3

RODR3

: Write to P3DDR

: Write to P3DR

: Write to P3ODR

: Read P3DR

: Read port 3

: Read P3ODR

Figure C-3 (d) Port 3 Block Diagram (Pin P33)

1087

P34DDR

Reset

Internal data bus

WDDR3

Reset

WDR3

P34

RDR3

RODR3

RPOR3

SCI module

Serial receive

data enable

Serial receive data

RxD1

P34DR

Reset

WODR3

P34ODR

Notes: *1 Output enable signal

*2 Open drain control signal

Legend

WDDR3

WDR3

WODR3

RDR3

RPOR3

RODR3

: Write to P3DDR

: Write to P3DR

: Write to P3ODR

: Read P3DR

: Read port 3

: Read P3ODR

Figure C-3 (e) Port 3 Block Diagram (Pin P34)

1088

P35DDR

Reset

Internal data bus

WDDR3

Reset

WDR3

P35

RDR3

RODR3

RPOR3

SCI module

IRQ5 interrupt input

Interrupt controller

Serial clock output

enable

Serial clock output

SCK1

Serial clock input

enable

P35DR

Reset

WODR3

P35ODR

Serial clock input

SCK1

Notes: *1 Priority order: IIC output > Serial clock output > DR output

*2 Output enable signal

*3 Open drain control signal

Legend

WDDR3

WDR3

WODR3

RDR3

RPOR3

RODR3

: Write to P3DDR

: Write to P3DR

: Write to P3ODR

: Read P3DR

: Read port 3

: Read P3ODR

Figure C-3 (f) Port 3 Block Diagram (Pin P35)

1089

P3nDDR

WDDR3

WDR3

P3n

RDR3

RODR3

RPOR3

P3nDR

WODR3

P3nODR

Reset

Internal data bus

Reset

*1 Output enable signal

*2 Open drain control signal

Notes:

Legend

WDDR3

WDR3

WODR3

RDR3

RPOR3

RODR3

n = 6 or 7

: Write to P3DDR

: Write to P3DR

: Write to P3ODR

: Read P3DR

: Read port 3

: Read P3ODR

Figure C-3 (g) Port 3 Block Diagram (Pins P36 and P37)

1090

C.4 Port 4 Block Diagram

P4n

RPOR4

Internal data bus

A/D converter module

Analog input

Legend

RPOR4 : Read port 4

n= 0 to 7

Figure C-4 Port 4 Block Diagram (Pins P40 to P47)

1091

C.5 Port 5 Block Diagrams

P5nDDR

WDDR5

WDR5

P5n

RDR5

RPOR5

P5nDR

Reset

Internal data bus

Reset

WDDR5

WDR5

RDR5

RPOR5

n = 0 to 2

: Write to P5DDR

: Write to P5DR

: Read P5DR

: Read port 5

Legend

Figure C-5 (a) Port 5 Block Diagram (Pins P50 to P52)

(H8S/2646, H8S/2646R, H8S/2645)

1092

P50DDR

WDDR5

WDR5

P50

RDR5

RPOR5

P50DR

Legend

WDDR5

WDR5

RDR5

RPOR5

: Write to P5DDR

: Write to P5DR

: Read P5DR

: Read port 5

Internal data bus

Reset

SCI module

Serial receive

data enable

Serial receive

data TxD2

Figure C-5 (b) Port 5 Block Diagram (Pin P50) (H8S/2648, H8S/2648R, H8S/2647)

1093

P51DDR

WDDR5

WDR5

P51

RDR5

RPOR5

P51DR

Internal data bus

Reset

SCI module

Serial receive

data enable

Serial receive

data TxD2

Legend

WDDR5

WDR5

RDR5

RPOR5

: Write to P5DDR

: Write to P5DR

: Read P5DR

: Read port 5

Figure C-5 (c) Port 5 Block Diagram (Pin P51) (H8S/2648, H8S/2648R, H8S/2647)

1094

P52DDR

WDDR5

WDR5

P52DR

P52

RDR5

RPOR5

Legend

WDDR5

WDR5

RDR5

RPOR5

: Write to P5DDR

: Write to P5DR

: Read P5DR

: Read port 5

Internal data bus

Reset

SCI module

Serial clock

output enable

Serial clock

output SCK2

Serial clock

input enable

Serial clock

input SCK2

Note: *Priority order: Serial clock output > DR output

Figure C-5 (d) Port 5 Block Diagram (Pin P52) (H8S/2648, H8S/2648R, H8S/2647)

1095

C.6 Port 9 Block Diagram

P9n

RPOR9

Internal data bus

A/D converter module

Analog input

RPOR9

n= 0 to 7: Read port 9

Legend

Figure C-6 Port 9 Block Diagram (Pins P90 to P97)

1096

C.7 Port A Block Diagram

PAnPCR

Reset

Internal data bus

Internal address bus

WPCRA

Reset

WDRA

PAn

RDRA

RODRA

RPORA

PAnDR

Reset

WDDRA

PAnDDR

Reset

WODRA

RPCRA

PAnODR

Mode4/5/6

Address

enable

Notes: *1 Output enable signal

*2 Open drain control signal

WDDRA

WDRA

WODRA

WPCRA

RDRA

RPORA

RODRA

RPCRA

n = 0 to 7

: Write to PADDR

: Write to PADR

: Write to PAODR

: Write to PAPCR

: Read PADR

: Read port A

: Read PAODR

: Read PAPCR

Legend

Figure C-7 Port A Block Diagram (Pins PA0 to PA7)

1097

C.8 Port B Block Diagram

PBnPCR

Reset

Internal address bus

Internal data bus

WPCRB

Reset

WDRB

PBn

RDRB

RODRB

RPORB

PBnDR

Reset

WDDRB

PBnDDR

Reset

WODRB

RPCRB

PBnODR

Mode 4/5/6

Address

enable

Notes: *1 Output enable signal

*2 Open drain control signal

WDDRB

WDRB

WODRB

WPCRB

RDRB

RPORB

RODRB

RPCRB

n= 0 to 7

: Write to PBDDR

: Write to PBDR

: Write to PBODR

: Write to PBPCR

: Read PBDR

: Read port B

: Read PBODR

: Read PBPCR

Legend

Figure C-8 Port B Block Diagram (Pins PB0 to PB7)

1098

C.9 Port C Block Diagram

PCnPCR

Reset

Internal address bus

Internal data bus

WPCRC

Reset

WDRA

PCn

RDRC

RODRC

RPORC

PCnDR

Reset

WDDRA

PCnDDR

Reset

WODRC

RPCRC

PCnODR

Mode 4/5

Mode 6

Notes: *1 Output enable signal

*2 Open drain control signal

WDDRA

WDRA

WODRA

WPCRA

RDRA

RPORA

RODRA

RPCRA

n= 0 to 7

: Write to PCDDR

: Write to PCDR

: Write to PCODR

: Write to PCPCR

: Read PCDR

: Read port A

: Read PCODR

: Read PCPCR

Legend

Figure C-9 Port C Block Diagram (Pins PC0 to PC7)

1099

C.10 Port D Block Diagram

PDnPCR

Reset

Internal upper data bus

WPCRD

Reset

WDRD

External address

upper write

PDn

RDRD

RPORD

PDnDR

WDDRD

PDnDDR

RPCRD

Mode 7

Mode 4/5/6

External address

write

Reset

External address upper read

WDDRD

WDRD

WPCRD

RDRD

RPORD

RPCRD

n= 0 to 7

: Write to PDDDR

: Write to PDDR

: Write to PDPCR

: Read PDDR

: Read port D

: Read PDPCR

Legend

Figure C-10 Port D Block Diagram (Pins PD0 to PD7)

1100

C.11 Port E Block Diagram

PEnPCR

Reset

Internal upper data bus

Internal lower data bus

WPCRE

Reset

WDRE

PEn

RDRE

RPORE

PEnDR

WDDRE

PEnDDR

RPCRE

Mode 7

Mode 4/5/6

External address

write

Reset

External addres lower read

WDDRE

WDRE

WPCRE

RDRE

RPORE

RPCRE

n= 0 to 7

: Write to PEDDR

: Write to PEDR

: Write to PEPCR

: Read PEDR

: Read port E

: Read PEPCR

Legend

Figure C-11 Port E Block Diagram (Pins PE0 to PE7)

1101

C.12 Port F Block Diagrams

PF0DDR

Reset

Internal data bus

WDDRF

Reset

WDRF

PF0

RDRF

RPORF

IRQ interrupt input

PF0DR

WDDRF

WDRF

RDRF

RPORF

: Write to PFDDR

: Write to PFDR

: Read PFDR

: Read port F

Legend

Figure C-12 (a) Port F Block Diagram (Pin PF0)

1102

PF2DDR

Reset

Internal data bus

WDDRF

Reset

WDRF

PF2DR

PF2

RDRF

RPORF

Wait input

Bus controller

Wait enable

Mode 4/5/6

WDDRF

WDRF

RDRF

RPORF

: Write to PFDDR

: Write to PFDR

: Read PFDR

: Read port F

Legend

Figure C-12 (b) Port F Block Diagram (Pin PF2)

1103

PF3DDR

Reset

Internal data bus

WDDRF

Reset

WDRF

PF3DR

PF3

RDRF

RPORF

Bus controller

ADTRG input

IRQ3 interrupt input

LWR output

Mode 4/5/6

WDDRF

WDRF

RDRF

RPORF

: Write to PFDDR

: Write to PFDR

: Read PFDR

: Read port F

Legend

Figure C-12 (c) Port F Block Diagram (Pin PF3)

1104

PF4DDR

Reset

Internal data bus

Mode 4/5/6

WDDRF

Reset

WDRF

PF4DR

PF4

RDRF

RPORF

Bus controller

HWR output

WDDRF

WDRF

RDRF

RPORF

: Write to PFDDR

: Write to PFDR

: Read PFDR

: Read port F

Legend

Figure C-12 (d) Port F Block Diagram (Pin PF4)

1105

PF5DDR

Reset

Internal data bus

WDDRF

Reset

Mode 4/5/6

WDRF

PF5DR

PF5

RDRF

RPORF

Bus controller

RD output

WDDRF

WDRF

RDRF

RPORF

: Write to PFDDR

: Write to PFDR

: Read PFDR

: Read port F

Legend

Figure C-12 (e) Port F Block Diagram (Pin PF5)

1106

PF6DDR

Reset

Internal data bus

WDDRF

Reset

Mode 4/5/6

WDRF

PF6DR

PF6

RDRF

RPORF

Bus controller

AS output

WDDRF

WDRF

RDRF

RPORF

: Write to PFDDR

: Write to PFDR

: Read PFDR

: Read port F

Legend

Figure C-12 (f) Port F Block Diagram (Pin PF6)

1107

WDDRF

PF7

RDRF

RPORF

Reset

Internal data bus

Mode 4/5/6

PF7DDR

Note: * Set priority

WDDRF

WDRF

RDRF

RPORF

: Write to PFDDR

: Write to PFDR

: Read PFDR

: Read port F

Legend

Figure C-12 (g) Port F Block Diagram (Pin PF7)

1108

C.13 Port G Block Diagram

PHnDDR

Reset

Internal data bus

WDDRH

Reset

WDRH

PHn

RDRH

RPORH

PWM module

PWM output enable

PWM output

PHnDR

WDDRH

WDRH

RDRH

RPORH

n = 0 to 7

: Write to PHDDR

: Write to PHDR

: Read PHDR

: Read port H

Legend

Figure C-13 Port H Block Diagram (Pins PH0 to PH7)

1109

C.14 Port J Block Diagram

PJnDDR

Reset

WDDRJ

Reset

WDRJ

PJn

RDRJ

RPORJ

PJnDR

Internal data bus

PWM module

PWM output enable

PWM output

WDDRJ

WDRJ

RDRJ

RPORJ

n = 0 to 7

: Write to PJDDR

: Write to PJDR

: Read PJDR

: Read port J

Legend

Figure C-14 Port J Block Diagram (Pins PJ0 to PJ7)

1110

C.15 Port K Block Diagram

PKnDDR

WDDRK

WDRK

PKn

RDRK

RPORK

PKnDR

Reset

Internal data bus

WDDRK

WDRK

RDRK

RPORK

n = 6 or 7

: Write to PKDDR

: Write to PKDR

: Read PKDR

: Read port K

Legend

Figure C-15 Port K Block Diagram (Pins PK6 and PK7)

1111

Appendix D Pin States

D.1 Port States in Each Mode

Table D-1 I/O Port States in Each Processing State (H8S/2646, H8S/2646R, H8S/2645)

Port Name

Pin Name

MCU

Operating

Mode Reset

Hardware

Standby

Mode Software Standby Mode Program Execution State

Sleep Mode

Port 1 4 to 7 T T kept I/O port

Port 2 4 to 7 T T kept I/O port

Port 3 4 to 7 T T kept I/O port

Port 4 4 to 7 T T T Input port

Port 5 4 to 7 T T kept I/O port

Port 9 4 to 7 T T T Input port

Port A 4, 5

[Address output, OPE = 0]

[Address output, OPE = 1]

kept

[Segment, common output]

port

[Otherwise]

kept

[Address output]

A23 to A16

[Segment, common output]

SEG24 to SEG21

COM4 to COM1

[Otherwise]

I/O port

7 T T [Segment, common output]

port

[Otherwise]

kept

[Segment, common output]

SEG24 to SEG21

COM4 to COM1

[Otherwise]

I/O port

Port B 4, 5

[Address output, OPE = 0]

[Address output, OPE = 1]

kept

[Segment output]

port

[Otherwise]

kept

[Address output]

A15 to A8

[Segment output]

SEG16 to SEG9

[Otherwise]

I/O port

7 T T [Segment output]

port

[Otherwise]

kept

[Segment output]

SEG16 to SEG9

[Otherwise]

I/O port

1112

Port Name

Pin Name

MCU

Operating

Mode Reset

Hardware

Standby

Mode Software Standby Mode Program Execution State

Sleep Mode

Port C 4, 5 L T [OPE = 0]

[OPE = 1]

kept

A7 to A0

6 T T [Segment output]

port

[DDR = 1, OPE = 0]

[DDR = 1, OPE = 1]

kept

[DDR = 0]

kept

[Segment output]

SEG8 to SEG1

[DDR = 1]

A7 to A0

[DDR = 0]

Input port

7 T T [Segment output]

port

[Otherwise]

kept

[Segment output]

SEG8 to SEG1

[Otherwise]

I/O port

Port D 4 to 6 T T T Data bus

7 T T kept I/O port

Port E 4 to 6 8 bit

bus T T kept I/O port

16 bit

bus T T T Data bus

7 T T kept I/O port

PF7/ø 4 to 6 Clock

output T [DDR = 0]

[DDR = 1]

[DDR = 0]

[DDR = 1]

Clock output

7 T T [DDR = 0]

[DDR = 1]

[DDR = 0]

[DDR = 1]

Clock output

PF6/AS 4 to 6 H T [OPE = 0]

[OPE = 1]

7 T T [Segment output]

port

[Otherwise]

kept

[Segment output]

SEG20

[Otherwise]

I/O port

1113

Port Name

Pin Name

MCU

Operating

Mode Reset

Hardware

Standby

Mode Software Standby Mode Program Execution State

Sleep Mode

PF5/RD

PF4/HWR

4 to 6 H T [OPE = 0]

[OPE = 1]

RD, HWR

7 T T [Segment output]

port

[Otherwise]

kept

[Segment output]

SEG19, SEG18

[Otherwise]

I/O port

PF3/LWR 4 to 6 H T [OPE = 0]

[OPE = 1]

LWR

7 T T kept I/O port

PF2/WAIT 4 to 6 T T [Segment output]

port

[Otherwise]

kept

[WAITE = 1]

WAIT

7 T T [Segment output]

port

[Otherwise]

kept

[Segment output]

SEG17

[Otherwise]

I/O port

PF0 4 to 7 T T kept I/O port

Port H 4 to 7 T T kept I/O port

Port J 4 to 7 T T kept I/O port

Port K 4 to 7 T T kept I/O port

Legend:

H : High level

L : Low level

T : High impedance

kept : Input port becomes high-impedance, output port retains state

Port : Determined by port setting (input is high-impedance)

DDR : Data direction register

OPE : Output port enable

WAITE : Wait input enable

1114

Table D-2 I/O Port States in Each Processing State (H8S/2648, H8S/2648R, H8S/2647)

Port Name

Pin Name

MCU

Operating

Mode Reset

Hardware

Standby

Mode Software Standby Mode Program Execution State

Sleep Mode

Port 1 4 to 7 T T kept I/O port

Port 2 4 to 7 T T kept I/O port

Port 3 4 to 7 T T kept I/O port

Port 4 4 to 7 T T T Input port

Port 5 4 to 7 T T kept I/O port

Port 9 4 to 7 T T T Input port

Port A 4, 5

[Address output, OPE = 0]

[Address output, OPE = 1]

kept

[Segment, common output]

port

[Otherwise]

kept

[Address output]

A23 to A16

[Segment, common output]

SEG40 to SEG37

COM4 to COM1

[Otherwise]

I/O port

7 T T [Segment, common output]

port

[Otherwise]

kept

[Segment, common output]

SEG40 to SEG37

COM4 to COM1

[Otherwise]

I/O port

Port B 4, 5

[Address output, OPE = 0]

[Address output, OPE = 1]

kept

[Segment output]

port

[Otherwise]

kept

[Address output]

A15 to A8

[Segment output]

SEG32 to SEG25

[Otherwise]

I/O port

7 T T [Segment output]

port

[Otherwise]

kept

[Segment output]

SEG32 to SEG25

[Otherwise]

I/O port

1115

Port Name

Pin Name

MCU

Operating

Mode Reset

Hardware

Standby

Mode Software Standby Mode Program Execution State

Sleep Mode

Port C 4, 5 L T [OPE = 0]

[OPE = 1]

kept

A7 to A0

6 T T [Segment output]

port

[DDR = 1, OPE = 0]

[DDR = 1, OPE = 1]

kept

[DDR = 0]

kept

[Segment output]

SEG24 to SEG17

[DDR = 1]

A7 to A0

[DDR = 0]

Input port

7 T T [Segment output]

port

[Otherwise]

kept

[Segment output]

SEG24 to SEG17

[Otherwise]

I/O port

Port D 4 to 6 T T T Data bus

7 T T kept I/O port

Port E 4 to 6 8 bit

bus T T kept I/O port

16 bit

bus T T T Data bus

7 T T kept I/O port

PF7/ø 4 to 6 Clock

output T [DDR = 0]

[DDR = 1]

[DDR = 0]

[DDR = 1]

Clock output

7 T T [DDR = 0]

[DDR = 1]

[DDR = 0]

[DDR = 1]

Clock output

PF6/AS 4 to 6 H T [OPE = 0]

[OPE = 1]

7 T T [Segment output]

port

[Otherwise]

kept

[Segment output]

SEG20

[Otherwise]

I/O port

1116

Port Name

Pin Name

MCU

Operating

Mode Reset

Hardware

Standby

Mode Software Standby Mode Program Execution State

Sleep Mode

PF5/RD

PF4/HWR

4 to 6 H T [OPE = 0]

[OPE = 1]

RD, HWR

7 T T [Segment output]

port

[Otherwise]

kept

[Segment output]

SEG19, SEG18

[Otherwise]

I/O port

PF3/LWR 4 to 6 H T [OPE = 0]

[OPE = 1]

LWR

7 T T kept I/O port

PF2/WAIT 4 to 6 T T [Segment output]

port

[Otherwise]

kept

[WAITE = 1]

WAIT

7 T T [Segment output]

port

[Otherwise]

kept

[Segment output]

SEG17

[Otherwise]

I/O port

PF0 4 to 7 T T kept I/O port

Port H 4 to 7 T T kept I/O port

Port J 4 to 7 T T kept I/O port

Port K 4 to 7 T T kept I/O port

Legend:

H : High level

L : Low level

T : High impedance

kept : Input port becomes high-impedance, output port retains state

Port : Determined by port setting (input is high-impedance)

DDR : Data direction register

OPE : Output port enable

WAITE : Wait input enable

1117

Appendix E Timing of Transition to and Recovery from

Hardware Standby Mode

Timing of Transition to Hardware Standby Mode

(1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low at

least 10 states before the STBY signal goes low, as shown below. RES must remain low until

STBY signal goes low (delay from STBY low to RES high: 0 ns or more).

STBY

RES

t2≥0ns

t1≥10tcyc

Figure E-1 Timing of Transition to Hardware Standby Mode

(2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do

not need to be retained, RES does not have to be driven low as in (1).

Timing of Recovery from Hardware Standby Mode

Drive the RES signal low and the NMI signal high approximately 100 ns or more before STBY

goes high to execute a power-on reset.

tOSC

tNMIRH

t≥100ns

NMI

STBY

RES

Figure E-2 Timing of Recovery from Hardware Standby Mode

1118

Appendix F Package Dimensions

Figure F-1 shows the package dimensions of the H8S/2646R and H8S/2648R and figure F-2

shows that of the H8S/2646, H8S/2645, H8S/2648, and H8S/2647.

Hitachi Code

JEDEC

JEITA

Mass

(reference value)

FP-144J

−

Conforms

2.4 g

*Dimension including the plating thickness

Base material dimension

0.10 M

22.0 ± 0.2

144

0.5

0.10

3.05 Max

0° − 8°

22.0 ± 0.2

108

109

0.17 ± 0.05

2.70

0.22 ± 0.05

0.5 ± 0.1

1.0

0.10

+0.15

−0.10

1.25

0.20 ± 0.04

0.15 ± 0.04

Unit: mm

Figure F-1 FP-144J Package Dimension (H8S/2646R, H8S/2648R)

1119

Hitachi Code

JEDEC

JEITA

Mass

(reference value)

FP-144G

−

Conforms

2.4 g

*Dimension including the plating thickness

Base material dimension

0.10 M

22.0 ± 0.2

144

0.5

0.10

3.05 Max

0° − 8°

22.0 ± 0.2

108

109

0.17 ± 0.05

2.70

0.22 ± 0.05

0.5 ± 0.1

1.0

0.10

+0.15

−0.10

1.25

0.20 ± 0.04

0.15 ± 0.04

Unit: mm

Figure F-2 FP-144G Package Dimension (H8S/2646, H8S/2645, H8S/2648, H8S/2647)

1120

H8S/2646 Series, H8S/2646R F-ZTAT™,

H8S/2648R F-ZTAT™ Hardware Manual

Publication Date: 1st Edition, December 1999

4th Edition, September 2002

Published by: Business Operation Division

Semiconductor & Integrated Circuits

Hitachi, Ltd.

Edited by: Technical Documentation Group

Hitachi Kodaira Semiconductor Co., Ltd.