Features
•Pin-programmable Mode
•Supply Voltage Range 1.55V to 3. 6V
•PHY IC_USB1.0 Downstream Port
•Bridge USB2.0 Section 7 to IC_USB1.0
•Bridge IC_USB1.0 to USB2.0 Section 7
•3.3V Voltage Reference
•Two 70mA LDO Voltage Regulators
•Less Than 5µA Static Current on Each Supply
•Slew Rate Control to Minimize Radiated EMI
•ESD 4kV Compliant with USB UICC
•Applications:
– Mobile USB UICC (ETSI 102 600), PC USB UICC, Token USB
Description
The AT73C260 is an Inter Chip USB transceiver fully compliant with the Universal
Serial Bus Specification, and more specifically with the IC_USB1.0 supplement. The
AT73C260 is a bidirectional differential interface. The AT73C260 is ideal for applica-
tions in mobile devices, PCs and USB tokens making use of an USB UICC.
The AT73C260’s upstream facing port may be connected to three different interfaces:
• Digital
• USB2.0 section 7 with or without cable
• IC_USB1.0
The AT73C2 60’s down strea m port complies with IC_U SB1.0. T he AT73C 260’s mode
is selected by three pins. When PVCC is powered by 3.3V and pull down resistors are
added on PDM and PDP, the AT73C260’s downstream port complies with USB2.0
section 7.
The AT73C260 includes a 3.5V Supply Monitor, a Low Power Band-Gap, a 3.3V
70mA Linea r Vol tage Regu lat or and a 1. 8V- 3. 0V 7 0mA Lin ear Vo lta ge Reg ul ator SI M
FTA compliant Test 27.17.2.1.
The AT73C260 is specified over the industrial temperature range - 40°C to +85°C.
The AT73C260 is available in a 3 X 3 mm, 0.5mm pitch, QFN16 package.
Power
Management
and Analog
Companions
(PMAAC)
AT73C260
Interchip USB
Transceiver
(PHY - IC_USB1.0,
Voltage Class
Converter,
USB2.0 - IC_USB1.0
Bridges)
Preliminary
11030A–PMAAC–13-Sep-10
2 11030A–PMAAC–13-Sep-10
AT73C260
1. Block Diagram
Figure 1-1. AT73C260 functional block diagram
13
HVCC PVCC
PDM
112
PDP
10
11
5
2
3
8
6
4
7
HDP
RCV
HDM
OE_N
HDMO
HDPO
1615
GNDM<0>M<1>
14
M<2>
9
PVRF
VBUS
Vref
3.3Volt
AT73C260
3
11030A–PMAAC–13-Sep-10
AT73C260
2. Package and Pinout
Figure 2-1. AT73C260 QFN16 package pinout - top view
C260B
YYWW
XXXXX
HVCC 1
OE_N
5
HDMO6
HDPO7
GND
8
VBUS 4
HDM 3
HDP 2
12 PVCC
9 PVRF
10 PDM
11 PDP
16
RCV
15
M<1>
14
M<2>
13
M<0>
PIN 1 INDICATOR
17
GND
Thermal Pad
(BOTTOM)
4 11030A–PMAAC–13-Sep-10
AT73C260
3. Pin Description
Table 3-1. AT73C260 Pin Description
Pin Name I/O Pin Number Type Function
HVCC Output 1Analog
Host Side VCC
•When pi n 4 (VBUS) is grou nde d. The LDO on pin HVC C is in
standby and its output is isolated. The Host supplies HVCC with the
appropriate voltage to the AT73C260’s upstream transceiver.
•When p in 4 (VB US) is con nected to a volt ag e source th e in ternal
volt age reference 3.3V and both LDO ar e activ ate d. The LDO on pin
1 provides power at 3.3V to the AT73C260’s upstream transceiver
and it may source up to 70mA.
HDP I/O 2Digital Bidirectional
HDM I/O 3Digital Bidirectional
VBUS Input 4Analog Supply, provides power to the LDOs on pin 1 and 12
GND Ground 5Analog GND Ground for Digital and I/Os
HDMO Output 6Digital Output
HDPO Output 7Digital Output
OE_N Input 8Digital Input
PVRF Input 9Analog PVCC LDO input reference
PDM I/O 10 Digital Bidirectional pad
PDP I/O 11 Digital Bidirectional pad
PVCC Input 12 Analog
Peripheral Side VCC
•When pi n 4 (VBUS) is grou nded. Th e LDO on p in PVCC is in
standby and its output is isolated. The application supplies PVCC
with the appropriate voltage to the AT73C260’s downstream
transceiver.
•When pin 4 (VBUS) is connected to a voltage source, the LDO on
pin PVCC fol lows the volt age on pin PVRF. The LDO on pin PVC C
provides power to the AT73C260’s downstream transceive r and i t
may source up to 70mA.
RCV Output 13 Digital Output
M<2> Input 14 Digital Input. For mode configuration
M<1> Input 15 Digital Input. For mode configuration
M<0> Input 16 Digital Input. For mode configuration
GND Ground 17 Analog Analog Ground. Thermal Pad. Shall be connected to GND for electrical
and power dissipation reasons.
5
11030A–PMAAC–13-Sep-10
AT73C260
4. Absolute Maximum Ratings
Notes: 1. Refer to Power Dissipation Rating section)
5. Recommended Operating Conditions
Note: 1. Refer to Power Dissipation Rating section
6. Power Diss ipation Ratings
Note: 1. According to specification JESD51-5
Table 4-1. Absolute Maximum Ratings
Operati ng Temperature (I ndustrial )........... ...... .-40°C to + 85°C(1) *NOTICE: S tresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at these or other conditions beyond those
indica ted in the op erational sectio ns of th is spe cificatio n
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reli-
ability.
Stora ge Temperature................. ...... ..... ...... ......-55°C to + 150°C
Power Supply Inp ut on HVCC.... ..... ................. ..... -0 .3V to + 3.6 V
Power Supply Input on VBUS.................... ......... -0. 3V to + 5.5V
Digital I/O Input Voltage...................................... -0.3V to + 3.6V
All Other Pi ns................................. ...... ..... ...... .....- 0.3V to + 3.6V
ESD (all pins)..............................................................4 KV HBM
Table 5-1. Recommended Operating Conditions
Parameter Condition Min Max Units
Operating Ambient Temperature(1) -40 85 °C
Power Supply Output PVCC 1.55 3.6 V
Power Supply Input HVCC 1.55 3.6 V
Power Supply Input VBUS 4.0 5.5 V
Table 6-1. Recommended Operating Conditions
Parameter Condition Min Typ Max Units
Maximum Junction Temperature -40 -- 125 °C
RTHjA(1) Package thermal junction to ambient
resistance -- -- 90 °C / W
Maximum On-chip Power Di ssipation Ambient temperature = 85°C -- -- 400 mW
6 11030A–PMAAC–13-Sep-10
AT73C260
7. Electrical Characteristics
7.1 I/Os DC Characteristics Referred to HVCC
Notes: 1. A 220nF ceramic capacitor is connected between the pin HVCC and the pin GND and closest to HVCC pin.
2. RPU1 Pull Up resistor is as per the ECN “Pull-up/pull-down resistors” published by the USB-IF. RPU1 value is betw een 900Ω
and 1575Ω when the bus is idle and between 1425Ω and 3090Ω when the upstream device is transmitting
3. RPU2 Pull Up resistor is as per the IC_USB1.0 published by the USB-IF. RPU2 value is between 1kΩ and 3kΩ to attach and
between 30kΩ and 150kΩ during idle.
7.2 I/Os DC Characteristics Referred to PVCC
Notes: 1. A 220nF ceramic capacitor is connected between the pin PVCC and the pin GND and closest to PVCC pin.
Table 7-1. HVCC Referred I/Os: HDP, HDM, RCV, HDMO, HDPO, OE_N and M<2:0>
Symbol Parameter Comments Min Typ Max Units
HVCC Host Side Supply Voltage 220n F ceramic capacitor (1) 1.55 -- 3.6 V
IHVCC Operating HVCC Supply Current Full Speed Transceiver / Receiver
at 12Mbp s, C LOAD = 18pF on HDP
and HDM during transmit -- -- 2mA
VIH Input High-Level Voltage VOH > VOH_MIN 0.65 x
HVCC -- HVCC +
0.3 V
VIL Input Low-Level Voltage VOH < VOL_MAX -0.3 -- 0.35 x
HVCC V
VOH Output High-Level Voltage IOH = - 2mA HVCC -
0.45 -- -- V
VOL Output Low -Lev el Voltage IOL = 2mA -- -- 0.45 V
RPDP Pull-Down Resistors on HDP,
HDM All Cases 30 -- 80 kΩ
RPU1(2) Upstream Pull-Up Resistors on
HDP M<0> = 0
M<2:1> = connected to HVCC 0.9 -- 3.09 kΩ
RPU2(3) Upstream Pull-Up Resistors on
HDP M<2:0> = connected to HVCC 1-- 150 kΩ
Table 7-2. PVCC Referred I/Os: PDP, PDM
Symbol Parameter Comments Min Typ Max Units
PVCC Peripheral Side Supply Voltage 220n F ceramic capacitor (1) 1.55 -- 3.6 V
IPVCC Operating PVCC Su ppl y Cu rren t Full Speed Transceiver / Receiver
at 12Mbps, C LOAD = 18pF on PDP
and PDM during tran sm it -- -- 2mA
VIH Input High-Level Voltage VOH > VOH_MIN 0.65 x
PVCC -- PVCC +
0.3 V
VIL Input Low-Level Voltage VOH < VOL_MAX -0.3 -- 0.35 x
PVCC V
VOH Output High-Level Voltage IOH = - 2mA PVCC -
0.45 -- -- V
VOL Output Low -Lev el Voltage IOL = 2mA -- -- 0.45 V
RPDH Pull-Down Resistors All Cases for PDP, PDM 30 -- 80 kΩ
7
11030A–PMAAC–13-Sep-10
AT73C260
7.3 Timing Characteristics Table
Notes: 1. External Capacitor is a 1µF or higher ceramic capacitor connected between the pin VBUS and the pin GND and closest to
VBUS pin
7.4 VBUS Supply Characteristics
Notes: 1. External Capacitor is a 1µF or higher ceramic capacitor connected between the pin VBUS and the pin GND and closest to
VBUS pin
.
Notes: 1. External Capacitor is a 1µF or higher ceramic capacitor connected between the pin VBUS and the pin GND and closest to
VBUS pin.
Table 7-3. Timing Table
Symbol Parameter Comments Min Typ Max Units
TDELAY Propagation Delay Time HVCC = 3.3V and PVCC = 3.0V -- 37 -- ns
HVCC = 3.3V and PVCC = 1.8V -- 42 -- ns
TSLEW_R_P Slew Rate, Rise Time on PDP 10%-90%, CLOAD=33pF, PVCC=3.0V -- 5.7 --
ns
10%-90%, CLOAD=33pF, PVCC=1.8V -- 10.5 --
TSLEW_R_M Slew Rate, Rise Time on PDM 10%-90%, CLOAD=33pF, PVCC=3.0V -- 5.6 --
10%-90%, CLOAD=33pF, PVCC=1.8V -- 10.6 --
TSLEW_F_P Slew Rate, Fall Time on PDP 10%-90%, CLOAD=33pF, PVCC=3.0V -- 6.1 --
10%-90%, CLOAD=33pF, PVCC=1.8V -- 7.6 --
TSLEW_F_M Slew Rate, Fall Time on PDM 10%-90%, CLOAD=33pF, PVCC=3.0V -- 6.1 --
10%-90%, CLOAD=33pF, PVCC=1.8V -- 7.7 --
TATTACH Attachme nt Tr ans it Tim e M<2:0>=110, HVCC = 3 .3V and PVCC
= 3.0V -- 400 -- ns
TATTACH Attachme nt Tr ans it Tim e M<2:0>=111, HVCC = 1. 8V and PVCC
= 3.3V -- 400 -- ns
Table 7-4. VBUS Supply Monitor
Symbol Parameter Comments Min Typ Max Units
VBUS Input Supply Voltage Range 1µF ceramic capacitor (1) 4.0 5.0 5.5 V
VTP Positive Threshold 3.36 3.5 3.64 V
VTN Negative Threshold 3.02 3.15 3.28 V
VHYS Hysteresis 348 361 374 mV
Table 7-5. VBUS Current Consumption
Symbol Parameter Comments Min Typ Max Units
VBUS Input Supply Voltage Range 1µF ceramic capacitor (1) 4.0 5.0 5.5 V
IVBUS VBUS Supply Current
VBUS active
• HVCC= 3.3V nominal
• 1.55V < PVRF < 3.6V
• Loads = 0mA
• Idle
-- 100 150 µA
8 11030A–PMAAC–13-Sep-10
AT73C260
7.5 HVCC and PVCC Supplies Characteristics
7.5.1 HVCC and PVCC Current Consumption
7.5.2 3.3V Supplied on HVCC
When VBUS is greater than 3.5V nominal, an internal LDO voltage regulator provides a 3.3V
nominal voltage source on pin HVCC.
Notes : 1. When VBUS is present and greater than VTP, 10kΩ pull down is removed on HVCC and on PVCC and LDO are started. When
VBUS goes below VTP, a 10kΩ pull down is connected on HVCC and PVCC and LDO are disabled. When VBUS = 0V and HVCC
and PVCC within their normal range the 10kΩ pull down are disconnected.
Table 7-6. PVCC and HVCC Current Consumption
Symbol Parameter Comments Min Typ Max Units
HVCC Host Supply Voltage 1.55 -- 3.6 V
PVCC Peripheral Supply Voltage 1.55 -- 3.6 V
IVCC XVCC Supply Current
VBUS = 0V, PVRF = 0V
• Loads = 0mA
• Idle
• HVCC forced at 3.6V
• PVCC forced at 3.3V
-- -- 5µA
Table 7-7. HVCC LDO Character isti c s
Symbol Parameter Comments Min Typ Max Units
HVCC(1) Output Voltage
- Enabled when VBUS is greater
than 3.5V typical.
- Disabled when VBUS goes b elow
3.15V typical
3.0 3.3 3.6 V
IOOutput Current 0-- 70 mA
ΔVDD_IL
Static Loa d Re gul ati on • VBUS > 4.5V
• IO = 10% to 90% -- -- 10 mV
Dynamic Load Regulation • VBUS > 4.5V
• IO = 10% to 90%
• TRISE = TFALL = 5µs -- 50 -- mV
ΔVDD_VIN Static Line Regul ati on
• VBUS from 4.3V to 5.5V
• IO = Max -- -- 20 mV
• VBUS from 4.0V to 5.5V
• IO = 7 mA -- -- 20 mV
TSTART Start-up Time
• VBUS From 0V to 5.0V
• TRISE = 10µs
• IO = 0mA
• VOUT > 3.0V
-- -- 60 µs
9
11030A–PMAAC–13-Sep-10
AT73C260
7.5.3 Voltage Supplied on PVCC
When VBUS is greater than 3.5V nominal, an internal LDO Follower provides a voltage source on
pin PVCC. The voltage on pin PVCC is equal to the voltage on pin PVRF.
PVCC LDO is in accordance with FTA Test 3GPP - 27.17.2.1 dedicated for Subscriber Iden-
tity Module (SIM) application.
Notes : 1. When VBUS is present and greater than VTP, 10kΩ pull down is removed on HVCC and on PVCC and LDO are started. When
VBUS goes below VTP, a 10kΩ pull down is connected on HVCC and PVCC and LDO are disabled. When VBUS = 0V and HVCC
and PVCC within their normal range the 10kΩ pull down are disconnected.
2. Off time is described in Section 9.3.4 on page 16. To reduce TSTOP time an external reisitor is recommended. This value
depends on COUT and load applied on the system.
Table 7-8. PVCC LDO Characteristics
Symbol Parameter Comments Min Typ Max Units
VBUS Supply Input Voltage On pin VBUS 4.0 5.0 5.5 V
PVCC(1) Output Voltage
- Enabled when VBUS is greater
than 3.5V typic al.
- Disabled when VBUS goes below
3.15V typical
- 1.55V < PVRF < 3.6V
1.55 -- 3.6 V
VOFF Follower Offset Voltage PVCC - PVRF -40 -- 40 mV
IOOutput Current 0-- 70 mA
ΔVDD_IL
Static Loa d Re gul ati on • VBUS > 4.5V
• IO = 10% to 90% -- -- 10 mV
Dynamic Load Regulation • VBUS > 4.5V
• IO = 10% to 90%
• TRISE = TFALL = 5µ s -- 30 -- mV
ΔVDD_VIN Static Line Regul ati on
• VBUS from 4.3V to 5.5V
• IO = Max -- -- 20 mV
• VBUS from 4.0V to 5.5V
• IO = 7 mA -- -- 20 mV
TSTART Start-up Time
• VBUS is set at 5.0V
• PVRF 0V to 1.8V with TRISE = 5µ s
• IO = 10mA
• VOUT > 1.62V
-- 20 35 µs
• VBUS is set at 5.0V
• PVRF 0V to 3.0V with TRISE = 5µ s
• IO = 10mA
• VOUT > 2.7V
-- 32 50 µs
TSTOP(2) Power-Off Time
• VBUS is set at 5.0V
• PVRF 3.0V to 0V with TFALL = 5µs
• RLOAD = 1KΩ. COUT=220nF/ X5R
• VOUT < 0.4V
-- -- 525 µs
• VBUS is set at 5.0V
• PVRF 3.0V to 0V with TFALL = 5µs
• IO = 7mA. COUT=220nF/ X5R
• VOUT < 0.4V
-- -- 225 µs
10 11030A–PMAAC–13-Sep-10
AT73C260
8. Components List.
Table 8-1. AT73C260 External Components List
Component Name Component Type Value / Tol. Reference Reference
R1, R2Resistor 33 Ω +/- 5% CRG0402J33R
R3Resistor 10 Ω +/- 5% CRG0603J10R
R4Resistor 10kΩ +/- 1% CPF0402F10KE1
R5Resistor 100kΩ +/- 1% CPF0603F100KC1
R6, R7Resistor 22kΩ +/- 5% CRG0402J22K
C1, C2Ceramic Capacitor COG 22pF +/- 20% C1005COG1H220J GRM1555C1H220JZ01
C3Ceramic Capacitor X5R 1µF +/- 20% C1005X5R0J105K GRM155R60J105KE19
C4Ceramic Capacitor X5R 220nF +/- 20% C1005X5R1C224KT GRM155R60J224KE01
C5Ceramic Capacitor X5R 220nF +/- 20% C1005X5R1C224KT GRM155R60J224KE01
11
11030A–PMAAC–13-Sep-10
AT73C260
9. Functional Description
9.1 AT73C260’s Upstream and Downstream Ports
This section relates to either upstream or downstream ports with digital, IC_USB1.0 or USB2.0
section 7 electrical characteristics.
Table 9 -1 shows the c onfigurat ion of t he ups tream and dow nstre am ports based on pin s 14, 1 5
and 16 voltages.
• 0 is when the pin is connected to GND.
• 1 is when the pin is connected to HVCC.
Notes:1. PVCC is set to 3.3V and external pull down resistors of 22kΩ ± 5% are connected, one bet ween
PDP and GND and the other between PDM and GND.
Table 9-1. Upstream and Downstream Ports
M<2>
Pin 14 M<1>
Pin 15 M<0>
Pin 16 Upstream
Port Downstream
Port
000 Digital IC_USB1.0
001 Digital IC_USB1.0
010 Digital IC_USB1.0
011 Digital IC_USB1.0
100Not Used Not Used
101 Digital IC_USB1.0
110Section 7 IC_USB1.0
111IC_USB1.0 Section 7 (1) / IC_USB1.0
12 11030A–PMAAC–13-Sep-10
AT73C260
9.2 AT73C260 Pull Up and Pull Down Resistors
Pull down resistors RPDP and RPDH values and beha vior s comp ly with th e IC_US B1.0 speci fica-
tion published by the USB-IF.
9.2.1 AT73C260 Upstream Port Connectivity (HVCC, HDP
, HDM):
The host, IC_USB1.0 or USB2.0 section 7, is connected to the AT73C260’s upstream port.
• When in IC_USB 1.0 RPU2 is selected.
• When in USB 2.0 se cti on 7 RPU1 is selected.
9.2.2 AT73C260 Downstream Port Connectivity (PVCC, PDP, PDM):
The peripheral, IC_USB1.0 or USB2.0 section 7, is connected to the AT73C260’s downstream
port.
• An IC_USB1.0 peripheral is connected to the AT73C260’s downstream port.
• An USB2.0 section 7 peripheral is connected to the AT73C260’s downstream port with
external pull down resistors as per precedent note (1) (See Table 9-1 on page 11).
Figure 9-1. AT73C260 Downstream and Upstream Ports
SW5
RPDH
SW6
HVCC PVCC
HDM
HDP
PDM
PDP
GND
SW2
RPU2
SW1
RPU1
RPDP
SW3 SW4
13
11030A–PMAAC–13-Sep-10
AT73C260
9.3 Theory Of Operation
9.3.1 Remote Wake Up
The AT73C260 does not support remote wake up.
9.3.2 Slew Rate Control
When the AT73C260 drives an IC_USB bus section the output buffer on each line (Figure 9-2)
drives the pin with a slew rate control to minimize radiated EMI.
Figure 9-2. AT73C260 Output Buffer
Figure 9-3. AT73C260 Output Buffer Slew Rate
Note: See Table 7-3 on page 7 for timing values.
Output buffers
TxIC_DP
TxIC_DM
CT
CT
CT = 18pF
t
R
90%
10%
tF
90%
10%
14 11030A–PMAAC–13-Sep-10
AT73C260
9.3.3 Attach
Figure 9-4. AT73C260 Attach Sequence
In the following paragraphs, two different attach sequences are described according the mode
selected. Mode VCC and Mode S7_ICC_TK are explained.
9.3.3.1 Attach Sequence ”Mode VCC”
The foll owing sequenc e describ es the AT73 C260 with an IC _USB upstre am connectio n and an
IC_USB downstream connection (Mode VCC ). For hardware co nnection refers to “Mode: Volt-
age Class Converter: VCC” on page 34.
•H
VCC and PVCC are present and are in their dedicated voltage range.
•R
PU1 is not used (SW1 always open). (For more information about switches, refers to Figure
9-1 on page 12)
• Before T1, RPDP and RPDH are connected. RPU2 is disconnected. (For more information about
resistors, refers to Figure 9-1 on page 12)
•T1: Peripheral event.
Beyo nd T1, PDP is driven high by the IC_USB peripheral’s pull-up resistor.
•T2: AT73C260 event.
The signa l is above VIH. T he AT73C260 ve rifies tha t the conditi on PDP is h igh lasts mor e
than 200ns nominal. This information is passed to the AT73C260’s Host side.
•T3: AT73C260 event.
Beyo nd T3, RPU2 (2k nominal) is connected while RPDP on HDP is disconnected.
•T4: Host event.
From T4 the host drives the reset with SE0.
•T5: AT73C260 event.
It takes 40 ns nominal beyond T4 for PDP to be driven low.
•T6: AT73C260 event.
During reset the AT73C260 detects a SE0 for more than 1µs nominal. Beyond T6 both
RPDH are disconnected.
HDP
PDP
T1
idle
idle
Reset
T2T3T4T5T6T7T8T9T10 T11
15
11030A–PMAAC–13-Sep-10
AT73C260
•T7: Host event.
Host stops driving SE0. The AT73C260 with its 2k nominal resistor, pulls-up HDP.
•T8: AT73C260 event.
The signal is above VIH.(on HDP)
•T9: AT73C260 event.
40ns nominal after T8. From T9, the AT73C260 drives high until VIH (on PDP) is reached
plus 100ns nominal until T11.
•T10: AT73C260 event.
Between T 7 and T10. HDP i s pulle d-up w ith 2k nominal until VIH ( on HDP) is reac hed p lus
100ns. At T10 RPU2 becomes 50k nominal.
9.3.3.2 Attach Sequence Mode S7_ICC_TK
The following sequence describes the AT73C260 with an USB2.0 section 7 upstream connec-
tion and an IC_USB downstream connection (Mode S7_ICC_TK). For hardware connection
refers to “Mod e: USB2.0 sectio n 7 to IC_USB1.0 with PV CC fixed by PVRF : S7_ICC_TK” on
page 38.
•H
VCC = 3.3V and PVCC are present and are in their dedicated voltage range.
•R
PU2 is not used (SW2 always open). RPDP are not used (SW3 and SW4 always open).(For
more information about switches, refers to Figure 9-1 on page 12)
• Before T1, RPDH are connected. RPU2 is disconnected. (For more information about resistors,
refers to Figure 9-1 on page 12)
•T1: Peripheral event.
Beyo nd T1, PDP is driven high by the IC_USB peripheral’s pull-up resistor.
•T2: AT73C260 event.
The signa l is above VIH. T he AT73C260 ve rifies tha t the conditi on PDP is h igh lasts mor e
than 200ns nominal. This information is passed to the AT73C260’s Host side.
•T3: AT73C260 event.
Beyo nd T3, RPU1 1.2k nominal, is connected.
•T4: Host event.
From T4 the host drives the reset with SE0.
•T5: AT73C260 event.
RPU1 becomes 2.2k nominal. It takes 40 ns nominal beyond T4 for PDP to be driven low.
•T6: AT73C260 event.
During reset the AT73C260 detects a SE0 for more than 1µs nominal. Beyond T6 both
RPDH are disconnected.
•T7: Host event.
Host stops driving SE0. The AT73C260 with its 2k nominal resistor, pulls-up HDP.
•T8: AT73C260 event.
The signal is above VIH.(on HDP)
16 11030A–PMAAC–13-Sep-10
AT73C260
•T9: AT73C260 event.
40ns nominal after T8. From T9, the AT73C260 drives high until VIH (on PDP) is reached
plus 100ns nominal until T11.
•T10: AT73C260 event.
Between T7 and T10. HDP is pulled-up with 2.2k nominal until VIH (on HDP) is reached plus
100ns. At T10 RPU1 becomes 1.2k nominal.
9.3.4 PVRF Driving PVCC
Figure 9-5. AT73C260 PVRF driving PVCC
When VBUS, pin 4, is providing power to the USB UICC via the LDOs, the voltage on PVCC (pin
12) is following the voltage on PVRF (pin 9) .
TSTART is mostly related to the capacitive load on PVCC and the strength of the LDO’s PMOS.
TSTART as mentioned in Table 7-8 on page 9 is less than 50µs.
TSTOP is mostly related to the load on PVCC since the LDO’s PMOS is off when starts TOFF.
Certa in applic ations may r equire P VCC to fall below a minimum voltage in less than TOFF and
guarantee a Power On Reset sequence in the USB UICC when PVCC is set again. For these
applications an extra load, such as a resistor across PVCC and GND in parallel with the USB
UICC and the decoupli ng ca pac ito r C5 may be require d.
As an example, for TOFF = 0.4ms, a decoupling capacitor C5 of 220nF and an USB UICC in
standby (less than 100µA) the extra resistor shall be less than 1kΩ.
PVRF
PVCC
10%
90%
TSTART TSTOP
TOFF
17
11030A–PMAAC–13-Sep-10
AT73C260
9.3.5 Reset Signaling
At the end of the Reset signaling on AT73C260’s host side and peripheral sides the pulled up
data line volt age has to reac h VIH_MIN in less than TDDIS, see Figu re 9-6. I f it is not th e cas e, the
host may see a disconnect condition.
Reset is forced during T2.
If a 100kΩ pull up resistor is used while the capacitive load is more than 20pF, the time constant
is greater than 2µs. To avoid any disconnect condition, the AT73C260 pulls up the appropriate
data li ne during about one bit duratio n with ex tra strength making the disconne ct conditio n
unlikely.
Figure 9-6. AT73C260 Reset Signaling
9.3.6 Resume Signaling
The AT73C260 supports resume signaling. The timings on IC_DP and IC_DM are those on HDP
and HDM delayed by 40ns nominal.
Figure 9-7. AT73C260 Resume Signaling
Notes: 1. J state means that HDP = 1 and HDM = 0.
2. K state means that HDP = 0 and HDM = 1.
3. SOF = Start Of Frame
V
IH_MIN
Less than T
DDIS
min (2µs)
IC_DP
IC_DM
Reset signaling
T1 T2
HDP
HDM
Idle, J state
The Hub signals resume to the UICC by forcing a K state during T
DRSMDN
(≥ 20ms)
SOF
T
DRSMND
(≥ 20ms minimum)
EOP (Two Low Speed bit time)
One J state
3ms max
18 11030A–PMAAC–13-Sep-10
AT73C260
9.4 General Descript ion
The AT73C260 covers four main functions:
• PHY (described in Section 9.4.3 on page 20)
• Bridge (described in Section 9.4.4 on page 30)
• IC_USB1.0 Voltage Class Converter (described in Section 9.4.5 on page 34)
• Bridge with LDOs for two specific applications (described in Section 9.4.6 on page 36),
and one ex tra function fr om many d escribed as an example wh ere the AT73 C260 is an inter-
chip PHY in a digital implementation (FPGA) of a peripheral.
9.4.1 Application Modes
The following Table 9-2 lists the applications and pin settings.
Notes: 1. 22kΩ Pull down on pins 10 and 11
2. PC with Digital Base Band
3. Token
4. M<2:0> code” 100” is not used
Table 9-2. AT73C260 Application Modes (4)
Mode Application M<2>
Pin 14 M<1>
Pin 15 M<0>
Pin 16 Function
PHY_6_SE0 Digital six wires unidirectional DAT_SE0 to IC_USB1.0 000 PHY
PHY_4_SE0 Digital four wires bidirectional DAT_SE0 to IC_USB1.0 001 PHY
PHY_6_DPDM Digital six wires unidirectional DP_DM to IC_USB1.0 010 PHY
PHY_4_DPDM Digital four wires bidirectional DP_DM to IC_USB1.0 011 PHY
PHY_3_ULPI Digital three wires bidirectional (DAT, SE0, OE_N) to IC_USB1.0 101 PHY
S7_ICC USB2.0 section 7 without cable to IC_USB1.0 110Bridge
S7_ICC_DBB USB2.0 section 7 with cable to IC_USB1.0, LDOs ON
VCC driven by the Digital Base Band (2) 110Bridge with
LDOs
S7_ICC_TK USB2.0 section 7 with cable to IC_USB1.0, LDOs ON
VCC fixed by PVRF (3) 110Bridge with
LDOs
ICC_S7 IC_USB1.0 to USB2.0 se cti on 7 (1) 111Bridge
VCC IC_USB1.0 to IC_USB1.0 111Voltage
Class
Converter
19
11030A–PMAAC–13-Sep-10
AT73C260
9.4.2 Function Descriptions
9.4.2.1 Downstream Port PHY:
A set of digital signals generated by an FPGA or an ASIC with I/O powered by a first power sup-
ply dr ive th e AT 73C260 whic h co nverts thes e signa ls i nto a nalog signal s IC_D P and IC _DM as
per IC_USB1.0 powered by a second power supply.
9.4.2.2 Bridge: Two cases are supported: USB2.0 section 7 to IC_USB1.0 and IC_USB1.0 to USB2.0 section 7.
• USB2.0 section 7 to IC_USB1.0
Downstream D+ and D- signals drive the AT 73C260 which converts these signals into analog
signals IC_DP and IC_DM as per IC_USB1.0.
• IC_USB1.0 to USB2.0 section 7
Downstream IC_USB1.0 signals drive the AT73C260 which converts these signals into analog
signals D+ and D- as per USB2.0 section 7.
9.4.2.3 Voltage Class Converter:
The following applications enable communications between an IC_USB1.0 compliant down-
stream port with a first voltage class V1 and an IC_USB1.0 compliant peripheral with a second
voltage cl as s VCC.
The range of the supplies, respectively Host and Device, are: HVCC (1.55V - 3.6V) and PVCC
(1.55V - 3.6V)
9.4.2.4 Bridge with LDOs:
Two cases are supported: one for PC with embedded Digital Base Band and one for Token.
• PC with embedded Digital Base Band
The AT73C260 provides up to 70mA from VBUS to the UICC under the VCC required by the DBB.
Also the AT73C260 converts D+ and D- signals into analog signal s IC_DP and IC_DM as per
IC_USB1.0.
• Token
The AT73C260 provides up to 70mA from VBUS to the UICC under VCC.
This voltage is generated by PVCC LDO and set by an external resistor bridge supplied by 3.3V
voltage re ferenc e (H VCC).
Also the AT73C260 converts D+ and D- signals into analog signals IC_DP and IC_DM as per
IC_USB1.0.
20 11030A–PMAAC–13-Sep-10
AT73C260
9.4.3 Downstream P ort PHY
In mobile applications, the USB UICC is handled by the user and special care should be taken in
the ES D prot ection on th e dow nstream por t facin g the USB UICC. The AT 73C2 60 do wnstrea m
port is protected against 4kV ESD.
Also, th e host a nd the US B UICC may not be l ocated on t he sam e boar d with a fle x conn ecting
the two PCBs. The AT73C260 should be located next to the host. The flex is between the
AT73C260’s downstream port and the USB UICC upstream port. The AT73C260 downstream
port has slew rate control on both PDM and PDP to minimize the radiated EMI.
Pins VBUS and PVRF are connected to GND and LDO outputs are isolated and in standby.
9.4.3.1 Mode: Digital six wires unidirectional DAT_SE0 to IC_USB1.0: PHY_6_SE0
Description
This application allows a Host, ASIC or FPGA, with the digital unidirectional Philips
PDIUSBP11A (MODE pin = 0) six wires interface to drive an IC_USB downstream port.
Figure 9-8. PHY_6 _S E0 Bl oc k Diagram
Hardware Configuration
In the following tables, the pin and the hardware configuration are described.
Table 9-3. AT73C260 Hardware Configuration
Mode M<2>
Pin 14 M<1>
Pin 15 M<0>
Pin 16 Application
PHY_6_SE0 0 0 0 Digital six wires unidirectional DAT_SE0 to
IC_USB1.0
Table 9-4. AT73C260 Pin description and configuration
Pin Number Pin Name I/O Type Polarity Function
1HVCC A-Power -- Supply by ASIC FPGA I/O Ring (1.55V
to 3.6V)
2TX_DAT D-Input -- Unidirectional T rans m it Data
3TX_SEO D-Input -- Unidirectional Transmit Single Ended 0
4VBUS A-Input -- Not Used and Connected to Ground
6RX_DM D-Output -- Unidir ectional Rece iv ing DM
7RX_DP D-Output -- Unidir ectional Rece iv ing DP
8TX_ENABLE_N D-Input Low Tx Enable N
9PVRF A-Input -- Connected to Ground
10 PDM D-I/O -- Downstream Port for USB Device
21
11030A–PMAAC–13-Sep-10
AT73C260
Application Diagram
In the following figure, the hardware configuration is described.
Figure 9-9. AT73C260: PHY - 6 wires DAT_SE0 to IC_USB1.0 - application diagram
Note: All external components are defined in component list Table 8-1 on page 10
11 PDP D-I/O -- Downstream Port for USB Device
12 PVCC A-Power -- Same as periphera l’s power (1.8V or 3V
typical)
13 RX_RCV D-Output -- Unidirectional Receiving RCV
14, 15, 16 M<2:0> D-Inputs Low Connected to Ground
Table 9-4. AT73C260 Pin description and configuration
Pin Number Pin Name I/O Type Polarity Function
C
4
HVCC
GND
13
H
VCC
P
VCC
PDM
112
PDP
10
11
AT73C260
5
2
3
8
6
4
7
HDP
RCV
HDM
OE_N
HDMO
HDPO
1615
GND
14
M<2>
9
P
VRF
V
BUS
Vref
3.3Volt
M<1> M<0>
C
5
PVCC
USB UICC
IC_DM
IC_DP
V
CC
ISO/IEC 7816-3
tx_dat
rx_rcv
tx_se0
rx_dm
rx_dp
tx_enable_n
ASIC/FPGA : 6 WIRES DAT_SE0
UTMI
DIGITAL WRAPPER
tx_dat
rx_rcv
tx_se0
rx_dm
rx_dp
tx_enable_n
22 11030A–PMAAC–13-Sep-10
AT73C260
9.4.3.2 Mode: Digital four wires bidirectional DAT_SE0 to IC_USB1.0: PHY_4_SE0
Description
This application allows a Host, ASIC or FPGA, with the digital bidirectional UTMIfs, DAT_SE0,
four wires interf ace to drive an IC_USB down stre am port.
Figure 9-10. PHY_4 _S E0 Bl oc k Diagram
Hardware Configuration
In the following tables, the pin and the hardware configuration are described.
Table 9-5. AT73C260 Hardware Configuration
Mode M<2>
Pin 14 M<1>
Pin 15 M<0>
Pin 16 Application
PHY_4_SE0 0 0 HVCC Digital four wires bidirectional DAT_SE0 to
IC_USB1.0
Table 9-6. AT73C260 Pin description and configuration
Pin Number Pin Name I/O Type Polarity Function
1HVCC A-Power -- Supply by ASIC FPGA I/O Ring (1.55V to
3.6V)
2TX_DAT/RX_DP D-I/O -- Bidirectional Rx_Dp/Tx_Data
3 TX_SE0/RX_DM D-I/O -- Bidirectional Rx_DM/Tx_Single Ended 0
4VBUS A-Input -- Not Used and Connected to Ground
6HDMO D-Output HiZ Not Connected
7HDPO D-Output HiZ Not Connected
8TX_ENABLE_N D-Input Low Tx Enable N
9PVRF A-Input -- Connected to Ground
10 PDM D-I/O -- Downstream Port for USB Device
11 PDP D-I/O -- Downstream Port for USB Device
12 PVCC A-Power -- Same as peripheral’s power (1.8V or 3V
typical)
13 RX_RCV D-Output -- Unidirectional Receiving RCV
14, 15 M<2:1> D-Inputs Low Connected to Ground
16 M<0> D-Input High Connected to HVCC
AT73C260
ASIC
FPGA
IC_USB_1.04
DAT_SEO
23
11030A–PMAAC–13-Sep-10
AT73C260
Application Diagram
In the following figure, the hardware configuration is described.
Figure 9-11. AT73C260: PHY - 4 wires DAT_SE0 to IC_USB1.0 - application diagram
Note: All external components are defined in component list Table 8-1 on page 10
C
4
HVCC
GND
13
H
VCC
P
VCC
PDM
112
PDP
10
11
AT73C260
5
2
3
8
6
4
7
HDP
RCV
HDM
OE_N
HDMO
HDPO
1615
GND
14
M<2>
9
P
VRF
V
BUS
Vref
3.3Volt
M<1> M<0>
nc
nc
HVCC
C
5
PVCC
USB UICC
IC_DM
IC_DP
V
CC
ISO/IEC 7816-3
tx_dat/rx_dp
rx_rcv
tx_se0/rx_dm
tx_enable_n
tx_dat
rx_rcv
tx_se0
rx_dm
rx_dp
tx_enable_n
ASIC/FPGA : 4 WIRES DAT_SE0
UTMI
DIGITAL WRAPPER
24 11030A–PMAAC–13-Sep-10
AT73C260
9.4.3.3 Mode: Digital six wires unidirectional DP_DM to IC_USB1.0: PHY_6_DPDM
Description
This application allows a Host, ASIC or FPGA, with the digital unidirectional Philips
PDIUSBP11A (MODE pin = 1) six wires interface to drive an IC_USB downstream port.
Figure 9-12. PHY_6_DPDM Block Diagram
Hardware Configuration
In the following tables, the pin and the hardware configuration are described.
Table 9-7. AT73C260 Hardware Configuration
Mode M<2>
Pin 14 M<1>
Pin 15 M<0>
Pin 16 Application
PHY_6_DPDM 0HVCC 0Digital six wires unidirectional DP_DM to
IC_USB1.0
Table 9-8. AT73C260 Pin description and configuration
Pin Number Pin Name I/O Type Polarity Function
1HVCC A-Power -- Supply by ASIC FPGA I/O Ring (1.55V
to 3.6V)
2TX_DP D-Input -- Uni d ir ect ional Tx DP
3TX_DM D-Input -- Uni d ir ect ional Tx DM
4VBUS A-Input -- Not Used and Connected to Ground
6RX_DM D-Output -- Unidirectional Rx DM
7RX_DP D-Output -- Unidirectional Rx DP
8TX_ENABLE_N D-Input Low Tx Enable N
9PVRF A-Input -- Connected to Ground
10 PDM D-I/O -- Downstream Port for USB Device
11 PDP D-I/O -- Downstream Port for USB Device
12 PVCC A-Power -- Same as periphera l’s power (1.8V or 3V
typical)
13 RX_RCV D-Output -- Unidirectional Receiving RCV
14 M<2> D-Input Low Connected to Ground
15 M<1> D-Input High Connected to HVCC
16 M<0> D-Input Low Connected to Ground
AT73C260
ASIC
FPGA
IC_USB_1.06
DP_DM
25
11030A–PMAAC–13-Sep-10
AT73C260
Application Diagram
In the following figure, the hardware configuration is described.
Figure 9-13. AT73C260: PHY - 6 wires DP_ DM to IC_USB1.0 - application diagram
Note: All external components are defined in component list Table 8-1 on page 10
C
4
HVCC
GND
13
H
VCC
P
VCC
PDM
112
PDP
10
11
AT73C260
5
2
3
8
6
4
7
HDP
RCV
HDM
OE_N
HDMO
HDPO
1615
GND
14
M<2>
9
P
VRF
V
BUS
Vref
3.3Volt
M<1> M<0>
HVCC
C
5
PVCC
USB UICC
IC_DM
IC_DP
V
CC
ISO/IEC 7816-3
tx_dp
rx_rcv
tx_dm
tx_enable_n
tx_dat
rx_rcv
tx_se0
rx_dm
rx_dp
tx_enable_n
ASIC/FPGA : 6 WIRES DP_DM
UTMI
DIGITAL WRAPPER
rx_dp
rx_dm
26 11030A–PMAAC–13-Sep-10
AT73C260
9.4.3.4 Mode: Digital four wires bidirectional DP_DM to IC_USB1.0: PHY_4_DPDM
Description
This application allows a Host, ASIC or FPGA, with the digital bidirectional UTMIfs, DP_DM, four
wires interface to drive an IC_USB downstream port.
Figure 9-14. PHY_4_DPDM Block Diagram
Hardware Configuration
In the following tables, the pin and the hardware configuration are described.
Table 9-9. AT73C260 Hardware Configuration
Mode M<2>
Pin 14 M<1>
Pin 15 M<0>
Pin 16 Application
PHY_4_DPDM 0HVCC HVCC Digital four wires bidirectional DP_DM to
IC_USB1.0
Table 9-10. AT73C260 Pin description and configuration
Pin Number Pin Name I/O Type Polarity Function
1HVCC A-Power -- Supply by ASIC FPGA I/O Ring (1.55V
to 3.6V)
2TX_DP/RX_DP D-I/O -- Bidirectional Tx_Dp/D x_DP
3TX_DM/RX_DM D-I/O -- Bidirectional Tx_Dm/Dx_DM
4VBUS A-Input -- Not Used and Connected to Ground
6HDMO D-Output HiZ Not Connected
7HDPO D-Output HiZ Not Connected
8TX_ENABLE_N D-Input Low Tx Enable N
9PVRF A-Input -- Connected to Ground
10 PDM D-I/O -- Downstream Port for USB Device
11 PDP D-I/O -- Downstream Port for USB Device
12 PVCC A-Power -- Same as periphera l’s power (1.8V or 3V
typical)
13 RX_RCV D-Output -- Unidirectional Receiving RCV
14 M<2> D-Input Low Connected to Ground
15,16 M<1:0> D-Inputs High Connected to HVCC
AT73C260
ASIC
FPGA
IC_USB_1.04
DP_DM
27
11030A–PMAAC–13-Sep-10
AT73C260
Application Diagram
In the following figure, the hardware configuration is described.
Figure 9-15. AT73C260: PHY - 4 wires DP_ DM to IC_USB1.0 - application diagram
Note: All external components are defined in component list Table 8-1 on page 10
C
4
HVCC
GND
13
H
VCC
P
VCC
PDM
112
PDP
10
11
AT73C260
5
2
3
8
6
4
7
HDP
RCV
HDM
OE_N
HDMO
HDPO
1615
GND
14
M<2>
9
P
VRF
V
BUS
Vref
3.3Volt
M<1> M<0>
nc
nc
HVCC
C
5
PVCC
USB UICC
IC_DM
IC_DP
V
CC
ISO/IEC 7816-3
tx_dp/rx_dp
rx_rcv
tx_dm/rx_dm
tx_enable_n
tx_dat
rx_rcv
tx_se0
rx_dm
rx_dp
tx_enable_n
ASIC/FPGA : 4 WIRES DP_DM
UTMI
DIGITAL WRAPPER
28 11030A–PMAAC–13-Sep-10
AT73C260
9.4.3.5 Mode: Digital three wires bidirectional (DAT, SE0, OE_N) to IC_USB1.0: PHY_3_ULPI
Description
This application allows a Host, ASIC or FPGA, with the digital bidirectional ULPI serial support,
DAT, SE0, and OE_N, three wires interface to drive an IC_USB downstream port.
Figure 9-16. PHY_3_ULPI Block Diagram
Hardware Configuration
In the following tables, the pin and the hardware configuration are described.
Table 9-11. AT73C260 Hardware Configuration
Mode M<2>
Pin 14 M<1>
Pin 15 M<0>
Pin 16 Application
PHY_3_ULPI HVCC 0HVCC Digit al three wires bid irectional DAT, SE0, OE _N to
IC_USB1.0
Table 9-12. AT73C260 Pin description and configuration
Pin Number Pin Name I/O Type Polarity Function
1HVCC A-Power -- Supply by ASIC FPGA I/O Ring
(1.55V to 3.6V)
2RX_RCV/TX_DAT D-I/O -- Bidirectional Rx_RCV / Tx_Data
3RX_SE0/TX_SE0 D-I/O -- Bidirectional Rx_SE0/Tx_SE0
4VBUS A-Input -- Not Used and Connected to Ground
6HDMO D-Output HiZ Not Connected
7HDPO D-Output HiZ Not Connected
8TX_ENABLE_N D-Input Low Tx Enable N
9PVRF A-Input -- Connected to Ground
10 PDM D-I/O -- Downstream Port for USB Device
11 PDP D-I/O -- Downstream Port for USB Device
12 PVCC A-Power -- Same as peripheral’s power (1.8V or
3V typical)
13 RCV D-Output HiZ Not Connected
14 M<2> D-Input High Connected to HVCC
15 M<1> D-Inputs Low Connected to Ground
16 M<0> D-Inputs High Connected to HVCC
AT73C260
ASIC
FPGA
IC_USB_1.03
ULPI
29
11030A–PMAAC–13-Sep-10
AT73C260
Application Diagram
In the following figure, the hardware configuration is described.
Figure 9-17. AT73C260: PHY - 3 wires DAT, SE0, OE_N to IC_USB1.0 - application diagram
Note: All external components are defined in component list Table 8-1 on page 10
C
4
HVCC
GND
13
H
VCC
P
VCC
PDM
112
PDP
10
11
AT73C260
5
2
3
8
6
4
7
HDP
RCV
HDM
OE_N
HDMO
HDPO
1615
GND
14
M<2>
9
P
VRF
V
BUS
Vref
3.3Volt
M<1> M<0>
nc
nc
nc
HVCC
C
5
PVCC
USB UICC
IC_DM
IC_DP
V
CC
ISO/IEC 7816-3
rx_rcv/tx_dat
rx_se0/tx_se0
tx_enable_n
tx_dat
rx_rcv
tx_se0
rx_dm
rx_dp
tx_enable_n
ASIC/FPGA : 3 WIRES DAT, SE0, OE_N
UTMI
DIGITAL WRAPPER
30 11030A–PMAAC–13-Sep-10
AT73C260
9.4.4 Bridge Pins VBUS and PVRF are connected to GND and LDO outputs are isolated and in standby.
Pin OE_N is connected to HVCC.
The following applications enable communications between.
•S7_ICC: an USB2.0 section 7 compliant downstream port and an IC_USB1.0 compliant
peripheral
•ICC_S7: an IC_USB1.0 compliant downstream port and an USB2.0 section 7 compliant
peripheral
9.4.4.1 Mode: USB2.0 section 7 downstream port to IC_USB1.0 peripheral: S7_ICC
Description
This application establishes a communication path between an USB2.0 section 7 downstream
port and an IC_USB perip heral .
An external 3.3V voltage source is applied on HVCC. AT73 C260 ’s D+ and D- inp ut pin s are com-
pliant with USB2.0 core specification.
This a pplicatio n is parti cularly we ll suite d for mobile devi ces where th e host ma y not have an
IC_USB1.0 down st re am port.
Figure 9-18. S7_ICC Bloc k Diag ra m
Hardware Configuration
In the following tables, the pin and the hardware configuration are described.
Table 9-13. AT73C260 Hardware Configuration
Mode M<2>
Pin 14 M<1>
Pin 15 M<0>
Pin 16 Application
S7_ICC HVCC HVCC 0USB2.0 section 7 downstream port to IC_USB1.0
peripheral
Table 9-14. AT73C260 Pin description and configuration
Pin Number Pin Name I/O Type Polarity Function
1HVCC A-Power -- Supplied by host at 3.3V
2D+ D-I/O -- Bidirectional D+
3D- D-I/O -- Bidirectional D-
4VBUS A-Input -- Not Used and Connected to Ground
6HDMO D-Output HiZ Not Connected
7HDPO D-Output HiZ Not Connected
8OE_N D-Input High Connected to HVCC
AT73C260
IC_USB_1.0USB 2.0
Section 7
31
11030A–PMAAC–13-Sep-10
AT73C260
Application Diagram
In the following figure, the hardware configuration is described.
Figure 9-19. AT73C260: Bridge - USB2.0 section 7 downstream port to IC_USB1.0 -application diagram
Note: All external components are defined in component list Table 8-1 on page 10
9PVRF A-Input -- Connected to Ground
10 PDM D-I/O -- Downstream Port for USB Device
11 PDP D-I/O -- Downstream Port for USB Device
12 PVCC A-Power -- Same as periphera l’s power (1.8V or 3V
typical)
13 RCV D-Output HiZ Not Connected
14 M<2> D-Input High Connected to HVCC
15 M<1> D-Inputs High Connected to HVCC
16 M<0> D-Inputs Low Connected to Ground
Table 9-14. AT73C260 Pin description and configuration
Pin Number Pin Name I/O Type Polarity Function
C
4
HVCC
D +
D -
GND
C
5
PVCC
USB UICC
IC_DM
IC_DP
V
CC
ISO/IEC 7816-3
13
H
VCC
P
VCC
PDM
112
PDP
10
11
AT73C260
5
2
3
8
6
4
7
HDP
RCV
HDM
OE_N
HDMO
HDPO
1615
GND
14
M<2>
9
P
VRF
V
BUS
Vref
3.3Volt
M<1> M<0>
nc
nc
nc
HVCC
HVCC
32 11030A–PMAAC–13-Sep-10
AT73C260
9.4.4.2 Mode: IC_USB1.0 downstream port to USB2.0 section 7 peripheral: ICC_S7
Description
This application establishes a communication path between an IC_USB1.0 downstream port
and an USB2.0 section 7 peripheral.
Figure 9-20. ICC_S7 Bloc k Diag ram
Hardware Configuration
In the following tables, the pin and the hardware configuration are described.
Table 9-15. AT73C260 Hardware Configuration
Mode M<2>
Pin 14 M<1>
Pin 15 M<0>
Pin 16 Application
ICC_S7 HVCC HVCC HVCC IC_USB1.0 downstream port to USB2.0 section 7
peripheral
Table 9-16. AT73C260 Pin description and configuration
Pin Number Pin Name I/O Type Polarity Function
1HVCC A-Power -- Same as host I/O Ring Power (1.8V to
3V typical)
2 IC_DP D-I/O -- Bidirectional IC_DP
3 IC_DM D-I/O -- Bidirectional IC_DM
4VBUS A-Input -- Not Used and Connected to Ground
6HDMO D-Output HiZ Not Connected
7HDPO D-Output HiZ Not Connected
8OE_N D-Input High Connected to HVCC
9PVRF A-Input -- Connected to Ground
10 D- D-I/O -- Downstream Port for USB Device
11 D+ D-I/O -- Downstream Port for USB Device
12 PVCC A-Power -- Supplied at 3.3V
13 RCV D-Output HiZ Not Connected
14 M<2> D-Input High Connected to HVCC
15 M<1> D-Inputs High Connected to HVCC
16 M<0> D-Inputs High Connected to HVCC
AT73C260
IC_USB_1.0 USB 2.0
µC/ASIC
Section 7
33
11030A–PMAAC–13-Sep-10
AT73C260
Application Diagram
In the following figure, the hardware configuration is described.
Figure 9-21. AT73C260: Bridge - IC_USB1.0 downstream port to USB2.0 section 7 - application diagram
Note: R6 and R7 are defined in component list Table 8-1 on page 10
C
4
IC_DP
IC_DM
GND
C
5
PVCC
D -
D +
13
H
VCC
P
VCC
PDM
112
PDP
10
11
AT73C260
5
2
3
8
6
4
7
HDP
RCV
HDM
OE_N
HDMO
HDPO
1615
GND
14
M<2>
9
P
VRF
V
BUS
Vref
3.3Volt
M<1> M<0>
nc
nc
nc
R
6
R
7
H
VCC
H
VCC
H
VCC
34 11030A–PMAAC–13-Sep-10
AT73C260
9.4.5 Mode: Voltage Class Converter: VCC
Description
Pins VBUS and PVRF are connected to GND and LDO outputs are isolated and in standby.
Pin OE_N is connected to HVCC.
The following applications enable communications between an IC_USB1.0 compliant down-
stream port with a first voltage class HVCC and an IC_USB1.0 compliant peripheral with a second
voltage cl as s PVCC.
Figure 9-22. Voltage Class Converter Block Diagram
Hardware Configuration
In the following tables, the pin and the hardware configuration are described.
Table 9-17. AT73C260 Hardware Configuration
Mode M<2>
Pin 14 M<1>
Pin 15 M<0>
Pin 16 Application
VCC HVCC HVCC HVCC IC_USB1.0 to IC_USB1.0 Voltage Class Converter
Table 9-18. AT73C260 Pin description and configuration
Pin Number Pin Name I/O Type Polarity Function
1HVCC A-Power -- Same as host I/O Ring Power (1.8V to
3V typical)
2 IC_DP D-I/O -- Bidirectional IC_DP
3 IC_DM D-I/O -- Bidirectional IC_DM
4VBUS A-Input -- Connected to Ground
6HDMO D-Output HiZ Not Connected
7HDPO D-Output HiZ Not Connected
8OE_N D-Input High Connected to HVCC
9PVRF A-Input -- Connected to Ground
10 PDM D-I/O -- Downstream Port for USB Device
11 PDP D-I/O -- Downstream Port for USB Device
12 PVCC A-Power -- Same as periphera l’s power (1.8V or 3V
typical)
13 RCV D-Output HiZ Not Connected
14 M<2> D-Input High Connected to HVCC
15 M<1> D-Inputs High Connected to HVCC
16 M<0> D-Inputs High Connected to HVCC
AT73C260
IC_USB_1.0
ASIC
IC_USB_1.0
35
11030A–PMAAC–13-Sep-10
AT73C260
Application Diagram
In the following figure, the hardware configuration is described.
Figure 9-23. AT73C260: Voltage Class Converter - IC_USB1.0 to IC_USB1.0 - application diagram
Note: All external components are defined in component list Table 8-1 on page 10
C
4
IC_DP
IC_DM
GND
C
5
PVCCHVCC
USB UICC
IC_DM
IC_DP
V
CC
ISO/IEC 7816-3
13
H
VCC
P
VCC
PDM
112
PDP
10
11
AT73C260
5
2
3
8
6
4
7
HDP
RCV
HDM
OE_N
HDMO
HDPO
1615
GND
14
M<2>
9
P
VRF
V
BUS
Vref
3.3Volt
M<1> M<0>
nc
nc
nc
HVCC
HVCC
36 11030A–PMAAC–13-Sep-10
AT73C260
9.4.6 Bridge With LDOs
LDOs are enabled.
AT73C260’s pin VBUS is connected to the USB signal VBUS through a low pass filter.
9.4.6.1 Mode: PC’s USB2.0 section 7 to IC_USB1.0 with VCC driven by the DBB: S7_ICC_DBB
Description
The PC’s Digital Base Band may not provide enough power to a USB UICC with mass storage.
The V BUS power supply voltage will make av ailable that extra power, up to 70mA, through the
AT73C260’s LDO if needed by the USB UICC.
The PC’s Digital Base Band supplies on pin 9 the power sequence required by ETSI. The
AT73C260 buffers the signal on PVRF to PVCC. PVCC sources power from VBUS to VCC.
On the Host side HVCC generates 3.3V fr om VBUS.
Figure 9-24. S7_ICC_DBB Block Diagram
Hardware Configuration
In the following tables, the pin and the hardware configuration are described.
Table 9-19. AT73C260 Hardware Configuration
Mode M<2>
Pin 14 M<1>
Pin 15 M<0>
Pin 16 Application
S7_ICC_DBB HVCC HVCC 0PC’s USB2.0 section 7 to IC_USB1.0 with VCC
driven by DBB
Table 9-20. AT73C260 Pin description and configuration
Pin Number Pin Name I/O Type Polarity Function
1HVCC A-Output -- Delivered by AT73C260 from VBUS at
3.3V
2D+ D-I/O -- Bidirectional D +
3D- D-I/O -- Bidirectional D -
4VBUS A-Input -- Supplied by USB Power Line
6HDMO D-Output HiZ Not Connected
7HDPO D-Output HiZ Not Connected
8OE_N D-Input High Connected to HVCC
9PVRF A-Input -- Control by Digital Base Band
AT73C260
Phone
µC/ASIC
IC_USB_1.0USB 2.0
DBB ISO7816
V
BUS
P
VRF
P
VCC
37
11030A–PMAAC–13-Sep-10
AT73C260
Application Diagram
In the following figure, the hardware configuration is described.
Figure 9-25. AT73C260: Bridge with LDO - USB2.0 section 7 to IC_USB1.0 with VCC driven by DBB - application diagram
Notes: 1. PVCC LDO regulator is compliant with SIM FTA 27.17.2.1 Tests Series.
2. All external components are defined in component list Table 8-1 on page 10
10 PDM D-I/O -- Downstream Port for USB Device
11 PDP D-I/O -- Downstream Port for USB Device
12 PVCC A-Output -- Delivered by A T73C260 from VBUS and
control by D BB
13 RCV D-Output HiZ Not Connected
14 M<2> D-Input High Connected to HVCC
15 M<1> D-Inputs High Connected to HVCC
16 M<0> D-Inputs Low Connected to Ground
Table 9-20. AT73C260 Pin description and configuration
Pin Number Pin Name I/O Type Polarity Function
C
4
GND C
5
USB UICC
IC_DM
IC_DP
V
CC
ISO/IEC 7816-3
13
H
VCC
P
VCC
PDM
112
PDP
10
11
AT73C260
5
8
6
4
7
RCV
OE_N
HDMO
HDPO
1615
GND
14
M<2>
P
VRF
V
BUS
Vref
3.3Volt
M<1> M<0>
nc
nc
nc
Digital
Base Band
I/O
RST
CLK
2
3
9
D +
R
1
C
1
D -
C
2
R
2
V
BUS
R
3
C
3
HVCC
HDP
HDM
HVCC
HVCC
38 11030A–PMAAC–13-Sep-10
AT73C260
9.4.6.2 Mode: USB2.0 section 7 to IC_USB1.0 with PVCC fixed by PVRF: S7_ICC_TK
Description
This is a token application where an USB UICC is connected to an USB2.0 section 7 down-
stream port.
The AT73C260’s LDOs supply HVCC set at 3.3V and PVCC set at the power supply voltage
required by the USB UICC .
This appl ication es tablishes a comm unication path be tween a USB2.0 s ection 7 downs tream
port and the USB UICC’s. The power to the USB UICC is provided by VBUS using an LDO able to
source up to 70mA.
This is the ty pic al elec tric al schem ati c for a USB UICC use d in a USB Token to be conne cte d to
a USB2.0 series A receptacle.
The voltage divider R4/R5 generates for example 3.0V buffered by the LDO to the downstream
side of the transceiver and to the USB UICC PVCC.
This set up allows passing USB CV tests to the USB UICC under tests.
Figure 9-26. S7_ICC_TK Block Diagram (Token Application)
Hardware Configuration
In the following tables, the pin and the hardware configuration are described.
Table 9-21. AT73C260 Hardware Configuration
Mode M<2>
Pin 14 M<1>
Pin 15 M<0>
Pin 16 Application
S7_ICC_TK HVCC HVCC 0USB2.0 secti on 7 to IC_ USB 1.0 wi th PVCC fixed by
PVRF
Table 9-22. AT73C260 Pin description and configuration
Pin Number Pin Name I/O Type Polarity Function
1HVCC A-Output -- Delivered by AT73C260 from VBUS at
3.3V
2D+ D-I/O -- Bidirectional D +
3D- D-I/O -- Bidirectional D -
4VBUS A-Input -- Supplied by USB Power Line
6HDMO D-Output HiZ Not Connected
7HDPO D-Output HiZ Not Connected
AT73C260 IC_USB_1.0USB 2.0
VBUS
PVRF
HVCC=3.3V
PVCC
39
11030A–PMAAC–13-Sep-10
AT73C260
Application Diagram
In the following figure, the hardware configuration is described.
Figure 9-27. AT73C260 : Bridge wit h LDO - USB2.0 section 7 to IC_USB1.0 with VCC fixed by PVRF - application diagram
Notes: 1. PVCC LDO regulator is compliant with SIM FTA 27.17.2.1 Tests Series.
2. All external components are defined in component list Table 8-1 on page 10
8OE_N D-Input High Connected to HVCC
9PVRF A-Input -- Fixed by external resistor bridge divider
10 PDM D-I/O -- Downstream Port for USB Device
11 PDP D-I/O -- Downstream Port for USB Device
12 PVCC A-Output -- Delivered by AT73C260 from VBUS
according external resistor ratio
13 RCV D-Output HiZ Not Connected
14 M<2> D-Input High Connected to HVCC
15 M<1> D-Inputs High Connected to HVCC
16 M<0> D-Inputs Low Connected to Ground
Table 9-22. AT73C260 Pin description and configuration
Pin Number Pin Name I/O Type Polarity Function
GND
C
5
USB UICC
IC_DM
IC_DP
V
CC
ISO/IEC 7816-3
13
H
VCC
P
VCC
PDM
112
PDP
10
11
AT73C260
5
8
6
4
7
RCV
OE_N
HDMO
HDPO
1615
GND
14
M<2>
P
VRF
V
BUS
Vref
3.3Volt
M<1> M<0>
nc
nc
nc
2
3
9
D +
R
1
C
1
D -
C
2
R
2
V
BUS
R
3
C
3
HDP
HDM
From Host USB2.0 section 7
with cable
R
5
R
4
C
4
HVCC
PVRF = PVCC = HVCC * R5/(R5+R4)
HVCC
HVCC
40 11030A–PMAAC–13-Sep-10
AT73C260
3. External resistors shall be in the following range: 100KΩ < R4 + R5 < 330KΩ in order to mini-
mize current consumption and to reach a good accuracy on PVCC. The bias current of PVRF
follower is less than +/-100nA.
41
11030A–PMAAC–13-Sep-10
AT73C260
9.4.7 Example of an Extra Function
For an FPGA implementation of a USB device, there is a need for an upstream IC_USB 1.0
PHY.
For this requirement the AT73C260 product can be configured as described below.
Pins VBUS and PVRF are connected to GND and LDO outputs are isolated and in standby.
9.4.7.1 Mode: Digital six wires unidirectional DAT_SE0 to IC_USB1.0 upstream: Extra Function
Description
This application allows a peripheral based on an ASIC or an FPGA with the digital unidirectional
six wires interface to be connected to an IC_USB 1.0 downstream port.
Here below, an example is shown. Other digital interfaces are compatible with this upstream
IC_USB 1.0 port.
Figure 9-28. PHY_6 _S E0 Bl oc k Diagram
Hardware Configuration
In the following tables, the pin and the hardware configuration are described.
Table 9-23. AT73C260 Hardware Configuration
Mode M<2>
Pin 14 M<1>
Pin 15 M<0>
Pin 16 Application
Extra Mode
(as an
example) 0 0 0 Digital six wires unidirectional DAT_SE0 to
IC_USB1.0 upstream
Table 9-24. AT73C260 Pin description and configuration
Pin Number Pin Name I/O Type Polarity Function
1HVCC A-Power -- Same as peripheral I/O ring (1.55V to
3.6V typical)
2TX_DAT D-Input -- Unidirectional T rans m it Data
3TX_SEO D-Input -- Unidirectional Transmit Single Ended 0
4VBUS A-Input -- Not Used and Connected to Ground
6RX_DM D-Output -- Unidir ectional Rece iv ing DM
7RX_DP D-Output -- Unidir ectional Rece iv ing DP
8TX_ENABLE_N D-Input Low Tx Enable N
AT73C260 ASIC
FPGA
IC_USB_1.0
6
HOST
pull-up
Control
DAT_SEO
42 11030A–PMAAC–13-Sep-10
AT73C260
Application Diagram
In the following figure, the hardware configuration is described.
Figure 9-29. AT73C260: Extra Mode - PHY of a 6-wire FPGA peripheral implementation - application diagram
Notes: 1. All external components are defined in component list Table 8-1 on page 10
2. In Upstream port configuration, the software must drive the REXT pull-up resistor.
9PVRF A-Input -- Connected to Ground
10 PDM D-I/O -- Downstream Port for USB Device
11 PDP D-I/O -- Downstream Port for USB Device
12 PVCC A-Power -- Same power as host VCC (1.8 or 3V
typical)
13 RX_RCV D-Output -- Unidirectional Receiving RCV
14, 15, 16 M<2:0> D-Inputs Low Connected to Ground
Table 9-24. AT73C260 Pin description and configuration
Pin Number Pin Name I/O Type Polarity Function
C
4
HVCC
GND
13
H
VCC
P
VCC
PDM
112
PDP
10
11
AT73C260
5
2
3
8
6
4
7
HDP
RCV
HDM
OE_N
HDMO
HDPO
1615
GND
14
M<2>
9
P
VRF
V
BUS
Vref
3.3Volt
M<1> M<0>
HVCC
C
5
PVCC
HOST
IC_DM
IC_DP
V
CC
R
EXT
PVCC
Pull-Up
Control
tx_dp
rx_rcv
tx_dm
tx_enable_n
tx_dat
rx_rcv
tx_se0
rx_dm
rx_dp
tx_enable_n
Pull-Up Control
ASIC/FPGA : Peripheral 6 WIRES DAT_SE0
UTMI
DIGITAL WRAPPER
rx_dp
rx_dm
43
11030A–PMAAC–13-Sep-10
AT73C260
10. Package Information
Figure 10-1. Mechanical Package Drawing for 16-lead Quad Flat No Lead Package
Note: All the dimensions are in mm
44 11030A–PMAAC–13-Sep-10
AT73C260
11. Ordering Information
Table 11-1. Ordering Information
Ordering Code Package Package Type Temperature Operating Range
AT73C260 QFN16 3 x 3 mm Green -40°C to +85°C
45
11030A–PMAAC–13-Sep-10
AT73C260
12. Revision History
Doc. Rev Date Comments
Change
Request
Ref.
11030A 13-Sep-10 First revision
46 11030A–PMAAC–13-Sep-10
AT73C260
i
11030A–PMAAC–13-Sep-10
AT73C260
1Block Diagram ..........................................................................................2
2Package and Pinout .................................................................................3
3Pin Description ......................................................................................... 4
4Absolute Maximum Ratings ....................................................................5
5Recommended Operating Conditions ....................................................5
6Power Dissipation Ratings ......................................................................5
7Electrical Characteristics ........................................................................6
7.1I/Os DC Characteristics Referred to HVCC ...............................................................6
7.2I/Os DC Characteristics Referred to PVCC ...............................................................6
7.3Timing Charac te ristic s Table ........................ ....... ...... ....... ...... ...... ....... ...... ....... ...... ...7
7.4VBUS Sup ply Characteris ti cs .... ...... ....... ...... ....... ...... ....... ...... ...... ....... ...... ....... ...... ...7
7.5HVCC and PVCC Supplies Characteristics ...............................................................8
8Components List. .................................... ................................ ...............10
9Functional Description ..........................................................................11
9.1AT73C260’s Upstream and Downstream Ports .......................................................11
9.2AT73C260 Pull Up and Pull Down Resistor s ....... ...... ....... ...... ...... ....... ...... ....... .......12
9.3Theory Of Operation ................................................................................................13
9.4General Description .................................................................................................18
10 Package Information ..............................................................................43
11 Ordering Information .............................................................................44
12 Revision History .....................................................................................45
ii 11030A–PMAAC–13-Sep-10
AT73C260
11030A–PMAAC–13-Sep-10
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