OCTOBER 2013
DSC-2967/16
1
©2013 Integrated Device Technology, Inc.
Features
◆◆
◆◆
◆High-speed address/chip select access time
– Military: 20/25/35/45/55/70/85/100ns (max.)
– Industrial: 20/25ns (max.)
– Commercial: 20/25ns (max.)
◆◆
◆◆
◆Low power consumption
◆◆
◆◆
◆Battery backup operation – 2V data retention voltage
(L Version only)
◆◆
◆◆
◆Produced with advanced CMOS high-performance
technology
◆◆
◆◆
◆Inputs and outputs directly TTL-compatible
◆◆
◆◆
◆Three-state outputs
◆◆
◆◆
◆Available in 28-pin DIP, CERDIP and SOJ
◆◆
◆◆
◆Military product compliant to MIL-STD-883, Class B
Description
The IDT7164 is a 65,536 bit high-speed static RAM organized as 8K
x 8. It is fabricated using high-performance, high-reliability CMOS tech-
nology.
Address access times as fast as 20ns are available and the circuit offers
a reduced power standby mode. When CS1 goes HIGH or CS2 goes
LOW, the circuit will automatically go to, and remain in, a low-power stand-
by mode. The low-power (L) version also offers a battery backup data
retention capability at power supply levels as low as 2V.
All inputs and outputs of the IDT7164 are TTL-compatible and
operation is from a single 5V supply, simplifying system designs. Fully
static asynchronous circuitry is used, requiring no clocks or refreshing
for operation.
The IDT7164 is packaged in a 28-pin 300 mil DIP and SOJ and a 28-
pin 600 mil CERDIP.
Military grade product is manufactured in compliance with MIL-STD-
883, Class B, making it ideally suited to military temperature applications
demanding the highest level of performance and reliability.
Functional Block Diagram
ADDRESS
DECODER
65,536 BIT
MEMORY ARRAY
I/O CONTROL
2967 drw 01
WE
CS
V
CC
GND
I/O
0
I/O
7
CONTROL
LOGIC
OE
2
CS
1
A
0
A
12
07
IDT7164S
IDT7164L
CMOS Static RAM
64K (8K x 8-Bit)
2
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
Pin Descriptions
Absolute Maximum Ratings(1)
Truth Table(1,2,3)
Recommended Operating
Temperature and Supply Voltage
Recommended DC Operating
Conditions
Name Description
A
0
- A
12
Address
I/O
0
- I/O
7
Data Inp ut/ Outp ut
CS
1
Chip Select
CS
2
Chip Select
WE Write Enable
OE Output Enable
GND Ground
V
CC
Power
29 67 t b l 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VCC + 0.5V.
Symbol Rating Com'l. Mil. Unit
V
TERM
(2)
Terminal Voltage
with Re s p e ct
to G ND
-0.5 to +7.0 -0.5 to +7.0 V
T
A
Operating
Temperature 0 to +70 -55 to +125
o
C
T
BIAS
Temperature
Under Bias -55 to +125 -65 to +135
o
C
T
STG
Sto rage Te mpe rature -55 to +125 -65 to +150
o
C
P
T
Powe r Dis sip atio n 1. 0 1.0 W
I
OUT
DC Output Curre nt 50 50 mA
2967 tb l 02
NOTES:
1. CS2 will power-down CS1, but CS1 will not power-down CS2.
2. H = VIH, L = VIL, X = don't care.
3. VLC = 0.2V, VHC = VCC - 0.2V
WE CS
1
CS
2
OE I/O Function
X H X X High-Z Deselected - Standby (I
SB
)
X X L X High-Z Deselected - Standby (I
SB
)
XV
HC
V
HC
or
V
LC
X High-Z Deselected - Standby (I
SB1
)
XXV
LC
X High-Z Deselected - Standby (I
SB1
)
H L H H Hig h-Z Outp ut Dis abl ed
HL HLDATA
OUT
Read Data
LLHXDATA
IN
Wri te Data
2967 tbl 03
Grade Temperature GND Vcc
Military -55
O
C to +125
O
C0V 5V ± 10%
Industrial -40
O
C to +85
O
C0V 5V ± 10%
Commercial 0
O
C to + 70
O
C0V 5V ± 10%
2967 tb l 04
NOTE:
1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle.
Symbol Parameter Min. Typ. Max. Unit
V
CC
Supply Voltage 4.5 5.0 5.5 V
GND Ground 0 0 0 V
V
IH
Inp ut HIGH Vo ltag e 2. 2
____
V
CC
+ 0.5 V
V
IL
Input LOW Vo ltage -0.5
(1)
____
0.8 V
2967 tb l 05
Pin Configurations
DIP/SOJ
Top View
2967 drw 02a
5
6
7
8
9
10
11
12
A12
1
2
3
4
24
23
22
21
20
19
18
17
D28-1
D28-3
P28-2
SO28-5
13
14
28
27
26
25
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
VCC
WE
A8
A9
A11
OE
A10
CS1
I/O7
16
15
I/O2
GND
I/O6
I/O5
I/O4
I/O3
NC
CS2
6.42
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
3
DC Electrical Char acteristics(1) (VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
Capacitance (TA = +25°C, f = 1.0MHz)
NOTE:
1. This parameter is determined by device characterization, but is not production
tested.
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Inp ut Cap ac itance V
IN
= 0V 8 pF
C
I/O
I/O Capac itanc e V
OUT
= 0V 8 pF
2967 tbl 06
lobmySretemaraPrewoP
02S4617 02L4617 52S4617 52L4617
tinU
.l'moC.dnI.liM.l'moC.dnI .liM
I
1CC
tnerruCylppuSrewoPgnitarepOSC
1
V=
LI
SC,
2
V=
HI
nepOstuptuO,
V
CC
f,.xaM=
=
0
)2(
S00101101109011011 Am
L0900100109001001
I
2CC
tnerruCgnitarepOcimanyDSC
1
V=
LI
SC,
2
V=
HI
nepOstuptuO,
V
CC
f=f,.xaM=
XAM
)2(
S071071081071071081 Am
L051051061051051061
I
BS
tnerruCylppuSrewoPybdnatS ,)leveLLTT( SC
1
> V
HI
SC,
2
< V
LI
,
V,nepOstuptuO
CC
f=f,.xaM=
XAM
)2(
S020202020202Am
L 335335
I
1BS
tnerruCylppuSrewoPybdnatSlluF 0=f,)leveLSOMC(
)2(
V,
CC
.xaM=
.1 SC
1
> V
CH
SCdna
2
> V
CH
ro,
SC.2
2
< V
CL
S515102515102Am
L2.02.012.02.01
70lbt7692
NOTES:
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
lobmySretemaraPrewoP
53S4617 53L4617 54S4617 54L4617 55S4617 55L4617 07S4617 07L4617 001/58S4617 001/58L4617
tinU.liM .liM.liM.liM.liM
I1CC tnerruCylppuSrewoPgnitarepOSC
1
V=
LI
SC,
2
V=
HI
nepOstuptuO,
V
CC
f,.xaM=
=
0
)2(
S001001001001001 Am
L0909090909
I2CC tnerruCgnitarepOcimanyDSC
1
V=
LI
SC,
2
V=
HI
nepOstuptuO,
V
CC
f=f,.xaM=
XAM
)2(
S061061061061061 Am
L041031521021021
IBS tnerruCylppuSrewoPybdnatS ,)leveLLTT( SC
1
> V
HI
SC,
2
< V
LI
,
V,nepOstuptuO
CC
f=f,.xaM=
XAM
)2(
S0202020202Am
L5555 5
I1BS tnerruCylppuSrewoPybdnatSlluF 0=f,)leveLSOMC(
)2(
V,
CC
.xaM=
.1 SC
1
> V
CH
SCdna
2
> V
CH
ro,
SC.2
2
< V
CL
S0202020202Am
L1111 1
80lbt7692
4
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
DC Electrical Characteristics (VCC = 5.0V ± 10%)
AC Test Conditions
*Includes scope and jig capacitances
Figure 2. AC Test Load
(for tCLZ1, tCLZ2, tOLZ, tCHZ1, tCHZ2, tOHZ, tOW, and tWHZ)
Figure 1. AC Test Load
Data Retention Characteristics Over All Temperature Ranges
(L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V)
2967 drw 03
480Ω
30pF*
255Ω
DATA
OUT
5V
,
2967 drw 04
480Ω
5pF*
255Ω
DATA
OUT
5V
,
Symbol Parameter Test Conditions
IDT7164S IDT7164L
UnitMin. Max. Min. Max.
|I
LI
|Input Le akag e Current V
CC
= Max.,
V
IN
=
GND to V
CC
MIL.
COM' L. & IND
____
____
10
5
____
____
5
2µA
|I
LO
| Output Leakage Current V
CC
= Max., CS
1
= V
IH
,
V
OUT
= GND to V
CC
MIL.
COM' L. & IND
____
____
10
5
____
____
5
2µA
V
OL
Output Low Voltage I
OL
= 8mA, V
CC
= Min.
____
0.4
____
0.4 V
I
OL
= 10mA , V
CC
= Min.
____
0.5
____
0.5
V
OH
Output High Voltage I
OH
= -4mA, V
CC
= Min. 2.4
____
2.4
____
V
2967 t bl 0 9
NOTES:
1. TA = +25°C.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization, but is not production tested.
Typ.
(1)
V
CC
@ Max.
V
CC
@
Sym bol Param eter Test Condi tion Mi n. 2.0V 3.0V 2.0V 3.0V Uni t
V
DR
V
CC
fo r Data Re te ntio n
____
2.0
____ ____ ____ ____
V
I
CCDR
Data Re te ntio n Current MIL.
COM ' L. & IND
____
____
10
10 15
15 200
60 300
90 µA
t
CDR
(3)
Chip Deselect to Data
Re tentio n Time 1. CS
1
> V
HC
CS
2
> V
HC
, or
2. CS
2
< V
LC
0
____ ____ ____ ____
ns
t
R
(3)
Ope ratio n Re co ve ry Time t
RC
(2)
____ ____ ____ ____
ns
I
I
LI
I
(3)
Input Leakage Current
____ ____ ____
22
µA
29 67 t b l 10
Inp ut P ul s e Le v e ls
Inp ut Ris e / Fall Ti me s
Inp ut Ti ming Re fe re nce Le v e ls
Outp ut Re fe renc e Le ve ls
AC Test Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
2967 tbl 11
6.42
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
5
AC Electrical Characteristics (VCC = 5.0V ± 10%, All Temperature Ranges)
NOTES:
1. Both chip selects must be active for the device to be selected.
2. This parameter is guaranteed by device characterization, but is not production tested.
lobmySretemaraP
02S4617 02L4617 52S4617 52L4617
tinU
.niM.xaM.niM.xaM
elcyCdaeR
t
CR
emiTelcyCdaeR02
____
52
____
sn
t
AA
emiTsseccAsserddA
____
91
____
52sn
t
1SCA
)1(
emiTsseccA1-tceleSpihC
____
02
____
52sn
t
2SCA
)1(
emiTsseccA2-tceleSpihC
____
52
____
03sn
t
2,1ZLC
)2(
Z-woLnituptuOot2,1-tceleSpihC5
____
5
____
sn
t
EO
dilaVtuptuOotelbanEtuptuO
____
8
____
21sn
t
ZLO
)2(
Z-woLnituptuOotelbanEtuptuO0
____
0
____
sn
t
2,1ZHC
)2(
Z-hgiHnituptuOot2,1-tceleSpihC
____
9
____
31sn
t
ZHO
)2(
Z-hgiHnituptuOotelbasiDtuptuO
____
8
____
01sn
t
HO
egnahCsserddAmorfdloHtuptuO5
____
5
____
sn
t
UP
)2(
emiTpUrewoPottceleSpihC0
____
0
____
sn
t
DP
)2(
emiTnwoDrewoPottceleseDpihC
____
02
____
52sn
elcyCetirW
t
CW
emiTelcyCetirW02
____
52
____
sn
t
2,1WC
etirW-fo-dnEottceleSpihC51
____
81
____
sn
t
WA
etirW-fo-dnEotdilaVsserddA51
____
81
____
sn
t
SA
emiTpu-teSsserddA0
____
0
____
sn
t
PW
htdiWesluPetirW51
____
12
____
sn
t
1RW
(emiTyrevoceRetirW SC
1
,EW )0
____
0
____
sn
t
2RW
SC(emiTyrevoceRetirW
2
)5
____
5
____
sn
t
ZHW
)2(
Z-hgiHnituptuOotelbanEetirW
____
8
____
01sn
t
WD
palrevOemiTetirWotataD01
____
31
____
sn
t
1HD
emiTetirWmorfdloHataD(SC
1
,EW )0
____
0
____
sn
t
2HD
SC(emiTetirWmorfdloHataD
2
)5
____
5
____
sn
t
WO
)2(
etirW-fo-dnEmorfevitcAtuptuO4
____
4
____
sn
21lbt7692
6
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
AC Electrical Characteristics (con't.) (VCC = 5.0V ± 10%, Military Temperature Ranges)
NOTES:
1. Both chip selects must be active for the device to be selected.
2. This parameter is guaranteed by device characterization, but is not production tested.
lobmySretemaraP
53S4617 53L4617 54S4617 54L4617 55S4617 55L4617 07S4617 07L4617 001/58S4617 001/58L4617
tinU
.xaM.n
iM.niM.xaM.niM.xaM.niM.xaM.niM.xaM
elcyCdaeR
t
CR
emiTelcyCdaeR53
____
54
____
55
____
07
____
001/58
____
sn
t
AA
emiTsseccAsserddA
____
53
____
54
____
55
____
07
____
001/58sn
t
1SCA
)1(
emiTsseccA1-tceleSpihC
____
53
____
54
____
55
____
07
____
001/58sn
t
2SCA
)1(
emiTsseccA2-tceleSpihC
____
04
____
54
____
55
____
07
____
001/58sn
t
2,1ZLC
)2(
Z-woLnituptuOot2,1-tceleSpihC5
____
5
____
5
____
5
____
5
____
sn
t
EO
dilaVtuptuOotelbanEtuptuO
____
81
____
52
____
03
____
53
____
04sn
t
ZLO
)2(
Z-woLnituptuOotelbanEtuptuO0
____
0
____
0
____
0
____
0
____
sn
t
2,1ZHC
)2(
Z-hgiHnituptuOot2,1-tceleSpihC
____
51
____
02
____
52
____
03
____
53sn
t
ZHO
)2(
Z-hgiHnituptuOotelbasiDtuptuO
____
51
____
02
____
52
____
03
____
53sn
t
HO
egnahCsserddAmorfdloHtuptuO5
____
5
____
5
____
5
____
5
____
sn
t
UP
)2(
emiTpUrewoPottceleSpihC0
____
0
____
0
____
0
____
0
____
sn
t
DP
)2(
emiTnwoDrewoPottceleseDpihC
____
53
____
54
____
55
____
07
____
001/58sn
elcyCetirW
t
CW
emiTelcyCetirW53
____
54
____
55
____
07
____
001/58
____
sn
t
2,1WC
etirW-fo-dnEottceleSpihC52
____
33
____
05
____
06
____
57
____
sn
t
WA
etirW-fo-dnEotdilaVsserddA52
____
33
____
05
____
06
____
57
____
sn
t
SA
emiTpu-teSsserddA0
____
0
____
0
____
0
____
0
____
sn
t
PW
htdiWesluPetirW52
____
52
____
05
____
06
____
57
____
sn
t
1RW
(emiTyrevoceRetirW SC
1
,EW )0
____
0
____
0
____
0
____
0
____
sn
t
2RW
SC(emiTyrevoceRetirW
2
)5
____
5
____
5
____
5
____
5
____
sn
t
ZHW
)2(
Z-hgiHnituptuOotelbanEetirW
____
41
____
81
____
52
____
03
____
53sn
t
WD
palrevOemiTetirWotataD51
____
02
____
52
____
03
____
53
____
sn
t
1HD
emiTetirWmorfdloHataD(SC
1
,EW )0
____
0
____
0
____
0
____
0
____
sn
t
2HD
SC(emiTetirWmorfdloHataD
2
)5
____
5
____
5
____
5
____
5
____
sn
t
WO
)2(
etirW-fo-dnEmorfevitcAtuptuO4
____
4
____
4
____
4
____
4
____
sn
31lbt7692
6.42
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
7
Timing W aveform of Read Cycle No. 1(1)
NOTES:
1. WE is HIGH for Read cycle.
2. Device is continuously selected, CS1 is LOW, CS2 is HIGH.
3. Address valid prior to or coincident with CS1 transition LOW and CS2 transition HIGH.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
Timing W aveform of R ead Cycle No. 2(1,2,4)
Timing W aveform of R ead Cycle No. 3(1,3,4)
ADDRESS
CS
1
OE
DATA
OUT
CS
2
t
RC
t
AA
t
OH
t
ACS2
t
CLZ2(5)
t
OE
t
ACS1
t
CLZ1
(5)
t
OLZ (5)
t
CHZ2 (5)
t
OHZ (5)
t
CHZ1 (5)
DATA VALID
2967 drw 05
2967 drw 06
ADDRESS
DATA
OUT
t
RC
t
AA
t
OH
t
OH
DATA VALID
DATA
OUT
t
ACS2
(5)
CS
1
CS
2
t
CLZ2
t
ACS1
(5)
t
CLZ1
t
PU
t
PD
I
CC
I
SB
t
CHZ2 (5)
t
CHZ1(5)
DATA VALID
POWER
SUPPLY
CURRENT
2967 drw 07
8
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
Timing Wav eform of Write Cy cle No . 1 (WE Controlled Timing)(1,5)
Timing Waveform of Write Cyc le No. 2 (CS Controlled Timing)(1)
NOTES:
1. A write occurs during the overlap of a LOW WE, a LOW CS1 and a HIGH CS2.
2. tWR1, 2 is measured from the earlier of CS1 or WE going HIGH or CS2 going LOW to the end of the write cycle.
3 . During this period, I/O pins are in the output state so that the input signals must not be applied.
4. If the CS1 LOW transition or CS2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ +tDW) to allow the I/O drivers to
turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum
write pulse width is as short as the specified tWP.
6. Transition is measured ±200mV from steady state.
ADDRESS
t
WC
t
WHZ (6)
2967 drw 08
CS
1
DATA
OUT
CS
2
t
AS
t
AW
t
WR1(2)
WE
t
WP
t
OW(6)
DATA
IN
t
DH1,2
t
DW
DATA VALID
(3) (5)
ADDRESS
CS
1
CS
2
t
WC
t
AS
WE
t
CW
t
WR2(2)
t
AW
DATA
IN
t
DH1,2
t
DW
DATA VALID
t
WR1
(2)
(4)
2967 drw 09
6.42
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
9
Ordering Information
Low VCC Data Retention Waveform
2967 drw 10
DA
T
A
RETENTION
MODE
4.5V 4.5V
V
DR
≥2V
V
IH
V
IH
t
R
t
CDR
V
CC
CS
V
DR
X
Power
XX
Speed
XXX
Package
X
Process/
Temperature
Range
Blank
I
B
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Military (-55°C to +125°C)
Compliant with MIL-STD-883, Class B
Y
TP
D
TD
300 mil SOJ (SO28-5)
300 mil Plastic DIP (P28-2)
600 mil CERDIP (D28-1)
300 mil CERDIP (D28-3)
S
L
Standard Power
Low Power
Device
Type
7164
2967 drw 11
X
GGreen
Blank
8
Tube or Tray
Tape and Reel
X
20
25
35
45
55
70
85
100
Commercial/Industrial/Military
Military Only
10
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
Datasheet Document History
01/13/00 Updated to new format
Pp. 1, 2, 3, 5, 10 Added Industrial Temperature range offerings
Pp. 1, 3, 9 Removed commercial 70ns speed grade offering
Pp. 1, 3, 6, 10 Added 100ns speed grade specification details
Pg. 3 Revised notes and footnotes in DC Electrical tables
Pp. 5, 6 Revised notes and footnotes in AC Electrical tables
Pg. 8 Removed Note 1 from Write Cycle No. 1 and No. 2 diagrams; renumbered notes and footnotes
Pp. 9, 10 Separated Ordering Information into commercial, industrial, and military offerings
Pg. 11 Added Datasheet Document History
08/09/00 Not recommended for new designs
02/01/01 Removed "Not recommended for new designs"
12/07/01 Pg. 10 Add PJ28 to Industrial temperature.
09/30/04 Pg. 9,10 Added "restricted hazardous substance device" to ordering information.
11/16/06 Pg.3 Added industrial temp power limits for 20ns part. Changed power limits for 25ns part for commercial
and industrial. Changed power limits for commercial and industrial for 35ns part.
Pg.10 Added 20ns part to ordering information. Refer to PCN SR-0602-01
02/20/07 Pg. 9, 10 Added L generation die step to data sheet ordering information.
04/27/11 Pg. 1-3,5,6,9 Obsoleted 24-pin 600 mil, 15ns for Commercial and 35ns for Industrial & Commercial.
Added Tape and Reel to Ordering information and updated description of Restricted hazardous
substance device to Green.
10/30/13: Pg. 1 In the Description: Removed reference to IDT's fabrication and removed "the latest revision of".
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or ipchelp@idt.com
San Jose, CA 95138 408-284-8200 800-345-7015
fax: 408-284-2775
www.idt.com
