CC1020
SWRS046E Page 1 of 89
CC1020
Low-Power RF Transceiver for Narrowband Systems
Applications
• Narrowband low power UHF wireless
data transmitters and receivers with
channel spacing as low as 12.5 and 25
kHz
• 402 / 424 / 426 / 429 / 433 / 447 / 449 /
469 / 868 / 915 / 960 MHz ISM/SRD
band systems
• AMR - Automatic Meter Reading
• Wireless alarm and security systems
• Home automation
• Low power telemetry
Product Description
CC1020
is a true single-chip UHF trans-
ceiver designed for very low power and
very low voltage wireless applications. The
circuit is mainly intended for the ISM
(Industrial, Scientific and Medical) and
SRD (Short Range Device) frequency
bands at 402, 424, 426, 429, 433, 447,
449, 469, 868, 915, and 960 MHz, but can
easily be programmed for multi-channel
operation at other frequencies in the 402 -
470 and 804 - 960 MHz range.
The
CC1020
is especially suited for narrow-
band systems with channel spacing of
12.5 or 25 kHz complying with ARIB STD-
T67 and EN 300 220.
The
CC1020
main operating parameters
can be programmed via a serial bus, thus
making
CC1020
a very flexible and easy to
use transceiver.
In a typical system
CC1020
will be used
together with a microcontroller and a few
external passive components.
Features
• True single chip UHF RF transceiver
• Frequency range 402 MHz - 470 MHz
and 804 MHz - 960 MHz
• High sensitivity (up to -118 dBm for a
12.5 kHz channel)
• Programmable output power
• Low current consumption (RX: 19.9
mA)
• Low supply voltage (2.3 V to 3.6 V)
• No external IF filter needed
• Low-IF receiver
• Very few external components required
• Small size (QFN 32 package)
• Pb-free package
• Digital RSSI and carrier sense indicator
• Data rate up to 153.6 kBaud
• OOK, FSK and GFSK data modulation
• Integrated bit synchronizer
• Image rejection mixer
• Programmable frequency and AFC
make crystal temperature drift
compensation possible without TCXO
• Suitable for frequency hopping systems
• Suited for systems targeting
compliance with EN 300 220, FCC
CFR47 part 15, ARIB STD-T67, and
ARIB STD-T96
• Development kit available
• Easy-to-use software for generating the
CC1020
configuration data
CC1020
SWRS046E Page 2 of 89
Table of Contents
1. Abbreviations................................................................................................................ 4
2. Absolute Maximum Ratings......................................................................................... 5
3. Operating Conditions ................................................................................................... 5
4. Electrical Specifications .............................................................................................. 5
4.1. RF Transmit Section ............................................................................................ 6
4.2. RF Receive Section ............................................................................................. 8
4.3. RSSI / Carrier Sense Section ............................................................................ 11
4.4. IF Section........................................................................................................... 11
4.5. Crystal Oscillator Section................................................................................... 12
4.6. Frequency Synthesizer Section ......................................................................... 13
4.7. Digital Inputs / Outputs....................................................................................... 14
4.8. Current Consumption......................................................................................... 15
5. Pin Assignment........................................................................................................... 15
6. Circuit Description...................................................................................................... 17
7. Application Circuit...................................................................................................... 18
8. Configuration Overview ............................................................................................. 21
8.1. Configuration Software ...................................................................................... 21
9. Microcontroller Interface............................................................................................ 22
9.1. 4-wire Serial Configuration Interface ................................................................. 23
9.2. Signal Interface .................................................................................................. 25
10. Data Rate Programming............................................................................................. 27
11. Frequency Programming ........................................................................................... 28
11.1. Dithering ......................................................................................................... 29
12. Receiver ....................................................................................................................... 30
12.1. IF Frequency .................................................................................................. 30
12.2. Receiver Channel Filter Bandwidth................................................................ 30
12.3. Demodulator, Bit Synchronizer and Data Decision........................................ 31
12.4. Receiver Sensitivity versus Data Rate and Frequency Separation ............... 32
12.5. RSSI ............................................................................................................... 33
12.6. Image Rejection Calibration ........................................................................... 35
12.7. Blocking and Selectivity ................................................................................. 36
12.8. Linear IF Chain and AGC Settings................................................................. 37
12.9. AGC Settling................................................................................................... 38
12.10. Preamble Length and Sync Word .................................................................. 39
12.11. Carrier Sense ................................................................................................. 39
12.12. Automatic Power-up Sequencing................................................................... 40
12.13. Automatic Frequency Control......................................................................... 41
12.14. Digital FM ....................................................................................................... 42
CC1020
SWRS046E Page 3 of 89
13. Transmitter .................................................................................................................. 43
13.1. FSK Modulation Formats ............................................................................... 43
13.2. Output Power Programming........................................................................... 45
13.3. TX Data Latency............................................................................................. 46
13.4. Reducing Spurious Emission and Modulation Bandwidth.............................. 46
14. Input / Output Matching and Filtering....................................................................... 46
15. Frequency Synthesizer .............................................................................................. 50
15.1. VCO, Charge Pump and PLL Loop Filter....................................................... 50
15.2. VCO and PLL Self-Calibration ....................................................................... 51
15.3. PLL Turn-on Time versus Loop Filter Bandwidth........................................... 52
15.4. PLL Lock Time versus Loop Filter Bandwidth................................................ 53
16. VCO and LNA Current Control .................................................................................. 53
17. Power Management .................................................................................................... 54
18. On-Off Keying (OOK).................................................................................................. 57
19. Crystal Oscillator ........................................................................................................ 58
20. Built-in Test Pattern Generator ................................................................................. 59
21. Interrupt on Pin DCLK ................................................................................................ 60
21.1. Interrupt upon PLL Lock................................................................................. 60
21.2. Interrupt upon Received Signal Carrier Sense .............................................. 60
22. PA_EN and LNA_EN Digital Output Pins ................................................................. 61
22.1. Interfacing an External LNA or PA ................................................................. 61
22.2. General Purpose Output Control Pins............................................................ 61
22.3. PA_EN and LNA_EN Pin Drive...................................................................... 61
23. System Considerations and Guidelines................................................................... 62
24. PCB Layout Recommendations ................................................................................ 64
25. Antenna Considerations ............................................................................................ 65
26. Configuration Registers............................................................................................. 65
26.1. CC1020 Register Overview............................................................................ 66
27. Package Marking ........................................................................................................ 86
28. Soldering Information ................................................................................................ 86
29. Plastic Tube Specification ......................................................................................... 86
30. Ordering Information.................................................................................................. 87
31. General Information.................................................................................................... 88
CC1020
SWRS046E Page 4 of 89
1. Abbreviations
ACP Adjacent Channel Power
ACR Adjacent Channel Rejection
ADC Analog-to-Digital Converter
AFC Automatic Frequency Control
AGC Automatic Gain Control
AMR Automatic Meter Reading
ASK Amplitude Shift Keying
BER Bit Error Rate
BOM Bill Of Materials
bps bits per second
BT Bandwidth-Time product (for GFSK)
ChBW Receiver Channel Filter Bandwidth
CW Continuous Wave
DAC Digital-to-Analog Converter
DNM Do Not Mount
ESR Equivalent Series Resistance
FHSS Frequency Hopping Spread Spectrum
FM Frequency Modulation
FS Frequency Synthesizer
FSK Frequency Shift Keying
GFSK Gaussian Frequency Shift Keying
IC Integrated Circuit
IF Intermediate Frequency
IP3 Third Order Intercept Point
ISM Industrial Scientific Medical
kbps kilo bits per second
LNA Low Noise Amplifier
LO Local Oscillator (in receive mode)
MCU Micro Controller Unit
NRZ Non Return to Zero
OOK On-Off Keying
PA Power Amplifier
PD Phase Detector / Power Down
PER Packet Error Rate
PCB Printed Circuit Board
PN9 Pseudo-random Bit Sequence (9-bit)
PLL Phase Locked Loop
PSEL Program Select
RF Radio Frequency
RSSI Received Signal Strength Indicator
RX Receive (mode)
SBW Signal Bandwidth
SPI Serial Peripheral Interface
SRD Short Range Device
TBD To Be Decided/Defined
T/R Transmit/Receive (switch)
TX Transmit (mode)
UHF Ultra High Frequency
VCO Voltage Controlled Oscillator
VGA Variable Gain Amplifier
XOSC Crystal oscillator
XTAL Crystal
CC1020
SWRS046E Page 5 of 89
2. Absolute Maximum Ratings
The absolute maximum ratings given Table 1 should under no circumstances be violated.
Stress exceeding one or more of the limiting values may cause permanent damage to the
device.
Parameter Min Max Unit Condition
Supply voltage, VDD -0.3 5.0 V All supply pins must have the
same voltage
Voltage on any pin -0.3 VDD+0.3, max 5.0 V
Input RF level 10 dBm
Storage temperature range -50 150 °C
Package body temperature 260 °C Norm: IPC/JEDEC J-STD-020 1
Humidity non-condensing 5 85 %
ESD
(Human Body Model)
±1
±0.4
kV
kV
All pads except RF
RF Pads
Table 1. Absolute maximum ratings
1 The reflow peak soldering temperature (body temperature) is specified according to
IPC/JEDEC J-STD_020“Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State
Surface Mount Devices”.
Caution! ESD sensitive device.
Precaution should be used when handling
the device in order to prevent permanent
damage.
3. Operating Conditions
The operating conditions for
CC1020
are listed in Table 2.
Parameter
Min Typ Max Unit Condition / Note
RF Frequency Range 402
804
470
960
MHz
MHz
Programmable in <300 Hz steps
Programmable in <600 Hz steps
Operating ambient temperature range
-40 85
°C
Supply voltage
2.3 3.0 3.6 V
The same supply voltage should
be used for digital (DVDD) and
analog (AVDD) power.
A 3.0 ±0.1 V supply is
recommended to meet the ARIB
STD-T67 selectivity and output
power tolerance requirements.
Table 2. Operating conditions
4. Electrical Specifications
Table 3 to Table 10 gives the
CC1020
electrical specifications. All measurements were
performed using the 2 layer PCB CC1020EMX reference design. This is the same test circuit
as shown in Figure 3. Temperature = 25°C, supply voltage = AVDD = DVDD = 3.0 V if
nothing else stated. Crystal frequency = 14.7456 MHz.
The electrical specifications given for 868 MHz are also applicable for the 902 - 928 MHz
frequency range.
CC1020
SWRS046E Page 6 of 89
4.1. RF Transmit Section
Parameter
Min Typ Max Unit Condition / Note
Transmit data rate
0.45
153.6 kBaud The data rate is programmable.
See section 10 on page 27 for
details.
NRZ or Manchester encoding can
be used. 153.6 kBaud equals
153.6 kbps using NRZ coding
and 76.8 kbps using Manchester
coding. See section 9.2 on page
25 for details
Minimum data rate for OOK is 2.4
kBaud
Binary FSK frequency separation
0
0
108
216
kHz
kHz
in 402 - 470 MHz range
in 804 - 960 MHz range
108/216 kHz is the maximum
specified separation at 1.84 MHz
reference frequency. Larger
separations can be achieved at
higher reference frequencies.
Output power
433 MHz
868 MHz
-20 to +10
-20 to +5
dBm
dBm
Delivered to 50 Ω single-ended
load. The output power is
programmable and should not be
programmed to exceed +10/+5
dBm at 433/868 MHz under any
operating conditions (refer to
CC1020 Errata Note 003). See
section 14 on page 46 for details.
Output power tolerance
-4
+3
dB
dB
At maximum output power
At 2.3 V, +85oC
At 3.6 V, -40oC
Harmonics, radiated CW
2nd harmonic, 433 MHz, +10 dBm
3rd harmonic, 433 MHz, +10 dBm
2nd harmonic, 868 MHz, +5 dBm
3rd harmonic, 868 MHz, +5 dBm
-50
-50
-50
-50
dBc
dBc
dBc
dBc
Harmonics are measured as
EIRP values according to EN 300
220. The antenna (SMAFF-433
and SMAFF-868 from R.W.
Badland) plays a part in
attenuating the harmonics.
Adjacent channel power (GFSK)
12.5 kHz channel spacing, 433 MHz
25 kHz channel spacing, 433 MHz
25 kHz channel spacing, 868 MHz
-46
-52
-49
dBc
dBc
dBc
For 12.5 kHz channel spacing
ACP is measured in a ±4.25 kHz
bandwidth at ±12.5 kHz offset.
Modulation: 2.4 kBaud NRZ PN9
sequence, ±2.025 kHz frequency
deviation.
For 25 kHz channel spacing ACP
is measured in a ±8.5 kHz
bandwidth at ±25 kHz offset.
Modulation: 4.8 kBaud NRZ PN9
sequence, ±2.475 kHz frequency
deviation.
CC1020
SWRS046E Page 7 of 89
Parameter
Min Typ Max Unit Condition / Note
Occupied bandwidth (99.5%,GFSK)
12.5 kHz channel spacing, 433 MHz
25 kHz channel spacing, 433 MHz
25 kHz channel spacing, 868 MHz
7.5
9.6
9.6
kHz
kHz
kHz
Bandwidth for 99.5% of total
average power.
Modulation for 12.5 channel
spacing: 2.4 kBaud NRZ PN9
sequence, ±2.025 kHz frequency
deviation.
Modulation for 25 kHz channel
spacing: 4.8 kBaud NRZ PN9
sequence, ±2.475 kHz frequency
deviation.
Modulation bandwidth, 868 MHz
19.2 kBaud, ±9.9 kHz frequency
deviation
38.4 kBaud, ±19.8 kHz frequency
deviation
48
106
kHz
kHz
Bandwidth where the power
envelope of modulation equals
-36 dBm. Spectrum analyzer
RBW = 1 kHz.
Spurious emission, radiated CW
47-74, 87.5-118,
174-230, 470-862 MHz
9 kHz - 1 GHz
1 - 4 GHz
-54
-36
-30
dBm
dBm
dBm
At maximum output power,
+10/+5 dBm at 433/868 MHz.
To comply with EN 300 220,
FCC CFR47 part 15, ARIB STD-
T67, and ARIB STD-T96 an
external (antenna) filter, as
implemented in the application
circuit in Figure 25, must be used
and tailored to each individual
design to reduce out-of-band
spurious emission levels.
Spurious emissions can be
measured as EIRP values
according to EN 300 220. The
antenna (SMAFF-433 and
SMAFF-868 from R.W. Badland)
plays a part in attenuating the
spurious emissions.
If the output power is increased
using an external PA, a filter must
be used to attenuate spurs below
862 MHz when operating in the
868 MHz frequency band in
Europe. Application Note AN036
CC1020/1021 Spurious Emission
presents and discusses a solution
that reduces the TX mode
spurious emission close to 862
MHz by increasing the REF_DIV
from 1 to 7.
Optimum load impedance
433 MHz
868 MHz
915 MHz
54 + j44
15 + j24
20 + j35
Ω
Ω
Ω
Transmit mode. For matching
details see section 14 on page
46.
Table 3. RF transmit parameters
CC1020
SWRS046E Page 8 of 89
4.2. RF Receive Section
Parameter
Min Typ Max Unit Condition / Note
Receiver Sensitivity, 433 MHz, FSK
12.5 kHz channel spacing, optimized
selectivity, ±2.025 kHz freq. deviation
12.5 kHz channel spacing, optimized
sensitivity, ±2.025 kHz freq. deviation
25 kHz channel spacing
500 kHz channel spacing
Receiver Sensitivity, 868 MHz, FSK
12.5 kHz channel spacing, ±2.475
kHz freq. deviation
25 kHz channel spacing
500 kHz channel spacing
-114
-118
-112
-96
-116
-111
-94
dBm
dBm
dBm
dBm
dBm
dBm
dBm
Sensitivity is measured with PN9
sequence at BER = 10-3
12.5 kHz channel spacing:
2.4 kBaud, Manchester coded
data.
25 kHz channel spacing:
4.8 kBaud, NRZ coded data,
±2.475 kHz frequency deviation.
500 kHz channel spacing:
153.6 kBaud, NRZ coded data,
±72 kHz frequency deviation.
See Table 19 and Table 20 for
typical sensitivity figures at other
data rates.
Receiver sensitivity, 433 MHz, OOK
2.4 kBaud
153.6 kBaud
Receiver sensitivity, 868 MHz, OOK
4.8 kBaud
153.6 kBaud
-116
-81
-107
-87
dBm
dBm
dBm
dBm
Sensitivity is measured with PN9
sequence at BER = 10-3
Manchester coded data.
See Table 27 for typical
sensitivity figures at other data
rates.
Saturation (maximum input level)
FSK and OOK
10
dBm
FSK: Manchester/NRZ coded
data
OOK: Manchester coded data
BER = 10-3
System noise bandwidth 9.6
to
307.2
kHz The receiver channel filter 6 dB
bandwidth is programmable from
9.6 kHz to 307.2 kHz. See
section 12.2 on page 30 for
details.
Noise figure, cascaded
433 and 868 MHz
7
dB
NRZ coded data
Input IP3
433 MHz, 12.5 kHz channel spacing
868 MHz, 25 kHz channel spacing
-23
-18
-16
-18
-15
-13
dBm
dBm
dBm
dBm
dBm
dBm
Two tone test (+10 MHz and +20
MHz)
LNA2 maximum gain
LNA2 medium gain
LNA2 minimum gain
LNA2 maximum gain
LNA2 medium gain
LNA2 minimum gain
CC1020
SWRS046E Page 9 of 89
Parameter
Min Typ Max Unit Condition / Note
Co-channel rejection, FSK and OOK
12.5 kHz channel spacing, 433 MHz
25 kHz channel spacing, 433 MHz
25 kHz channel spacing, 868 MHz
-11
-11
-11
dB
dB
dB
Wanted signal 3 dB above the
sensitivity level, FM jammer (1
kHz sine, ± 2.5 kHz deviation) at
operating frequency,
BER = 10-3
Adjacent channel rejection (ACR)
12.5 kHz channel spacing, 433 MHz
25 kHz channel spacing, 433 MHz
25 kHz channel spacing, 868 MHz
32
37
32
dB
dB
dB
Wanted signal 3 dB above the
sensitivity level, FM jammer (1
kHz sine, ± 2.5 kHz deviation) at
adjacent channel. BER = 10-3
Image channel rejection
433/868 MHz
No I/Q gain and phase calibration
I/Q gain and phase calibrated
26/31
49/52
dB
dB
Wanted signal 3 dB above the
sensitivity level, CW jammer at
image frequency. BER = 10-3.
Image rejection after calibration
will depend on temperature and
supply voltage. Refer to section
12.6 on page 35.
Selectivity*
12.5 kHz channel spacing, 433 MHz
25 kHz channel spacing, 433 MHz
25 kHz channel spacing, 868 MHz
(*Close-in spurious response
rejection)
41
41
39
dB
dB
dB
Wanted signal 3 dB above the
sensitivity level. CW jammer is
swept in 12.5 kHz/25 kHz steps
to within ± 1 MHz from wanted
channel. BER = 10-3. Adjacent
channel and image channel are
excluded.
Blocking / Desensitization*
433/868 MHz
± 1 MHz
± 2 MHz
± 5 MHz
± 10 MHz
(*Out-of-band spurious response
rejection)
50/57
64/71
64/71
75/78
dB
dB
dB
dB
Wanted signal 3 dB above the
sensitivity level, CW jammer at ±
1, 2, 5 and 10 MHz offset.
BER = 10-3. 12.5 kHz/25 kHz
channel spacing at 433/868 MHz.
Complying with EN 300 220,
class 2 receiver requirements.
Image frequency suppression,
433/868 MHz
No I/Q gain and phase calibration
I/Q gain and phase calibrated
36/41
59/62
dB
dB
Ratio between sensitivity for a
signal at the image frequency to
the sensitivity in the wanted
channel. Image frequency is RF-
2 IF. The signal source is a 2.4
kBaud, Manchester coded data,
±2.025 kHz frequency deviation,
signal level for BER = 10-3
Spurious reception
40 dB Ratio between sensitivity for an
unwanted frequency to the
sensitivity in the wanted channel.
The signal source is a 2.4 kBaud,
Manchester coded data, ±2.025
kHz frequency deviation, swept
over all frequencies 100 MHz - 2
GHz. Signal level for BER = 10-3
Intermodulation rejection (1)
12.5 kHz channel spacing, 433 MHz
25 kHz channel spacing, 868 MHz
30
30
dB
dB
Wanted signal 3 dB above the
sensitivity level, two CW jammers
at +2Ch and +4Ch where Ch is
channel spacing 12.5 kHz or 25
kHz. BER = 10-2
CC1020
SWRS046E Page 10 of 89
Parameter
Min Typ Max Unit Condition / Note
Intermodulation rejection (2)
12.5 kHz channel spacing, 433 MHz
25 kHz channel spacing, 868 MHz
56
55
dB
dB
Wanted signal 3 dB above the
sensitivity level, two CW jammers
at +10 MHz and +20 MHz offset.
BER = 10-2
LO leakage, 433/868 MHz <-80/-66 dBm
VCO leakage -64 dBm VCO frequency resides between
1608 - 1880 MHz
Spurious emission, radiated CW
9 kHz - 1 GHz
1 - 4 GHz
<-60
<-60
dBm
dBm
Complying with EN 300 220,
FCC CFR47 part 15, ARIB STD-
T67, and ARIB STD-T96.
Spurious emissions can be
measured as EIRP values
according to EN 300 220.
Input impedance
433 MHz
868 MHz
58 - j10
54 - j22
Ω
Ω
Receive mode. See section 14 on
page 46 for details.
Matched input impedance, S11
433 MHz
868 MHz
-14
-12
dB
dB
Using application circuit matching
network. See section 14 on page
46 for details.
Matched input impedance
433 MHz
868 MHz
39 - j14
32 - j10
Ω
Ω
Using application circuit matching
network. See section 14 on page
46 for details.
Bit synchronization offset 8000 ppm The maximum bit rate offset
tolerated by the bit
synchronization circuit for 6 dB
degradation (synchronous modes
only)
Data latency
NRZ mode
Manchester mode
4
8
Baud
Baud
Time from clocking the data on
the transmitter DIO pin until data
is available on receiver DIO pin
Table 4. RF receive parameters
CC1020
SWRS046E Page 11 of 89
4.3. RSSI / Carrier Sense Section
Parameter
Min Typ Max Unit Condition / Note
RSSI dynamic range
55 dB 12.5 and 25 kHz channel spacing
RSSI accuracy ± 3
dB
See section 12.5 on page 33 for
details.
RSSI linearity ± 1 dB
RSSI attach time
2.4 kBaud, 12.5 kHz channel spacing
4.8 kBaud, 25 kHz channel spacing
153.6 kBaud, 500 kHz channel spacing
3.8
1.9
140
ms
ms
µs
Shorter RSSI attach times can be
traded for lower RSSI accuracy.
See section 12.5 on page 33 for
details.
Shorter RSSI attach times can
also be traded for reduced
sensitivity and selectivity by
increasing the receiver channel
filter bandwidth.
Carrier sense programmable range
40 dB Accuracy is as for RSSI
Adjacent channel carrier sense
12.5 kHz channel spacing
25 kHz channel spacing
-72
-72
dBm
dBm
At carrier sense level −110 dBm,
FM jammer (1 kHz sine, ±2.5 kHz
deviation) at adjacent channel.
Adjacent channel carrier sense is
measured by applying a signal on
the adjacent channel and observe
at which level carrier sense is
indicated.
Spurious carrier sense
-70 dBm At carrier sense level −110 dBm,
100 MHz - 2 GHz. Adjacent
channel and image channel are
excluded.
Table 5. RSSI / Carrier sense parameters
4.4. IF Section
Parameter
Min Typ Max Unit Condition / Note
Intermediate frequency (IF)
307.2 kHz See section 12.1 on page 30 for
details.
Digital channel filter bandwidth
9.6
to
307.2
kHz
The channel filter 6 dB bandwidth
is programmable from 9.6 kHz to
307.2 kHz. See section 12.2 on
page 30 for details.
AFC resolution
150 Hz
At 2.4 kBaud
Given as Baud rate/16. See
section 12.13 on page 41 for
details.
Table 6. IF section parameters
CC1020
SWRS046E Page 12 of 89
4.5. Crystal Oscillator Section
Parameter
Min Typ Max Unit Condition / Note
Crystal Oscillator Frequency
4.9152 14.7456 19.6608 MHz Recommended frequency is
14.7456 MHz. See section 19 on
page 58 for details.
Reference frequency accuracy
requirement
+/- 5.7
+/- 2.8
+/- 4
ppm
ppm
ppm
433 MHz (EN 300 220)
868 MHz (EN 300 220)
Must be less than ±5.7 / ±2.8
ppm to comply with EN 300 220
25 kHz channel spacing at
433/868 MHz.
Must be less than ±4 ppm to
comply with Japanese 12.5 kHz
channel spacing regulations
(ARIB STD-T67).
NOTE:
The reference frequency
accuracy (initial tolerance) and
drift (aging and temperature
dependency) will determine the
frequency accuracy of the
transmitted signal.
Crystal oscillator temperature
compensation can be done using
the fine step PLL frequency
programmability and the AFC
feature. See section 12.13 on
page 41 for details.
Crystal operation
Parallel
C4 and C5 are loading
capacitors. See section 19 on
page 58 for details.
Crystal load capacitance
12
12
12
22
16
16
30
30
16
pF
pF
pF
4.9-6 MHz, 22 pF recommended
6-8 MHz, 16 pF recommended
8-19.6 MHz, 16 pF recommended
Crystal oscillator start-up time 1.55
1.0
0.90
0.95
0.60
0.63
ms
ms
ms
ms
ms
ms
4.9152 MHz, 12 pF load
7.3728 MHz, 12 pF load
9.8304 MHz, 12 pF load
14.7456 MHz, 16 pF load
17.2032 MHz, 12 pF load
19.6608 MHz, 12 pF load
External clock signal drive,
sine wave
300
mVpp
The external clock signal must be
connected to XOSC_Q1 using a
DC block (10 nF). Set
XOSC_BYPASS = 0 in the
INTERFACE register when using
an external clock signal with low
amplitude or a crystal.
External clock signal drive,
full-swing digital external clock
0 - VDD
V
The external clock signal must be
connected to XOSC_Q1. No DC
block shall be used. Set
XOSC_BYPASS = 1 in the
INTERFACE register when using
a full-swing digital external clock.
Table 7. Crystal oscillator parameters
CC1020
SWRS046E Page 13 of 89
4.6. Frequency Synthesizer Section
Parameter
Min Typ Max Unit Condition / Note
Phase noise, 402 - 470 MHz
12.5 kHz channel spacing
-90
-100
-105
-110
-114
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Unmodulated carrier
At 12.5 kHz offset from carrier
At 25 kHz offset from carrier
At 50 kHz offset from carrier
At 100 kHz offset from carrier
At 1 MHz offset from carrier
Measured using loop filter
components given in Table 13.
The phase noise will be higher for
larger PLL loop filter bandwidth.
Phase noise, 804 - 960 MHz
25 kHz channel spacing
-85
-95
-101
-109
-118
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Unmodulated carrier
At 12.5 kHz offset from carrier
At 25 kHz offset from carrier
At 50 kHz offset from carrier
At 100 kHz offset from carrier
At 1 MHz offset from carrier
Measured using loop filter
components given in Table 13.
The phase noise will be higher for
larger PLL loop filter bandwidth.
PLL loop bandwidth
12.5 kHz channel spacing, 433 MHz
25 kHz channel spacing, 868 MHz
2.7
8.3
kHz
kHz
After PLL and VCO calibration.
The PLL loop bandwidth is
programmable.
PLL lock time (RX / TX turn time)
12.5 kHz channel spacing, 433 MHz
25 kHz channel spacing, 868 MHz
500 kHz channel spacing
900
640
14
us
us
us
307.2 kHz frequency step to RF
frequency within ±10% of channel
spacing. Depends on loop filter
component values and PLL_BW
register setting. See Table 26 on
page 53 for more details.
PLL turn-on time. From power down
mode with crystal oscillator running.
12.5 kHz channel spacing, 433 MHz
25 kHz channel spacing, 868 MHz
500 kHz channel spacing
3.2
2.5
700
ms
ms
us
Time from writing to registers to
RF frequency within ±10% of
channel spacing. Depends on
loop filter component values and
PLL_BW register setting. See
Table 25 on page 53 for more
details.
Table 8. Frequency synthesizer parameters
CC1020
SWRS046E Page 14 of 89
4.7. Digital Inputs / Outputs
Parameter
Min Typ Max Unit Condition / Note
Logic « 0 » input voltage
0 0.3*
VDD
V
Logic « 1 » input voltage
0.7*
VDD
VDD V
Logic « 0 » output voltage 0
0.4 V Output current −2.0 mA,
3.0 V supply voltage
Logic « 1 » output voltage 2.5
VDD V Output current 2.0 mA,
3.0 V supply voltage
Logic “0” input current
NA −1 µA Input signal equals GND.
PSEL has an internal pull-up
resistor and during configuration
the current will be -350 µA.
Logic “1” input current
NA 1 µA Input signal equals VDD
DIO setup time 20 ns TX mode, minimum time DIO
must be ready before the positive
edge of DCLK. Data should be
set up on the negative edge of
DCLK.
DIO hold time
10 ns TX mode, minimum time DIO
must be held after the positive
edge of DCLK. Data should be
set up on the negative edge of
DCLK.
Serial interface (PCLK, PDI, PDO
and PSEL) timing specification
See Table 14 on page 24 for
more details
Pin drive, LNA_EN, PA_EN
0.90
0.87
0.81
0.69
0.93
0.92
0.89
0.79
mA
mA
mA
mA
mA
mA
mA
mA
Source current
0 V on LNA_EN, PA_EN pins
0.5 V on LNA_EN, PA_EN pins
1.0 V on LNA_EN, PA_EN pins
1.5 V on LNA_EN, PA_EN pins
Sink current
3.0 V on LNA_EN, PA_EN pins
2.5 V on LNA_EN, PA_EN pins
2.0 V on LNA_EN, PA_EN pins
1.5 V on LNA_EN, PA_EN pins
See Figure 35 on page 62 for
more details.
Table 9. Digital inputs / outputs parameters
CC1020
SWRS046E Page 15 of 89
4.8. Current Consumption
Parameter
Min Typ Max Unit Condition / Note
Power Down mode
0.2 1.8
µA Oscillator core off
Current Consumption,
receive mode 433 and 868 MHz
19.9 mA
Current Consumption,
transmit mode 433/868 MHz :
P = -20 dBm
P = -5 dBm
P = 0 dBm
P = +5 dBm
P = +10 dBm (433 MHz only)
12.3/14.5
14.4/17.0
16.2/20.5
20.5/25.1
27.1
mA
mA
mA
mA
mA
The output power is delivered to
a 50 Ω single-ended load.
See section 13.2 on page 45 for
more details.
Current Consumption, crystal
oscillator
Current Consumption, crystal
oscillator and bias
Current Consumption, crystal
oscillator, bias and synthesizer
77
500
7.5
µA
µA
mA
14.7456 MHz, 16 pF load crystal
14.7456 MHz, 16 pF load crystal
14.7456 MHz, 16 pF load crystal
Table 10. Current consumption
5. Pin Assignment
Table 11 provides an overview of the
CC1020
pinout.
The
CC1020
comes in a QFN32 type
package.
PCLK 1VC24
AVDD
23
AVDD
22
RF_OUT
21
AVDD
20
RF_IN
19
AVDD
18
R_BIAS
17
AVDD16
PA_EN
15
LNA_EN
14
AVDD
13
AVDD
12
XOSC_Q2
11
XOSC_Q1
10
LOCK
9
DIO 8
DCLK 7
DGND 6
DVDD 5
DGND 4
PDO 3
PDI 2
32PSEL
31DVDD
30DGND
29AVDD
28CHP_OUT
27AVDD
26AD_REF
25AGND
AGND
Exposed die
attached pad
Figure 1.
CC1020
package (top view)
CC1020
SWRS046E Page 16 of 89
Pin no. Pin name Pin type Description
- AGND Ground (analog) Exposed die attached pad. Must be soldered to a solid ground plane as
this is the ground connection for all analog modules. See page 64 for
more details.
1 PCLK Digital input Programming clock for SPI configuration interface
2 PDI Digital input Programming data input for SPI configuration interface
3 PDO Digital output Programming data output for SPI configuration interface
4 DGND Ground (digital) Ground connection (0 V) for digital modules and digital I/O
5 DVDD Power (digital) Power supply (3 V typical) for digital modules and digital I/O
6 DGND Ground (digital) Ground connection (0 V) for digital modules (substrate)
7 DCLK Digital output Clock for data in both receive and transmit mode.
Can be used as receive data output in asynchronous mode
8 DIO Digital input/output Data input in transmit mode; data output in receive mode
Can also be used to start power-up sequencing in receive
9 LOCK Digital output PLL Lock indicator, active low. Output is asserted (low) when PLL is in
lock. The pin can also be used as a general digital output, or as receive
data output in synchronous NRZ/Manchester mode
10 XOSC_Q1 Analog input Crystal oscillator or external clock input
11 XOSC_Q2 Analog output Crystal oscillator
12 AVDD Power (analog) Power supply (3 V typical) for crystal oscillator
13 AVDD Power (analog) Power supply (3 V typical) for the IF VGA
14 LNA_EN Digital output General digital output. Can be used for controlling an external LNA if
higher sensitivity is needed.
15 PA_EN Digital output General digital output. Can be used for controlling an external PA if
higher output power is needed.
16 AVDD Power (analog) Power supply (3 V typical) for global bias generator and IF anti-alias
filter
17 R_BIAS Analog output
Connection for external precision bias resistor (82 kΩ, ± 1%)
18 AVDD Power (analog) Power supply (3 V typical) for LNA input stage
19 RF_IN RF Input RF signal input from antenna (external AC-coupling)
20 AVDD Power (analog) Power supply (3 V typical) for LNA
21 RF_OUT RF output RF signal output to antenna
22 AVDD Power (analog) Power supply (3 V typical) for LO buffers, mixers, prescaler, and first PA
stage
23 AVDD Power (analog) Power supply (3 V typical) for VCO
24 VC Analog input VCO control voltage input from external loop filter
25 AGND Ground (analog) Ground connection (0 V) for analog modules (guard)
26 AD_REF Power (analog) 3 V reference input for ADC
27 AVDD Power (analog) Power supply (3 V typical) for charge pump and phase detector
28 CHP_OUT Analog output PLL charge pump output to external loop filter
29 AVDD Power (analog) Power supply (3 V typical) for ADC
30 DGND Ground (digital) Ground connection (0 V) for digital modules (guard)
31 DVDD Power (digital) Power supply connection (3 V typical) for digital modules
32 PSEL Digital input Programming chip select, active low, for configuration interface. Internal
pull-up resistor.
Table 11. Pin assignment overview
Note:
DCLK, DIO and LOCK are high-
impedance (3-state) in power down
(BIAS_PD = 1 in the MAIN register).
The exposed die attached pad must be
soldered to a solid ground plane as this is
the main ground connection for the chip.
CC1020
SWRS046E Page 17 of 89
6. Circuit Description
RF_IN LNA
FREQ
SYNTH
DIGITAL
DEMODULATOR
- Digital RSSI
- Gain Control
- Image Suppression
- Channel Filtering
- Demodulation
DIGITAL
MODULATOR
- Modulation
- Data shaping
- Power Control
BIAS
Power
Control
DIGITAL
INTERFACE
TO µC
CONTROL
LOGIC
PA
ADC
ADC
RF_OUT
R_BIAS XOSC_Q1 XOSC_Q2
PDO
XOSC
VC CHP_OUT
LNA 2
0
90 :2
0
90 :2
Multiplexer
Multiplexer
PA_EN LNA_EN
PCLK
PDI
PSEL
Figure 2.
CC1020
simplified block diagram
A simplified block diagram of
CC1020
is
shown in Figure 2. Only signal pins are
shown.
CC1020
features a low-IF receiver. The
received RF signal is amplified by the low-
noise amplifier (LNA and LNA2) and
down-converted in quadrature (I and Q) to
the intermediate frequency (IF). At IF, the
I/Q signal is complex filtered and
amplified, and then digitized by the ADCs.
Automatic gain control, fine channel
filtering, demodulation and bit
synchronization is performed digitally.
CC1020
outputs the digital demodulated
data on the DIO pin. A synchronized data
clock is available at the DCLK pin. RSSI is
available in digital format and can be read
via the serial interface. The RSSI also
features a programmable carrier sense
indicator.
In transmit mode, the synthesized RF
frequency is fed directly to the power
amplifier (PA). The RF output is frequency
shift keyed (FSK) by the digital bit stream
that is fed to the DIO pin. Optionally, a
Gaussian filter can be used to obtain
Gaussian FSK (GFSK).
The frequency synthesizer includes a
completely on-chip LC VCO and a 90
degrees phase splitter for generating the
LO_I and LO_Q signals to the down-
conversion mixers in receive mode. The
VCO operates in the frequency range
1.608-1.880 GHz. The CHP_OUT pin is
the charge pump output and VC is the
control node of the on-chip VCO. The
external loop filter is placed between these
pins. A crystal is to be connected between
XOSC_Q1 and XOSC_Q2. A lock signal is
available from the PLL.
The 4-wire SPI serial interface is used for
configuration.
CC1020
SWRS046E Page 18 of 89
7. Application Circuit
Very few external components are
required for the operation of
CC1020
. The
recommended application circuit is shown
in Figure 3. The external components are
described in Table 12 and values are
given in Table 13.
Input / output matching
L1 and C1 are the input match for the
receiver. L1 is also a DC choke for
biasing. L2 and C3 are used to match the
transmitter to 50 Ω. Internal circuitry
makes it possible to connect the input and
output together and match the
CC1020
to
50 Ω in both RX and TX mode. However, it
is recommended to use an external T/R
switch for optimum performance. See
section 14 on page 46 for details.
Component values for the matching
network are easily found using the
SmartRF® Studio software.
Bias resistor
The precision bias resistor R1 is used to
set an accurate bias current.
PLL loop filter
The loop filter consists of two resistors (R2
and R3) and three capacitors (C6-C8). C7
and C8 may be omitted in applications
where high loop bandwidth is desired. The
values shown in Table 13 can be used for
data rates up to 4.8 kBaud. Component
values for higher data rates are easily
found using the SmartRF® Studio
software.
Crystal
An external crystal with two loading
capacitors (C4 and C5) is used for the
crystal oscillator. See section 19 on page
58 for details.
Additional filtering
Additional external components (e.g. RF
LC or SAW filter) may be used in order to
improve the performance in specific
applications. See section 14 on page 46
for further information.
Power supply decoupling and filtering
Power supply decoupling and filtering
must be used (not shown in the application
circuit). The placement and size of the
decoupling capacitors and the power
supply filtering are very important to
achieve the optimum performance for
narrowband applications. TI provides a
reference design that should be followed
very closely.
Ref Description
C1 LNA input match and DC block, see page 46
C3 PA output match and DC block, see page 46
C4 Crystal load capacitor, see page 58
C5 Crystal load capacitor, see page 58
C6 PLL loop filter capacitor
C7 PLL loop filter capacitor (may be omitted for highest loop bandwidth)
C8 PLL loop filter capacitor (may be omitted for highest loop bandwidth)
C60 Decoupling capacitor
L1 LNA match and DC bias (ground), see page 46
L2 PA match and DC bias (supply voltage), see page 46
R1 Precision resistor for current reference generator
R2 PLL loop filter resistor
R3 PLL loop filter resistor
R10 PA output match, see page 46
XTAL Crystal, see page 58
Table 12. Overview of external components (excluding supply decoupling capacitors)
CC1020
SWRS046E Page 19 of 89
1PCLK
PDI
PDO
DGND
DGND
DCLK
DIO
DVDD
2
3
4
6
5
7
8
CC1020
9
LOCK
10
XOSC_Q1
11
XOSC_Q2
12
AVDD
13
AVDD
14
LNA_EN
15
PA_EN
16
AVDD
32 PSEL
31 DVDD
30 DGND
29 AVDD
28 CHP_OUT
27 AVDD
26 AD_REF
25 AGND
24
VC
AVDD
AVDD
RF_OUT
RF_IN
AVDD
R_BIAS
AVDD
23
22
21
19
20
18
17
C4C5
XTAL
LC Filter
Monopole
antenna
(50 Ohm)
L2
C3
AVDD=3V
L1
C1
R1
AVDD=3V
AVDD=3V
DVDD=3V
DVDD=3V
AVDD=3V
Microc ontroller configuration i nterfac e and signal interfac e
C7 R3
C8
C6
R2
AVDD=3V
T/R Switch
C60
R10
1PCLK
PDI
PDO
DGND
DGND
DCLK
DIO
DVDD
2
3
4
6
5
7
8
CC1020
9
LOCK
10
XOSC_Q1
11
XOSC_Q2
12
AVDD
13
AVDD
14
LNA_EN
15
PA_EN
16
AVDD
32 PSEL
31 DVDD
30 DGND
29 AVDD
28 CHP_OUT
27 AVDD
26 AD_REF
25 AGND
24
VC
AVDD
AVDD
RF_OUT
RF_IN
AVDD
R_BIAS
AVDD
23
22
21
19
20
18
17
C4C4C5C5
XTALXTAL
LC FilterLC Filter
Monopole
antenna
(50 Ohm)
L2
C3
AVDD=3V
L1
C1
R1
AVDD=3V
AVDD=3V
DVDD=3V
DVDD=3V
AVDD=3V
Microc ontroller configuration i nterfac e and signal interfac e
C7 R3
C8
C6
R2
AVDD=3V
T/R Switch
C60
R10
Figure 3. Typical application and test circuit (power supply decoupling not shown)
Item 433 MHz 868 MHz 915 MHz
C1 10 pF, 5%, NP0, 0402 47 pF, 5%, NP0, 0402 47 pF, 5%, NP0, 0402
C3 5.6 pF, 5%, NP0, 0402 10 pF, 5%, NP0, 0402 10 pF, 5%, NP0, 0402
C4 22 pF, 5%, NP0, 0402 22 pF, 5%, NP0, 0402 22 pF, 5%, NP0, 0402
C5 12 pF, 5%, NP0, 0402 12 pF, 5%, NP0, 0402 12 pF, 5%, NP0, 0402
C6 220 nF, 10%, X7R, 0603 100 nF, 10%, X7R, 0603 100 nF, 10%, X7R, 0603
C7 8.2 nF, 10%, X7R, 0402 3.9 nF, 10%, X7R, 0402 3.9 nF, 10%, X7R, 0402
C8 2.2 nF, 10%, X7R, 0402 1.0 nF, 10%, X7R, 0402 1.0 nF, 10%, X7R, 0402
C60 220 pF, 5%, NP0, 0402 220 pF, 5%, NP0, 0402 220 pF, 5%, NP0, 0402
L1 33 nH, 5%, 0402 82 nH, 5%, 0402 82 nH, 5%, 0402
L2 22 nH, 5%, 0402 3.6 nH, 5%, 0402 3.6 nH, 5%, 0402
R1 82 kΩ, 1%, 0402 82 kΩ, 1%, 0402 82 kΩ, 1%, 0402
R2 1.5 kΩ, 5%, 0402 2.2 kΩ, 5%, 0402 2.2 kΩ, 5%, 0402
R3 4.7 kΩ, 5%, 0402 6.8 kΩ, 5%, 0402 6.8 kΩ, 5%, 0402
R10 82 Ω, 5%, 0402 82 Ω, 5%, 0402 82 Ω, 5%, 0402
XTAL 14.7456 MHz crystal,
16 pF load
14.7456 MHz crystal,
16 pF load
14.7456 MHz crystal,
16 pF load
Note: Items shaded vary for different frequencies. For 433 MHz, 12.5 kHz channel, a loop filter with
lower bandwidth is used to improve adjacent and alternate channel rejection.
Table 13. Bill of materials for the application circuit in Figure 3
Note:
The PLL loop filter component values in
Table 13 (R2, R3, C6-C8) can be used for
data rates up to 4.8 kBaud. The SmartRF®
Studio software provides component
values for other data rates using the
equations on page 50.
In the CC1020EMX reference design
LQG15HS series inductors from Murata
have been used. The switch is SW-456
from M/A-COM.
CC1020
SWRS046E Page 20 of 89
The LC filter in Figure 3 is inserted in the
TX path only. The filter will reduce the
emission of harmonics and the spurious
emissions in the TX path. An alternative is
to insert the LC filter between the antenna
and the T/R switch as shown in Figure 4.
The filter will reduce the emission of
harmonics and the spurious emissions in
the TX path as well as increase the
receiver selectivity. The sensitivity will be
slightly reduced due to the insertion loss of
the LC filter.
1PCLK
PDI
PDO
DGND
DGND
DCLK
DIO
DVDD
2
3
4
6
5
7
8
CC1020
9
LOCK
10
XOSC_Q1
11
XOSC_Q2
12
AVDD
13
AVDD
14
LNA_EN
15
PA_EN
16
AVDD
32 PSEL
31 DVDD
30 DGND
29 AVDD
28 CHP_OUT
27 AVDD
26 AD_REF
25 AGND
24
VC
AVDD
AVDD
RF_OUT
RF_IN
AVDD
R_BIAS
AVDD
23
22
21
19
20
18
17
C4C5
XTAL
LC Filter
Monopole
antenna
(50 Ohm)
L2
C3
AVDD=3V
L1
C1
R1
AVDD=3V
AVDD=3V
DVDD=3V
DVDD=3V
AVDD=3V
Microc ontroller configuration i nterfac e and signal interfac e
C7 R3
C8
C6
R2
AVDD=3V
T/R Switch
C60
R10
1PCLK
PDI
PDO
DGND
DGND
DCLK
DIO
DVDD
2
3
4
6
5
7
8
CC1020
9
LOCK
10
XOSC_Q1
11
XOSC_Q2
12
AVDD
13
AVDD
14
LNA_EN
15
PA_EN
16
AVDD
32 PSEL
31 DVDD
30 DGND
29 AVDD
28 CHP_OUT
27 AVDD
26 AD_REF
25 AGND
24
VC
AVDD
AVDD
RF_OUT
RF_IN
AVDD
R_BIAS
AVDD
23
22
21
19
20
18
17
C4C4C5C5
XTALXTAL
LC FilterLC Filter
Monopole
antenna
(50 Ohm)
L2
C3
AVDD=3V
L1
C1
R1
AVDD=3V
AVDD=3V
DVDD=3V
DVDD=3V
AVDD=3V
Microc ontroller configuration i nterfac e and signal interfac e
C7 R3
C8
C6
R2
AVDD=3V
T/R Switch
C60
R10
Figure 4. Alternative application circuit (power supply decoupling not shown)
CC1020
SWRS046E Page 21 of 89
8. Configuration Overview
CC1020
can be configured to achieve
optimum performance for different
applications. Through the programmable
configuration registers the following key
parameters can be programmed:
• Receive / transmit mode
• RF output power
• Frequency synthesizer key parameters:
RF output frequency, FSK frequency
separation, crystal oscillator reference
frequency
• Power-down / power-up mode
• Crystal oscillator power-up / power-
down
• Data rate and data format (NRZ,
Manchester coded or UART interface)
• Synthesizer lock indicator mode
• Digital RSSI and carrier sense
• FSK / GFSK / OOK modulation
8.1. Configuration Software
TI provides users of
CC1020
with a
software program, SmartRF® Studio
(Windows interface) that generates all
necessary
CC1020
configuration data
based on the user’s selections of various
parameters. These hexadecimal numbers
will then be the necessary input to the
microcontroller for the configuration of
CC1020
. In addition, the program will
provide the user with the component
values needed for the input/output
matching circuit, the PLL loop filter and the
LC filter.
Figure 5 shows the user interface of the
CC1020
configuration software.
Figure 5. SmartRF® Studio user interface
CC1020
SWRS046E Page 22 of 89
9. Microcontroller Interface
Used in a typical system,
CC1020
will
interface to a microcontroller. This
microcontroller must be able to:
• Program
CC1020
into different modes
via the 4-wire serial configuration
interface (PDI, PDO, PCLK and PSEL)
• Interface to the bi-directional
synchronous data signal interface (DIO
and DCLK)
• Optionally, the microcontroller can do
data encoding / decoding
• Optionally, the microcontroller can
monitor the LOCK pin for frequency
lock status, carrier sense status or
other status information.
• Optionally, the microcontroller can read
back the digital RSSI value and other
status information via the 4-wire serial
interface
Configuration interface
The microcontroller interface is shown in
Figure 6. The microcontroller uses 3 or 4
I/O pins for the configuration interface
(PDI, PDO, PCLK and PSEL). PDO should
be connected to a microcontroller input.
PDI, PCLK and PSEL must be
microcontroller outputs. One I/O pin can
be saved if PDI and PDO are connected
together and a bi-directional pin is used at
the microcontroller.
The microcontroller pins connected to PDI,
PDO and PCLK can be used for other
purposes when the configuration interface
is not used. PDI, PDO and PCLK are high
impedance inputs as long as PSEL is not
activated (active low).
PSEL has an internal pull-up resistor and
should be left open (tri-stated by the
microcontroller) or set to a high level
during power down mode in order to
prevent a trickle current flowing in the pull-
up.
Signal interface
A bi-directional pin is usually used for data
(DIO) to be transmitted and data received.
DCLK providing the data timing should be
connected to a microcontroller input.
As an option, the data output in receive
mode can be made available on a
separate pin. See section 9.2 on page for
25 further details.
PLL lock signal
Optionally, one microcontroller pin can be
used to monitor the LOCK signal. This
signal is at low logic level when the PLL is
in lock. It can also be used for carrier
sense and to monitor other internal test
signals.
PDI
PCLK
PSEL
DIO
LOCK
Micro-
controller
DCLK (Optional)
PDO (Optional)
PDI
PCLK
PSEL
DIO
LOCK
Micro-
controller
DCLK (Optional)
PDO (Optional)
Figure 6. Microcontroller interface
CC1020
SWRS046E Page 23 of 89
9.1. 4-wire Serial Configuration Interface
CC1020
is configured via a simple 4-wire
SPI-compatible interface (PDI, PDO,
PCLK and PSEL) where
CC1020
is the
slave. There are 8-bit configuration
registers, each addressed by a 7-bit
address. A Read/Write bit initiates a read
or write operation. A full configuration of
CC1020
requires sending 33 data frames of
16 bits each (7 address bits, R/W bit and 8
data bits). The time needed for a full
configuration depends on the PCLK
frequency. With a PCLK frequency of 10
MHz the full configuration is done in less
than 53 µs. Setting the device in power
down mode requires sending one frame
only and will in this case take less than 2
µs. All registers are also readable.
During each write-cycle, 16 bits are sent
on the PDI-line. The seven most
significant bits of each data frame (A6:0)
are the address-bits. A6 is the MSB (Most
Significant Bit) of the address and is sent
as the first bit. The next bit is the R/W bit
(high for write, low for read). The 8 data-
bits are then transferred (D7:0). During
address and data transfer the PSEL
(Program SELect) must be kept low. See
Figure 7.
The timing for the programming is also
shown in Figure 7 with reference to Table
14. The clocking of the data on PDI is
done on the positive edge of PCLK. Data
should be set up on the negative edge of
PCLK by the microcontroller. When the
last bit, D0, of the 8 data-bits has been
loaded, the data word is loaded into the
internal configuration register.
The configuration data will be retained
during a programmed power down mode,
but not when the power supply is turned
off. The registers can be programmed in
any order.
The configuration registers can also be
read by the microcontroller via the same
configuration interface. The seven address
bits are sent first, then the R/W bit set low
to initiate the data read-back.
CC1020
then
returns the data from the addressed
register. PDO is used as the data output
and must be configured as an input by the
microcontroller. The PDO is set at the
negative edge of PCLK and should be
sampled at the positive edge. The read
operation is illustrated in Figure 8.
PSEL must be set high between each
read/write operation.
PCLK
PDI
PSEL
Address Write mode
6543210 7 6 5 4 3 2 1 0
Data byte
THD
TSS
TCL,min TCH,min
THS
W
TSD
PDO
Figure 7. Configuration registers write operation
CC1020
SWRS046E Page 24 of 89
PCLK
PDI
PSEL
A
ddress
Read mode
6
5
4
3 2 1 0
T
SS
T
CL,min T
CH,min
T
HS
R
PDO
7 6 5 4 3 2
1
0
Data byte
T
SH
Figure 8. Configuration registers read operation
Parameter Symbol
Min Max Unit Conditions
PCLK, clock
frequency
FPCLK
10 MHz
PCLK low
pulse
duration
TCL,min 50 ns The minimum time PCLK must be low.
PCLK high
pulse
duration
TCH,min 50 ns The minimum time PCLK must be high.
PSEL setup
time
TSS
25 ns The minimum time PSEL must be low before
positive edge of PCLK.
PSEL hold
time
THS 25 ns The minimum time PSEL must be held low after
the negative edge of PCLK.
PSEL high
time
TSH 50 ns The minimum time PSEL must be high.
PDI setup
time
TSD
25 ns The minimum time data on PDI must be ready
before the positive edge of PCLK.
PDI hold time
THD 25 ns The minimum time data must be held at PDI, after
the positive edge of PCLK.
Rise time Trise 100 ns The maximum rise time for PCLK and PSEL
Fall time Tfall 100 ns The maximum fall time for PCLK and PSEL
Note: The setup and hold times refer to 50% of VDD. The rise and fall times refer to 10% /
90% of VDD. The maximum load that this table is valid for is 20 pF.
Table 14. Serial interface, timing specification
CC1020
SWRS046E Page 25 of 89
9.2. Signal Interface
The
CC1020
can be used with NRZ (Non-
Return-to-Zero) data or Manchester (also
known as bi-phase-level) encoded data.
CC1020
can also synchronize the data from
the demodulator and provide the data
clock at DCLK. The data format is
controlled by the DATA_FORMAT[1:0] bits
in the MODEM register.
CC1020
can be configured for three
different data formats:
Synchronous NRZ mode
In transmit mode
CC1020
provides the data
clock at DCLK and DIO is used as data
input. Data is clocked into
CC1020
at the
rising edge of DCLK. The data is
modulated at RF without encoding.
In receive mode
CC1020
performs the
synchronization and provides received
data clock at DCLK and data at DIO. The
data should be clocked into the interfacing
circuit at the rising edge of DCLK. See
Figure 9.
Synchronous Manchester encoded
mode
In transmit mode
CC1020
provides the data
clock at DCLK and DIO is used as data
input. Data is clocked into
CC1020
at the
rising edge of DCLK and should be in NRZ
format. The data is modulated at RF with
Manchester code. The encoding is done
by
CC1020
. In this mode the effective bit
rate is half the baud rate due to the
coding. As an example, 4.8 kBaud
Manchester encoded data corresponds to
2.4 kbps.
In receive mode
CC1020
performs the
synchronization and provides received
data clock at DCLK and data at DIO.
CC1020
performs the decoding and NRZ
data is presented at DIO. The data should
be clocked into the interfacing circuit at the
rising edge of DCLK. See Figure 10.
In synchronous NRZ or Manchester mode
the DCLK signal runs continuously both in
RX and TX unless the DCLK signal is
gated with the carrier sense signal or the
PLL lock signal. Refer to section 21 and
section 21.2 for more details.
If SEP_DI_DO = 0 in the INTERFACE
register, the DIO pin is the data output in
receive mode and data input in transmit
mode.
As an option, the data output can be made
available at a separate pin. This is done
by setting SEP_DI_DO = 1 in the
INTERFACE register. Then, the LOCK pin
will be used as data output in synchronous
mode, overriding other use of the LOCK
pin.
Transparent Asynchronous UART
mode
In transmit mode DIO is used as data
input. The data is modulated at RF without
synchronization or encoding.
In receive mode the raw data signal from
the demodulator is sent to the output
(DIO). No synchronization or decoding of
the signal is done in
CC1020
and should be
done by the interfacing circuit.
If SEP_DI_DO = 0 in the INTERFACE
register, the DIO pin is the data output in
receive mode and data input in transmit
mode. The DCLK pin is not active and can
be set to a high or low level by
DATA_FORMAT[0].
If SEP_DI_DO = 1 in the INTERFACE
register, the DCLK pin is the data output in
receive mode and the DIO pin is the data
input in transmit mode. In TX mode the
DCLK pin is not active and can be set to a
high or low level by DATA_FORMAT[0].
See Figure 11.
Manchester encoding and decoding
In the Synchronous Manchester encoded
mode
CC1020
uses Manchester coding
when modulating the data. The
CC1020
also performs the data decoding and
synchronization. The Manchester code is
based on transitions; a “0” is encoded as a
low-to-high transition, a “1” is encoded as
a high-to-low transition. See Figure 12.
The Manchester code ensures that the
signal has a constant DC component,
which is necessary in some FSK
demodulators. Using this mode also
ensures compatibility with CC400/CC900
designs.
CC1020
SWRS046E Page 26 of 89
Clock provided by CC1020
FSK modulating signal (NRZ),
internal in CC1020
Data provided by microcontroller
Tran smitter side:
Clock provided by CC1020
Demodulated signal (NRZ),
internal in CC1020
Data pr ovide d by CC1020
DCLK
DIO
“RF”
“RF”
DCLK
DIO
Receiver side:
Clock provided by CC1020
FSK modulating signal (NRZ),
internal in CC1020
Data provided by microcontroller
Tran smitter side:
Clock provided by CC1020
Demodulated signal (NRZ),
internal in CC1020
Data pr ovide d by CC1020
DCLK
DIO
“RF”
“RF”
DCLK
DIO
Receiver side:
Figure 9. Synchronous NRZ mode (SEP_DI_DO = 0)
Clock provided by CC1020
FSK modulating signal (Manchester
encoded), internal in CC1020
Data pr ovided by microcontroller
Tran smitter sid e:
Clock provided by CC1020
Demo dulated signal (Manchester
encoded), internal in CC1020
Data pr ovided by CC1020
DCLK
DIO
“RF”
“RF”
DCLK
DIO
Receiver side :
Clock provided by CC1020
FSK modulating signal (Manchester
encoded), internal in CC1020
Data pr ovided by microcontroller
Tran smitter sid e:
Clock provided by CC1020
Demo dulated signal (Manchester
encoded), internal in CC1020
Data pr ovided by CC1020
DCLK
DIO
“RF”
“RF”
DCLK
DIO
Receiver side :
Figure 10. Synchronous Manchester encoded mode (SEP_DI_DO = 0)
CC1020
SWRS046E Page 27 of 89
DCLK is not used in transmit mode, and is
used as data output in receive mode. It can be
set to default high or low in transmit mode.
FSK modula tin g si gna l,
internal in CC1020
Data provided by UART (TXD)
Transmitter side:
DCLK is used as data output
provided by CC1020.
Connect to UART (RXD)
Demodulated signal (NRZ),
internal in CC1020
DIO is not used in receive mode. Used only
as data input in transmit mode
DCLK
DIO
“RF”
“RF”
DCLK
DIO
Receiver side:
DCLK is not used in transmit mode, and is
used as data output in receive mode. It can be
set to default high or low in transmit mode.
FSK modula tin g si gna l,
internal in CC1020
Data provided by UART (TXD)
Transmitter side:
DCLK is used as data output
provided by CC1020.
Connect to UART (RXD)
Demodulated signal (NRZ),
internal in CC1020
DIO is not used in receive mode. Used only
as data input in transmit mode
DCLK
DIO
“RF”
“RF”
DCLK
DIO
Receiver side:
Figure 11. Transparent Asynchronous UART mode (SEP_DI_DO = 1)
Time
1 0 1 1 0 0 0 1 1 0 1
Tx
data
Time
1 0 1 1 0 0 0 1 1 0 1
Tx
data
Figure 12. Manchester encoding
10. Data Rate Programming
The data rate (baud rate) is programmable
and depends on the crystal frequency and
the programming of the CLOCK
(CLOCK_A and CLOCK_B) registers.
The baud rate (B.R) is given by
21)1_(8
.. DIVDIVDIVREF
f
RB xosc
⋅⋅+⋅
=
where DIV1 and DIV2 are given by the
value of MCLK_DIV1 and MCLK_DIV2.
Table 17 shows some possible data rates
as a function of crystal frequency in
synchronous mode. In asynchronous
transparent UART mode any data rate up
to 153.6 kBaud can be used.
MCLK_DIV2[1:0] DIV2
00 1
01 2
10 4
11 8
Table 15. DIV2 for different settings of
MCLK_DIV2
MCLK_DIV1[2:0] DIV1
000 2.5
001 3
010 4
011 7.5
100 12.5
101 40
110 48
111 64
Table 16. DIV1 for different settings of
MCLK_DIV1
CC1020
SWRS046E Page 28 of 89
Crystal frequency [MHz] Data rate
[kBaud] 4.9152 7.3728 9.8304 12.288 14.7456 17.2032 19.6608
0.45 X X
0.5 X
0.6 X X X X X X X
0.9 X X
1 X
1.2 X X X X X X X
1.8 X X
2 X
2.4 X X X X X X X
3.6 X X
4 X
4.096 X X
4.8 X X X X X X X
7.2 X X
8 X
8.192 X X
9.6 X X X X X X X
14.4 X X
16 X
16.384 X X
19.2 X X X X X X X
28.8 X X
32 X
32.768 X X
38.4 X X X X X X X
57.6 X X
64 X
65.536 X
76.8 X X X X X X X
115.2 X X
128 X
153.6 X X X X X
Table 17. Some possible data rates versus crystal frequency
11. Frequency Programming
Programming the frequency word in the
configuration registers sets the operation
frequency. There are two frequency words
registers, termed FREQ_A and FREQ_B,
which can be programmed to two different
frequencies. One of the frequency words
can be used for RX (local oscillator
frequency) and the other for TX
(transmitting carrier frequency) in order to
be able to switch very fast between RX
mode and TX mode. They can also be
used for RX (or TX) at two different
channels. The F_REG bit in the MAIN
register selects frequency word A or B.
The frequency word is located in
FREQ_2A:FREQ_1A:FREQ_0A and
FREQ_2B:FREQ_1B:FREQ_0B for the
FREQ_A and FREQ_B word respectively.
The LSB of the FREQ_0 registers are
used to enable dithering, section 11.1.
The PLL output frequency is given by:
⎟
⎠
⎞
⎜
⎝
⎛⋅+
+⋅= 32768
5.0
4
3DITHERFREQ
ff refc
in the frequency band 402 – 470 MHz, and
⎟
⎠
⎞
⎜
⎝
⎛⋅+
+⋅= 16384
5.0
2
3DITHERFREQ
ff refc
in the frequency band 804 – 960 MHz.
The BANDSELECT bit in the ANALOG
register controls the frequency band used.
BANDSELECT = 0 gives 402 – 470 MHz,
and BANDSELECT = 1 gives 804 – 960
MHz.
The reference frequency is the crystal
oscillator clock frequency divided by
REF_DIV (3 bits in the CLOCK_A or
CC1020
SWRS046E Page 29 of 89
CLOCK_B register), a number between 1
and 7:
1_ +
=DIVREF
f
fxosc
ref
FSK frequency deviation is programmed in
the DEVIATION register. The deviation
programming is divided into a mantissa
(TXDEV_M[3:0]) and an exponent
(TXDEV_X[2:0]).
Generally REF_DIV should be as low as
possible but the following requirements
must be met
[]
MHz
f
fc
ref 256
8304.9 >≥
in the frequency band 402 – 470 MHz, and
[]
MHz
f
fc
ref 512
8304.9 >≥
in the frequency band 804 – 960 MHz.
The PLL output frequency equations
above give the carrier frequency, fc , in
transmit mode (centre frequency). The two
FSK modulation frequencies are given by:
f0 = fc − fdev
f1 = fc + fdev
where fdev is set by the DEVIATION
register:
)16_(
2_ −
⋅⋅= XTXDEV
refdev MTXDEVff
in the frequency band 402 – 470 MHz and
)15_(
2_ −
⋅⋅= XTXDEV
refdev MTXDEVff
in the frequency band 804 – 960 MHz.
OOK (On-Off Keying) is used if
TXDEV_M[3:0] = 0000.
The TX_SHAPING bit in the DEVIATION
register controls Gaussian shaping of the
modulation signal.
In receive mode the frequency must be
programmed to be the LO frequency. Low
side LO injection is used, hence:
fLO = fc − fIF
where fIF is the IF frequency (ideally 307.2
kHz).
11.1. Dithering
Spurious signals will occur at certain
frequencies depending on the division
ratios in the PLL. To reduce the strength of
these spurs, a common technique is to
use a dithering signal in the control of the
frequency dividers. Dithering is activated
by setting the DITHER bit in the FREQ_0
registers. It is recommended to use the
dithering in order to achieve the best
possible performance.
CC1020
SWRS046E Page 30 of 89
12. Receiver
12.1. IF Frequency
The IF frequency is derived from the
crystal frequency as
[]
)10:2_(8 +⋅
=DIVADC
f
fxoscx
IF
where ADC_DIV[2:0] is set in the MODEM
register.
The analog filter succeeding the mixer is
used for wideband and anti-alias filtering
which is important for the blocking
performance at 1 MHz and larger offsets.
This filter is fixed and centered on the
nominal IF frequency of 307.2 kHz. The
bandwidth of the analog filter is about 160
kHz.
Using crystal frequencies which gives an
IF frequency within 300 – 320 kHz means
that the analog filter can be used
(assuming low frequency deviations and
low data rates).
Large offsets, however, from the nominal
IF frequency will give an un-symmetric
filtering (variation in group delay and
different attenuation) of the signal,
resulting in decreased sensitivity and
selectivity. See Application Note AN022
Crystal Frequency Selection for more
details.
For IF frequencies other than 300 – 320
kHz and for high frequency deviation and
high data rates (typically ≥ 76.8 kBaud) the
analog filter must be bypassed by setting
FILTER_BYPASS = 1 in the FILTER
register. In this case the blocking
performance at 1 MHz and larger offsets
will be degraded.
The IF frequency is always the ADC clock
frequency divided by 4. The ADC clock
frequency should therefore be as close to
1.2288 MHz as possible.
12.2. Receiver Channel Filter Bandwidth
In order to meet different channel spacing
requirements, the receiver channel filter
bandwidth is programmable. It can be
programmed from 9.6 to 307.2 kHz.
The minimum receiver channel filter
bandwidth depends on baud rate,
frequency separation and crystal
tolerance.
The signal bandwidth must be smaller
than the available receiver channel filter
bandwidth. The signal bandwidth (SBW)
can be approximated by (Carson’s rule):
SBW = 2 · fm + 2 · frequency deviation
where fm is the modulating signal. In
Manchester mode the maximum
modulating signal occurs when
transmitting a continuous sequence of 0’s
(or 1’s). In NRZ mode the maximum
modulating signal occurs when
transmitting a 0-1-0 sequence. In both
Manchester and NRZ mode 2·fm is then
equal to the programmed baud rate. The
equation for SBW can then be rewritten as
SBW = Baud rate + frequency separation
Furthermore, the frequency offset of the
transmitter and receiver must also be
considered. Assuming equal frequency
error in the transmitter and receiver (same
type of crystal) the total frequency error is:
f_error = ±2 · XTAL_ppm · f_RF
where XTAL_ppm is the total accuracy of
the crystal including initial tolerance,
temperature drift, loading and ageing.
F_RF is the RF operating frequency.
The minimum receiver channel filter
bandwidth (ChBW) can then be estimated
as
ChBW > SBW + 2 · f_error
The DEC_DIV[4:0] bits in the FILTER
register control the receiver channel filter
CC1020
SWRS046E Page 31 of 89
bandwidth. The 6 dB bandwidth is given
by:
ChBW = 307.2 / (DEC_DIV + 1) [kHz]
where the IF frequency is set to 307.2
kHz.
In SmartRF® Studio the user specifies the
channel spacing and the channel filter
bandwidth is set according to Table 18.
For narrowband systems with channel
spacings of 12.5 and 25 kHz the channel
filter bandwidth is 12.288 kHz and 19.2
kHz respectively to comply with ARIB
STD-T67 and EN 300 220.
For wideband systems (channel spacing of
50 kHz and above) it is possible to use
different channel filter bandwidths than
given in Table 18.
There is a trade-off between selectivity as
well as sensitivity and accepted frequency
tolerance. In applications where larger
frequency drift is expected, the filter
bandwidth can be increased, but with
reduced adjacent channel rejection (ACR)
and sensitivity.
Channel
spacing
[kHz]
Filter
bandwidth
[kHz]
FILTER.DEC_DIV
[4:0]
[decimal(binary)]
12.5 12.288 24 (11000b)
25 19.2 15 (01111b)
50 25.6 11 (01011b)
100 51.2 5 (00101b)
150 102.4 2 (00010b)
200 153.6 1 (00001b)
500 307.2 0 (00000b)
Table 18. Channel filter bandwidths used
for the channel spacings defined in
SmartRF® Studio
12.3. Demodulator, Bit Synchronizer and Data Decision
The block diagram for the demodulator,
data slicer and bit synchronizer is shown
in Figure 13. The built-in bit synchronizer
synchronizes the internal clock to the
incoming data and performs data
decoding. The data decision is done using
over-sampling and digital filtering of the
incoming signal. This improves the
reliability of the data transmission. Using
the synchronous modes simplifies the
data-decoding task substantially.
The recommended preamble is a
‘010101…’ bit pattern. The same bit
pattern should also be used in Manchester
mode, giving a ‘011001100110…‘chip’
pattern. This is necessary for the bit
synchronizer to synchronize to the coding
correctly.
The data slicer does the bit decision.
Ideally the two received FSK frequencies
are placed symmetrically around the IF
frequency. However, if there is some
frequency error between the transmitter
and the receiver, the bit decision level
should be adjusted accordingly. In
CC1020
this is done automatically by measuring
the two frequencies and use the average
value as the decision level.
The digital data slicer in
CC1020
uses an
average value of the minimum and
maximum frequency deviation detected as
the comparison level. The RXDEV_X[1:0]
and RXDEV_M[3:0] in the
AFC_CONTROL register are used to set
the expected deviation of the incoming
signal. Once a shift in the received
frequency larger than the expected
deviation is detected, a bit transition is
recorded and the average value to be
used by the data slicer is calculated.
The minimum number of transitions
required to calculate a slicing level is 3.
That is, a 010 bit pattern (NRZ).
The actual number of bits used for the
averaging can be increased for better data
decision accuracy. This is controlled by
the SETTLING[1:0] bits in the
AFC_CONTROL register. If RX data is
present in the channel when the RX chain
is turned on, then the data slicing estimate
will usually give correct results after 3 bit
transitions. The data slicing accuracy will
increase after this, depending on the
SETTLING[1:0] bits. If the start of
transmission occurs after the RX chain
has turned on, the minimum number of bit
transitions (or preamble bits) before
correct data slicing will depend on the
SETTLING[1:0] bits.
CC1020
SWRS046E Page 32 of 89
The automatic data slicer average value
function can be disabled by setting
SETTLING[1:0] = 00. In this case a
symmetrical signal around the IF
frequency is assumed.
The internally calculated average FSK
frequency value gives a measure for the
frequency offset of the receiver compared
to the transmitter. This information can
also be used for an automatic frequency
control (AFC) as described in section
12.13.
Digital filtering
Average
filter
Data
filter
Decimator
Frequency
detector
Data slicer
comparator
Bit
synchronizer
and data
decoder
Figure 13. Demodulator block diagram
12.4. Receiver Sensitivity versus Data Rate and Frequency Separation
The receiver sensitivity depends on the
channel filter bandwidth, data rate, data
format, FSK frequency separation and the
RF frequency. Typical figures for the
receiver sensitivity (BER = 10-3) are shown
in Table 19 and Table 20 for FSK. For best
performance, the frequency deviation
should be at least half the baud rate in
FSK mode.
The sensitivity is measured using the
matching network shown in the application
circuit in Figure 3, which includes an
external T/R switch.
Refer to Application Note AN029
CC1020/1021 AFC for plots of sensitivity
versus frequency offset.
Sensitivity [dBm]
Data rate
[kBaud]
Channel spacing
[kHz]
Deviation
[kHz]
Filter BW
[kHz] NRZ
mode
Manchester
mode
UART
mode
2.4 optimized sensitivity 12.5 ± 2.025 9.6 -115 -118 -115
2.4 optimized selectivity 12.5 ± 2.025 12.288 -112 -114 -112
4.8 25
± 2.475 19.2 -112 -112 -112
9.6 50
± 4.95 25.6 -110 -111 -110
19.2 100
± 9.9 51.2 -107 -108 -107
38.4 150
± 19.8 102.4 -104 -104 -104
76.8 200
± 36.0 153.6 -101 -101 -101
153.6 500
± 72.0 307.2 -96 -97 -96
Table 19. Typical receiver sensitivity as a function of data rate at 433 MHz, FSK
modulation, BER = 10-3, pseudo-random data (PN9 sequence)
Note: “Optimized selectivity” in Table 19 is relevant for systems targeting compliance with
ARIB STD-T67, 12.5 kHz channel spacing.
CC1020
SWRS046E Page 33 of 89
Sensitivity [dBm]
Data rate
[kBaud]
Channel spacing
[kHz]
Deviation
[kHz]
Filter BW
[kHz] NRZ
mode
Manchester
mode
UART
mode
2.4 12.5
± 2.025 12.288 -112 -116 -112
4.8 25
± 2.475 19.2 -111 -112 -111
9.6 50
± 4.95 25.6 -109 -110 -109
19.2 100
± 9.9 51.2 -107 -107 -107
38.4 150
± 19.8 102.4 -103 -103 -103
76.8 200
± 36.0 153.6 -99 -100 -99
153.6 500
± 72.0 307.2 -94 -94 -94
Table 20. Typical receiver sensitivity as a function of data rate at 868 MHz, FSK
modulation, BER = 10-3, pseudo-random data (PN9 sequence)
12.5. RSSI
CC1020
has a built-in RSSI (Received
Signal Strength Indicator) giving a digital
value that can be read form the RSSI
register. The RSSI reading must be offset
and adjusted for VGA gain setting
(VGA_SETTING[4:0] in the VGA3
register).
The digital RSSI value is ranging from 0 to
106 (7 bits).
The RSSI reading is a logarithmic
measure of the average voltage amplitude
after the digital filter in the digital part of
the IF chain:
RSSI = 4 log2(signal amplitude)
The relative power is then given by RSSI x
1.5 dB in a logarithmic scale.
The number of samples used to calculate
the average signal amplitude is controlled
by AGC_AVG[1:0] in the VGA2 register.
The RSSI update rate is given by:
[]
10:1_ _
2+
=AVGAGC clockfilter
RSSI
f
f
where AGC_AVG[1:0] is set in the VGA2
register and ChBWf clockfilter ⋅= 2
_.
Maximum VGA gain is programmed by the
VGA_SETTING[4:0] bits. The VGA gain is
programmed in approximately 3 dB/LSB.
The RSSI measurement can be referred to
the power (absolute value) at the RF_IN
pin by using the following equation:
P = 1.5·RSSI – 3·VGA_SETTING –
RSSI_Offset [dBm]
The RSSI_Offset depends on the channel
filter bandwidth used due to different VGA
settings. Figure 14 and Figure 15 show
typical plots of RSSI reading as a function
of input power for different channel
spacings. See section 12.5 on page 33 for
a list of channel filter bandwidths
corresponding to the various channel
spacings. Refer to Application Note AN030
CC1020/1021 RSSI for further details.
The following method can be used to
calculate the power P in dBm from the
RSSI readout values in Figure 14 and
Figure 15:
P = 1.5·[RSSI – RSSI_ref] + P_ref
where P is the output power in dBm for the
current RSSI readout value. RSSI_ref is
the RSSI readout value taken from
Figure 14 or Figure 15 for an input power
level of P_ref. Note that the RSSI reading
in decimal value changes for different
channel filter bandwidths.
The analog filter has a finite dynamic
range and is the reason why the RSSI
reading is saturated at lower channel
spacings. Higher channel spacing is
typically used for high frequency deviation
and data rates. The analog filter bandwidth
is about 160 kHz and is bypassed for high
frequency deviation and data rates and is
the reason why the RSSI reading is not
saturated for 200 kHz and 500 kHz
channel spacing in Figure 14 and Figure
15.
CC1020
SWRS046E Page 34 of 89
0
10
20
30
40
50
60
70
80
-125 -115 -105 -95 -85 -75 -65 -55 -45 -35 -25
Input power level [dBm]
RSSI readout value [decimal]
12.5 kHz 25 kHz 50 kHz 100 kHz 150 kHz 200 kHz 500 kHz
Figure 14. Typical RSSI value vs. input power for some typical channel spacings, 433 MHz
0
10
20
30
40
50
60
70
80
-125 -115 -105 -95 -85 -75 -65 -55 -45 -35 -25
Input power level [dBm]
RSSI readout value [decimal]
12.5 kHz 25 kHz 50 kHz 100 kHz 150 kHz 200 kHz 500 kHz
Figure 15. Typical RSSI value vs. input power for some typical channel spacings, 868 MHz
CC1020
SWRS046E Page 35 of 89
12.6. Image Rejection Calibration
For perfect image rejection, the phase and
gain of the “I” and “Q” parts of the analog
RX chain must be perfectly matched. To
improve the image rejection, the “I” and
“Q” phase and gain difference can be fine-
tuned by adjusting the PHASE_COMP and
GAIN_COMP registers. This allows
compensation for process variations and
other nonidealities. The calibration is done
by injecting a signal at the image
frequency, and adjusting the phase and
gain difference for minimum RSSI value.
During image rejection calibration, an
unmodulated carrier should be applied at
the image frequency (614.4 kHz below the
desired channel). No signal should be
present in the desired channel. The signal
level should be 50 – 60 dB above the
sensitivity in the desired channel, but the
optimum level will vary from application to
application. Too large input level gives
poor results due to limited linearity in the
analog IF chain, while too low input level
gives poor results due to the receiver
noise floor.
For best RSSI accuracy, use
AGC_AVG[1:0] = 11 during image
rejection calibration (RSSI value is
averaged over 16 filter output samples).
The RSSI register update rate then equals
the receiver channel bandwidth (set in
FILTER register) divided by 8, as the filter
output rate is twice the receiver channel
bandwidth. This gives the minimum
waiting time between RSSI register reads
(0.5 ms is used below). TI recommends
the following image calibration procedure:
1. Define 3 variables: XP = 0, XG = 0 and DX = 64.
Go to step 3.
2. Set DX = DX/2.
3. Write XG to GAIN_COMP register.
4. If XP+2·DX < 127 then
write XP+2·DX to PHASE_COMP register
else
write 127 to PHASE_COMP register.
5. Wait at least 3 ms. Measure signal strength Y4
as filtered average of 8 reads from RSSI register
with 0.5 ms of delay between each RSSI read.
6. Write XP+DX to PHASE_COMP register.
7. Wait at least 3 ms. Measure signal strength Y3
as filtered average of 8 reads from RSSI register
with 0.5 ms of delay between each RSSI read.
8. Write XP to PHASE_COMP register.
9. Wait at least 3 ms. Measure signal strength Y2
as filtered average of 8 reads from RSSI register
with 0.5 ms of delay between each RSSI read.
10. Write XP-DX to PHASE_COMP register.
11. Wait at least 3 ms. Measure signal strength Y1
as filtered average of 8 reads from RSSI register
with 0.5 ms of delay between each RSSI read.
12. Write XP-2·DX to PHASE_COMP register.
13. Wait at least 3 ms. Measure signal strength Y0
as filtered average of 8 reads from RSSI register
with 0.5 ms of delay between each RSSI read.
14. Set AP = 2·(Y0-Y2+Y4) – (Y1+Y3).
15. If AP > 0 then
set DP = ROUND( 7·DX·(2·(Y0-Y4)+Y1-
Y3) / (10·AP) )
else
if Y0+Y1 > Y3+Y4 then
set DP = DX
else
set DP = -DX.
16. If DP > DX then
set DP = DX
else
if DP < -DX then set DP = -DX.
17. Set XP = XP+DP.
18. Write XP to PHASE_COMP register.
19. If XG+2·DX < 127 then
write XG+2·DX to GAIN_COMP register
else
write 127 to GAIN_COMP register.
20. Wait at least 3 ms. Measure signal strength Y4
as filtered average of 8 reads from RSSI register
with 0.5 ms of delay between each RSSI read.
21. Write XG+DX to GAIN_COMP register.
22. Wait at least 3 ms. Measure signal strength Y3
as filtered average of 8 reads from RSSI register
with 0.5 ms of delay between each RSSI read.
23. Write XG to GAIN_COMP register.
24. Wait at least 3 ms. Measure signal strength Y2
as filtered average of 8 reads from RSSI register
with 0.5 ms of delay between each RSSI read.
25. Write XG-DX to GAIN_COMP register.
26. Wait at least 3 ms. Measure signal strength Y1
as filtered average of 8 reads from RSSI register
with 0.5 ms of delay between each RSSI read.
27. Write XG-2·DX to GAIN_COMP register.
28. Wait at least 3 ms. Measure signal strength Y0
as filtered average of 8 reads from RSSI register
with 0.5 ms of delay between each RSSI read.
29. Set AG = 2·(Y0-Y2+Y4) – (Y1+Y3).
30. If AG > 0 then
set DG = ROUND( 7·DX·(2·(Y0-Y4)+Y1-
Y3) / (10·AG) )
else
if Y0+Y1 > Y3+Y4 then
set DG = DX
else
set DG = -DX.
31. If DG > DX then
set DG = DX
else
if DG < -DX then set DG = -DX.
32. Set XG = XG+DG.
33. If DX > 1 then go to step 2.
34. Write XP to PHASE_COMP register and
XG to GAIN_COMP register.
If repeated calibration gives varying
results, try to change the input level or
increase the number of RSSI reads N. A
good starting point is N=8. As accuracy is
more important in the last fine-calibration
steps, it can be worthwhile to increase N
for each loop iteration.
CC1020
SWRS046E Page 36 of 89
For high frequency deviation and high data
rates (typically ≥ 76.8 kBaud) the analog
filter succeeding the mixer must be
bypassed by setting FILTER_BYPASS = 1
in the FILTER register. In this case the
image rejection is degraded.
The image rejection is reduced for low
supply voltages (typically <2.5 V) when
operating in the 402 – 470 MHz frequency
range.
12.7. Blocking and Selectivity
Figure 16 shows the blocking/selectivity at
433 MHz, 12.5 kHz channel spacing.
Figure 17 shows the blocking/selectivity at
868 MHz, 25 kHz channel spacing. The
blocking rejection is the ratio between a
modulated blocker (interferer) and a
wanted signal 3 dB above the sensitivity
limit.
-20.0
-10.0
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
-900
-700
-500
-300
-100
-50
0
50
100
300
500
700
900
Blocker frequency offset [kHz]
Blocker rejection [dB]
Figure 16. Typical blocker rejection. Carrier frequency set to 434.3072 MHz (12.5 kHz
channel spacing, 12.288 kHz receiver channel filter bandwidth)
CC1020
SWRS046E Page 37 of 89
-20.0
-10.0
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
-950
-750
-550
-350
-200
-100
0
100
200
350
550
750
950
Blocker frequency offset [kHz]
Blocker rejection [dB]
Figure 17. Typical blocker rejection. Carrier frequency set to 868.3072 MHz (25 kHz
channel spacing, 19.2 kHz receiver channel filter bandwidth)
12.8. Linear IF Chain and AGC Settings
CC1020
is based on a linear IF chain
where the signal amplification is done in
an analog VGA (Variable Gain Amplifier).
The gain is controlled by the digital part of
the IF chain after the ADC (Analog to
Digital Converter). The AGC (Automatic
Gain Control) loop ensures that the ADC
operates inside its dynamic range by using
an analog/digital feedback loop.
The maximum VGA gain is programmed
by the VGA_SETTING[4:0] in the VGA3
register. The VGA gain is programmed in
approximately 3 dB/LSB. The VGA gain
should be set so that the amplified thermal
noise from the front-end balance the
quantization noise from the ADC.
Therefore the optimum maximum VGA
gain setting will depend on the channel
filter bandwidth.
A digital RSSI is used to measure the
signal strength after the ADC. The
CS_LEVEL[4:0] in the VGA4 register is
used to set the nominal operating point of
the gain control (and also the carrier sense
level). Further explanation can be found in
Figure 18.
The VGA gain will be changed according
to a threshold set by the VGA_DOWN[2:0]
in the VGA3 register and the VGA_UP[2:0]
in the VGA4 register. Together, these two
values specify the signal strength limits
used by the AGC to adjust the VGA gain.
To avoid unnecessary tripping of the VGA,
an extra hysteresis and filtering of the
RSSI samples can be added. The
AGC_HYSTERESIS bit in the VGA2
register enables this.
The time dynamics of the loop can be
altered by the VGA_BLANKING bit in the
ANALOG register, and VGA_FREEZE[1:0]
and VGA_WAIT[2:0] bits in the VGA1
register.
When VGA_BLANKING is activated, the
VGA recovery time from DC offset spikes
after a gain step is reduced.
VGA_FREEZE determines the time to hold
bit synchronization, VGA and RSSI levels
after one of these events occur:
• RX power-up
• The PLL has been out of lock
• Frequency register setting is switched
between A and B
This feature is useful to avoid AGC
operation during start-up transients and to
ensure minimum dwell time using
frequency hopping. This means that bit
synchronization can be maintained from
hop to hop.
CC1020
SWRS046E Page 38 of 89
VGA_WAIT determines the time to hold
the present bit synchronization and RSSI
levels after changing VGA gain. This
feature is useful to avoid AGC operation
during the settling of transients after a
VGA gain change. Some transients are
expected due to DC offsets in the VGA.
At the sensitivity limit, the VGA gain is set
by VGA_SETTING. In order to optimize
selectivity, this gain should not be set
higher than necessary. The SmartRF®
Studio software gives the settings for
VGA1 – VGA4 registers. For reference,
the following method can be used to find
the AGC settings:
1. Disable AGC and use maximum LNA2 gain by
writing BFh to the VGA2 register. Set minimum
VGA gain by writing to the VGA3 register with
VGA_SETTING = 0.
2. Apply no RF input signal, and measure ADC noise
floor by reading the RSSI register.
3. Apply no RF input signal, and write VGA3 register
with increasing VGA_SETTING value until the
RSSI register value is approximately 4 larger than
the value read in step 2. This places the front-end
noise floor around 6 dB above the ADC noise floor.
4. Apply an RF signal with strength equal the desired
carrier sense threshold. The RF signal should
preferably be modulated with correct Baud rate and
deviation. Read the RSSI register value, subtract 8,
and write to CS_LEVEL in the VGA4 register. Vary
the RF signal level slightly and check that carrier
sense indication (bit 3 in STATUS register)
switches at the desired input level.
5. If desired, adjust the VGA_UP and VGA_DOWN
settings according to the explanation in Figure 18.
6. Enable AGC and select LNA2 gain change level.
Write 55h to VGA2 register if the resulting
VGA_SETTING>10. Otherwise, write 45h to VGA2.
Modify AGC_AVG in the above VGA2 value if
faster carrier sense and AGC settling is desired.
RSSI Level
0
Zero level depends on front-end settings and VGA_SETTING
value.
CS_LEVEL+8
VGA_UP
VGA_DOWN+3
(signal strength, 1.5dB/step)
Carrier sense is turned on here.
AGC increases gain if below this
level (unless at maximum).
AGC decreases gain if above
this level (unless at minimum).
To set CS_LEVEL, subtract 8 from RSSI readout with RF
input signal at desired carrier sense level.
Note that the AGC works with "raw" filter output signal
strength, while the RSSI readout value is compensated for
VGA gain changes by the AGC.
The AGC keeps the signal strength in this range. Minimize
VGA_DOWN for best selectivity, but leave some margin to
avoid frequent VGA gain changes during reception.
The AGC keeps the signal strength above carrier sense level
+ VGA_UP. Minimize VGA_UP for best selectivity, but
increase if first VGA gain reduction occurs too close to the
noise floor.
Figure 18. Relationship between RSSI, carrier sense level, and AGC settings CS_LEVEL,
VGA_UP and VGA_DOWN
12.9. AGC Settling
After turning on the RX chain, the following
occurs:
A) The AGC waits 16-128 ADC_CLK
(1.2288 MHz) periods, depending on the
VGA_FREEZE setting in the VGA1
register, for settling in the analog parts.
B) The AGC waits 16-48 FILTER_CLK
periods, depending on the VGA_WAIT
setting in the VGA1 register, for settling in
the analog parts and the digital channel
filter.
C) The AGC calculates the RSSI value as
the average magnitude over the next 2-16
CC1020
SWRS046E Page 39 of 89
FILTER_CLK periods, depending on the
AGC_AVG setting in the VGA2 register.
D) If the RSSI value is higher than
CS_LEVEL+8, then the carrier sense
indicator is set (if CS_SET = 0). If the
RSSI value is too high according to the
CS_LEVEL, VGA_UP and VGA_DOWN
settings, and the VGA gain is not already
at minimum, then the VGA gain is reduced
and the AGC continues from B).
E) If the RSSI value is too low according to
the CS_LEVEL and VGA_UP settings, and
the VGA gain is not already at maximum
(given by VGA_SETTING), then the VGA
gain is increased and the AGC continues
from B).
2-3 VGA gain changes should be
expected before the AGC has settled.
Increasing AGC_AVG increases the
settling time, but may be worthwhile if
there is the time in the protocol, and for
reducing false wake-up events when
setting the carrier sense close to the noise
floor.
The AGC settling time depends on the
FILTER_CLK (= 2·ChBW). Thus, there is a
trade off between AGC settling time and
receiver sensitivity because the AGC
settling time can be reduced for data rates
lower than 76.8 kBaud by using a wider
receiver channel filter bandwidth (i.e.
larger ChBW).
12.10. Preamble Length and Sync Word
The rules for choosing a good sync word
are as follows:
1. The sync word should be significantly
different from the preamble
2. A large number of transitions is good for
the bit synchronization or clock recovery.
Equal bits reduce the number of
transitions. The recommended sync word
has at most 3 equal bits in a row.
3. Autocorrelation. The sync word should
not repeat itself, as this will increase the
likelihood for errors.
4. In general the first bit of sync should be
opposite of last bit in preamble, to achieve
one more transition.
The recommended sync words for
CC1020
are 2 bytes (0xD391), 3 bytes (0xD391DA)
or 4 bytes (0xD391DA26) and are selected
as the best compromise of the above
criteria.
Using the register settings provided by the
SmartRF® Studio software, packet error
rates (PER) less than 0.5% can be
achieved when using 24 bits of preamble
and a 16 bit sync word (0xD391). Using a
preamble longer than 24 bits will improve
the PER.
When performing the PER measurements
described above the packet format
consisted of 10 bytes of random data, 2
bytes CRC and 1 dummy byte in addition
to the sync word and preamble at the start
of each package.
For the test 1000 packets were sent 10
times. The transmitter was put in power
down between each packet. Any bit error
in the packet, either in the sync word, in
the data or in the CRC caused the packet
to be counted as a failed packet.
12.11. Carrier Sense
The carrier sense signal is based on the
RSSI value and a programmable
threshold. The carrier sense function can
be used to simplify the implementation of a
CSMA (Carrier Sense Multiple Access)
medium access protocol.
Carrier sense threshold level is
programmed by CS_LEVEL[4:0] in the
VGA4 register and VGA_SETTING[4:0] in
the VGA3 register.
VGA_SETTING[4:0] sets the maximum
gain in the VGA. This value must be set so
that the ADC works with optimum dynamic
range for a certain channel filter
bandwidth. The detected signal strength
(after the ADC) will therefore depend on
this setting.
CS_LEVEL[4:0] sets the threshold for this
specific VGA_SETTING[4:0] value. If the
VGA_SETTING[4:0] is changed, the
CC1020
SWRS046E Page 40 of 89
CS_LEVEL[4:0] must be changed
accordingly to maintain the same absolute
carrier sense threshold. See Figure 18 for
an explanation of the relationship between
RSSI, AGC and carrier sense settings.
The carrier sense signal can be read as
the CARRIER_SENSE bit in the STATUS
register.
The carrier sense signal can also be made
available at the LOCK pin by setting
LOCK_SELECT[3:0] = 0100 in the LOCK
register.
12.12. Automatic Power-up Sequencing
CC1020
has a built-in automatic power-up
sequencing state machine. By setting the
CC1020
into this mode, the receiver can be
powered-up automatically by a wake-up
signal and will then check for a carrier
signal (carrier sense). If carrier sense is
not detected, it returns to power-down
mode. A flow chart for automatic power-up
sequencing is shown in Figure 19.
The automatic power-up sequencing mode
is selected when PD_MODE[1:0] = 11 in
the MAIN register. When the automatic
power-up sequencing mode is selected,
the functionality of the MAIN register is
changed and used to control the
sequencing.
By setting SEQ_PD = 1 in the MAIN
register,
CC1020
is set in power down
mode. If SEQ_PSEL = 1 in the
SEQUENCING register the automatic
power-up sequence is initiated by a
negative transition on the PSEL pin.
If SEQ_PSEL = 0 in the SEQUENCING
register, then the automatic power-up
sequence is initiated by a negative
transition on the DIO pin (as long as
SEP_DI_DO = 1 in the INTERFACE
register).
Sequence timing is controlled through
RX_WAIT[2:0] and CS_WAIT[3:0] in the
SEQUENCING register.
VCO and PLL calibration can also be done
automatically as a part of the sequence.
This is controlled through SEQ_CAL[1:0]
in the MAIN register. Calibration can be
done every time, every 16th sequence,
every 256th sequence, or never. See the
register description for details. A
description of when to do, and how the
VCO and PLL self-calibration is done, is
given in section 15.2 on page 51.
See also Application Note AN070 CC1020
Automatic Power-Up Sequencing available
from the TI web site.
CC1020
SWRS046E Page 41 of 89
Power down
Crystal oscillator and bias off
Frequency synthesizer off
Receive chain off
Wait for PLL
lock or timeout,
127 filter clocks
Turn on crystal oscillator/bias
Frequency synthesizer off
Receive chain off
Crystal oscillator and bias on
Turn on frequency synthesizer
Receive chain off
Optional waiting time before
turning on receive chain
Programmable:
32-256 ADC clocks
Crystal oscillator and bias on
Frequency synthesizer on
Turn on receive chain
Receive mode
Crystal oscillator and bias on
Frequency synthesizer on
Receive chain on
Wait for
carrier sense or timeout
Programmable: 20-72
filter clocks
Set
SEQ_ERROR
flag in STATUS
register
Optional calibration
Programmable: each time,
once in 16, or once in 256
Receive chain off
PLL in lock
PLL timeout
Sequencing wake-up event
Carrier sense timeout
Carrier sense
(negative transition on
PSEL pin or DIO pin)
(Positive transition on SEQ_PD in MAIN register)
Sequencing power-down event
Figure 19. Automatic power-up sequencing flow chart
Notes to Figure 19:
Filter clock (FILTER_CLK):
ChBWf clockfilter ⋅
=
2
_
where ChBW is defined on page 30.
ADC clock (ADC_CLK):
[]
)10:2_(2 +⋅
=DIVADC f
fxoscx
ADC
where ADC_DIV[2:0] is set in the MODEM
register.
12.13. Automatic Frequency Control
CC1020
has a built-in feature called AFC
(Automatic Frequency Control) that can be
used to compensate for frequency drift.
The average frequency offset of the
received signal (from the nominal IF
frequency) can be read in the AFC
register. The signed (2’s-complement) 8-
bit value AFC[7:0] can be used to
compensate for frequency offset between
transmitter and receiver.
The frequency offset is given by:
∆F = AFC·Baud rate / 16
The receiver can be calibrated against the
transmitter by changing the operating
frequency according to the measured
offset. The new frequency must be
calculated and written to the FREQ
register by the microcontroller. The AFC
can be used for an FSK/GFSK signal, but
not for OOK. Application Note AN029
CC1020
SWRS046E Page 42 of 89
CC1020/1021 AFC provides the procedure
and equations necessary to implement
AFC.
The AFC feature reduces the crystal
accuracy requirement.
12.14. Digital FM
It is possible to read back the
instantaneous IF from the FM demodulator
as a frequency offset from the nominal IF
frequency. This digital value can be used
to perform a pseudo analog FM
demodulation.
The frequency offset can be read from the
GAUSS_FILTER register and is a signed
8-bit value coded as 2-complement.
The instantaneous deviation is given by:
F = GAUSS_FILTER·Baud rate / 8
The digital value should be read from the
register and sent to a DAC and filtered in
order to get an analog audio signal. The
internal register value is updated at the
MODEM_CLK rate. MODEM_CLK is
available at the LOCK pin when
LOCK_SELECT[3:0] = 1101 in the LOCK
register, and can be used to synchronize
the reading.
For audio (300 – 4000 Hz) the sampling
rate should be higher than or equal to 8
kHz (Nyquist) and is determined by the
MODEM_CLK. The MODEM_CLK, which
is the sampling rate, equals 8 times the
baud rate. That is, the minimum baud rate,
which can be programmed, is 1 kBaud.
However, the incoming data will be filtered
in the digital domain and the 3-dB cut-off
frequency is 0.6 times the programmed
Baud rate. Thus, for audio the minimum
programmed Baud rate should be
approximately 7.2 kBaud.
The GAUSS_FILTER resolution
decreases with increasing baud rate. A
accumulate and dump filter can be
implemented in the uC to improve the
resolution. Note that each
GAUSS_FILTER reading should be
synchronized to the MODEM_CLK. As an
example, accumulating 4 readings and
dividing the total by 4 will improve the
resolution by 2 bits.
Furthermore, to fully utilize the
GAUSS_FILTER dynamic range the
frequency deviation must be 16 times the
programmed baud rate.
CC1020
SWRS046E Page 43 of 89
13. Transmitter
13.1. FSK Modulation Formats
The data modulator can modulate FSK,
which is a two level FSK (Frequency Shift
Keying), or GFSK, which is a Gaussian
filtered FSK with BT = 0.5. The purpose of
the GFSK is to make a more bandwidth
efficient system as shown in Figure 20.
The modulation and the Gaussian filtering
are done internally in the chip. The
TX_SHAPING bit in the DEVIATION
register enables the GFSK. GFSK is
recommended for narrowband operation.
Figure 21 and Figure 22 show typical eye
diagrams for 434 MHz and 868 MHz
operation respectively.
Figure 20. FSK vs. GFSK spectrum plot. 2.4 kBaud, NRZ, ±2.025 kHz frequency deviation
CC1020
SWRS046E Page 44 of 89
Figure 21. FSK vs. GFSK eye diagram. 2.4 kBaud, NRZ, ±2.025 kHz frequency deviation
Figure 22. GFSK eye diagram. 153.6 kBaud, NRZ, ±79.2 kHz frequency deviation
CC1020
SWRS046E Page 45 of 89
13.2. Output Power Programming
The RF output power from the device is
programmable by the 8-bit PA_POWER
register. Figure 23 and Figure 24 shows
the output power and total current
consumption as a function of the
PA_POWER register setting. It is more
efficient in terms of current consumption to
use either the lower or upper 4-bits in the
register to control the power, as shown in
the figures. However, the output power
can be controlled in finer steps using all
the available bits in the PA_POWER
register.
-25.0
-20.0
-15.0
-10.0
-5.0
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
01234567890A0B0C0D0E0F5060708090A0B0C0D0E0F0FF
PA_POWER [hex]
Current [mA] / Output power [dBm]
Current Consumption Output Power
Figure 23. Typical output power and current consumption, 433 MHz
-25.0
-20.0
-15.0
-10.0
-5.0
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
01234567890A0B0C0D0E0F5060708090A0B0C0D0E0F0FF
PA_POWER [hex]
Current [mA] / Output power [dBm]
Current Consumption Output Power
Figure 24. Typical output power and current consumption, 868 MHz
CC1020
SWRS046E Page 46 of 89
13.3. TX Data Latency
The transmitter will add a delay due to the
synchronization of the data with DCLK and
further clocking into the modulator. The
user should therefore add a delay
equivalent to at least 2 bits after the data
payload has been transmitted before
switching off the PA (i.e. before stopping
the transmission).
13.4. Reducing Spurious Emission and Modulation Bandwidth
Modulation bandwidth and spurious
emission are normally measured with the
PA continuously on and a repeated test
sequence.
In cases where the modulation bandwidth
and spurious emission are measured with
the
CC1020
switching from power down
mode to TX mode, a PA ramping
sequence could be used to minimize
modulation bandwidth and spurious
emission.
PA ramping should then be used both
when switching the PA on and off. A linear
PA ramping sequence can be used where
register PA_POWER is changed from 00h
to 0Fh and then from 50h to the register
setting that gives the desired output power
(e.g. F0h for +10 dBm output power at 433
MHz operation). The longer the time per
PA ramping step the better, but setting the
total PA ramping time equal to 2 bit
periods is a good compromise between
performance and PA ramping time.
14. Input / Output Matching and Filtering
When designing the impedance matching
network for the
CC1020
the circuit must be
matched correctly at the harmonic
frequencies as well as at the fundamental
tone. A recommended matching network is
shown in Figure 25. Component values for
various frequencies are given in Table 21.
Component values for other frequencies
can be found using the SmartRF® Studio
software.
As can be seen from Figure 25 and Table
21, the 433 MHz network utilizes a T-type
filter, while the 868/915 MHz network has
a π-type filter topology.
It is important to remember that the
physical layout and the components used
contribute significantly to the reflection
coefficient, especially at the higher
harmonics. For this reason, the frequency
response of the matching network should
be measured and compared to the
response of the TI reference design. Refer
to Figure 27 and Table 22 as well as
Figure 28 and Table 23.
The use of an external T/R switch reduces
current consumption in TX for high output
power levels and improves the sensitivity
in RX. A recommended application circuit
is available from the TI web site
(CC1020EMX). The external T/R switch
can be omitted in certain applications, but
performance will then be degraded.
The match can also be tuned by a shunt
capacitor array at the PA output
(RF_OUT). The capacitance can be set in
0.4 pF steps and used either in RX mode
or TX mode. The RX_MATCH[3:0] and
TX_MATCH[3:0] bits in the MATCH
register control the capacitor array.
CC1020
SWRS046E Page 47 of 89
ANTENNA
RF_IN
RF_OUT
CC1020
L2
C3
AVDD=3V
L1
C1
T/R SWITCH
R10
C60
L70 L71
C71 C72
ANTENNA
RF_IN
RF_OUT
CC1020
L2
C3
AVDD=3V
L1
C1
T/R SWITCH
R10
C60
L70 L71
C71 C72
Figure 25. Input/output matching network
Item 433 MHz 868 MHz 915 MHz
C1 10 pF, 5%, NP0, 0402 47 pF, 5%, NP0, 0402 47 pF, 5%, NP0, 0402
C3 5.6 pF, 5%, NP0, 0402 10 pF, 5%, NP0, 0402 10 pF, 5%, NP0, 0402
C60 220 pF, 5%, NP0, 0402 220 pF, 5%, NP0, 0402 220 pF, 5%, NP0, 0402
C71 DNM 8.2 pF 5%, NP0, 0402 8.2 pF 5%, NP0, 0402
C72 4.7 pF, 5%, NP0, 0402 8.2 pF 5%, NP0, 0402 8.2 pF 5%, NP0, 0402
L1 33 nH, 5%, 0402 82 nH, 5%, 0402 82 nH, 5%, 0402
L2 22 nH, 5%, 0402 3.6 nH, 5%, 0402 3.6 nH, 5%, 0402
L70 47 nH, 5%, 0402 5.1 nH, 5%, 0402 5.1 nH, 5%, 0402
L71 39 nH, 5%, 0402 0 Ω resistor, 0402 0 Ω resistor, 0402
R10 82 Ω, 5%, 0402 82 Ω, 5%, 0402 82 Ω, 5%, 0402
Table 21. Component values for the matching network described in Figure 25 (DNM = Do
Not Mount).
Figure 26. Typical LNA input impedance, 200 – 1000 MHz
CC1020
SWRS046E Page 48 of 89
433 M H z
Figure 27. Typical optimum PA load impedance, 433 MHz. The frequency is swept from
300 MHz to 2500 MHz. Values are listed in Table 22
Frequency (MHz) Real (Ohms) Imaginary (Ohms)
433 54 44
866 20 173
1299 288 -563
1732 14 -123
2165 5 -66
Table 22. Impedances at the first 5 harmonics (433 MHz matching network)
CC1020
SWRS046E Page 49 of 89
868 MH z
Figure 28: Typical optimum PA load impedance, 868/915 MHz. The frequency is swept
from 300 MHz to 2800 MHz. Values are listed in Table 23
Frequency (MHz) Real (Ohms) Imaginary (Ohms)
868 15 24
915 20 35
1736 1.5 18
1830 1.7 22
2604 3.2 44
2745 3.6 45
Table 23. Impedances at the first 3 harmonics (868/915 MHz matching network)
CC1020
SWRS046E Page 50 of 89
15. Frequency Synthesizer
15.1. VCO, Charge Pump and PLL Loop Filter
The VCO is completely integrated and
operates in the 1608 – 1920 MHz range. A
frequency divider is used to get a
frequency in the UHF range (402 – 470
and 804 – 960 MHz). The BANDSELECT
bit in the ANALOG register selects the
frequency band.
The VCO frequency is given by:
⎟
⎠
⎞
⎜
⎝
⎛⋅+
+⋅= 8192
5.0
3DITHERFREQ
ff refVCO
The VCO frequency is divided by 2 and by
4 to generate frequencies in the two
bands, respectively.
The VCO sensitivity (sometimes referred
to as VCO gain) varies over frequency and
operating conditions. Typically the VCO
sensitivity varies between 12 and 36
MHz/V. For calculations the geometrical
mean at 21 MHz/V can be used. The PLL
calibration (explained below) measures
the actual VCO sensitivity and adjusts the
charge pump current accordingly to
achieve correct PLL loop gain and
bandwidth (higher charge pump current
when VCO sensitivity is lower).
The following equations can be used for
calculating PLL loop filter component
values, see Figure 3, for a desired PLL
loop bandwidth, BW:
C7 = 3037 (fref / BW2) -7 [pF]
R2 = 7126 (BW / fref) [kΩ]
C6 = 80.75 (fref / BW2) [nF]
R3 = 21823 (BW / fref) [kΩ]
C8 = 839 (fref / BW2) -6 [pF]
Define a minimum PLL loop bandwidth as
BWmin = 22075.80 ref
f⋅. If BWmin >
Baud rate/3 then set BW = BWmin and if
BWmin < Baud rate/3 then set BW = Baud
rate/3 in the above equations.
There are two special cases when using
the recommended 14.7456 MHz crystal:
1 If the data rate is 4.8 kBaud or
below and the channel spacing is
12.5 kHz the following loop filter
components are recommended:
C6 = 220 nF
C7 = 8200 pF
C8 = 2200 pF
R2 = 1.5 kΩ
R3 = 4.7 kΩ
2) If the data rate is 4.8 kBaud or below
and the channel spacing is different from
12.5 kHz the following loop filter
components are recommended:
C6 = 100 nF
C7 = 3900 pF
C8 = 1000 pF
R2 = 2.2 kΩ
R3 = 6.8 kΩ
After calibration the PLL bandwidth is set
by the PLL_BW register in combination
with the external loop filter components
calculated above. The PLL_BW can be
found from
PLL_BW = 174 + 16 log2(fref /7.126)
where fref is the reference frequency (in
MHz). The PLL loop filter bandwidth
increases with increasing PLL_BW setting.
Note that in SmartRF® Studio PLL_BW is
fixed to 9E hex when the channel spacing
is set up for 12.5 kHz, optimized
selectivity.
After calibration the applied charge pump
current (CHP_CURRENT[3:0]) can be
read in the STATUS1 register. The charge
pump current is approximately given by:
[]
uAI CURRENTCHP
CHP 4_
216 ⋅=
The combined charge pump and phase
detector gain (in A/rad) is given by the
charge pump current divided by 2π.
The PLL bandwidth will limit the maximum
modulation frequency and hence data
rate.
CC1020
SWRS046E Page 51 of 89
15.2. VCO and PLL Self-Calibration
To compensate for supply voltage,
temperature and process variations, the
VCO and PLL must be calibrated. The
calibration is performed automatically and
sets the maximum VCO tuning range and
optimum charge pump current for PLL
stability. After setting up the device at the
operating frequency, the self-calibration
can be initiated by setting the
CAL_START bit in the CALIBRATE
register. The calibration result is stored
internally in the chip, and is valid as long
as power is not turned off. If large supply
voltage drops (typically more than 0.25 V)
or temperature variations (typically more
than 40oC) occur after calibration, a new
calibration should be performed.
The nominal VCO control voltage is set by
the CAL_ITERATE[2:0] bits in the
CALIBRATE register.
The CAL_COMPLETE bit in the STATUS
register indicates that calibration has
finished. The calibration wait time
(CAL_WAIT) is programmable and is
inverse proportional to the internal PLL
reference frequency. The highest possible
reference frequency should be used to get
the minimum calibration time. It is
recommended to use CAL_WAIT[1:0] = 11
in order to get the most accurate loop
bandwidth.
Calibration
time [ms]
Reference frequency [MHz]
CAL_WAIT 1.8432 7.3728 9.8304
00 49 ms 12 ms 10 ms
01 60 ms 15 ms 11 ms
10 71 ms 18 ms 13 ms
11 109 ms 27 ms 20 ms
Table 24. Typical calibration times
The CAL_COMPLETE bit can also be
monitored at the LOCK pin, configured by
LOCK_SELECT[3:0] = 0101, and used as
an interrupt input to the microcontroller.
To check that the PLL is in lock the user
should monitor the LOCK_CONTINUOUS
bit in the STATUS register. The
LOCK_CONTINUOUS bit can also be
monitored at the LOCK pin, configured by
LOCK_SELECT[3:0] = 0010.
There are separate calibration values for
the two frequency registers. However, dual
calibration is possible if all of the below
conditions apply:
• The two frequencies A and B differ by
less than 1 MHz
• Reference frequencies are equal
(REF_DIV_A[2:0] = REF_DIV_B[2:0]
in the CLOCK_A/CLOCK_B registers)
• VCO currents are equal
(VCO_CURRENT_A[3:0] =
VCO_CURRENT_B[3:0] in the VCO
register).
The CAL_DUAL bit in the CALIBRATE
register controls dual or separate
calibration.
The single calibration algorithm
(CAL_DUAL=0) using separate calibration
for RX and TX frequency is illustrated in
Figure 29. The same algorithm is
applicable for dual calibration if
CAL_DUAL=1. Application Note AN023
CC1020 MCU Interfacing, available from
the TI web site, includes example source
code for single calibration.
TI recommends that single calibration be
used for more robust operation.
There is a small, but finite, possibility that
the PLL self-calibration will fail. The
calibration routine in the source code
should include a loop so that the PLL is re-
calibrated until PLL lock is achieved if the
PLL does not lock the first time. Refer to
CC1020
Errata Note 004.
CC1020
SWRS046E Page 52 of 89
End of c a libration
Wait for T≥100 us
Calibrate RX frequency register A
(to calibrate TX frequency register
B write MAIN register = D1h).
Register CALIBRATE = 34h
Write MAIN register = 1 1h:
RXTX=0, F_REG=0, PD_ MO D E=1,
FS_PD=0, CORE_PD=0, BIAS_PD=0,
RESET_N=1
Write FREQ_A, FREQ_B, VCO,
CLOCK_A and CL OCK_B register s.
PLL_BW = 174 + 16log2(fref/7.126)
Start single c alibration
Write CALIBRATE register = B4h
Start calibration
fref is the reference frequency (in
MHz)
Yes
Read STATUS register and wait until
LOCK_CONTINUOUS=1
Read STATUS register and wait until
CAL_COMPLETE=1
Calibration OK? No
End of c a librationEnd of c a libration
Wait for T≥100 us
Calibrate RX frequency register A
(to calibrate TX frequency register
B write MAIN register = D1h).
Register CALIBRATE = 34h
Write MAIN register = 1 1h:
RXTX=0, F_REG=0, PD_ MO D E=1,
FS_PD=0, CORE_PD=0, BIAS_PD=0,
RESET_N=1
Write FREQ_A, FREQ_B, VCO,
CLOCK_A and CL OCK_B register s.
PLL_BW = 174 + 16log2(fref/7.126)
Start single c alibrationStart single calibration
Write CALIBRATE register = B4h
Start calibration
fref is the reference frequency (in
MHz)
Yes
Read STATUS register and wait until
LOCK_CONTINUOUS=1
Read STATUS register and wait until
CAL_COMPLETE=1
Calibration OK? No
Figure 29. Single calibration algorithm for RX and TX
15.3. PLL Turn-on Time versus Loop Filter Bandwidth
If calibration has been performed the PLL
turn-on time is the time needed for the PLL
to lock to the desired frequency when
going from power down mode (with the
crystal oscillator running) to TX or RX
mode. The PLL turn-on time depends on
the PLL loop filter bandwidth. Table 25
gives the PLL turn-on time for different
PLL loop filter bandwidths.
CC1020
SWRS046E Page 53 of 89
C6
[nF]
C7
[pF]
C8
[pF]
R2
[kΩ]
R3
[kΩ]
PLL turn-on time
[us]
Comment
220 8200 2200 1.5 4.7 3200 Up to 4.8 kBaud data rate, 12.5 kHz channel
spacing
100 3900 1000 2.2 6.8 2500 Up to 4.8 kBaud data rate, 25 kHz channel spacing
56 2200 560 3.3 10 1400 Up to 9.6 kBaud data rate, 50 kHz channel spacing
15 560 150 5.6 18 1300 Up to 19.2 kBaud data rate, 100 kHz channel
spacing
3.9 120 33 12 39 1080 Up to 38.4 kBaud data rate, 150 kHz channel
spacing
1.0 27 3.3 27 82 950 Up to 76.8 kBaud data rate, 200 kHz channel
spacing
0.2 1.5 - 47 150 700 Up to 153.6 kBaud data rate, 500 kHz channel
spacing
Table 25. Typical PLL turn-on time to within ±10% of channel spacing for different loop
filter bandwidths
15.4. PLL Lock Time versus Loop Filter Bandwidth
If calibration has been performed the PLL
lock time is the time needed for the PLL to
lock to the desired frequency when going
from RX to TX mode or vice versa. The
PLL lock time depends on the PLL loop
filter bandwidth. Table 26 gives the PLL
lock time for different PLL loop filter
bandwidths.
PLL lock time
[us]
C6
[nF]
C7
[pF]
C8
[pF]
R2
[kΩ]
R3
[kΩ]
1 2 3
Comment
220 8200 2200 1.5 4.7 900 180 1300 Up to 4.8 kBaud data rate, 12.5 kHz channel
spacing
100 3900 1000 2.2 6.8 640 270 830 Up to 4.8 kBaud data rate, 25 kHz channel
spacing
56 2200 560 3.3 10 400 140 490 Up to 9.6 kBaud data rate, 50 kHz channel
spacing
15 560 150 5.6 18 140 70 230 Up to 19.2 kBaud data rate, 100 kHz channel
spacing
3.9 120 33 12 39 75 50 180 Up to 38.4 kBaud data rate, 150 kHz channel
spacing
1.0 27 3.3 27 82 30 15 55 Up to 76.8 kBaud data rate, 200 kHz channel
spacing
0.2 1.5 - 47 150 14 14 28 Up to 153.6 kBaud data rate, 500 kHz channel
spacing
Table 26. Typical PLL lock time to within ±10% of channel spacing for different loop filter
bandwidths. 1) 307.2 kHz step, 2) 1 channel step, 3) 1 MHz step
16. VCO and LNA Current Control
The VCO current is programmable and
should be set according to operating
frequency, RX/TX mode and output power.
Recommended settings for the
VCO_CURRENT bits in the VCO register
are shown in the register overview and
also given by SmartRF® Studio. The VCO
current for frequency FREQ_A and
FREQ_B can be programmed
independently.
The bias currents for the LNA, mixer and
the LO and PA buffers are also
programmable. The FRONTEND and the
BUFF_CURRENT registers control these
currents.
CC1020
SWRS046E Page 54 of 89
17. Power Management
CC1020
offers great flexibility for power
management in order to meet strict power
consumption requirements in battery-
operated applications. Power down mode
is controlled through the MAIN register.
There are separate bits to control the RX
part, the TX part, the frequency
synthesizer and the crystal oscillator in the
MAIN register. This individual control can
be used to optimize for lowest possible
current consumption in each application.
Figure 30 shows a typical power-on and
initializing sequence for minimum power
consumption.
Figure 31 shows a typical sequence for
activating RX and TX mode from power
down mode for minimum power
consumption.
Note that PSEL should be tri-stated or set
to a high level during power down mode in
order to prevent a trickle current from
flowing in the internal pull-up resistor.
Application Note AN023 CC1020 MCU
Interfacing includes example source code
and is available from the TI web site.
TI recommends resetting the
CC1020
(by
clearing the RESET_N bit in the MAIN
register) when the chip is powered up
initially. All registers that need to be
configured should then be programmed
(those which differ from their default
values). Registers can be programmed
freely in any order. The
CC1020
should
then be calibrated in both RX and TX
mode. After this is completed, the
CC1020
is ready for use. See the detailed
procedure flowcharts in Figure 29 – Figure
31.
With reference to Application Note AN023
CC1020 MCU Interfacing TI recommends
the following sequence:
After power up:
1) ResetCC1020
2) Initialize
3) WakeUpCC1020ToRX
4) Calibrate
5) WakeUpCC1020ToTX
6) Calibrate
After calibration is completed, enter TX
mode (SetupCC1020TX), RX mode
(SetupCC1020RX) or power down mode
(SetupCC1020PD)
From power-down mode to RX:
1) WakeUpCC1020ToRX
2) SetupCC1020RX
From power-down mode to TX:
1) WakeUpCC1020ToTX
2) SetupCC1020TX
Switching from RX to TX mode:
1) SetupCC1020TX
Switching from TX to RX mode:
1 SetupCC1020RX
CC1020
SWRS046E Page 55 of 89
Power Down mode
Pow er Off
RESET_N=1
ResetCC1020
WakeupCC1020ToRx/
WakeupCC1020ToTx
Cali brate VCO and PLL
SetupCC1020PD
Program all necessary registers
except MAIN and RESET
Turn on crystal oscillator, bias
generator and synthesizer
successively
Turn on power
Reset CC1020
MAIN: RX_T X=0, F_REG=0,
PD_MODE=1, FS_PD=1,
XOSC_PD=1 , BIAS_PD=1
RESET_N=0
MAIN: PD_MODE=1, FS_PD=1,
XOSC_PD=1 , BIAS_PD=1
PA_POWER=00h
Power Down mode
Pow er OffPower Off
RESET_N=1
ResetCC1020
WakeupCC1020ToRx/
WakeupCC1020ToTx
Cali brate VCO and PLL
SetupCC1020PD
Program all necessary registers
except MAIN and RESET
Turn on crystal oscillator, bias
generator and synthesizer
successively
Turn on power
Reset CC1020
MAIN: RX_T X=0, F_REG=0,
PD_MODE=1, FS_PD=1,
XOSC_PD=1 , BIAS_PD=1
RESET_N=0
MAIN: PD_MODE=1, FS_PD=1,
XOSC_PD=1 , BIAS_PD=1
PA_POWER=00h
Figure 30. Initialising sequence
CC1020
SWRS046E Page 56 of 89
Turn on crystal oscillator core
MAIN: PD_MODE=1, FS_PD=1, XOSC_PD=0, BIAS_PD=1
Wait 1.2 ms*
Power Down mode *Time to wait depends
on the crystal frequency
and the load capacitance
Wait until lock detected from LOCK pin
or STATUS register
Turn on RX: MAIN: PD_MODE = 0
Wait until lock detected from LOCK pin
or STATUS register
Turn on TX: MAIN: PD_MODE = 0
Set PA_POWER
RX mode TX mode
Turn off RX/TX:
MAIN: PD_MODE = 1, FS_PD=1,
XOSC_PD=1, BIAS_PD=1
PA_POWER=00h
Power Down mode
Turn on frequency synthesizer
MAIN: RXTX=0, F_REG=0, FS_PD=0 Turn on frequency synthesizer
MAIN: RXTX=1, F_REG=1, FS_PD=0
RX or TX?
RX TX
WakeupCC1020ToRxSetupCC1020RxSetupCC1020PD
WakeupCC1020ToTx
SetupCC1020Tx
SetupCC1020PD
Turn on bias generator. MAIN: BIAS_PD=0
Wait 150 us
Turn on crystal oscillator core
MAIN: PD_MODE=1, FS_PD=1, XOSC_PD=0, BIAS_PD=1
Wait 1.2 ms*
Power Down modePower Down mode *Time to wait depends
on the crystal frequency
and the load capacitance
Wait until lock detected from LOCK pin
or STATUS register
Turn on RX: MAIN: PD_MODE = 0
Wait until lock detected from LOCK pin
or STATUS register
Turn on TX: MAIN: PD_MODE = 0
Set PA_POWER
Wait until lock detected from LOCK pin
or STATUS register
Turn on RX: MAIN: PD_MODE = 0
Wait until lock detected from LOCK pin
or STATUS register
Turn on TX: MAIN: PD_MODE = 0
Set PA_POWER
RX mode TX mode
RX modeRX mode TX modeTX mode
Turn off RX/TX:
MAIN: PD_MODE = 1, FS_PD=1,
XOSC_PD=1, BIAS_PD=1
PA_POWER=00h
Power Down modePower Down mode
Turn on frequency synthesizer
MAIN: RXTX=0, F_REG=0, FS_PD=0 Turn on frequency synthesizer
MAIN: RXTX=1, F_REG=1, FS_PD=0
Turn on frequency synthesizer
MAIN: RXTX=0, F_REG=0, FS_PD=0 Turn on frequency synthesizer
MAIN: RXTX=1, F_REG=1, FS_PD=0
RX or TX?
RX TX
WakeupCC1020ToRxSetupCC1020RxSetupCC1020PD
WakeupCC1020ToTx
SetupCC1020Tx
SetupCC1020PD
Turn on bias generator. MAIN: BIAS_PD=0
Wait 150 us
Figure 31. Sequence for activating RX or TX mode
CC1020
SWRS046E Page 57 of 89
18. On-Off Keying (OOK)
The data modulator can also provide OOK
(On-Off Keying) modulation. OOK is an
ASK (Amplitude Shift Keying) modulation
using 100% modulation depth. OOK
modulation is enabled in RX and in TX by
setting TXDEV_M[3:0] = 0000 in the
DEVIATION register. An OOK eye
diagram is shown in Figure 32.
The data demodulator can also perform
OOK demodulation. The demodulation is
done by comparing the signal level with
the “carrier sense” level (programmed as
CS_LEVEL in the VGA4 register). The
signal is then decimated and filtered in the
data filter. Data decision and bit
synchronization are as for FSK reception.
In this mode AGC_AVG in the VGA2
register must be set to 3. The channel
bandwidth must be 4 times the Baud rate
for data rates up to 9.6 kBaud. For the
highest data rates the channel bandwidth
must be 2 times the Baud rate (see Table
27). Manchester coding must always be
used for OOK.
Note that the automatic frequency control
(AFC) cannot be used when receiving
OOK, as it requires a frequency shift.
The AGC has a certain time-constant
determined by FILTER_CLK, which
depends on the IF filter bandwidth. There
is a lower limit on FILTER_CLK and hence
the AGC time constant. For very low data
rates the minimum time constant is too
fast and the AGC will increase the gain
when a “0” is received and decrease the
gain when a “1” is received. For this
reason the minimum data rate in OOK is
2.4 kBaud.
Typical figures for the receiver sensitivity
(BER = 10-3) are shown in Table 27 for
OOK.
Figure 32. OOK eye diagram. 9.6 kBaud
CC1020
SWRS046E Page 58 of 89
Sensitivity [dBm]
Data rate
[kBaud]
Filter BW
[kHz] 433 MHz
Manchester mode
868 MHz
Manchester mode
2.4 9.6 -116
4.8 19.2 -113 -107
9.6 38.4 -103 -104
19.2 51.2 -102 -101
38.4 102.4 -95 -97
76.8 153.6 -92 -94
153.6 307.2 -81 -87
Table 27. Typical receiver sensitivity as a function of data rate at 433 and 868 MHz, OOK
modulation, BER = 10-3, pseudo-random data (PN9 sequence)
19. Crystal Oscillator
The recommended crystal frequency is
14.7456 MHz, but any crystal frequency in
the range 4 – 20 MHz can be used. Using
a crystal frequency different from 14.7456
MHz might in some applications give
degraded performance. Refer to
Application Note AN022 Crystal
Frequency Selection for more details on
the use of other crystal frequencies than
14.7456 MHz. The crystal frequency is
used as reference for the data rate (as
well as other internal functions) and in the
4 – 20 MHz range the frequencies 4.9152,
7.3728, 9.8304, 12.2880, 14.7456,
17.2032, 19.6608 MHz will give accurate
data rates as shown in Table 17 and an IF
frequency of 307.2 kHz. The crystal
frequency will influence the programming
of the CLOCK_A, CLOCK_B and MODEM
registers.
An external clock signal or the internal
crystal oscillator can be used as main
frequency reference. An external clock
signal should be connected to XOSC_Q1,
while XOSC_Q2 should be left open. The
XOSC_BYPASS bit in the INTERFACE
register should be set to ‘1’ when an
external digital rail-to-rail clock signal is
used. No DC block should be used then. A
sine with smaller amplitude can also be
used. A DC blocking capacitor must then
be used (10 nF) and the XOSC_BYPASS
bit in the INTERFACE register should be
set to ‘0’. For input signal amplitude, see
section 4.5 on page 12.
Using the internal crystal oscillator, the
crystal must be connected between the
XOSC_Q1 and XOSC_Q2 pins. The
oscillator is designed for parallel mode
operation of the crystal. In addition,
loading capacitors (C4 and C5) for the
crystal are required. The loading capacitor
values depend on the total load
capacitance, CL, specified for the crystal.
The total load capacitance seen between
the crystal terminals should equal CL for
the crystal to oscillate at the specified
frequency.
parasiticL C
CC
C+
+
=
54
11 1
The parasitic capacitance is constituted by
pin input capacitance and PCB stray
capacitance. Total parasitic capacitance is
typically 8 pF. A trimming capacitor may
be placed across C5 for initial tuning if
necessary.
The crystal oscillator circuit is shown in
Figure 33. Typical component values for
different values of CL are given in Table
28.
The crystal oscillator is amplitude
regulated. This means that a high current
is required to initiate the oscillations. When
the amplitude builds up, the current is
reduced to what is necessary to maintain
approximately 600 mVpp amplitude. This
ensures a fast start-up, keeps the drive
level to a minimum and makes the
oscillator insensitive to ESR variations. As
long as the recommended load
capacitance values are used, the ESR is
not critical.
The initial tolerance, temperature drift,
aging and load pulling should be carefully
specified in order to meet the required
frequency accuracy in a certain
CC1020
SWRS046E Page 59 of 89
application. By specifying the total
expected frequency accuracy in SmartRF®
Studio together with data rate and
frequency separation, the software will
estimate the total bandwidth and compare
to the available receiver channel filter
bandwidth. The software will report any
contradictions and a more accurate crystal
will be recommended if required.
Figure 33. Crystal oscillator circuit
Item CL= 12 pF CL= 16 pF CL= 22 pF
C4 6.8 pF 15 pF 27 pF
C5 6.8 pF 15 pF 27 pF
Table 28. Crystal oscillator component values
20. Built-in Test Pattern Generator
The
CC1020
has a built-in test pattern
generator that generates a PN9 pseudo
random sequence. The PN9_ENABLE bit
in the MODEM register enables the PN9
generator. A transition on the DIO pin is
required after enabling the PN9 pseudo
random sequence.
The PN9 pseudo random sequence is
defined by the polynomial x9 + x5 + 1.
The PN9 sequence is ‘XOR’ed with the
DIO signal in both TX and RX mode as
shown in Figure 34. Hence, by transmitting
only zeros (DIO = 0), the BER (Bit Error
Rate) can be tested by counting the
number of received ones. Note that the 9
first received bits should be discarded in
this case. Also note that one bit error will
generate 3 received ones.
Transmitting only ones (DIO = 1), the BER
can be tested by counting the number of
received zeroes.
The PN9 generator can also be used for
transmission of ‘real-life’ data when
measuring narrowband ACP (Adjacent
Channel Power), modulation bandwidth or
occupied bandwidth.
C5C4
XTAL
XOSC_Q2 XOSC_Q1
CC1020
SWRS046E Page 60 of 89
876543210
XOR
XOR
Tx out (modulating signal)
Tx data (DIO pin)
876543210
XOR
XOR
Rx pseudo random sequence
Rx in (Demodulated Rx data)
Rx out (DIO pin)
Tx pseudo random sequence
Figure 34. PN9 pseudo random sequence generator in TX and RX mode
21. Interrupt on Pin DCLK
21.1. Interrupt upon PLL Lock
In synchronous mode the DCLK pin on
CC1020
can be used to give an interrupt
signal to wake the microcontroller when
the PLL is locked.
PD_MODE[1:0] in the MAIN register
should be set to 01. If DCLK_LOCK in the
INTERFACE register is set to 1 the DCLK
signal is always logic high if the PLL is not
in lock. When the PLL locks to the desired
frequency the DCLK signal changes to
logic 0. When this interrupt has been
detected write PD_MODE[1:0] = 00. This
will enable the DCLK signal.
This function can be used to wait for the
PLL to be locked before the PA is ramped
up in transmit mode. In receive mode, it
can be used to wait until the PLL is locked
before searching for preamble.
21.2. Interrupt upon Received Signal Carrier Sense
In synchronous mode the DCLK pin on
CC1020
can also be used to give an
interrupt signal to the microcontroller when
the RSSI level exceeds a certain threshold
(carrier sense threshold). This function can
be used to wake or interrupt the
microcontroller when a strong signal is
received.
Gating the DCLK signal with the carrier
sense signal makes the interrupt signal.
This function should only be used in
receive mode and is enabled by setting
DCLK_CS = 1 in the INTERFACE register.
CC1020
SWRS046E Page 61 of 89
The DCLK signal is always logic high
unless carrier sense is indicated. When
carrier sense is indicated the DCLK starts
running. When gating the DCLK signal
with the carrier sense signal at least 2
dummy bits should be added after the data
payload in TX mode. The reason being
that the carrier sense signal is generated
earlier in the receive chain (i.e. before the
demodulator), causing it to be updated 2
bits before the corresponding data is
available on the DIO pin.
In transmit mode DCLK_CS must be set to
0. Refer to
CC1020
Errata Note 002.
22. PA_EN and LNA_EN Digital Output Pins
22.1. Interfacing an External LNA or PA
CC1020
has two digital output pins, PA_EN
and LNA_EN, which can be used to
control an external LNA or PA. The
functionality of these pins are controlled
through the INTERFACE register. The
outputs can also be used as general digital
output control signals.
EXT_PA_POL and EXT_LNA_POL control
the active polarity of the signals.
EXT_PA and EXT_LNA control the
function of the pins. If EXT_PA = 1, then
the PA_EN pin will be activated when the
internal PA is turned on. Otherwise, the
EXT_PA_POL bit controls the PA_EN pin
directly. If EXT_LNA = 1, then the
LNA_EN pin will be activated when the
internal LNA is turned on. Otherwise, the
EXT_LNA_POL bit controls the LNA_EN
pin directly.
These two pins can therefore also be used
as two general control signals, see section
22.2. In the TI reference design LNA_EN
and PA_EN are used to control the
external T/R switch.
22.2. General Purpose Output Control Pins
The two digital output pins, PA_EN and
LNA_EN, can be used as two general
control signals by setting EXT_PA = 0 and
EXT_LNA = 0. The output value is then
set directly by the value written to
EXT_PA_POL and EXT_LNA_POL.
The LOCK pin can also be used as a
general-purpose output pin. The LOCK pin
is controlled by LOCK_SELECT[3:0] in the
LOCK register. The LOCK pin is low when
LOCK_SELECT[3:0] = 0000, and high
when LOCK_SELECT[3:0] = 0001.
These features can be used to save I/O
pins on the microcontroller when the other
functions associated with these pins are
not used.
22.3. PA_EN and LNA_EN Pin Drive
Figure 35 shows the PA_EN and LNA_EN
pin drive currents. The sink and source
currents have opposite signs but absolute
values are used in Figure 35.
CC1020
SWRS046E Page 62 of 89
0
200
400
600
800
1000
1200
1400
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
oltage on PA_EN/LNA_EN pin [V]
Current [uA]
source current, 3 V sink current, 3V source current, 2.3 V
sink current, 2.3 V source current, 3.6 V sink current, 3.6 V
Figure 35. Typical PA_EN and LNA_EN pin drive
23. System Considerations and Guidelines
SRD regulations
International regulations and national laws
regulate the use of radio receivers and
transmitters. SRDs (Short Range Devices)
for license free operation are allowed to
operate in the 433 and 868 – 870 MHz
bands in most European countries. In the
United States, such devices operate in the
260 – 470 and 902 – 928 MHz bands.
CC1020
is also applicable for use in the 950
– 960 MHz frequency band in Japan. A
summary of the most important aspects of
these regulations can be found in
Application Note AN001 SRD regulations
for license free transceiver operation,
available from the TI web site.
Narrowband systems
CC1020
is specifically designed for
narrowband systems complying with ARIB
STD-T67 and EN 300 220. The
CC1020
meets the strict requirements to ACP
(Adjacent Channel Power) and occupied
bandwidth for a narrowband transmitter.
To meet the ARIB STD-T67 requirements
a 3.0 V regulated voltage supply should be
used.
For the receiver side,
CC1020
gives very
good ACR (Adjacent Channel Rejection),
image frequency suppression and blocking
properties for channel spacings down to
12.5 kHz.
Such narrowband performance normally
requires the use of external ceramic filters.
The
CC1020
provides this performance as
a true single-chip solution with integrated
IF filters.
Japan and Korea have allocated several
frequency bands at 424, 426, 429, 447,
449 and 469 MHz for narrowband license
free operation.
CC1020
is designed to
meet the requirements for operation in all
these bands, including the strict
requirements for narrowband operation
down to 12.5 kHz channel spacing.
Due to on-chip complex filtering, the image
frequency is removed. An on-chip
calibration circuit is used to get the best
possible image rejection. A narrowband
preselector filter is not necessary to
achieve image rejection.
A unique feature in
CC1020
is the very fine
frequency resolution. This can be used for
temperature compensation of the crystal if
the temperature drift curve is known and a
temperature sensor is included in the
system. Even initial adjustment can be
performed using the frequency
CC1020
SWRS046E Page 63 of 89
programmability. This eliminates the need
for an expensive TCXO and trimming in
some applications. For more details refer
to Application Note AN027 Temperature
Compensation available from the TI web
site.
In less demanding applications, a crystal
with low temperature drift and low aging
could be used without further
compensation. A trimmer capacitor in the
crystal oscillator circuit (in parallel with C5)
could be used to set the initial frequency
accurately.
The frequency offset between a
transmitter and receiver is measured in the
CC1020
and can be read back from the
AFC register. The measured frequency
offset can be used to calibrate the receiver
frequency using the transmitter as the
reference. For more details refer to
Application Note AN029 CC1020/1021
AFC available from the TI web site.
CC1020
also has the possibility to use
Gaussian shaped FSK (GFSK). This
spectrum-shaping feature improves
adjacent channel power (ACP) and
occupied bandwidth. In ‘true’ FSK systems
with abrupt frequency shifting, the
spectrum is inherently broad. By making
the frequency shift ‘softer’, the spectrum
can be made significantly narrower. Thus,
higher data rates can be transmitted in the
same bandwidth using GFSK.
Low cost systems
As the
CC1020
provides true narrowband
multi-channel performance without any
external filters, a very low cost high
performance system can be achieved. The
oscillator crystal can then be a low cost
crystal with 50 ppm frequency tolerance
using the on-chip frequency tuning
possibilities.
Battery operated systems
In low power applications, the power down
mode should be used when
CC1020
is not
being active. Depending on the start-up
time requirement, the oscillator core can
be powered during power down. See
section 17 on page 54 for information on
how effective power management can be
implemented.
High reliability systems
Using a SAW filter as a preselector will
improve the communication reliability in
harsh environments by reducing the
probability of blocking. The receiver
sensitivity and the output power will be
reduced due to the filter insertion loss. By
inserting the filter in the RX path only,
together with an external RX/TX switch,
only the receiver sensitivity is reduced and
output power is remained. The PA_EN
and LNA_EN pin can be configured to
control an external LNA, RX/TX switch or
power amplifier. This is controlled by the
INTERFACE register.
Frequency hopping spread spectrum
systems (FHSS)
Due to the very fast locking properties of
the PLL, the
CC1020
is also very suitable
for frequency hopping systems. Hop rates
of 1-100 hops/s are commonly used
depending on the bit rate and the amount
of data to be sent during each
transmission. The two frequency registers
(FREQ_A and FREQ_B) are designed
such that the ‘next’ frequency can be
programmed while the ‘present’ frequency
is used. The switching between the two
frequencies is done through the MAIN
register. Several features have been
included to do the hopping without a need
to re-synchronize the receiver. For more
details refer to Application Note AN014
Frequency Hopping Systems available
from the TI web site.
In order to implement a frequency hopping
system with
CC1020
do the following:
Set the desired frequency, calibrate and
store the following register settings in non-
volatile memory:
STATUS1[3:0]: CHP_CURRENT[3:0]
STATUS2[4:0]: VCO_ARRAY[4:0]
STATUS3[5:0]:VCO_CAL_CURRENT[5:0]
Repeat the calibration for each desired
frequency. VCO_CAL_CURRENT[5:0] is
not dependent on the RF frequency and
the same value can be used for all
frequencies.
When performing frequency hopping, write
the stored values to the corresponding
TEST1, TEST2 and TEST3 registers, and
enable override:
TEST1[3:0]: CHP_CO[3:0]
TEST2[4:0]: VCO_AO[4:0]
CC1020
SWRS046E Page 64 of 89
TEST2[5]: VCO_OVERRIDE
TEST2[6]: CHP_OVERRIDE
TEST3[5:0]: VCO_CO[5:0]
TEST3[6]: VCO_CAL_OVERRIDE
CHP_CO[3:0] is the register setting read
from CHP_CURRENT[3:0], VCO_AO[4:0]
is the register setting read from
VCO_ARRAY[4:0] and VCO_CO[5:0] is
the register setting read from
VCO_CAL_CURRENT[5:0].
Assume channel 1 defined by register
FREQ_A is currently being used and that
CC1020
should operate on channel 2 next
(to change channel simply write to register
MAIN[6]). The channel 2 frequency can be
set by register FREQ_B which can be
written to while operating on channel 1.
The calibration data must be written to the
TEST1-3 registers after switching to the
next frequency. That is, when hopping to a
new channel write to register MAIN[6] first
and the test registers next. The PA should
be switched off between each hop and the
PLL should be checked for lock before
switching the PA back on after a hop has
been performed.
Note that the override bits
VCO_OVERRIDE, CHP_OVERRIDE and
VCO_CAL_OVERRIDE must be disabled
when performing a re-calibration.
24. PCB Layout Recommendations
The top layer should be used for signal
routing, and the open areas should be
filled with metallization connected to
ground using several vias.
The area under the chip is used for
grounding and must be connected to the
bottom ground plane with several vias. In
the TI reference designs we have placed 9
vias inside the exposed die attached pad.
These vias should be “tented” (covered
with solder mask) on the component side
of the PCB to avoid migration of solder
through the vias during the solder reflow
process.
Do not place a via underneath
CC1020
at
“pin #1 corner” as this pin is internally
connected to the exposed die attached
pad, which is the main ground connection
for the chip.
Each decoupling capacitor should be
placed as close as possible to the supply
pin it is supposed to decouple. Each
decoupling capacitor should be connected
to the power line (or power plane) by
separate vias. The best routing is from the
power line (or power plane) to the
decoupling capacitor and then to the
CC1020
supply pin. Supply power filtering is
very important, especially for pins 23, 22,
20 and 18.
Each decoupling capacitor ground pad
should be connected to the ground plane
using a separate via. Direct connections
between neighboring power pins will
increase noise coupling and should be
avoided unless absolutely necessary.
The external components should ideally
be as small as possible and surface mount
devices are highly recommended.
Precaution should be used when placing
the microcontroller in order to avoid noise
interfering with the RF circuitry.
A CC1020/1070DK Development Kit with
a fully assembled CC1020EMX Evaluation
Module is available. It is strongly advised
that this reference layout is followed very
closely in order to get the best
performance. The layout Gerber files are
available from the TI web site.
CC1020
SWRS046E Page 65 of 89
25. Antenna Considerations
CC1020
can be used together with various
types of antennas. The most common
antennas for short-range communication
are monopole, helical and loop antennas.
Monopole antennas are resonant
antennas with a length corresponding to
one quarter of the electrical wavelength
(λ/4). They are very easy to design and
can be implemented simply as a “piece of
wire” or even integrated onto the PCB.
Non-resonant monopole antennas shorter
than λ/4 can also be used, but at the
expense of range. In size and cost critical
applications such an antenna may very
well be integrated onto the PCB.
Helical antennas can be thought of as a
combination of a monopole and a loop
antenna. They are a good compromise in
size critical applications. But helical
antennas tend to be more difficult to
optimize than the simple monopole.
Loop antennas are easy to integrate into
the PCB, but are less effective due to
difficult impedance matching because of
their very low radiation resistance.
For low power applications the λ/4-
monopole antenna is recommended due
to its simplicity as well as providing the
best range.
The length of the λ/4-monopole antenna is
given by:
L = 7125 / f
where f is in MHz, giving the length in cm.
An antenna for 868 MHz should be 8.2
cm, and 16.4 cm for 433 MHz.
The antenna should be connected as
close as possible to the IC. If the antenna
is located away from the input pin the
antenna should be matched to the feeding
transmission line (50 Ω).
For a more thorough background on
antennas, please refer to Application Note
AN003 SRD Antennas available from the
TI web site.
26. Configuration Registers
The configuration of
CC1020
is done by
programming the 8-bit configuration
registers. The configuration data based on
selected system parameters are most
easily found by using the SmartRF® Studio
software. Complete descriptions of the
registers are given in the following tables.
After a RESET is programmed, all the
registers have default values. The TEST
registers also get default values after a
RESET, and should not be altered by the
user.
TI recommends using the register settings
found using the SmartRF® Studio
software. These are the register settings
that TI specifies across temperature,
voltage and process. Please check the TI
web site for regularly updates to the
SmartRF® Studio software.
CC1020
SWRS046E Page 66 of 89
26.1. CC1020 Register Overview
ADDRESS Byte Name Description
00h MAIN Main control register
01h INTERFACE Interface control register
02h RESET Digital module reset register
03h SEQUENCING Automatic power-up sequencing control register
04h FREQ_2A Frequency register 2A
05h FREQ_1A Frequency register 1A
06h FREQ_0A Frequency register 0A
07h CLOCK_A Clock generation register A
08h FREQ_2B Frequency register 2B
09h FREQ_1B Frequency register 1B
0Ah FREQ_0B Frequency register 0B
0Bh CLOCK_B Clock generation register B
0Ch VCO VCO current control register
0Dh MODEM Modem control register
0Eh DEVIATION TX frequency deviation register
0Fh AFC_CONTROL RX AFC control register
10h FILTER Channel filter / RSSI control register
11h VGA1 VGA control register 1
12h VGA2 VGA control register 2
13h VGA3 VGA control register 3
14h VGA4 VGA control register 4
15h LOCK Lock control register
16h FRONTEND Front end bias current control register
17h ANALOG Analog modules control register
18h BUFF_SWING LO buffer and prescaler swing control register
19h BUFF_CURRENT LO buffer and prescaler bias current control register
1Ah PLL_BW PLL loop bandwidth / charge pump current control register
1Bh CALIBRATE PLL calibration control register
1Ch PA_POWER Power amplifier output power register
1Dh MATCH Match capacitor array control register, for RX and TX impedance matching
1Eh PHASE_COMP Phase error compensation control register for LO I/Q
1Fh GAIN_COMP Gain error compensation control register for mixer I/Q
20h POWERDOWN Power-down control register
21h TEST1 Test register for overriding PLL calibration
22h TEST2 Test register for overriding PLL calibration
23h TEST3 Test register for overriding PLL calibration
24h TEST4 Test register for charge pump and IF chain testing
25h TEST5 Test register for ADC testing
26h TEST6 Test register for VGA testing
27h TEST7 Test register for VGA testing
40h STATUS Status information register (PLL lock, RSSI, calibration ready, etc.)
41h RESET_DONE Status register for digital module reset
42h RSSI Received signal strength register
43h AFC Average received frequency deviation from IF (can be used for AFC)
44h GAUSS_FILTER Digital FM demodulator register
45h STATUS1 Status of PLL calibration results etc. (test only)
46h STATUS2 Status of PLL calibration results etc. (test only)
47h STATUS3 Status of PLL calibration results etc. (test only)
48h STATUS4 Status of ADC signals (test only)
49h STATUS5 Status of channel filter “I” signal (test only)
4Ah STATUS6 Status of channel filter “Q” signal (test only)
4Bh STATUS7 Status of AGC (test only)
CC1020
SWRS046E Page 67 of 89
MAIN Register (00h)
REGISTER NAME Default
value
Active Description
MAIN[7] RXTX - - RX/TX switch, 0: RX , 1: TX
MAIN[6] F_REG - - Selection of Frequency Register,
0: Register A, 1: Register B
MAIN[5:4] PD_MODE[1 :0] - - Power down mode
0 (00): Receive Chain in power-down in TX, PA in power-down in
RX
1 (01): Receive Chain and PA in power-down in both TX and RX
2 (10): Individual modules can be put in power-down by
programming the POWERDOWN register
3 (11): Automatic power-up sequencing is activated (see below)
MAIN[3] FS_PD - H Power Down of Frequency Synthesizer
MAIN[2] XOSC_PD - H Power Down of Crystal Oscillator Core
MAIN[1] BIAS_PD - H Power Down of BIAS (Global Current Generator) and Crystal
Oscillator Buffer
MAIN[0] RESET_N - L Reset, active low. Writing RESET_N low will write default values to
all other registers than MAIN. Bits in MAIN do not have a default
value and will be written directly through the configuration
interface. Must be set high to complete reset.
MAIN Register (00h) when using automatic power-up sequencing (RXTX = 0, PD_MODE[1:0] =11)
REGISTER NAME Default
value
Active Description
MAIN[7] RXTX - - Automatic power-up sequencing only works in RX (RXTX=0)
MAIN[6] F_REG - - Selection of Frequency Register, 0: Register A, 1: Register B
MAIN[5 :4] PD_MODE[1 :0] - H Set PD_MODE[1:0]=3 (11) to enable sequencing
MAIN[3:2] SEQ_CAL[1:0]
- - Controls PLL calibration before re-entering power-down
0: Never perform PLL calibration as part of sequence
1: Always perform PLL calibration at end of sequence
2: Perform PLL calibration at end of every 16th sequence
3: Perform PLL calibration at end of every 256th sequence
MAIN[1] SEQ_PD - ↑ ↑1: Put the chip in power down and wait for start of new power-up
sequence
MAIN[0] RESET_N - L Reset, active low. Writing RESET_N low will write default values to
all other registers than MAIN. Bits in MAIN do not have a default
value and will be written directly through the configuration
interface. Must be set high to complete reset.
CC1020
SWRS046E Page 68 of 89
INTERFACE Register (01h)
REGISTER NAME Default
value
Active Description
INTERFACE[7] XOSC_BYPASS 0 H Bypass internal crystal oscillator, use external clock
0: Internal crystal oscillator is used, or external sine wave fed
through a coupling capacitor
1: Internal crystal oscillator in power down, external clock
with rail-to-rail swing is used
INTERFACE[6] SEP_DI_DO 0 H Use separate pin for RX data output
0: DIO is data output in RX and data input in TX. LOCK pin
is available (Normal operation).
1: DIO is always input, and a separate pin is used for RX
data output (synchronous mode: LOCK pin, asynchronous
mode: DCLK pin).
If SEP_DI_DO=1 and SEQ_PSEL=0 in SEQUENCING
register then negative transitions on DIO is used to start
power-up sequencing when PD_MODE=3 (power-up
sequencing is enabled).
INTERFACE[5] DCLK_LOCK 0 H Gate DCLK signal with PLL lock signal in synchronous mode
Only applies when PD_MODE = “01”
0: DCLK is always 1
1: DCLK is always 1 unless PLL is in lock
INTERFACE[4] DCLK_CS 0 H Gate DCLK signal with carrier sense indicator in
synchronous mode
Use when receive chain is active (in power-up)
Always set to 0 in TX mode.
0: DCLK is independent of carrier sense indicator.
1: DCLK is always 1 unless carrier sense is indicated
INTERFACE[3] EXT_PA 0 H Use PA_EN pin to control external PA
0: PA_EN pin always equals EXT_PA_POL bit
1: PA_EN pin is asserted when internal PA is turned on
INTERFACE[2] EXT_LNA 0 H Use LNA_EN pin to control external LNA
0: LNA_EN pin always equals EXT_LNA_POL bit
1: LNA_EN pin is asserted when internal LNA is turned on
INTERFACE[1] EXT_PA_POL 0 H Polarity of external PA control
0: PA_EN pin is “0” when activating external PA
1: PA_EN pin is “1” when activating external PA
INTERFACE[0] EXT_LNA_POL 0 H Polarity of external LNA control
0: LNA_EN pin is “0” when activating external LNA
1: LNA_EN pin is “1” when activating external LNA
Note: If TF_ENABLE=1 or TA_ENABLE=1 in TEST4 register, then INTERFACE[3:0] controls analog test
module: INTERFACE[3] = TEST_PD, INTERFACE[2:0] = TEST_MODE[2:0]. Otherwise, TEST_PD=1
and TEST_MODE[2:0]=001.
RESET Register (02h)
REGISTER NAME Default
value
Active Description
RESET[7] ADC_RESET_N 0 L Reset ADC control logic
RESET[6] AGC_RESET_N 0 L Reset AGC (VGA control) logic
RESET[5] GAUSS_RESET_N 0 L Reset Gaussian data filter
RESET[4] AFC_RESET_N 0 L Reset AFC / FSK decision level logic
RESET[3] BITSYNC_RESET_N 0 L Reset modulator, bit synchronization logic and PN9
PRBS generator
RESET[2] SYNTH_RESET_N 0 L Reset digital part of frequency synthesizer
RESET[1] SEQ_RESET_N 0 L Reset power-up sequencing logic
RESET[0] CAL_LOCK_RESET_N 0 L Reset calibration logic and lock detector
Note: For reset of CC1020 write RESET_N=0 in the MAIN register. The reset register should not be
used during normal operation.
Bits in the RESET register are self-clearing (will be set to 1 when the reset operation starts). Relevant
digital clocks must be running for the resetting to complete. After writing to the RESET register, the user
should verify that all reset operations have been completed, by reading the RESET_DONE status
register (41h) until all bits equal 1.
CC1020
SWRS046E Page 69 of 89
SEQUENCING Register (03h)
REGISTER NAME Default
value
Active Description
SEQUENCING[7] SEQ_PSEL 1 H Use PSEL pin to start sequencing
0: PSEL pin does not start sequencing. Negative
transitions on DIO starts power-up sequencing if
SEP_DI_DO=1.
1: Negative transitions on the PSEL pin will start power-
up sequencing
SEQUENCING[6:4] RX_WAIT[2:0] 0 - Waiting time from PLL enters lock until RX power-up
0: Wait for approx. 32 ADC_CLK periods (26 µs)
1: Wait for approx. 44 ADC_CLK periods (36 µs)
2: Wait for approx. 64 ADC_CLK periods (52 µs)
3: Wait for approx. 88 ADC_CLK periods (72 µs)
4: Wait for approx. 128 ADC_CLK periods (104 µs)
5: Wait for approx. 176 ADC_CLK periods (143 µs)
6: Wait for approx. 256 ADC_CLK periods (208 µs)
7: No additional waiting time before RX power-up
SEQUENCING[3:0] CS_WAIT[3:0] 10 - Waiting time for carrier sense from RX power-up
0: Wait 20 FILTER_CLK periods before power down
1: Wait 22 FILTER_CLK periods before power down
2: Wait 24 FILTER_CLK periods before power down
3: Wait 26 FILTER_CLK periods before power down
4: Wait 28 FILTER_CLK periods before power down
5: Wait 30 FILTER_CLK periods before power down
6: Wait 32 FILTER_CLK periods before power down
7: Wait 36 FILTER_CLK periods before power down
8: Wait 40 FILTER_CLK periods before power down
9: Wait 44 FILTER_CLK periods before power down
10: Wait 48 FILTER_CLK periods before power down
11: Wait 52 FILTER_CLK periods before power down
12: Wait 56 FILTER_CLK periods before power down
13: Wait 60 FILTER_CLK periods before power down
14: Wait 64 FILTER_CLK periods before power down
15: Wait 72 FILTER_CLK periods before power down
FREQ_2A Register (04h)
REGISTER NAME Default
value
Active Description
FREQ_2A[7:0] FREQ_A[22:15] 131 - 8 MSB of frequency control word A
FREQ_1A Register (05h)
REGISTER NAME Default
value
Active Description
FREQ_1A[7:0] FREQ_A[14:7] 177 - Bit 15 to 8 of frequency control word A
FREQ_0A Register (06h)
REGISTER NAME Default
value
Active Description
FREQ_0A[7:1] FREQ_A[6:0] 124 - 7 LSB of frequency control word A
FREQ_0A[0] DITHER_A 1 H Enable dithering for frequency A
CC1020
SWRS046E Page 70 of 89
CLOCK_A Register (07h)
REGISTER NAME Default
value
Active Description
CLOCK_A[7:5] REF_DIV_A[2:0] 2 - Reference frequency divisor (A):
0: Not supported
1: REF_CLK frequency = Crystal frequency / 2
…
7: REF_CLK frequency = Crystal frequency / 8
It is recommended to use the highest possible reference
clock frequency that allows the desired Baud rate.
CLOCK_A[4:2] MCLK_DIV1_A[2:0] 4 - Modem clock divider 1 (A):
0: Divide by 2.5
1: Divide by 3
2: Divide by 4
3: Divide by 7.5 (2.5·3)
4: Divide by 12.5 (2.5·5)
5: Divide by 40 (2.5·16)
6: Divide by 48 (3·16)
7: Divide by 64 (4·16)
CLOCK_A[1:0] MCLK_DIV2_A[1:0] 0 - Modem clock divider 2 (A):
0: Divide by 1
1: Divide by 2
2: Divide by 4
3: Divide by 8
MODEM_CLK frequency is FREF frequency divided by
the product of divider 1 and divider 2.
Baud rate is MODEM_CLK frequency divided by 8.
FREQ_2B Register (08h)
REGISTER NAME Default
value
Active Description
FREQ_2B[7:0] FREQ_B[22:15] 131 - 8 MSB of frequency control word B
FREQ_1B Register (09h)
REGISTER NAME Default
value
Active Description
FREQ_1B[7:0] FREQ_B[14:7] 189 - Bit 15 to 8 of frequency control word B
FREQ_0B Register (0Ah)
REGISTER NAME Default
value
Active Description
FREQ_0B[7:1] FREQ_B[6:0] 124 - 7 LSB of frequency control word B
FREQ_0B[0] DITHER_B 1 H Enable dithering for frequency B
CC1020
SWRS046E Page 71 of 89
CLOCK_B Register (0Bh)
REGISTER NAME Default
value
Active Description
CLOCK_B[7:5] REF_DIV_B[2:0] 2 - Reference frequency divisor (B):
0: Not supported
1: REF_CLK frequency = Crystal frequency / 2
…
7: REF_CLK frequency = Crystal frequency / 8
CLOCK_B[4:2] MCLK_DIV1_B[2:0] 4 - Modem clock divider 1 (B):
0: Divide by 2.5
1: Divide by 3
2: Divide by 4
3: Divide by 7.5 (2.5·3)
4: Divide by 12.5 (2.5·5)
5: Divide by 40 (2.5·16)
6: Divide by 48 (3·16)
7: Divide by 64 (4·16)
CLOCK_B[1:0] MCLK_DIV2_B[1:0] 0 - Modem clock divider 2 (B):
0: Divide by 1
1: Divide by 2
2: Divide by 4
3: Divide by 8
MODEM_CLK frequency is FREF frequency divided by
the product of divider 1 and divider 2.
Baud rate is MODEM_CLK frequency divided by 8.
VCO Register (0Ch)
REGISTER NAME Default
value
Active Description
VCO[7 :4] VCO_CURRENT_A[3:0] 8 - Control of current in VCO core for frequency A
0 : 1.4 mA current in VCO core
1 : 1.8 mA current in VCO core
2 : 2.1 mA current in VCO core
3 : 2.5 mA current in VCO core
4 : 2.8 mA current in VCO core
5 : 3.2 mA current in VCO core
6 : 3.5 mA current in VCO core
7 : 3.9 mA current in VCO core
8 : 4.2 mA current in VCO core
9 : 4.6 mA current in VCO core
10 : 4.9 mA current in VCO core
11 : 5.3 mA current in VCO core
12 : 5.6 mA current in VCO core
13 : 6.0 mA current in VCO core
14 : 6.4 mA current in VCO core
15 : 6.7 mA current in VCO core
Recommended setting: VCO_CURRENT_A=4
VCO[3:0] VCO_CURRENT_B[3:0] 8 - Control of current in VCO core for frequency B
The current steps are the same as for
VCO_CURRENT_A
Recommended setting: VCO_CURRENT_B=4
CC1020
SWRS046E Page 72 of 89
MODEM Register (0Dh)
REGISTER NAME Default
value
Active Description
MODEM[7] - 0 - Reserved, write 0
MODEM[6:4] ADC_DIV[2:0] 3 - ADC clock divisor
0: Not supported
1: ADC frequency = XOSC frequency / 4
2: ADC frequency = XOSC frequency / 6
3: ADC frequency = XOSC frequency / 8
4: ADC frequency = XOSC frequency / 10
5: ADC frequency = XOSC frequency / 12
6: ADC frequency = XOSC frequency / 14
7: ADC frequency = XOSC frequency / 16
Note that the intermediate frequency should be as close
to 307.2 kHz as possible. ADC clock frequency is always
4 times the intermediate frequency and should therefore
be as close to 1.2288 MHz as possible.
MODEM[3] - 0 - Reserved, write 0
MODEM[2] PN9_ENABLE 0 H Enable scrambling of TX and RX with PN9 pseudo-
random bit sequence
0: PN9 scrambling is disabled
1: PN9 scrambling is enabled (x9+x5+1)
The PN9 pseudo-random bit sequence can be used for
BER testing by only transmitting zeros, and then
counting the number of received ones.
MODEM[1:0] DATA_FORMAT[1:0] 0 - Modem data format
0 (00): NRZ operation
1 (01): Manchester operation
2 (10): Transparent asynchronous UART operation, set
DCLK=0
3 (11): Transparent asynchronous UART operation, set
DCLK=1
DEVIATION Register (0Eh)
REGISTER NAME Default
value
Active Description
DEVIATION[7] TX_SHAPING 1 H Enable Gaussian shaping of transmitted data
Recommended setting: TX_SHAPING=1
DEVIATION[6 :4] TXDEV_X[2 :0] 6 - Transmit frequency deviation exponent
DEVIATION [3 :0] TXDEV_M[3 :0] 8 - Transmit frequency deviation mantissa
Deviation in 402-470 MHz band:
FREF ·TXDEV_M ·2(TXDEV_X−16)
Deviation in 804-960 MHz band:
FREF ·TXDEV_M ·2(TXDEV_X−15)
On-off-keying (OOK) is used in RX/TX if TXDEV_M[3:0]=0
To find TXDEV_M given the deviation and TXDEV_X:
TXDEV_M = deviation·2(16−TXDEV_X)/FREF
in 402-470 MHz band,
TXDEV_M = deviation·2(15−TXDEV_X)/FREF
in 804-960 MHz band.
Decrease TXDEV_X and try again if TXDEV_M < 8.
Increase TXDEV_X and try again if TXDEV_M ≥ 16.
CC1020
SWRS046E Page 73 of 89
AFC_CONTROL Register (0Fh)
REGISTER NAME Default
value
Active Description
AFC_CONTROL[7:6] SETTLING[1:0] 2 - Controls AFC settling time versus accuracy
0: AFC off; zero average frequency is used in demodulator
1: Fastest settling; frequency averaged over 1 0/1 bit pair
2: Medium settling; frequency averaged over 2 0/1 bit pairs
3: Slowest settling; frequency averaged over 4 0/1 bit pairs
Recommended setting: AFC_CONTROL=3 for higher
accuracy unless it is essential to have the fastest settling
time when transmission starts after RX is activated.
AFC_CONTROL[5:4] RXDEV_X[1:0] 1 - RX frequency deviation exponent
AFC_CONTROL[3:0] RXDEV_M[3:0] 12 - RX frequency deviation mantissa
Expected RX deviation should be:
Baud rate · RXDEV_M ·2(RXDEV_X−3) / 3
To find RXDEV_M given the deviation and RXDEV_X:
RXDEV_M = 3 · deviation ·2(3−RXDEV_X) / Baud rate
Decrease RXDEV_X and try again if RXDEV_M<8.
Increase RXDEV_X and try again if RXDEV_M≥16.
Note: The RX frequency deviation should be close to half the TX frequency deviation for GFSK at 100
kBaud data rate and below. The RX frequency deviation should be close to the TX frequency deviation
for FSK and for GFSK at 100 kBaud data rate and above.
FILTER Register (10h)
REGISTER NAME Default
value
Active Description
FILTER[7] FILTER_BYPASS 0 H Bypass analog image rejection / anti-alias filter. Set to 1 for
increased dynamic range at high Baud rates.
Recommended setting:
FILTER_BYPASS=0 below 76.8 kBaud,
FILTER_BYPASS=1 for 76.8 kBaud and up.
FILTER[6:5] DEC_SHIFT[1:0] 0 - Number of extra bits to shift decimator input
(may improve filter accuracy and lower power consumption).
Recommended settings:
DEC_SHIFT=0 when DEC_DIV ≤1 (receiver channel bandwidth
≥ 153.6 kHz),
DEC_SHIFT=1 when optimized sensitivity and 1< DEC_DIV <
24 (12.29 kHz < receiver channel bandwidth < 153.6 kHz),
DEC_SHIFT=2 when optimized selectivity and DEC_DIV ≥ 24
(receiver channel bandwidth ≤12.29 kHz)
FILTER[4:0] DEC_DIV[4:0] 0 - Decimation clock divisor
0: Decimation clock divisor = 1, 307.2 kHz channel filter BW.
1: Decimation clock divisor = 2, 153.6 kHz channel filter BW.
…
30: Decimation clock divisor = 31, 9.91 kHz channel filter BW.
31: Decimation clock divisor = 32, 9.6 kHz channel filter BW.
Channel filter bandwidth is 307.2 kHz divided by the decimation
clock divisor.
CC1020
SWRS046E Page 74 of 89
VGA1 Register (11h)
REGISTER NAME Default
value
Active Description
VGA1[7 :6] CS_SET[1:0] 1 - Sets the number of consecutive samples at or above carrier
sense level before carrier sense is indicated (e.g. on LOCK
pin)
0: Set carrier sense after first sample at or above carrier sense
level
1: Set carrier sense after second sample at or above carrier
sense level
2: Set carrier sense after third sample at or above carrier
sense level
3: Set carrier sense after fourth sample at or above carrier
sense level
Increasing CS_SET reduces the number of “false” carrier
sense events due to noise at the expense of increased carrier
sense response time.
VGA1[5] CS_RESET 1 - Sets the number of consecutive samples below carrier sense
level before carrier sense indication (e.g. on lock pin) is reset
0: Carrier sense is reset after first sample below carrier sense
level
1: Carrier sense is reset after second sample below carrier
sense level
Recommended setting: CS_RESET=1 in order to reduce the
chance of losing carrier sense due to noise.
VGA1[4 :2] VGA_WAIT[2 :0]
1 - Controls how long AGC, bit synchronization, AFC and RSSI
levels are frozen after VGA gain is changed when frequency is
changed between A and B or PLL has been out of lock or after
RX power-up
0: Freeze operation for 16 filter clocks, 8/(filter BW) seconds
1: Freeze operation for 20 filter clocks, 10/(filter BW) seconds
2: Freeze operation for 24 filter clocks, 12/(filter BW) seconds
3: Freeze operation for 28 filter clocks, 14/(filter BW) seconds
4: Freeze operation for 32 filter clocks, 16/(filter BW) seconds
5: Freeze operation for 40 filter clocks, 20/(filter BW) seconds
6: Freeze operation for 48 filter clocks, 24/(filter BW) seconds
7: Freeze present levels unconditionally
VGA1[1:0] VGA_FREEZE[1:0] 1 - Controls the additional time AGC, bit synchronization, AFC
and RSSI levels are frozen when frequency is changed
between A and B or PLL has been out of lock or after RX
power-up
0: Freeze levels for approx. 16 ADC_CLK periods (13 µs)
1: Freeze levels for approx. 32 ADC_CLK periods (26 µs)
2: Freeze levels for approx. 64 ADC_CLK periods (52 µs)
3: Freeze levels for approx. 128 ADC_CLK periods (104 µs)
CC1020
SWRS046E Page 75 of 89
VGA2 Register (12h)
REGISTER NAME Default
value
Active Description
VGA2[7] LNA2_MIN 0 - Minimum LNA2 setting used in VGA
0: Minimum LNA2 gain
1: Medium LNA2 gain
Recommended setting: LNA2_MIN=0 for best selectivity.
VGA2[6] LNA2_MAX 1 - Maximum LNA2 setting used in VGA
0: Medium LNA2 gain
1: Maximum LNA2 gain
Recommended setting: LNA2_MAX=1 for best sensitivity.
VGA2[5:4] LNA2_SETTING[1:0]
3 - Selects at what VGA setting the LNA gain should be
changed
0: Apply LNA2 change below min. VGA setting.
1: Apply LNA2 change at approx. 1/3 VGA setting (around
VGA setting 10).
2: Apply LNA2 change at approx. 2/3 VGA setting (around
VGA setting 19).
3: Apply LNA2 change above max. VGA setting.
Recommended setting:
LNA2_SETTING=0 if VGA_SETTING<10,
LNA2_SETTING=1 otherwise.
If LNA2_MIN=1 and LNA2_MAX=0, then the LNA2 setting is
controlled by LNA2_SETTING:
0: Between medium and maximum LNA2 gain
1: Minimum LNA2 gain
2: Medium LNA2 gain
3: Maximum LNA2 gain
VGA2[3] AGC_DISABLE 0 H Disable AGC
0: AGC is enabled
1: AGC is disabled (VGA_SETTING determines VGA gain)
Recommended setting: AGC_DISABLE=0 for good dynamic
range.
VGA2[2] AGC_HYSTERESIS
1 H Enable AGC hysteresis
0: No hysteresis. Immediate gain change for smallest
up/down step
1: Hysteresis enabled. Two samples in a row must indicate
gain change for smallest up/down step
Recommended setting: AGC_HYSTERESIS=1.
VGA2[1:0] AGC_AVG[1:0] 1 - Sets how many samples that are used to calculate average
output magnitude for AGC/RSSI.
0: Magnitude is averaged over 2 filter output samples
1: Magnitude is averaged over 4 filter output samples
2: Magnitude is averaged over 8 filter output samples
3: Magnitude is averaged over 16 filter output samples
Recommended setting: AGC_AVG=1.
For best AGC/RSSI accuracy AGC_AVG=3.
For automatic power-up sequencing, the AGC_AVG and
CS_SET values must be chosen so that carrier sense is
available in time to be detected before the chip re-enters
power-down.
CC1020
SWRS046E Page 76 of 89
VGA3 Register (13h)
REGISTER NAME Default
value
Active Description
VGA3[7 :5] VGA_DOWN[2:0] 1 - Decides how much the signal strength must be above
CS_LEVEL+VGA_UP before VGA gain is decreased. Based
on the calculated internal strength level, which has an LSB
resolution of 1.5 dB.
0: Gain is decreased when level is above CS_LEVEL+ 8 +
VGA_UP + 3
1: Gain is decreased when level is above CS_LEVEL+ 8 +
VGA_UP + 4
…
6: Gain is decreased when level is above CS_LEVEL+ 8 +
VGA_UP + 9
7: Gain is decreased when level is above CS_LEVEL+ 8 +
VGA_UP + 10
See Figure 18 on page 38 for an explanation of the
relationship between RSSI, AGC and carrier sense settings.
VGA3[4:0] VGA_SETTING[4:0] 24 H VGA setting to be used when receive chain is turned on
This is also the maximum gain that the AGC is allowed to use.
See Figure 18 on page 38 for an explanation of the
relationship between RSSI, AGC and carrier sense settings.
VGA4 Register (14h)
REGISTER NAME Default
value
Active Description
VGA4[7 :5] VGA_UP[2:0] 1 - Decides the level where VGA gain is increased if it is not
already at the maximum set by VGA_SETTING. Based on the
calculated internal strength level, which has an LSB resolution
of 1.5 dB.
0: Gain is increased when signal is below CS_LEVEL + 8
1: Gain is increased when signal is below CS_LEVEL+ 8 + 1
…
6: Gain is increased when signal is below CS_LEVEL+ 8 + 6
7: Gain is increased when signal below CS_LEVEL+ 8 + 7
See Figure 18 on page 38 for an explanation of the
relationship between RSSI, AGC and carrier sense settings.
VGA4[4:0] CS_LEVEL[4:0] 24 H Reference level for Received Signal Strength Indication
(carrier sense level) and AGC.
See Figure 18 on page 38 for an explanation of the
relationship between RSSI, AGC and carrier sense settings.
CC1020
SWRS046E Page 77 of 89
LOCK Register (15h)
REGISTER NAME Default
value
Active Description
LOCK[7:4] LOCK_SELECT[3:0] 0 - Selection of signals to LOCK pin
0: Set to 0
1: Set to 1
2: LOCK_CONTINUOUS (active low)
3: LOCK_INSTANT (active low)
4: CARRIER_SENSE (RSSI above threshold, active low)
5: CAL_COMPLETE (active low)
6: SEQ_ERROR (active low)
7: FXOSC
8: REF_CLK
9: FILTER_CLK
10: DEC_CLK
11: PRE_CLK
12: DS_CLK
13: MODEM_CLK
14: VCO_CAL_COMP
15: F_COMP
LOCK[3] WINDOW_WIDTH 0 - Selects lock window width
0: Lock window is 2 prescaler clock cycles wide
1: Lock window is 4 prescaler clock cycles wide
Recommended setting: WINDOW_WIDTH=0.
LOCK[2] LOCK_MODE 0 - Selects lock detector mode
0: Counter restart mode
1: Up/Down counter mode
Recommended setting: LOCK_MODE=0.
LOCK[1:0] LOCK_ACCURACY[1:0] 0 - Selects lock accuracy (counter threshold values)
0: Declare lock at counter value 127, out of lock at value 111
1: Declare lock at counter value 255, out of lock at value 239
2: Declare lock at counter value 511, out of lock at value 495
3: Declare lock at counter value 1023, out of lock at value
1007
Note: Set LOCK_SELECT=2 to use the LOCK pin as a lock indicator.
CC1020
SWRS046E Page 78 of 89
FRONTEND Register (16h)
REGISTER NAME Default
value
Active Description
FRONTEND[7 :6] LNAMIX_CURRENT[1:0] 2 - Controls current in LNA, LNA2 and mixer
Recommended setting: LNAMIX_CURRENT=1
FRONTEND[5 :4] LNA_CURRENT[1 :0] 1 - Controls current in the LNA
Recommended setting: LNA_CURRENT=3.
Can be lowered to save power at the expense of
reduced sensitivity.
FRONTEND[3] MIX_CURRENT 0 - Controls current in the mixer
Recommended setting:
MIX_CURRENT=1 at 426-464 MHz,
MIX_CURRENT=0 at 852-928 MHz.
FRONTEND[2] LNA2_CURRENT 0 - Controls current in LNA 2
Recommended settings:
LNA2_CURRENT=0 at 426-464 MHz,
LNA2_CURRENT=1 at 852-928 MHz.
FRONTEND[1] SDC_CURRENT 0 - Controls current in the single-to-diff. Converter
Recommended settings:
SDC_CURRENT=0 at 426-464 MHz,
SDC_CURRENT=1 at 852-928 MHz.
FRONTEND[0] LNAMIX_BIAS 1 - Controls how front-end bias currents are generated
0: Constant current biasing
1: Constant Gm·R biasing (reduces gain variation)
Recommended setting: LNAMIX_BIAS=0.
CC1020
SWRS046E Page 79 of 89
ANALOG Register (17h)
REGISTER NAME Default
value
Active Description
ANALOG[7] BANDSELECT 1 - Frequency band selection
0: 402-470 MHz band
1: 804-960 MHz band
ANALOG[6] LO_DC 1 - Lower LO DC level to mixers
0: High LO DC level to mixers
1: Low LO DC level to mixers
Recommended settings:
LO_DC=1 for 402-470 MHz,
LO_DC=0 for 804-960 MHz.
ANALOG[5] VGA_BLANKING 1 H Enable analog blanking switches in VGA when
changing VGA gain.
0: Blanking switches are disabled
1: Blanking switches are turned on for approx.
0.8µs when gain is changed (always on if
AGC_DISABLE=1)
Recommended setting: VGA_BLANKING=0.
ANALOG[4] PD_LONG 0 H Selects short or long reset delay in phase
detector
0: Short reset delay
1: Long reset delay
Recommended setting: PD_LONG=0.
ANALOG[3] - 0 - Reserved, write 0
ANALOG[2] PA_BOOST 0 H Boost PA bias current for higher output power
Recommended setting: PA_BOOST=1.
ANALOG[1:0]
DIV_BUFF_CURRENT[1:0] 3 - Overall bias current adjustment for VCO divider
and buffers
0: 4/6 of nominal VCO divider and buffer current
1: 4/5 of nominal VCO divider and buffer current
2: Nominal VCO divider and buffer current
3: 4/3 of nominal VCO divider and buffer current
Recommended setting:
DIV_BUFF_CURRENT=3
BUFF_SWING Register (18h)
REGISTER NAME Default
value
Active Description
BUFF_SWING[7:6] PRE_SWING[1:0] 3 - Prescaler swing.
0: 2/3 of nominal swing
1: 1/2 of nominal swing
2: 4/3 of nominal swing
3: Nominal swing
Recommended setting: PRE_SWING=0.
BUFF_SWING[5:3] RX_SWING[2:0] 4 - LO buffer swing, in RX (to mixers)
0: Smallest load resistance (smallest swing)
…
7: Largest load resistance (largest swing)
Recommended setting: RX_SWING=2.
BUFF_SWING[2:0] TX_SWING[2:0] 1 - LO buffer swing, in TX (to power amplifier driver)
0: Smallest load resistance (smallest swing)
…
7: Largest load resistance (largest swing)
Recommended settings:
TX_SWING=4 for 402-470 MHz,
TX_SWING=0 for 804-960 MHz.
CC1020
SWRS046E Page 80 of 89
BUFF_CURRENT Register (19h)
REGISTER NAME Default
value
Active Description
BUFF_CURRENT[7:6] PRE_CURRENT[1:0] 1 - Prescaler current scaling
0: Nominal current
1: 2/3 of nominal current
2: 1/2 of nominal current
3: 2/5 of nominal current
Recommended setting: PRE_CURRENT=0.
BUFF_CURRENT[5:3] RX_CURRENT[2:0] 4 - LO buffer current, in RX (to mixers)
0: Minimum buffer current
…
7: Maximum buffer current
Recommended setting: RX_CURRENT=4.
BUFF_CURRENT[2:0] TX_CURRENT[2:0] 5 - LO buffer current, in TX (to PA driver)
0: Minimum buffer current
…
7: Maximum buffer current
Recommended settings:
TX_CURRENT=2 for 402-470 MHz,
TX_CURRENT=5 for 804-960 MHz.
PLL_BW Register (1Ah)
REGISTER NAME Default
value
Active Description
PLL_BW[7:0] PLL_BW[7:0] 134 - Charge pump current scaling/rounding factor.
Used to calibrate charge pump current for the
desired PLL loop bandwidth. The value is given by:
PLL_BW = 174 + 16 log2(fref/7.126) where fref is the
reference frequency in MHz.
CALIBRATE Register (1Bh)
REGISTER NAME Default
value
Active Description
CALIBRATE[7] CAL_START 0 ↑ ↑ 1: Calibration started
0: Calibration inactive
CALIBRATE[6] CAL_DUAL 0 H Use calibration results for both frequency A and B
0: Store results in A or B defined by F_REG (MAIN[6])
1: Store calibration results in both A and B
CALIBRATE[5:4] CAL_WAIT[1:0] 0 - Selects calibration wait time (affects accuracy)
0 (00): Calibration time is approx. 90000 F_REF periods
1 (01): Calibration time is approx. 110000 F_REF periods
2 (10): Calibration time is approx. 130000 F_REF periods
3 (11): Calibration time is approx. 200000 F_REF periods
Recommended setting: CAL_WAIT=3 for best accuracy in
calibrated PLL loop filter bandwidth.
CALIBRATE[3] - 0 - Reserved, write 0
CALIBRATE[2:0] CAL_ITERATE[2:0] 5 - Iteration start value for calibration DAC
0 (000): DAC start value 1, VC<0.49 V after calibration
1 (001): DAC start value 2, VC<0.66 V after calibration
2 (010): DAC start value 3, VC<0.82 V after calibration
3 (011): DAC start value 4, VC<0.99 V after calibration
4 (100): DAC start value 5, VC<1.15 V after calibration
5 (101): DAC start value 6, VC<1.32 V after calibration
6 (110): DAC start value 7, VC<1.48 V after calibration
7 (111): DAC start value 8, VC<1.65 V after calibration
Recommended setting: CAL_ITERATE=4.
CC1020
SWRS046E Page 81 of 89
PA_POWER Register (1Ch)
REGISTER NAME Default
value
Active Description
PA_POWER[7:4] PA_HIGH [3:0] 0 - Controls output power in high-power array
0: High-power array is off
1: Minimum high-power array output power
…
15: Maximum high-power array output power
PA_POWER[3:0] PA_LOW[3:0] 15 - Controls output power in low-power array
0: Low-power array is off
1: Minimum low-power array output power
…
15: Maximum low-power array output power
It is more efficient in terms of current consumption to use
either the lower or upper 4-bits in the PA_POWER
register to control the power.
MATCH Register (1Dh)
REGISTER NAME Default value Active Description
MATCH[7:4] RX_MATCH[3:0] 0 - Selects matching capacitor array value for RX. Each
step is approximately 0.4 pF.
MATCH[3:0] TX_MATCH[3:0] 0 - Selects matching capacitor array value for TX.
Each step is approximately 0.4 pF.
PHASE_COMP Register (1Eh)
REGISTER NAME Default
value
Active Description
PHASE_COMP[7:0] PHASE_COMP[7:0] 0 - Signed compensation value for LO I/Q phase error.
Used for image rejection calibration.
−128: approx. −6.2° adjustment between I and Q phase
−1: approx. −0.02° adjustment between I and Q phase
0: approx. +0.02° adjustment between I and Q phase
127: approx. +6.2° adjustment between I and Q phase
GAIN_COMP Register (1Fh)
REGISTER NAME Default
value
Active Description
GAIN_COMP[7:0] GAIN_COMP[7:0] 0 - Signed compensation value for mixer I/Q gain error. Used
for image rejection calibration.
−128: approx. −1.16 dB adjustment between I and Q gain
−1: approx. −0.004 dB adjustment between I and Q gain
0: approx. +0.004 dB adjustment between I and Q gain
127: approx. +1.16 dB adjustment between I and Q gain
POWERDOWN Register (20h)
REGISTER NAME Default
value
Active Description
POWERDOWN[7] PA_PD 0 H Sets PA in power-down when PD_MODE[1:0]=2
POWERDOWN[6] VCO_PD 0 H Sets VCO in power-down when PD_MODE[1:0]=2
POWERDOWN[5] BUFF_PD 0 H Sets VCO divider, LO buffers and prescaler in power-down
when PD_MODE[1:0]=2
POWERDOWN[4] CHP_PD 0 H Sets charge pump in power-down when PD_MODE[1:0]=2
POWERDOWN[3] LNAMIX_PD 0 H Sets LNA/mixer in power-down when PD_MODE[1:0]=2
POWERDOWN[2] VGA_PD 0 H Sets VGA in power-down when PD_MODE[1:0]=2
POWERDOWN[1] FILTER_PD 0 H Sets image filter in power-down when PD_MODE[1:0]=2
POWERDOWN[0] ADC_PD 0 H Sets ADC in power-down when PD_MODE[1:0]=2
CC1020
SWRS046E Page 82 of 89
TEST1 Register (21h, for test only)
REGISTER NAME Default
value
Active Description
TEST1[7:4] CAL_DAC_OPEN[3:0] 4 - Calibration DAC override value, active when
BREAK_LOOP=1
TEST1[3:0] CHP_CO[3:0] 13 - Charge pump current override value
TEST2 Register (22h, for test only)
REGISTER NAME Default
value
Active Description
TEST2[7] BREAK_LOOP 0 H 0: PLL loop closed
1: PLL loop open
TEST2[6] CHP_OVERRIDE 0 H 0: use calibrated value
1: use CHP_CO[3:0] value
TEST2[5] VCO_OVERRIDE 0 H 0: use calibrated value
1: use VCO_AO[4:0] value
TEST2[4:0] VCO_AO[4:0] 16 - VCO_ARRAY override value
TEST3 Register (23h, for test only)
REGISTER NAME Default
value
Active Description
TEST3[7] VCO_CAL_MANUAL 0 H Enables “manual” VCO calibration (test only)
TEST3[6] VCO_CAL_OVERRIDE 0 H Override VCO current calibration
0: Use calibrated value
1: Use VCO_CO[5:0] value
VCO_CAL_OVERRIDE controls VCO_CAL_CLK if
VCO_CAL_MANUAL=1. Negative transitions are then
used to sample VCO_CAL_COMP.
TEST3[5:0] VCO_CO[5:0] 6 - VCO_CAL_CURRENT override value
TEST4 Register (24h, for test only)
REGISTER NAME Default
value
Active Description
TEST4[7] CHP_DISABLE 0 H Disable normal charge pump operation
TEST4[6] CHP_TEST_UP 0 H Force charge pump to output “up” current
TEST4[5] CHP_TEST_DN 0 H Force charge pump to output “down” current
TEST4[4:3] TM_IQ[1:0] 0 - Value of differential I and Q outputs from mixer when
TM_ENABLE=1
0: I output negative, Q output negative
1: I output negative, Q output positive
2: I output positive, Q output negative
3: I output positive, Q output positive
TEST4[2] TM_ENABLE 0 H Enable DC control of mixer output (for testing)
TEST4[1] TF_ENABLE 0 H Connect analog test module to filter inputs
TEST4[0] TA_ENABLE 0 H Connect analog test module to ADC inputs
If TF_ENABLE=1 or TA_ENABLE=1 in TEST4 register, then INTERFACE[3:0] controls analog test
module: INTERFACE[3] = TEST_PD, INTERFACE[2:0] = TEST_MODE[2:0]. Otherwise, TEST_PD=1
and TEST_MODE[2]=1.
TEST5 Register (25h, for test only)
REGISTER NAME Default
value
Active Description
TEST5[7] F_COMP_ENABLE 0 H Enable frequency comparator output F_COMP from
phase detector
TEST5[6] SET_DITHER_CLOCK 1 H Enable dithering of delta-sigma clock
TEST5[5] ADC_TEST_OUT 0 H Outputs ADC samples on LOCK and DIO, while
ADC_CLK is output on DCLK
TEST5[4] CHOP_DISABLE 0 H Disable chopping in ADC integrators
TEST5[3] SHAPING_DISABLE 0 H Disable ADC feedback mismatch shaping
TEST5[2] VCM_ROT_DISABLE 0 H Disable rotation for VCM mismatch shaping
TEST5[1:0] ADC_ROTATE[1:0] 0 - Control ADC input rotation
0: Rotate in 00 01 10 11 sequence
1: Rotate in 00 10 11 01 sequence
2: Always use 00 position
3: Rotate in 00 10 00 10 sequence
CC1020
SWRS046E Page 83 of 89
TEST6 Register (26h, for test only)
REGISTER NAME Default
value
Active Description
TEST6[7:4] - 0 - Reserved, write 0
TEST6[3] VGA_OVERRIDE 0 - Override VGA settings
TEST6[2] AC1O 0 - Override value to first AC coupler in VGA
0: Approx. 0 dB gain
1: Approx. −12 dB gain
TEST6[1:0] AC2O[1:0] 0 - Override value to second AC coupler in VGA
0: Approx. 0 dB gain
1: Approx. −3 dB gain
2: Approx. −12 dB gain
3: Approx. −15 dB gain
TEST7 Register (27h, for test only)
REGISTER NAME Default
value
Active Description
TEST7[7:6] - 0 - Reserved, write 0
TEST7[5:4] VGA1O[1:0] 0 - Override value to VGA stage 1
TEST7[3:2] VGA2O[1:0] 0 - Override value to VGA stage 2
TEST7[1:0] VGA3O[1:0] 0 - Override value to VGA stage 3
STATUS Register (40h, read only)
REGISTER NAME Default
value
Active Description
STATUS[7] CAL_COMPLETE - H Set to 0 when PLL calibration starts, and set to 1 when
calibration has finished
STATUS[6] SEQ_ERROR - H Set to 1 when PLL failed to lock during automatic power-
up sequencing
STATUS[5] LOCK_INSTANT - H Instantaneous PLL lock indicator
STATUS[4] LOCK_CONTINUOUS - H PLL lock indicator, as defined by LOCK_ACCURACY.
Set to 1 when PLL is in lock
STATUS[3] CARRIER_SENSE - H Carrier sense when RSSI is above CS_LEVEL
STATUS[2] LOCK - H Logical level on LOCK pin
STATUS[1] DCLK - H Logical level on DCLK pin
STATUS[0] DIO - H Logical level on DIO pin
RESET_DONE Register (41h, read only)
REGISTER NAME Default
value
Active Description
RESET_DONE[7] ADC_RESET_DONE - H Reset of ADC control logic done
RESET_DONE[6] AGC_RESET_DONE - H Reset of AGC (VGA control) logic done
RESET_DONE[5] GAUSS_RESET_DONE - H Reset of Gaussian data filter done
RESET_DONE[4] AFC_RESET_DONE - H Reset of AFC / FSK decision level logic done
RESET_DONE[3] BITSYNC_RESET_DONE - H Reset of modulator, bit synchronization logic
and PN9 PRBS generator done
RESET_DONE[2] SYNTH_RESET_DONE - H Reset digital part of frequency synthesizer
done
RESET_DONE[1] SEQ_RESET_DONE - H Reset of power-up sequencing logic done
RESET_DONE[0] CAL_LOCK_RESET_DONE - H Reset of calibration logic and lock detector
done
RSSI Register (42h, read only)
REGISTER NAME Default
value
Active Description
RSSI[7] - - - Not in use, will read 0
RSSI[6:0] RSSI[6:0] - - Received signal strength indicator.
The relative power is given by RSSI x 1.5 dB in a logarithmic
scale.
The VGA gain set by VGA_SETTING must be taken into
account. See section 12.5 for more details.
CC1020
SWRS046E Page 84 of 89
AFC Register (43h, read only)
REGISTER NAME Default
value
Active Description
AFC[7 :0] AFC[7:0] - - Average received frequency deviation from IF. This 8-bit 2-
complement signed value equals the demodulator decision level
and can be used for AFC. The average frequency offset from the
IF frequency is ∆F = Baud rate · AFC / 16
GAUSS_FILTER Register (44h)
REGISTER NAME Default
value
Active Description
GAUSS_FILTER[7 :0] GAUSS_FILTER[7:0] - - Readout of instantaneous IF frequency offset
from nominal IF. Signed 8-bit value.
∆F = Baud rate · GAUSS_FILTER / 8
STATUS1 Register (45h, for test only)
REGISTER NAME Default
value
Active Description
STATUS1[7:4] CAL_DAC[3:0] - - Status vector defining applied Calibration DAC value
STATUS1[3:0] CHP_CURRENT[3:0] - - Status vector defining applied CHP_CURRENT value
STATUS2 Register (46h, for test only)
REGISTER NAME Default
value
Active Description
STATUS2[7 :5] CC1020_VERSION[2 :0] - - CC1020 version code :
0 : Pre-production version
1: First production version
2-7: Reserved for future use
STATUS2[4:0] VCO_ARRAY[4:0] - - Status vector defining applied VCO_ARRAY
value
STATUS3 Register (47h, for test only)
REGISTER NAME Default
value
Active Description
STATUS3[7] F_COMP - - Frequency comparator output from phase
detector
STATUS3[6] VCO_CAL_COMP - - Readout of VCO current calibration comparator.
Equals 1 if current defined by
VCO_CURRENT_A/B is larger than the VCO
core current
STATUS3[5:0] VCO_CAL_CURRENT[5:0] - - Status vector defining applied
VCO_CAL_CURRENT value
STATUS4 Register (48h, for test only)
REGISTER NAME Default
value
Active Description
STATUS4[7:6] ADC_MIX[1:0] - - Readout of mixer input to ADC
STATUS4[5:3] ADC_I[2:0] - - Readout of ADC “I” output
STATUS4[2:0] ADC_Q[2:0] - - Readout of ADC “Q” output
STATUS5 Register (49h, for test only)
REGISTER NAME Default
value
Active Description
STATUS5[7:0] FILTER_I[7:0] - - Upper bits of “I” output from channel filter
STATUS6 Register (4Ah, for test only)
REGISTER NAME Default
value
Active Description
STATUS6[7 :0] FILTER_Q[7 :0] - - Upper bits of “Q” output from channel filter
CC1020
SWRS046E Page 85 of 89
STATUS7 Register (4Bh, for test only)
REGISTER NAME Default
value
Active Description
STATUS7[7:5] - - - Not in use, will read 0
STATUS7[4:0] VGA_GAIN_OFFSET[4:0] - - Readout of offset between VGA_SETTING and
actual VGA gain set by AGC
CC1020
SWRS046E Page 86 of 89
27. Package Marking
When contacting technical support with a chip-related question, please state the entire
marking information as shown below.
CC1020
TI YMG
MLLL G4
o – pin one symbolization
TI – TI letters
YM – Year Month Date Code
GMLLL – Assy Lot Code
G4 – fixed code
28. Soldering Information
The recommendations for lead-free reflow in IPC/JEDEC J-STD-020 should be followed.
29. Plastic Tube Specification
Description: MAGAZINE, 7X7 QFN
Tube Specification
Device Package Tube Width Tube Length Units per Tube
CC1020RUZ QFN 32 8.91 mm 381 mm 52
CC1020
SWRS046E Page 87 of 89
30. Ordering Information
Orderable
Device
Status
(1) Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan (2) Lead
Finish
MSL Peak
Temp (3)
CC1020RUZ Active QFN RUZ 32 2080 Green (RoHS &
no Sb/Br)
Cu NiPdAu LEVEL3-260C
1 YEAR
CC1020RUZR Active QFN RUZ 32 2500 Green (RoHS &
no Sb/Br)
Cu NiPdAu LEVEL3-260C
1 YEAR
Orderable Evaluation Module Description Minimum Order Quantity
CC1020_1070DK-433 CC1020/1070 Development Kit, 433 MHz
1
CC1020_1070DK-868/915 CC1020/1070 Development Kit, 868/915 MHz
1
CC1020
SWRS046E Page 88 of 89
31. General Information
Document Revision History
Revision Date Description/Changes
1.4 November 2003 New improved image calibration routine.
Changes to preamble length and synchronization word for improved packet
error rate.
Included plot of blocking/selectivity.
Included data on PA_EN and LNA_EN pin drive.
Changes to Digital FM.
Changes to some of the electrical specification parameters.
1.5 February 2004 Included data for intermodulation rejection
Changed “channel width” to “channel spacing”
Maximum power down current increased from 1 uA to 1.8 uA.
Update on preamble length and synchronization word for improved packet
error rate.
1.6 December 2004 The various sections have been reorganized to improve readability
Added chapter numbering
Reorganized electrical specification section
Electrical specifications updated
Changes to sensitivity figures
Changes to TX spurious emission and harmonics figures
Changes to ACP figure at 868 MHz operation
Changes to current consumption figures in RX and TX mode and crystal
oscillator, bias and synthesizer mode
Changes to noise figure
Updates to section on input / output matching
Updates to section on VCO and PLL self-calibration
Updates to section on VCO, charge pump and PLL loop filter
Updates to section on receiver channel filter bandwidth
Updates to section on RSSI
Updates to section on image rejection calibration
Updates to section on preamble length and sync word
Description of OOK modulation and demodulation merged into one section
New bill of materials for operation at 433 MHz and 868/915 MHz
Added recommended PCB footprint for package (QFN 32)
Added information that there should be no via at “pin #1 corner” (section 27.1)
Added list of abbreviations
Changes to ordering information
1.7 October 2005 RSSI dynamic range changed from 63 dB to 55 dB
Recommended CAL_ITERATE changed from 5 to 4
PLL timeout in “Automatic power-up sequencing flow chart” changed from
1024 filter clocks to 127 filter clocks
Calibration routine flow chart changed in accordance to CC1020 Errata Note
004
Added chapter on TX data latency
1.8 January 2006 Updates to Ordering Information and Address Information
SWRS046A November 2007 Main reason for update was that some of the symbols in the data sheet were
garbled.
The drill diameter for the vias underneath the die attached pad changed from
14 mil to 10 mil.
The spurious reception parameter changed from Max 40 dB to Min 40 dB.
SWRS046B July 2008 Updated Plastic Tube specification, Carrier Tape and Reel specification to
reflect new MOQ quantities.
SWRS046C February 2009 Package Description changed to reflect CC1020RUZ in compliance with
PCN20081216001.
Package Marking changed in compliance with PCN20081216001.
Package Thermal Properties removed to align with general TI datasheets
Plastic Tube Specification: added device CC1020RUZ and changed tube
width to reflect CC1020RUZ in compliance with PCN20081216001.
Carrier Tape and Reel Specification: added device CC1020RUZR
Ordering Information: changed device orderable names to CC1020RUZ and
CC1020RUZR in compliance with PCN20081216001.
Added important information and disclaimer
Product Status Definition: removed
Carrier Tape and Reel Specification is removed, since this was duplicate
information to Tape And Reel Information
CC1020
SWRS046E Page 89 of 89
Revision Date Description/Changes
SWRS046D September 2009 Added reference to Application Note AN070 CC1020 Automatic Power-Up
Sequencing.
Interchanged XOSC_Q1 and XOSC_Q2 in figure 33 to reflect the reference
design.
Increased maximum RF frequency from 940 MHz to 960 MHz.
Added reference to ARIB STD-T96.
Updated Package Marking in Section 27.1
SWRS046E January 2010 Chapter on Package Drawing and chapter on Recommended PCB Footprint
for Package removed from data sheet since this was duplicate information
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
CC1020RUZR VQFN RUZ 32 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Apr-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CC1020RUZR VQFN RUZ 32 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Apr-2009
Pack Materials-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CC1020RUZR VQFN RUZ 32 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Feb-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CC1020RUZR VQFN RUZ 32 2500 336.6 336.6 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Feb-2012
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic."Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP®Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
TI E2E Community Home Page e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright ©2012, Texas Instruments Incorporated
