AK4359VF - Asahi Kasei Corporation

[AK4359]

MS0289-E-03 2011/02

- 1 -

GENERAL DESCRIPTION

The AK4359 is eight channels 24bit DAC corresponding to digital audio system. Using AKM's advanced

multi bit architecture for its modulator the AK4359 delivers a wide dynamic range while preserving linearity

for improved THD+N performance. The AK4359 has single end SCF outputs, increasing performance for

systems with excessive clock jitter. The AK4359 accepts 192kHz PCM data, ideal for a wide range of

applications including DVD-Audio.

FEATURES

 Sampling Rate Ranging from 8kHz to 192kHz

 24Bit 8 times Digital Filter with Slow roll-off option

 THD+N: -94dB

 DR, S/N: 106dB

 High Tolerance to Clock Jitter

 Single Ended Output Buffer with 2nd order Analog LPF

 Digital De-emphasis for 32, 44.1 & 48kHz sampling

 Zero Detect function

 Channel Independent Digital Attenuator (Linear 256 steps)

 3-wire Serial and I2C Bus μP I/F for mode setting

 I/F format: MSB justified, LSB justified (16bit, 20bit, 24bit), I2S, TDM

 Master clock: 256fs, 384fs, 512fs or 768fs or 1152fs (Normal Speed Mode)

128fs, 192fs, 256fs or 384fs (Double Speed Mode)

128fs or 192fs (Quad Speed Mode)

 Power Supply: 4.5 to 5.5V

 30pin VSOP Package

SCF DAC DATT

DZF

LOUT1

SCF DAC DATT

ROUT1

SCF DAC DATT

LOUT2

SCF DAC DATT

ROUT2

SCF DAC DATT

LOUT3

SCF DAC DATT

ROUT3

Audio

I/F

Control

Register

AK4359

MCLK

LRCK

BICK

3-wire

or I2C

SDTI1

SDTI2

SDTI3

PCM

SCF DAC DATT

LOUT4

SCF DAC DATT

ROUT4

SDTI4

LPF

106dB 192kHz 24-Bit 8ch DAC

AK4359

[AK4359]

MS0289-E-03 2011/02

- 2 -

■ Ordering Guide

AK4359VF -40 ∼ +85°C 30pin VSOP

AKD4359 Evaluation Board for AK4359

■ Pin Layout

6

5

4

3

2

1 MCLK

BICK

LRCK

SDTI1

RSTB

SMUTE/CSN/CAD0

7

DIF0/CDTI/SDA 8

DZF1

DZF2

AVDD

AVSS

VCOM

LOUT1

ROUT1

P/S

AK4359

Top

View

10

9 SDTI2

SDTI3

SDTI4 11

DIF1 12

LOUT2

ROUT2

LOUT3

ROUT3

25

26

27

28

29

30

24

23

21

22

20

19

ACKS/CCLK/SCL

DEM0 13

DVDD 14

LOUT4

ROUT4

18

17

DVSS 15 DEM1/I2C 16

[AK4359]

MS0289-E-03 2011/02

- 3 -

■ Compatibility with AK4384

1. Function

Functions AK4384 AK4359

# of channels 2 8

I2C Not available Available

DEM control Register Pin/Register

16/20bit LSB ju stified format

control Register Pin/Register

2. Pin Configuration

AK4359 AK4384 Pin# Pin# AK4384 AK4359

MCLK MCLK 1 30 DZFL DZF1

BICK BICK 2 29 DZFR DZF2

SDTI1 SDTI 3 28 VDD AVDD

LRCK LRCK 4 27 VSS AVSS

RSTB PDN 5 26 VCOM VCOM

SMUTE/CSN/CAD0 SMUTE/CSN 6 25 AOUTL LOUT1

ACKS/CCLK/SCL ACKS/CCLK 7 24 AOUTR ROUT1

DIF0/CDTI/SDA DIF0/CDTI 8 23 P/S P/S

SDTI2 9 22 LOUT2

SDTI3 10 21 ROUT2

SDTI4 11 20 LOUT3

DIF1 12 19 ROUT3

DEM0 13 18 LOUT4

DVDD 14 17 ROUT4

DVSS 15 16 I2C/DEM1

3. Register map

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

00H Control 1 ACKS TDM1 TDM0 DIF2 DIF1 DIF0 PW1 RSTN

01H Control 2 0 0 SLOW DFS1 DFS0 DEM1 DEM0 SMUTE

02H Control 3 PW4 PW3 PW2 0 0 DZFB 0 0

03H LOUT1 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0

04H ROUT1 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0

05H LOUT2 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0

06H ROUT2 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0

07H LOUT3 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0

08H ROUT3 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0

09H LOUT4 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0

0AH ROUT4 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0

0BH Invert Output Signal INVL1 INVR1 INVL2 INVR2 INVL3 INVR3 INVL4 INVR4

0CH DZF1 Control L1 R1 L2 R2 L3 R3 L4 R4

0DH DZF2 Control L1 R1 L2 R2 L3 R3 L4 R4

0EH DEM Control 0 0 0 0 DEMA DEMB DEMC DEMD

: Compatible with AK4384’s register.

[AK4359]

MS0289-E-03 2011/02

- 4 -

PIN/FUNCTION

No. Pin Name I/O Function

1 MCLK I Master Clock Input Pin

An external TTL clock should be input on this pin.

2 BICK I Audio Serial Data Clock Pin

3 SDTI1 I DAC1 Audio Serial Data Input Pin

4 LRCK I L/R Clock Pin

5 RSTB I Reset Mode Pin

When at “L”, the AK4359 is in the reset mode.

The AK4359 must be reset once upon power-up.

SMUTE I Soft Mute Pin in parallel control mode

“H”: Enable, “L”: Disable

CSN I Chip Select Pin in serial 3-wire mode

6

CAD0 I Chip Address Pin in serial I2C mode

ACKS I Auto Setting Mode Pin in parallel control mode

“L”: Manual Setting Mode, “H”: Auto Setting Mode

CCLK I Control Data Clock Pin in serial 3-wire mode

7

SCL Control Data Clock Pin in serial I2C mode

DIF0 I Audio Data Interface Format Pin in parallel control mode

CDTI I Control Data Input Pin in serial 3-wire mode

8

SDA I/O Control Data Pin in serial I2C mode

9 SDTI2 I DAC2 Audio Serial Data Input Pin

10 SDTI3 I DAC3 Audio Serial Data Input Pin

11 SDTI4 I DAC4 Audio Serial Data Input Pin

12 DIF1 I Audio Data Interface Format Pin

13 DEM0 I De-emphasis Filter Enable Pin

14 DVDD Digital Power Supply Pin, +4.5∼+5.5V

15 DVSS Digital Ground Pin

I2C I Control Mode Select Pin in serial control mode

“L”: 3-wire Serial, “H”: I2C Bus

16

DEM1 I De-emphasis Filter Enable Pin in parallel control mode

17 ROUT4 O DAC4 Rch Analog Output Pin

18 LOUT4 O DAC4 Rch Analog Output Pin

19 ROUT3 O DAC3 Rch Analog Output Pin

20 LOUT3 O DAC3 Rch Analog Output Pin

21 ROUT2 O DAC2 Rch Analog Output Pin

22 LOUT2 O DAC2 Rch Analog Output Pin

23 P/S I Parallel/Serial Select Pin (Internal pull-up pin)

“L”: Serial control mode, “H”: Parallel control mode

24 ROUT1 O DAC1 Rch Analog Output Pin

25 LOUT1 O DAC1 Lch Analog Output Pin

26 VCOM O Common Voltage Pin, AVDD/2

Normally connected to AVSS with a 0.1μF ceramic capacitor in parallel with

a 10μF electrolytic cap.

27 AVSS - Analog Ground Pin

28 AVDD - Analog Power Supply Pin, +4.5∼+5.5V

29 DZF2 O Data Zero Input Detect Pin

30 DZF1 O Data Zero Input Detect Pin

Note: All input pins except pull-up pin should not be left floating.

[AK4359]

MS0289-E-03 2011/02

- 5 -

■ Handling of Unused Pin

The unused I/O pins should be processed appropriately as below.

Classification Pin Name Setting

Analog LOUT4-1, ROUT4-1 Leave open.

DZF2-1 Leave open.

SDTI4-1

SMUTE (Parallel control mode) Connect to DVSS.

Digital

DEM0, DIF1 (Serial control mode) Connect to DVDD or DVSS.

ABSOLUTE MAXIMUM RATINGS

(AVSS=DVSS=0V; Note 1)

Parameter Symbol Min Max Units

Power Supplies

Analog

Digital

|AVSS-DVSS| (Note 2)

AVDD

DVDD

ΔGND

-0.3

-

6.0

0.3

V

Input Current (any pins except for supplies) IIN - ±10 mA

Analog Input Voltage VINA -0.3 AVDD+0.3 V

Digital Input Voltage VIND -0.3 DVDD+0.3 V

Ambient Operating Temperature Ta -40 85 °C

Storage Temperature Tstg -65 150 °C

Note 1. All voltages with respect to ground.

Note 2. AVSS and DVSS must be connected to the same analog ground plane.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS

(AVSS=DVSS=0V; Note 1)

Parameter Symbol Min Typ Max Units

Power Supplies

(Note 3) Analog

Digital AVDD

DVDD 4.5

4.5 5.0

5.0 5.5

5.5 V

V

Note 3. The power up sequence between AVDD and DVDD is not critical.

*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.

[AK4359]

MS0289-E-03 2011/02

- 6 -

ANALOG CHARACTERISTICS

(Ta=25°C; AVDD=DVDD=5V; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Input Data;

Measurement frequency=20Hz ∼ 20kHz; RL ≥5kΩ; unless otherwise specified)

Parameter Min Typ Max Units

Resolution 24 Bits

Dynamic Characteristics (Note 4)

Fs=44.1kHz

BW=20kHz 0dBFS

-60dBFS -94

-42 -84

- dB

dB

fs=96kHz

BW=40kHz 0dBFS

-60dBFS -92

-39 -

- dB

dB

THD+N

fs=192kHz

BW=40kHz 0dBFS

-60dBFS -92

-39 -

- dB

dB

Dynamic Range (-60dBFS with A-weighted) (Note 5) 98 106 dB

S/N (A-weighted) (Note 6) 98 106 dB

Interchannel Isolation (1kHz) 90 100 dB

Interchannel Gain Mismatch 0.2 0.5 dB

DC Accuracy

Gain Drift 100 - ppm/°C

Output Voltage (Note 7) 3.15 3.4 3.65 Vpp

Load Resistance (Note 8) 5 kΩ

Power Supplies

Power Supply Current (AVDD+DVDD)

Normal Operation (RSTB pin = “H”, fs≤96kHz)

Normal Operation (RSTB pin = “H”, fs=192kHz)

Reset Mode (RSTB pin = “L”) (Note 9)

55

63

60

85

90

150

mA

μA

Note 4. Measured by Audio Precision System Two. Refer to the evaluation board manual.

Note 5. 100dB at 16bit data.

Note 6. S/N does not depend on input bit length.

Note 7. Full scale voltage (0dB). Output voltage scales with the voltage of AVDD pin. AOUT (typ. @0dB) =

3.4Vpp×AVDD/5.0

Note 8. For AC-load.

Note 9. P/S pin is ti e d t o DVDD and the ot her al l di git a l i nput pi ns i ncl udi ng cl ock pi ns (M CLK, BICK, LRCK) are tied

to DVSS.

[AK4359]

MS0289-E-03 2011/02

- 7 -

SHARP ROLL-OFF FILTER CHARACTERISTICS

(Ta = 25°C; AVDD=DVDD = 4.5 ∼ 5.5V; fs = 44.1kHz; DEM = OFF; SLOW = “0”)

Parameter Symbol Min Typ Max Units

Digital filter

Passband ±0.05dB (Note 10)

-6.0dB PB 0

-

22.05 20.0

- kHz

kHz

Stopband (Note 10) SB 24.1 kHz

Passband Ripple PR ± 0.02 dB

Stopband Attenuation SA 54 dB

Group Delay (Note 11) GD - 19.3 - 1/fs

Digital Filter + SCF

Frequency Response

20.0kHz

40.0kHz

80.0kHz

Fs=44.1kHz

Fs=96kHz

Fs=192kHz

FR

-

+ 0.06/-0.10

+ 0.06/-0.13

+ 0.06/-0.51

-

dB

Note 10. The passband and stopband frequencies scale with fs(system sampling rate). For example, PB=0.4535×fs

(@±0.05dB), SB=0.546×fs.

Note 11. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data of both

channels to input register to the output of analog signal.

SLOW ROLL-OFF FILTER CHARACTERISTICS

(Ta = 25°C; AVDD=DVDD = 4.5~5.5V; fs = 44.1kHz; DEM = OFF; SLOW = “1”)

Parameter Symbol Min Typ Max Units

Digital Filter

Passband ±0.04dB (Note 12)

-3.0dB PB

0

-

18.2 8.1

- kHz

kHz

Stopband (Note 12) SB 39.2 kHz

Passband Ripple PR ± 0.005 dB

Stopband Attenuation SA 72 dB

Group Delay (Note 11) GD - 19.3 - 1/fs

Digital Filter + SCF

Frequency Response

20.0kHz

40.0kHz

80.0kHz

fs=44.kHz

fs=96kHz

fs=192kHz

FR

-

+0.1/-4.3

+0.1/-3.3

+0.1/-3.7

-

dB

Note 12. The passband and stopband frequencies scal e with fs. For example, PB = 0.185×fs (@±0.04dB), SB = 0.888×fs.

DC CHARACTERISTICS

(Ta = 25°C; AVDD=DVDD = 4.5 ∼ 5.5V)

Parameter Symbol Min Typ Max Units

High-Level Input Voltage

Low-Level Input Voltage VIH

VIL 2.2

- -

0.8 V

V

High-Level Output Voltage (Iout = -80µA)

Low-Level Output Voltage

(DZF1, DZF2 pins: Iout= 80µA)

(SDA pins: Iout= 3mA)

VOH

VOL

DVDD-0.4

-

0.4

V

Input Leakage Current (Note 13) Iin - - ± 10 μA

Note 13. P/S pin has internal pull-up device, nominally 100kΩ.

[AK4359]

MS0289-E-03 2011/02

- 8 -

SWITCHING CHARACTERISTICS

(Ta = 25°C; AVDD, DVDD = 4.5 ∼ 5.5V; CL = 20pF)

Parameter Symbol Min Typ Max Units

Master Clock Frequency

Duty Cycle fCLK

dCLK 2.048

40 11.2896

36.864

60 MHz

%

LRCK Frequency

Normal Mode (TDM0= “0”, TDM1= “0”)

Normal Speed Mode

Double Speed Mode

Quad Speed Mode

Duty Cycle

fsn

fsd

fsq

Duty

8

60

120

45

48

96

192

55

kHz

%

TDM256 mode (TDM0= “1”, TDM1= “0”)

Normal Speed Mode

High time

Low time

fsn

tLRH

tLRL

8

3/256fs

48

kHz

ns

TDM128 mode (TDM0= “1”, TDM1= “1”)

Normal Speed Mode

Double Speed Mode

High time

Low time

fsn

fsd

tLRH

tLRL

8

60

3/128fs

48

96

kHz

ns

Audio Interface Timing

BICK Period

BICK Pulse Width Low

Pulse Width High

BICK “↑” to LRCK Edge (Note 14)

LRCK Edge to BICK “↑” (Note 14)

SDTI Hold Time

SDTI Setup Time

tBCK

tBCKL

tBCKH

tBLR

tLRB

tSDH

tSDS

81

30

20

10

ns

Control Interface Timing (3-wire Serial control mode):

CCLK Period

CCLK Pulse Width Low

Pulse Width High

CDTI Setup Time

CDTI Hold Time

CSN High Time

CSN “↓” to CCLK “↑”

CCLK “↑” to CSN “↑”

tCCK

tCCKL

tCCKH

tCDS

tCDH

tCSW

tCSS

tCSH

200

80

40

150

50

ns

Control Interface Timing (I2C Bus mode):

SCL Clock Frequency

Bus Free Time Between Transmissions

Start Condition Hold Time (prior to first clock pulse)

Clock Low Time

Clock High Time

Setup Time for Repeated Start Condition

SDA Hold Time from SCL Falling (Note 15)

SDA Setup Time from SCL Rising

Rise Time of Both SDA and SCL Lines

Fall Time of Both SDA and SCL Lines

Setup Time for Stop Condition

Pulse Width of Spike Noise Suppressed by Input Filter

fSCL

tBUF

tHD:STA

tLOW

tHIGH

tSU:STA

tHD:DAT

tSU:DAT

tR

tF

tSU:STO

tSP

-

1.3

0.6

1.3

0.6

0

0.1

-

0.6

0

400

-

0.3

-

50

kHz

μs

ns

[AK4359]

MS0289-E-03 2011/02

- 9 -

Parameter Symbol Min Typ Max Units

Reset Timing

RSTB Pulse Width (Note 16)

tRST

150

ns

Note 14. BICK rising edge must not occur at the same time as LRCK edge.

Note 15. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.

Note 16. The AK4359 can be reset by bringing RSTB pin = “L”.

Note 17. I2C-bus is a trademark of NXP B.V.

[AK4359]

MS0289-E-03 2011/02

- 10 -

■ Timing Diagram

1/fCLK

tCLKL

VIH

tCLKH

MCLK VIL

dCLK=tCLKH x fCLK, tCLKL x fCLK

1/fs

VIH

LRCK VIL

tBCK

tBCKL

VIH

tBCKH

BICK VIL

Clock Timing

tLRB

LRCK

VIH

BICK VIL

tSDS

VIH

SDTI VIL

tSDH

VIH

VIL

tBLR

Audio Serial Interface Timing

[AK4359]

MS0289-E-03 2011/02

- 11 -

tCSS

CSN

VIH

CCLK VIL

VIH

CDTI VIL

VIH

VIL

C1 C0 R/W A4

tCCKL tCCKH

tCDS tCDH

WRITE Command Input Timing

CSN

VIH

CCLK VIL

VIH

CDTI VIL

VIH

VIL

D3 D2 D1 D0

tCSW

tCSH

WRITE Data Input Timing

tHIGH

SCL

SDA VIH

tLOW

tBUF

tHD:STA

tR tF

tHD:DAT tSU:DAT tSU:STA

Stop Start Start Stop

tSU:STO

VIL

VIH

VIL

tSP

I2C Bus mode Timing

tRST

VIL

RSTB

Reset Timing

[AK4359]

MS0289-E-03 2011/02

- 12 -

OPERATION OVERVIEW

■ System Clock

The external clocks, which are required t o operate the AK4359, are MCLK, LRCK and BICK. The mast er clock (MCLK)

should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation

filter and the delta-sigma m odulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS bit

= “0”: Register 00H), the sampling speed is set by DFS0-1 bits (Table 1). The frequency of MCLK at each sampling speed

is set automatically. (Table 2~Table 4) In Auto Sett ing Mode (ACKS bit = “1”: Default), as MCLK frequency is detected

automatically (Table 5), and the internal m ast er clock becom e s the appropriat e frequency (Table 6), it is not necessary to

set DFS0-1.

In parallel control m ode, the sampli ng speed can be set by only ACKS pi n. When ACKS pin = “L”, the AK4359 operate s

by Normal Speed Mode. When ACKS pin = “H”, Auto setting mode is enabled. The parallel control mode does not

support 128fs and 192fs of Double Speed Mode.

All external clocks (MCLK, BICK and LRCK) should alway s be present whenever the AK4359 is in the normal operation

mode (RSTB pin = ”H”). If these clocks are not provided, the AK4359 may draw excess current and may fall into

unpredictable operation. This is because the device utilizes dynamic refreshed logic internally. The AK4359 should be

reset by RSTB pin = “L” after t hrese clocks are provided. If the exte rnal clocks are not present , the AK4359 should be in

the power-down mode (RSTB pin = ”L”). After exiting reset(RSTB = “↑”) at power-up etc., the AK4359 is in the

power-down mode until MCLK is input.

DFS1 DFS0 Sampling Rate (fs)

0 0 Normal Speed Mode 8kHz~48kHz Default

0 1 Double Speed Mode 60kHz~96kHz

1 0 Quad Speed Mode 120kHz~192kHz

Table 1. Sampling Speed (Manual Setting Mode)

LRCK MCLK BICK

fs 256fs 384fs 512fs 768fs 1152fs 64fs

32.0kHz 8.1920MHz 12.2880MHz 16.3840MHz 24.5760MHz 36.8640MHz 2.0480MHz

44.1kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz N/A 2.8224MHz

48.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz N/A 3.0720MHz

Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)

[AK4359]

MS0289-E-03 2011/02

- 13 -

LRCK MCLK BICK

fs 128fs 192fs 256fs 384fs 64fs

88.2kHz 106896MHz 16.9344MHz 22.5792MHz 33.8688MHz 5.6448MHz

96.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz 6.1440MHz

Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode)

LRCK MCLK BICK

fs 128fs 192fs 64fs

176.4kHz 22.5792MHz 33.8688MHz 106896MHz

192.0kHz 24.5760MHz 36.8640MHz 12.2880MHz

Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode)

MCLK Sampling Speed

512fs 768fs Normal

256fs 384fs Double

128fs 192fs Quad

Table 5. Sampling Speed (Auto Setting Mode)

LRCK MCLK (MHz)

fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs

Sampling

Speed

32.0kHz - - - - 16.3840 24.5760 36.8640

44.1kHz - - - - 22.5792 33.8688 -

48.0kHz - - - - 24.5760 36.8640 -

Normal

88.2kHz - - 22.5792 33.8688 - - -

96.0kHz - - 24.5760 36.8640 - - - Double

176.4kHz 22.5792 33.8688 - - - - -

192.0kHz 24.5760 36.8640 - - - - - Quad

Table 6. System Clock Example (Auto Setting Mode)

[AK4359]

MS0289-E-03 2011/02

- 14 -

■ Audio Serial Interface Format

In parallel control m ode, the DIF0-1 pins as shown in Table 7 can select four serial data modes. In serial mode, the DIF0-2

bits shown in Table 8 can select five serial data modes. Initial value of DIF0-2 bits is “010”. The setting of DIF1 pin is

ignored. In all m odes the serial data is MSB-first, 2’s com plement format and is latched on the rising edge of BICK. Mode

2 can be used for 16/20 MSB justified formats by zeroing the unused LSBs.

In serial control mode, when TDM0 bit = “1”, the audio interface becomes TDM mode. In TDM256 mode (TDM1 bit =

“0”, Table 9), the serial data of all DAC (eight channels) is input to the SDTI1 pin. The input data to SDTI2-4 pins is

ignored. BICK should be fixed to 256fs. “H” time and “L” time of LRCK should be 3/256fs at least. The serial data is

MSB-first, 2’s com plement format. The input data to SDTI1 pin is lat ched on the rising edge of BICK. In TDM128 m ode

(TDM1 bit = “1”, Table 10), the serial data of DAC (four channels; L1, R 1, L2, R2) is input to the SDTI1 pin. Other four

data (L3, R3, L4, R4) is input to the SDTI2. The input data to SDTI3-4 pins is ignored. BICK should be fixed to 128fs.

Mode DIF1 DIF0 SDTI Format LRCK BICK Figure

0 0 0 16bit LSB Justified H/L ≥32fs Figure 1

1 0 1 20bit LSB Justified H/L ≥40fs Figure 2

2 1 0 24bit MSB Justified H/L ≥48fs Figure 3

3 1 1 24bit I2S Compatible L/H ≥48fs Figure 4

Table 7. Audio Data Formats (Parallel control mode)

Mode TDM1 TDM0 DIF2 DIF1 DIF0 SDTI Format LRCK BICK Figure

0 0 0 0 0 0 16bit LSB Justified H/L ≥32fs Figure 1

1 0 0 0 0 1 20bit LSB Justified H/L ≥40fs Figure 2

2 0 0 0 1 0 24bit MSB Justified H/L ≥48fs Figure 3 Default

3 0 0 0 1 1 24bit I2S Compatible L/H ≥48fs Figure 4

4 0 0 1 0 0 24bit LSB Justified H/L ≥48fs Figure 2

Table 8. Audio Data Formats (Serial control mode)

SDTI

BICK

LRCK

SDTI 15 14 6 5 4

BICK

0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1

3 2 1 0 15 14

(

32fs

)

(

64fs

)

014

115 16 17 31 0 1 14 15 16 17 31 0 1

15 14 0 15 14 0

Mode 0 Don’t care Don’t care

15:MSB, 0:LSB

Mode 0 15 14 6 5 4 3 2 1 0

Lch Data Rch Data

Figure 1. Mode 0 Timing

[AK4359]

MS0289-E-03 2011/02

- 15 -

SDTI

LRCK

BICK

(

64fs

)

091 10 11 12 31 0 1 9 10 11 12 31 0 1

19 0 19 0

Mode 1 Don’t care Don’t care

19:MSB, 0:LSB

SDTI

Mode 4 23:MSB, 0:LSB

20 19 0 20 19 0

Don’t care Don’t care

22 21 22 21

Lch Data Rch Data

8

23 23

8

Figure 2. Mode 1,4 Timing

LRCK

BICK

(

64fs

)

SDTI

0221 2 24 31 0 1 31 0 1

23:MSB, 0:LSB

22 1 0 Don’t care23

Lch Data Rch Data

23 30 2222423 30

22 1 0 Don’t care

23 2223

Figure 3. Mode 2 Timing

LRCK

BICK

(

64fs

)

SDTI

031 2 24 31 0 1 31 0 1

23:MSB, 0:LSB

22 10Don’t care

23

Lch Data Rch Data

23 25 322423 25

22 1 0Don’t care23 23

Figure 4. Mode 3 Timing

[AK4359]

MS0289-E-03 2011/02

- 16 -

Mode TDM1 TDM0 DIF2 DIF1 DIF0 SDTI Format LRCK BICK Figure

0 1 0 0 0 N/A

0 1 0 0 1 N/A

5 0 1 0 1 0 24bit MSB Justified ↑ 256fs Figure 5

6 0 1 0 1 1

24bit I2S

Compatible ↓ 256fs Figure 6

7 0 1 1 0 0 24bit LSB Justified ↑ 256fs Figure 7

Table 9. Audio Data Formats (TDM256 mode)

LRCK

BICK(256fs)

SDTI1(i)

256 BICK

22 0

L1

32 BICK

22 0

R1

32 BICK

22 0

L2

32 BICK

22 0

R2

32 BICK

22 0

L3

32 BICK

22 0

R3

32 BICK

22 0

L4

32 BICK

22 0

R4

32 BICK

22 23 23 23 23 23 23 23 23 23

3/256fs (min) 3/256fs (min)

Figure 5. Mode 5 Timing

LRCK

BICK(256fs)

SDTI1(i)

256 BICK

23 0

L1

32 BICK

23 0

R1

32 BICK

23 0

L2

32 BICK

23 0

R2

32 BICK

23 0

L3

32 BICK

23 0

R3

32 BICK

23 0

L4

32 BICK

23 0

R4

32 BICK

23

3/256fs (min) 3/25 6fs (min)

Figure 6. Mode 6 Timing

LRCK

BICK(256fs)

SDTI1(i)

256 BICK

22 0

L1

32 BICK

22 0

R1

32 BICK

22 0

L2

32 BICK

22 0

R2

32 BICK

22 0

L3

32 BICK

22 0

R3

32 BICK

22 0

L4

32 BICK

22 0

R4

32 BICK

23 23 23 23 23 23 23 23 23

3/256fs (min) 3/256fs (min)

Figure 7. Mode 7 Timing

[AK4359]

MS0289-E-03 2011/02

- 17 -

Mode TDM1 TDM0 DIF2 DIF1 DIF0 SDTI Format LRCK BICK Figure

1 1 0 0 0 N/A

1 1 0 0 1 N/A

8 1 1 0 1 0 24bit MSB Justified ↑ 128fs Figure 8

9 1 1 0 1 1

24bit I2S

Compatible ↓ 128fs Figure 9

10 1 1 1 0 0 24bit LSB Justified ↑ 128fs Figure

10

Table 10. Audio Data Formats (TDM128 mode)

LRCK

BICK(128fs)

128 BICK

L1

32 BICK R1

32 BICK L2

32 BICK R2

32 BICK

L3

32 BICK R3

32 BICK L4

32 BICK R4

32 BICK

SDTI1(i) 22 0 22 022 022 0 23 23 23 23 22 23

SDTI2(i) 22 0 22 022 022 0 23 23 23 23 22 23

3/128fs (min) 3/128fs (min)

Figure 8. Mode 8 Timing

LRCK

BICK(128fs)

128 BICK

L1

32 BICK R1

32 BICK L2

32 BICK R2

32 BICK

L3

32 BICK R3

32 BICK L4

32 BICK R4

32 BICK

SDTI1(i) 22 0 22 022 022 0 23 23 23 23 23

SDTI2(i) 22 0 22 022 022 0

23 23 23 23 23

3/128fs (min) 3/128fs (min)

Figure 9. Mode 9 Timing

LRCK

BICK(128fs)

128 BICK

L1

32 BICK R1

32 BICK L2

32 BICK R2

32 BICK

L3

32 BICK R3

32 BICK L4

32 BICK R4

32 BICK

SDTI1(i) 22 0 22 022 022 0

23 23 23 23 19

SDTI2(i) 22 0 22 022 022 0

23 23 23 23 19

3/128fs (min) 3/128fs (min)

Figure 10. Mode 10 Timing

[AK4359]

MS0289-E-03 2011/02

- 18 -

■ De-emphasis Filter

A digital de-emphasis filter is available for 32, 44.1 or 48kHz sam pling rates (tc = 50/15μs). In case of doubl e speed and

quad speed mode, the digital de-emphasis filter is always off. In serial control mode, the DEM0-1 bits are valid for the

DAC enabled by the DEMA-D bits. In parallel control mode, DEM0-1 pins are valid.

DEM1 DEM0 Mode

0 0 44.1kHz

0 1 OFF

Default

1 0 48kHz

1 1 32kHz

Table 11. De-emphasis Filter Control (Normal Speed Mode)

■ Output Volume

The AK4359 includes channel independent digital output volumes (ATT) wi th 256 levels at li near step including MUTE.

These volumes are in front of the DAC and can attenuate the input data from 0dB to –48dB and mute. When changing

levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. The transition

time of 1 level and all 256 levels is shown in Table 12. The attenuation level is calculated by ATT = 20 log10

(ATT_DATA / 255) [dB] and MUTE at ATT_DATA = “0”.

Transition Time

Sampling Speed 1 Level 255 to 0

Normal Speed Mode 4LRCK 1020LRCK

Double Speed Mode 8LRCK 2040LRCK

Quad Speed Mode 16LRCK 4080LRCK

Table 12. ATT Transition time

■ Zero Detection

When the input data at all channels are continuously zeros for 8192 LRCK cycles, the AK4359 has Zero Detection like

Table 13. DZF pin imme diately goes to “L” if input data of each channel is not zero after going DZF “H”. If RSTN bit is

“0”, DZF pin goes to “H”. DZF pin goes to “L” after 4~5LRCK if input data of each channel is not zero after RSTN bit

returns to “1”. Zero detect function can be disabl ed by DZFE bit. In this case, all DZF pins are always “L”. When one of

PW1-4 bit is set to “0”, the input dat a of DAC that the PW bit is set to “0” should be zero in order to enable zero detection

of the other channels. When all PW1-4 bits are set to “0”, DZF pin fixes “L”. DZFB bi t can invert the polarity of DZF pin.

In parallel control mode, the zero detect function is disabled and the DZF pin is fixed to “L”.

DZF Pin Operations

DZF1 ANDed output of zero detection flag of each channel set to “1” in 0CH register

DZF2 ANDed output of zero detection flag of each channel set to “1” in 0DH register

Table 13. DZF pins Operation

[AK4359]

MS0289-E-03 2011/02

- 19 -

■ Soft Mute Operation

Soft mute operation is performed at digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated by

-∞ during ATT_DATA×ATT transition time (Table 12) from the current ATT level. When the SMUTE bit is returned to

“0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA×ATT

transition time. If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is

discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source

without stopping the signal transmission.

SMUTE

A

ttenuation

DZF pin

ATT Level

-∞

A

OUT

8192/fs

GD GD

(1)

(2)

(3)

(4)

(1)

Notes:

(1) ATT_DATA×ATT transition time (Table 12). For example, in Norm al Speed Mode, this tim e is 1020LRCK cycles

(1020/fs) at ATT_DATA=255.

(2) The analog output corresponding to the digital input has a group delay, GD.

(3) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the att enuation is discontinued and

returned to ATT level by the same cycle.

(4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to

“H”. DZF pin im mediat ely goes to “L” if input data are not zero aft er going DZF “H”. In parallel control mode, the

DZF pin is fixed to “L” regardless of the state of SMUTE pin.

Figure 11. Soft Mute and Zero Detection (DZFB bit = “0”)

[AK4359]

MS0289-E-03 2011/02

- 20 -

■ System Reset

The AK4359 should be reset once by bringing RSTB pin = ”L” upon power-up. The AK4359 is powered up and the

internal timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4359 is in the

power-down mode until MCLK and LRCK are input.

■ Power ON/OFF timing

All DACs are placed in the power-down mode by bringing RSTB pin “L” and the registers are initialized. the analog

outputs go to VCOM. As some click noise occurs at the edge of RSTB signal, the analog output should be muted

externally if the click noise in fluences system application.

Each DAC can be powered down by setting each power-down bit (PW1-4) to “0”. In this case, the registers are not

initialized and the corresponding analog outputs go to VCOM. As some click noise occurs at the edge of RSTB signal, the

analog output should be muted externally if the click noise influences system application.

RSTB pin

Power

Reset

Normal Ope ration

Clock In

MCLK,LRCK,SCLK

DAC In

(Digital)

DAC Out

(Analog)

External

Mute Mute ON

(5)

DZF1/DZF2

Don’t care

“0”data

GD

(1)

(3)

(4)

(6)

GD

(3)

M u te ON

“0”data

Don’t care

Interna l

State

(2) (2)

Notes:

(1) The analog output corresponding to digital input has the group delay (GD).

(2) Analog outputs go to VCOM at the power-down mode.

(3) Click noise occurs at the edge of RSTB signal. This noise is output even if “0” data is input.

(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (RSTB pin = “L”).

(5) Mute the analog output externally if the click noise (3) influence system application.

The timing example is shown in this figure.

(6) DZF pins are “L” in the power-down mode (RSTB pin = “L”). (DZFB bit = “0”)

Figure 12. Power-down/up Sequence Example

[AK4359]

MS0289-E-03 2011/02

- 21 -

■ Reset Function (RSTN bit)

When RSTN bit = “0”, internal circuit of DAC is powered down but the registers are not initialized. The analog outputs go

to VCOM vol tage and DZF pins go to “H” at DZFB bit = “0”. Figure 13 shows the exam pl e of reset by RSTN bit . When

RSTN bit = “0”, pop noise is decreased at no clock state.

Internal

State

RSTN bit

Digital Block Power-down Normal Operat i on

GD GD

“0” data

D/A Out

(Analog)

D/A In

(Digital)

Clock In

MCLK,LRCK,BICK

(1) (3)

DZF

(3) (1)

(2)

Normal Operation

2/fs(5)

Internal

RSTN bit

2~3/fs (6)3~4/fs (6)

Don’t care

(4)

Notes:

(1) The analog output corresponding to digital input has the group delay (GD).

(2) Analog outputs go to VCOM voltage.

(3) Small pop noise occurs at the edges(“↑ ↓”) of the internal timing of RSTN bit. This noise is output even if “0”

data is input.

(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN bit = “0”).

(5) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 2/fs after RSTN bit becomes “1”.

(6) There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0 ”, and 2~3/fs from RSTN bit “1” to the

internal RSTN bit “1”.

Figure 13. Reset Sequence Example (DZFB bit = “0”)

[AK4359]

MS0289-E-03 2011/02

- 22 -

■ Register Control Interface

The AK4359 controls its functi ons via registers. 2 types of control mode write internal registers. In the I2C-bus mode, the

chip address is determined by the state of the CAD0 pin. In 3-wire mode, the chip address is fixed to “11”. RSTB pin =

“L” initializes the registers to their default values. Writing “0” to the RSTN bit resets th e internal timing circuit, bu t the

register s are not initialized.

* The AK4359 does not support the read command.

* When the AK4359 is in the power down mode (RSTB bit = “L”) or the MCLK is not provided, Writing to control

register is inhibited.

* When the state of P/S pin is changed, the AK4359 should be reset by RSTB bit = “L”.

* In serial control mode, the setting of parallel pins is invalid.

Function Parallel Control Mode Serial Control Mode

Double sampling mode at 128/192fs X O

De-emphasis O O

SMUTE O O

Zero Detection X O

24bit LSB justified format X O

TDM mode X O

Table 14. Function Table (O: Supported, X: Not supported)

(1) 3-wire Serial Control Mode (I2C pin = “L”)

3-wire μP interface pins, CSN, CCLK and CDTI, write internal registers. The data on this interface consists of Chip

Address (2bits, C1/0; fixed to “11”), Read/Write (1bit; fixed to “1”, Write only), Register Address (MSB first, 5bits) and

Control Data (MSB first, 8bits). The AK4359 latches the data on the rising edge of CCLK, so data should clocked in on

the falling edge. The writi ng of data becomes vali d by the rising edge of CSN. The clock speed of C CLK is 5MHz (max).

CDTI

CCLK

CSN

C1

012345678 9 10 11 12 13 14 15

D4D5D6D7A1A2A3A4R/WC0 A0 D0D1D2D3

C1-C0: Chip Address (Fixed to “11”)

R/W: READ/WRITE (Fixed to “1”, Write only)

A4-A0: Register Address

D7-D0: Control Data

Figure 14. Control I/F Timing

[AK4359]

MS0289-E-03 2011/02

- 23 -

(2) I2C-bus Control Mode (I2C pin = “H”)

The AK4359 supports the fast-mode I2C-bus system (max: 400kHz).

Figure 15 shows the data transfer sequence at the I2C-bus mode. All commands are preceded by a START condition. A

HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 19). After the

START condition, a slave address is sent. This address is 7 bits long followed by an eight h bit which is a data directi on bit

(R/W) (Figure 16). The most significant six bits of the slave address are fixed as “001001”. The next one bit are CAD0

(device address bit). The bit identify the specifi c device on the bus. The hard-wired input pin (C AD0 pin) set them . If the

slave address match that of the AK4359 and R/W bit is “0”, the AK4359 generates the acknowledge and the write

operation is executed. If R/W bit is “1”, the AK4359 generates the not acknowledge since the AK4359 can be only a

slave-receiver. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during

the acknowledge clock pulse (Figure 20).

The second byte consists of the address for control registers of the AK4359. The format is MSB first, and those most

significant 3-bits are fixed to zeros (Figure 17). Those data after the second byte contain control dat a. The format is M SB

first, 8bits (Figure 18). The AK4359 generates an acknowledge after each byte has been received. A data transfer is

always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL

is HIGH defines a STOP condition (Figure 19).

The AK4359 is capable of more than one byte write operation by one sequence. After receipt of the third byte, the

AK4359 generates an acknowledge, and awaits the next data again. The master can transmit m ore than one byte instead of

terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal 5bits address

counter is incremented by one, and the next data is taken into next address automatically. If the addresses exceed 1FH

prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be

overwritten.

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line

can only change when the clock signal on the SCL line is LOW (Figure 21) except for the START and the STOP

condition.

SDA

S

T

A

R

T

A

C

K

A

C

K

SSlave

A

ddress

A

C

K

Sub

A

ddress(n) Data(n) P

S

T

O

P

Data(n+x)

A

C

K

Data(n+1)

A

C

K

R/W

A

C

K

Figure 15. Data transfer sequence at the I2C-bus mode

0 0 1 0 0 1 CAD0 R/W

(Those CAD1/0 should match with CAD1/0 pins)

Figure 16. The first byte

0 0 0 A4 A3 A2 A1 A0

Figure 17. The second byte

D7 D6 D5 D4 D3 D2 D1 D0

Figure 18. Byte structure after the second byte

[AK4359]

MS0289-E-03 2011/02

- 24 -

SCL

SDA

stop conditionstart condition

SP

Figure 19. START and STOP conditions

SCL FROM

MASTER

acknowledge

DATA

OUTPUT BY

MASTER

DATA

OUTPUT BY

SLAVE(AK4359)

1 98

START

CONDITION

not acknowledge

clock pulse for

acknowledgement

S

2

Figure 20. Acknowledge on the I2C-bus

SCL

SDA

data line

stable;

data valid

change

of data

allowed

Figure 21. Bit transfer on the I2C-bus

[AK4359]

MS0289-E-03 2011/02

- 25 -

■ Register Map

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

00H Control 1 ACKS TDM1 TDM0 DIF2 DIF1 DIF0 PW1 RSTN

01H Control 2 0 0 SLOW DFS1 DFS0 DEM1 DEM0 SMUTE

02H Control 3 PW4 PW3 PW2 0 0 DZFB PW1 0