M95320-WDW6P/PB - STMicroelectronics, Inc.

December 2007 Rev 8 1/45

M95320 M95320-W M95320-R

M95640 M95640-W M95640-R

32 Kbit and 64 Kbit serial SPI bus EEPROMs

with high speed clock

Features

■Compatible with SPI bus serial interface

(positive clock SPI modes)

■Single supply voltage:

– 4.5 to 5.5 V for M95320 and M95640

– 2.5 to 5.5 V for M95320-W and M95320-W

– 1.8 to 5.5 V for M95320-R and M95640-R

■10 MHz, 5 MHz or 2 MHz clock rates

■5 ms write time

■Status Register

■Hardware protection of the Status Register

■Byte and Page Write (up to 32 bytes)

■Self-timed programming cycle

■Adjustable size read-only EEPROM area

■Enhanced ESD protection

■More than 1 million Write cycles

■More than 40-year data retention

■Packages

– ECOPACK® (RoHS compliant)

SO8 (MN)

150 mil width

TSSOP8 (DW)

169 mil width

UFDFPN8 (MB)

2 x 3 mm

www.st.com

Contents M95320, M95640, M95320-x, M95640-x

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Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.6 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.7 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.8 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1.1 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.2 Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.2.1 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.3 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.4 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.3 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.3.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

M95320, M95640, M95320-x, M95640-x Contents

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6.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.3.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.4 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.5 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.6 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7 Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

10 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

List of tables M95320, M95640, M95320-x, M95640-x

4/45

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 3. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 5. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 6. Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 8. Operating conditions (M95320 and M95640) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 9. Operating conditions (M95320-W and M95640-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 10. Operating conditions (M95320-R and M95640-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 11. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 12. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 13. DC characteristics (M95320 and M95640, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 14. DC characteristics (M95320-W and M95640-W, device grade 6). . . . . . . . . . . . . . . . . . . . 29

Table 15. DC characteristics (M95320-W and M95640-W, device grade 3). . . . . . . . . . . . . . . . . . . . 29

Table 16. DC characteristics (M95320-R and M95640-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 17. AC characteristics (M95320 and M95640, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 18. AC characteristics (M95320-W and M95640-W, device grade 6). . . . . . . . . . . . . . . . . . . . 32

Table 19. AC characteristics (M95320-W and M95640-W, device grade 3). . . . . . . . . . . . . . . . . . . . 33

Table 20. AC characteristics (M95320-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 21. AC characteristics (M95640-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 22. SO8N – 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . 38

Table 23. TSSOP8 – 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 39

Table 24. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 25. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 26. Available M95320x products (package, voltage range, temperature grade) . . . . . . . . . . . 42

Table 27. Available M95640x products (package, voltage range, temperature grade) . . . . . . . . . . . 42

Table 28. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

M95320, M95640, M95320-x, M95640-x List of figures

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List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. 8 pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 7. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 8. Write Disable (WRDI) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 9. Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 10. Write Status Register (WRSR) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 11. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 12. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 13. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 14. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 15. Serial Input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 16. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 17. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 18. SO8N – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 38

Figure 19. TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 20. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package

outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Description M95320, M95640, M95320-x, M95640-x

6/45

1 Description

These electrically erasable programmable memory (EEPROM) devices are accessed by a

high speed SPI-compatible bus.

The M95320, M95320-W and M95320-R are 32 Kbit devices organized as 4096 x 8 bits.

The M95640, M95640-W and M95640-R are 64 Kbit devices organized as 8192 x 8 bits.

The device is accessed by a simple serial interface that is SPI-compatible. The bus signals

are C, D and Q, as shown in Ta bl e 1 and Figure 1.

The device is selected when Chip Select (S) is taken low. Communications with the device

can be interrupted using Hold (HOLD).

In order to meet environmental requirements, ST offers these devices in ECOPACK®

packages.

ECOPACK® packages are Lead-free and RoHS compliant. ECOPACK is an ST trademark.

ECOPACK specifications are available at: www.st.com.

Figure 1. Logic diagram

Figure 2. 8 pin package connections

1. See Package mechanical section for package dimensions and how to identify pin-1.

AI01789C

VCC

M95xxx

HOLD

VSS

DVSS

HOLDQ

AI01790D

M95xxx

M95320, M95640, M95320-x, M95640-x Description

7/45

Table 1. Signal names

Signal name Description

C Serial Clock

D Serial data input

Q Serial data output

SChip Select

WWrite Protect

HOLD Hold

VCC Supply voltage

VSS Ground

Signal description M95320, M95640, M95320-x, M95640-x

8/45

2 Signal description

During all operations, VCC must be held stable and within the specified valid range:

VCC(min) to VCC(max).

All of the input and output signals must be held high or low (according to voltages of VIH,

VOH, VIL or VOL, as specified in Ta b l e 1 3 to Ta b le 1 6 ). These signals are described next.

2.1 Serial Data output (Q)

This output signal is used to transfer data serially out of the device. Data is shifted out on the

falling edge of Serial Clock (C).

2.2 Serial Data input (D)

This input signal is used to transfer data serially into the device. It receives instructions,

addresses, and the data to be written. Values are latched on the rising edge of Serial Clock

(C).

2.3 Serial Clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data

present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on

Serial Data Output (Q) changes after the falling edge of Serial Clock (C).

2.4 Chip Select (S)

When this input signal is high, the device is deselected and Serial Data output (Q) is at high

impedance. Unless an internal Write cycle is in progress, the device will be in the Standby

Power mode. Driving Chip Select (S) low selects the device, placing it in the Active Power

mode.

After Power-up, a falling edge on Chip Select (S) is required prior to the start of any

instruction.

2.5 Hold (HOLD)

The Hold (HOLD) signal is used to pause any serial communications with the device without

deselecting the device.

During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data

input (D) and Serial Clock (C) are Don’t Care.

To start the Hold condition, the device must be selected, with Chip Select (S) driven low.

M95320, M95640, M95320-x, M95640-x Signal description

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2.6 Write Protect (W)

The main purpose of this input signal is to freeze the size of the area of memory that is

protected against Write instructions (as specified by the values in the BP1 and BP0 bits of

the Status Register).

This pin must be driven either high or low, and must be stable during all write operations.

2.7 VSS ground

VSS is the reference for the VCC supply voltage.

2.8 VCC supply voltage

Refer to Section 4.1: Supply voltage (VCC) on page 12.

Connecting to the SPI bus M95320, M95640, M95320-x, M95640-x

10/45

3 Connecting to the SPI bus

These devices are fully compatible with the SPI protocol.

All instructions, addresses and input data bytes are shifted in to the device, most significant

bit first. The Serial Data input (D) is sampled on the first rising edge of the Serial Clock (C)

after Chip Select (S) goes low.

All output data bytes are shifted out of the device, most significant bit first. The Serial Data

output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such

as the Read from Memory Array and Read Status Register instructions) have been clocked

into the device.

Figure 3 shows three devices, connected to an MCU, on a SPI bus. Only one device is

selected at a time, so only one device drives the Serial Data output (Q) line at a time, all the

others being high impedance.

Figure 3. Bus master and memory devices on the SPI bus

1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.

The pull-up resistor R (represented in Figure 3) ensures that a device is not selected if the

bus master leaves the S line in the high impedance state.

In applications where the bus master might enter a state where all inputs/outputs SPI bus

would be in high impedance at the same time (for example, if the bus master is reset during

the transmission of an instruction), the clock line (C) must be connected to an external pull-

down resistor so that, if all inputs/outputs become high impedance, the C line is pulled low

(while the S line is pulled high): this will ensure that S and C do not become high at the

same time, and so, that the tSHCH requirement is met. The typical value of R is 100 kΩ.

AI12836b

SPI bus master

SPI memory

device

SDO

SDI

SCK

CQD

SPI memory

device

CQD

SPI memory

device

CQD

CS3 CS2 CS1

SPI interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

WHOLD WHOLD WHOLD

RRR

VCC

VCC VCC VCC

VSS

VSS VSS VSS

M95320, M95640, M95320-x, M95640-x Connecting to the SPI bus

11/45

3.1 SPI modes

These devices can be driven by a microcontroller with its SPI peripheral running in either of

the two following modes:

●CPOL=0, CPHA=0

●CPOL=1, CPHA=1

For these two modes, input data is latched in on the rising edge of Serial Clock (C), and

output data is available from the falling edge of Serial Clock (C).

The difference between the two modes, as shown in Figure 4, is the clock polarity when the

bus master is in Stand-by mode and not transferring data:

●C remains at 0 for (CPOL=0, CPHA=0)

●C remains at 1 for (CPOL=1, CPHA=1)

Figure 4. SPI modes supported

AI01438B

MSB

CPHA

CPOL

MSB

Operating features M95320, M95640, M95320-x, M95640-x

12/45

4 Operating features

4.1 Supply voltage (VCC)

4.1.1 Operating supply voltage VCC

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage

within the specified [VCC(min), VCC(max)] range must be applied (see Ta bl e 8 , Ta b l e 9 and

Ta bl e 1 0 ). In order to secure a stable DC supply voltage, it is recommended to decouple the

VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the

VCC/VSS package pins.

This voltage must remain stable and valid until the end of the transmission of the instruction

and, for a Write instruction, until the completion of the internal write cycle (tW).

4.1.2 Power-up conditions

When the power supply is turned on, VCC continuously rises from VSS to VCC. During this

time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage, it is

therefore recommended to connect the S line to VCC via a suitable pull-up resistor.

In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge

sensitive as well as level sensitive: after power-up, the device does not become selected

until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select

(S) must have been high, prior to going low to start the first operation.

The VCC rise time must not vary faster than 1 V/µs.

4.1.3 Device reset

In order to prevent inadvertent Write operations during power-up (continuous rise of VCC), a

power on reset (POR) circuit is included. At power-up, the device will not respond to any

instruction until VCC has reached the power on reset threshold voltage (this threshold is

lower than the minimum VCC operating voltage defined in Ta bl e 8 , Ta bl e 9 and Ta b l e 1 0 ).

Until VCC passes over the POR threshold, the device is reset. Once VCC has passed over

the POR threshold, the device is in the following state:

●Standby Power mode

●deselected (at next power-up, a falling edge is required on Chip Select (S) before any

instruction can be started)

●not in the Hold condition

●Status register

– the Write Enable Latch (WEL) bit is reset to 0

– the Write In Progress (WIP) bit is reset to 0

– the SRWD, BP1 and BP0 bits of the Status Register are in the same state as when

power was last removed (they are non-volatile bits).

M95320, M95640, M95320-x, M95640-x Operating features

13/45

4.1.4 Power-down

At power-down (continuous decrease in VCC), as soon as VCC drops from the normal

operating voltage to below the power on reset threshold voltage, the device is reset and

stops responding to any instruction sent to it. During power-down, the device must be

deselected (Chip Select (S) should be allowed to follow the voltage applied on VCC) and in

Standby Power mode (that is there must be no internal Write cycle in progress).

4.2 Active Power and Standby Power modes

When Chip Select (S) is low, the device is selected, and in the Active Power mode. The

device consumes ICC, as specified in Ta b l e 1 3 to Ta bl e 1 6 .

When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in

progress, the device then goes in to the Standby Power mode, and the device consumption

drops to ICC1.

4.2.1 Hold condition

The Hold (HOLD) signal is used to pause any serial communications with the device without

resetting the clocking sequence.

During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data

input (D) and Serial Clock (C) are Don’t Care.

To enter the Hold condition, the device must be selected, with Chip Select (S) low.

Normally, the device is kept selected, for the whole duration of the Hold condition.

Deselecting the device while it is in the Hold condition, has the effect of resetting the state of

the device, and this mechanism can be used if it is required to reset any processes that had

been in progress.

The Hold condition starts when the Hold (HOLD) signal is driven low at the same time as

Serial Clock (C) already being low (as shown in Figure 5).

The Hold condition ends when the Hold (HOLD) signal is driven high at the same time as

Serial Clock (C) already being low.

Figure 5 also shows what happens if the rising and falling edges are not timed to coincide

with Serial Clock (C) being low.

Figure 5. Hold condition activation

AI02029D

HOLD

Hold

Condition

Hold

Condition

Operating features M95320, M95640, M95320-x, M95640-x

14/45

4.3 Status Register

Figure 6 shows the position of the Status Register in the control logic of the device. The

Status Register contains a number of status and control bits that can be read or set (as

appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a

detailed description of the Status Register bits.

4.4 Data protection and protocol control

Non-volatile memory devices can be used in environments that are particularly noisy, and

within applications that could experience problems if memory bytes are corrupted.

Consequently, the device features the following data protection mechanisms:

●Write and Write Status Register instructions are checked that they consist of a number

of clock pulses that is a multiple of eight, before they are accepted for execution.

●All instructions that modify data must be preceded by a Write Enable (WREN)

instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state

by the following events:

–Power-up

– Write Disable (WRDI) instruction completion

– Write Status Register (WRSR) instruction completion

– Write (WRITE) instruction completion

●The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be

configured as read-only.

●The Write Protect (W) signal allows the Block Protect (BP1, BP0) bits of the Status

For any instruction to be accepted, and executed, Chip Select (S) must be driven high after

the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising

edge of Serial Clock (C).

Two points need to be noted in the previous sentence:

●The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth

bit of a data byte, depending on the instruction (except for Read Status Register

(RDSR) and Read (READ) instructions).

●The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus

transaction for some other device on the SPI bus.

Table 2. Write-protected block size

Status Register bits

Protected block

Array addresses protected

BP1 BP0 64 Kbit devices 32 Kbit devices

0 0 none none none

0 1 Upper quarter 1800h - 1FFFh 0C00h - 0FFFh

1 0 Upper half 1000h - 1FFFh 0800h - 0FFFh

1 1 Whole memory 0000h - 1FFFh 0000h - 0FFFh

M95320, M95640, M95320-x, M95640-x Memory organization

15/45

5 Memory organization

The memory is organized as shown in Figure 6.

Figure 6. Block diagram

AI01272C

HOLD

WControl Logic High Voltage

Generator

I/O Shift Register

Address Register

and Counter

Data

1 Page

X Decoder

Y Decoder

Size of the

Read only

EEPROM

area

Status

Instructions M95320, M95640, M95320-x, M95640-x

16/45

6 Instructions

Each instruction starts with a single-byte code, as summarized in Ta b l e 3 .

If an invalid instruction is sent (one not contained in <Blue>Table 3.), the device

automatically deselects itself.

6.1 Write Enable (WREN)

The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.

The only way to do this is to send a Write Enable instruction to the device.

As shown in Figure 7, to send this instruction to the device, Chip Select (S) is driven low,

and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then

enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven

high.

Figure 7. Write Enable (WREN) sequence

Table 3. Instruction set

Instruction Description Instruction format

WREN Write Enable 0000 0110

WRDI Write Disable 0000 0100

RDSR Read Status Register 0000 0101

WRSR Write Status Register 0000 0001

READ Read from Memory Array 0000 0011

WRITE Write to Memory Array 0000 0010

AI02281E

21 34567

High Impedance

Instruction

M95320, M95640, M95320-x, M95640-x Instructions

17/45

6.2 Write Disable (WRDI)

One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction

to the device.

As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven low,

and the bits of the instruction byte are shifted in, on Serial Data Input (D).

The device then enters a wait state. It waits for a the device to be deselected, by Chip Select

(S) being driven high.

The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:

●Power-up

●WRDI instruction execution

●WRSR instruction completion

●WRITE instruction completion.

Figure 8. Write Disable (WRDI) sequence

AI03750D

21 34567

High Impedance

Instruction

Instructions M95320, M95640, M95320-x, M95640-x

18/45

6.3 Read Status Register (RDSR)

The Read Status Register (RDSR) instruction allows the Status Register to be read. The

Status Register may be read at any time, even while a Write or Write Status Register cycle

is in progress. When one of these cycles is in progress, it is recommended to check the

Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible

to read the Status Register continuously, as shown in Figure 9.

The Status Register format is shown in Ta b l e 4 and the status and control bits of the Status

6.3.1 WIP bit

The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write

Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such

cycle is in progress.

6.3.2 WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.

When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable

Latch is reset and no Write or Write Status Register instruction is accepted.

6.3.3 BP1, BP0 bits

The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be

software protected against Write instructions. These bits are written with the Write Status

1, the relevant memory area (as defined in Ta bl e 4 ) becomes protected against Write

(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the

Hardware Protected mode has not been set.

6.3.4 SRWD bit

The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write

Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)

signal allow the device to be put in the Hardware Protected mode (when the Status Register

Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this mode, the

non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the

Write Status Register (WRSR) instruction is no longer accepted for execution.

Table 4. Status Register format

b7 b0

SRWD 0 0 0 BP1 BP0 WEL WIP

Status Register Write Protect

Block Protect bits

Write Enable Latch bit

Write In Progress bit

M95320, M95640, M95320-x, M95640-x Instructions

19/45

Figure 9. Read Status Register (RDSR) sequence

6.4 Write Status Register (WRSR)

The Write Status Register (WRSR) instruction allows new values to be written to the Status

have been executed. After the Write Enable (WREN) instruction has been decoded and

executed, the device sets the Write Enable Latch (WEL).

The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low,

followed by the instruction code and the data byte on Serial Data Input (D).

The instruction sequence is shown in Figure 10.

The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the

Status Register. b6, b5 and b4 are always read as 0.

Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that latches in

the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise,

the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (S) is

driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated.

While the Write Status Register cycle is in progress, the Status Register may still be read to

check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1

during the self-timed Write Status Register cycle, and is 0 when it is completed. When the

cycle is completed, the Write Enable Latch (WEL) is reset.

The Write Status Register (WRSR) instruction allows the user to change the values of the

Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-

only, as defined in Ta b le 4 .

The Write Status Register (WRSR) instruction also allows the user to set or reset the Status

Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to

be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR)

instruction is not executed once the Hardware Protected Mode (HPM) is entered.

The contents of the Status Register Write Disable (SRWD) and Block Protect (BP1, BP0)

bits are frozen at their current values from just before the start of the execution of Write

Status Register (WRSR) instruction. The new, updated, values take effect at the moment of

completion of the execution of Write Status Register (WRSR) instruction.

21 3456789101112131415

Instruction

AI02031E

Q76543210

Status Register Out

High Impedance

MSB

76543210

Status Register Out

MSB

Instructions M95320, M95640, M95320-x, M95640-x

20/45

The protection features of the device are summarized in Ta bl e 2 .

When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial

delivery state), it is possible to write to the Status Register provided that the Write Enable

Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless

of the whether Write Protect (W) is driven high or low.

When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two

cases need to be considered, depending on the state of Write Protect (W):

●If Write Protect (W) is driven high, it is possible to write to the Status Register provided

that the Write Enable Latch (WEL) bit has previously been set by a Write Enable

(WREN) instruction.

●If Write Protect (W) is driven low, it is not possible to write to the Status Register even if

the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN)

instruction. (Attempts to write to the Status Register are rejected, and are not accepted

for execution). As a consequence, all the data bytes in the memory area that are

software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register,

are also hardware protected against data modification.

Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be

entered:

●by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)

low

●or by driving Write Protect (W) low after setting the Status Register Write Disable

(SRWD) bit.

The only way to exit the Hardware Protected mode (HPM) once entered is to pull Write

Protect (W) high.

If Write Protect (W) is permanently tied high, the Hardware Protected mode (HPM) can

never be activated, and only the Software Protected mode (SPM), using the Block Protect

(BP1, BP0) bits of the Status Register, can be used.

Table 5. Protection modes

signal

SRWD

bit Mode Write protection of the

Status Register

Memory content

Protected area(1)

1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2.

Unprotected area(1)

Software

Protected

(SPM)

Status Register is Writable

(if the WREN instruction has

set the WEL bit)

The values in the BP1 and

BP0 bits can be changed

Write Protected Ready to accept

Write instructions

Hardware

Protected

(HPM)

Status Register is Hardware

write protected

The values in the BP1 and

BP0 bits cannot be changed

Write Protected Ready to accept

Write instructions

M95320, M95640, M95320-x, M95640-x Instructions

21/45

Figure 10. Write Status Register (WRSR) sequence

Table 6. Address range bits(1)

1. b15 to b13 are Don’t Care on the 64 Kbit devices.

b15 to b12 are Don’t Care on the 32 Kbit devices.

Device 32 Kbit devices 64 Kbit devices

Address bits A11-A0 A12-A0

AI02282D

21 3456789101112131415

High Impedance

Instruction Status

765432 0

MSB

Instructions M95320, M95640, M95320-x, M95640-x

22/45

6.5 Read from Memory Array (READ)

As shown in Figure 11, to send this instruction to the device, Chip Select (S) is first driven

low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data

Input (D). The address is loaded into an internal address register, and the byte of data at

that address is shifted out, on Serial Data Output (Q).

If Chip Select (S) continues to be driven low, the internal address register is automatically

incremented, and the byte of data at the new address is shifted out.

When the highest address is reached, the address counter rolls over to zero, allowing the

Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a

single READ instruction.

The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip

Select (S) signal can occur at any time during the cycle.

The first byte addressed can be any byte within any page.

The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.

Figure 11. Read from Memory Array (READ) sequence

1. Depending on the memory size, as shown in Table 6, the most significant address bits are Don’t Care.

AI01793D

21 345678910 2021222324252627

1413 3210

28 29 30

76543 1 7

High Impedance Data Out 1

Instruction 16-Bit Address

MSB

Data Out 2

M95320, M95640, M95320-x, M95640-x Instructions

23/45

6.6 Write to Memory Array (WRITE)

As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven

low. The bits of the instruction byte, address byte, and at least one data byte are then shifted

in, on Serial Data Input (D).

The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input

data. In the case of Figure 12, this occurs after the eighth bit of the data byte has been

latched in, indicating that the instruction is being used to write a single byte. The self-timed

Write cycle starts from the rising edge of Chip Select (S), and continues for a period tWC (as

specified in Ta b l e 1 8 to Ta bl e 2 0 ), at the end of which the Write in Progress (WIP) bit is reset

to 0.

If, though, Chip Select (S) continues to be driven low, as shown in Figure 13, the next byte of

input data is shifted in, so that more than a single byte, starting from the given address

towards the end of the same page, can be written in a single internal Write cycle.

Each time a new data byte is shifted in, the least significant bits of the internal address

counter are incremented. If the number of data bytes sent to the device exceeds the page

boundary, the internal address counter rolls over to the beginning of the page, and the

previous data there are overwritten with the incoming data. (The page size of these devices

is 32 bytes).

The instruction is not accepted, and is not executed, under the following conditions:

●if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable

instruction just before)

●if a Write cycle is already in progress

●if the device has not been deselected, by Chip Select (S) being driven high, at a byte

boundary (after the eighth bit, b0, of the last data byte that has been latched in)

●if the addressed page is in the region protected by the Block Protect (BP1 and BP0)

bits.

Figure 12. Byte Write (WRITE) sequence

1. Depending on the memory size, as shown in Table 6, the most significant address bits are Don’t Care.

AI01795D

21 345678910 2021222324252627

1413 3210

28 29 30

High Impedance

Instruction 16-Bit Address

765432 0

Data Byte

Instructions M95320, M95640, M95320-x, M95640-x

24/45

Figure 13. Page Write (WRITE) sequence

1. Depending on the memory size, as shown in Table 6, the most significant address bits are Don’t Care.

AI01796D

3433 35 36 37 38 39 40 41 42 44 45 46 4732

21 345678910 2021222324252627

1413 3210

28 29 30

Instruction 16-Bit Address

765432 0

Data Byte 1

765432 0

Data Byte 2

765432 0

Data Byte 3

65432 0

Data Byte N

M95320, M95640, M95320-x, M95640-x Power-up and delivery state

25/45

7 Power-up and delivery state

7.1 Power-up state

After Power-up, the device is in the following state:

●Standby Power mode

●deselected (after power-up, a falling edge is required on Chip Select (S) before any

instructions can be started).

●not in the Hold condition

●the Write Enable Latch (WEL) is reset to 0

●Write In Progress (WIP) is reset to 0

The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous

power-down (they are non-volatile bits).

7.2 Initial delivery state

The device is delivered with the memory array set at all 1s (FFh). The Status Register Write

Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.

Maximum rating M95320, M95640, M95320-x, M95640-x

26/45

8 Maximum rating

Stressing the device outside the ratings listed in Ta bl e 7 may cause permanent damage to

the device. These are stress ratings only, and operation of the device at these, or any other

conditions outside those indicated in the operating sections of this specification, is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability. Refer also to the STMicroelectronics SURE Program and other relevant

quality documents.

Table 7. Absolute maximum ratings

Symbol Parameter Min. Max. Unit

TSTG Storage temperature –65 150 °C

TAAmbient operating temperature –40 130 °C

TLEAD Lead temperature during soldering See note (1)

1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®

7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)

2002/95/EU

°C

VOOutput voltage –0.50 VCC+0.6 V

VIInput voltage –0.50 6.5 V

VCC Supply voltage –0.50 6.5 V

VESD

Electrostatic discharge voltage (human body

model)(2)

2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω)

–4000 4000 V

M95320, M95640, M95320-x, M95640-x DC and AC parameters

27/45

9 DC and AC parameters

This section summarizes the operating and measurement conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC characteristic tables that

follow are derived from tests performed under the measurement conditions summarized in

the relevant tables. Designers should check that the operating conditions in their circuit

match the measurement conditions when relying on the quoted parameters.

Figure 14. AC measurement I/O waveform

Table 8. Operating conditions (M95320 and M95640)

Symbol Parameter Min. Max. Unit

VCC Supply voltage 4.5 5.5 V

TAAmbient operating temperature (device grade 3) –40 125 °C

Table 9. Operating conditions (M95320-W and M95640-W)

Symbol Parameter Min. Max. Unit

VCC Supply voltage 2.5 5.5 V

Ambient operating temperature (device grade 6) –40 85 °C

Ambient operating temperature (device grade 3) –40 125 °C

Table 10. Operating conditions (M95320-R and M95640-R)

Symbol Parameter Min.(1)

1. This product is under development. For more information, please contact your nearest ST sales office.

Max. (1) Unit

VCC Supply voltage 1.8 5.5 V

TAAmbient operating temperature –40 85 °C

Table 11. AC measurement conditions(1)

1. Output Hi-Z is defined as the point where data out is no longer driven.

Symbol Parameter Min. Typ. Max. Unit

CLLoad capacitance 30 pF

Input rise and fall times 50 ns

Input pulse voltages 0.2VCC to 0.8VCC V

Input and output timing reference voltages 0.3VCC to 0.7VCC V

AI00825B

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Input and Output

Timing Reference Levels

Input Levels

DC and AC parameters M95320, M95640, M95320-x, M95640-x

28/45

Table 12. Capacitance(1)

1. Sampled only, not 100% tested, at TA=25°C and a frequency of 5MHz.

Symbol Parameter Test condition Min.Max.Unit

COUT Output capacitance (Q) VOUT = 0 V 8 pF

CIN Input capacitance (D) VIN = 0 V 8 pF

Input capacitance (other pins) VIN = 0 V 6 pF

Table 13. DC characteristics (M95320 and M95640, device grade 3)

Symbol Parameter Test condition Min. Max. Unit

ILI Input leakage current VIN = VSS or VCC ± 2 µA

ILO Output leakage current S = VCC, VOUT = VSS or VCC ± 2 µA

ICC Supply current C=0.1V

CC/0.9VCC at 5 MHz,

VCC = 5V, Q = open 4mA

ICC1

Supply current

(Standby)

S = VCC, VCC = 5 V,

VIN = VSS or VCC

5µA

VIL Input low voltage –0.45 0.3 VCC V

VIH Input high voltage 0.7 VCC VCC+1 V

VOL(1)

1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.

Output low voltage IOL = 2 mA, VCC = 5 V 0.4 V

VOH(1) Output high voltage IOH = –2 mA, VCC = 5 V 0.8 VCC V

M95320, M95640, M95320-x, M95640-x DC and AC parameters

29/45

Table 14. DC characteristics (M95320-W and M95640-W, device grade 6)

Symbol Parameter Test condition Min. Max. Unit

ILI Input leakage current VIN = VSS or VCC ± 2 µA

ILO Output leakage current S = VCC, VOUT = VSS or VCC ± 2 µA

ICC Supply current

C = 0.1VCC/0.9VCC at 5 MHz,

VCC = 2.5 V, Q = open 3mA

C = 0.1VCC/0.9VCC at 10 MHz,

VCC = 3.0 V, Q = open 4mA

ICC1

Supply current

(Standby)

S = VCC, VCC = 2.5 V

VIN = VSS or VCC

1µA

S = VCC, VCC = 5.0 V

VIN = VSS or VCC

2µA

VIL Input low voltage –0.45 0.3VCC V

VIH Input high voltage 0.7VCC VCC+1 V

VOL Output low voltage IOL = 1.5 mA, VCC = 2.5 V or

IOL = 2 mA, VCC = 5.5 V 0.4 V

VOH Output high voltage IOH = –0.4 mA, VCC = 2.5 V or

IOH = –2 mA, VCC = 5.5 V 0.8VCC V

Table 15. DC characteristics (M95320-W and M95640-W, device grade 3)

Symbol Parameter Test condition Min. Max. Unit

ILI Input leakage current VIN = VSS or VCC ± 2 µA

ILO Output leakage current S = VCC, VOUT = VSS or VCC ± 2 µA

ICC Supply current C = 0.1VCC/0.9VCC at 5 MHz,

VCC = 2.5 V, Q = open 3mA

ICC1 Supply current (Standby) S = VCC, VCC = 2.5 V, VIN = VSS or VCC 2µA

VIL Input low voltage –0.45 0.3VCC V

VIH Input high voltage 0.7VCC VCC+1 V

VOL Output low voltage IOL = 1.5 mA, VCC = 2.5 V 0.4 V

VOH Output high voltage IOH = –0.4 mA, VCC = 2.5 V 0.8VCC V

DC and AC parameters M95320, M95640, M95320-x, M95640-x

30/45

Table 16. DC characteristics (M95320-R and M95640-R)

Symbol Parameter Test condition Min. Max. Unit

ILI Input leakage current VIN = VSS or VCC ± 1 µA

ILO Output leakage current S = VCC, VOUT = VSS or VCC ± 1 µA

ICC Supply current

C = 0.1VCC/0.9VCC at max clock

frequency, 1.8 V < VCC =2.5V,

Q = open

3mA

ICC1 Supply current (Standby) S = VCC, VIN = VSS or VCC,

1.8 V < VCC =2.5V 1µA

VIL Input low voltage 1.8 V ≤ VCC < 2.5 V –0.45 0.25VCC V

2.5 V ≤ VCC < 5.5 V –0.45 0.3VCC V

VIH Input high voltage 1.8 V ≤ VCC < 2.5 V 0.75VCC VCC+1 V

2.5 V ≤ VCC < 5.5 V 0.7 VCC VCC+1 V

VOL Output low voltage IOL = 0.15 mA, VCC = 1.8 V 0.3 V

VOH Output high voltage IOH = –0.1 mA, VCC = 1.8 V 0.8 VCC V

M95320, M95640, M95320-x, M95640-x DC and AC parameters

31/45

Table 17. AC characteristics (M95320 and M95640, device grade 3)

Test conditions specified in Table 10 and Table 1 1

Symbol Alt. Parameter Min. Max. Unit

fCfSCK Clock frequency D.C. 5 MHz

tSLCH tCSS1 S active setup time 90 ns

tSHCH tCSS2 S not active setup time 90 ns

tSHSL tCS S deselect time 100 ns

tCHSH tCSH S active hold time 90 ns

tCHSL S not active hold time 90 ns

tCH(1)

1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).

tCLH Clock high time 90 ns

tCL(1) tCLL Clock low time 90 ns

tCLCH(2)

2. Value guaranteed by characterization, not 100% tested in production.

tRC Clock rise time 1 µs

tCHCL(2) tFC Clock fall time 1 µs

tDVCH tDSU Data in setup time 20 ns

tCHDX tDH Data in hold time 30 ns

tHHCH Clock low hold time after HOLD not active 70 ns

tHLCH Clock low hold time after HOLD active 40 ns

tCLHL Clock low set-up time before HOLD active 0 ns

tCLHH Clock low set-up time before HOLD not active 0 ns

tSHQZ(2) tDIS Output disable time 100 ns

tCLQV tVClock low to output valid 60 ns

tCLQX tHO Output hold time 0 ns

tQLQH(2) tRO Output rise time 50 ns

tQHQL(2) tFO Output fall time 50 ns

tHHQV tLZ HOLD high to output valid 50 ns

tHLQZ(2) tHZ HOLD low to output high-Z 100 ns

tWtWC Write time 5 ms

DC and AC parameters M95320, M95640, M95320-x, M95640-x

32/45

Table 18. AC characteristics (M95320-W and M95640-W, device grade 6)

Test conditions specified in Tabl e 11 and Ta ble 9

Symbol Alt. Parameter Min. Max. Unit

fCfSCK Clock frequency D.C. 10 MHz

tSLCH tCSS1 S active setup time 30 ns

tSHCH tCSS2 S not active setup time 30 ns

tSHSL tCS S deselect time 40 ns

tCHSH tCSH S active hold time 30 ns

tCHSL S not active hold time 30 ns

tCH(1)

1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).

tCLH Clock high time 42 ns

tCL(1) tCLL Clock low time 40 ns

tCLCH(2)

2. Value guaranteed by characterization, not 100% tested in production.

tRC Clock rise time 2 µs

tCHCL(2) tFC Clock fall time 2 µs

tDVCH tDSU Data in setup time 10 ns

tCHDX tDH Data in hold time 10 ns

tHHCH Clock low hold time after HOLD not active 30 ns

tHLCH Clock low hold time after HOLD active 30 ns

tCLHL Clock low set-up time before HOLD active 0 ns

tCLHH Clock low set-up time before HOLD not active 0 ns

tSHQZ(2) tDIS Output disable time 40 ns

tCLQV tVClock low to output valid 40 ns

tCLQX tHO Output hold time 0 ns

tQLQH(2) tRO Output rise time 40 ns

tQHQL(2) tFO Output fall time 40 ns

tHHQV tLZ HOLD high to output valid 40 ns

tHLQZ(2) tHZ HOLD low to output high-Z 40 ns

tWtWC Write time 5 ms

M95320, M95640, M95320-x, M95640-x DC and AC parameters

33/45

Table 19. AC characteristics (M95320-W and M95640-W, device grade 3)

Test conditions specified in Ta ble 11 and Tab l e 9

Symbol Alt. Parameter Min. Max. Unit

fCfSCK Clock frequency D.C. 5 MHz

tSLCH tCSS1 S active setup time 90 ns

tSHCH tCSS2 S not active setup time 90 ns

tSHSL tCS S deselect time 100 ns

tCHSH tCSH S active hold time 90 ns

tCHSL S not active hold time 90 ns

tCH(1)

1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).

tCLH Clock high time 90 ns

tCL(1) tCLL Clock low time 90 ns

tCLCH(2)

2. Value guaranteed by characterization, not 100% tested in production.

tRC Clock rise time 1 µs

tCHCL(2) tFC Clock fall time 1 µs

tDVCH tDSU Data in setup time 20 ns

tCHDX tDH Data in hold time 30 ns

tHHCH Clock low hold time after HOLD not active 70 ns

tHLCH Clock low hold time after HOLD active 40 ns

tCLHL Clock low set-up time before HOLD active 0 ns

tCLHH Clock low set-up time before HOLD not active 0 ns

tSHQZ(2) tDIS Output disable time 100 ns

tCLQV tVClock low to output valid 60 ns

tCLQX tHO Output hold time 0 ns

tQLQH(2) tRO Output rise time 50 ns

tQHQL(2) tFO Output fall time 50 ns

tHHQV tLZ HOLD high to output valid 50 ns

tHLQZ(2) tHZ HOLD low to output high-Z 100 ns

tWtWC Write time 5 ms

DC and AC parameters M95320, M95640, M95320-x, M95640-x

34/45

Table 20. AC characteristics (M95320-R)

Test conditions specified in Table 11 and Table 1 0

Symbol Alt. Parameter Min. Max. Unit

fCfSCK Clock frequency D.C. 5 MHz

tSLCH tCSS1 S active setup time 60 ns

tSHCH tCSS2 S not active setup time 60 ns

tSHSL tCS S deselect time 90 ns

tCHSH tCSH S active hold time 60 ns

tCHSL S not active hold time 60 ns

tCH(1)

1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).

tCLH Clock high time 90 ns

tCL(1) tCLL Clock low time 90 ns

tCLCH(2)

2. Value guaranteed by characterization, not 100% tested in production.

tRC Clock rise time 2 µs

tCHCL(2) tFC Clock fall time 2 µs

tDVCH tDSU Data in setup time 20 ns

tCHDX tDH Data in hold time 20 ns

tHHCH Clock low hold time after HOLD not active 60 ns

tHLCH Clock low hold time after HOLD active 60 ns

tCLHL Clock low set-up time before HOLD active 0 0

tCLHH Clock low set-up time before HOLD not active 0 0

tSHQZ(2) tDIS Output disable time 80 ns

tCLQV tVClock low to output valid 80 ns

tCLQX tHO Output hold time 0 ns

tQLQH(2) tRO Output rise time 80 ns

tQHQL(2) tFO Output fall time 80 ns

tHHQV tLZ HOLD high to output valid 80 ns

tHLQZ(2) tHZ HOLD low to output high-Z 80 ns

tWtWC Write time 5 ms

M95320, M95640, M95320-x, M95640-x DC and AC parameters

35/45

Table 21. AC characteristics (M95640-R)

Test conditions specified in Table 1 0 and Tab le 1 1

Symbol Alt. Parameter Min. Max. Unit

fCfSCK Clock frequency D.C. 2 MHz

tSLCH tCSS1 S active setup time 150 ns

tSHCH tCSS2 S not active setup time 150 ns

tSHSL tCS S deselect time 200 ns

tCHSH tCSH S active hold time 150 ns

tCHSL S not active hold time 150 ns

tCH(1)

1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).

tCLH Clock high time 200 ns

tCL(1) tCLL Clock low time 200 ns

tCLCH(2)

2. Value guaranteed by characterization, not 100% tested in production.

tRC Clock rise time 2 µs

tCHCL(2) tFC Clock fall time 2 µs

tDVCH tDSU Data in setup time 50 ns

tCHDX tDH Data in hold time 50 ns

tHHCH Clock low hold time after HOLD not active 150 ns

tHLCH Clock low hold time after HOLD active 150 ns

tCLHL Clock low set-up time before HOLD active 0 0

tCLHH Clock low set-up time before HOLD not active 0 0

tSHQZ(2) tDIS Output disable time 200 ns

tCLQV tVClock low to output valid 200 ns

tCLQX tHO Output hold time 0 ns

tQLQH(2) tRO Output rise time 200 ns

tQHQL(2) tFO Output fall time 200 ns

tHHQV tLZ HOLD high to output valid 200 ns

tHLQZ(2) tHZ HOLD low to output high-Z 200 ns

tWtWC Write time 5 ms

DC and AC parameters M95320, M95640, M95320-x, M95640-x

36/45

Figure 15. Serial Input timing

Figure 16. Hold timing

AI01447C

MSB IN

tDVCH

High Impedance

LSB IN

tSLCH

tCHDX

tCHCL

tCLCH

tSHCH

tSHSL

tCHSHtCHSL

AI01448B

HOLD

tCLHL

tHLCH

tHHCH

tCLHH

tHHQVtHLQZ

M95320, M95640, M95320-x, M95640-x DC and AC parameters

37/45

Figure 17. Output timing

AI01449e

LSB OUT

DADDR.

LSB IN

tSHQZ

tCH

tCL

tQLQH

tQHQL

tCLQX

tCLQV

tCLQX

tCLQV

Package mechanical M95320, M95640, M95320-x, M95640-x

38/45

10 Package mechanical

Figure 18. SO8N – 8 lead plastic small outline, 150 mils body width, package outline

1. Drawing is not to scale.

Table 22. SO8N – 8 lead plastic small outline, 150 mils body width, package

mechanical data

Symbol

millimeters inches(1)

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Typ Min Max Typ Min Max

A 1.75 0.0689

A1 0.10 0.25 0.0039 0.0098

A2 1.25 0.0492

b 0.28 0.48 0.011 0.0189

c 0.17 0.23 0.0067 0.0091

ccc 0.10 0.0039

D 4.90 4.80 5.00 0.1929 0.189 0.1969

E 6.00 5.80 6.20 0.2362 0.2283 0.2441

E1 3.90 3.80 4.00 0.1535 0.1496 0.1575

e1.27– –0.05 - -

h 0.25 0.50 0.0098 0.0197

k0°8°0°8°

L 0.40 1.27 0.0157 0.05

L1 1.04 0.0409

SO-A

ccc

h x 45˚

0.25 mm

GAUGE PLANE

M95320, M95640, M95320-x, M95640-x Package mechanical

39/45

Figure 19. TSSOP8 – 8 lead thin shrink small outline, package outline

1. Drawing is not to scale.

Table 23. TSSOP8 – 8 lead thin shrink small outline, package mechanical data

Symbol

millimeters inches(1)

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Typ. Min. Max. Typ. Min. Max.

A 1.200 0.0472

A1 0.050 0.150 0.0020 0.0059

A2 1.000 0.800 1.050 0.0394 0.0315 0.0413

b 0.190 0.300 0.0075 0.0118

c 0.090 0.200 0.0035 0.0079

CP 0.100 0.0039

D 3.000 2.900 3.100 0.1181 0.1142 0.1220

e 0.650 – – 0.0256 – –

E 6.400 6.200 6.600 0.2520 0.2441 0.2598

E1 4.400 4.300 4.500 0.1732 0.1693 0.1772

L 0.600 0.450 0.750 0.0236 0.0177 0.0295

L1 1.000 0.0394

α0° 8° 0° 8°

TSSOP8AM

EE1

A2A

Package mechanical M95320, M95640, M95320-x, M95640-x

40/45

Figure 20. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package

outline

1. Drawing is not to scale.

Table 24. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package

mechanical data

Symbol

millimeters inches(1)

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Typ Min Max Typ Min Max

A 0.55 0.45 0.6 0.0217 0.0177 0.0236

A1 0.02 0 0.05 0.0008 0 0.002

b 0.25 0.2 0.3 0.0098 0.0079 0.0118

D 2 1.9 2.1 0.0787 0.0748 0.0827

D2 1.6 1.5 1.7 0.063 0.0591 0.0669

E 3 2.9 3.1 0.1181 0.1142 0.122

E2 0.2 0.1 0.3 0.0079 0.0039 0.0118

e 0.5 - - 0.0197 - -

L 0.45 0.4 0.5 0.0177 0.0157 0.0197

L1 0.15 0.0059

L3 0.3 0.0118

ddd(2)

2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from

measurement.

0.08 0.08

UFDFPN-01

ddd

M95320, M95640, M95320-x, M95640-x Part numbering

41/45

11 Part numbering

For a list of available options (speed, package, etc.) or for further information on any aspect

of this device, please contact your nearest ST sales office.

The category of second-level interconnect is marked on the package and on the inner box

label, in compliance with JEDEC Standard JESD97. The maximum ratings related to

soldering conditions are also marked on the inner box label.

Table 25. Ordering information scheme

Example: M95640 – W MN 6 T P /P

Device type

M95 = SPI serial access EEPROM

Device function

640 = 64 Kbit (8192 x 8)

320 = 32 Kbit (4096 x 8)

Operating voltage

blank = VCC = 4.5 to 5.5 V

W = VCC = 2.5 to 5.5 V

R = VCC = 1.8 to 5.5 V

Package

MN = SO8 (150 mils width)

DW = TSSOP8 (169 mils width)

MB = MLP8 (2x3 mm)

Device grade

6 = Industrial temperature range, –40 to 85 °C.

Device tested with standard test flow

3 = Device tested with high reliability certified flow(1)automotive temperature range

(–40 to 125 °C)

1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment.

The high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask your

nearest ST sales office for a copy.

Option

blank = Standard Packing

T = Tape and Reel Packing

Plating technology

P or G = ECOPACK (RoHS compliant)

Process letter(2)

2. The Process letter only concerns Grade-3 devices.

/P or /PB = DP26% Chartered

Part numbering M95320, M95640, M95320-x, M95640-x

42/45

Table 26. Available M95320x products (package, voltage range, temperature grade)

Package M95320

4.5 V to 5.5 V

M95320-W

2.5 V to 5.5 V

M95320-R

1.8 V to 5.5 V

SO8 (MN) Range 3 Range 6

Range 3 Range 6

TSSOP (DW) - Range 6 Range 6

MLP 2 × 3 mm (MB) - - Range 6

Table 27. Available M95640x products (package, voltage range, temperature grade)

Package M95640

4.5 V to 5.5 V

M95640-W

2.5 V to 5.5 V

M95640-R

1.8 V to 5.5 V

SO8 (MN) Range 3 Range 6

Range 3 Range 6

TSSOP (DW) - - Range 6

M95320, M95640, M95320-x, M95640-x Revision history

43/45

12 Revision history

Table 28. Document revision history

Date Revision Changes

13-Jul-2000 1.2

Human Body Model meets JEDEC std (Table 2). Minor adjustments on pp

1,11,15. New clause on p7. Addition of TSSOP8 package on pp 1, 2,

Ordering Info, Mechanical Data

16-Mar-2001 1.3

Test condition added ILI and ILO, and specification of tDLDH and tDHDL

removed.

tCLCH, tCHCL, tDLDH and tDHDL changed to 50ns for the -V range.

“-V” Voltage range changed to “2.7V to 3.6V” throughout.

Maximum lead soldering time and temperature conditions updated.

Instruction sequence illustrations updated.

“Bus Master and Memory Devices on the SPI bus” illustration updated.

Package Mechanical data updated

19-Jul-2001 1.4 M95160 and M95080 devices removed to their own data sheet

06-Dec-2001 1.5 Endurance increased to 1M write/erase cycles

Instruction sequence illustrations updated

18-Dec-2001 2.0 Document reformatted using the new template. No parameters changed.

08-Feb-2002 2.1

Announcement made of planned upgrade to 10MHz clock for the 5V, –40

to 85°C, range.

Endurance set to 100K write/erase cycles

18-Dec-2002 2.2

10MHz, 5MHz, 2MHz clock; 5ms, 10ms Write Time; 100K, 1M erase/write

cycles distinguished on front page, and in the DC and AC Characteristics

tables

26-Mar-2003 2.3 Process identification letter corrected in footnote to AC Characteristics

table for temp. range 3

26-Jun-2003 2.4 -S voltage range upgraded by removing it and inserting -R voltage range

in its place

15-Oct-2003 3.0 Table of contents, and Pb-free options added. VIL(min) improved to -0.45V

21-Nov-2003 3.1 VI(min) and VO(min) corrected (improved) to -0.45V

28-Jan-2004 4.0 TSSOP8 connections added to DIP and SO connections

24-May-2005 5.0

M95320-S and M95640-S root part numbers (1.65 to 5.5V Supply) and

related characteristics added.

20MHz Clock rate added.TSSOP14 package removed and MLP8 package

added.

Description of Power On Reset: VCC Lock-Out Write Protect updated.

Product List summary table added. Absolute Maximum Ratings for

VIO(min) and VCC(min) improved. Soldering temperature information

clarified for RoHS compliant devices. Device Grade 3 clarified, with

reference to HRCF and automotive environments. AEC-Q100-002

compliance. tCHHL(min) and tCHHH(min) is tCH for products under “S”

process. tHHQX corrected to tHHQV

Figure 16: Hold timing updated.

Revision history M95320, M95640, M95320-x, M95640-x

44/45

07-Jul-2006 6

Document converted to new ST template.

Packages are ECOPACK® compliant. PDIP package removed.

SO8N package specifications updated (see Ta bl e 2 2 and Figure 18).

M95640-S and M95320-S part numbers removed (DC and AC parameters

updated accordingly).

How to identify previous, current and new products by the Process

identification letter Table removed.

Figure 4: SPI modes supported updated and Note 2 added. First three

paragraphs of Section 4: Operating features replaced by Section 4.1:

Supply voltage (VCC).

TA added to Table 7: Absolute maximum ratings. ICC and ICC1 updated in

Ta bl e 1 3 , Ta b l e 1 3 , Tabl e 1 4 and Tabl e 1 6 . VOL and VOH updated in

Ta bl e 1 4 . ICC updated in Ta b l e 1 5 . Data in Ta bl e 1 6 is no longer

preliminary.

tCH updated in Ta b l e 1 8 . Table 21: AC characteristics (M95640-R) added.

Timing line of tSHQZ modified in Figure 17: Output timing.

Process letter added to Table 25: Ordering information scheme, Note 2

removed. Note 2 removed from Figure 2.

09-Oct-2007 7

JEDEC standard revision updated to D in Note 1 below Table 7: Absolute

maximum ratings.

Note 2 removed below Figure 3 and explanatory paragraph added.

Section 4.1: Supply voltage (VCC) updated. Table 6: Address range bits

corrected.

Products operating at VCC = 4.5 V to 5.5 V are no longer available in the

device grade 6 TA temperature range.

ICC and ICC1 parameters modified in Table 14: DC characteristics

(M95320-W and M95640-W, device grade 6).

Maximum frequency for M95640-W and M95320-W upgraded from 5 MHz

to 10 MHz in the device grade 6 TA temperature range (Table 18: AC

characteristics (M95320-W and M95640-W, device grade 6) modified

accordingly).

Table 27: Available M95640x products (package, voltage range,

temperature grade): /PB process letter added, /P process letter removed.

Blank option removed below Plating technology in Table 25: Ordering

information scheme.

Ta bl e 2 6 and Ta b l e 2 7 added. Small text changes.

Table 24: UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead,

package mechanical data updated.

Package mechanical inch values calculated from mm and rounded to 4

decimal digits in Section 10: Package mechanical.

17-Dec-2007 8

Section 2.7: VSS ground added.

Device behavior when VCC passes over the POR threshold updated (see

Section 4.1.3: Device reset and Section 4.1.4: Power-down).

VIL and VIH modified in Table 16: DC characteristics (M95320-R and

M95640-R).

tW, write time, modified in Table 20: AC characteristics (M95320-R) and

Table 21: AC characteristics (M95640-R). Small text changes.

Table 28. Document revision history (continued)

Date Revision Changes

M95320, M95640, M95320-x, M95640-x

45/45

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