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Semiconductor
MSM5117400D
4,194,304-Word ×
××
× 4-Bit DYNAMIC RAM : FAST PAG E MODE TY PE
DESCRIPTION
The MSM5117400D is a 4,194,304-word × 4-bit dynamic RAM fabricated in Oki’s silicon-gate CMOS
technology. The MSM5117400D achieves high integration, high-speed operation, and low-power consumption
because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The
MSM5117400D is available in a 26/24-pin plastic SOJ, 26/24-pin plastic TSOP.
FEATURES
•4,194,304-word × 4-bit configuration
•Single 5V power supply, ±10% tolerance
•Input : TTL compatible, low input capacitance
•Output : TTL compatible, 3- st at e
•Refresh : 2048 cycles/32 ms
•Fast page mode, read m o dif y w r it e capabilit y
•CAS before RAS refresh, hidden refresh, RAS-only refresh capability
•Multi-bit te st m ode capabilit y
•Package options:
26/24-pin 300mil plastic SOJ (SOJ26/24-P-300-1.27) (Product : MSM5117400D-xxSJ)
26/24-pin 300mil plastic TSOP (TSOPII26/24-P-300-1.27-K) (Product : MSM5117400D-xxTS-K)
xx : indicates speed rank.
PRODUCT FAMI LY
Access Time (Max.) Power Dissipation
Family tRAC tAA tCAC tOEA
Cycle Time
(Min.) Operating (Max.) Standby (Max.)
MSM5117400D-50 50ns 25ns 13ns 13ns 90ns 550mW
MSM5117400D-60 60ns 30ns 15ns 15ns 110ns 495mW
MSM5117400D-70 70ns 35ns 20ns 20ns 130ns 440mW
5.5mW
This version: Jun. 2000
MSM5117400D
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PIN CONFIGRATION (TOP VIEW)
Pin Name Function
A0–A10 Address Input
RAS Row Address Strobe
CAS Column Address Strobe
DQ1–DQ4 Data Input/Data Output
OE Output Enable
WE Write Enable
VCC Power Supply (5V)
VSS Ground (0V)
NC No Connection
26/24-Pin Plastic SOJ 26/24-Pin Plastic TSOP
(K Type)
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
DQ1
DQ2
VCC
VCC
VSS
VSS
DQ4
DQ3
A9
A8
A7
A6
A0
A1
A2
A3
WE
RAS
NC
A10
A5
A4
CAS
OE
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
DQ1
DQ2
VCC
VCC
VSS
VSS
A9
A8
A7
A6
A0
A1
A2
A3
WE
RAS
NC
A10
A5
A4
OE
DQ4
DQ3
CAS
MSM5117400D
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BLOCK DIAGRAM
A0
–
A10
4
4
4
4
44
11
1111
11
Timing
Generator
Column
Address
Buffers
Internal
Address
Counter
Row
Address
Buffers
Refresh
Control Clock
Column Decoders
Sense Amplifiers
Memory
Cells
Word
Drivers
Row
Deco-
ders
I/O
Selector Input
Buffers
Output
Buffers
DQ1
-
DQ
4
OE
WE
RAS
CAS
V
C
C
V
SS
On Chip
VBB Generator
Timing
Generator
4
Write
Clock
Generator
MSM5117400D
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ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Symbol Rating Unit
Voltage on Any Pin Relative to VSS VIN, VOUT −0.5 to VCC + 0.5 V
Voltage VCC supply Relative to VSS VCC 0.5 to 7.0 V
Short Circuit Output Current IOS 50 mA
Power Dissipation PD* 1W
Operating Temperature Topr 0 to 70 °C
Storage Temperature Tstg −55 to 150 °C
*: Ta = 25°C
Recommended Operating Condi tions
(Ta = 0°C to 70°C)
Parameter Symbol Min. Typ. Max. Unit
VCC 4.5 5.0 5.5 V
Power Supply Voltage VSS 000V
Input High Voltage VIH 2.4 VCC + 0.5*1 V
Input Low Voltage VIL −0.5*2 0.8 V
Notes: *1. The input voltage is VCC + 2.0V when the pulse width is less than 20ns (the pulse width is with
respect to the point at which VCC is applied).
*2. The input voltage is VSS − 2.0V when the pulse width is less than 20ns (the pulse width respect to
the point at which VSS is applied).
Capacitance
(VCC = 5V ± 10%, Ta = 25°C, f=1MHz )
Parameter Symbol Typ. Max. Unit
Input Capacitance (A0 – A10) CIN1 5pF
Input Capacitance
(RAS, CAS, WE, OE) CIN2 7pF
Output Capacitance (DQ1 – DQ4) CI/O 7pF
MSM5117400D
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DC Characteristics
(VCC = 5V ± 10%, Ta = 0°C to 70°C)
MSM5117400
D-50 MSM5117400
D-60 MSM5117400
D-70
Parameter Symbol Condition
Min. Max Min. Max Min. Max
Unit Note
Output High Voltage VOH IOH = −5.0mA 2.4 VCC 2.4 VCC 2.4 VCC V
Output Low Voltage VOL IOL = 4.2mA 00.400.400.4V
Input Leakage
Current ILI
0V ≤ VI ≤ 6.5V ;
All other pins not
under test = 0V −10 10 −10 10 −10 10 µA
Output Leakage
Current ILO DQ disable
0V ≤ VO ≤ VCC −10 10 −10 10 −10 10 µA
Average Power
Supply Current
(Operating) ICC1 RAS, CAS cy cling,
tRC = Min. 100 90 80 mA 1,2
RAS, CAS = VIH 222
Power Supply
Current
(Standby) ICC2 RAS, CAS ≥
VCC – 0.2V 111mA 1
Average Power
Supply Current
(RAS-only Refresh) ICC3
RAS cycling,
CAS = VIH,
tRC = Min. 100 90 80 mA 1,2
Power Supply
Current
(Standby) ICC5
RAS = VIH,
CAS = VIL,
DQ = enable 555mA1
Average Power
Supply Current
(CAS before RAS
Refresh)
ICC6 RAS = cycling,
CAS before RAS 100 90 80 mA 1,2
Average Power
Supply Current
(Fast Page Mode) ICC7
RAS = VIL,
CAS cycling,
tPC = Min. 80 70 60 mA 1,3
Notes: 1. ICC Max. is specified as ICC for output open condition.
2. The address can be changed once or less while RAS = VIL.
3. The address can be changed once or less while CAS = VIH.
MSM5117400D
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AC Characteristic (1/2)
(VCC = 5V ± 10%, Ta = 0°C to 70°C) Note1, 2, 3
MSM5117400
D-50 MSM5117400
D-60 MSM5117400
D-70
Parameter Symbol
Min. Max. Min. Max. Min. Max.
Unit Note
Random Read or Write Cycle Time tRC 90 110 130 ns
Read Modify Write Cycle Time tRWC 131 155 185 ns
Fast Page Mode Cycle Time tPC 35 40 45 ns
Fast Page Mode Read Modify
Write Cycle Time tPRWC 76 85 100 ns
Access Time from RAS tRAC 50 60 70 ns 4,5,6
Access Time from CAS tCAC 13 15 20 ns 4,5
Access Time from Column Address tAA 25 30 35 ns 4,6
Access Time from CAS Precharge tCPA 30 35 40 ns 4
Access Time from OE tOEA 13 15 20 ns 4
Output Low Impedance Time from
CAS tCLZ 000ns 4
CAS to Data Output Buffer Turn-
off Delay Time tOFF 013015020ns7
OE to Data Output Buffer Turn-off
Delay Time tOEZ 013015020ns7
Transition Time tT350350350ns3
Refresh Period tREF 32 32 32 m
RAS Precharge Time tRP 30 40 50 ns
RAS Pulse Width tRAS 50 10,000 60 10,000 70 10,000 ns
RAS Pulse Width (Fast Page Mode) tRASP 50 100,000 60 100,000 70 100,000 ns
RAS Hold Time tRSH 13 15 20 ns
RAS Hold Time referenced to OE tROH 13 15 20 ns
CAS Precharge Time
(Fast Page Mode) tCP 710 10 ns
CAS Pulse Width tCAS 13 10,000 15 10,000 20 10,000 ns
CAS Hold Time tCSH 50 60 70 ns
CAS to RAS Precharge Time tCRP 555ns
RAS Hold Time from CAS Precharge tRHCP 30 35 40 ns
RAS to CAS Delay Time tRCD 17 37 20 45 20 50 ns 5
RAS to Column Address Delay Time tRAD 12 25 15 30 15 35 ns
Row Address Set-up Time tASR 000ns
Row Address Hold Time tRAH 710 10 ns
Column Address Set-up Time tASC 000ns
MSM5117400D
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AC Characteristic (2/2)
(VCC = 5V ± 10%, Ta = 0°C to 70°C) Note1, 2, 3
MSM5117400
D-50 MSM5117400
D-60 MSM5117400
D-70
Parameter Symbol
Min. Max. Min. Max. Min. Max.
Unit Note
Column Address Hold Time tCAH 710 15 ns
Column Address to RAS Lead Time tRAL 25 30 35 ns
Read Command Set-up Time tRCS 000ns
Read Command Hold Time tRCH 000ns 8
Read Command Hold Time
referenced to RAS tRRH 000ns 8
Write Command Set-up Time tWCS 000ns 9
Write Command Hold Time tWCH 710 15 ns
Write Command Pulse Width tWP 710 10 ns
OE Command Hold Time tOEH 13 15 20 ns
Write Command to RAS Lead Time tRWL 13 15 20 ns
Write Command to CAS Lead Time tCWL 13 15 20 ns
Data-in Set-up Time tDS 000ns 10
Data-in Hold Time tDH 710 15 ns 10
OE to Data-in Delay Time tOED 13 15 20 ns
CAS to WE Delay Time tCWD 36 40 50 ns 9
Column Address to WE Delay Time tAWD 48 55 65 ns 9
RAS to WE Delay Time tRWD 73 85 100 ns 9
CAS Precharge WE Delay Time tCPWD 53 60 70 ns 9
CAS Active Delay Time from RAS
Precharge tRPC 555ns
RAS to CAS Set-up Time
(CAS before RAS) tCSR 10 10 10 ns
RAS to CAS Hold Time
(CAS before RAS) tCHR 10 10 10 ns
WE to RAS Precharge Time
(CAS before RAS) tWRP 10 10 10 ns
WE Hold Time from RAS
(CAS before RAS) tWRH 10 10 10 ns
RAS to WE Set-up Time
(Test Mode) tWTS 10 10 10 ns
RAS to WE Hold Time
(Test Mode) tWTH 10 10 10 ns
MSM5117400D
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Notes: 1. A start-up delay of 200µs is required after power-up, followe d by a minimum of eight initializ ation
cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved.
2. The AC characteristics assume tT = 5ns.
3. VIH (Min.) and VIL (Max.) are reference lev els for m easuring input tim ing sig nals. Transition tim es
(tT) are measured between VIH and VIL.
4. This parameter is measured with a load circuit equivalent to 2 TTL load and 100pF.
5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.)
limit, then the access time is controlled by tCAC.
6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.
tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.)
limit, then the access time is controlled by tAA.
7. tOFF (Max.) and tOEZ (Max.) define the time at w hich the output achiev ed the open circuit condition
and are not referenced to output voltage levels.
8. tRCH or tRRH must be satisfied for a read cycle.
9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write
cycle and the data out will remain open circuit (high im pedance) throughout the entire cy cle. If tCWD
≥ tCWD (Min.), tRWD ≥ tRWD(Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a
read modify write cycle and data out will contain data read from the selected cell; if neither of the
above sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
10. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE
leading edge in an OE control write cycle, or a read modify write cycle.
11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is
latched and remains in effect until the exit cycle is generated. I n a test mode C A0 and CA 1 are not
used and each DQ pin now accesses 4-bit locations. Since all 4DQ pins are used, a total of 16 data
bits can be written in parallel into the m em ory array. I n a read cy cle, if 4 data bits are equal, the DQ
pin will indicate a high level. If the 4 data bits are not equal, the DQ pin will indicate a low level.
The test mode is cleared and the memory device returned to its normal operating state by
performing a RAS-only refresh cycle or a CAS before RAS refresh cycle.
12. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified
value. These parameters should be specified in test mode cycle by adding the above value to the
specified value in this data sheet.
MSM5117400D
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Timing Chart
•Read Cycle
•Write Cy cle (Early Write)
“H” or “L”
tAA
tRAS
tCAS
tRP
tRCS
tOFF
tCLZ
tCAC
tOEA
tASC
tRRH
tRAH
tASR
tRAD tRAL
tCRP
tCAH
tCRP tRCD
tRC
Row
tCSH tRSH
Column
tRAC
tROH
Valid Data-out
tRCH
tOEZ
Open
RAS VIH
VIL
CAS VIH
VIL
Address VIH
VIL
WE VIH
VIL
OE VIH
VIL
DQ VOH
VOL
tCAS
tRAD
tWCS tWCH
tCWL
tASR tRAH tASC
tCRP
tRP
tRC
tRAS
Valid Data-in
tDH
tRWL
Row
tCSH
tCRP tRCD tRSH
Column
tCAH
tRAL
tDS
tWP
RAS VIH
VIL
CAS VIH
VIL
Address VIH
VIL
WE VIH
VIL
OE VIH
VIL
DQ VIH
VIL
“H” or “L”
Open
MSM5117400D
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•Read Modif y Write Cycle
tRP
tRAS
tDH
tDS
tOEZ
tCLZ
tOED
tAA tOEH
tRWD
tCWD
tCWL
tRWL
tCAH
tASC
tASR tRAH
tRAD
tCRP tRCD tRSH
tCAS
tCRP
tCAC
Valid
Data-out
Row
tCSH
Column
tRAC
tOEA
tRCS
tAWD
tWP
tRWC
RAS VIH
VIL
CAS VIH
VIL
Address VIH
VIL
WE VIH
VIL
OE VIH
VIL
DQ VI/OH
VI/OL
“H” or “L”
Valid
Data-in
MSM5117400D
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•Fast Page Mode Cycle
•Fast Page Mode Write Cycle (Early Write)
tCWL
tWP
tRWL tWCH
tCWL
tWP
tCWL
tWCH
tWP
tWCH
tCSH tRAL
tCRP
tDH
tDS
tDH
tDS
tDH
tDS
Valid
Data-in
tWCS
tWCS
tWCS
tASC tCAH
tASC tCAH
tRAD
tASR tASC
tRAH
tRCD
tCRP tCAS tCAS
tRSH
tCP tCAS
tRP
tRHPC
Valid
Data-in
Valid
Data-in
“H” or “L”
tCAH
tCP
tPC
RAS VIH
VIL
CAS VIH
VIL
Address VIH
VIL
WE VIH
VIL
DQ VIH
VIL
tRASP
Row Column Column Column
Note: OE = “H” or “L”
tRHCP
tPC
tCAS
tOEZ
tCAC
tOFF tCAC
tCLZ
tOEA
tCSH
tCAC tOEZ
tRRH
tRAC
tOEA
tRAL
tASC
tCAH
tRCS
tRCH
tCPA
tAA
tAA
tRCH
tRCS
tCAH
tASC
tRAH
tRAD
tRCS
tASR tASC
tCP
tCAS
tRSH
tRASP
tCAS
tCP
tRCD
tCRP
tCLZ
tCAH
Valid
Data-out
tCPA
tRP
RAS VIH
VIL
CAS VIH
VIL
Address VIH
VIL
WE VIH
VIL
OE VIH
VIL
DQ VOH
VOL
Row Column Column Column
“H” or “L”
tCRP
tRCH
tAA tOEA
tOFF tOEZ
Valid
Data-out
tCLZ
tOFF
Valid
Data-out
MSM5117400D
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•Fast Page Mode Read Modify Write Cycle
•RAS-only Refresh Cycle
Note: WE, OE = “H” or “L”
tASR tRAH
tCRP tRPC
tRP
tRAS
tRC
tOFF
RAS VIH
VIL
CAS VIH
VIL
VIH
VIL
Address
VOH
VOL
DQ
“H” or “L”
Row
Open
“H” or “L”
tRCS
Row
Column
tAA
tDH
tDS
tROH
tCPWD tRWL
tCWL
tRCS
Column
tWP
tCPWD
tCWD
tCWL
tCWD
tAWD
tRAL
tCAH
tCRP
tCP tCAS
tCLZ
tCAS
tASC
tASC
tOED
tDH
tOEZ
tOED
tCAC
tOED
tDH
tOEZ
tOEA
tAWD
In
tWP
tDS
tAA
tDS
Column
tRP
tRAH
tRSH
tASR
tRAD
tCAH
Out
tCSH
tCAS
tRAC
tRASP
tOEZ
tRCS
tCAC
tPRWC
tCAC
tCLZ tCLZ
tWP
tCWL
tAWD
tRCD
tCPA
tCP
tOEA
tAA
tCPA
tOEA
tRWD
tCWD
tCAH
tASC
In InOut Out
RAS VIH
VIL
CAS VIH
VIL
Address VIH
VIL
WE VIH
VIL
OE VIH
VIL
DQ VI/OH
VI/OL
Note: In = Valid Data-in, Out = Valid Data-out
MSM5117400D
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•CAS before RAS Refresh Cycle
•Hidden Refresh Read Cycle
tWRP
tWRH
tWRP
tOFF
RAS
tRPC
tRP
tRC
tRAS
tCHR
tCSR
tRP
tCP
tRPC
VIH
VIL
CAS VIH
VIL
VOH
VOL
DQ Open
Note: WE, OE, Address = “H” or “L” “H” or “L”
VIH
VIL
WE
tOFF
tRAC tCLZ
tOEZ
tROH
tOEA
tCAC tRRH
tAA
tRAL
tRCS
tCAH
tRAH
tASR tASC
Column
tRAD
tRP
tRAS
tRC
tRP tCHR
tRAS
tRSH
tRCD
tCRP
tRC
RAS VIH
VIL
CAS VIH
VIL
Address VIH
VIL
WE VIH
VIL
OE VIH
VIL
DQ VOH
VOL Open
Row
Valid Data-out
“H” or “L”
MSM5117400D
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•Hidden Refresh Write Cycle
•Test Mode Initiate Cycle
tOFF
tWTS tWTH
tCP
tRPC
tCSR
tRP
tCHR
tRAS
tRC
RAS VIH
VIL
CAS VIH
VIL
WE VIH
VIL
DQ VIH
VIL
“H” or “L”
Open
Note: OE, Address = “H” or “L”
tWRP tWRH
tDS tDH
tWCH
tRAL
tWP
tWCS
tCAH
tRAH
tASR tASC
Column
tRAD
tRP
tRAS
tRC
tRP tCHR
tRAS
tRSH
tRCD
tCRP
tRC
RAS VIH
VIL
CAS VIH
VIL
Address VIH
VIL
WE VIH
VIL
OE VIH
VIL
DQ VIH
VIL
Row
Valid Data-in
“H” or “L”
