Revised May 2003 FIN1108 * FIN1108T (Preliminary) LVDS 8 Port High Speed Repeater General Description Features This 8 port repeater is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. Greater than 800 Mbps data rate The FIN1108 accepts and outputs LVDS levels with a typical differential output swing of 330 mV which provides low EMI at ultra low power dissipation even at high frequencies. The FIN1108 provides a VBB reference for AC coupling on the inputs. In addition the FIN1108 can directly accept LVPECL, HSTL, and SSTL-2 for translation to LVDS. The FIN1108T has internal termination across the receiver inputs for reduced part count, reduced stub length and better noise immunity. See Applications section. 3.3V power supply operation 3.5 ps maximum random jitter and 135 ps maximum deterministic jitter Wide rail-to-rail common mode range LVDS receiver inputs accept LVPECL, HSTL, and SSTL-2 directly Ultra low power consumption 20 ps typical channel-to-channel skew Power off protection > 7.5 kV HBM ESD Protection Meets or exceeds the TIA/EIA-644-A LVDS standard Available in space saving 48-lead TSSOP package Open circuit fail safe protection VBB reference output FIN1108T (RT) features Internal Termination Resistors Ordering Code: Package Number Package Description FIN1108MTD Order Number MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide FIN1108TMTD (Preliminary) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. (c) 2003 Fairchild Semiconductor Corporation DS500655 www.fairchildsemi.com FIN1108 * FIN1108T (Preliminary) LVDS 8 Port High Speed Repeater March 2002 FIN1108 * FIN1108T (Preliminary) Pin Descriptions Pin Name Connection Diagram Description RIN1+, RIN2+, RIN3+, RIN4+, RIN5+, RIN6+, RIN7+, RIN8+ Non-inverting LVDS Input RIN1-, RIN2-, RIN3-, RIN4-, RIN5-, RIN6-, RIN7-, RIN8- Inverting LVDS Input DOUT1+, DOUT2+, Non-inverting Driver Output DOUT3+, DOUT4+, DOUT5+, DOUT6+, DOUT7+, DOUT8+ DOUT1-, DOUT2-, Inverting Driver Output DOUT3-, DOUT4-, DOUT5-, DOUT6-, DOUT7-, DOUT8- EN Driver Enable Pin for All Output EN12 Inverting Driver Enable Pin for DOUT1 and DOUT2 EN34 Inverting Driver Enable Pin for DOUT3 and DOUT4 EN56 Inverting Driver Enable Pin for DOUT5 and DOUT6 EN78 Inverting Driver Enable Pin for DOUT7 and DOUT8 VCC Power Supply GND Ground VBB Reference Voltage Output Function Table Functional Diagram Inputs Outputs EN ENxx DIN+ H L H L DIN- DOUT+ H L H L L H L H Fail Safe Case DOUT- H L H L X H X X Z Z L X X X Z Z H = HIGH Logic Level L = LOW Logic Level X = Don't Care Z = High Impedance www.fairchildsemi.com 2 Signal Optimization via Internal Termination reliable high-speed operation with tighter required signal settling times. Below is a list of the advantages/disadvantages of internal termination. For LVDS signaling in point-to-point applications, receivers or repeaters with on-chip termination are preferable to reduce the overshoot or undershoot due to the reflection caused by stubs at receiver inputs. As a rule of thumb, usually the termination resistor for an LVDS receiver should be placed as close as possible to the receiver, especially for high speed applications. If the distance between termination resistors and receivers is too long, the interconnection will be seen as an un-terminated stub which can produce reflections resulting in higher EMI. Internal termination can effectively smooth out this ringing which can otherwise jeopardize the receiver noise margin. This is important for Internal termination is not suitable for all applications. In order to set a proper VOD at the driver outputs, receivers with on-chip termination resistors only work for point-topoint applications since multi-drop applications would require termination resistor for each receiver, reducing the equivalent termination to RT/n. This would reduce the driver output swing by n. Advantages: Disadvantages: 1. Reduced device count resulting in reduced board space and production cost. 1. Without special process treatment, on-chip termination can experience greater temperature variation. This is usually tolerable for low speed applications that have a sufficient unit interval. 2. Reduced reflections caused by the stub length on the receiver inputs, improving the signal integrity. 2. For applications with high common-mode noise, a center tapped capacitor at the receiver side is desirable to filter out the common-mode voltage noise of the input LVDS signal. This scheme works for an external termination scheme with two (50 each for nominal 100 termination resistor) half-value termination resistors connected in series and center tapped to a capacitor to Ground. To implement this scheme using internal termination resistors, a center tap pin would have to be used. This would increase the package size of the part. 3 www.fairchildsemi.com FIN1108 * FIN1108T (Preliminary) Applications FIN1108 * FIN1108T (Preliminary) Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) -0.5V to +4.6V Recommended Operating Conditions LVDS DC Input Voltage (VIN) -0.5V to +4.6V -0.5V to +4.6V Supply Voltage (VCC) LVDS DC Output Voltage (VOUT) Driver Short Circuit Current (IOSD) Storage Temperature Range (TSTG) Continuous 10 mA Voltage (|VID|) -65C to +150C 260C ESD (Human Body Model) 7500V ESD (Machine Model) (0V + |VID|/2) to (VCC - |VID|/2) Range (VIC) Lead Temperature (TL) (Soldering, 10 seconds) 100 mV to VCC Common Mode Voltage 150C Max Junction Temperature (TJ) 3.0V to 3.6V Magnitude of Differential -40C to +85C Operating Temperature (TA) Note 1: The "Absolute Maximum Ratings": are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature and output/input loading variables. Fairchild does not recommend operation of circuits outside databook specification. 400V DC Electrical Characteristics Symbol Parameter Min Test Conditions Typ Max (Note 2) Units VTH Differential Input Threshold HIGH See Figure 1; VIC = +0.05V, + 1.2V, or VCC - 0.05V VTL Differential Input Threshold LOW See Figure 1; VIC = +0.05V, + 1.2V, or VCC - 0.05V VIH Input HIGH Voltage (EN or EN) 2.0 VCC VIL Input LOW Voltage (EN or EN) GND 0.8 V VOD Output Differential Voltage 250 330 450 mV VOD VOD Magnitude Change from Differential LOW-to-HIGH RL = 100 , Driver Enabled, 25 mV VOS Offset Voltage See Figure 2 1.125 1.23 1.375 V VOS Offset Magnitude Change from 25 mV -3.4 -6 mA 3.4 6 mA 20 A 100 -100 mV Differential LOW-to-HIGH IOS Short Circuit Output Current DOUT+ = 0V and DOUT- = 0V, Driver Enabled VOD = 0V, Driver Enabled IIN mV Input Current (EN, EN, DINx+, DINx-) VIN = 0V to VCC, Other Input = VCC or 0V (for Differential Inputs) V IOFF Power Off Input or Output Current VCC = 0V, VIN or VOUT = 0V to 3.6V 20 A ICCZ Disabled Power Supply Current Drivers Disabled 20 mA ICC Power Supply Current Drivers Enabled, Any Valid Input Condition 80 mA IOZ Disabled Output Leakage Current Driver Disabled, DOUT+ = 0V to 3.6V or 20 A VIC Common Mode Voltage Range VCC - (VID/2) V CIN Input Capacitance DOUT- = 0V to 3.6V COUT Output Capacitance VBB Output Reference Voltage RT Terminating Resistance VID/2 3 LVDS Input 3 pF 3 VCC = 3.3V, IBB = 0 to -275 A 1.125 1.2 100 Note 2: All typical values are at TA = 25C and with VCC = 3.3V. www.fairchildsemi.com Enable Input 4 pF 1.375 V Over supply voltage and operating temperature ranges, unless otherwise specified Symbol tPLHD Parameter Test Conditions Differential Output Propagation Delay LOW-to-HIGH tPHLD Differential Output Propagation Delay HIGH-to-LOW RL = 100 , CL = 5 pF, tTLHD Differential Output Rise Time (20% to 80%) VID = 200 mV to 450 mV, tTHLD Differential Output Fall Time (80% to 20%) VIC = VID/2 to VCC - (VID/2), tSK(P) Pulse Skew |tPLH - tPHL| Duty Cycle = 50%, tSK(LH), Channel-to-Channel Skew See Figure 1 and Figure 1 tSK(HL) (Note 4) tSK(PP) Part-to-Part Skew (Note 5) fMAX Maximum Frequency (Note 6)(Note 7) tPZHD Differential Output Enable Time tPHZD Differential Output Enable Time from Z to LOW RL = 100 , CL = 5 pF, Differential Output Disable Time See Figure 2 and Figure 3 Differential Output Disable Time from LOW to Z tDJ tRJ LVDS Data Jitter, VID = 300 mV, PRBS = 223 - 1, Deterministic VIC = 1.2V at 800 Mbps LVDS Clock Jitter, VID = 300 mV, Random (RMS) VIC = 1.2V at 400 MHz Max Units 0.75 1.1 1.75 ns 0.75 1.1 1.75 ns 0.29 0.4 0.58 ns 0.29 0.4 0.58 ns 0.02 0.2 ns 0.02 400 from HIGH to Z tPLZD Typ (Note 3) 0.02 from Z to HIGH tPZLD Min 0.15 ns 0.5 ns >630 MHz 3 5 ns 3.1 5 ns 2.2 5 ns 2.5 5 ns 80 135 ps 1.9 3.5 ps Note 3: All typical values are at TA = 25C and with VCC = 3.3V. Note 4: tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direction. Note 5: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction (either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits. Note 6: Passing criteria for maximum frequency is the output VOD > 250 mV and the duty cycle is better than 45% / 55% with all channels switching. Note 7: Output loading is transmission line environment only; CL is < 1 pF of stray test fixture capacitance. FIGURE 1. Differential Receiver Voltage Definitions Note A: All LVDS input pulses have frequency = 10 MHz, tR or tF < = 0.5 ns Note B: CL includes all probe and jig capacitances FIGURE 3. Differential Driver Propagation Delay and Transition Time Test Circuit FIGURE 2. Differential Driver DC Test Circuit 5 www.fairchildsemi.com FIN1108 * FIN1108T (Preliminary) AC Electrical Characteristics FIN1108 * FIN1108T (Preliminary) FIGURE 4. AC Waveform Note A: All LVTTL input pulses have frequency = 10MHz, tR or tF < = 2 ns Note B: CL includes all probe and jig capacitances FIGURE 5. Differential Driver Enable and Disable Circuit FIGURE 6. Enable and Disable AC Waveforms www.fairchildsemi.com 6 FIN1108 * FIN1108T (Preliminary) LVDS 8 Port High Speed Repeater 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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