EVAL-AD5669REBRZ - Analog Devices Inc.

Octal, 12-/16-Bit, I2C, dense

DACs

with 5 ppm/°C On-Chip Reference

Data Sheet

AD5629R/AD5669R

Rev. F Document Feedback

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

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FEATURES

Low power octal DACs

AD5629R: 12 bits

AD5669R: 16 bits

2.6 mm × 2.6 mm 16-ball WLCSP

4 mm × 4 mm 16-lead LFCSP and 16-lead TSSOP

On-chip 1.25 V/2.5 V, 5 ppm/°C reference

Power down to 400 nA at 5 V, 200 nA at 3 V

2.7 V to 5.5 V power supply

Guaranteed monotonic by design

Power-on reset to zero scale or midscale

3 power-down functions

Hardware LDAC and CLR functions

I2C-compatible serial interface supports standard (100 kHz)

and fast (400 kHz) modes

APPLICATIONS

Process control

Data acquisition systems

Portable battery-powered instruments

Digital gain and offset adjustment

Programmable voltage and current sources

FUNCTIONAL BLOCK DIAGRAM

1.25V/2. 5V RE F

REFIN

REFOUT

LDAC

CLR GND

INPUT

DAC A V

OUT

BUFFER

INPUT

DAC B V

OUT

BUFFER

INPUT

DAC C V

OUT

BUFFER

INPUT

DAC D V

OUT

BUFFER

INPUT

DAC E V

OUT

BUFFER

INPUT

DAC F V

OUT

BUFFER

INPUT

DAC G V

OUT

BUFFER

INPUT

DAC H V

OUT

BUFFER

POWER-ON RESET POWER-DOWN LOGIC

INTERFACE LOGIC

SCL

SDA

AD5629R/AD5669R

08819-001

Figure 1.

GENERAL DESCRIPTION

The AD5629R/AD5669R devices are low power, octal, 12-/16-

bit, buffered voltage-output DACs. All devices are guaranteed

monotonic by design.

The AD5629R/AD5669R have an on-chip reference with an

internal gain of 2. The AD5629R-1/AD5669R-1 have a 1.25 V,

5 ppm/°C reference, giving a full-scale output range of 2.5 V.

The AD5629R-2/AD5629R-3 and the AD5669R-2/AD5669R-3

have a 2.5 V 5 ppm/°C reference, giving a full-scale output range

of 5 V depending on the option selected. Devices with 1.25 V

reference selected operate from a single 2.7 V to 5.5 V supply.

Devices with 2.5 V reference selected operate from 4.5 V to 5.5 V.

The on-chip reference is off at power-up, allowing the use of an

external reference. The internal reference is enabled via a

software write.

The parts incorporate a power-on reset circuit to ensure that

the DAC output powers up to 0 V (AD5629R-1/AD5629R-2,

AD5669R-1/AD5669R-2) or midscale (AD5629R-3/AD5669R-3)

and remains powered up at this level until a valid write takes place.

The part contains a power-down feature that reduces the current

consumption of the device to 400 nA at 5 V and provides software-

selectable output loads while in power-down mode for any or

all DAC channels.

PRODUCT HIGHLIGHTS

1. Octal, 12-/16-bit DACs.

2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference.

3. Available in 16-lead LFCSP and TSSOP, and 16-ball WLCSP.

4. Power-on reset to 0 V or midscale.

5. Power-down capability. When powered down, the DAC

typically consumes 200 nA at 3 V and 400 nA at 5 V.

AD5629R/AD5669R Data Sheet

Rev. F | Page 2 of 30

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

AC Characteristics ........................................................................ 6

I2C Timing Characteristics .......................................................... 7

Absolute Maximum Ratings ............................................................ 9

ESD Caution .................................................................................. 9

Pin Configurations and Function Descriptions ......................... 10

Typical Performance Characteristics ........................................... 12

Terminology .................................................................................... 19

Theory of Operation ...................................................................... 21

Digital-to-Analog Converter (DAC) Section ......................... 21

Resistor String ............................................................................. 21

Internal Reference ...................................................................... 21

Output Amplifier ........................................................................ 22

Serial Interface ............................................................................ 22

Write Operation.......................................................................... 22

Read Operation........................................................................... 22

Input Shift Register .................................................................... 24

Multiple Byte Operation ............................................................ 24

Internal Reference Register ....................................................... 25

Power-On Reset .......................................................................... 25

Power-Down Modes .................................................................. 26

Clear Code Register ................................................................... 26

LDAC Function .......................................................................... 28

Power Supply Bypassing and Grounding ................................ 28

Outline Dimensions ....................................................................... 29

Ordering Guide .......................................................................... 30

REVISION HISTORY

6/2018—Rev. E to Rev. F

Changes to Serial Interface Section .............................................. 22

Updated Outline Dimensions ....................................................... 29

Changes to Ordering Guide .......................................................... 30

9/2016—Rev. D to Rev. E

Change to Read Operation Section .............................................. 22

4/2014—Rev. C to Rev. D

Change to VOUTB, VOUTC, VOUTD, VOUTE, VOUTG, VOUTH Ball

Numbers; Table 6 ............................................................................ 11

2/2014—Rev. B to Rev. C

Change to Table 6 ........................................................................... 11

Changes to Figure 38, Figure 39, and Figure 40 ......................... 17

Changes to Ordering Guide .......................................................... 30

2/2013—Rev. A to Rev. B

Added 16-Ball WLCSP ....................................................... Universal

Changes to Features Section............................................................ 1

Added Figure 5, Renumbered Sequentially ................................ 10

Moved Table 6 ................................................................................. 11

Changes to Figure 25 and Figure 26 ............................................. 15

Added Figure 58 .............................................................................. 29

Changes to Ordering Guide .......................................................... 30

12/2010—Rev. 0 to Rev. A

Changes to Features, General Description, and Product

Highlights Sections............................................................................ 1

Changes to AD5629R Relative Accuracy Parameter, Reference

Output (1.25 V) Reference Input Range Parameter, and Reference

Output (2.5 V) Reference Input Range Parameter (Table 1) ....... 3

Changes to Relative Accuracy Parameter, Reference Tempco

Parameter (Table 2) ........................................................................... 5

Changes to Output Voltage Settling Time Parameter (Table 3) .. 6

Changes to Table 5 ............................................................................. 9

Changes to CLR Pin Description (Table 6) ................................. 10

Added Figure 32 and Figure 33 .................................................... 15

Added Figure 46 ............................................................................. 17

Changes to Internal Reference Section ........................................ 20

Changes to Power-On Reset Section ........................................... 23

Changes to Clear Code Register Section ..................................... 24

Updated Outline Dimensions ....................................................... 27

Changes to Ordering Guide .......................................................... 28

10/2010—Revision 0: Initial Version

Data Sheet AD5629R/AD5669R

Rev. F | Page 3 of 30

SPECIFICATIONS

VDD = 4.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.

Table 1.

A Grade1 B Grade1

Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments

STATIC PERFORMANCE2

AD5629R

Resolution 12 12 Bits

Relative Accuracy ±0.5 ±4 ±0.5 ±1 LSB See Figure 7

Differential Nonlinearity ±0.25 ±0.25 LSB Guaranteed monotonic by design

(see Figure 9)

AD5669R

Resolution 16 16 Bits

Relative Accuracy ±8 ±32 ±8 ±16 LSB See Figure 6

Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design

(see Figure 8)

Zero-Code Error 6 19 6 19 mV All 0s loaded to DAC register (see Figure 19)

Zero-Code Error Drift ±2 ±2 µV/°C

Full-Scale Error −0.2 −1 −0.2 −1 % FSR All 1s loaded to DAC register (see Figure 20)

Gain Error ±1 ±1 % FSR

Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C

Offset Error ±6 ±19 ±6 ±19 mV

DC Power Supply Rejection

Ratio

–80 –80 dB VDD ± 10%

DC Crosstalk

(External Reference)

10 10 µV Due to full-scale output change,

RL = 2 kΩ to GND or VDD

5 5 µV/mA Due to load current change

10 10 µV Due to powering down (per channel)

DC Crosstalk

(Internal Reference)

25 25 µV Due to full-scale output change,

RL = 2 kΩ to GND or VDD

10 10 µV/mA Due to load current change

OUTPUT CHARACTERISTICS3

Output Voltage Range 0 VDD 0 VDD V

Capacitive Load Stability 2 2 nF RL = ∞

10 10 nF RL = 2 kΩ

DC Output Impedance 0.5 0.5 Ω

Short-Circuit Current 30 30 mA VDD = 5 V

Power-Up Time 4 4 µs Coming out of power-down mode, VDD = 5 V

REFERENCE INPUTS

Reference Current 40 50 40 50 µA VREFIN = VDD = 5.5 V (per DAC channel)

Reference Input Range 0 VDD 0 VDD V

Reference Input Impedance 14.6 14.6 kΩ

REFERENCE OUTPUT (1.25 V)

Output Voltage 1.247 1.253 1.247 1.253 µA TA = 25°C

Reference Input Range ±15 ±5 ±15 ppm/°C LFCSP, TSSOP

±15 WLCSP

Output Impedance 7.5 7.5 kΩ

REFERENCE OUTPUT (2.5 V)

Output Voltage 2.495 2.505 2.495 2.505 µA TA = 25°C

Reference Input Range ±15 ±5 ±10 ppm/°C

Output Impedance 7.5 7.5 kΩ

AD5629R/AD5669R Data Sheet

Rev. F | Page 4 of 30

A Grade1 B Grade1

Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS3

Input Current ±3 ±3 µA All digital inputs

Input Low Voltage, VINL 0.8 0.8 V VDD = 5 V

Input High Voltage, VINH 2 2 V VDD = 5 V

Pin Capacitance 3 3 pF

POWER REQUIREMENTS

VDD 4.5 5.5 4.5 5.5 V All digital inputs at 0 or VDD,

DAC active, excludes load current

IDD (Normal Mode)4 VIH = VDD and VIL = GND

VDD = 4.5 V to 5.5 V 1.3 1.8 1.3 1.8 mA Internal reference off

2 2.5 2 2.5 mA Internal reference on

IDD (All Power-Down Modes)5

VDD = 4.5 V to 5.5 V 0.4 1 0.4 1 µA VIH = VDD and VIL = GND

1 Temperature range is −40°C to +105°C, typical at 25°C.

2 Linearity calculated using a reduced code range of the AD5629R (Code 32 to Code 4064) and the AD5669R (Code 512 to 65,024). Output unloaded.

3 Guaranteed by design and characterization; not production tested.

4 Interface inactive. All DACs active. DAC outputs unloaded.

5 All eight DACs powered down.

Data Sheet AD5629R/AD5669R

Rev. F | Page 5 of 30

VDD = 2.7 V to 3.6 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.

Table 2.

A Grade1 B Grade1

Parameter Min Typ Max Min Typ Max Unit Conditions/Comments

STATIC PERFORMANCE2

AD5629R

Resolution 12 12 Bits

Relative Accuracy ±0.5 ±4 ±0.5 ±1 LSB See Figure 7

Differential Nonlinearity ±0.25 ±0.25 LSB Guaranteed monotonic by design (see Figure 9)

AD5669R

Resolution 16 16 Bits

Relative Accuracy ±8 ±32 ±8 ±16 LSB See Figure 6

Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design (see Figure 8)

Zero-Code Error 6 19 6 19 mV All 0s loaded to DAC register (see Figure 19)

Zero-Code Error Drift ±2 ±2 µV/°C

Full-Scale Error −0.2 −1 −0.2 −1 % FSR All 1s loaded to DAC register (see Figure 20)

Gain Error ±1 ±1 % FSR

Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C

Offset Error ±6 ±19 ±6 ±19 mV

DC Power Supply Rejection

Ratio

–80 –80 dB VDD ± 10%

DC Crosstalk

(External Reference)

10 10 µV Due to full-scale output change,

RL = 2 kΩ to GND or VDD

5 5 µV/mA Due to load current change

10 10 µV Due to powering down (per channel)

DC Crosstalk

(Internal Reference)

25 25 µV Due to full-scale output change,

RL = 2 kΩ to GND or VDD

µV/mA

Due to load current change

OUTPUT CHARACTERISTICS3

Output Voltage Range 0 VDD 0 VDD V

Capacitive Load Stability 2 2 nF RL = ∞

10 10 nF RL = 2 kΩ

DC Output Impedance 0.5 0.5 Ω

Short-Circuit Current 30 30 mA VDD = 3 V

Power-Up Time 4 4 µs Coming out of power-down mode, VDD = 3 V

REFERENCE INPUTS

Reference Current 40 50 40 50 µA VREFIN = VDD = 3.6 V (per DAC channel)

Reference Input Range 0 VDD 0 VDD

Reference Input Impedance

14.6

kΩ

REFERENCE OUTPUT

Output Voltage

AD5629R/AD5669R 1.247 1.253 1.247 1.253 V TA = 25°C

Reference Tempco3 ±15 ±5 ±15 ppm/°C LFCSP, TSSOP

±15

WLCSP

Reference Output Impedance 7.5 7.5 kΩ

LOGIC INPUTS3

Input Current ±3 ±3 µA All digital inputs

Input Low Voltage, VINL 0.8 0.8 V VDD = 3 V

Input High Voltage, VINH 2 2 V VDD = 3 V

Pin Capacitance 3 3 pF

AD5629R/AD5669R Data Sheet

Rev. F | Page 6 of 30

A Grade1 B Grade1

Parameter Min Typ Max Min Typ Max Unit Conditions/Comments

POWER REQUIREMENTS

VDD 2.7 3.6 2.7 3.6 V All digital inputs at 0 or VDD,

DAC active, excludes load current

IDD (Normal Mode)4 VIH = VDD and VIL = GND

VDD = 2.7 V to 3.6 V 1.0 1.5 1.0 1.5 mA Internal reference off

1.8 2.25 1.7 2.25 mA Internal reference on

IDD (All Power-Down Modes)5

VDD = 2.7 V to 3.6 V 0.2 1 0.2 1 µA VIH = VDD and VIL = GND

1 Temperature range is −40°C to +105°C, typical at 25°C.

2 Linearity calculated using a reduced code range of the AD5629R (Code 32 to Code 4064) and the AD5669R (Code 512 to 65,024). Output unloaded.

3 Guaranteed by design and characterization; not production tested.

4 Interface inactive. All DACs active. DAC outputs unloaded.

5 All eight DACs powered down.

AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.

Table 3.

Parameter1, 2 Min Typ Max Unit Conditions/Comments3

Output Voltage Settling Time 2.5 7 µs ¼ to ¾ scale settling to ±2 LSB

Slew Rate 1.2 V/µs

Digital-to-Analog Glitch Impulse 4 nV-s 1 LSB change around major carry (see Figure 35)

19 nV-s From Code 59904 to Code 59903

Digital Feedthrough 0.1 nV-s

Reference Feedthrough −90 dB VREFIN = 2 V ± 0.1 V p-p, frequency = 10 Hz to 20 MHz

Digital Crosstalk 0.2 nV-s

Analog Crosstalk 0.4 nV-s

DAC-to-DAC Crosstalk 0.8 nV-s

Multiplying Bandwidth 320 kHz VREFIN = 2 V ± 0.2 V p-p

Total Harmonic Distortion −80 dB VREFIN = 2 V ± 0.1 V p-p, frequency = 10 kHz

Output Noise Spectral Density 120 nV/√Hz DAC code = 0x8400, 1 kHz

100 nV/√Hz DAC code = 0x8400, 10 kHz

1 Guaranteed by design and characterization; not production tested.

2 See the Terminology section.

3 Temperature range is −40°C to +105°C, typical at 25°C.

Data Sheet AD5629R/AD5669R

Rev. F | Page 7 of 30

I2C TIMING CHARACTERISTICS

VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, fSCL = 400 kHz, unless otherwise noted.

Table 4.

Parameter Conditions Min Max Unit Description

fSCL1 Standard mode 100 kHz Serial clock frequency

Fast mode 400 kHz

t1 Standard mode 4 μs tHIGH, SCL high time

Fast mode 0.6 μs

t2 Standard mode 4.7 μs tLOW, SCL low time

Fast mode 1.3 μs

t3 Standard mode 250 ns tSU;DAT, data setup time

Fast mode 100 ns

t4 Standard mode 0 3.45 μs tHD;DAT, data hold time

Fast mode 0 0.9 μs

t5 Standard mode 4.7 μs tSU;STA, setup time for a repeated start condition

Fast mode 0.6 μs

t6 Standard mode 4 μs tHD;STA, hold time (repeated) start condition

Fast mode 0.6 μs

t7 Standard mode 4.7 μs tBUF, bus-free time between a stop and a start condition

Fast mode

1.3

μs

t8 Standard mode 4 μs tSU;STO, setup time for a stop condition

Fast mode 0.6 μs

t9 Standard mode 1000 ns tRDA, rise time of SDA signal

Fast mode 300 ns

t10 Standard mode 300 ns tFDA, fall time of SDA signal

Fast mode 300 ns

t11 Standard mode 1000 ns tRCL, rise time of SCL signal

Fast mode 300 ns

t11A Standard mode 1000 ns tRCL1, rise time of SCL signal after a repeated start condition and

after an acknowledge bit

Fast mode 300 ns

Standard mode

300

FCL

, fall time of SCL signal

Fast mode 300 ns

t13 Standard mode 10 ns LDAC pulse width low

Fast mode 10 ns

t14 Standard mode 300 ns Falling edge of ninth SCL clock pulse of last byte of a valid write to

the LDAC falling edge

Fast mode 300 ns

t15 Standard mode 20 ns CLR pulse width low

Fast mode 20 ns

tSP2 Fast mode 0 50 ns Pulse width of spike suppressed

1 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on the EMC

behavior of the part.

2 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode or less than 10 ns for high speed mode.

AD5629R/AD5669R Data Sheet

Rev. F | Page 8 of 30

SCL

SDA

P S S P

CLR

LDAC*

*ASYNCHRO NOUS LDAC UPDATE MODE.

08819-002

Figure 2. Serial Write Operation

Data Sheet AD5629R/AD5669R

Rev. F | Page 9 of 30

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 5.

Parameter Rating

VDD to GND −0.3 V to +7 V

Digital Input Voltage to GND −0.3 V to VDD + 0.3 V

VOUT to GND −0.3 V to VDD + 0.3 V

VREFIN/VREFOUT to GND −0.3 V to VDD + 0.3 V

Operating Temperature Range

Industrial −40°C to +105°C

Storage Temperature Range

−65°C to +150°C

Junction Temperature (TJ MAX) +150°C

Power Dissipation (TJ MAX − TA)/θJA

Thermal Impedance, θJA

16-Lead TSSOP (4-Layer Board) 112.6°C/W

16-Lead LFCSP (4-Layer Board) 30.4°C/W

Reflow Soldering Peak Temperature

Pb Free 260°C

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

ESD CAUTION

AD5629R/AD5669R Data Sheet

Rev. F | Page 10 of 30

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

GND

OUT

REFIN

REFOUT

OUT

CLR

OUT

16 A0

15 LDAC

14 SCL

13 SDA

TOP VIEW

(Not to Scale)

AD5629R/AD5669R

08819-003

NOTES

1. EXPOSED PAD MUST BE TIED TO GND.

Figure 3. 16-Lead LFCSP (CP-16-17)

OUT

LDAC

SDA

GND

OUT

REFIN

REFOUT

CLR

OUT

SCL

TOP VIEW

(No t t o Scale)

AD5629R/

AD5669R

08819-004

Figure 4. 16-Lead TSSOP (RU-16)

TOP VIEW

(BALL SI DE DO W N)

Not to Scale

08819-105

234

INDICATOR

GND

OUT

SDA

OUT

REF

OUT

SCL

LDAC

OUT

CLR

Figure 5. 16-Ball WLCSP

Data Sheet AD5629R/AD5669R

Rev. F | Page 11 of 30

Table 6. Pin Function Descriptions

Pin No.

LFCSP TSSOP WLCSP Mnemonic Description

15 1 B2 LDAC

Pulsing this pin low allows any or all DAC registers to be updated if the input registers

have new data. This allows all DAC outputs to simultaneously update. Alternatively,

this pin can be tied permanently low.

16 2 A4 A0 Address Input. Sets the least significant bit of the 7-bit slave address.

1 3 B3 VDD Power Supply Input. These parts can be operated from 2.7 V to 5.5 V. Decouple the

supply with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.

2 4 B4 VOUTA Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

3 5 C4 VOUTC Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

4 6 C3 VOUTE Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.

OUT

Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.

6 8 D3 VREFIN/VREFOUT The AD5629R/AD5669R have a common pin for reference input and reference output.

When using the internal reference, this is the reference output pin. When using an

external reference, this is the reference input pin. The default for this pin is as a

reference input.

7 9 D2 CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all

LDAC pulses are ignored. When CLR is activated, the input register and the DAC

midscale, or full scale. The default setting clears the output to 0 V.

8 10 D1 VOUTH Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.

9 11 C1 VOUTF Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.

10 12 C2 VOUTD Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

OUT

Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

12 14 A1 GND Ground Reference Point for All Circuitry on the Parts.

13 15 A3 SDA Serial Data Input. This is used in conjunction with the SCL line to clock data into or

out of the 32-bit input shift register. It is a bidirectional, open-drain data line that

should be pulled to the supply with an external pull-up resistor.

14 16 A2 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into or

out of the 32-bit input shift register.

17 N/A N/A Exposed Pad

(EPAD)

The exposed pad must be tied to GND.

AD5629R/AD5669R Data Sheet

Rev. F | Page 12 of 30

TYPICAL PERFORMANCE CHARACTERISTICS

–2

–4

–6

–8

–10

INL (LSB)

VDD = 5V

EXT REF = 5V

TA = 25° C

CODES

010k 20k 30k 40k 50k 60k 65535

08819-106

Figure 6. INL AD5669R—External Reference

1.0

–1.0

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

0500 1000 1500 2000 2500 3000 3500 4095

INL (LSB)

CODES

= 5V

EXT REF = 5V

= 25° C

08819-108

Figure 7. INL AD5629R—External Reference

1.0

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

–1.0

DNL ( LSB)

VDD = 5V

EXT REF = 5V

TA = 25° C

CODES

010k 20k 30k 40k 50k 60k 65535

08819-109

Figure 8. DNL AD5669R—External Reference

05001000150020002500300035004095

DNL ( LSB)

CODES

–0.05

–0.10

–0.15

–0.20

0.05

0.10

0.15

0.20 VDD = 5V

EXT REF = 5V

TA = 25° C

08819-111

Figure 9. DNL AD5629R—External Reference

–10

–5

010k 20k 30k 40k 50k 60k 65535

INL (LSB)

CODES

= 5V

INT RE F = 2.5V

= 25° C

08819-112

Figure 10. INL AD5669R-2—Internal Reference

1.0

0.5

–0.5

–1.0 0500 1000 1500 2000 2500 3000 3500 4095

INL (LSB)

CODES

= 5V

INT RE F = 2.5V

= 25° C

08819-114

Figure 11. INL AD5629R-2—Internal Reference

Data Sheet AD5629R/AD5669R

Rev. F | Page 13 of 30

1.0

0.5

–1.0

–0.5

0 10k 20k 30k 40k 50k 60k 65535

DNL (L S B)

CODES

= 5V

INT REF = 2.5V

= 25°C

08819-115

Figure 12. DNL AD5669R-2—Internal Reference

–0.05

–0.10

–0.15

–0.20

0.05

0.10

0.15

0.20

0 500 1000 1500 2000 2500 3000 3500 4095

DNL (L SB)

CODES

= 5V

INT REF = 2.5V

= 25°C

08819-117

Figure 13. DNL AD5629R-2—Internal Reference

–10

–6

–8

–4

–2

0 10k 20k 30k 40k 50k 60k 65535

INL (LSB)

CODES

= 3V

INT REF = 1.25V

= 25°C

08819-118

Figure 14. INL AD5669R-1—Internal Reference

0 500 1000 1500 2000 2500 3000 3500 4095

INL (LSB)

CODES

= 3V

INT REF = 1.25V

= 25°C

1.0

0.5

–0.5

–1.0

08819-120

Figure 15. INL AD5629R-1—Internal Reference

0 10k 20k 30k 40k 50k 60k 65535

DNL (LSB)

CODES

= 3V

INT REF = 1.25V

= 25°C

1.0

0.5

–1.0

–0.5

08819-121

Figure 16. DNL AD5669R-1—Internal Reference

0 500 1000 1500 2000 2500 3000 3500 4095

DNL (LSB)

CODES

–0.05

–0.10

–0.15

–0.20

0.05

0.10

0.15

0.20 V

= 3V

INT REF = 1.25V

= 25°C

08819-123

Figure 17. DNL AD5629R-1—Internal Reference

AD5629R/AD5669R Data Sheet

Rev. F | Page 14 of 30

–0.30

–0.25

–0.20

–0.15

–0.10

–0.05

–40 1251109580655035205

–10

–25

ERROR ( % FSR)

TEMPERATURE (°C)

FULL- S CALE E RROR

GAI N E RROR

= 5V

08819-124

Figure 18. Gain Error and Full-Scale Error vs. Temperature

–40 125

1109580

655035205

–10–25

ERROR ( mV )

TEMPERATURE (°C)

ZERO-CODE E RROR

OFFSET ERROR

= 5V

08819-125

Figure 19. Zero-Code Error and Offset Error vs. Temperature

–0.16

–0.26

–0.25

–0.24

–0.23

–0.22

–0.21

–0.20

–0.19

–0.18

–0.17

2.7 5.55.14.74.33.93.53.1

ERROR ( % FSR)

(V)

FULL- S CALE E RROR

GAI N E RROR

= 25° C

08819-126

Figure 20. Gain Error and Full-Scale Error vs. Supply Voltage

1.95

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

2.7 5.5

5.1

4.7

4.3

3.9

3.53.1

ERROR ( mV )

(V)

ZERO-CODE E RROR

OFFSET ERROR

= 25° C

08819-127

Figure 21. Zero-Code Error and Offset Error vs. Supply Voltage

WITH E X TERNAL REFERENCE ( mA)

NUMBER O F HI TS

0.85 0.90 0.95

1.00 1.05

08819-128

Figure 22. IDD Histogram with External Reference

WITH INT E RNAL REFERENCE ( mA)

NUMBER O F HI TS

1.65 1.70 1.75 1.80 1.85 1.90

08819-129

Figure 23. IDD Histogram with Internal Reference

Data Sheet AD5629R/AD5669R

Rev. F | Page 15 of 30

0.4

–0.5

–0.4

–0.3

–0.2

–0.1

0.1

0.2

0.3

–10–8–6–4–20246810

ERROR V OLT AGE (V)

SOURCE/ SINK CURRENT (mA)

VDD = 5V, I NT REF = 2.5V

VDD = 3V , IN T RE F = 1.25V

TA = 25°C

08819-130

Figure 24. Headroom at Rails vs. Source and Sink

–1

–0.03 –0.02 –0.01 0 0.01 0.02 0.03

OUT

(V)

SO URCE AND SI NK CURRENT ( A)

ZERO CO DE

FUL L SCALE

MIDSCALE

1/4 S CALE

3/4 S CALE

= 5V

INT REF = 2.5V

= 25°C

08819-131

Figure 25. AD5669R-2 Source and Sink Capability

4.0

–1.0

–0.5

0.5

1.0

1.5

2.0

2.5

3.0

3.5

–0.03 –0.02 –0.01 0 0.01 0.02 0.03

OUT

(V)

SOU RCE AND S INK CURRENT (A)

ZE RO CO DE

FULL SCALE

MIDSCALE

1/4 S CALE

3/4 S CALE

= 3V

INT REF = 1.25V

= 25°C

08819-132

Figure 26. AD5669R-1 Source and Sink Capability

1.8

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

0 10k 20k 30k 40k 50k 60k

(mA)

DIGITAL CODES (Decimal)

= 25° C

= 5V

= 3V

08819-133

Figure 27. Supply Current vs. Code

2.0

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

–40 –25 –10 5 20 35 50 65 80 95 110 125

(mA)

TEM PE RAT URE ( °C)

= 3.6V

= 5.5V

= 25°C

08819-134

Figure 28. Supply Current vs. Temperature

1.48

1.34

1.36

1.38

1.40

1.42

1.44

1.46

2.7 5.55.14.74.33.93.53.1

(mA)

(V)

= 25° C

08819-135

Figure 29. Supply Current vs. Supply Voltage

AD5629R/AD5669R Data Sheet

Rev. F | Page 16 of 30

2.3

2.1

1.9

1.7

1.5

1.3

1.1

0.9

0.7 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

(mA)

LOGIC

(V)

= 25° C

=5V

=3V

08819-136

Figure 30. Supply Current vs. Logic Input Voltage

0–2 86420

OUT

(V)

TIME (µs)

= 5V

EXT REF = 5V

= 25°C

08819-137

Figure 31. Full-Scale Settling Time, 5 V

5.5

4.5

3.5

2.5

1.5

0.5

5.0

4.0

3.0

2.0

1.0

–0.5

–0.0010 0.00100.00060.0002–0.0002–0.0006

VOL T AGE (V)

TIME (s)

OUT

= 5V

EXT REF = 5V

= 25°C

08819-138

Figure 32. Power-On Reset to 0 V

5.5

4.5

3.5

2.5

1.5

0.5

5.0

4.0

3.0

2.0

1.0

–0.5

–0.0010 0.00100.00060.0002–0.0002–0.0006

VOL T AGE (V)

TIME (s)

OUT

= 5V

EXT REF = 5V

= 25°C

08819-139

Figure 33. Power-On Reset to Midscale

5.5

4.5

3.5

2.5

1.5

0.5

5.0

4.0

3.0

2.0

1.0

–0.5

–10 1050–5

VOL T AG E (V)

TIME (µs)

OUT

CLK R IS ING EDGE

= 5V

EXT REF = 5V

= 25° C

08819-140

Figure 34. Exiting Power-Down to Midscale

CH3 10.0mV

CH4 5.0V M400n s A CH4 1. 50V

T 17.0%

= 5V

EXT REF = 5V

= 25° C

OUT

CLK RIS ING E DGE

08819-141

Figure 35. Digital-to-Analog Glitch Impulse (Negative)

Data Sheet AD5629R/AD5669R

Rev. F | Page 17 of 30

0.0010

–0.0015

–0.0010

–0.0005

0.0005

09876543

GLITCH AMPLITUDE (V)

TIME (µs)

VDD = 5V

EXT REF = 5V

TA = 25° C

08819-142

Figure 36. Analog Crosstalk

0.0020

–0.0015

–0.0010

–0.0005

0.0010

0.0015

0.0005

087

543

GLITCH AMPLITUDE (V)

TIME (µs)

VDD = 5V

EXT REF = 5V

TA = 25° C

08819-143

Figure 37. DAC-to-DAC Crosstalk

–8

–6

–4

–2

0108 97654321

OUTPUT VOLTAGE (µV)

TIME (s)

= 5.5V

EXT REF = 5V

DAC CODE = 0xFF 00

08819-144

Figure 38. 0.1 Hz to 10 Hz Output Noise Plot, External Reference

–20

–15

–10

–5

0108 9765

321

OUTPUT NOISE (µV)

TIME (s)

EXT RE F = 2.5V

DAC CODE = 0xFF 00

08819-145

Figure 39. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference

–20

–15

–10

–5

0108 97654321

OUTPUT NOISE (µV)

TIME (s)

INT REF = 1.25V

DAC CODE = 0xFF 00

08819-146

Figure 40. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference

800

100

200

300

400

600

700

500

100 1M100k10k1k

OUTPUT NOISE (nV/ Hz)

FREQUENCY ( Hz )

REF

= 1.25V

REF

= 2.5V

= 5.5V

DAC CODE = 0x8400

08819-147

Figure 41. Noise Spectral Density, Internal Reference

AD5629R/AD5669R Data Sheet

Rev. F | Page 18 of 30

–140

–120

–100

–80

–60

–40

–20

010,000

8000600040002000

THD ( dB)

FREQUENCY ( Hz )

= 5.5V

EXT REF = 5V

= 25° C

REF

= 2V ± 0.1V p-p

FREQUENCY = 10kHz

08819-148

Figure 42. Total Harmonic Distortion

010987654

321

SETTLING TIME (µs)

CAPACITIVE LOAD (nF)

VDD = E X TERNAL REF E RE NCE = 5V

VDD = E X TERNAL REF E RE NCE = 3V

TA = 25° C

08819-149

Figure 43. Settling Time vs. Capacitive Load

5.5

–0.5

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

–10 1050–5

VOLTAGE (V)

TIME (µs)

VOUTA

CLR PULSE

EXT REF = 5V

08819-150

Figure 44. Hardware CLR

–80

–70

–60

–50

–40

–30

–20

–10

10 100M

10M

100k

1k0

100

OUT

(d Bm)

FREQUENCY ( Hz )

CH A

CH B

CH C

CH D

CH E

CH F

CH G

CH H

–3dB

= 5.5V

EXT REF = 5V

= 25° C

REF

= 2V ± 0.2V p-p

08819-151

Figure 45. Multiplying Bandwidth

1.2510

1.2490

1.2492

1.2494

1.2496

1.2498

1.2500

1.2502

1.2504

1.2506

1.2508

–40 25 105

REFE RE NCE ( pp m/° C)

TEMPERATURE (°C)

= 5.5V

08819-152

Figure 46. 1.25 V Reference Temperature Coefficient vs. Temperature

2.503

2.495

2.496

2.497

2.498

2.499

2.500

2.501

2.502

105 25 –40

REFE RE NCE ( pp m/° C)

TEMPERATURE (°C)

08819-153

Figure 47. 2.5 V Reference Temperature Coefficient vs. Temperature

Data Sheet AD5629R/AD5669R

Rev. F | Page 19 of 30

TERMINOLOGY

Relative Accuracy

For the DAC, relative accuracy, or integral nonlinearity (INL), is

a measure of the maximum deviation in LSBs from a straight line

passing through the endpoints of the DAC transfer function.

Figure 6, Figure 7, Figure 10, Figure 11, Figure 14, and Figure 15

show plots of typical INL vs. code.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between the

measured change and the ideal 1 LSB change between any two

adjacent codes. A specified differential nonlinearity of ±1 LSB

maximum ensures monotonicity. This DAC is guaranteed

monotonic by design. Figure 8, Figure 9, Figure 12, Figure 13,

Figure 16, and Figure 17 show plots of typical DNL vs. code.

Offset Error

Offset error is a measure of the difference between the actual

VOUT and the ideal VOUT, expressed in millivolts in the linear

region of the transfer function. Offset error is measured on the

AD5669R between Code 512 and Code 65024 loaded into the

DAC register. It can be negative or positive and is expressed in

millivolts.

Zero-Code Error

Zero-code error is a measure of the output error when zero

code (0x0000) is loaded into the DAC register. Ideally, the

output should be 0 V. The zero-code error is always positive

because the output of the DAC cannot go below 0 V. It is due to

a combination of the offset errors in the DAC and output

amplifier. Zero-code error is expressed in millivolts. Figure 19

shows a plot of typical zero-code error vs. temperature.

Gain Error

Gain error is a measure of the span error of the DAC. It is the

deviation in slope of the DAC transfer characteristic from the

ideal, expressed as a percentage of the full-scale range.

Zero-Code Error Drift

Zero-code error drift is a measure of the change in zero-code

error with a change in temperature. It is expressed in µV/°C.

Gain Error Drift

Gain error drift is a measure of the change in gain error with

changes in temperature. It is expressed in (ppm of full-scale

range)/°C.

Full-Scale Error

Full-scale error is a measure of the output error when full-scale

code (0xFFFF) is loaded into the DAC register. Ideally, the

output should be VREF − 1 LSB. Full-scale error is expressed as

a percentage of the full-scale range. Figure 18 shows a plot of

typical full-scale error vs. temperature.

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the

analog output when the input code in the DAC register changes

state. It is normally specified as the area of the glitch in nV-s and

is measured when the digital input code is changed by 1 LSB at

the major carry transition (0x7FFF to 0x8000). Figure 35 shows

a typical digital-to-analog glitch impulse plot.

DC Power Supply Rejection Ratio (PSRR)

PSRR indicates how the output of the DAC is affected by changes

in the supply voltage. PSRR is the ratio of the change in VOUT to

a change in VDD for full-scale output of the DAC. VREF is held at

2 V, a n d VDD is varied ±10%. It is measured in decibels.

DC Crosstalk

DC crosstalk is the dc change in the output level of one DAC in

response to a change in the output of another DAC. It is measured

with a full-scale output change on one DAC (or soft power-down

and power-up) while monitoring another DAC kept at midscale.

It is expressed in microvolts.

DC crosstalk due to load current change is a measure of the impact

that a change in load current on one DAC has on another DAC

kept at midscale. It is expressed in microvolts per milliamp.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into

the analog output of a DAC from the digital input pins of the

device, but is measured when the DAC is not being written to. It

is specified in nV-s and measured with a full-scale change on

the digital input pins, that is, from all 0s to all 1s or vice versa.

Digital Crosstalk

Digital crosstalk is the glitch impulse transferred to the output

of one DAC at midscale in response to a full-scale code change

(all 0s to all 1s or vice versa) in the input register of another DAC.

It is measured in standalone mode and is expressed in nV-s.

Analog Crosstalk

Analog crosstalk is the glitch impulse transferred to the output

of one DAC due to a change in the output of another DAC. It is

measured by loading one of the input registers with a full-scale

code change (all 0s to all 1s or vice versa) while keeping LDAC

high and then pulsing LDAC low and monitoring the output of

the DAC whose digital code has not changed. The area of the

glitch is expressed in nV-s.

AD5629R/AD5669R Data Sheet

Rev. F | Page 20 of 30

DAC-to-DAC Crosstalk

DAC-to-DAC crosstalk is the glitch impulse transferred to the

output of one DAC due to a digital code change and subsequent

output change of another DAC. This includes both digital and

analog crosstalk. It is measured by loading one of the DACs

with a full-scale code change (all 0s to all 1s or vice versa) with

LDAC low and monitoring the output of another DAC. The

energy of the glitch is expressed in nV-s.

Multiplying Bandwidth

The amplifiers within the DAC have a finite bandwidth. The

multiplying bandwidth is a measure of this. A sine wave on the

reference (with full-scale code loaded to the DAC) appears on

the output. The multiplying bandwidth is the frequency at

which the output amplitude falls to 3 dB below the input.

Total Harmonic Distortion (THD)

Total harmonic distortion is the difference between an ideal

sine wave and its attenuated version using the DAC. The sine

wave is used as the reference for the DAC, and the THD is a

measure of the harmonics present on the DAC output. It is

measured in decibels.

Data Sheet AD5629R/AD5669R

Rev. F | Page 21 of 30

THEORY OF OPERATION

DIGITAL-TO-ANALOG CONVERTER (DAC) SECTION

The AD5629R/AD5669R are fabricated on a CMOS process.

The architecture consists of a string of DACs followed by an

output buffer amplifier. Each part includes an internal 1.25 V/

2.5 V, 5 ppm/°C reference with an internal gain of 2. Figure 48

and Figure 49 show block diagrams of the DAC architecture.

OUTPUT

AMPLIFIER

GAIN = ×2

DAC

REF ( + )

REFIN

REFOUT

OUT

REF ( –)

RESISTOR

STRING

GND

INTERNAL

REFERENCE

CAN BE O V E RDRIVE N

BY V

REFIN

REFOUT

08819-045

Figure 48. DAC Architecture for Internal Reference Configuration

REF

BUFFER

OUTPUT

AMPLIFIER

GAIN = ×2

REFIN

REFOUT

GND

REF (+ )

REF (–)

RESISTOR

STRING V

OUT

08819-046

Figure 49. DAC Architecture for External Reference Configuration

Because the input coding to the DAC is straight binary, the ideal

output voltage when using an external reference is given by













 N

REFIN

OUT

The ideal output voltage when using the internal reference is

given by













 N

REFOUTOUT

where:

D = decimal equivalent of the binary code that is loaded to the

DAC register as follows:

0 to 4095 for AD5629R (12 bits).

0 to 65,535 for AD5669R (16 bits).

N = the DAC resolution.

RESISTOR STRING

The resistor string section is shown in Figure 50. It is simply a

string of resistors, each of value R. The code loaded into the

DAC register determines at which node on the string the voltage is

tapped off to be fed into the output amplifier. The voltage is

tapped off by closing one of the switches connecting the string

to the amplifier. Because it is a string of resistors, it is guaranteed

monotonic.

TO OUTPUT

AMPLIFIER

08819-047

Figure 50. Resistor String

INTERNAL REFERENCE

The AD5629R/AD5669R have an on-chip reference with an

internal gain of 2. The AD5629R-1/AD5669R-1 have a 1.25 V,

5 ppm/°C reference, giving a full-scale output of 2.5 V or the

AD5629R-2/AD5629R-3/AD5669R-2/AD5669R-3 have a 2.5 V,

5 ppm/°C reference, working between a supply from 4.5 V to

5.5 V giving a full-scale output of 5 V. The on-board reference

is off at power-up, allowing the use of an external reference. The

internal reference is enabled via a write to the control register

(see Table 8).

The internal reference associated with each part is available at

the VREFOUT pin. A buffer is required if the reference output is

used to drive external loads. When using the internal reference,

it is recommended that a 100 nF capacitor be placed between

the reference output and GND for reference stability.

Individual channel power-down is not supported while using

the internal reference.

AD5629R/AD5669R Data Sheet

Rev. F | Page 22 of 30

OUTPUT AMPLIFIER

The output buffer amplifier can generate rail-to-rail voltages on

its output, which gives an output range of 0 V to VDD. The amplifier

is capable of driving a load of 2 kΩ in parallel with 1000 pF to

GND. The source and sink capabilities of the output amplifier

can be seen in Figure 25 and Figure 26. The slew rate is 1.5 V/µs

with a ¼ to ¾ scale settling time of 10 µs.

SERIAL INTERFACE

The AD5629R/AD5669R have 2-wire I2C-compatible serial

interfaces (refer to The I2C-Bus Specification, Version 2.1,

January 2000, available from Philips Semiconductor). The

AD5629R/AD5669R can be connected to an I2C bus as a slave

device under the control of a master device. See Figure 2 for a

timing diagram of a typical write sequence.

The AD5629R/AD5669R support standard (100 kHz) and fast

(400 kHz) modes. High speed operation is only available on

selected models. See the Ordering Guide for a full list of

models. Support is not provided for 10-bit addressing and

general call addressing.

The AD5629R/AD5669R each have a 7-bit slave address. The

parts have a slave address whose five MSBs are 10101, and the

two LSBs are set by the state of the A0 address pin, which

determines the state of the A0 and A1 address bits.

The facility to make hardwired changes to the A0 pin allows the

user to incorporate up to three of these devices on one bus, as

outlined in Table 7.

Table 7. ADDR Pin Settings

A0 Pin Connection

VDD 0 0

GND 1 1

The 2-wire serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a start

condition when a high-to-low transition on the SDA line

occurs while SCL is high. The following byte is the address

byte, which consists of the 7-bit slave address. The slave

address corresponding to the transmitted address responds

by pulling SDA low during the ninth clock pulse (this is

termed the acknowledge bit). At this stage, all other devices

on the bus remain idle while the selected device waits for

data to be written to or read from its shift register.

2. Data is transmitted over the serial bus in sequences of nine

clock pulses (eight data bits followed by an acknowledge

bit). The transitions on the SDA line must occur during

the low period of SCL and remain stable during the high

period of SCL.

3. When all data bits have been read or written, a stop

condition is established. In write mode, the master pulls

the SDA line high during the 10th clock pulse to establish

a stop condition. If a stop condition is generated between

the 7th and 8th clock pulse of the I2C address frame, a power

cycle is required to recover the part. In read mode, the master

issues a no acknowledge for the ninth clock pulse (that is,

the SDA line remains high). The master brings the SDA

line low before the 10th clock pulse and then high during

the 10th clock pulse to establish a stop condition.

WRITE OPERATION

When writing to the AD5629R/AD5669R, the user must begin

with a start command followed by an address byte (R/W = 0),

after which the DAC acknowledges that it is prepared to receive

data by pulling SDA low. The AD5629R/AD5669R require two

bytes of data for the DAC and a command byte that controls

various DAC functions. Three bytes of data must, therefore, be

written to the DAC, the command byte followed by the most

significant data byte and the least significant data byte, as shown in

Figure 51. After these data bytes are acknowledged by the

AD5629R/AD5669R, a stop condition follows.

READ OPERATION

When reading data back from the AD5629R/AD5669R, the

user begins with a start command followed by an address byte

(R/W = 1), after which the DAC acknowledges that it is prepared

to transmit data by pulling SDA low. Three bytes of data are then

read from the DAC, the first two of which are both acknowledged

by the master as shown in Figure 52. A stop condition follows.

Data Sheet AD5629R/AD5669R

Rev. F | Page 23 of 30

FRAME 2

COMM AND BYTE

FRAME 1

SLAVE ADDRESS

19 91

SCL

START BY

MASTER ACK. BY

AD5629R/AD5669R ACK. BY

AD5629R/AD5669R

SDA R/W DB23A0A11101 0 DB22 DB21 DB20 DB19 DB18 DB17 DB16

19 91

ACK. BY

AD5629R/AD5669R ACK. BY

AD5629R/AD5669R

FRAME 4

LEAS T SI GNI FICANT

DATA BYTE

FRAME 3

MOST SIGNIFICANT

DATA BYTE

STO P BY

MASTER

SCL

(CONTINUED)

SDA

(CONTINUED) DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

08819-048

Figure 51. I2C Write Operation

FRAME 2

COM MAND BYTE

FRAME 1

SL AVE ADDRESS

19 91

SCL

START BY

MASTER ACK. BY

AD5629R/AD5669R ACK. BY

MASTER

SDA R/W DB23A0A11101 0 DB22 DB21 DB20 DB19 DB18 DB17 DB16

19 91

ACK. BY

MASTER NO ACK.

FRAME 4

LEAS T SIG NI F ICANT

DATA BYTE

FRAME 3

MO ST SIG NI FI CANT

DATA BY TE

STO P BY

MASTER

SCL

(CONTINUED)

SDA

(CONTINUED) DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

08819-049

Figure 52. I2C Read Operation

Table 8. Command Definitions

Command

C3 C2 C1 C0 Description

0 0 0 0 Write to Input Register n

0 0 0 1 Update DAC Register n

0 0 1 0 Write to Input Register n; update all

(software LDAC)

0 0 1 1 Write to and update DAC Channel n

0 1 0 0 Power down/power up DAC

0 1 0 1 Load clear code register

0 1 1 0 Load LDAC register

0 1 1 1 Reset (power-on reset)

1 0 0 0 Set up internal REF register

1 0 0 1 Enable multiple byte mode

1 0 1 0 Reserved

– – – – Reserved

1 1 1 1 Reserved

Table 9. Address Commands

Address (n)

A3 A2 A1 A0 Selected DAC Channel

0 0 0 0 DAC A

0 0 0 1 DAC B

0 0 1 0 DAC C

0 0 1 1 DAC D

0 1 0 0 DAC E

0 1 0 1 DAC F

0 1 1 0 DAC G

0 1 1 1 DAC H

1 1 1 1 All DACs

AD5629R/AD5669R Data Sheet

Rev. F | Page 24 of 30

INPUT SHIFT REGISTER

The input shift register is 24 bits wide. Data is loaded into the

device as a 24-bit word under the control of a serial clock input,

SCL. The input register contents for this operation is shown in

Figure 53 and Figure 54. The eight MSBs make up the command

byte. DB23 to DB20 are the command bits, C3, C2, C1, and C0,

that control the mode of operation of the device (see Table 9 for

details). The last four bits of the first byte are the address bits,

A3, A2, A1, and A0, (see Table 9 for details). The rest of the bits

are the 16-/12-bit data-word.

The AD5669R data-word comprises the 16-bit input code (see

Figure 53) while the AD5629R data word is comprised of 12-

bits followed by four don’t cares (see Figure 54).

MULTIPLE BYTE OPERATION

Multiple byte operation is supported on the AD5629R/AD5669R.

Command 1001 is reserved for multiple byte operation (see

Table 8) A 2-byte operation is useful for applications that require

fast DAC updating and do not need to change the command

byte. The S bit (DB22) in the command register can be set to 1

for the 2-byte mode of operation. For standard 3-byte and 4-byte

operation, the S bit (DB22) in the command byte should be set to 0.

Data Sheet AD5629R/AD5669R

Rev. F | Page 25 of 30

INTERNAL REFERENCE REGISTER

The internal reference is available on all versions. The on-board

reference is off at power-up by default. The on-board reference

can be turned off or on by a user-programmable internal REF

the internal reference value. Command 1000 is reserved for

setting the internal REF register (see Table 8). Table 11 shows

how the state of the bits in the input shift register corresponds

to the mode of operation of the device.

POWER-ON RESET

The AD5629R/AD5669R contain a power-on reset circuit that

controls the output voltage during power-up. The AD5629R/

AD5669R DAC output powers up to 0 V and the AD5669R-3

DAC output powers up to midscale. The output remains powered

up at this level until a valid write sequence is made to the DAC.

This is useful in applications where it is important to know the

state of the output of the DAC while it is in the process of powering

up. There is also a software executable reset function that resets

the DAC to the power-on reset code. Command 0111 is reserved

for this reset function (see Table 8). Any events on LDAC or

CLR during power-on reset are ignored.

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

COMMAND DAC ADDRESS DAC DATA DAC DATA

COMM AND BY TE DATA HIGH BY TE DATA L OW BY TE

08819-050

Figure 53. AD5669R Input Register Contents

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X

COMMAND DAC ADDRESS DAC DATA DAC DATA

COMM AND BY TE DATA HIGH BY TE DATA L OW BY TE

08819-052

Figure 54. AD5629R Input Register Contents

AD5629R/AD5669R Data Sheet

Rev. F | Page 26 of 30

POWER-DOWN MODES

The AD5629R/AD5669R contain four separate modes of

operation. Command 0100 is reserved for the power-down

function (see Table 8). These modes are software-programmable

by setting two bits, Bit DB9 and Bit DB8, in the control register.

Table 12 shows how the state of the bits corresponds to the

mode of operation of the device. Any or all DACs (DAC H to

DAC A) can be powered down to the selected mode by setting

the corresponding eight bits (DB7 to DB0) to 1. See Table 13 for

the contents of the input shift register during power-down/power-

up operation.

When both bits are set to 0, the part works normally with its

normal power consumption of 1.3 mA at 5 V. However, for the

three power-down modes, the supply current falls to 0.4 µA at

5 V (0.2 µA at 3 V). Not only does the supply current fall, but

the output stage is also internally switched from the output of

the amplifier to a resistor network of known values. This has the

advantage that the output impedance of the part is known while

the part is in power-down mode. There are three different

options. The output is connected internally to GND through

either a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited

(three-state). The output stage is illustrated in Figure 55.

RESISTOR

NETWORK

OUT

RESISTOR

STRING DAC

POWER-DOWN

CIRCUITRY

AMPLIFIER

08819-051

Figure 55. Output Stage During Power-Down

The bias generator of the selected DAC(s), output amplifier,

resistor string, and other associated linear circuitry is shut down

when the power-down mode is activated. The internal reference

is powered down only when all channels are powered down.

However, the contents of the DAC register are unaffected when

in power-down. The time to exit power-down is typically 4 µs

for VDD = 5 V and for VDD = 3 V.

Any combination of DACs can be powered up by setting PD1

and PD0 to 0 (normal operation). The output powers up to the

value in the input register (LDAC low) or to the value in the

DAC register before powering down (LDAC high).

CLEAR CODE REGISTER

The AD5629R/AD5669R have a hardware CLR pin that is an

asynchronous clear input. The CLR input is falling edge sensitive.

Bringing the CLR line low clears the contents of the input

configurable CLR register and sets the analog outputs accordingly.

This function can be used in system calibration to load zero scale,

midscale, or full scale to all channels together. These clear code

values are user-programmable by setting two bits, Bit DB1 and

Bit DB0, in the CLR control register (see Table 15). The default

setting clears the outputs to 0 V. Command 0101 is reserved for

loading the clear code register (see Table 8).

The part exits clear code mode at the end of the next valid write

to the part. If CLR is activated during a write sequence, the write

is aborted.

The CLR pulse activation time (the falling edge of CLR to when

the output starts to change) is typically 280 ns. However, if

outside the DAC linear region, it typically takes 520 ns after

executing CLR for the output to start changing (see Figure 44).

See Table 14 for the contents of the input shift register during

the loading clear code register operation.

Table 10. Internal Reference Register

Internal REF Register (DB0) Action

0 Reference off (default)

1 Reference on

Table 11. 32-Bit Input Shift Register Contents for Reference Set-Up Command

MSB LSB

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB1 DB0

1 0 0 0 X X X X X 1/0

Command bits (C3 to C0) Address bits (A3 to A0)—don’t cares Don’t cares Internal REF on/off

Table 12. Power-Down Modes of Operation

DB9 DB8 Operating Mode

0 0 Normal operation

Power-down modes

0 1 1 kΩ to GND

100 kΩ to GND

1 1 Three-state

Data Sheet AD5629R/AD5669R

Rev. F | Page 27 of 30

Table 13. 32-Bit Input Shift Register Contents for Power-Down/Power-Up Function

MSB

LSB

DB23 DB22 DB21 DB20 DB19 to DB16 DB15 to DB10 DB9 DB8 DB7 to DB1 DB0

0 1 0 0 X X PD1 PD0 DAC H to DAC B DAC A

Command bits (C3 to C0) Address bits (A3 to A0)—

don’t cares

Don’t cares Power-

down mode

Power-down/power-up channel selection—

set bit to 1 to select

Table 14. 32-Bit Input Shift Register Contents for Clear Code Function

MSB LSB

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB2 DB1 DB0

0 1 0 1 X X X X X CR1 CR0

Command bits (C3 to C0) Address bits (A3 to A0)—don’t cares Don’t cares Clear code register

Table 15. Clear Code Register

Clear Code Register

DB1

DB0

CR1 CR0 Clears to Code

0 0 0x0000

0 1 0x8000

1 0 0xFFFF

1 1 No operation

AD5629R/AD5669R Data Sheet

Rev. F | Page 28 of 30

LDAC FUNCTION

The outputs of all DACs can be updated simultaneously using

the hardware LDAC pin.

Synchronous LDAC

The DAC registers are updated after new data is read in. LDAC

can be permanently low or pulsed as in Figure 2.

Asynchronous LDAC

The outputs are not updated at the same time that the input

registers are written to. When LDAC goes low, the DAC

registers are updated with the contents of the input register.

Alternatively, the outputs of all DACs can be updated simulta-

neously using the software LDAC function by writing to Input

reserved for this software LDAC function.

An LDAC register gives the user extra flexibility and control

over the hardware LDAC pin. Setting the LDAC bit register

to 0 for a DAC channel means that this channel’s update is

controlled by the LDAC pin. If this bit is set to 1, this channel

updates synchronously; that is, the DAC register is updated

after new data is read, regardless of the state of the LDAC pin.

It effectively sees the LDAC pin as being tied low. See Table 16

for the LDAC register mode of operation.

This flexibility is useful in applications where the user wants

to simultaneously update select channels while the rest of the

channels are synchronously updating. Writing to the DAC

using command 0110 loads the 8-bit LDAC register (DB7 to

DB0). The default for each channel is 0, that is, the LDAC pin

works normally. Setting the bits to 1 means the DAC channel

is updated regardless of the state of the LDAC pin. See Table 17

for the contents of the input shift register during the load LDAC

POWER SUPPLY BYPASSING AND GROUNDING

When accuracy is important in a circuit, it is helpful to carefully

consider the power supply and ground return layout on the board.

The printed circuit board containing the AD5629R/AD5669R

should have separate analog and digital sections. If the AD5629R/

AD5669R are in a system where other devices require an

AGND-to-DGND connection, the connection should be made

at one point only. This ground point should be as close as

possible to the AD5629R/AD5669R.

The power supply to the AD5629R/AD5669R should be

bypassed with 10 µF and 0.1 µF capacitors. The capacitors

should be as physically close as possible to the device, with the

0.1 µF capacitor ideally right up against the device. The 10 µF

capacitors are the tantalum bead type. It is important that the

0.1 µF capacitor have low effective series resistance (ESR) and

low effective series inductance (ESI), such as is typical of

common ceramic types of capacitors. This 0.1 µF capacitor

provides a low impedance path to ground for high frequencies

caused by transient currents due to internal logic switching.

The power supply line should have as large a trace as possible to

provide a low impedance path and reduce glitch effects on the

supply line. Clocks and other fast switching digital signals should

be shielded from other parts of the board by digital ground. Avoid

crossover of digital and analog signals if possible. When traces

cross on opposite sides of the board, ensure that they run at right

angles to each other to reduce feedthrough effects through the

board. The best board layout technique is the microstrip technique,

where the component side of the board is dedicated to the ground

plane only and the signal traces are placed on the solder side.

However, this is not always possible with a 2-layer board.

Table 16. LDAC Register

Load DAC Register

LDAC Bits (DB7 to DB0) LDAC Pin LDAC Operation

0 1/0 Determined by LDAC pin.

1 X—don’t care DAC channels update, overriding the LDAC pin. DAC channels see LDAC as 0.

Table 17. 32-Bit Input Shift Register Contents for LDAC Register Function

MSB LSB

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16

DB15

to DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 1 1 0 X X X X X DAC H DAC G DAC F DAC E DAC D DAC C DAC B DAC A

Command bits (C3 to C0) Address bits (A3 to A0)—

don’t cares

Don’t

cares Setting LDAC bit to 1 overrides LDAC pin

Data Sheet AD5629R/AD5669R

Rev. F | Page 29 of 30

OUTLINE DIMENSIONS

2.70

2.60 SQ

2.50

COMPLIANT

JEDEC STANDA RDS MO-220- WG GC.

0.65

BSC

4.10

4.00 SQ

3.90

0.45

0.40

0.35

0.80

0.75

0.70 0. 05 M A X

0.02 NOM

0.20 REF

0.20 M IN

COPLANARITY

0.08

PIN 1

INDICATOR

0.35

0.30

0.25

BO T TO M VIE W

PKG-004828

SEATING

PLANE

TOP VI E W

SIDE V IEW FOR PROPER CO NNE CTI ON OF

THE EXPOSED PAD, REFER TO

THE P IN CONF IGURATION AND

FUNCTI O N DE S CRI P T IO NS

SECTION OF THIS DATA SHEET.

02-22-2017-C

PIN 1

INDICATOR AREA OPTIONS

(SEE DETAIL A)

DETAIL A

(JEDEC 95)

EXPOSED

PAD

Figure 56. 16-Lead Lead Frame Chip Scale Package [LFCSP]

4 mm × 4 mm Body, 0.75 mm Package Height

(CP-16-17)

Dimensions shown in millimeters

16 9

PIN 1

SEATING

PLANE

8°

0°

4.50

4.40

4.30

6.40

BSC

5.10

5.00

4.90

0.65

BSC

0.15

0.05

1.20

MAX 0.20

0.09 0.75

0.60

0.45

0.30

0.19

COPLANARITY

0.10

COMP LI ANT TO JEDEC STANDARDS MO-153- AB

Figure 57. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

AD5629R/AD5669R Data Sheet

Rev. F | Page 30 of 30

10-23-2012-A

0.650

0.595

0.540

SIDE VIEW

0.270

0.240

0.210

0.340

0.320

0.300

COPLANARITY

0.05

SEATING

PLANE

BOTTOM VIEW

(BALL SI DE UP)

TOP VIEW

(BALL SI DE DOW N)

BALLA1

IDENTIFIER

0.50

REF

1.50

REF

2.645

2.605 SQ

2.565

Figure 58. 16-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-16-16)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description

Package

Option

Power-On

Reset to Code Accuracy

Internal

Reference

AD5629RARUZ-1 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±4 LSB INL 1.25 V

AD5629RARUZ-1-RL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±4 LSB INL 1.25 V

AD5629RBRUZ-2 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±1 LSB INL 2.5 V

AD5629RBRUZ-2-RL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±1 LSB INL 2.5 V

AD5629RACPZ-2-RL7 −40°C to +105°C 16-Lead LFCSP CP-16-17 Zero ±4 LSB INL 2.5 V

AD5629RACPZ-3-RL7 −40°C to +105°C 16-Lead LFCSP CP-16-17 Midscale ±4 LSB INL 2.5 V

AD5629RBCPZ-1-RL7 −40°C to +105°C 16-Lead LFCSP CP-16-17 Zero ±1 LSB INL 1.25 V

AD5629RBCPZ-2-RL7 −40°C to +105°C 16-Lead LFCSP CP-16-17 Zero ±1 LSB INL 2.5 V

AD5629RBCBZ-1-RL7 −40°C to +105°C 16-Lead WLCSP CB-16-16 Zero ±1 LSB INL 1.25 V

AD5669RARUZ-1 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±32 LSB INL 1.25 V

AD5669RARUZ-1-RL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±32 LSB INL 1.25 V

AD5669RBRUZ-2 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±16 LSB INL 2.5 V

AD5669RBRUZ-2-RL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±16 LSB INL 2.5 V

AD5669RACPZ-2-RL7 −40°C to +105°C 16-Lead LFCSP CP-16-17 Zero ±32 LSB INL 2.5 V

AD5669RACPZ-3-RL7 −40°C to +105°C 16-Lead LFCSP CP-16-17 Midscale ±32 LSB INL 2.5 V

AD5669RBCPZ-1-RL7 −40°C to +105°C 16-Lead LFCSP CP-16-17 Zero ±16 LSB INL 1.25 V

AD5669RBCPZ-2-RL7 −40°C to +105°C 16-Lead LFCSP CP-16-17 Zero ±16 LSB INL 2.5 V

AD5669RBCPZ-1500R7 −40°C to +105°C 16-Lead LFCSP CP-16-17 Zero ±16 LSB INL 1.25 V

AD5669RBCPZ-2500R7 −40°C to +105°C 16-Lead LFCSP CP-16-17 Zero ±16 LSB INL 2.5 V

AD5669RBCBZ-1-RL7 −40°C to +105°C 16-Lead WLCSP CB-16-16 Zero ±16 LSB INL 1.25 V

AD5669RBCBZ-1-R5 −40°C to +105°C 16-Lead WLCSP CB-16-16 Zero ±16 LSB INL 1.25 V

EVAL-AD5629RSDZ Evaluation Board

EVAL-AD5669RSDZ Evaluation Board

1 Z = RoHS Compliant Part.

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D08819-0-6/18(F)