25AA256-I/P - MICROCHIP - Datasheet.Live

25AA256/25LC256

Device Selection Table

Features:

• Max. Clock 10 MHz

• Low-Power CMOS Technology:

- Max. Write Current: 5 mA at 5.5V, 10 MHz

- Read Current: 6 mA at 5.5V, 10 MHz

- Standby Current: 1 μA at 5.5V

• 32,768 x 8-bit Organization

• 64-Byte Page

• Self-Timed Erase and Write Cycles (5 ms max.)

• Block Write Protection:

- Protect none, 1/4, 1/2 or all of array

• Built-In Write Protection:

- Power-on/off data protection circuitry

- Write enable latch

- Write-protect pin

• Sequential Read

• High Reliability:

- Endurance: 1,000,000 erase/write cycles

- Data retention: > 200 years

- ESD protection: > 4000V

• Temperature Ranges Supported:

• Pb-Free and RoHS Compliant

Pin Function Table

Description:

The Microchip Technology Inc. 25AA256/25LC256

(25XX256*) are 256 Kbit Serial Electrically Erasable

PROMs. The memory is accessed via a simple Serial

Peripheral Interface (SPI) compatible serial bus. The

bus signals required are a clock input (SCK) plus sep-

arate data in (SI) and data out (SO) lines. Access to the

device is controlled through a Chip Select (CS) input.

Communication to the device can be paused via the

hold pin (HOLD). While the device is paused,

transitions on its inputs will be ignored, with the

exception of Chip Select, allowing the host to service

higher priority interrupts.

The 25XX256 is available in standard packages

including 8-lead PDIP and SOIC, and advanced

packaging including 8-lead DFN and 8-lead TSSOP.

Package Types (not to scale)

Part Number VCC Range Page Size Temp. Ranges Packages

25LC256 2.5-5.5V 64 Byte I, E P, SN, SM, ST, MF

25AA256 1.8-5.5V 64 Byte I P, SN, SM, ST, MF

- Industrial (I): -40°Cto +85°C

- Automotive (E): -40°C to +125°C

Name Function

CS Chip Select Input

SO Serial Data Output

WP Write-Protect

VSS Ground

SI Serial Data Input

SCK Serial Clock Input

HOLD Hold Input

VCC Supply Voltage

HOLD

SCK

PDIP/SOIC

(P, SN, SM)

TSSOP

(ST)

DFN

VSS

HOLD

SCK

1VCC

(MF)

HOLD

SCK

Rotated TSSOP

(ST)

HOLD

SCK

256K SPI Bus Serial EEPROM

* 25XX256 is used in this document as a generic part number for the 25AA256, 25LC256 devices.

25AA256/25LC256

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings (†)

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V

Storage temperature .................................................................................................................................-65°C to 150°C

Ambient temperature under bias...............................................................................................................-40°C to 125°C

ESD protection on all pins..........................................................................................................................................4 kV

TABLE 1-1: DC CHARACTERISTICS

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an

extended period of time may affect device reliability.

DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V

Automotive (E): T

A = -40°C to +125°C VCC = 2.5V to 5.5V

Param.

No. Sym. Characteristic Min. Typ.(2) Max. Units Test Conditions

D001 VIH High-level input

voltage

.7 VCC —VCC +1 V

D002 VIL Low-level input

voltage

-0.3 — 0.3 VCC VVCC ≥ 2.5V

D003 VIL -0.3 — 0.2 VCC VVCC < 2.5V

D004 VOL Low-level output

voltage

——0.4VIOL = 2.1 mA, VCC = 4.5V

D005 VOL ——0.2VIOL = 1.0 mA, VCC = 2.5V

D006 VOH High-level output

voltage

VCC -0.5 — — V IOH = -400 μA

D007 ILI Input leakage current — — ±1 μACS = VCC, VIN = VSS OR VCC

D008 ILO Output leakage

current

——±1μACS = VCC, VOUT = VSS OR VCC

D009 CINT Internal Capacitance

(all inputs and

outputs)

——7pFTA = 25°C, FCLK = 1.0 MHz,

VCC = 5.0V (Note 1)

D010 ICC Read

Operating Current

—

2.5

0.5

2.5

VCC = 5.5V; FCLK = 10.0 MHz;

SO = Open

VCC = 2.5V; FCLK = 5.0 MHz;

SO = Open

D011 ICC Write —

—

0.6

0.15

VCC = 5.5V

VCC = 2.5V

D012 ICCS

Standby Current

—

0.1 5

μA

CS = VCC = 5.5V, Inputs tied to VCC

or VSS, 125°C

CS = VCC = 5.5V, Inputs tied to VCC

or VSS, 85°C

Note 1: This parameter is periodically sampled and not 100% tested.

2: Typical measurements taken at room temperature (25°C).

25AA256/25LC256

TABLE 1-2: AC CHARACTERISTICS

AC CHARACTERISTICS Industrial (I): T

A = -40°C to +85°C VCC = 1.8V to 5.5V

Automotive (E): T

A = -40°C to +125°C VCC = 2.5V to 5.5V

Param.

No. Sym. Characteristic Min. Max. Units Test Conditions

1FCLK Clock Frequency —

—

MHz

4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

1.8V ≤ Vcc < 2.5V

CSS CS Setup Time 50

100

150

—

4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

1.8V ≤ Vcc < 2.5V

CSH CS Hold Time 100

200

250

—

4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

1.8V ≤ Vcc < 2.5V

CSD CS Disable Time 50 — ns —

5 Tsu Data Setup Time 10

—

4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

1.8V ≤ Vcc < 2.5V

HD Data Hold Time 20

—

4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

1.8V ≤ Vcc < 2.5V

RCLK Rise Time — 100 ns (Note 1)

8TFCLK Fall Time — 100 ns (Note 1)

9THI Clock High Time 50

100

150

—

4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

1.8V ≤ Vcc < 2.5V

10 TLO Clock Low Time 50

100

150

—

4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

1.8V ≤ Vcc < 2.5V

11 TCLD Clock Delay Time 50 — ns —

12 TCLE Clock Enable Time 50 — ns —

13 TVOutput Valid from Clock

Low

—

100

160

4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

1.8V ≤ Vcc < 2.5V

14 THO Output Hold Time 0 — ns (Note 1)

15 TDIS Output Disable Time —

—

160

4.5V ≤ Vcc ≤ 5.5V (Note 1)

2.5V ≤ Vcc ≤ 4.5V (Note 1)

1.8V ≤ Vcc ≤ 2.5V (Note 1)

16 THS HOLD Setup Time 20

—

4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

1.8V ≤ Vcc < 2.5V

17 THH HOLD Hold Time 20

—

4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

1.8V ≤ Vcc < 2.5V

Note 1: This parameter is periodically sampled and not 100% tested.

2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle

is complete.

3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site

at www.microchip.com.

25AA256/25LC256

TABLE 1-3: AC TEST CONDITIONS

18 THZ HOLD Low to Output

High-Z

160

—

4.5V ≤ Vcc ≤ 5.5V (Note 1)

2.5V ≤ Vcc < 4.5V (Note 1)

1.8V ≤ Vcc < 2.5V (Note 1)

19 THV HOLD High to Output

Valid

160

—

4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

1.8V ≤ Vcc < 2.5V

20 TWC Internal Write Cycle

Time

—5ms(NOTE 2)

21 — Endurance 1M — E/W

Cycles

(NOTE 3)

TABLE 1-2: AC CHARACTERISTICS (CONTINUED)

AC CHARACTERISTICS Industrial (I): T

A = -40°C to +85°C VCC = 1.8V to 5.5V

Automotive (E): T

A = -40°C to +125°C VCC = 2.5V to 5.5V

Param.

No. Sym. Characteristic Min. Max. Units Test Conditions

Note 1: This parameter is periodically sampled and not 100% tested.

2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle

is complete.

3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site

at www.microchip.com.

AC Waveform:

VLO = 0.2V —

VHI = VCC – 0.2V (Note 1)

VHI = 4.0V (Note 2)

CL = 50 pF —

Timing Measurement Reference Level

Input 0.5 VCC

Output 0.5 VCC

Note 1: For VCC ≤ 4.0V

2: For VCC > 4.0V

25AA256/25LC256

FIGURE 1-1: HOLD TIMING

FIGURE 1-2: SERIAL INPUT TIMING

FIGURE 1-3: SERIAL OUTPUT TIMING

SCK

HOLD

16 16 17

Don’t Care 5

High-Impedance

n + 2 n + 1 n n - 1

n + 2 n + 1 n nn - 1

SCK

711

LSB in

MSB in

High-Impedance

Mode 1,1

Mode 0,0

SCK

MSB out ISB out

Don’t Care

Mode 1,1

Mode 0,0

25AA256/25LC256

2.0 FUNCTIONAL DESCRIPTION

2.1 Principles of Operation

The 25XX256 is a 32,768-byte Serial EEPROM

designed to interface directly with the Serial Peripheral

Interface (SPI) port of many of today’s popular

microcontroller families, including Microchip’s PIC®

microcontrollers. It may also interface with microcon-

trollers that do not have a built-in SPI port by using

discrete I/O lines programmed properly in firmware to

match the SPI protocol.

The 25XX256 contains an 8-bit instruction register. The

device is accessed via the SI pin, with data being

clocked in on the rising edge of SCK. The CS pin must

be low and the HOLD pin must be high for the entire

operation.

Table 2-1 contains a list of the possible instruction

bytes and format for device operation. All instructions,

addresses, and data are transferred MSB first, LSB

last.

Data (SI) is sampled on the first rising edge of SCK

after CS goes low. If the clock line is shared with other

peripheral devices on the SPI bus, the user can assert

the HOLD input and place the 25XX256 in ‘HOLD’

mode. After releasing the HOLD pin, operation will

resume from the point when the HOLD was asserted.

2.2 Read Sequence

The device is selected by pulling CS low. The 8-bit

READ instruction is transmitted to the 25XX256

followed by the 16-bit address, with the first MSB of the

address being a “don’t care” bit. After the correct READ

instruction and address are sent, the data stored in the

memory at the selected address is shifted out on the

SO pin. The data stored in the memory at the next

address can be read sequentially by continuing to

provide clock pulses. The internal Address Pointer is

automatically incremented to the next higher address

after each byte of data is shifted out. When the highest

address is reached (7FFFh), the address counter rolls

over to address 0000h allowing the read cycle to be

continued indefinitely. The read operation is terminated

by raising the CS pin (Figure 2-1).

2.3 Write Sequence

Prior to any attempt to write data to the 25XX256, the

write enable latch must be set by issuing the WREN

instruction (Figure 2-4). This is done by setting CS low

and then clocking out the proper instruction into the

25XX256. After all eight bits of the instruction are

transmitted, the CS must be brought high to set the

write enable latch. If the write operation is initiated

immediately after the WREN instruction without CS

being brought high, the data will not be written to the

array because the write enable latch will not have been

properly set.

Once the write enable latch is set, the user may

proceed by setting the CS low, issuing a WRITE

instruction, followed by the 16-bit address, with the first

MSB of the address being a “don’t care” bit, and then

the data to be written. Up to 64 bytes of data can be

sent to the device before a write cycle is necessary.

The only restriction is that all of the bytes must reside

in the same page.

For the data to be actually written to the array, the CS

must be brought high after the Least Significant bit (D0)

of the nth data byte has been clocked in. If CS is

brought high at any other time, the write operation will

not be completed. Refer to Figure 2-2 and Figure 2-3

for more detailed illustrations on the byte write

sequence and the page write sequence, respectively.

While the write is in progress, the STATUS register may

be read to check the status of the WPEN, WIP, WEL,

BP1 and BP0 bits (Figure 2-6). A read attempt of a

memory array location will not be possible during a

write cycle. When the write cycle is completed, the

write enable latch is reset.

Note: Page write operations are limited to writing

bytes within a single physical page,

regardless of the number of bytes

actually being written. Physical page

boundaries start at addresses that are

integer multiples of the page buffer size (or

‘page size’) and, end at addresses that are

integer multiples of page size – 1. If a

Page Write command attempts to write

across a physical page boundary, the

result is that the data wraps around to the

beginning of the current page (overwriting

data previously stored there), instead of

being written to the next page as might be

expected. It is therefore necessary for the

application software to prevent page write

operations that would attempt to cross a

page boundary.

25AA256/25LC256

BLOCK DIAGRAM

FIGURE 2-1: READ SEQUENCE

SCK

HOLD

STATUS

I/O Control Memory

Control

Logic

Dec

HV Generator

EEPROM

Array

Page Latches

Y Decoder

Sense Amp.

R/W Control

Logic

VCC

VSS

TABLE 2-1: INSTRUCTION SET

Instruction Name Instruction Format Description

READ 0000 0011 Read data from memory array beginning at selected address

WRITE 0000 0010 Write data to memory array beginning at selected address

WRDI 0000 0100 Reset the write enable latch (disable write operations)

WREN 0000 0110 Set the write enable latch (enable write operations)

RDSR 0000 0101 Read STATUS register

WRSR 0000 0001 Write STATUS register

SCK

0 234567891011 21222324252627282930311

0100000115 14 13 12 210

76543210

Instruction 16-bit Address

Data Out

High-Impedance

25AA256/25LC256

FIGURE 2-2: BYTE WRITE SEQUENCE

FIGURE 2-3: PAGE WRITE SEQUENCE

9 1011 2122232425262728293031

0000000115 14 13 12 21076543210

Instruction 16-bit Address Data Byte

High-Impedance

SCK

0 23456718

Twc

9 1011 2122232425262728293031

0000000115 14 13 12 21076543210

Instruction 16-bit Address Data Byte 1

SCK

0 23456718

41 42 43 46 47

76543210

Data Byte n (64 max)

SCK

32 34 35 36 37 38 3933 40

76543210

Data Byte 3

76543210

Data Byte 2

44 45

25AA256/25LC256

2.4 Write Enable (WREN) and Write

Disable (WRDI)

The 25XX256 contains a write enable latch. See

Table 2-1 for the Write-Protect Functionality Matrix.

This latch must be set before any write operation will be

completed internally. The WREN instruction will set the

latch, and the WRDI will reset the latch.

The following is a list of conditions under which the

write enable latch will be reset:

• Power-up

•WRDI instruction successfully executed

•WRSR instruction successfully executed

•WRITE instruction successfully executed

FIGURE 2-4: WRITE ENABLE SEQUENCE (WREN)

FIGURE 2-5: WRITE DISABLE SEQUENCE (WRDI)

SCK

0 2345671

High-Impedance

010000 01

SCK

0 2345671

High-Impedance

010000 01

25AA256/25LC256

2.5 Read Status Register Instruction

(RDSR)

The Read Status Register instruction (RDSR) provides

access to the STATUS register. The STATUS register

may be read at any time, even during a write cycle. The

STATUS register is formatted as follows:

TABLE 2-2: STATUS REGISTER

The Write-In-Process (WIP) bit indicates whether the

25XX256 is busy with a write operation. When set to a

‘1’, a write is in progress, when set to a ‘0’, no write is

in progress. This bit is read-only.

The Write Enable Latch (WEL) bit indicates the status

of the write enable latch and is read-only. When set to

a ‘1’, the latch allows writes to the array, when set to a

‘0’, the latch prohibits writes to the array. The state of

this bit can always be updated via the WREN or WRDI

commands, regardless of the state of write protection

on the STATUS register. These commands are shown

in Figure 2-4 and Figure 2-5.

The Block Protection (BP0 and BP1) bits indicate

which blocks are currently write-protected. These bits

are set by the user issuing the WRSR instruction. These

bits are nonvolatile, and are shown in Table 2-3.

See Figure 2-6 for the RDSR timing sequence.

FIGURE 2-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR)

76543210

W/R ---W/RW/R R R

WPEN xxxBP1 BP0 WEL WIP

W/R = writable/readable. R = read-only.

91011 12131415

11000000

7654 2 10

Instruction

Data from STATUS Register

High-Impedance

SCK

0 23456718

25AA256/25LC256

2.6 Write Status Register Instruction

(WRSR)

The Write Status Register instruction (WRSR) allows the

user to write to the nonvolatile bits in the STATUS

select one of four levels of protection for the array by

writing to the appropriate bits in the STATUS register.

The array is divided up into four segments. The user

has the ability to write-protect none, one, two, or all four

of the segments of the array. The partitioning is

controlled as shown in Table 2-3.

The Write-Protect Enable (WPEN) bit is a nonvolatile

bit that is available as an enable bit for the WP pin. The

Write-Protect (WP) pin and the Write-Protect Enable

(WPEN) bit in the STATUS register control the

programmable hardware write-protect feature. Hard-

ware write protection is enabled when WP pin is low

and the WPEN bit is high. Hardware write protection is

disabled when either the WP pin is high or the WPEN

bit is low. When the chip is hardware write-protected,

only writes to nonvolatile bits in the STATUS register

are disabled. See Table 2-1 for a matrix of functionality

on the WPEN bit.

See Figure 2-7 for the WRSR timing sequence.

TABLE 2-3: ARRAY PROTECTION

FIGURE 2-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)

BP1 BP0 Array Addresses

Write-Protected

00 none

01 upper 1/4

(6000h-7FFFh)

10 upper 1/2

(4000h-7FFFh)

11 all

(0000h-7FFFh)

91011 12131415

01000000

7654 210

Instruction Data to STATUS Register

High-Impedance

SCK

0 23456718

Note: An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write STATUS register

sequence.

25AA256/25LC256

2.7 Data Protection

The following protection has been implemented to

prevent inadvertent writes to the array:

• The write enable latch is reset on power-up

• A write enable instruction must be issued to set

the write enable latch

• After a byte write, page write or STATUS register

write, the write enable latch is reset

•CS

must be set high after the proper number of

clock cycles to start an internal write cycle

• Access to the array during an internal write cycle

is ignored and programming is continued

2.8 Power-On State

The 25XX256 powers on in the following state:

• The device is in low-power Standby mode

(CS =1)

• The write enable latch is reset

• SO is in high-impedance state

• A high-to-low-level transition on CS is required to

enter active state

TABLE 2-1: WRITE-PROTECT FUNCTIONALITY MATRIX

WEL

(SR bit 1)

WPEN

(SR bit 7) WP pin Protected Blocks Unprotected Blocks STATUS Register

0xxProtected Protected Protected

10xProtected Writable Writable

110 (low) Protected Writable Protected

111 (high) Protected Writable Writable

x = don’t care

25AA256/25LC256

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

3.1 Chip Select (CS)

A low level on this pin selects the device. A high level

deselects the device and forces it into Standby mode.

However, a programming cycle which is already

initiated or in progress will be completed, regardless of

the CS input signal. If CS is brought high during a

program cycle, the device will go into Standby mode as

soon as the programming cycle is complete. When the

device is deselected, SO goes to the high-impedance

state, allowing multiple parts to share the same SPI

bus. A low-to-high transition on CS after a valid write

sequence initiates an internal write cycle. After power-

up, a low level on CS is required prior to any sequence

being initiated.

3.2 Serial Output (SO)

The SO pin is used to transfer data out of the 25XX256.

During a read cycle, data is shifted out on this pin after

the falling edge of the serial clock.

3.3 Write-Protect (WP)

This pin is used in conjunction with the WPEN bit in the

STATUS register to prohibit writes to the nonvolatile

bits in the STATUS register. When WP is low and

WPEN is high, writing to the nonvolatile bits in the

STATUS register is disabled. All other operations

function normally. When WP is high, all functions,

including writes to the nonvolatile bits in the STATUS

low during a STATUS register write sequence will

disable writing to the STATUS register. If an internal

write cycle has already begun, WP going low will have

no effect on the write.

The WP pin function is blocked when the WPEN bit in

the STATUS register is low. This allows the user to

install the 25XX256 in a system with WP pin grounded

and still be able to write to the STATUS register. The

WP pin functions will be enabled when the WPEN bit is

set high.

3.4 Serial Input (SI)

The SI pin is used to transfer data into the device. It

receives instructions, addresses and data. Data is

latched on the rising edge of the serial clock.

3.5 Serial Clock (SCK)

The SCK is used to synchronize the communication

between a master and the 25XX256. Instructions,

addresses or data present on the SI pin are latched on

the rising edge of the clock input, while data on the SO

pin is updated after the falling edge of the clock input.

3.6 Hold (HOLD)

The HOLD pin is used to suspend transmission to the

25XX256 while in the middle of a serial sequence with-

out having to retransmit the entire sequence again. It

must be held high any time this function is not being

used. Once the device is selected and a serial

sequence is underway, the HOLD pin may be pulled

low to pause further serial communication without

resetting the serial sequence. The HOLD pin must be

brought low while SCK is low, otherwise the HOLD

function will not be invoked until the next SCK high-to-

low transition. The 25XX256 must remain selected

during this sequence. The SI, SCK and SO pins are in

a high-impedance state during the time the device is

paused and transitions on these pins will be ignored. To

resume serial communication, HOLD must be brought

high while the SCK pin is low, otherwise serial

communication will not resume. Lowering the HOLD

line at any time will tri-state the SO line.

Name PDIP/SOIC

TSSOP/DFN

Rotated

TSSOP Function

CS 1 3 Chip Select Input

SO 2 4 Serial Data Output

WP 3 5 Write-Protect Pin

VSS 4 6 Ground

SI 5 7 Serial Data Input

SCK 6 8 Serial Clock Input

HOLD 7 1 Hold Input

VCC 8 2 Supply Voltage

25AA256/25LC256

4.0 PACKAGING INFORMATION

4.1 Package Marking Information

T/XXXNNN

XXXXXXXX

YYWW

8-Lead PDIP

8-Lead SOIC (3.90 mm)

XXXXYYWW

XXXXXXXT

NNN

XXXX

TYWW

8-Lead TSSOP

NNN

I/P 1L7

25LC256

0528

Example:

SN 0528

25LC256I

1L7

5LE

I528

Example:

8-Lead DFN Example:

XXXXXXX

T/XXXXX

YYWW

25LC256

I/MF

0528

1L7

NNN

Legend: XX...X Part number or part number code

T Temperature (I, E)

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn)

Note: For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

TSSOP 1st Line Marking Codes

Device Standard Rotated

25AA256 5AE 5AEX

25LC256 5LE 5LEX

8-Lead SOIC (208 mil)

XXXXXXXX

YYWWNNN

Example:

25LC256

05281L7

I/SM

25AA256/25LC256

8-Lead Plastic Dual Flat, No Lead Package (MF) – 6x5 mm Body [DFN-S]

PUNCH SINGULATED

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package may have one or more exposed tie bars at ends.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e 1.27 BSC

Overall Height A – 0.85 1.00

Molded Package Thickness A2 – 0.65 0.80

Standoff A1 0.00 0.01 0.05

Base Thickness A3 0.20 REF

Overall Length D 4.92 BSC

Molded Package Length D1 4.67 BSC

Exposed Pad Length D2 3.85 4.00 4.15

Overall Width E 5.99 BSC

Molded Package Width E1 5.74 BSC

Exposed Pad Width E2 2.16 2.31 2.46

Contact Width b 0.35 0.40 0.47

Contact Length L 0.50 0.60 0.75

Contact-to-Exposed Pad K 0.20 – –

Model Draft Angle Top φ– – 12°

NOTE 2

NOTE 1

EXPOSED

PAD

BOTTOM VIEW

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Microchip Technology Drawing C04-113B

25AA256/25LC256

8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

Notes:

1. Pin 1 visual index feature may vary, but must be located with the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units INCHES

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e .100 BSC

Top to Seating Plane A – – .210

Molded Package Thickness A2 .115 .130 .195

Base to Seating Plane A 1 .015 – –

Shoulder to Shoulder Width E .290 .310 .325

Molded Package Width E1 .240 .250 .280

Overall Length D .348 .365 .400

Tip to Seating Plane L .115 .130 .150

Lead Thickness c .008 .010 .015

Upper Lead Width b1 .040 .060 .070

Lower Lead Width b .014 .018 .022

Overall Row Spacing § eB – – .430

NOTE 1

Microchip Technology Drawing C04-018

25AA256/25LC256

8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e 1.27 BSC

Overall Height A – – 1.75

Molded Package Thickness A2 1.25 – –

Standoff

A1 0.10 – 0.25

Overall Width E 6.00 BSC

Molded Package Width E1 3.90 BSC

Overall Length D 4.90 BSC

Chamfer (optional) h 0.25 – 0.50

Foot Length L 0.40 – 1.27

Footprint L1 1.04 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.17 – 0.25

Lead Width b 0.31 – 0.51

Mold Draft Angle Top α5° – 15°

Mold Draft Angle Bottom β5° – 15°

NOTE 1

12 3

Microchip Technology Drawing C04-057

25AA256/25LC256

(JEITA/EIAJ Standard, Formerly called SOIC)

8-Lead Plastic Small Outline (SM) – Medium, 5.28 mm Body [SOIJ]

Notes:

1. SOIJ, JEITA/EIAJ Standard, formerly called SOIC.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e 1.27 BSC

Overall Height A 1.77 – 2.03

Molded Package Thickness A2 1.75 – 1.98

Standoff § A1 0.05 – 0. 25

Overall Width E 7.62 – 8.26

Molded Package Width E1 5.11 – 5.38

Overall Length D 5.13 – 5.33

Foot Length L 0.51 – 0.76

Foot Angle φ0° – 8°

Lead Thickness c 0.15 – 0.25

Lead Width b 0.36 – 0.51

Mold Draft Angle Top α– – 15°

Mold Draft Angle Bottom β– – 15°

Microchip Technology Drawing C04-056B

25AA256/25LC256

8-Lead Plastic Thin Shri nk Small Outline (ST) – 4.4 mm Body [TSSOP]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e 0.65 BSC

Overall Height A – – 1.20

Molded Package Thickness A2 0.80 1.00 1.05

Standoff A1 0.05 – 0.15

Overall Width E 6.40 BSC

Molded Package Width E1 4.30 4.40 4.50

Molded Package Length D 2.90 3.00 3.10

Foot Length L 0.45 0.60 0.75

Footprint L1 1.00 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.09 – 0.20

Lead Width b 0.19 – 0.30

NOTE 1

L1 L

Microchip Technology Drawing C04-086

25AA256/25LC256

APPENDIX A: REVISION HISTORY

Revision C (11/03)

Corrections to Section 1.0, Electrical Characteristics.

Revision D (06/05)

Update package information

Revision E (08/05)

Remove Preliminary status. Revise Table 1-1, Params.

D011 and D012.

Revision F (05/07)

Update Pb-free; Replace Package Drawings (Rev. AP);

Update Product ID section.

25AA256/25LC256

THE MICROCHIP WEB SITE

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

•Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

•General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

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listing of seminars and events, listings of

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CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

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will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

CUSTOMER SUPPORT

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Development Systems Information Line

Customers should contact their distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

Technical support is available through the web site

at: http://support.microchip.com

25AA256/25LC256

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To: Technical Publications Manager

RE: Reader Response

Total Pages Sent ________

From: Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

Application (optional):

Would you like a reply? Y N

Device: Literature Number:

Questions:

FAX: (______) _________ - _________

DS21822F25AA256/25LC256

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

25AA256/25LC256

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X/XX

PackageTape & Reel

Device

Device: 25AA256

25LC256

25AA256X

25LC256X

256k-bit, 1.8V, 64-Byte Page, SPI Serial EEPROM

256k-bit, 2.5V, 64-Byte Page, SPI Serial EEPROM

256k-bit, 1.8V, 64-Byte Page, SPI Serial EEPROM,

rotated pinout (ST only)

256k-bit, 2.5V, 64-Byte Page, SPI Serial EEPROM,

rotated pinout (ST only)

Tape & Reel: Blank =

Standard packaging (tube)

Tape & Reel

Temperature

Range:

-40°C to+85°C

-40°C to+125°C

Package: MF =

SN =

ST =

SM =

Micro Lead Frame (6 x 5 mm body), 8-lead

Plastic DIP (300 mil body), 8-lead

Plastic SOIC (3.90 mml body), 8-lead

TSSOP, 8-lead

Plastic SOIC (5.28 mm body), 8-lead

Examples:

a) 25AA256T-I/SN = 256k-bit, 1.8V Serial

EEPROM, Industrial temp., Tape & Reel, SOIC

package

b) 25AA256T-I/ST = 256k-bit, 1.8V Serial

EEPROM, Industrial temp., Tape & Reel,

TSSOP package

c) 25LC256-I/P = 256k-bit, 2.5V Serial EEPROM,

Industrial temp., P-DIP package

d) 25LC256T-E/ST = 256k-bit, 2.5V Serial

EEPROM, Extended temp., Tape & Reel,

TSSOP package

e) 25LC256XT-I/ST = 256k-bit, 2.5V Serial

EEPROM, Industrial temp., Tape and Reel,

Rotated TSSOP package

–X

Temp Range

25AA256/25LC256

NOTES:

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable

Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The

Embedded Control Solutions Company are registered

trademarks of Microchip Technology Incorporated in the

U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,

MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select

Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,

WiperLock and ZENA are trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

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12/08/06