1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
WF4M32-XXX5
I/O
8
I/O
9
I/O
10
A
14
A
16
A
11
A
0
A
18
I/O
0
I/O
1
I/O
2
RESET
CS
2
GND
I/O
11
A
10
A
9
A
15
V
CC
CS
1
A
19
I/O
3
I/O
15
I/O
14
I/O
13
I/O
12
OE
A
17
WE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
24
I/O
25
I/O
26
A
7
A
12
A
21
A
13
A
8
I/O
16
I/O
17
I/O
18
V
CC
CS
4
NC
I/O
27
A
4
A
5
A
6
A20
CS
3
GND
I/O
19
I/O
31
I/O
30
I/O
29
I/O
28
A
1
A
2
A
3
I/O
23
I/O
22
I/O
21
I/O
20
11 22 33 44 55 66
1 12 23 34 45 56
August 2002 Rev. 4
I/O0-31 Data Inputs/Outputs
A0-21 Address Inputs
WE Write Enables
CS1-4 Chip Selects
OE Output Enable
VCC Power Supply
GND Ground
RESET Reset
FIG. 1 PIN CONFIGURATION FOR WF4M32-XH2X5 PIN DESCRIPTION
TOP VIEW
4MX32 5V FLASH MODULE, SMD 5962-97612 (pending)
FEATURES
nAccess Times of 100, 120, 150ns
nPackaging:
• 66 pin, PGA Type, 1.385" square, Hermetic
Ceramic HIP (Package 402).
• 68 lead, 40mm Low Profile CQFP ( Package
502 ), 3.5mm (0.140") height.
• 68 lead, Hermetic CQFP (G2T), 22.4mm
(0.880") square (Package 509) 4.57mm
(0.180") height. Designed to fit JEDEC 68
lead 0.990CQFJ footprint (Fig. 3)
nSector Architecture
• 32 equal size sectors of 64KBytes per each
2Mx8 chip
• Any combination of sectors can be erased. Also
supports full chip erase.
nMinimum 100,000 Write/Erase Cycles Minimum
BLOCK DIAGRAM
nOrganized as 4Mx32
nUser configurable as 8Mx16 or 16Mx8 in HIP and
G4T packages.
nCommercial, Industrial, and Military Temperature Ranges
n5 Volt Read and Write. 5V ± 10% Supply.
nLow Power CMOS
nData Polling and Toggle Bit feature for detection of
program or erase cycle completion.
nSupports reading or programming data to a sector
not being erased.
nRESET pin resets internal state machine to the read
mode.
nBuilt-in Decoupling Caps and Multiple Ground
Pins for Low Noise Operation, Separate Power
and Ground Planes to improve noise immunity
PRELIMINARY*
*This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
Note:
For programming information refer to Flash Programming 16M5 Application Note.
I/O
0-7
CS
1
I/O
8-15
CS
2
I/O
16-23
CS
3
I/O
24-31
CS
OE
A
0-20
4
A
21
2M
x 8
2M x 8
2M
x 8
2M x 8
2M
x 8
2Mx 8
2M
x 8
2M x 8
WE
RESET
2
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
White Electronic Designs
WF4M32-XXX5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
V
CC
A
11
A
12
A
13
A
14
A
15
A
16
CS
2
OE
CS
4
A
17
A
18
A
19
A
20
A21
RESET
NC
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
NC
A
0
A
1
A
2
A
3
A
4
A
5
CS
1
GND
CS
3
WE
A
6
A
7
A
8
A
9
A
10
V
CC
PIN DESCRIPTION
FIG. 2 PIN CONFIGURATION FOR WF4M32-XG4TX5
I/O0-31 Data Inputs/Outputs
A0-21 Address Inputs
WE Write Enable
CS1-4 Chip Selects
OE Output Enable
VCC Power Supply
RESET Reset
GND Ground
NC Not Connected
TOP VIEW
PIN DESCRIPTION
FIG. 3 PIN CONFIGURATION FOR WF4M32-XG2TX5
TOP VIEW
The White 68 lead G2T CQFP
fills the same fit and function
as the JEDEC 68 lead CQFJ or
68 PLCC. But the G2T has the
TCE and lead inspection
advantage of the CQFP form.
I/O0-31 Data Inputs/Outputs
A0-20 Address Inputs
WE Write Enables
CS1-2 Banks Selects
OE Output Enable
VCC Power Supply
GND Ground
RESET Reset
BLOCK DIAGRAM
BLOCK DIAGRAM
Note:
CS1& CS2 are used as bank select
I/O0-7
CS1
I/O8-15
CS2
I/O16-23
CS3
I/O24-31
CS
OE
A0-20
4
A
21
2M
x 8
2M x 8
WE
RESET
2M
x 8
2M x 8
2M
x 8
2M x 8
2M
x 8
2M x 8
BUFFER
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
V
CC
A
11
A
12
A
13
A
14
A
15
A
16
CS
1
OE
CS
2
A
17
NC
NC
NC
A
18
A
19
A
20
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
RESET
A
0
A
1
A
2
A
3
A
4
A
5
NC
GND
NC
WE
A
6
A
7
A
8
A
9
A
10
V
CC
2M x 8
8
I/O
0-7
CS
1
I/O
8-15
CS
2
I/O
16-23
I/O
24-31
A
0-20
OE
WE
RESET
2M x 8
2M x 8
8
2M x 8
2M x 8
8
2M x 8
2M x 8
8
2M x 8
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
WF4M32-XXX5
Parameter Symbol Conditions HIP G2T G4T Unit
Min Max Min Max Min Max
Input Leakage Current ILI VCC = 5.5, VIN = GND to VCC 10 10 10 µA
Output Leakage Current I LOx32 VCC = 5.5, VIN = GND to VCC 10 10 10 µA
VCC Active Current for Read (1) ICC1 CS = VIL, OE = VIH, f = 5MHz 320 215 345 mA
VCC Active Current for Program ICC2 CS = VIL, OE = VIH 420 295 445 mA
or Erase (2)
VCC Standby Current I CC3 VCC = 5.5, CS = VIH, f = 5MHz, RESET = VIH 20 2.0 95 mA
Output Low Voltage VOL IOL = 12.0 mA, VCC = 4.5 0.45 0.45 0.45 V
Output High Voltage VOH IOH = -2.5 mA, VCC = 4.5 0.85 x 0.85 x 0.85 x V
Vcc Vcc Vcc
Low VCC Lock-Out Voltage VLKO 3.2 4.2 3.2 4.2 3.2 4.2 V
Parameter
Symbol
HIP (H2) CQFP (G2T) CQFP( G4T)
OE capacitance COE 75 75 20
WE capacitance CWE 75 75 20
CS capacitance CCS 20 50 20
Data I/O capacitance CI/O 30 30 30
Address input capacitance CAD 75 75 20
This parameter is guaranteed by design but not tested.
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Ratings Unit
Voltage on Any Pin Relative to VSS VT-2.0 to +7.0 V
Power Dissipation PT8W
Storage Temperature Tstg -65 to +125 °C
Short Circuit Output Current IOS 100 mA
Endurance - Write/Erase Cycles 100,000 min cycles
(Mil Temp)
Data Retention (Mil Temp) 20 years
RECOMMENDED DC OPERATING CONDITIONS
Parameter Symbol Min Typ Max Unit
Supply Voltage VCC 4.5 5.0 5.5 V
Ground VSS 00 0V
Input High Voltage VIH 2.0 - VCC + 0.5 V
Input Low Voltage VIL -0.5 - +0.8 V
Operating Temperature (Mil.) TA -55 - +125 °C
Operating Temperature (Ind.) TA -40 - +85 °C
DC CHARACTERISTICS - CMOS COMPATIBLE
(VCC = 5.0V, GND = 0V, TA = -55°C TO +125°C)
NOTES:
1. The Icc current listed includes both the DC operating current and the frequency dependent component (@ 5MHz). The
frequency component typically is less than 2mA/MHz, with OE at VIH.
2. Icc active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions VIL = 0.3V, VIH = VCC - 0.3V
CAPACITANCE (PF)
(TA = +25°C, VIN = OV, F = 1.0MHZ)
HIP = 66 pin, PGA Type, 1.385" square, Hermetic
Ceramic HIP (Package 402).
G2T = 68 lead, Hermetic CQFP (G2T), 22.4mm (0.880")
square. Designed to fit JEDEC 68 lead 0.990" CQFJ
footprint (Fig. 3) (Package 509)
G4T = 68 lead, 40mm Low Profile CQFP, 3.5mm (0.140")
(Package 502 )
4
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White Electronic Designs
WF4M32-XXX5
AC CHARACTERISTICS FOR G2T PACKAGE WRITE/ERASE/PROGRAM OPERATIONS - WE CONTROLLED
(VCC = 5.0V, TA = -55°C TO +125°C)
Parameter Symbol -100 -120 -150 Unit
Min Max Min Max Min Max
Write Cycle Time tAVAV tWC 100 120 150 ns
Chip Select Setup Time tELWL tCS 000 ns
Write Enable Pulse Width tWLWH tWP 45 50 50 ns
Address Setup Time tAVWL tAS 000 ns
Data Setup Time tDVWH tDS 45 50 50 ns
Data Hold Time tWHDX tDH 000 ns
Address Hold Time tWLAX tAH 45 50 50 ns
Write Enable Pulse Width High tWHWL tWPH 20 20 20 ns
Duration of Byte Programming Operation (1) tWHWH1 300 300 300 µs
Sector Erase (2) tWHWH2 15 15 15 sec
Read Recovery Time before Write tGH
W
L000 µs
VCC Setup Time tVCS 50 50 50 µs
Chip Programming Time 44 44 44 sec
Chip Erase Time (3) 256 256 256 sec
Output Enable Hold Time (4) tOEH 10 10 10 ns
RESET Pulse Width tRP 500 500 500 ns
NOTES:
1. Typical value for tWHWH1 is 7µs.
2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
AC CHARACTERISTICS FOR G2T PACKAGE READ-ONLY OPERATIONS
(VCC = 5.0V, TA = -55°C TO +125°C)
Parameter Symbol -100 -120 -150 Unit
Min Max Min Max Min Max
Read Cycle Time tAVAV tRC 100 120 150 ns
Address Access Time tAVQV tACC 100 120 150 ns
Chip Select Access Time tELQV tCE 100 120 150 ns
Output Enable to Output Valid tGLQV tOE 40 50 55 ns
Chip Select High to Output High Z (1) tEHQZ tDF 20 30 35 ns
Output Enable High to Output High Z (1) tGHQZ tDF 20 30 35 ns
Output Hold from Addresses, CS or OE Change, tAXQX tOH 000ns
whichever is First
RST Low to Read Mode (1) tReady 20 20 20 µs
1. Guaranteed by design, not tested.
5
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White Electronic Designs
WF4M32-XXX5
AC CHARACTERISTICS FOR G2T PACKAGE WRITE/ERASE/PROGRAM OPERATIONS,CS CONTROLLED
(VCC = 5.0V, GND = 0V, TA = -55°C TO +125°C)
Parameter Symbol -100 -120 -150 Unit
Min Max Min Max Min Max
Write Cycle Time tAVAV tWC 100 120 150 ns
Write Enable Setup Time tWLEL tWS 000ns
Chip Select Pulse Width tELEH tCP 45 50 50 ns
Address Setup Time tAVEL tAS 000ns
Data Setup Time tDVEH tDS 45 50 50 ns
Data Hold Time tEHDX tDH 000ns
Address Hold Time tELAX tAH 45 50 50 ns
Chip Select Pulse Width High tEHEL tCPH 20 20 20 ns
Duration of Byte Programming Operation (1) tWHWH1 300 300 300 µs
Sector Erase Time (2) tWHWH2 15 15 15 sec
Read Recovery Time tGHEL 000µs
Chip Programming Time 44 44 44 sec
Chip Erase Time (3) 256 256 256 sec
Output Enable Hold Time (4) tOEH 10 10 10 ns
NOTES:
1. Typical value for tWHWH1 is 7µs.
2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
6
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White Electronic Designs
WF4M32-XXX5
AC CHARACTERISTICS FOR G4T AND H2 PACKAGES WRITE/ERASE/PROGRAM OPERATIONS - WE CONTROLLED
(VCC = 5.0V, TA = -55°C TO +125°C)
Parameter Symbol -100 -120 -150 Unit
Min Max Min Max Min Max
Write Cycle Time tAVAV tWC 100 120 150 ns
Chip Select Setup Time tELWL tCS 000 ns
Write Enable Pulse Width tWLWH tWP 45 50 50 ns
Address Setup Time tAVWL tAS 000 ns
Data Setup Time tDVWH tDS 45 50 50 ns
Data Hold Time tWHDX tDH 15 15 15 ns
Address Hold Time (1) tWLAX tAH 45 50 50 ns
Write Enable Pulse Width High (2) tWHWL tWPH 20 20 20 ns
Duration of Byte Programming Operation (3) tWHWH1 300 300 300 µs
Sector Erase (4) tWHWH2 15 15 15 sec
Read Recovery Time before Write tGH
W
L000 µs
VCC Setup Time tVCS 50 50 50 µs
Chip Programming Time 44 44 44 sec
Chip Erase Time (5) 256 256 256 sec
Output Enable Hold Time (6) tOEH 10 10 10 ns
RESET Pulse Width tRP 500 500 500 ns
NOTES:
1. A21 must be held constant until WE or CS go high, whichever occurs first.
2. Guaranteed by design, but not tested.
3. Typical value for tWHWH1 is 7µs.
4. Typical value for tWHWH2 is 1sec.
5. Typical value for Chip Erase Time is 32sec.
6. For Toggle and Data Polling.
AC CHARACTERISTICS FOR G4T AND H2 PACKAGES READ-ONLY OPERATIONS
(VCC = 5.0V, TA = -55°C TO +125°C)
Parameter Symbol -100 -120 -150 Unit
Min Max Min Max Min Max
Read Cycle Time tAVAV tRC 100 120 150 ns
Address Access Time tAVQV tACC 100 120 150 ns
Chip Select Access Time tELQV tCE 100 120 150 ns
Output Enable to Output Valid tGLQV tOE 50 50 55 ns
Chip Select High to Output High Z tEHQZ tDF 40 45 45 ns
Output Enable High to Output High Z tGHQZ tDF 40 45 45 ns
Output Hold from Addresses, CS or OE Change, tAXQX tOH 000ns
whichever is First
RST Low to Read Mode tReady 20 20 20 µs
7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
WF4M32-XXX5
AC CHARACTERISTICS FOR G4T AND H2 PACKAGES WRITE/ERASE/PROGRAM OPERATIONS,CS CONTROLLED
(VCC = 5.0V, GND = 0V, TA = -55°C TO +125°C)
FIG. 4 AC TEST CIRCUIT AC TEST CONDITIONS
Notes:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75
W
.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
Parameter Typ Unit
Input Pulse Levels
VIL = 0, VIH = 3.0
V
Input Rise and Fall 5 ns
Input and Output Reference Level 1.5 V
Output Timing Reference Level 1.5 V
Parameter Symbol -100 -120 -150 Unit
Min Max Min Max Min Max
Write Cycle Time tAVAV tWC 100 120 150 ns
Write Enable Setup Time tWLEL tWS 000ns
Chip Select Pulse Width tELEH tCP 45 50 50 ns
Address Setup Time tAVEL tAS 000ns
Data Setup Time tDVEH tDS 45 50 50 ns
Data Hold Time tEHDX tDH 15 15 15 ns
Address Hold Time (1) tELAX tAH 45 50 50 ns
Chip Select Pulse Width High tEHEL tCPH 20 20 20 ns
Duration of Byte Programming Operation (2) tWHWH1 300 300 300 µs
Sector Erase Time (3) tWHWH2 15 15 15 sec
Read Recovery Time tGHEL 000µs
Chip Programming Time 44 44 44 sec
Chip Erase Time (4) 256 256 256 sec
Output Enable Hold Time (5) tOEH 10 10 10 ns
NOTES:
1. A21 must be held constant until WE or CS go high, whichever occurs first.
2. Typical value for tWHWH1 is 7µs.
3. Typical value for tWHWH2 is 1sec.
4. Typical value for Chip Erase Time is 32sec.
5. For Toggle and Data Polling.
FIG. 5 RESET TIMING DIAGRAM
RESET
tRP
tReady
8
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
White Electronic Designs
WF4M32-XXX5
FIG. 6 AC WAVEFORMS FOR READ OPERATIONS
9
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White Electronic Designs
WF4M32-XXX5
NOTES:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D7 is the output of the complement of the data written to each chip.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
FIG. 7 WRITE/ERASE/PROGRAM OPERATION, WE CONTROLLED
10
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White Electronic Designs
WF4M32-XXX5
FIG. 8 AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS
NOTE:
1. SA is the sector address for Sector Erase.
11
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White Electronic Designs
WF4M32-XXX5
FIG. 9 AC WAVEFORMS FOR DATA POLLING DURING EMBEDDED A LGORITHM OPERATIONS
CS
OE
WE
t
OE
t
CE
t
CH
t
OH
D7 D7 =
Valid Data
High Z
D0-D6 = Invalid D0-D7
Valid Data
t
DF
D7
D0-D6
t
OEH
t
WHWH 1 or 2
Data
12
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
White Electronic Designs
WF4M32-XXX5
Notes:
1. PA represents the address of the memory location to be programmed.
2. PD represents the data to be programmed at byte address.
3. D7 is the output of the complement of the data written to each chip.
4. DOUT is the output of the data written to the device.
5. Figure indicates the last two bus cycles of a four bus cycle sequence.
FIG. 10 ALTERNATE CS CONTROLLED PROGRAMMING OPERATION TIMINGS
13
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White Electronic Designs
WF4M32-XXX5
PACKAGE 402: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H2)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
PACKAGE 502: 68 LEAD, CERAMIC QUAD FLAT PACK, LOW PROFILE CQFP (G4T)
14
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
White Electronic Designs
WF4M32-XXX5
PACKAGE 509: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2T)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
The White 68 lead G2T CQFP
fills the same fit and function
as the JEDEC 68 lead CQFJ or
68 PLCC. But the G2T has the
TCE and lead inspection
advantage of the CQFP form.
15
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White Electronic Designs
WF4M32-XXX5
DEVICE TYPE SECTOR SIZE SPEED PACKAGE SMD NO.
4M x 32 5V Flash Module 64KByte 150ns 66 pin HIP (H2) 5962-97612 01HXX*
4M x 32 5V Flash Module 64KByte 120ns 66 pin HIP (H2) 5962-97612 02HXX*
4M x 32 5V Flash Module 64KByte 100ns 66 pin HIP (H2) 5962-97612 03HXX*
4M x 32 5V Flash Module 64KByte 150ns 68 lead CQFP Low Profile (G4T) 5962-97612 01HXX*
4M x 32 5V Flash Module 64KByte 120ns 68 lead CQFP Low Profile (G4T) 5962-97612 02HXX*
4M x 32 5V Flash Module 64KByte 100ns 68 lead CQFP Low Profile (G4T) 5962-97612 03HXX*
4M x 32 5V Flash Module 64KByte 150ns 68 lead CQFP Low Profile (G2T) 5962-97612 01HXX*
4M x 32 5V Flash Module 64KByte 120ns 68 lead CQFP Low Profile (G2T) 5962-97612 02HXX*
4M x 32 5V Flash Module 64KByte 100ns 68 lead CQFP Low Profile (G2T) 5962-97612 03HXX*
ORDERING INFORMATION
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
V
PP
PROGRAMMING VOLTAGE
5 = 5 V
DEVICE GRADE:
M =Military Screened -55°C to +125°C
I =Industrial -40°C to +85°C
C =Commercial 0°C to +70°C
PACKAGE TYPE:
H2 =Ceramic Hex In line Package, HIP (Package 402)
G4T = 40mm Low Profile CQFP (Package 502)
G2T = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 509)
ACCESS TIME (ns)
ORGANIZATION, 4M x 32
User configurable as 8M x 16 or 16M x 8 in HIP and G4T packages
FLASH
WHITE ELECTRONIC DESIGNS CORP.
W F 4M32 - XXX X X 5 X
*Pending
