Rev 0.5 / Feb. 2006 1
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Document Title
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash Memory
Revision History
Revision
No. History Draft Date Remark
0.0 Initial Draft. Dec. 2004 Preliminary
0.1
1) Edit Pin Description table
2) Edit Data Protection texts
3) Add Read ID table
4) Add Marking Information
5) Add Application note
6) Change AC characteristics
May. 23. 2005 Preliminary
0.2
1) Add ULGA Package.
- Figures & texts are added.
2) Correct the test Conditions (DC Characteristics table)
3) Change AC Conditions table
4) Add tWW parameter ( tWW = 100ns, min)
- Texts & Figures are added.
- tWW is added in AC timing characteristics table.
5) Add tRBSY (Table12)
- tRBSY (Dummy Busy Time for Cache Read)
- tRBSY is 5us (typ.)
- Figure 19,20 are edited.
6) Edit System Interface Using CE don’t care Figures.
Aug. 09. 2005 Preliminary
tCLS tCLH tCS tCH tWP tALS tDS tDH
Before1051551510105
After0100102502010
tWC tWH tRP tRC tREA tREH tCEA
Before 30 10 15 30 18 10 23
After50152550352045
Test Conditions (ILI, ILO)
Before VIN=VOUT=0 to 3.6V
After VIN=VOUT=0 to Vcc (max)
Rev 0.5 / Feb. 2006 2
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Revision History
-Continued-
Revision
No. History Draft Date Remark
0.2
7) Change AC characteristics
8) Delete the errata.
9) Correct Address Cycle Map.
Aug. 09. 2005 Preliminary
0.3
1) Delete the 1.8V device’s features.
2) Change DC characteristics (Table 9)
- Operating Current
3) Correct PKG dimension (TSOP PKG)
Aug. 19. 2005 Preliminary
0.4 1) Delete Preliminary. Dec. 09. 2005
0.5
1) Correct tCS parameter in Autosleep
Feb. 14. 2006
tWH tR tREA tOH tREH
Before 20(4) 25 35 15 20
After1530301015
ICC1 ICC2 ICC3
Typ Max Typ Max Typ Max
Before 20 40 20 40 20 40
After153015301530
CP
Before 0.050
After 0.100
tCS
Before 100ns (Min.)
After 40ns (Min.)
Rev 0.5 / Feb. 2006 3
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES
- Cost effective solutions for mass storage applications
NAND INTERFACE
- x8 or x16 bus width.
- Multiplexed Address/ Data
- Pinout compatibility for all densities
SUPPLY VOLTAGE
- 3.3V device: VCC = 2.7 to 3.6V : HY27UFXX2G2M
Memory Cell Array
= (2K+ 64) Bytes x 64 Pages x 2,048 Blocks
= (1K+32) Words x 64 pages x 2,048 Blocks
PAGE SIZE
- x8 device : (2K + 64 spare) Bytes
: HY27UF082G2M
- x16 device: (1K + 32 spare) Words
: HY27UF162G2M
BLOCK SIZE
- x8 device: (128K + 4K spare) Bytes
- x16 device: (64K + 2K spare) Words
PAGE READ / PROGRAM
- Random access: 30us (max.)
- Sequential access: 50ns (min.)
- Page program time: 200us (typ.)
COPY BACK PROGRAM MODE
- Fast page copy without external buffering
CACHE PROGRAM MODE
- Internal Cache Register to improve the program
throughput
FAST BLOCK ERASE
- Block erase time: 2ms (Typ.)
STATUS REGISTER
ELECTRONIC SIGNATURE
- Manufacturer Code
- Device Code
CHIP ENABLE DON'T CARE OPTION
- Simple interface with microcontroller
AUTOMATIC PAGE 0 READ AT POWER-UP OPTION
- Boot from NAND support
- Automatic Memory Download
SERIAL NUMBER OPTION
HARDWARE DATA PROTECTION
- Program/Erase locked during Power transitions
DATA INTEGRITY
- 100,000 Program/Erase cycles
- 10 years Data Retention
PACKAGE
- HY27UF(08/16)2G2M-T(P)
: 48-Pin TSOP1 (12 x 20 x 1.2 mm)
- HY27UF(08/16)2G2M-T (Lead)
- HY27UF(08/16)2G2M-TP (Lead Free)
- HY27UF(08/16)2G2M-UP
: 52-ULGA (12 x 17 x 0.65 mm)
- HY27UF(08/16)2G2M-UP (Lead Free)
Rev 0.5 / Feb. 2006 4
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
1. SUMMARY DESCRIPTION
The HYNIX HY27UF(08/16)2G2M series is a 256Mx8bit with spare 8Mx8 bit capacity. The device is offe red in 3.3V Vcc
Power Supply.
Its NAND cell provides the most cost-effective solution for the solid state mass storage market.
The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old
data is erased.
The device contains 2048 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected
Flash cells.
A program operation allows to write the 2112 -byte pa ge in t ypical 200us an d an er as e op er ation can be perf orm ed in
typical 2ms on a 128K-byte(X8 device) block.
Data in the page mode can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and
data input/output as well as command input. This interf ace allows a reduced pin count an d easy migr ation towards dif-
ferent densities, without any rearrangement of footprint.
Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin.
The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where
required, and internal verification and margining of data.
The modifying can be locked using the WP input pin.
The output pin R/B (open drain buffer) signa ls the status of the d evice d uring each operation. In a system with multi-
ple memories the R/B pins can be connected all together to provide a global status signal.
Even the write-intensive systems can take advantage of the HY27UF(08/16)1G2M extended reliability of 100K pro-
gram/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.
Optionally the chip could be offered with the CE don’t care function. This option allows the direct download of the code
from the NAND Flash memory device by a microcontroller, since the CE transitions do not stop the read operation.
The copy back function allows the optimization of defective blocks management: whe n a page progr am operat ion fails
the data can be directly programmed in another page inside the same array section without the time consuming serial
data insertion phase.
The cache program feature allows the data insertion in the cache register while the data register is copied into the
flash array. This pipelined program operation improves the program throughput when long files are written inside the
memory.
A cache read feature is also implemented. This feature allows to dramatically improve the read throughput when con-
secutive pages have to be streamed out.
This device includes also extra f eatures like O TP/Unique ID area, Block Lock mechanism, Automatic Read at P ower Up,
Read ID2 extension.
The HYNIX HY27UF(08/16)2G2M series is available in 48 - TSOP1 12 x 20 mm, 52-ULGA 12 x 17 mm.
1.1 Product List
PART NUMBER ORIZATION VCC RANGE PACKAGE
HY27UF082G2M x8 2.7V - 3.6 Volt 48TSOP1 / 52-ULGA
HY27UF162G2M x16
Rev 0.5 / Feb. 2006 5
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Figure1: Logic Diagram
9&&
966
35(
:3
&/(
$/(
5(
:(
&( ,2a,2
,2a,2[2QO\
5%
IO15 - IO8 Data Input / Outputs (x16 only)
IO7 - IO0 Data Input / Outputs
CLE Command latch enable
ALE Address latch enable
CE Chip Enable
RE Read Enable
WE Write Enable
WP Write Protect
R/B Ready / Busy
Vcc Power Supply
Vss Ground
NC No Connection
PRE Power-On Read Enable, Lock Unlock
Table 1: Signal Names
Rev 0.5 / Feb. 2006 6
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
1&
1&
1&
1&
1&
1&
5%
5(
&(
1&
1&
9FF
9VV
1&
1&
&/(
$/(
:(
:3
1&
1&
1&
1&
1&
9VV
,2
,2
,2
,2
,2
,2
,2
,2
1&
35(
9FF
1&
1&
1&
,2
,2
,2
,2
,2
,2
,2
,2
9VV
1$1')ODVK
7623
[
1&
1&
1&
1&
1&
1&
5%
5(
&(
1&
1&
9FF
9VV
1&
1&
&/(
$/(
:(
:3
1&
1&
1&
1&
1&
1&
1&
1&
1&
,2
,2
,2
,2
1&
1&
35(
9FF
9VV
1&
1&
1&
,2
,2
,2
,2
1&
1&
1&
1&
1$1')ODVK
7623
[
Figure 2. 48TSOP1 Contactions, x8 and x16 Device
Rev 0.5 / Feb. 2006 7
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
1&
1&
1&
1&
1&
1&
1&
1&
1&
1&
1&
1&
:(
:3 966
,2
,2
,2 ,2
,2
,2
,2
966
,2
5%
1&
1& 1&
1&
1&
1&
1& 1&
1&
966
966
9&&
9&&
1& &/(
$/(
&(
5(
1&
1& 1&
1&
1&
1&
1&
1&
1&
$
%
&
'
(
)
*
+
-
.
/
0
1
Figure 3. 52-ULGA Contactions, x8 Device
(Top view through package)
Rev 0.5 / Feb. 2006 8
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
1.2 PIN DESCRIPTION
Pin Name Description
IO0-IO7
IO8-IO15(1)
DATA INPUTS/OUTPUTS
The IO pins allow to input command, address and data and to output data during read / program
operations. The inputs are latched on the rising edge of Write Enable (WE). The I/O buffer float to
High-Z when the device is deselected or the outputs are disabled.
CLE COMMAND LATCH ENABLE
This input activates the latching of the IO inputs inside the Command Register on the Rising edge of
Write Enable (WE).
ALE ADDRESS LATCH ENABLE
This input activates the latching of the IO inputs inside the Address Register on the Rising edge of
Write Enable (WE).
CE CHIP ENABLE
This input controls the selection of the device. When the device is busy CE low does not deselect the
memory.
WE WRITE EN AB LE
This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise
edge of WE.
RE
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is
valid tREA after the falling edge of RE which also increments the internal column address counter by
one.
WP WRITE PROTECT
The WP pin, when Low, provides an Hardware protection against undesired modify (program / erase)
operations.
R/B READY BUSY
The Ready/Busy output is an Open Drain pin that signals the state of the memory.
VCC SUPPLY VOLTAGE
The VCC supplies the power for all the operations (Read, Write, Erase).
VSS GROUND
NC NO CONNECTION
PRE
To Enable and disable the Lock mechanism and Power On Auto Read. When PRE is a logic high,
Block Lock mode and Power-On Auto-Read mode are enabled, and when PRE is a logic low, Block
Lock mode and Power-On Auto-Read mode are disabled. Power- On Auto-Read mode is available only
on 3.3V device.
Not using LOCK MECHANISM & POWER-ON AUTO-READ, connect it Vss or leave it NC
Table 2: Pin Description
NOTE:
1. For x16 version only
2. A 0.1uF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple
the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required
during program and erase operations.
Rev 0.5 / Feb. 2006 9
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7
1st Cycle A0 A1 A2 A3 A4 A5 A6 A7
2nd Cycle A8 A9 A10 A11 L(1) L(1) L(1) L(1)
3rd Cycle A12 A13 A14 A15 A16 A17 A18 A19
4th Cycle A20 A21 A22 A23 A24 A25 A26 A27
5th Cycle A28 L(1) L(1) L(1) L(1) L(1) L(1) L(1)
Table 3: Address Cycle Map(x8)
NOTE:
1. L must be set to Low.
IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8-IO15
1st Cycle A0 A1 A2 A3 A4 A5 A6 A7 L(1)
2nd Cycle A8 A9 A10 L(1) L(1) L(1) L(1) L(1) L(1)
3rd Cycle A11 A12 A13 A14 A15 A16 A17 A18 L(1)
4th Cycle A19 A20 A21 A22 A23 A24 A25 A26 L(1)
5th Cycle A27 L(1) L(1) L(1) L(1) L(1) L(1) L(1) L(1)
Table 4: Address Cycle Map(x16)
NOTE:
1. L must be set to Low.
FUNCTION 1st CYCLE 2nd CYCLE 3rd CYCLE Acceptable command
during busy
READ 1 00h 30h -
READ FOR COPY-BACK 00h 35h -
READ ID 90h - -
RESET FFh - - Yes
PAGE PROGRAM (start) 80h 10h -
COPY BACK PGM (start) 85h 10h -
CACHE PROGRAM 80h 15h -
BLOCK ERASE 60h D0h -
READ STATUS REGISTER 70h - - Yes
RANDOM DATA INPUT 85h - -
RANDOM DATA OUTPUT 05h E0h -
CACHE READ START 00h 31h -
CACHE READ EXIT 34h - -
LOCK BLOCK 2Ah - -
LOCK TIGHT 2Ch - -
UNLOCK (start area) 23h - -
UNLOCK (end area) 24h - -
READ LOCK STATUS 7Ah - -
Table 5: Command Set
Rev 0.5 / Feb. 2006 10
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
CLE ALE CE WE RE WP MODE
H L L Rising H X Read Mode Command Input
L H L Rising H X Address Input(5 cycles)
H L L Rising H H Wri te Mode Command Input
L H L Rising H H Address Input(5 cycles)
LLLRisingHHData Input
LL
L(1) H Falling X Sequential Read and Data Output
L L L H H X During Read (Busy)
XXXXXHDuring Program (Busy)
XXXXXHDuring Erase (Busy)
XXXXXLWrite Protect
XXHXX0V/VccStand By
Table 6: Mode Selection
NOTE:
1. With the CE don’t care option CE high during latency time does not stop the read operation
Rev 0.5 / Feb. 2006 11
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
2. BUS OPERATION
There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input,
Data Output, Write Protect, and Standby.
Typically glitches le ss than 5 ns o n Chip Enable, W rite Enab le and R ead Ena ble are ig nore d by the memo ry and do not
affect bus operations.
2.1 Command Input.
Command Input bus operation is used to give a command to the memory device. Command are accepted with Chip
Enable low, Command Latch Enable High, Address Latch Enable low an d Read Enable High and latched on the rising
edge of Write Enable. Moreover for commands that starts a modifying operation (write/erase) the Write Protect pin
must be high. See figure 5 and table 13 for details of the timings requirements. Command codes ar e always applied on
IO7:0, disregarding the bus configuration (X8/X16).
2.2 Address Input.
Address Input bus op er ation allows the ins ertion of the memory addr ess. To insert the 28 addresses needed to access
the 2Gbit 5 clock cycles are needed. Addresses are accepted with Chip Enable low, Address Latch Enable High, Com-
mand Latch Enable low and R ead Enable high and latche d on the rising edge of Write Enable. More over f or commands
that starts a modify operation (write/er ase) the W rite Protect pin must be high. See figure 6 and table 14 f or details of
the timings requirements. Addresses are always applied on IO7:0, disregarding the bus configuration (X8/X16).
2.3 Data Input.
Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serially and
timed by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command
Latch Enable low, Read Enable High, and Write Protect High and latched on the rising edge of W rite Enable. See figure
7 and table 13 for details of the timings requirements.
2.4 Data Output.
Data Output bus operation allows to read data from the memory array and to check the status register content, the
lock status and the ID data. Data can be serially shifted out toggling the Read Enable pin with Chip Enable low, Write
Enable High, Address Latch Enable low, and Command Latch Enable low. See figures 8,10,11,12,26,35 and table 13
for details of the timings requirements.
2.5 Write Protect.
Hardware Write Protection is activated when the Write Protect pin is low. In this condition modify operation do not
start and the content of the memory is not altered. Write Protect pin is not latched by Write Enable to ensure the pro-
tection even during the power up.
2.6 Standby.
In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced.
Rev 0.5 / Feb. 2006 12
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
3. DEVICE OPERATION
3.1 Page Read.
Upon initial devi ce power up , the device de fault s to R ead mode. This oper ati on is also initi ated by writ ing 00h and 30h
to the command register along with four address cycles. In two consecutive read operations, the second one doesn’t’
need 00h command, wh ich four address cy cles and 30h command initiates that op eration. Two types of oper ations are
available : random read, serial page read. The random read mode is enabled when the page address is changed. The
2112 bytes (X8 device) or 1056 words (X16 device) of data within the selected page are transferred to the data regis-
ters in less than 30us(tR). The syste m co ntr oller may detect the com pletion of this data transfer (tR) by analyzing the
output of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in 50ns cycle time
by sequentially pulsing RE. The r epetitive high to low transitions of the RE clock make the de vice output the data start-
ing from the selected column address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data out-
put command.
The column address of next data, which is going to be out, may be cha nged to the address which follows r andom data
output command.
Random data output can be operated multiple times regardless of how many times it is done in a page.
3.2 Page Program.
The device is progr ammed basically by pa ge, but it does allow multiple par tial page pr ogr amming of a word or consec-
utive bytes up to 2112 (X8 device) or words up to 1056 (X16 device), in a single page program cycle. The number of
consecutive partial page programming operation within the same page without an intervening erase operation must
not exceed 4 times for main array (X8 device:1time/512byte, X16 device:1time/256word) and 4 times for spare array
(X8 device:1time/16byte ,X16 device:1time/8word).
The addressing should be done in sequential order in a block 1. A page program cycle consists of a serial data
loading period in which up to 2112bytes (X8 device) or 1056words (X16 device) of data may be loaded into the data
register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate
cell.
The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the five cycle
address inputs and then serial data. The words other than those to be programmed do not need to be loaded. The
device supports random data input in a page. The column address of next data, which will be entered, may be
changed to the address which follows random data input command (85h). Random data input may be operated multi-
ple times regardless of how many times it is done in a page.
The Page Program confirm command (10h) initiates the programming process. Writing 10h alone without previously
entering the serial data will not initiate the pr ogr am ming process . The internal write s tate contro ller automatically ex e-
cutes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other
tasks. Once the progr am process starts, the R ead Status Regis ter command may be entered to read the status register.
The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit (I/
O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in
progress. When the Page Program is complete, the Write Status Bit (I/O 0) may be checked. The internal write verify
detects only errors for "1"s that are not successfully programme d to "0"s . The command r egister r ema ins in Read Sta-
tus command mode until another va lid command is written to the command register. Figure 13 details the sequence.
Rev 0.5 / Feb. 2006 13
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
3.3 Block Erase.
The Erase oper ation is done on a block basis. Block addr ess loading is accomplished in two cycles initiated by an Erase
Setup command (60h). Only addr ess A18 to A28 (X8) or A17 to A27 (X16) is v alid while A12 to A17 (X8) or A11 to A16
(X16) is ignored. The Erase Confirm command (D0h) following the block address loading initiates the internal erasing
process. This two-step sequence of setup f ollowed by ex ecutio n command ensur es that memory contents are not acci-
dentally erased due to external noise conditions.
At the rising edg e of WE af ter th e er ase confirm comm and input, the internal write controller handles erase and er ase-
verify.
Once the era se process starts , the R ead Status Register command may be entered to r ead the status register. The sys-
tem controller can detect the completion of an er ase by m onitoring the R/B output, or the Status bit (I/O 6) of the Sta-
tus Register. Only the Read Status command and Reset command are valid while erasing is in progress. When the
erase operation is completed, the Write Status Bit (I/O 0) may be checked.
Figure 17 details the sequence.
3.4 Copy-Back Program.
The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an
external memory. Since the time-consuming cycles of serial access and re-loading cy cles are re moved, the sys tem per-
formance is improved. The bene fit is especially obvious when a portion of a block is updated and the rest of the block
also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a
sequential execution of page-read without serial access and copying-program with the address of destination page. A
read operation with "35h" command and the address of the source page moves the whole 2112byte (X8 device) or
1056word (X16 device) data into the internal data buffer. As soon as the device returns to Ready state, Copy Back
command (85h) with the address cycles of destination page may be written. The Program Confirm command (10h) is
required to actually beg in the programming operation. Data input cycle for modifying a port ion or multip le distant por-
tions of the source page is allowed as shown in Figure 15.
"When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But, if
Copy-Back operations are accumu lated over time, bit e rror due to charge loss is not checked by external
error detection/correction scheme. For this reason, two bit error correction is recommended for the u se
of Copy-Back operation."
Figure 15 shows the command sequence for the copy-back operation.
3.5 Read Status Register.
The device contains a Status Register which ma y be read to find out whether rea d, progra m or erase oper ation is com-
pleted, and whether the progr am or er as e oper a tion is c omplet ed successf u lly. After writ ing 70h c ommand to t he com-
mand register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE,
whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory
connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer
to table 14 for specific Status Register definitions. The command register remains in Status Read mode until further
commands are issued to it. Therefore, if the status register is read during a random read cycle, the read command
(00h) should be given before starting read cycles. See figure 9 for details of the Read Status operation.
Rev 0.5 / Feb. 2006 14
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
3.6 Read ID.
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an
address input of 00h. Four read cycles sequentially output the manufacturer code (ADh), and the device code and
00h(don’t care), 4th cycle ID, respectively. The command register remains in Read ID mode until further commands
are issued to it. Figure 18 shows the operation sequence, while table 15, 16, 17 explain the byte meaning.
3.7 Reset.
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state
during random read, pr ogr am or er ase mode, the res et operation will abort these operations. The contents of memory
cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is
cleared to wait for the next comm and, and the Status R egister is clear ed to value E0h when WP is high. Ref er to table
15 for device status after reset operation. If the device is already in reset state a new reset command will not be
accepted by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Refer
to figure 28.
3.8 Cache Program.
Cache Program is an extension of Page Program, which is executed with 2112byte (X8 device) or 1056word (X16
device) data registers, and is available only within a block. Since the device has 1 page of cache memory, serial data
input may be executed while data stored in data register are programmed into memory cell. After writing the first set
of data up to 2112byte (X8 device) or 1056word (X16 device) into the selected cache registers, Cache Program com-
mand (15h) instead of actual Pa ge Program (10h) is input to make cache registers free and to start internal program
operation. To transfer data from cache registers to data registers, the device remains in Busy state for a short period
of time (tCBSY) and has its cache registers ready for the next data-input while the internal programming gets started
with the data loaded into data registers. Read Status command (70h) may be issued to find out when cache registers
become ready by polling the Cache-Busy st atus bit (I/O 6). Pass/fail status of only the previous page is available upon
the return to Ready state. When the next set of data is input with the Cache Program command, tCBSY is affected by
the progress of pending internal programming. The programming of the cache registers is initiated only when the
pending progr am cycle is finished and the data registers are availa ble for the trans fer of data fr om cache registers. The
status bit (I/O5) for internal Ready/Busy may be polled to identify the completion of internal programming.
If the system monitors the p rogress of pr ogr amming only with R/B , the last page of the target progr amming sequence
must be programmed with actual Page Program command (10h). If the Cache Program command (15h) is used
instead, status bit (I/O5) must be polled to find out when the last programming is actually finished before starting
other operat ions such as read. Pass/fail status is available in two steps. I/O 1 returns with the status of the previous
page upon Ready or I/O6 status bit changing to "1", and later I/O 0 with the status of current page upon true Ready
(returning from internal programming) or I/O 5 status bit changing to "1". I/O 1 may be read together when I/O 0 is
checked. See figure 16 for more details.
NOTE : Since programming the last page does not employ caching, the program time has to be that of Page Program.
However, if the previous program cycle with the cache data has not finished, the actual program cycle of the
last page is initiated only after completion of the previous cycle, which can be expressed as the following
formula.
tPROG= Program time for the last page+ Progra m time for the ( last -1 )th page -
(Program command cycle time + Last page data loading time)
Rev 0.5 / Feb. 2006 15
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
3.9 Cache Read
Cache read oper ation allows automa tic download of consecut ive pa ges, up to the whole device. Immedia tely afte r 1st
latency end, while user can start reading out data, device internally starts reading following page.
Start address of 1st page is at page start (A<10:0>=00h), after 1st latency time (tr) , automatic data download will
be uninterrupted. In f a ct latency time is 30us, while downlo ad of a page requir e at least 100us f or x8 device (50us fo r
x16 device).
Cache read operation command is like standard read, except for confirm code (30h for standard read, 31h for cache
read) user can check operation status using :
- R/B ( ‘0’ means latency ongoing, download not possible, ‘1’ means download of n page possible, even if device
internally is active on n+1 page
- Status register (SR<6> behave like R/B, SR<5> is ‘0’ when device is internally reading and ‘1’ when device is idle)
To exit cache read operation a cache read exit command (34h) must be issued. this command can be given any time
(both device idle and reading).
If device is active (SR<5>=0) it will go idle within 5us, while if it is not active, device itself will go busy for a time
shorter then tRBSY before becoming again idle and ready to accept any further commands.
If user arrives reading last byte/word of the memory array, then has to stop by giving a cache read exit command.
Random data output is not available in cache read.
Cache read operation must be done only block by block if system needs to avoid reading also from invalid blocks.
Rev 0.5 / Feb. 2006 16
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
4. OTHER FEATURES
4.1 Data Protection & Power On/Off Sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal
voltage detector disables all functions whenever Vcc is below about 2V(3.3V device). WP pin provides hardware pro-
tection and is recommended to be kept at VIL during powe r-up an d power- down. A recove ry time of minimum 10us is
required before internal circuit gets ready for any command sequences as shown in Figure 29.
The two-step command sequence for program/erase provides additional software protection.
4.2 Ready/Busy.
The device has a Ready/Busy output that provides method of indicating the completion of a page program, erase,
copy-back, cache progr am and random read completion. The R/B pin is normally high and goes to low when the device
is busy (after a reset, read, pr og ram, erase oper a tion). It re turns to high when the internal controller has finished the
operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up
resistor value is related to tr(R/B) and current drain during busy (Ibusy), an appropriate value can be obtained with
the following refere nce chart (Fig 30). Its value can be determined by the following guidance.
4.3 Lock Block Feature
In high state of PRE pin, Block lock mode and Power on Auto read are enabled, otherwise it is regarded
as NAND Flash without PRE pin.
Block Lock mode is enabled while PRE pin state is high, which is to off er prote ction fe atures f or NAND Flash data. The
Block Lock mode is divided into Unlock, Lock, Lock-tight operation. Consecutive blocks protects data allows those
blocks to be locked or lock-tighten with no latency. This block lock scheme offers two levels of protection. The first
allows so ftware control (command input method) of block locking that is useful for frequently changed data blocks,
while the second requires hardware control (WP low pulse input method) bef or e lock ing can be changed that is usef ul
for protecting infrequently changed code blocks. The followings summarized the locking functionality.
- All blocks are in a locked state on power-up. Unlock sequence can unlock the locked blocks.
- The Lock-tight command locks blocks and prevents from being unlocked. Lock-tight state can be returned to lock
state only by Hardware control(WP low pulse input).
1. Block lock operation
1) Lock
- Command Sequence: Lock block Command (2Ah). See Fig. 23.
- All blocks default to locked by power-up and Hardware control (WP low pulse input)
- Partial block lock is not available; Lock block operation is based on all block unit
- Unlocked blocks can be locked by using the Lock block command, and a lock block’s status can be changed to
unlock or lock-tight using the appropriate commands
- On the program or erase operation in Locked or Lock-tighten block, Busy state holds 1~10us(tLBSY)
Rev 0.5 / Feb. 2006 17
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
2) Unlock
- Command Sequence: Unlock block Command (23h) + Start block address + Command (24h) + End block address.
See Fig. 24.
- Unlocked blocks can be programmed or erased.
- An unlocked block’s status can be changed to the locked or lock-tighten state using the appropriate sequence of
commands.
- Only one consecutive area can be released to unlock state from lock state; Unlocking multi area is not available.
- Start block address must be nearer to the logical LSB (Least Significant Bit) than End block address.
- One block is selected for unlocking block when Start block address is same as End block address.
3) Lock-tight
- Command Sequence: Lock-tight block Command (2Ch). See Fig. 25.
- Lock -tighten blocks offer the user an additional level of write protection beyond that of a regular lock block. A block
that is lock-tighten can’t have its state changed by software control, only by hardware control (WP low pulse
input); Unlocking multi area is not available
- Only locked blocks can be lock-tighten by lock-tight command.
- On the program or erase operation in Locked or Lock-tighten block, Busy state holds 1~10us(tLBSY)
2. Block lock Status Read
Block Lock Status can be read on a block basis to find out whether designated block is available to be programmed or
erased. After writing 7Ah command to the command register and block address to be checked, a read cycle outputs
the content of the Block Lock Status R egister to the I/O pins on the falling edge of CE or RE, whichever occurs last. RE
or CE does not need to be toggled for updated status. Block Lock Status Read is prohibited while the device is busy
state.
Refer to table 18 for specific Status Register definitions. The command register remains in Block Lock Status Read
mode until further commands are issued to it.
In high state of PRE pin, write protection status can be checked by Block Lock Status Read (7Ah) while
in low state by Status Read (70h).
4.4 Power-On Auto-Read (Auto-Cache read)
The device is designed to off er a utomatic reading of the first page without command and address inp ut sequence dur-
ing power-on.
This feature is available in 2 possible configurations.
- Auto-Read : automatic download of page 0 block 0
- Auto-Cache read : automatic download starting from page 0 block 0. This cache read operation allows download of
any portion of memory, without any latency time. whole 1Gbit can be therefore dow nlo aded, if fir mw ar e c an manag e
passing thru bad blocks.
An internal voltage detector en ables auto-page read f unctions when Vcc reaches about 1.8V. PRE pin does NOT control
activation of auto- page re ad function. Au to-page read function is enabled only wh en PRE pin is logic high state. Serial
access may be done after power-on without latency. Power-On Auto Read mode is available only on 3.3V device.
Alternatively the device can support an automatic cache read download, with all same function alities stated just abo ve
for auto-read.
Rev 0.5 / Feb. 2006 18
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Symbol Parameter Value Unit
3.3V
TA
Ambient Operating Temperature (Commercial Temperature Range) 0 to 70 ℃
Ambient Operating Temperature (Extended Temperature Range) -25 to 85 ℃
Ambient Operating Temperature (Industrial Temperature Range) -40 to 85 ℃
TBIAS Temperature Under Bias -50 to 125 ℃
TSTG Storage Temperature -65 to 150 ℃
VIO(2) Input or Output Voltage -0.6 to 4.6 V
Vcc Supply Voltage -0.6 to 4.6 V
Table 8: Absolute maximum ratings
NOTE:
1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute
Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of
the device at these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
2. Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions.
Parameter Symbol Min Typ Max Unit
Valid Block Number NVB 2008 2048 Blocks
Table 7: Valid Blocks Number
Rev 0.5 / Feb. 2006 19
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
$''5(66
5(*,67(5
&2817(5
352*5$0
(5$6(
&21752//(5
+9*(1(5$7,21
&200$1'
,17(5)$&(
/2*,&
&200$1'
5(*,67(5
'$7$
5(*,67(5
,2
5(
%8))(56
<'(&2'(5
3$*(%8))(5
;
'
(
&
2
'
(
5
0ELW0ELW
1$1')ODVK
0(025<$55$<
:3
&(
:(
&/(
$/(
35(
$a$
Figure 4: Block Diagram
Rev 0.5 / Feb. 2006 20
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Parameter Symbol Test Conditions 3.3Volt Unit
Min Typ Max
Operating
Current
Sequential
Read ICC1 tRC=50ns
CE=VIL,
IOUT=0mA -1530mA
Program ICC2 --1530mA
Erase ICC3 --1530mA
Stand-by Current (TTL) ICC4 CE=VIH,
PRE=WP=0V/Vcc --1mA
Stand-by Current (CMOS) ICC5 CE=Vcc-0.2,
PRE=WP=0V/Vcc -1050uA
Input Leakage Current ILI VIN=0 to Vcc (max) - - ±10 uA
Output Leakage Current ILO VOUT =0 to Vcc (max) - - ±10 uA
Input High Voltage VIH - 0.8xVcc - Vcc+0.3 V
Input Low Voltage VIL - -0.3 - 0.2xVcc V
Output High Voltage Level VOH IOH=-100uA - - - V
IOH=-400uA 2.4 - - V
Output Low Voltage Level VOL IOL=100uA - - - V
IOL=2.1mA - - 0.4 V
Output Low Current (R/B)IOL
(R/B)VOL=0.2V - - - mA
VOL=0.4V 8 10 - mA
Table 9: DC and Operating Characteristics
Parameter Value
3.3Volt
Input Pulse Levels 0V to Vcc
Input Rise and Fall Times 5ns
Input and Output Timing Levels Vcc/2
Output Load (2.7V - 3.3V) 1 TTL GATE and CL=50pF
Output Load (3.0V - 3.6V) 1 TTL GATE and CL=100pF
Table 10: AC Conditions
Rev 0.5 / Feb. 2006 21
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Item Symbol Test Condition Min Max Unit
Input / Output Capacitance CI/O VIL=0V - 10 pF
Input Capacitance CIN VIN=0V - 10 pF
Table 11: Pin Capacitance (TA=25℃, F=1.0MHz)
Parameter Symbol Min Typ Max Unit
Program Time tPROG - 200 700 us
Dummy Busy Time for Cache Program tCBSY -3700us
Dummy Busy Time for Cache Read tRBSY -5-us
Dummy Busy Time for the Lock or Lock-tight Block tLBSY -510us
Number of partial Program Cycles in the same page Main Array NOP - - 4 Cycles
Spare Array NOP - - 4 Cycles
Block Erase Time tBERS -23ms
Table 12: Program / Erase Characteristics
Rev 0.5 / Feb. 2006 22
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Parameter Symbol 3.3Volt Unit
Min Max
CLE Setup time tCLS 0ns
CLE Hold time tCLH 10 ns
CE setup time tCS 0(5) ns
CE hold time tCH 10 ns
WE puls e width tWP 25(3) ns
ALE setup time tALS 0ns
ALE hold time tALH 10 ns
Data setup time tDS 20 ns
Data hold time tDH 10 ns
Write Cycle time tWC 50 ns
WE High hold time tWH 15 ns
ALE to Data Loading Time tADL(2) 100 ns
Data Transfer from Cell to register tR30 us
ALE to RE Delay tAR 10 ns
CLE to RE Delay tCLR 10 ns
Ready to RE Low tRR 20 ns
RE Pulse Width tRP 25 ns
WE High to Busy tWB 100 ns
Read Cycle Time tRC 50 ns
RE Access Time tREA 30 ns
RE High to Output High Z tRHZ 30 ns
CE High to Output High Z tCHZ 20 ns
RE or CE High to Output Hold tOH 10 ns
RE High Hold Time tREH 15 ns
Output High Z to RE low tIR 0ns
CE Access Time tCEA 45 ns
WE High to RE low tWHR 60 ns
Device Resetting Time (Read / Program / Erase) tRST 5/10/500(1) us
Write Protection time tWW(4) 100 ns
Table 13: AC Timing Characteristics
NOTE:
1. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us
2. tADL is the time from the WE rising edge of final address cycle WE rising edge of first data cycle.
3. If tCS is less than 10ns tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.
4. Program / Erase Enable Operation : WP high to WE High.
Program / Erase Disable Operation : WP Low to WE High.
5. tCS=min. 40ns after Autosleep
Rev 0.5 / Feb. 2006 23
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
IO Page
Program Block
Erase Cache
Program Read Cache
Read CODING
0 Pass / Fail Pass / Fail Pass / Fail (N) NA Pass: ‘0’ Fail: ‘1’
1 NA NA Pass / Fail (N-1) NA Pass: ‘0’ Fail: ‘1’
(Only for Cache Program,
else Don’t care)
2NA NA NA NA -
3NA NA NA NA -
4NA NA NA NA -
5 Ready/Busy Ready/Busy P/E/R
Controller Bit Ready/Busy P/E/R
Controller Bit Active: ‘0’ Idle: ‘1’
6 Ready/Busy Ready/Busy Cache Register
Free Rea dy/ Bu sy Read y/ Busy Busy: ‘0’ Ready’: ‘1’
7 Write Protect Write Pr otect Write Protect Write Protect Protected: ‘0’ Not
Protected: ‘1’
Table 14: Status Register Coding
DEVICE IDENTIFIER BYTE DESCRIPTION
1st Manufacturer Code
2nd Device Identifier
3rd Don't care
4th Page Size, Block Size, Spare Size, Organization
Table 15: Device Identifier Coding
Rev 0.5 / Feb. 2006 24
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Description IO7 IO6 IO5-4 IO3 IO2 IO1-0
Page Size
(Without Spare Area)
1K
2K
Reserved
Reserved
0 0
0 1
1 0
1 1
Spare Area Size
(Byte / 512Byte) 8
16 0
1
Serial Access Time
50ns / 30ns
25ns
Reserved
Reserved
0
1
0
1
0
0
1
1
Block Size
(Without Spare Area)
64K
128K
256K
Reserved
0 0
0 1
1 0
1 1
Organization X8
X16 0
1
Table 16: 4th Byte of Device Identifier Description
Part Number Voltage Bus Widt Manufacture Code Device Code 3rd code 4th code
HY27UF082G2M 3.3V x8 ADh DAh don’t care 15h
HY27UF162G2M 3.3V x16 ADh CAh don’t care 55h
Table 17: Read ID Data Table
Rev 0.5 / Feb. 2006 25
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
,2a,2 ,28QORFN ,2/RFN ,2/RFNWLJKW
;
;
;
;
5HDGEORFNFDVH
5HDGEORFNFDVH
5HDGEORFNFDVH
5HDGEORFNFDVH
/RFN
8QORFN
/RFN
/RFNWLJKW
8QORFN
/RFNWLJKW
/RFN 8QORFN /RFNWLJKW
Figure 5: Command Latch Cycle
W&/
6
W&6
W:3
&RPPDQG
&/(
&(
:(
$/(
,2[
W'+W'6
W$/6 W$/+
W&/+
W&+
Table 18: Lock Status Code
Rev 0.5 / Feb. 2006 26
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
W&/6
W&6
W:3
W:& W:& W:&
W:3 W:3 W:3
W$/6
W:+W:+W:+W:+
W$/+ W$/6W$/6W$/6W$/6
&RO$GG
W$/+ W$/+ W$/+ W$/+
W'+
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W:&
W'+ W'+ W'+ W'+
W'6 W'6 W'6 W'6
W'6
&/(
&(
:(
$/(
,2[
Figure 6: Address Latch Cycle
Rev 0.5 / Feb. 2006 27
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
W:&W$/6
W&/+
W&+
W:3
W:+
',1 ',1 ',1ILQDO
W:+
W'+ W'+ W'+
W'6 W'6 W'6
W:3 W:3
&/(
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:(
Figure 8: Sequential Out Cycle after Read (CLE=L, WE=H, ALE=L)
W
&($
W
5($
W
53
W
5($
W
5+=
W
5+=
'RXW
127(67UDQVLWLRQLVPHDVXUHGP9IURPVWHDG\VWDWHYROWDJHZLWKORDG
7KLVSDUDPHWHULVVDPSOHGDQGQRWWHVWHG
'RXW 'RXW
W
&+=
W
2+
W
2+
W
5($
W
5(+
W
5&
W
55
&(
5(
5%
,2[
Figure 7. Input Data Latch Cycle
Rev 0.5 / Feb. 2006 28
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Figure 9: Status Read Cycle
W&/6
W&/5
W&/+
W&6
W&+
W:3
W:+5
W&($
W'6 W5($
W&+=
W5+=
K 6WDWXV2XWSXW
W'+ W,5
&(
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[
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5(
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:&
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55
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%XV\
'RXW1 'RXW1 'RXW0
W
:%
W
$5
W
5
W
5&
W
5+=
Figure 10: Read1 Operation (Read One Page)
Rev 0.5 / Feb. 2006 29
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
W55
W5
&ROXPQ$GGUHVV
K
&RO$GG
&/(
&(
:(
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5(
,2[
5%
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'RXW1 'RXW1
5RZ$GGUHVV
W$5
W:%
W5&
W2+
W&+=
%XV\
Figure 11: Read1 Operation intercepted by CE
Rev 0.5 / Feb. 2006 30
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
&/(
$/(
&(
5(
5%
,2[
:(
W&/5
K
&ROXPQ$GGUHVV 5RZ$GGUHVV
%XV\
K K (K
'RXW1 'RXW0
'RXW1 'RXW0&RO$GG 5RZ$GG 5RZ$GG 5RZ$GG&RO$GG
&ROXPQ$GGUHVV
&RO$GG &RO$GG
W5 W5&
W:%
W$5
W55
W:+5
W5($
Figure 12 : Random Data output
Rev 0.5 / Feb. 2006 31
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Figure 13: Page Program Operation
&/(
$/(
&(
5(
5%
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:(
W:&
K
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6HULDO'DWD
,QSXW&RPPDQG &ROXPQ$GGUHVV 5RZ$GGUHVV 5HDG6WDWXV
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XSWRP%\WH
6HULDO,QSXW
&RO$GG 5RZ$GG 5RZ$GG 5RZ$GG
'LQ
1'LQ
0K K ,2R
W:& W:&
W$'/ W:% W352*
Rev 0.5 / Feb. 2006 32
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
&/(
$
/(
&(
5(
5%
,2[
1RWHVW$'/LVWKHWLPHIURPWKH:(ULVLQJHGJHRIILQDODGGUHVVF\FOHWRWKH:(ULVLQJHGJHRIILUVWGDWDF\FOH
:(
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.
K K K
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W:& W:&
W:%
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6HULDO'DWD
,QSXW&RPPDQG 5DQGRP'DWD
,QSXW&RPPDQG
&ROXPQ$GGUHVV &ROXPQ$GGUHVV5RZ$GGUHVV 6HULDO,QSXW 6HULDO,QSXW 3URJUDP
&RPPDQG
5HDG6WDWXV
&RPPDQG
W$'/ W$'/
Figure 14 : Random Data In
Rev 0.5 / Feb. 2006 33
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
&/(
$/(
&(
5(
5%
1RWHVW$'/LVWKHWLPHIURPWKH:(ULVLQJHGJHRIILQDODGGUHVVF\FOHWRWKH:(ULVLQJHGJHRIILUVWGDWDF\FOH
,2[
:(
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W352*
W5
K
&ROXPQ$GGUHVV 5RZ$GGUHVV &ROXPQ$GGUHVV
%XV\ %XV\
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,QSXW&RPPDQG ,2 6XFFHVVIXO3URJUDP
,2 (UURULQ3URJUDP
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K K K
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'DWD1'DWD
&RO
$GG
&RO
$GG
5RZ
$GG
5RZ
$GG
5RZ
$GG &RO
$GG
&RO
$GG
5RZ
$GG
5RZ
$GG
5RZ
$GG
W:&
W$'/
5HDG6WDWXV
&RPPDQG
Figure 15 : Copy Back Program
Rev 0.5 / Feb. 2006 34
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
&/(
$/(
&(
5(
5%
,2[
:(
5%
,2[
([&DFKH3URJUDP
W:&
K K ,2
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/DVW3DJH,QSXW3URJUDP
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W&%6<PD[XV
W&%6<
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W&%6< W&%6< W352*
6HULDO'DWD
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&RPPDQG
'XPP\
K K
$GGUHVV
'DWD,QSXW $GGUHVV
'DWD,QSXW $GGUHVV
'DWD,QSXW $GGUHVV
'DWD,QSXW
K K K KK K K
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'LQ
1'LQ
0'LQ
1'LQ
0
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$GG
K &RO
$GG
5RZ
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5RZ
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5RZ
$GG
W:% W352*
W:% W&%6<
&RO
$GG &RO
$GG
5RZ
$GG
5RZ
$GG
5RZ
$GG
Figure 16 : Cache Program
Rev 0.5 / Feb. 2006 35
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
W:&
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Figure 17: Block Erase Operation (Erase One Block)
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Figure 18: Read ID Operation
Rev 0.5 / Feb. 2006 36
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
'K
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Figure 19: start address at page start :after 1st latency uninterrupted data flow
Rev 0.5 / Feb. 2006 37
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
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Figure 20: exit from cache read in 5us when device internally is reading
Rev 0.5 / Feb. 2006 38
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
System Interface Using CE don’t care
To simplify system interface, CE may be deasserted during data loading or sequential data-reading as shown below.
So, it is possible to conn ect NAND Flash t o a microporc essor. The only function that was removed from standard NAND
Flash to make CE don’t care read operation was disabling of the automatic sequential read function.
Figure 21: Program Operation with CE don’t-care.
Figure 22: Read Operation with CE don’t-care.
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Rev 0.5 / Feb. 2006 39
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
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Figure 23: Lock Command
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Figure 24: Unlock Command Sequence
Rev 0.5 / Feb. 2006 40
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
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Figure 25: Lock Tight Command
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Figure 26: Lock Status Read Timing
Rev 0.5 / Feb. 2006 41
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
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Figure 27: Automatic Read at Power On
Rev 0.5 / Feb. 2006 42
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
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Figure 29: Power On/Off Timing
Rev 0.5 / Feb. 2006 43
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
5SYDOXHJXLGHQFH
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Figure 30: Ready/Busy Pin electrical specifications
Rev 0.5 / Feb. 2006 44
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
/RFN
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Figure 31: Lock/Unlock FSM Flow Cart
Figure 32: page programming within a block
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Rev 0.5 / Feb. 2006 45
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Bad Block Management
Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the
blocks are va lid. A Bad Block does not affect the perf ormance of valid blocks because it is isolated from the bit line and
common source line by a select transi stor. The devices are supplied with all the locations inside valid blocks
erased(FFh). The Bad Block Information is written prior to shipping. Any block where the 1st Byte in the spare area of
the 1st or 2nd page(if the 1st page is Bad) does not contain FFh is a Bad Block. The Bad Block Information must be
read before any erase is attempted as the Bad Block Information may be erased. For the system to be able to recog-
nize the Bad Blocks based on the original information it is recommended to create a Bad Block table following the flow-
chart shown in Figure 33. The 1st block, which is placed on 00h block address is guaranteed to be a valid block.
Bad Replacement
Over the lifetime of the device additional Bad Blocks may dev elop. In this case the block has to be replaced by copying
the data to a v alid block. These additional Bad Blocks ca n be identified as attempts to progr am or er ase them will give
errors in the Status Register.
As the failure of a page progr am operation doe s not affect the data in other pages in the same block, the block can be
replaced by re-programming the current data and copying the rest of the replaced block to an available valid block.
The Copy Back Program command can be used to copy the data to a valid block.
See the “Copy Back Program” section for more details.
Refer to Table 19 for the recommended procedure to follow if an error occurs during an operation.
Operation Recommended Procedure
Erase Block Replacement
Program Block Replacement or ECC
Read ECC
Table 19: Block Failure
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Rev 0.5 / Feb. 2006 46
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Write Protect Operation
The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations
are enabled and disabled as follows (Figure 34~37)
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Figure 34: Enable Programming
Figure 35: Disable Programming
Rev 0.5 / Feb. 2006 47
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
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Figure 36: Enable Erasing
Figure 37: Disable Erasing
Rev 0.5 / Feb. 2006 48
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
5. APPENDIX : Extra Features
5.1 Automatic Page0 Read after Power Up
The timing diagram related to this operation is shown in Fig. 27
Due to this functionality the CPU can directly download the boot loader from the first page of the NAND flash, storing
it inside the internal cache and starting the execution after the download completed.
5.2 Addressing for program operation
Within a block, the pages must be progr ammed consecutively from LSB (least significant bit) page of the block to MSB
(most significant bit) page of the block. Random address programming is prohibited. See Fig. 32.
Rev 0.5 / Feb. 2006 49
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Table 20: 48pin-TSOP1, 12 x 20mm, Package Mechanical Data
Symbol millimeters
Min Typ Max
A1.200
A1 0.050 0.150
A2 0.980 1.030
B 0.170 0.250
C 0.100 0.200
CP 0.100
D 11.910 12.000 12.120
E 19.900 20.000 20.100
E1 18.300 18.400 18.500
e 0.500
L 0.500 0.680
alpha 0 5
Figure 38. 48pin-TSOP1, 12 x 20mm, Package Outline
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Rev 0.5 / Feb. 2006 50
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Symbol millimeters
Min Typ Max
A 16.90 17.00 17.10
A1 13.00
A2 12.00
B 11.90 12.00 12.10
B1 10.00
B2 6.00
C1.00
C1 1.50
C2 2.00
D1.00
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Figure 39. 52-ULGA, 12 x 17mm, Package Outline
(Top view through package)
Table 21: 52-ULGA, 12 x 17mm, Package Mechanical Data
Rev 0.5 / Feb. 2006 51
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
MARKING INFORMATION - TSOP1 / ULGA
Packag M arking Exam ple
TSOP1
/
ULGA
K O R
H Y 2 7 x F x x 2 G 2 M
x x x x Y W W x x
- hynix
- K O R
- HY27xFxx2G2M xxxx
HY : HYNIX
2 7 : NAND Flash
x : Pow er Supply
F : Classification
x x : Bit Organization
2 G: Density
2 : Mode
M: Version
x : Package Type
x : Package M aterial
x : Operating Tem perature
x : Bad Block
- Y : Year (ex: 5= year 2005, 06= year 2006)
- ww: W ork W eek (ex: 12= w ork w eek 12)
- xx: Process Code
Note
- C apital Le tter
- S ma ll L e tte r
: H yn ix Symb ol
: Orig in Co u ntry
: U (2 .7V ~ 3 .6V )
: S in g le L e v e l C e ll+Qu a d r u p le D ie +L a rge B lo c k
: 08(x8), 16(x16)
: 2 G bit
: 1nCE & 1R/nB; Sequential Row Read Disable
: 1 st Gen era tio n
: T(48-TSO P1), U(52-ULGA)
: Blank(N ormal), P(Lead Free)
: C (0℃~70℃), E(-25℃~85℃)
M(-3 0℃~85℃), I(-40℃~85℃)
: B(Included Bad Block), S(1~5 Bad Block),
P(All Good Block)
: Fixe d Ite m
: N o n-fixe d Item
: P art N umbe r
Rev 0.5 / Feb. 2006 52
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Application Note
1. Power-on/off Sequence
After power is on, the device starts an internal ci rcuit initialization when the power supply voltage reaches a specific
level. The device shows its internal initialization status with the Ready/Busy signal if initializati on i s on pro gr ess. Whil e
the device is initializing, the device sets internal registeries to default value and generates internal biases to operate
circuits. Typically the initializing time of 20us is required.
Po wer-off or power f ailure befo re write/erase op eration is complete will cause a loss of data. The WP signal helps user
to protect not only the data integrity but also device circuitry from being damaged at power-on/off by keeping WP at
VIL during power-on/off.
For the device to operate stably, it is highly recommended to operate the device as shown Fig.40.
Figure 40: Power-on/off sequence
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Rev 0.5 / Feb. 2006 53
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
2. Automatic sleep mode for low power consumption
The device provides the automatic sleep function for lo w power consumption.
The device enters the automatic sleep mode by keeping CE at VIH level for 10us without any additional command
input, and exits simply by lowering CE to VIL level.
Typically, consecutive opera tio n is ex ecutable right after deactivating the automatic sleep mode, while tCS of 40ns is
required prior to following operation as shown in Fig.41.
Figure 41: tCS setting when deactivating the auto sleep mode
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