LTC4317
1
4317fa
For more information www.linear.com/LTC4317
Typical applicaTion
FeaTures DescripTion
Dual I2C/SMBus
Address Translator
The LT C
®
4317 enables the hardwired address of one or more
I2C or SMBus slave device to be translated to a different ad-
dress. This allows slaves with the same hardwired address to
coexist on the same bus. Only discrete resistors are needed
to select the new address and no software programming is
required. Up to 127 different address translations are available.
The LTC4317 incorporates a pass-through mode which dis-
ables the address translation and allows general call address-
ing by the master. The LTC4317 is designed to automatically
recover from abnormal bus conditions like bus stuck low or
premature STOP bits.
The LTC4317 has two output channels for two different sets
of slaves. The input channels are tied together to a com-
mon set of pins to reduce the pin count and package size.
PART NUMBER
NUMBER OF INPUT
CHANNELS
NUMBER OF OUTPUT
CHANNELS
LTC4316 1 1
LTC4317 1 2
LTC4318 2 2
applicaTions
n Allows Multiple Slaves with the Same Address to
Coexist on the Same Bus
n Resistor Configurable Address Translation
n No Software Programming Required
n Compatible with SMBus, I2C and I2C Fast Mode
n Pass-Through Mode Allows General Call Addressing
n ±4kV HBM ESD Ruggedness
n Level Translation for 2.5V, 3.3V and 5V Buses
n Stuck Bus Timeout
n Prevents SDA and SCL Corruption During Live Board
Insertion and Removal
n Support Bus Hot Swap
n 16-Lead DFN 5mm × 3mm Package
n I2C, SMBus Address Expansion
n Address Translation
n Servers
n Telecom L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 6356140, 6650174, 7032051, 7478286. Patent pending.
4317 TA01b
TRANSLATION
BYTE
SDAOUT1
SCLIN
SDAIN
ADDRESS BITSSTART
a6 a5 a4 a3 a2 a1 a0
0 1 1 0 1 0 0 = 0x34
0 0 0 0 0 1 0 = 0x02
0
0
0
0 1 1 0 1 1 0 = 0x36
R/W
BIT
ACK
BIT
SCL
SDA
4317 TA01a
3.3V
845k 61.9k
3.3V
3.3V
MASTER
SCLOUT1
SDAOUT1
READY1
SCLIN
SDAIN
ENABLE1
SENDS
ADDRESS 0x34
SCL
SDA
5V
SLAVE# 1
ADDRESS
0x36
RECEIVES
ADDRESS 0x36
TRANSLATES
BY 0x04
TRANSLATES
BY 0x02
XORL1XORL2
LTC4317
VCC
GND
ENABLE2 READY2
93.1k
SCLOUT2
SDAOUT2
XORH2
XORH1
SCL
SDA
5V
RECEIVES
ADDRESS 0x30
SLAVE# 2
ADDRESS
0x36
LTC4317
2
4317fa
For more information www.linear.com/LTC4317
absoluTe MaxiMuM raTings
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4317CDHC#PBF LTC4317CDHC#TRPBF 4317 16-Lead (5mm × 3mm) Plastic DFN 0°C to 70°C
LTC4317IDHC#PBF LTC4317IDHC#TRPBF 4317 16-Lead (5mm × 3mm) Plastic DFN –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
pin conFiguraTion
Input Supply Voltage VCC ............................. –0.3V to 6V
Input Voltages
ENABLEn ...................................................... –0.3V to 6V
XORLn, XORHn ................................–0.3V to VCC + 0.3V
Output Voltages
READYn ....................................................... –0.3V to 6V
Output Currents
READYn, SDAOUTn ................................................50mA
Input/Output Voltages
SCLIN, SCLOUTn, SDAIN, SDAOUTn ............ –0.3V to 6V
Operating Temperature Range
LTC4317C ................................................ 0°C to 70°C
LTC4317I .............................................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
(Notes 1, 2)
16
15
14
13
12
11
10
9
17
GND
1
2
3
4
5
6
7
8
SCLOUT2
SCLIN
SCLOUT1
SDAOUT1
SDAIN
SDAOUT2
READY1
READY2
GND
ENABLE2
XORH2
XORL2
XORH1
XORL1
VCC
ENABLE1
TOP VIEW
DHC PACKAGE
16-LEAD (5mm × 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 42°C/W
EXPOSED PAD (PIN 17) IS GND, PCB CONNECTION OPTIONAL
LTC4317
3
4317fa
For more information www.linear.com/LTC4317
elecTrical characTerisTics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V, unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Supply
VCC Input Supply Range l2.25 5.5 V
ICC Input Supply Current ENABLE = 3.3V, SCLIN = SDAIN = 0V l0.8 2 mA
ENABLE = 0V, SCLIN = SDAIN = 0V l350 800 µA
VCC(UVLO) VCC Supply Undervoltage Lockout VCC Rising l1.9 2.1 2.2 V
VCC(HYST) VCC Supply Undervoltage Lockout Hysteresis 100 mV
ENABLE and READY
VENABLE(TH) ENABLE Threshold Voltage Enable Rising l1 1.4 1.8 V
VENABLE(HYST) ENABLE Hysteresis 50 mV
IENABLE(LEAK) ENABLE Input Current l±1 µA
VREADY(OL) READY Output Low Voltage I = 3mA l0.4 V
IREADY(OH) READY Off Leakage Current VCC = VREADY = 5.5V l±5 µA
SCLIN, SDAIN, SCLOUT, SDAOUT
VSCL,SDA(TH) Threshold Voltage SDA, SCL Pins Rising l1.5 1.8 2.0 V
VSCL,SDA(HYST) Hysteresis 50 mV
ISCL,SDA(LEAK) Leakage Current SDA, SCL Pins = 5.5V, 0V, VCC = 5.5V, 0V l±10 µA
ISCL,SDA(LEAK-INOUT) Input to Output Leakage Current SDAIN, SCLIN Pins = 5.5V, VCC = 5.5V,
SDAOUT, SCLOUT Pins = 4.5V
l±10 µA
CSCL,SDA Pin Capacitance Note 3 l10 pF
VSCL,SDA(PRE) Precharge Voltage l0.8 1 1.2 V
VSDAOUT(OL) SDAOUT Output Low Voltage I = 4mA l0.4 V
RDS(ON) Pass Switch On Resistance VCC = 2.25V, SCLIN = SDAIN = 0.4V
VCC = 3.3V, SCLIN = SDAIN = 0.4V
VCC = 5V, SCLIN = SDAIN = 0.4V
l
l
l
3
2.2
1.8
12
8
6
Ω
Ω
Ω
XORH, XORL
IXORH/XORL XORH and XORL Input Current l±100 nA
I2C Interface Timing
fSCL(MAX) Maximum SCLIN Clock Frequency Note 3 l400 kHz
tPDHL(SDAOUTn) SDAOUT Fall Delay C = 100pF, RPULLUP = 10k l170 300 ns
tf(SDAOUTn) SDAOUT Fall Time C = 100pF, RPULLUP = 10k l20 60 300 ns
tTIMEOUT Stuck Bus Timeout SCLIN Held Low or High l25 30 35 ms
tIDLE Bus Idle Time l80 120 160 µs
tGLITCH SCLIN and SDAIN Glitch Filter l50 100 ns
Note 2: All currents into pins are positive and all voltages are referenced to
GND unless otherwise indicated.
Note 3: Guaranteed by design and not tested.
LTC4317
4
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For more information www.linear.com/LTC4317
Typical perForMance characTerisTics
Pass Switch On Resistance vs
Temperature
READY Output Low
Voltage vs Current
SDAOUT Fall Delay vs
Temperature
Supply Current vs Temperature
Standby Supply Current vs
Temperature Pass Switch On Resistance vs VCC
TA = 25°C, VCC = 3.3V unless otherwise noted.
TiMing DiagraM
4317 EC
SDAOUT
SDAIN 50%
tPDHL(SDAOUT)
t
f(SDAOUT)
70%
30%
50%
TEMPERATURE (°C)
–50
I
CC
(mA)
1.0
0.9
0.8
0.7
0.6 0 50–25 25 75
4317 G01
100
ENABLE = VCC
VCC = 3.3V
VCC = 5V
VCC = 2.25V
TEMPERATURE (°C)
–50
I
CC
(μA)
800
700
500
300
600
400
200
100
00 50–25 25 75
4317 G02
100
ENABLE = 0V
VCC (V)
2.0
R
DS(ON)
(Ω)
6
5
3
1
4
2
03.0 4.02.5 3.5 4.5
4317 G03
5.0
TA = –40°C
TA = 85°C
TA = 25°C
SDAIN = SCLIN = 0.4V
TEMPERATURE (°C)
–50
R
DS(ON)
(Ω)
6
5
3
1
4
2
00 50–25 25 75
4317 G04
100
VCC = 5V
VCC = 2.25V
VCC = 3.3V
SDAIN = SCLIN = 0.4V
IREADY (mA)
0
V
READY(OL)
(mV)
100
80
40
60
20
02 64 8
4317 G05
10
TA = –40°C
TA = 85°C
VCC = 3.3V
TA = 25°C
TEMPERATURE (°C)
–50
t
PDHL(SDAOUT)
(ns)
240
200
220
160
180
140
100
120
0 50–25 25 75
4317 G06
100
VCC = 3.3V
C = 100pF
LTC4317
5
4317fa
For more information www.linear.com/LTC4317
Typical perForMance characTerisTics
SDAOUT Fall Delay vs Bus
Capacitance
SDAOUT Fall Time vs
Temperature
SDAOUT Fall Time vs Bus
Capacitance
TA = 25°C, VCC = 3.3V unless otherwise noted.
pin FuncTions
XORL1/XORL2: Translator XOR Lower Nibble Configura-
tion Input. The DC voltage at this pin configures the lower
4-bit nibble of the address translation byte. Tie the pin to
an external resistive divider connected between VCC and
GND to set the desired DC voltage.
XORH1/XORH2: Translator XOR Upper Nibble Configura-
tion Input. The DC voltage at this pin configures the upper
3-bit nibble of the address translation byte. Tie the pin to
an external resistive divider connected between VCC and
GND to set the desired DC voltage. Connect this pin to VCC
to activate pass-through mode. See Application Informa-
tion section for more details.
ENABLE1/ENABLE2: Enable Input. If ENABLE pin is low,
the address translation is disabled, SDAIN is disconnected
from SDAOUT, and SCLIN is disconnected from SCLOUT.
A low to high transition on ENABLE restarts the configura-
tion of the address translation byte and also enables the
address translation. Connect to VCC if unused.
Exposed Pad: Exposed pad may be left open or connected
to device GND.
GND: Device Ground.
READY1/READY2: Ready Status Output. This is an open
drain output to indicate that the device is ready for address
translation. The pin releases high when the LTC4317 has
completed configuration of the address translation byte,
SDAIN is connected to SDAOUT and SCLIN is connected to
SCLOUT. Connect a pull-up resistor, typically 10k, from this pin
to the bus pull-up supply. Leave open or tie to GND if unused.
SCLIN: Input Bus Clock Input and Output. Connect this
pin to the SCL line on the master side. An external pull-up
resistor or current source is required.
SCLOUT1/SCLOUT2: Output Bus Clock Input and Output.
Connect this pin to the SCL line on the slave side. An external
pull-up resistor or current source is required. Connect to
VCC through a pull-up resistor if unused.
SDAIN: Input Bus Data Input and Output. Connect this pin
to the SDA line on the master side. An external pull-up
resistor or current source is required.
SDAOUT1/SDAOUT2: Output Bus Data Input and Output.
Connect this pin to the SDA line on the slave side. An
external pull-up resistor or current source is required.
Connect to VCC through a pull-up resistor if unused.
VCC: Power Supply Input (2.25V to 5.5V). If the supply
voltages for the input and output buses are different, con-
nect this pin to the lower supply. If the input and output
supplies have the same nominal value and with tolerance
less than or equal to ±10%, connect VCC to either supply.
Bypass with at least 0.1µF to GND.
CBUS (pF)
0
t
PDHL(SDAOUT)
(ns)
300
250
275
150
200
175
225
125
100 200 600400 800
4317 G07
1000
VCC = 3.3V
VCC = 5V
VCC = 2.25V
TEMPERATURE (°C)
–50
t
f(SDAOUT)
(ns)
120
100
60
80
40
20 0 50–25 25 75
4317 G08
100
C = 100pF
VCC = 5V
VCC = 2.25V
VCC = 3.3V
CBUS (pF)
0
t
f(SDAOUT)
(ns)
120
100
60
80
40
20 200 600400 800
4317 G09
1000
VCC = 5V
VCC = 2.25V
VCC = 3.3V
LTC4317
6
4317fa
For more information www.linear.com/LTC4317
block DiagraM
I2C Hot
Swap
LOGIC
7-BIT
ADDRESS
TRANSLATION
BYTE
GND
CONTROL
LOGIC
VCC/2
CMP6 CMP5
PRECHARGE 1.4V
N4
1V
200k
PRECHARGE
1V
READY1
SDAOUT1
SCLOUT1
XORL1
XORH1
SDAIN
SCLIN
SDAOUT2
SCLOUT2
VCC
–
+
N3
–
+
CMP3
1.8V
–
+
1.8V
CMP1
–
+
I2C Hot
Swap
LOGIC
CMP4
1.8V
–
+
GLITCH
FILTER
1.8V
CMP2
–
+
GLITCH
FILTER
XOR
N1
N2
200k
PRECHARGE PRECHARGEPRECHARGE
1V
200k
1V
200k
ENABLE1
READY2
XORL2
XORH2
ENABLE2
LTC4317
7
4317fa
For more information www.linear.com/LTC4317
operaTion
Figure 1. Basic Functions of the LTC4317
4317 F01
VCC1
MASTER
SCLOUT
SDAOUT
SCLIN
SDAIN
VCC2
SLAVE
#1
LTC4317
SLAVE
#2
7-BIT ADDRESS
TRANSLATION
BYTE SHIFT REGISTER
0000010 ENABLE
ADDRESS
TRANSLATION
N3
1.8V
CMP2
–
+
XOR
N1
N2
In most conditions, N1 and N2 stay on so that the input
and output buses are connected.
Translation starts when the master issues a START bit
(SDAIN goes low while SCLIN is high). The LTC4317
turns off N2 to disconnect SDAIN from SDAOUT. As the
master sends the address byte, the LTC4317 translates
the incoming address at the SDAIN pin to a new address
at the SDAOUT pin by XORing each incoming bit with
a user-configurable translation byte, one bit at a time.
N3 turns on and off to send out the new address to the
SDAOUTpin. Once all 7 bits of the address are processed,
the LTC4317 turns on N2 again to reconnect SDAIN to
SDAOUT. The master then transmits the R/W bit directly
to the slave. If the new, translated address on SDAOUT
matches the slave’s address, the slave pulls SDAOUT low
to acknowledge (ACK bit). N2 remains on and the rest of
the data bytes are transmitted unmodified between the
master and slave. The address translation process restarts
when the master issues a new START bit.
The LTC4317 is an I2C/SMBus address translator. It bridges
two segments of an I2C bus, reading incoming addresses
on the master side and retransmitting them to the slave
side with the 7-bit I2C addresses translated in real time.
This allows multiple I2C devices with the same address
to be connected to the same bus without interference.
The translated addresses are configured with external
resistors, and no extra software is required. An ENABLE
pin allows bus segments to be enabled and disabled, and
the LTC4317 allows hot swapping isolated bus segments
together.
Figure 1 shows an I2C master connected to the input bus
of the LTC4317 (SCLIN and SDAIN). The slave devices
requiring address translation are connected to the output
bus of the LTC4317 (SCLOUT and SDAOUT). Any other
slave devices that do not require address translation are
placed together with the master on the input bus of the
LTC4317. Two switches (N1 and N2) inside the LTC4317
connect the input bus to the output bus. N1 connects
SCLIN to SCLOUT while N2 connects SDAIN to SDAOUT.
LTC4317
8
4317fa
For more information www.linear.com/LTC4317
operaTion
Table 1.
DESCRIPTION
BINARY ADDRESS 7-BIT HEX ADDRESS
WITHOUT R/W
8-BIT HEX ADDRESS
WITH R/W = 0
a6 a5 a4 a3 a2 a1 a0 R/W
Input Address from SDAIN 0 0 1 1 0 1 0 0 0x1A 0x34
Translation Byte 0 0 0 0 0 0 1 0 0x01 0x02
Output Address to SDAOUT 0 0 1 1 0 1 1 0 0x1B 0x36
Figure 2. Basic Address Translation Waveforms
TRANSLATION
BYTE
SDAOUT
SCLIN
SDAIN
ADDRESS BITSSTART
a6 a5 a4 a3 a2 a1 a0
0110100
0000010
0
0
0
0 110110
4317 F02
N2 GATE N2 ON N2 ON N2 OFF
R/W
BIT
ACK
BIT
= 0x34
= 0x02
= 0x36
Figure 2 shows typical waveforms for the circuit on the
front page. In this example, the master transmits address
0x34 while the slave is configured to respond to address
0x36. The resistive dividers at the XORL and XORH pins are
configured to generate an address translation byte of 0x02.
Note that in this example, the 8-bit hexadecimal address
format (with R/W = 0) is used. 7-bit addresses are also
commonly found in I2C device documentation. Make sure
to use the correct format when calculating the address
translation byte. Table 1 shows examples of both formats.
LTC4317
9
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For more information www.linear.com/LTC4317
Figure 4. Two Slaves Sharing One Channel of LTC4317
Figure 3. Two Independent Address Translation
operaTion
SCL
SDA
4317 F03
MASTER
SCLOUT1
SDAOUT1
SCLIN
SDAIN
SCL
SDA
SLAVE
#1
LTC4317
SCLOUT2
SDAOUT2
SCL
SDA
SLAVE
#3
SCL
SDA
SLAVE
#2
SLAVE #1
INPUT ADDRESS
0x32
TRANSLATION BYTE
0x06
HARDWIRED ADDRESS
0x34
SLAVE #3
INPUT ADDRESS 0x36
TRANSLATION BYTE 0x02
HARDWIRED ADDRESS
0x34
HARDWIRED ADDRESS
0x34
00110010
00000110
00110100
00110110
00000010
00110100
SCL
SDA
4317 F04
MASTER
SCL
SDA
SLAVE
#2
SCLOUT
SDAOUT
SCLIN
SDAIN
SCL
SDA
SLAVE
#1
LTC4317
SCL
SDA
SLAVE
#3
HARDWIRED ADDRESS
0x34
TRANSLATION BYTE
0x02
SLAVE #1
INPUT ADDRESS
0x36
SLAVE #3
INPUT ADDRESS
0x32
HARDWIRED ADDRESS
0x34
HARDWIRED ADDRESS
0x30
00110110
00000010
00110100
00110010
00000010
00110000
System Configurations
There are several ways that individual slaves or banks of
slaves can be connected to an LTC4317. In Figure 3, each
slave is paired with one channel of the LTC4317. This
configuration allows for maximum flexibility in allocating
the bus addresses. Both read and write operations and all
protocols supported by the LTC4317 are allowed. Figure4
shows two slaves with different hardwired addresses
translated to two different addresses using one channel of
the LTC4317 and a common translation byte. A program
is available to help the user visualize an I2C bus with the
LTC4317; this program can be found in the following link:
www.linear.com/TranslatorTool
Setting the Translation Byte
When the LTC4317 is first powered up or any time a rising
edge is detected on the ENABLE pin, the LTC4317 reads
the voltages at the XORH and XORL pins to determine the
7-bit translation byte. These voltages are referenced to
VCC so a resistive divider at each of these pins is the most
convenient way to set the voltages. The required transla-
tion byte can be determined by taking the bitwise XOR of
the slave’s original address and the desired input address.
The voltages at the XORH and XORL pins configure the
translation byte. The XORL voltage configures the lower4
translation bits (excluding the R/W bit), while the XORH
voltage configures the upper 3 translation bits. Tables 2
and 3 show the recommended resistive divider values. RLT
and RLB are the top and bottom resistors connected to
XORL, while RHT and RHB are the top and bottom resistors
connected to XORH (Figure 5). Use 1% tolerance resistors
for RLT , RLB, RHT and RHB.
Figure 5. Address Translation Byte Configuration Resistors
4317 F05
V
CC
RHT RLT
XORLXORH
LTC4317
VCC
RHB RLB
LTC4317
10
4317fa
For more information www.linear.com/LTC4317
operaTion
Table 2. Setting the Resistive Divider at XORL
LOWER
4-BIT OF
TRANSLATION
BYTE
VXORL/VCC
RECOMMENDED
RLT [kΩ]
RECOMMENDED
RLB [kΩ]a3 a2 a1 a0
0 0 0 0 ≤ 0.03125 Open Short
0 0 0 1 0.09375 ±0.015 976 102
0 0 1 0 0.15625 ±0.015 976 182
0 0 1 1 0.21875 ±0.015 1000 280
0 1 0 0 0.28125 ±0.015 1000 392
0 1 0 1 0.34375 ±0.015 1000 523
0 1 1 0 0.40625 ±0.015 1000 681
0 1 1 1 0.46875 ±0.015 1000 887
1 0 0 0 0.53125 ±0.015 887 1000
1 0 0 1 0.59375 ±0.015 681 1000
1 0 1 0 0.65625 ±0.015 523 1000
1 0 1 1 0.71875 ±0.015 392 1000
1 1 0 0 0.78125 ±0.015 280 1000
1 1 0 1 0.84375 ±0.015 182 976
1 1 1 0 0.90625 ±0.015 102 976
1 1 1 1 ≥ 0.96875 Short Open
Table 3. Setting the Resistive Divider at XORH
UPPER
3-BIT OF
TRANSLATION
BYTE
VXORH/VCC
RECOMMENDED
RHT [kΩ]
RECOMMENDED
RHB [kΩ]a6 a5 a4
0 0 0 ≤ 0.03125 Open Short
0 0 1 0.09375 ±0.015 976 102
0 1 0 0.15625 ±0.015 976 182
0 1 1 0.21875 ±0.015 1000 280
1 0 0 0.28125 ±0.015 1000 392
1 0 1 0.34375 ±0.015 1000 523
1 1 0 0.40625 ±0.015 1000 681
1 1 1 0.46875 ±0.015 1000 887
For example, if RLT = 976k, RLB = 102k, RHT = 1000k, and
RHB = 280k, the lower 4 translation bits are 0001b and
the upper 3 bits are 011b. The 8-bit hexadecimal address
translation byte is obtained by adding a 0 as the LSB,
which gives 0110 0010b or 0x62. If the configuration
voltages at XORL and XORH pins are the same, they can
be tied together and connected to a single resistive divider.
Alternatively, three resistors can be used to configure
the XORL and XORH pins (Figure 6). Use the following
procedure to calculate the value of the three resistors:
Figure 6. Address Translation Byte
Configuration Using Three Resistors
4317 F06
V
CC
RA1
XORH
LTC4317
VCC
XORL
RA3
RA2
First choose a total resistance value RTOTAL
RA3 = RTOTAL • (VXORH/VCC)
RA2 = (RTOTAL • VXORL/VCC) – RA3
RA1 = RTOTAL – RA3 – RA2
Use 1% tolerance resistors for RA1, RA2 and RA3.
Once the XORL and XORH pins are read, the LTC4317
turns on switches N1 and N2, connecting the input and
output, and the READY pin goes high to indicate that the
LTC4317 is ready to start address translation.
The address translation byte can be changed during
operation by changing the XORH and XORL voltages and
toggling the ENABLE pin (high-low-high). This triggers
the LTC4317 to re-read the XORL and XORH voltages.
Enable/UVLO
If the ENABLE pin is driven below VENABLE(TH) or if VCC
is below the UVLO threshold, the LTC4317 shuts down.
The internal shift register storing the address translation
byte is cleared, address translation is disabled, switches
N1, N2 and N3 are off, the READY pin is pulled low and
the quiescent current drops to 350µA.
LTC4317
11
4317fa
For more information www.linear.com/LTC4317
operaTion
Precharge and Hot Swap
When the LTC4317 is first powered on, switches N1 and
N2 are initially off. This allows a LTC4317 and its con-
nected slaves to be hot swapped onto an active I2C bus.
Internal precharge circuitry initially sets the bus lines to
1V through a 200k resistor, minimizing disturbance to an
active bus when the LTC4317 is connected. The LTC4317
keeps N1 and N2 off until ENABLE goes high, the XORL/
XORH pins are read, and both sides of the I2C bus are
idle (indicated either by a STOP bit or all bus pins high
for longer than 120µs). Once these conditions are met, N1
and N2 turn on, and the READY pin goes high to indicate
that the LTC4317 is ready to start address translation.
Pass-Through Mode
If the master wants to communicate with the slave us-
ing the general call address, it can temporarily disable
address translation by pulling XORH high. This disables
address translation and keeps N1 and N2 on regardless
of the activity on the buses. Any translation that may be in
progress is stopped immediately when XORH goes high.
Extra Transitions on SDAOUT
In an I2C/SMBus system, the master changes the state of
the SDA line when SCL is low. The LTC4317 also advances
the address translation byte shift register when the SCLIN
is low. The translation byte transitions occur approximately
100ns after the falling edge of SCLIN. If the SDAIN tran-
sitions sent by the master do not coincide exactly with
the LTC4317 address translation bit transitions, an extra
transition on SDAOUT may appear (Figure7). These extra
SDA transitions are like glitches similar to those occurring
during normal Acknowledge bit transitions and do not pose
problems in the system because devices on the bus latch
SDA data only when SCL is high.
Level Translation and Supply Voltage Matching
The LTC4317 can operate with different supply voltages
on the input and output bus, and it will level shift the
voltages on the SCLIN, SDAIN, SCLOUT, and SDAOUT
pins to match the supply voltage at each side. VCC must
be powered from the lower of the two supply voltages
for level shifting to operate correctly. For example, if the
input bus is powered by a 5V supply and the output bus
is powered by a 3.3V supply, the LTC4317 VCC pin must
be connected to the 3.3V supply as shown in Figure 8.
If the LTC4317 supply pin is connected to the higher bus
supply, current may flow through the switches N1 and
N2 to the bus with lower supply. If the voltage difference
Figure 7. Extra Transitions on SDAOUT While SCL Is Low
TRANSLATION
BYTE
SDAOUT
SCLIN
SDAIN
GLITCH
0101
0110
0011
4317 F07
N2 GATE N2 OFF
ADDRESS BITS
GLITCH
Figure 8. A 5V to 3.3V Level Translation Application
4317 F08
5V
MASTER
SCLOUT
SDAOUT
SCLIN
SDAIN
3.3V
SLAVE
#1
LTC4317
VCC
is less than 1V, this current is limited to less than 10µA.
This allows the input and output buses to be connected
to nominally identical supplies that may have up ±10%
tolerance, and the LTC4317 VCC pin can be connected to
either supply.
Extra START and STOP Bits
During normal operation, an I2C master should not issue
a START or STOP bit within a data byte. I2C slave behavior
when such a command is received can be unpredictable.
The LTC4317 will recover automatically when an unex-
pected START or STOP is received during the address byte;
however, depending on the state of the translating bits,
it may convert START bits to STOP bits and vice versa,
causing unexpected slave behavior.
LTC4317
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For more information www.linear.com/LTC4317
operaTion
If a START bit is received during the address byte when
the active translating bit is a "1", the slave device will see
a STOP bit. This will typically reset the slave and cause it
to miss the remainder of the transmission. If the START
bit is received while the active translating bit is a "0", the
START passes through the LTC4317 unchanged. The slave
will react in the same way it would if the LTC4317 was
not present, and will typically reset when the master next
issues a STOP bit. In both cases, the LTC4317 automati-
cally resets at the next STOP bit and the next message
will be transmitted normally.
If a STOP bit is received during the address byte, the
LTC4317 will abort the address translation and ensure that
a STOP bit is issued at SDAOUT to reset the slave. If the
active translating bit is a "0" when the STOP arrives, it is
not modified, and the slave will see the STOP and typically
reset. If the active translating bit is a "1" when the STOP
arrives, the slave device will see a START bit. This might
leave the slave in an indeterminate state, so the LTC4317
briefly disconnects the slave from the master, adds a short
delay, and then generates a STOP bit at the SDAOUT pin
(Figure 9). It then reconnects the busses and waits for a
START bit to begin the next transmission. Again, in both
cases, the LTC4317 automatically resets and the next
message will be transmitted normally.
Stuck Bus Timeout
During the address translation, if SCLIN stays low or high
for more than 30ms without any transitions, the LTC4317
will abort the address translation and reconnect SDAIN
to SDAOUT. It will then wait for a START bit to start a new
address translation. This prevents any bus stuck low/
high conditions from permanently disconnecting SDAIN
fromSDAOUT.
Supported Protocols
The LTC4317 is designed to support most I2C and SMBus
message protocols. The only exceptions are protocols that
use pre-assigned addresses on the slave side of the bus.
Supported I2C and SMBus Protocols:
Send/Receive Byte
Write Byte/Word
Read Byte/Word
Process Call
Block Write/Read
Block Write-Block Read Process Call
Extended Read and Write Commands
General Call (I2C Only)
Start Byte (I2C Only)
PMBus (without PEC)
Unsupported I2C Protocols:
10-Bit Addressing
Device ID
Ultra Fast-Mode I2C Bus Protocol
Unsupported SMBus Protocols:
SMBus Host Notify
Address Resolution Protocol (ARP)
Parity Error Code (PEC)
Alert Response Address (ARA)
PMBus (with PEC)
Figure 9. Stop Bit within Address Byte when
Address Translation Byte Is 1
TRANSLATION
BYTE
SDAOUT
SCLIN
SDAIN
N2 GATE N2 OFF N2 OFF
N2 ON
ADDRESS BIT
BECOMES
STOP BIT
STOP
BIT
START
BIT
1
4317 F09
N1 GATE N1 ON N1 ON
N1
OFF
START
BIT
STOP
BIT START
BIT
LTC4317
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For more information www.linear.com/LTC4317
Typical applicaTions
Figure 10. LTC4317 with Address Translation Byte of 0x02 and 0x04
4317 F10
VCC 845k 61.9k
VCC
VCC
SCLOUT1
SDAOUT1
ENABLE1
SCL1
SDA1
GND
VCC
SCLIN
SDAIN
READY1
TO MASTER SCL
TO MASTER SDA
PLUG-IN
CARD 1
MOTHERBOARD
CONNECTOR 1
INPUT ADDRESS
0x32
TO SLAVE #1
HARDWIRED
ADDRESS
0x30
XORL1XORL2 XORH1XORH2
LTC4317
VCC
READY2
93.1k
VCC
10k
10k
10k
10k
10k10k
10k
SCLOUT2
SDAOUT2
ENABLE2
SCL2
SDA2
GND
VCC
PLUG-IN
CARD 2
MOTHERBOARD
CONNECTOR 2
INPUT ADDRESS
0x34
TO SLAVE #2
HARDWIRED
ADDRESS
0x30
VCC
10k
10k
10k
LTC4317
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For more information www.linear.com/LTC4317
package DescripTion
Please refer to http://www.linear.com/product/LTC4317#packaging for the most recent package drawings.
3.00 ±0.10
(2 SIDES)
5.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
R = 0.20
TYP
4.40 ±0.10
(2 SIDES)
18
169
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DHC16) DFN 1103
0.25 ±0.05
PIN 1
NOTCH
0.50 BSC
4.40 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.20 ±0.05
0.50 BSC
0.65 ±0.05
3.50 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
DHC Package
16-Lead Plastic DFN (5mm × 3mm)
(Reference LTC DWG # 05-08-1706 Rev Ø)
LTC4317
15
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For more information www.linear.com/LTC4317
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
A 10/15 Minor edits 4, 5
LTC4317
16
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For more information www.linear.com/LTC4317
© LINEAR TECHNOLOGY CORPORATION 2015
LT 1015, • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC4317
relaTeD parTs
Typical applicaTion
PART NUMBER DESCRIPTION COMMENTS
LTC4300A-1/
LTC4300A-2/
LTC4300A-3
Hot Swappable 2-Wire Bus Buffers LTC4300A-1: Bus Buffer with READY and ENABLE
LTC4300A-2: Dual Supply Buffer with ACC
LTC4300A-3: Dual Supply Buffer and ENABLE
LTC4302-1/
LTC4302-2
Addressable 2-Wire Bus Buffer Address Expansion, GPIO, Software Controlled
LTC4303/
LTC4304
Hot Swappable 2-Wire Bus Buffer with Stuck
Bus Recovery
Provides Automatic Clocking to Free Stuck I2C Busses
LTC4305/
LTC4306
2- or 4-Channel, 2-Wire Bus Multiplexers
with Capacitance Buffering
Two or Four Software Selectable Downstream Busses, Stuck Bus Disconnect, Rise Time
Accelerators, Fault Reporting, ±10kV HBM ESD
LTC4307 Low Offset, Hot Swappable 2-Wire Bus
Buffer with Stuck Bus Recovery
60mV Buffer Offset, 30ms Stuck Bus Disconnect and Recovery, Rise Time Accelerators,
±5kV HBM ESD
LTC4307-1 High Definition Multimedia Interface (HDMI)
Level Shifting 2-Wire Bus Buffer
60mV Buffer Offset, 3.3V to 5V Level Shifting, ±5kV HBM ESD
LTC4308 Low Voltage, Level Shifting Hot Swappable
2-Wire Bus Buffer with Stuck Bus Recovery
Bus Buffer with 1V Precharge, ENABLE and READY, 0.9V to 5.5V Level Translation, 30ms
Stuck Bus Disconnect and Recovery, Output Side Rise Time Accelerators, ±6kV HBM ESD
LTC4309 Low Offset Hot Swappable 2-Wire Bus
Buffer with Stuck Bus Recovery
60mV Buffer Offset, 30ms Stuck Bus Disconnect and Recovery, Rise Time Accelerators,
±5kV HBM ESD, 1.8V to 5.5V Level Translation
LTC4310-1/
LTC4310-2
Hot Swappable I2C Isolators Bidirectional I2C Communication Between Two Isolated Busses, LTC4310-1: 100kHz Bus,
LTC4310-2: 400kHz Bus
LTC4311 Hot Swappable I2C/SMBus Accelerator Rise Time Acceleration with ENABLE, ±8kV HBM ESD
LTC4312/
LTC4314
2- or 4-Channel, Hardware Selectable 2-Wire
Bus Multiplexers with Capacitance Buffering
Two or Four Pin Selectable Downstream Busses, VIL Up to 0.3V • VCC, Rise Time
Accelerators, 45ms Stuck Bus Disconnect and Recovery, ±4kV HBM ESD
LTC4313-1/
LTC4313-2/
LTC4313-3
High Noise Margin 2-Wire Bus Buffers VIL = 0.3V • VCC, Rise Time Accelerators, Stuck Bus Disconnect and Recovery, 1V
Precharge, ±4kV HBM ESD
Figure 11. Comparison Between LTC4316/LTC4317/LTC4318
4317 F11
SCLOUT
SDAOUT
READY
SCLOUT
SDAOUT
READY
VCC
SCLIN
SDAIN
XORH
XORL
ENABLE
GND
SCLIN
SDAIN
XORH
XORL
ENABLE
SINGLE
LTC4316
SCLOUT1
SDAOUT1
READY1
SCLOUT
SDAOUT
READY
VCC
SCLIN
SDAIN
XORH1
XORL1
ENABLE1
SCLIN
SDAIN
XORH
XORL
ENABLE
“Y” CONNECTED DUAL
LTC4317
SCLOUT2
SDAOUT2
READY2
SCLOUT
SDAOUT
READY
SCLIN
SDAIN
XORH
XORL
ENABLE
CHANNEL2
CHANNEL1
SCLOUT1
SDAOUT1
READY1
SCLOUT
SDAOUT
READY
VCC
SCLIN1
SDAIN1
XORH1
XORL1
ENABLE1
SCLIN
SDAIN
XORH
XORL
ENABLE
DUAL
LTC4318
SCLOUT2
SDAOUT2
READY2
SCLOUT
SDAOUT
READY
SCLIN2
SDAIN2
XORH2
XORL2
ENABLE2
GND
SCLIN
SDAIN
XORH
XORL
ENABLE
CHANNEL2
CHANNEL1
XORH2
XORL2
ENABLE2
GND