SD18U128 SD18U128L Ultra Low Power 128K x 8 CMOS SRAM Features Functional Description * Low-power consumption - Active: 20mA at 70ns - Stand-by: 5 A (CMOS input/output) 1 A CMOS input/output, L version The SD18U128 is a low power CMOS Static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW CE1, an active HIGH CE2, an active LOW OE, and Tri-state I/O's. This device has an automatic power-down mode feature when deselected. * Single +1.8to 2.2V Power Supply Writing to the device is accomplished by taking Chip Enable 1 (CE1) with Write Enable (WE) LOW, and Chip Enable 2 (CE2) HIGH. Reading from the device is performed by taking Chip Enable 1 (CE1) with Output Enable (OE) LOW while Write Enable (WE) and Chip Enable 2 (CE2) is HIGH. The I/O pins are placed in a high-impedance state when the device is deselected: the outputs are disabled during a write cycle. * Equal access and cycle time * 70/85/100/150 ns access time * Easy memory expansion with CE1, CE2 and OE inputs * 1.0V data retention mode * TTL compatible, Tri-state input/output * Automatic power-down when deselected 32-Pin TSOP1 / STSOP (See next page) Logic Block Diagram ROW DECODER ROW DECODER A1 A A21 AA32 AA43 AA54 A6 A5 A7 A6 A8 AA97 SENSEAMP AMP SENSE INPUT BUFFER BUFFER A A00 1024 1024 X X 1024 1024 I/O8 I/O 7 COLUMN DECODER A10 A11 A12 A13 A14 A15 A16 A10 A11 A12 A13 A14 A15 A16 1 32 OE A9 2 31 A10 A8 3 30 CE1 A13 4 29 I/O8 WE 5 28 I/O7 CE2 6 27 I/O6 A15 7 26 I/O5 Vcc 8 25 I/O4 NC 9 24 GND A16 10 23 I/O3 11 22 I/O2 A12 12 21 I/O1 I/O1 A7 13 20 A0 I/O 0 A6 14 19 A1 A5 15 18 A2 A4 16 17 A3 CONTROL CIRCUIT COLUMN DECODER A11 A14 A8 A9 The SD18U128L comes with a 1V data retention feature and Lower Standby Power. The SD18U128 is available in a 32-pin 8 x 20 mm TSOP1 / STSOP / 48-fpBGA packages. CONTROL CIRCUIT OE WE OE CE1 WE CE2 CE1 CE2 Revised 12/2/98 20410 TOWN CENTER LANE, STE 270 s CUPERTINO, CA 95014 s TEL (408) 255-1262 s FAX (408) 255-1359 SD18U128/SD18U128L Soft Device, Inc. SD28U128B 6 5 4 3 2 1 A B C D E F G H TOP VIEW Top View 48-CSP Ball-Grid Array package(shading indicates no ball) A B C D E F G H 1 A0 I/O4 I/O5 VSS VDD I/O6 I/O7 A9 2 A1 A2 NC NC NC NC OE A10 3 CE2 WE NC NC NC NC CE1 A11 4 A3 A4 A5 NC NC NC A16 A12 2 5 A6 A7 NC NC NC NC A15 A13 6 A8 I/O0 I/O1 VDD VSS I/O2 I/O3 A14 SD18U128/SD18U128L Absolute Maximum Ratings * Parameter Symbol Minimum Maximum Unit Voltage on Any Pin Relative to Gnd Vt -0.5 4.6 V Power Dissipation PT - 1.0 W Storage Temperature (Plastic) Tstg -55 +150 0C Temperature Under Bias Tbias -40 +85 0C * Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth Table CE1 CE2 WE OE Data Mode H X X X High-Z Standby X L X X High-Z Standby L H H L Data Out L H H H High-Z Active, Output Disable L H L X Data In Active, Write Active, Read * Key: X = Don't Care, L = Low, H = High Recommended Operating Conditions (TA = 00C to +700C / -400C to 850C**) Parameter Supply Voltage Input Voltage Symbol Min Typ Max Unit VCC 1.8 2.0 2.2 V Gnd 0.0 0.0 0.0 V VIH 1.6 - VCC + 0.2 V VIL -0.5* - 0.4 V * VIL min = -1.0V for pulse width less than tRC/2. ** For Industrial Temperature. 3 SD18U128/SD18U128L DC Operating Characteristics (Vcc = 1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to 850C) Parameter Sym Test Conditions -70 -85 -100 -150 Min Max Min Max Min Max Min Max Unit Input Leakage Current IILII Vcc = Max, Vin = Gnd to Vcc - 1 - 1 - 1 - 1 A Output Leakage Current IILOI CE1 = VIH or CE2 = VIL Vcc= Max, VOUT = Gnd to Vcc - 1 - 1 - 1 - 1 A Operating Power Supply Current ICC CE1 = VIL , CE2 = VIH VIN = VIH or VIL , IOUT = 0 mA - 3 - 3 - 3 - 3 mA ICC1 CE1 = VIL , CE2 = VIH IOUT = 0mA, Min Cycle, 100% Duty - 25 - 20 - 15 - 15 mA ICC2 CE1 = 0.2V, CE2 = Vcc - 0.2V IOUT = 0mA, - 3 - 3 - 3 - 3 mA Average Operating Current Cycle Time=1s, 100% Duty Standby Power Supply Current (TTL Level) ISB CE1 = VIH or CE2 = VIL - 0.5 - 0.5 - 0.5 - 0.5 mA Standby Power Supply Current (CMOS Level) ISB1 CE1 > Vcc - 0.2V or CE2 < 0.2V, f = 0 VIN < 0.2V or VIN > Vcc- 0.2V - 5 - 5 - 5 - 5 A - 1 - 1 - 1 - 1 A L Output Low Voltage VOL IOL = 2 mA - 0.4 - 0.4 - 0.4 - 0.4 V Output High Voltage VOH IOH = -1 mA 1.6 - 1.6 - 1.6 - 1.6 - V Capacitance (f = 1MHz, TA = 250C) Parameter* Symbol Test Condition Max Unit Input Capacitance Cin Vin = 0V 7 pF I/O Capacitance CI/O Vin = Vout = 0V 8 pF * This parameter is guaranteed by device characterization and is not production tested. AC Test Conditions Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level 0.4V to 1.6V 5ns TTL CL * 50% of input level (VIL + VIH)/2 Output Load Condition 70ns/85 ns CL = 30pf + 1TTL Load Load 100ns/150 ns CL = 100pf + 1TTL Load 4 Figure A. * Including Scope and Jig Capacitance SD18U128/SD18U128L Read Cycle (3,9) (Vcc = 1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to +850C) Parameter Symbol -70 -85 Unit -150 -100 Note Min Max Min Max Min Max Min Max Read Cycle Time tRC 70 - 85 - 100 - 150 - ns Address Access Time tAA - 70 - 85 - 100 - 150 ns Chip Enable Access Time tACE - 70 - 85 - 100 - 150 ns Output Enable Access Time tOE - 40 - 40 - 50 - 70 ns Output Hold from Address Change tOH 10 - 10 - 10 - 10 - ns Chip Enable to Output in Low-Z tCLZ 10 - 10 - 10 - 10 - ns 4,5 Chip Disable to Output in High-Z tCHZ - 30 - 35 - 40 - 50 ns 4,5 Output Enable to Output in Low-Z tOLZ 5 - 5 - 5 - 5 - ns 4,5 Output Disable to Output in High-Z tOHZ - 25 - 30 - 35 - 40 ns 4,5 Power-Up Time tPU 0 - 0 - 0 - 0 - ns 5 Power-Down Time tPD - 70 - 85 - 100 - 150 ns 5 Unit Note Write Cycle (3,11) (Vcc = 1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to +850C) Parameter Symbol -70 -85 -100 -150 Min Max Min Max Min Max Min Max Write Cycle Time tWC 70 - 85 - 100 - 150 - ns Chip Enable to Write End tCW 60 - 70 - 80 - 120 - ns Address Setup to Write End tAW 60 - 70 - 80 - 120 - ns Address Setup Time tAS 0 - 0 - 0 - 0 - ns Write Pulse Width tWP 50 - 60 - 70 - 100 - ns Write Recovering Time tWR 0 - 0 - 0 - 0 - ns Data Valid to Write End tDW 30 - 35 - 40 - 60 - ns Data Hold Time tDH 0 - 0 - 0 - 0 - ns Write Enable to Output in High-Z tWZ - 30 - 35 - 40 - 50 ns 4,5 Output Active from Write End tOW 5 - 5 - 5 - 5 - ns 4,5 5 SD18U128/SD18U128L Timing Waveform of Read Cycle 1 (3,6,7,9) (Address Controlled) tRC Address tAA tOH DOUT Data Valid Timing Waveform of Read Cycle 2 (5,6,8,9) (CE1 Controlled) tRC CE1 tOE OE tOHZ tCHZ tOLZ tACE DOUT Data Valid tPD tCLZ Supply Current ICC tPU 50% 50% ISB Timing Waveform of Read Cycle 3 (3,6,8,9) (CE2 Controlled) tRC CE2 tOE OE tOHZ tCHZ tOLZ tACE DOUT Data Valid tPD tCLZ Supply Current ICC tPU 50% 50% 6 ISB SD18U128/SD18U128L Timing Waveform of Write Cycle 1 (10,11) (WE Controlled) tAW tWC tWR Address tWP WE tAS tDW DIN tDH Data Valid tWZ tOW DOUT Timing Waveform of Write Cycle 2 (10,11) (CE1 Controlled) tWC tAW tWR Address tAS tCW CE1 tWP WE tWZ tDW DIN tDH Data Valid DOUT Timing Waveform of Write Cycle 3 (10,11) (CE2 Controlled) tWC tAW tWR Address tAS tCW CE2 tWP WE tWZ tDW DIN tDH Data Valid DOUT 7 SD18U128/SD18U128L Data Retention Characteristics (L Version Only)(1) Parameter Symbol Test Condition Min Max Unit 1.0 - V VCC for Data Retention VDR CE1 > VCC - 0.2V or Data Retention Current ICCDR CE2 < + 0.2V - 1 A Chip Deselect to Data Retention Time tCDR VIN > VCC - 0.2V or 0 - ns Operation Recovery Time(2) tR VIN < 0.2V tRC - ns Data Retention Waveform (L Version Only) (TA = 00C to +700C / -400C to +850C) Data Retention Mode VCC Vcc_typ VDR > 1.0V tCDR CE Vcc_typ tR V DR V IH V IH Notes 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. L-version includes this feature. This Parameter is samples and not 100% tested. For test conditions, see AC Test Condition, Figure A. This parameter is tested with CL = 5pF as shown in Figure B. Transition is measured + 500mV from steady-state voltage. This parameter is guaranteed, but is not tested. WE is HIGH for read cycle. CE1 and OE are LOW and CE2 is HIGH for read cycle. Address valid prior to or coincident with CE1 transition LOW or CE2 transition HIGH. All read cycle timings are referenced from the last valid address to the first transtion address. CE1 or WE must be HIGH or CE2 must be LOW during address transition. All write cycle timings are referenced from the last valid address to the first transition address. 8 SD18U128/SD18U128L Ordering Information Device Type* Speed SD18U128K-70 SD18U128K-85 SD18U128K-100 SD18U128K-150 70 ns 85 ns 100 ns 150 ns SD18U128LK-70 SD18U128LK-85 SD18U128LK-100 SD18U128LK-150 70 ns 85 ns 100 ns 150 ns SD18U128SK-70 SD18U128SK-85 SD18U128SK-100 SD18U128SK-150 70 ns 85 ns 100 ns 150 ns SD18U128LSK-70 SD18U128LSK-85 SD18U128LSK-100 SD18U128LSK-150 70 ns 85 ns 100 ns 150 ns SD18U128FG-70 SD18U128FG-85 SD18U128FG-100 SD18U128FG-150 70 ns 85 ns 100 ns 150 ns Package 8 x 20 mm 32-pin Plastic TSOP1 8 x 13.4 mm 32-pin Plastic STSOP * For Induatrial Temperature tested devices, an "I" designator will be added to the end of the Device number. Note: Soft Device reserves the right to make changes to its products and to this data sheet at any time, without notice, to improve design or performance. Soft Device makes no representation that circuits shown are free from patent infringments. Circuitry and other examples shown are meant only to indicate the performance and characteristics of our products. Soft Device products are not authorized for use as critical components in life support systems without written permission of the appropriate officer of Soft Device. 9