[AK4432] AK4432 108dB 192kHz 32bit 2-Channel Audio DAC 1. General Description The AK4432 is a 32-bit Stereo DAC which corresponds to digital audio systems. An internal circuit includes newly developed 32-bit Digital Filter achieving short group delay and high quality sound. The AK4432 has single end SCF outputs, increasing performance for systems with excessive clock jitter. The AK4432 is ideal for a wide range of applications that demands high sound quality including Home Theater and Car audio surround systems. It is housed in a 16-pin TSSOP package, saving more board space. 2. Features 1. 2ch 32bit DAC - 128 times Oversampling - 32-bit High Quality Sound Low Group Delay Digital Filter - Single Ended Output, Smoothing Filter - THD+N: 91dB - DR, S/N: 108dB - Channel Isolation Digital Volume (12dB-115dB, 0.5dB Step, Mute) - Soft Mute - De-emphasis Filter (32kHz, 44.1kHz, 48kHz) - I/F Format: MSB justified, LSB justified, I2S, TDM - Zero Detection 2. Sampling Frequency - Normal Speed Mode: 8kHz to 48kHz - Double Speed Mode: 64kHz to 96kHz - Quad Speed Mode: 128kHz to 192kHz 3. Master Clock 256fs, 384fs, 512fs or 768fs (Normal Speed Mode: fs=8kHz 48kHz) 256fs or 384fs (Double Speed Mode: fs=48kHz 96kHz) 128fs or 192fs (Quad Speed Mode: fs=96kHz 192kHz) 4. P Interface: 3-wire Serial (7MHz max)/ I2C bus (400kHz Mode, 1MHz Mode) 5. Power Supply - Analog: AVDD = 3.0 3.6V - Input/Output Buffer: LVDD = 3.0 3.6V - Integrated LDO for Digital Power Supply 6. Power Consumptions: 7.8mA (fs=48kHz) 7. Operational Temperature: Ta = - 40 105C 8. Package: 16-pin TSSOP (0.65mm pitch) 015002029-E-00 -1- 2015/02 [AK4432] 3. Table of Contents 1. 2. 3. 4. General Description .................................................................................................................. 1 Features ................................................................................................................................... 1 Table of Contents ..................................................................................................................... 2 Block Diagram .......................................................................................................................... 3 Block Diagram .................................................................................................................................... 3 Compatibility with AK4438, AK4452 and AK4458 .............................................................................. 4 5. Pin Configurations and Functions ............................................................................................. 5 Ordering Guide................................................................................................................................... 5 Pin Layout .......................................................................................................................................... 5 Pin Functions...................................................................................................................................... 6 Handling of Unused Pin ..................................................................................................................... 6 6. Absolute Maximum Ratings ...................................................................................................... 7 7. Recommended Operation Conditions ....................................................................................... 7 8. Analog Characteristics .............................................................................................................. 8 9. Filter Characteristics (fs=48kHz) ............................................................................................... 9 Sharp Roll-Off Filter (DASD bit = "0", DASL bit = "0") ....................................................................... 9 Slow Roll-Off Filter (DASD bit = "0", DASL bit = "1") ....................................................................... 10 Short Delay Sharp Roll-Off Filter (DASD bit = "1", DASL bit = "0") ................................................. 11 Short Delay Slow Roll-Off Filter (DASD bit = "1", DASL bit = "1") ................................................... 12 10. DC Characteristics .............................................................................................................. 13 11. Switching Characteristics .................................................................................................... 14 Timing Diagram ................................................................................................................................ 17 12. Functional Descriptions ....................................................................................................... 21 System Clock ................................................................................................................................... 21 Audio Interface Format..................................................................................................................... 23 Digital Volume Function ................................................................................................................... 30 Soft Mute Operation ......................................................................................................................... 31 Error Detection ................................................................................................................................. 32 System Reset ................................................................................................................................... 32 Power Down Function ...................................................................................................................... 33 Power Off and Reset Functions ....................................................................................................... 34 Clock Synchronization ..................................................................................................................... 35 Parallel Mode ................................................................................................................................... 36 Audio Interface ................................................................................................................................. 36 Soft Mute .......................................................................................................................................... 36 System Clock ................................................................................................................................... 36 Serial Control Interface .................................................................................................................... 37 Register Map .................................................................................................................................... 43 Register Definitions .......................................................................................................................... 44 13. Recommended External Circuits ......................................................................................... 46 14. Package .............................................................................................................................. 48 Outline Dimensions .......................................................................................................................... 48 Material & Lead Finish ..................................................................................................................... 48 Marking............................................................................................................................................. 49 15. Revision History .................................................................................................................. 49 IMPORTANT NOTICE ................................................................................................................ 50 015002029-E-00 -2- 2015/02 [AK4432] 4. Block Diagram Block Diagram Audio I/F AOUTL AOUTR SMF SMF SCF SCF PDN DAC MCLK MCLK DAC LRCK BICK LRCK BICK SDIN SDTI VSS AVDD uP I/F (I2C/SPI) SMUTE/CSN/I2CFIL ACKS/CCLK/SCL VCOM DIF/CDTI/SDA LDO LVDD P/S LDOO Figure 1. Block Diagram 015002029-E-00 -3- 2015/02 [AK4432] Compatibility with AK4438, AK4452 and AK4458 Channel fs S/(N+D) DR AVDD (Analog Supply) TVDD or LVDD (I/O Buffer) Digital Filter SA(Sharp) GD(Sharp) GD (SD Slow) Super Slow Roll-off OSR Doubler (Over Sampling) Zero Detection Digital Volume ATT Speed (*Default) LR Ch Output Select Reset Function (MCLK detect) Clock Synchronization Package AK4432 2ch 8k to 192kHz 91dB 108dB 3.0 to 3.6V 3.0 to 3.6V 69.9dB 26.4/fs 5.2/fs No No (128x) No +12 to -115.0dB 1020/fs (*) 4080 No AK4436 / 38 6ch / 8ch 8k to 768kHz 91dB 108dB 3.0 to 3.6V 1.7 to 3.6V 80dB 26.8/fs 4.8/fs Yes Yes (256x) Yes +0 to -127.0dB 4080/fs (*) 2040510255 Yes AK4452 / 54 / 56 / 58 2ch / 4ch / 6ch / 8ch 8k to 768kHz 107dB 115dB 3.0 to 5.5V 1.7 to 3.6V 80dB 26.8/fs 4.8/fs Yes Yes (256x) Yes +0 to -127.0dB 4080/fs (*) 2040510255 Yes No Yes Yes Yes (Note) Yes 16-pin TSSOP 32-pin QFN Yes AK4452/54: 32-pin QFN AK4456/58: 48-pin QFN Note. MSB justified and 32-bit I2S compatible formats are available for audio interface but LSB justified format is not available. 015002029-E-00 -4- 2015/02 [AK4432] 5. Pin Configurations and Functions Ordering Guide AK4432VT AKD4432 -40 +105C 16-pin TSSOP (0.65mm pitch) Evaluation Board for the AK4432 Pin Layout MCLK 1 16 LDOO BICK 2 15 LVDD SDTI 3 14 AVDD LRCK 4 13 VSS PDN 5 12 VCOM SMUTE/CSN/I2CFIL 6 11 AOUTL ACKS/CCLK/SCL 7 10 AOUTR DIF/CDTI/SDA 8 9 P/S AK4432 Top View Figure 2. Pin Layout 015002029-E-00 -5- 2015/02 [AK4432] Pin Functions No. Pin Name MCLK BICK SDTI LRCK I/O I I I I PD state - Function 1 External Master Clock Input Pin 2 Audio Serial Data Clock Pin 3 Audio Serial Data Input 4 Input Channel Clock Pin Power-Down & Reset Pin 5 PDN I When "L", the AK4432 is powered-down and the control registers are reset to default state. Soft Mute Pin in Parallel control mode. SMUTE I When this pin is changed to "H", soft mute cycle is initiated. When returning "L", the output mute releases. 6 CSN I Chip Select Pin in 3-wire serial control mode I2C Interface Mode Select Pin I2CFIL I "L": Fast Mode (400kHz), "H": Fast Mode Plus (1MHz). Do not change this pin during PDN pin = "H". Auto Setting Mode in Parallel control mode ACKS I "L": Manual Setting Mode, "H": Auto Setting Mode 7 CCLK I Control Data Clock Pin in 3-wire serial control mode SCL I Control Data Clock Pin in I2C Bus serial control mode Audio Data Format Select in Parallel control mode. DIF I "L": 32bit MSB, "H": 32bit I2S 8 CDTI I Control Data Input Pin in 3-wire serial control mode SDA I/O Control Data Input Pin in I2C Bus serial control mode Parallel/Serial Mode Select Pin 9 P/S I "L": Serial Mode, "H": Parallel Mode Do not change this pin during PDN pin = "H". 10 AOUTR O Hi-z Rch Analog Output Pin 11 AOUTL O Hi-z Lch Analog Output Pin Common Voltage Output Pin, AVDDx1/2 500ohm 12 VCOM O Large external capacitor around 2.2F is used to reduce Pull-down power-supply noise. 13 VSS Ground Pin 14 AVDD Analog Power Supply Pin, 3.0V3.6V 15 LVDD LDO Power Supply / Digital I/F Power Supply Pin, 3.0V3.6V 580ohm LDO Output Pin 16 LDOO O Pull-down This pin should be connected to ground with 1.0uF. Note 1. All digital input pins must not be allowed to float. Handling of Unused Pin Unused I/O pins must be connected appropriately. Classification Analog 015002029-E-00 Pin Name AOUTL, AOUTR Setting Open -6- 2015/02 [AK4432] 6. Absolute Maximum Ratings (VSS =0V; Note 2) Parameter Symbol Min. Max. Unit Power Supply AVDD -0.3 4.3 V Power Supply LVDD -0.3 4.3 V Input Current (any pins except for supplies) IIN mA 10 Input Voltage (Note 3) VIN -0.3 (LVDD+0.3) or 4.3 V Ambient Temperature (power applied) Ta -40 105 C Storage Temperature Tstg -65 150 C Note 2. All voltages with respect to ground. VSS must be connected to the same analog ground plane. Note 3. The maximum Digital input voltage is smaller value between (LVDD+0.3)V and 4.3V. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 7. Recommended Operation Conditions (VSS=0V; Note 2) Parameter Power Supplies Analog Symbol AVDD Min. 3.0 Typ. 3.3 Max. 3.6 Unit V LDO, Digital (I/F) LVDD 3.0 3.3 3.6 V Note 4. Do not turn off the power supply of the AK4432 with the power supply of the peripheral device turned on. When using the I2C interface, pull-up resistors of SDA and SCL pins should be connected to LVDD or less voltage. * AKM assumes no responsibility for the usage beyond the conditions in this data sheet. 015002029-E-00 -7- 2015/02 [AK4432] 8. Analog Characteristics (Ta=25C; AVDD = LVDD=3.3V; VSS =0V; fs=48kHz, 96kHz, 192kHz; BICK=64fs; Signal Frequency=1kHz; 32bit Data; Measurement Frequency=20Hz20kHz at fs=48kHz, 20Hz~40kHz at fs=96kHz, 20Hz~40kHz at fs=192kHz, unless otherwise specified.) Parameter Min. Typ. Max. Unit DAC Analog Output Characteristics Resolution 32 bit Output Voltage (Note 5) 2.55 2.83 3.11 Vpp S/(N+D) fs=48kHz 80 91 dB (0dBFS) fs=96kHz 89 dB fs=192kHz 89 dB Dynamic Range fs=48kHz (A-weighted) 108 dB (-60dBFS) fs=96kHz 101 fs=192kHz 101 S/N fs=48kHz (A-weighted) 108 dB fs=96kHz 101 fs=192kHz 101 Interchannel Isolation 90 110 dB Interchannel Gain Mismatch 0 0.7 dB Load Resistance (Note 6) 10 k Load Capacitance 30 pF Note 5. Full-scale output voltage. The output voltage is always proportional to AVDD (AVDD x 0.86). Note 6. AC Load Parameter Power Supplies Power Supply Current Normal Operation (PDN pin = "H") AVDD fs=48kHz, 96kHz, 192kHz LVDD fs=48kHz fs=96kHz fs=192kHz Typ. Max. Unit 6.5 1.3 1.6 2.1 9.0 2 2.5 3.0 mA mA mA mA Power-down mode (PDN pin = "L") (Note 7) 10 200 Note 7. Quiescent Current. All digital input pins including clock pins are fixed to VSS. A 015002029-E-00 -8- Min. 2015/02 [AK4432] 9. Filter Characteristics (fs=48kHz) (Ta= -40 +105C; AVDD =3.0 3.6V, LVDD=3.0 3.6V; DEM=OFF) Sharp Roll-Off Filter (DASD bit = "0", DASL bit = "0") fs=48kHz Parameter -0.08dB~+0.08dB Passband (Note 8) -6.0dB Passband Ripple Stopband (Note 8) Stopband Attenuation Group Delay (Note 9) Digital Filter + SCF + SMF Frequency Response: 0Hz 20kHz fs=96kHz Parameter -0.08dB~+0.08dB Passband (Note 8) -6.0dB Passband Ripple Stopband (Note 8) Stopband Attenuation Group Delay (Note 9) Digital Filter + SCF + SMF Frequency Response: 0Hz 40kHz fs=192kHz Parameter -0.08dB~+0.08dB Passband (Note 8) -6.0dB Passband Ripple Stopband (Note 8) Stopband Attenuation Group Delay (Note 9) Digital Filter + SCF + SMF Frequency Response: 0Hz 80kHz 015002029-E-00 Symbol PB PB PR SB SA GD Min. 0 -0.08 26.2 69.9 - FR -0.20 Symbol PB PB PR SB SA GD Min. 0 -0.08 52.5 69.8 - FR -0.50 Symbol PB PB PR SB SA GD Min. 0 -0.08 104.9 69.8 - FR -2.00 -9- Typ. 23.99 Max. 22.2 +0.08 26.4 - Unit kHz kHz dB kHz dB 1/fs -0.10 dB Typ. 48.00 Max. 44.4 +0.08 26.4 - Unit kHz kHz dB kHz dB 1/fs -0.10 dB Typ. 96.00 Max. 88.8 +0.08 26.4 - Unit kHz kHz dB kHz dB 1/fs 0.00 dB 2015/02 [AK4432] Slow Roll-Off Filter (DASD bit = "0", DASL bit = "1") fs=48kHz Parameter -0.07dB~+0.021dB Passband (Note 8) -3.0dB Passband Ripple Stopband (Note 8) Stopband Attenuation Group Delay (Note 9) Digital Filter + SCF + SMF Frequency Response: 0Hz 20kHz fs=96kHz Parameter -0.07dB~+0.023dB Passband (Note 8) -3.0dB Passband Ripple Stopband (Note 8) Stopband Attenuation Group Delay (Note 9) Digital Filter + SCF + SMF Frequency Response: 0Hz 40kHz fs=192kHz Parameter -0.07dB~+0.023dB Passband (Note 8) -3.0dB Passband Ripple Stopband (Note 8) Stopband Attenuation Group Delay (Note 9) Digital Filter + SCF + SMF Frequency Response: 0Hz 80kHz 015002029-E-00 Symbol PB PB PR SB SA GD Min. 0 -0.07 42.6 72.6 - FR -3.75 Symbol PB PB PR SB SA GD Min. 0 -0.07 85.1 72.6 - FR -4.25 Symbol PB PB PR SB SA GD Min. 0 -0.07 170.3 72.6 - FR -5.00 - 10 - Typ. 19.75 Max. 9.0 +0.021 26.4 - Unit kHz kHz dB kHz dB 1/fs -2.75 dB Typ. 39.6 Max. 18.1 +0.023 26.4 - Unit kHz kHz dB kHz dB 1/fs -2.75 dB Typ. 79.3 Max. 36.1 +0.023 26.4 - Unit kHz kHz dB kHz dB 1/fs -3.00 dB 2015/02 [AK4432] Short Delay Sharp Roll-Off Filter (DASD bit = "1", DASL bit = "0") fs=48kHz Parameter -0.07dB~+0.07dB Passband (Note 8) -6.0dB Passband Ripple Stopband (Note 8) Stopband Attenuation Group Delay (Note 9) Digital Filter + SCF + SMF Frequency Response: 0Hz 20kHz fs=96kHz Parameter -0.08dB~+0.08dB Passband (Note 8) -6.0dB Passband Ripple Stopband (Note 8) Stopband Attenuation Group Delay (Note 9) Digital Filter + SCF + SMF Frequency Response: 0Hz 40kHz fs=192kHz Parameter -0.08dB~+0.08dB Passband (Note 8) -6.0dB Passband Ripple Stopband (Note 8) Stopband Attenuation Group Delay (Note 9) Digital Filter + SCF + SMF Frequency Response: 0Hz 80kHz 015002029-E-00 Symbol PB PB PR SB SA GD Min. 0 -0.07 26.2 56.6 - FR -0.20 Symbol PB PB PR SB SA GD Min. 0 -0.08 52.5 56.4 - FR -0.50 Symbol PB PB PR SB SA GD Min. 0 -0.08 104.9 56.4 - FR -2.00 - 11 - Typ. 24.11 Max. 22.0 +0.07 5.9 - Unit kHz kHz dB kHz dB 1/fs -0.10 dB Typ. 48.25 Max. 44.3 +0.08 5.9 - Unit kHz kHz dB kHz dB 1/fs -0.10 dB Typ. 96.50 Max. 88.6 +0.08 5.9 - Unit kHz kHz dB kHz dB 1/fs 0.00 dB 2015/02 [AK4432] Short Delay Slow Roll-Off Filter (DASD bit = "1", DASL bit = "1") fs=48kHz Parameter -0.07dB~+0.05dB Passband (Note 8) -3.0dB Passband Ripple Stopband (Note 8) Stopband Attenuation Group Delay (Note 9) Digital Filter + SCF + SMF Frequency Response: 0Hz 20kHz fs=96kHz Parameter -0.07dB~+0.05dB Passband (Note 8) -3.0dB Passband Ripple Stopband (Note 8) Stopband Attenuation Group Delay (Note 9) Digital Filter + SCF + SMF Frequency Response: 0Hz 40kHz Symbol PB PB PR SB SA GD Min. 0 -0.07 43.0 74.9 - FR -3.50 Symbol PB PB PR SB SA GD Min. 0 -0.07 86.0 74.9 - FR -4.00 Typ. 20.24 Max. 10.1 +0.05 5.2 - Unit kHz kHz dB kHz dB 1/fs -2.50 dB Typ. 40.50 Max. 20.3 +0.05 5.2 - Unit kHz kHz dB kHz dB 1/fs -2.50 dB fs=192kH Parameter Symbol Min. Typ. Max. Unit -0.07dB~+0.05dB PB 0 40.6 kHz Passband (Note 8) -3.0dB PB 81.00 kHz Passband Ripple PR -0.07 +0.05 dB Stopband (Note 8) SB 172.0 kHz Stopband Attenuation SA 74.9 dB Group Delay (Note 9) GD 5.2 1/fs Digital Filter + SCF + SMF FR -4.75 -2.75 dB Frequency Response: 0Hz 80kHz Note 8. The passband and stopband frequencies are proportional to "fs" (system sampling rate). Each frequency response refers to that of 1kHz. Note 9. The calculated delay time caused by digital filtering. The digital filter's delay is calculated as the time from setting 16/24/32bit impulse data into the input register until an analog peak signal is output. 015002029-E-00 - 12 - 2015/02 [AK4432] 10. DC Characteristics (Ta= -40 +105C; AVDD =3.0 3.6V, LVDD =3.0 3.6V, VSS=0V) Parameter Symbol Min. All digital input pins except SCL and SDA pins High-Level Input Voltage VIH1 80%LVDD Low-Level Input Voltage VIL1 SCL, SDA Pin High-Level Input Voltage VIH2 70%LVDD Low-Level Input Voltage VIL2 SDA Pin Low-Level Output Voltage Fast Mode (Iout= 3mA) VOL1 Fast Mode Plus (Iout= 20mA) VOL2 Input Leakage Current Iin - 015002029-E-00 - 13 - Typ. Max. Unit - 20%LVDD V V - 30%LVDD V V - 0.4 0.4 10 V V A 2015/02 [AK4432] 11. Switching Characteristics (Ta=-40 105C; AVDD=LVDD=3.0 3.6V; CL=20pF, unless otherwise specified) Parameter Symbol Min. Typ. Max. Master Clock Timing External Clock 256fsn: fCLK 2.048 12.288 Pulse Width Low tCLKL 32 Pulse Width High tCLKH 32 384fsn: fCLK 3.072 18.432 Pulse Width Low tCLKL 22 Pulse Width High tCLKH 22 512fsn, 256fsd, 128fsq: fCLK 4.096 24.576 Pulse Width Low tCLKL 16 Pulse Width High tCLKH 16 768fsn, 384fsd, 192fsq: fCLK 16.384 36.864 Pulse Width Low tCLKL 11 Pulse Width High tCLKH 11 LRCK Timing (Slave Mode) Stereo mode (TDM1-0 bits = "00") Normal Speed Mode fsn 8 48 Double Speed Mode fsd 48 96 Quad Speed Mode fsq 96 192 Duty Cycle Duty 50 TDM128 mode (TDM1-0 bits = "01") LRCK frequency fsn 8 48 fsd 48 96 fsq 96 192 I2S compatible: Pulse Width Low tLRL 1/(128fsq) 127/(128fsq) MSB or LSB justified: Pulse Width High tLRH 1/(128fsq) 127/(128fsq) TDM256 mode (TDM1-0 bits = "10") LRCK frequency fsn 8 48 fsd 48 96 I2S compatible: Pulse Width Low tLRL 1/(256fsd) 255/(256fsd) MSB or LSB justified: Pulse Width High tLRH 1/(256fsd) 255/(256fsd) 015002029-E-00 - 14 - Unit MHz ns ns MHz ns ns MHz ns ns MHz ns ns kHz kHz kHz % kHz kHz kHz s s kHz kHz s s 2015/02 [AK4432] Parameter Symbol Min. Audio Interface Timing Normal Mode (TDM1-0 bits = "00") BICK Period Normal Speed Mode tBCK 1/256fsn Double Speed Mode tBCK 1/256fsd Quad Speed Mode tBCK 1/128fsq BICK Pulse Width Low tBCKL 18 BICK Pulse Width High tBCKH 18 BICK "" to LRCK Edge (Note 10) tBLR 5 tLRB 5 LRCK Edge to BICK "" (Note 10) tSDH 5 SDTI Hold Time tSDS 5 SDTI Setup Time TDM128 mode (TDM1-0 bits = "01") BICK Period Normal Speed Mode tBCK 1/128fsn Double Speed Mode tBCK 1/128fsd Quad Speed Mode tBCK 1/128fsq BICK Pulse Width Low tBCKL 18 BICK Pulse Width High tBCKH 18 BICK "" to LRCK Edge (Note 10) tBLR 5 tLRB 5 LRCK Edge to BICK "" (Note 10) tSDH 5 SDTI Hold Time tSDS 5 SDTI Setup Time TDM256 mode (TDM1-0 bits = "10") BICK Period Normal Speed Mode tBCK 1/256fsn Double Speed Mode tBCK 1/256fsd BICK Pulse Width Low tBCKL 18 BICK Pulse Width High tBCKH 18 BICK "" to LRCK Edge (Note 10) tBLR 5 tLRB 5 LRCK Edge to BICK "" (Note 10) tSDH 5 SDTI Hold Time tSDS 5 SDTI Setup Time Note 10. BICK rising edge must not occur at the same time as LRCK edge. 015002029-E-00 - 15 - Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2015/02 [AK4432] Parameter Symbol Min. Typ. Max. Unit Control Interface Timing (3-wire Serial mode): CCLK frequency fCCK 7 MHz CCLK Pulse Width Low tCCKL 60 ns Pulse Width High tCCKH 60 ns CDTI Setup Time tCDS 60 ns CDTI Hold Time tCDH 60 ns CSN "H" Time tCSW 150 ns tCSS 150 ns CSN "" to CCLK "" tCSH 240 ns CCLK "" to CSN "" Control Interface Timing (I2C Fast mode): kHz SCL Clock Frequency fSCL 400 s Bus Free Time Between Transmissions tBUF 1.3 s Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6 s Clock Low Time tLOW 1.3 s Clock High Time tHIGH 0.6 Setup Time for Repeated Start Condition tSU:STA 0.6 s SDA Hold Time from SCL Falling (Note 11) tHD:DAT 0 s SDA Setup Time from SCL Rising tSU:DAT 0.1 s Rise Time of Both SDA and SCL Lines tR 1.0 s Fall Time of Both SDA and SCL Lines tF 0.3 s Setup Time for Stop Condition tSU:STO 0.6 s Pulse Width of Spike Noise Suppressed by Input Filter tSP 0 50 ns pF Capacitive load on bus Cb 400 Control Interface Timing (I2C Fast mode Plus): MHz SCL Clock Frequency fSCL 1 s Bus Free Time Between Transmissions tBUF 0.5 s Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.26 s Clock Low Time tLOW 0.5 s Clock High Time tHIGH 0.26 Setup Time for Repeated Start Condition tSU:STA 0.26 s SDA Hold Time from SCL Falling (Note 12) tHD:DAT 0 s SDA Setup Time from SCL Rising tSU:DAT 0.05 s Rise Time of Both SDA and SCL Lines tR 0.12 s Fall Time of Both SDA and SCL Lines tF 0.12 s Setup Time for Stop Condition tSU:STO 0.26 s Pulse Width of Spike Noise Suppressed by Input Filter tSP 0 50 ns pF Capacitive load on bus Cb 550 Power-down & Reset Timing PDN Pulse Width (Note 13) tPD 800 ns Note 11. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note 12. Data must be held for sufficient time to bridge the 120ns transition time of SCL. Note 13. The AK4432 can be reset by setting the PDN pin to "L" upon power-up. The PDN pin must held "L" for more than 800ns for a certain reset. The AK4432 is not reset by the "L" pulse less than 50ns. Note 14. I2C is a trademark of NXP B.V. 015002029-E-00 - 16 - 2015/02 [AK4432] Timing Diagram 1/fCLK VIH MCLK VIL tCLKH tCLKL 1/fsn, 1/fsd, 1/fsq VIH LRCK VIL tdLRKH tdLRKL Duty = tdLRKH (or tdLRKL) x fs x 100 tBCK VIH BICK VIL tBCKH tBCKL Figure 3. Clock Timing (TDM1-0 bits = "00") 1/fCLK VIH MCLK VIL tCLKH tCLKL 1/fs VIH LRCK VIL tLRH tLRL tBCK VIH BICK VIL tBCKH tBCKL Figure 4. Clock Timing (Except TDM1-0 bits = "00") 015002029-E-00 - 17 - 2015/02 [AK4432] VIH LRCK VIL tBLR tLRB VIH BICK VIL tSDS tSDH VIH SDTI VIL Figure 5. Audio Interface Timing (TDM1-0 bits = "00") VIH LRCK VIL tBLR tLRB VIH BICK VIL tSDS tSDH VIH SDTI VIL Figure 6. Audio Interface Timing (Except TDM1-0 bits = "00") 015002029-E-00 - 18 - 2015/02 [AK4432] VIH VIL CCLK tCCKL tCCKH 1/fCCK 1/fCCK Figure 7. 3-wire Serial Mode Interface Timing VIH VIL tCSW CSN VIH CDTI VIL tCDS tCDH VIH VIL CCLK tCSS tCSH tCSS tCSH Figure 8. WRITE Data Input Timing (3-wire Serial mode) 015002029-E-00 - 19 - 2015/02 [AK4432] VIH SDA VIL tLOW tBUF tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT Start tSU:DAT tSU:STA tSU:STO Start Stop Figure 9. I2C Bus Mode Timing tPD VIH PDN VIL Figure 10. Power-down & Reset Timing 015002029-E-00 - 20 - 2015/02 [AK4432] 12. Functional Descriptions System Clock The external clocks which are required to operate the AK4432 are MCLK, LRCK and BICK. MCLK should be synchronized with LRCK and BICK but the phase is not critical. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS bit= "0": Default), the sampling speed is set by DFS0, DFS1 (Table 1). The frequency of MCLK at each sampling speed is set automatically (Table 2, Table 3, Table 4). In Auto Setting Mode (ACKS bit= "1"), as MCLK frequency is detected automatically (Table 5) and the internal master clock attains the appropriate frequency (Table 6), so it is not necessary to set DFS bits. The AK4432 exits system reset (power-down mode) by inputting MCLK and LRCK after the PDN pin="H". If the clock is stopped, a click noise occurs when restarting the clock. Mute the digital output externally if the click noise affects system applications. DFS1 0 0 1 1 LRCK fs 8.0kHz 44.1kHz 48.0kHz DFS0 0 1 0 1 Sampling Speed Mode (fs) Normal Speed Mode 8kHz~48kHz (default) Double Speed Mode 48kHz~96kHz Quad Speed Mode 96kHz~192kHz N/A (N/A: Not available) Table 1. Sampling Speed (Manual Setting Mode) 256fs 2.0480 11.2896 12.2880 MCLK (MHz) 384fs 512fs 3.0720 4.0960 16.9344 22.5792 18.4320 24.5760 768fs 6.1440 33.8688 36.8640 BICK (MHz) 64fs 0.512 2.8224 3.0720 Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode) LRCK fs 88.2kHz 96.0kHz MCLK (MHz) 256fs 384fs 22.5792 33.8688 24.5760 36.8640 BICK (MHz) 64fs 5.6448 6.1440 Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode) LRCK fs 176.4kHz 192.0kHz MCLK (MHz) 128fs 192fs 22.5792 24.5760 33.8688 36.8640 BICK (MHz) 64fs 11.2896 12.2880 Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode) 015002029-E-00 - 21 - 2015/02 [AK4432] 512fs 256fs 128fs MCLK 768fs 384fs 192fs Sampling Speed Mode Normal Speed Mode Double Speed Mode Quad Speed Mode Table 5. Sampling Speed (Auto Setting Mode) LRCK fs 8.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz 128fs 22.5792 24.5760 192fs 33.8688 36.8640 MCLK (MHz) 256fs 384fs 22.5792 33.8688 24.5760 36.8640 - 512fs 4.0960 22.5792 24.5760 - 768fs 6.1440 33.8688 36.8640 - Sampling Speed Mode Normal Speed Mode Double Speed Mode Quad Speed Mode Table 6. System Clock Example (Auto Setting Mode) 015002029-E-00 - 22 - 2015/02 [AK4432] Audio Interface Format TDM1-0 bits, DIF2-0 bits, SDS2-0 bits, TDM1-0 pins and DIF pin settings should not be changed during operation. MSB justified and I2S formats are available but LSB justified format is not available when SYNCE bit = "1" (default). Normal Mode (TDM1-0 bit="00") Two channels audio data is shifted in via the SDTI pin using BICK and LRCK inputs. Eight data formats are supported and selected by the DIF2-0 bits as shown in Table 7. In all formats the serial data is MSB first, 2's complement format and is latched on the rising edge of BICK. Input "0" data to unused bits if the data does not use maximum bits when MSB justified, I2S format is selected. (e.g. Mode2 can be used in 16-bit MSB justified by zeroing the unused 8bits LSB). TDM128 Mode (TDM1-0 bit="01") Four channels audio data is shifted in via the SDTI pin using BICK and LRCK inputs. Data is selected by SDS1-0 bits. BICK is fixed to 128fs. Six data formats are supported and selected by the DIF2-0 bits as shown in Table 7. In all formats the serial data is MSB first, 2's complement format and is latched on the rising edge of BICK. TDM256 Mode (TDM1-0 bit="1X") Eight channels audio data is shifted in via the SDTI pin using BICK and LRCK inputs. Data is selected by SDS1-0 bits. BICK is fixed to 256fs. Six data formats are supported and selected by the DIF2-0 bits as shown in Table 7. In all formats the serial data is MSB first, 2's complement format and is latched on the rising edge of BICK. 015002029-E-00 - 23 - 2015/02 [AK4432] Mode TDM1 TDM0 DIF2 0 0 0 DIF1 0 0 1 DIF0 0 1 0 SDTI Format LRCK BICK 0 16-bit LSB justified H/L 32fs 1 20-bit LSB justified H/L 40fs 2 24-bit MSB justified H/L 48fs 16-bit I2S compatible L/H 32fs 3 0 1 1 Normal 2 24-bit I S compatible L/H 0 0 48fs (Note 15) 4 1 0 0 24-bit LSB justified H/L 48fs 5 1 0 1 32-bit LSB justified H/L 64fs 6 1 1 0 32-bit MSB justified H/L 64fs 7 1 1 1 32-bit I2S compatible L/H 64fs 0 0 0 N/A 128fs 0 0 1 N/A 128fs 8 0 1 0 24-bit MSB justified 128fs 9 0 1 1 24-bit I2S compatible 128fs TDM128 0 1 10 1 0 0 24-bit LSB justified 128fs 11 1 0 1 32-bit LSB justified 128fs 12 1 1 0 32-bit MSB justified 128fs 13 1 1 1 32-bit I2S compatible 128fs 0 0 0 N/A 256fs 0 0 1 N/A 256fs 14 0 1 0 24-bit MSB justified 256fs 15 0 1 1 24-bit I2S compatible 256fs TDM256 1 0 16 1 0 0 24-bit LSB justified 256fs 17 1 0 1 32-bit LSB justified 256fs 18 1 1 0 32-bit MSB justified 256fs 19 1 1 1 32-bit I2S compatible 256fs Note 15. BICK that is input to each channel must be longer than the bit length of setting format. Table 7. Audio Data Format (N/A: Not available) 015002029-E-00 - 24 - 2015/02 [AK4432] LRCK 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 BICK (32fs) SDTI Mode 0 15 14 6 1 0 5 14 4 15 3 16 2 1 17 0 31 15 0 14 6 5 14 1 4 15 3 16 2 1 17 0 31 15 14 0 1 0 1 0 1 BICK (64fs) SDTI Mode 0 Don't care 15 14 Don't care 0 15 14 0 15:MSB, 0:LSB Lch Data Rch Data Figure 11. Mode 0 Timing LRCK 0 1 8 9 10 11 12 31 0 1 8 9 10 11 12 31 BICK (64fs) SDTI Mode 1 Don't care 19 0 Don't care 19 0 Don't care 19 0 19 0 19:MSB, 0:LSB SDTI Mode 4 Don't care 23 22 21 20 23 22 20 21 23:MSB, 0:LSB Lch Data Rch Data Figure 12. Mode 1/4 Timing LRCK 0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 BICK (64fs) SDTI 23 22 1 0 Don't care 23 22 1 0 Don't care 23 22 23:MSB, 0:LSB Lch Data Rch Data Figure 13. Mode 2 Timing 015002029-E-00 - 25 - 2015/02 [AK4432] LRCK 0 1 2 3 23 24 25 31 0 1 2 3 23 24 25 31 0 1 BICK (64fs) SDTI 23 0 1 22 Don't care 23 22 0 1 23 Don't care 23:MSB, 0:LSB Lch Data Rch Data Figure 14. Mode 3 Timing LRCK 0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 0 1 BICK (64fs) SDTI Mode 5,6 31 30 1 0 31 30 0 1 31 30 32:MSB, 0:LSB Lch Data Rch Data Figure 15. Mode 5/6 Timing LRCK 0 1 2 3 23 24 25 31 0 1 0 31 2 3 23 24 25 31 0 1 0 31 BICK (64fs) SDTI 31 30 1 30 1 30 32:MSB, 0:LSB Lch Data Rch Data Figure 16. Mode 7 Timing 015002029-E-00 - 26 - 2015/02 [AK4432] 128 BICK LRCK BICK(128fs) SDTI Mode8 23 22 SDTI Mode11,12 31 30 0 23 22 0 0 31 30 23 22 23 22 0 0 31 30 0 0 31 30 23 22 0 31 30 2 L1 R1 L2 R2 32 BICK 32 BICK 32 BICK 32 BICK Figure 17. Mode 8/11/12 Timing 128 BICK LRCK BICK(128fs) SDTI Mode9 23 22 SDTI Mode13 31 30 0 0 23 22 0 23 22 0 31 30 23 22 0 31 30 L1 R1 32 BICK 32 BICK 23 0 0 31 30 2 0 31 30 L2 R2 32 BICK 32 BICK Figure 18. Mode 9/13 Timing 128 BICK LRCK BICK(128fs) SDTI 23 22 0 23 22 0 23 22 0 0 23 22 L1 R1 L2 R2 32 BICK 32 BICK 32 BICK 32 BICK 23 Figure 19. Mode 10 Timing 015002029-E-00 - 27 - 2015/02 [AK4432] 256 BICK LRCK BICK (256fs) SDTI Mode14 SDTI Mode17,18 23 22 0 31 30 23 22 0 0 31 30 23 22 0 0 31 30 23 22 0 0 31 30 23 22 0 0 31 30 23 22 0 0 31 30 23 22 0 0 31 30 23 22 0 0 31 30 23 22 0 31 30 L1 R1 L2 R2 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 23 23 Figure 20. Mode 14/17/18 Timing 256 BICK LRCK BICK (256fs) SDTI Mode15 SDTI Mode19 23 0 23 31 30 0 23 0 31 30 0 23 0 31 30 0 23 0 31 30 0 23 0 31 30 0 0 31 30 0 0 31 30 0 0 31 30 23 0 31 L1 R1 L2 R2 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK Figure 21. Mode 15/19 Timing 256 BICK LRCK BICK(256fs) SDTI 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 L1 R1 L2 R2 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 0 23 Figure 22. Mode 16 Timing 015002029-E-00 - 28 - 2015/02 [AK4432] [2] Data Select SDS1-0 bits control the playback channel of each DAC. LRCK L1 SDTI R1 Figure 23. Data Slot in Normal Mode 128 BICK LRCK L1 SDTI R1 L2 R2 Figure 24. Data Slot in TDM128 Mode 256 BICK LRCK SDTI L1 R1 L2 R2 L3 R3 L4 R4 Figure 25. Data Slot in TDM256 Mode Normal TDM128 SDS1 SDS0 x x DAC1 Lch Rch L1 R1 x 0 L1 R1 x 1 L2 R2 0 0 1 1 0 1 0 1 L1 R1 L2 R2 TDM256 L3 R3 L4 R4 (x: don't care) Table 8. Data Select 015002029-E-00 - 29 - 2015/02 [AK4432] Digital Volume Function The AK4432 has a channel-independent digital attenuator (256 levels, 0.5dB steps). Attenuation level of each channel of the DAC can be set by ATT7-0 bits (register 04-05H), respectively (Table 9). DAC Lch ATTL7-0bits 00h 01h 02h : 17h 18h 19h : FDh FEh FFh DAC Rch ATTR7-0bits 00h 01h 02h : 17h 18h 19h : FDh FEh FFh Attenuation Level +12.0dB +11.5dB +11.0dB : +0.5dB 0.0dB -0.5dB : -114.5dB -115.0dB MUTE (-) (default) Table 9. Attenuation level of Digital Attenuator Transition time between set values of ATT7-0 bits can be selected by the ATS bit (Table 10). When changing output levels, transitions are executed via soft changes (0.125dB steps by every 1/4 ATT speed); thus not switching noise occurs during these transitions. Mode ATS 0 1 0 1 ATT speed(Transition Time) 1 step(0.5dB) Soft Transition(0.125dB) 4/fs 1/fs 16/fs 4/fs (default) Table 10. Digital Volume Transition Time In Mode0, it takes 255step*4/fs+1/fs(mute)=1020/fs (21.3ms @fs=48kHz) from FFH to 00H and in Mode1, it takes 255step*16/fs+4/fs(mute)=4084/fs (85.1ms @fs=48kHz). Mode ATS 0 1 0 1 00h FFh Transition Time Transition Time(fs) fs=48kHz fs=44.1kHz 1021/fs 21.3ms 23.2ms 4084/fs 85.1ms 92.6ms Table 11. Digital Volume Transition Time 00h FFh fs=8kHz 127.6ms 510.5ms (default) Just after power up the DAC, the digital volume level is at MUTE. Then, the volume changes to the value set by registers in soft transition after releasing the power-down state. 015002029-E-00 - 30 - 2015/02 [AK4432] Soft Mute Operation The soft mute operation is performed at digital domain. When the SMUTE pin goes to "H" or set SMUTE bit to "1", the output signal is attenuated by during ATT_DATA ATT transition time from the current ATT level. When the SMUTE pin is returned to "L" or the SMUTE bit is returned to "0", the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA ATT transition time. If the soft mute is cancelled before attenuating , the attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source without stopping the signal transmission. SMUTE pin or SMUTE bit (1) (1) ATT_Level (3) Attenuation - GD (2) GD (2) AOUT Note: (1) ATT_DATA ATT transition time. For example, this time is 1020LRCK cycles (1020/fs) at ATT_DATA=255 in Normal Speed Mode. (2) The analog output corresponding to the digital input has group delay (GD). (3) If the soft mute is cancelled before attenuating after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. Figure 26. Soft Mute Function and Zero Detection 015002029-E-00 - 31 - 2015/02 [AK4432] Error Detection Three types of error can be detected by the AK4432 (Table 12). The internal LDO will be powered down and register access will be disabled when an error is detected. Once an error is detected, the AK4432 will not return to normal operation automatically even if all error conditions are removed. Reset the AK4432 once by bringing the PDN pin = "L" and start up again. In I2C mode, errors can be detected by monitoring Acknowledge. If an error occurs, the AK4432 stops sending Acknowledge. No Error Error Condition 1 Internal Reference Voltage Error Internal reference voltage is not powered up. 2 LDO Over Voltage Detection LDO voltage > 1.6V (Typ) 3 LDO Over Current Detection LDO current < 100mA (Typ) Table 12. ERROR Detection System Reset The AK4432 should be reset once by bringing the PDN pin = "L" upon power-up. Power-down state of the reference voltage such as LDO and VCOM will be released by the PDN pin = "H", and then after 1ms register writing becomes available. The internal DAC will be powered up after MCLK and LRCK are input. The AK4432 is in power-down state until MCLK and LRCK are input. 015002029-E-00 - 32 - 2015/02 [AK4432] Power Down Function The AK4432 is placed in power-down mode by bringing the PDN pin "L" and the analog outputs become floating (Hi-Z) state. Power-up and power-down timings are shown in Figure 27. Power (1) PDN pin LDOO pin (2) Internal PDN Internal State Normal Operation (Register Write and DAC input are available) DAC In (Digital) "0"data "0"data GD (4) DAC Out (Analog) Reset (3) (5) GD (5) (4) (6) Clock In Don't care Don't care MCLK,LRCK,BICK External Mute (7) Mute ON Mute ON Note: (1) After AVDD and LVDD are powered-up, the PDN pin should be "L" for 800ns. (2) After PDN pin = "H", the LDO circuit (internal digital block driving power supply) and REF generating circuit (analog reference voltage source) are powered up, and control registers are initialized. Control register settings should be made after 1ms from the PDN pin = "H". (3) The analog output corresponding to digital input has group delay (GD). (4) Analog outputs are floating (Hi-Z) in power down mode. (5) Click noise occurs at an edge of PDN signal. This noise is output even if "0" data is input. (6) MCLK, BICK and LRCK clocks can be stopped in power-down mode (PDN pin= "L"). (7) Mute the analog output externally if click noise (5) adversely affect system performance. The timing example is shown in this figure. Figure 27. Pin Power Down/Up Sequence Example 015002029-E-00 - 33 - 2015/02 [AK4432] Power Off and Reset Functions PMDA DAC 0 1 OFF ON Register Digital Analog Output Keep OFF Hi-Z Keep ON normal Table 13. Power OFF and Reset Function (default) (1) Power OFF Function (PMDA bit) All DACs will be powered down immediately by setting PMDA bit to "0". In this time, all internal circuits except register are powered down and the analog output goes to floating state (Hi-z). Figure 28 shows a timing example of power-on and power-down. PMDA bit Internal State Normal Operation Power-off D/A In (Digital) Normal Operation "0" data GD D/A Out (Analog) (1) GD (3) (2) (3) (1) (4) Clock In Don't care MCLK, BICK, LRCK External MUTE (5) Mute ON Note: (1) The analog output corresponding to digital input has group delay (GD). (2) Analog outputs are floating (Hi-Z) in power down mode. (3) Click noise occurs at the edges (" ") of the internal timing of PMDA bit. This noise is output even if "0" data is input. (4) Each clock input (MCLK, BICK, LRCK) can be stopped in power down mode (PMDA bit = "0"). (5) Mute the analog output externally if the click noise (3) adversely affects system performance. Figure 28. Power-off/on Sequence Example 1 015002029-E-00 - 34 - 2015/02 [AK4432] Clock Synchronization The AK4432 has a reset function of internal counter that keeps the phase difference of the DAC outputs between the AK7738 less than 13/256fs. Clock synchronization function is enabled by SYNCE bit = "1" (default = "1"). SYNCE bit setting must be changed when data is all "0" (no data input). When SYNCE bit = "1" (default) MSB justified and 32-bit I2S compatible formats are available but LSB justified format is not available. (1) Synchronization with AK7738 In the use cases shown below (Figure 29), the phase difference of DAC output between the AK7738 and the AK4432 can be kept less than 13/256fs by clock synchronization function. Use Case1 Use Case2 Figure 29. Available Use Cases for Synchronization with the AK7738 Note: When synchronizing with the AK7738, both the AK7738 and the AK4432 should be set as BICK =64fs, 32-bit MSB justified (DIF2-0 bits = "110"). LRCK[kHz] Normal Double Quad BICK[fs] MCLK[fs] MCLK[MHz] Phase Diff. [1/MCLK] Phase Diff. [s] Phase Diff. [deg] *1 48 64 256 12.288 7 ~ 13 0.57 ~ 1.06 4.1 ~ 7.6 96 64 256 24.576 9 ~ 12 0.37 ~ 0.49 2.6 ~ 3.5 192 64 128 24.576 7 ~ 10 0.29 ~ 0.41 2.1 ~ 2.9 Table 14. Phase Difference Relationship between the AK7738 and the AK4432 Note 16. Phase difference to a 20 kHz signal. 015002029-E-00 - 35 - 2015/02 [AK4432] Parallel Mode The AK4432 will be in parallel control mode (pin control mode) by bringing the PS pin= "H". In parallel mode, functions that need to set by registers are not available except three followings that can be used by pin settings. Functions that cannot be controlled by pin settings are operated in their default register settings. Audio Interface The DIF pin controls audio interface mode (Table 15). Available modes are 32-bit MSB justified (DIF pin = "L") and 32-bit I2C compatible (DIF pin = "H"). DIF pin Mode L Mode6 (Table 7) H Mode7 (Table 7) Table 15. Audio Interface Forma (Parallel Mode) Soft Mute Soft mute function can be used by controlling SUMTE signal by the SMUTE pin. (Figure 26) System Clock Auto setting mode becomes available by setting the ACKS pin to "H". The AK4432 is in Manual setting mode when the ACKS pin is "L". In this case, the sampling speed is fixed to Normal speed mode (Table 16). Input MCKI frequency shown in Table 16. ACKS pin L H H H 015002029-E-00 MCKI Sampling Speed Mode 768fs, 512fs, 384fs, 256fs Normal Speed Mode 512fs, 768fs Normal Speed Mode 256fs, 384fs Double Speed Mode 128fs, 192fs Quad Speed Mode Table 16. System Clock (Parallel Mode) - 36 - 2015/02 [AK4432] Serial Control Interface The AK4432 corresponds to both 3-wire serial and I2C bus interfaces. After releasing power-down mode, the AK4432 is in I2C interface mode. 3-wire serial mode will be enabled by writing a dummy command four times continuously following power-up when the CSN pin = "H". (Figure 30) Input "0cDE 0xADDA 0x7A" to the CDTI pin during the CSN pin = "L" is defined as a dummy command. The data format is MSB first. (Figure 30) CSN CCLK CDTI Dummy Command Dummy Command Dummy Command Dummy Command CSN CCLK CDTI don'tcare (L/H) 0xDE (8bit) 0x7A(8bit) 0xADDA (16bit) don'tcare (L/H) Figure 30. Dummy Comand Format 015002029-E-00 - 37 - 2015/02 [AK4432] (1) 3-wire Serial Control Mode (I2C pin = "L") The internal registers may be written through the 3-wire P interface pins (CSN, CCLK and CDTI). The data on this interface consists of a Command code (8bits, the most significant bit is R/W flag and fixed to "1" (write only) and other 7bits are fixed to "1000000"), Register address (MSB first, 16bits) and Control data (MSB first, 8bits) (Figure 31). Address and data are clocked in on the rising edge of CCLK and data is clocked out on the falling edge. For write operations, data is latched on the 8th rising edge of CCLK. The clock speed of CCLK is 7MHz (max). The AK4432 can perform more than one byte write operation per sequence (Figure 35). The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 16-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 05H prior to generating a stop condition, the address counter will "roll over" to 00H and the previous data will be overwritten. Internal registers are initialized by setting the PDN pin = "L". CSN CCLK don'tcare CDTI (L/H) Command Code (8bit) don'tcare (L/H) Control Data (8bit) Register Address (16bit) Figure 31. Control I/F Timing R/W 1 0 0 0 0 0 0 R/W: READ/WRITE (Fixed to "1", Write only) Figure 32. Command Code 0 0 0 0 0 0 0 0 0 0 0 0 0 A2 A1 A0 Figure 33. Register Address D7 D6 D5 D4 D3 D2 D1 D0 Figure 34. Control Data * The AK4432 does not support data read in 3-wire serial mode. * Control register write is not possible when the PDN pin = "L". * Data will not be written if there are 17times or more CCLK rising edges, or 15times or less CCLK rising edges while the CSN pin is "L". CSN CCLK CDTI don't care (L/H) Command Address DATA DATA DATA DATA DATA don't care (L/H) Figure 35. Continuous Write of Control Data 015002029-E-00 - 38 - 2015/02 [AK4432] (2) I2C-bus Control Mode The I2C-bus in the AK4432 can run in fast-mode (max: 400kHz) and fast-mode plus (max: 1MHz) (Table 17). I2C-bus mode should be fixed to either mode during operation. The PDN pin must be "L" when changing the I2C-bus mode. SMUTE/CSN/I2CFIL pin Bus Mode L Fast Mode H Fast Mode Plus Table 17. I2C-Bus Mode Setting (1) WRITE Operation Figure 36 shows the data transfer sequence of the I2C-bus mode. All commands are preceded by a START condition. A High to Low transition on the SDA line while SCL is HIGH indicates a START condition (Figure 44). After a START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit (R/W). The most significant seven bits of the slave address are fixed as "0011001" (Figure 37). If the slave address matches that of the AK4432, the AK4432 generates an acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 45). R/W bit = "1" indicates that the read operation is to be executed. "0" indicates that the write operation is to be executed. The second byte is an 8-bit command code. The format is MSB first, and it is fixed to "11000000" (Figure 38). The third byte and fourth byte consist of the control register address of the AK4432. The format is MSB first, the third byte is fixed to zeros and the most significant 5bits of the fourth byte are fixed to zeros (Figure 39, Figure 40). The data after the fifth byte contains control data. The format is MSB first, 8bits (Figure 41). The AK4432 generates an acknowledge after each byte is received. Data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines STOP condition (Figure 44). The AK4432 can perform more than one byte write operation per sequence. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 16-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds "05H" prior to generating a stop condition, the address counter will "roll over" to "00H" and the previous data will be overwritten. The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only be changed when the clock signal on the SCL line is LOW (Figure 46) except for the START and STOP conditions. S T A R T S T O P R/W="0" Slave SDA S Address Command Code A C K Address(1) Address(0) A C K A C K Data(0) A C K A C K P Data(n) Data(1) A C K A C K A C K Figure 36. Data Transfer Sequence in I2C-bus Mode 015002029-E-00 - 39 - 2015/02 [AK4432] 0 0 1 1 0 0 1 R/W 0 0 0 0 0 A2 A1 A0 D1 D0 R/W: READ/WRITE ("0": Write, "1": Read) Figure 37. The First Byte 1 1 0 0 0 0 Figure 38. The Second Byte 0 0 0 0 0 Figure 39. The Third Byte 0 0 0 0 0 Figure 40. The Fourth Byte D7 D6 D5 D4 D3 D2 Figure 41. Byte Structure of The Fifth and Succeeding Bytes 015002029-E-00 - 40 - 2015/02 [AK4432] (2) READ Operation In the AK4432, when a "write- slave-address assignment" (R/W bit = "0") is received at the first byte(Figure 37), the command code "01000000"(Figure 44) at the second byte and the address at the third and fourth bytes are received (Figure 39, Figure 40). When the fourth byte is received and an acknowledgement is transmitted, the read command waits for the next restart condition. After receiving the restart condition, if a "read slave-address assignment" is received at the first byte, data is transferred at the second and succeeding bytes. When the master does not generate an acknowledge but generates a stop condition instead, the AK4432 ceases transmission. S T A R T R E S T A R T R/W="0" Slave SDA S Address Command Code A C K Address(0) A C K A C K Slave S Address Address(1) S T O P R/W="1" Data(0) A C K A C K MA AC SK T E R MA AC SK T E R P Data(n) Data(1) MA AC SK T E R MN A A S C T K E R Figure 42. Random Address Read 0 1 0 0 0 0 0 0 Figure 43. The Second Byte (READ) 015002029-E-00 - 41 - 2015/02 [AK4432] SDA SCL S P start condition stop condition Figure 44. START and STOP Conditions DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 2 1 8 9 S clock pulse for acknowledgement START CONDITION Figure 45. Acknowledge on the I2C-Bus SDA SCL data line stable; data valid change of data allowed Figure 46. Bit Transfer on the I2C-Bus 015002029-E-00 - 42 - 2015/02 [AK4432] Register Map Addr 00H 01H 02H 03H 04H 05H Register Name Power Management Control 1 Data interface Control 2 AOUTL Volume Control AOUTR Volume Control D7 0 0 0 0 ATTL7 ATTR7 D6 0 0 SDS1 0 ATTL6 ATTR6 D5 0 0 SDS0 0 ATTL5 ATTR5 D4 0 0 TDM1 DASL ATTL4 ATTR4 D3 0 0 TDM0 DASD ATTL3 ATTR3 D2 0 DFS1 DIF2 ATS ATTL2 ATTR2 D1 D0 PMDA 0 DFS0 ACKS DIF1 DIF0 SMUTE SYNCE ATTL1 ATTL0 ATTR1 ATTR0 Note 17. Data must not be written into addresses from 06H to FFH. Note 18. The bit defined as 0 must contain a "0" value. Note 19. When the PDN pin goes to "L", the registers are initialized to their default values. 015002029-E-00 - 43 - 2015/02 [AK4432] Register Definitions Addr 00H Register Name Power Management R/W Default D7 0 R/W 0 D6 0 R/W 0 D5 0 R/W 0 D4 0 R/W 0 D3 0 R/W 0 D2 0 R/W 0 D1 PMDA R/W 1 D0 0 R/W 0 D1 DFS0 R/W 0 D0 ACKS R/W 0 RMDA: DAC Power Management 0: Power Down 1: Normal Operation Addr 01H Register Name Control 1 R/W Default D7 0 R/W 0 D6 0 R/W 0 D5 0 R/W 0 D4 0 R/W 0 D3 0 R/W 0 D2 DFS1 R/W 0 ACKS: Master Clock Frequency Auto Setting Mode Enable 0: Disable, Manual Setting Mode 1: Enable, Auto Setting Mode When ACKS bit = "1", the MCLK frequency is detected automatically. In this case, the setting of DFS bits is ignored. When this bit is "0", DFS1-0 bits set the sampling speed mode and MCLK frequency for each mode is detected automatically. DFS1-0: Sampling Speed Mode (Table 1) The setting of DFS bits is ignored at ACKS bit ="1". Addr 02H Register Name Data interface R/W Default D7 0 R/W 0 D6 SDS1 R/W 0 D5 SDS0 R/W 0 D4 TDM1 R/W 0 D3 TDM0 R/W 0 D2 DIF2 R/W 1 D1 DIF1 R/W 1 D0 DIF0 R/W 0 DIF2-0: Audio Interface Mode Select (Table 7) Default: "110" (32-bit MSB justified) TDM1-0: TDM Format Select Default: "00" (Stereo Mode) Mode TDM1 TDM0 Sampling Speed Mode 0 0 0 Stereo mode (Normal, Double, Quad Speed Mode) 1 0 1 TDM128 mode (Normal, Double, Quad Speed Mode) 2 1 0 TDM256 mode (Double, Quad Speed Mode) 3 1 1 TDM256 mode (Double, Quad Speed Mode) SDS1-0: DAC Data Select Default: "00" (Stereo Mode) 0: Normal Operation 1: Output Other Slot Data (Table 8) 015002029-E-00 - 44 - 2015/02 [AK4432] Addr 03H Register Name Control 2 R/W Default D7 0 R/W 0 D6 0 R/W 0 D5 0 R/W 0 D4 DASL R/W 0 D3 DASD R/W 0 D2 ATS R/W 0 D1 D0 SMUTE SYNCE R/W R/W 0 1 SYNCE: SYNC Mode Enable 0: OFF 1: ON (default) SMUTE: Soft Mute Enable 0: Normal Operation 1: All DAC outputs are soft muted ATS: Transition Time Setting of Digital Attenuator (Table 10) Default: "00" DASD: Digital Filter Setting for DAC Block 0: Sharp roll off filter or Slow roll off filter (default) 1: Short delay Sharp roll off filter or Short delay Slow roll off filter DASL: Slow Roll-off Filter Enable for DAC Block 0: Sharp Roll-off Filter (default) 1: Slow Roll-off Filter DASD bit 0 0 1 1 Addr 04H 05H DASL bit Mode 0 Sharp roll-off filter 1 Slow roll-off filter 0 Short delay Sharp roll-off filter 1 Short delay Slow roll-off filter Table 18 Digital Filter setting for DAC Block Register Name AOUTL Volume Control AOUTR Volume Control R/W Default D7 D6 D5 D4 D3 (default) D2 D1 D0 ATTL7 ATTR7 ATTL6 ATTR6 ATTL5 ATTR5 ATTL4 ATTR4 ATTL3 ATTR3 ATTL2 ATTR2 ATTL1 ATTR1 ATTL0 ATTR0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 1 R/W 0 R/W 0 R/W 0 ATTL7-0: DAC Lch Attenuation Level Default:18(0dB) ATTR7-0: DAC Rch Attenuation Level Default:18(0dB) 015002029-E-00 - 45 - 2015/02 [AK4432] 13. Recommended External Circuits 1 MCLK LDOO 16 2 BICK LVDD 15 1.0u Audio Controller 3 SDTI 4 LRCK 5 PDN 6 0.1u AVDD 14 VSS 13 VCOM 12 SMUTE/CSN/I2CFIL AOUTL 11 7 ACKS/CCLK/SCL AOUTR 10 8 DIF/CDTI/SDA PS 9 0.1u P AK4432 + + 10u 10u LDO Supply 3.0 to 3.6V Analog Supply 3.0 to 3.6V 2.2u 1.0u Lch Out MUTE Rch Out 1.0u Connect to AVDD or VSS Digital Ground Analog Ground Figure 47. System Connection Diagram (P/S pin = "H") 1 MCLK LDOO 16 2 BICK LVDD 15 3 SDTI AVDD 14 4 LRCK VSS 13 1.0u Audio Controller 0.1u 0.1u AK4432 + + 10u 10u LDO Supply 3.0 to 3.6V Analog Supply 3.0 to 3.6V 2.2u 5 PDN VCOM 12 6 SMUTE/CSN/I2CFIL AOUTL 11 7 ACKS/CCLK/SCL AOUTR 10 8 DIF/CDTI/SDA PS 9 1.0u P Lch Out MUTE Rch Out 1.0u Digital Ground Analog Ground Figure 48. System Connection Diagram (P/S pin = "L") 015002029-E-00 - 46 - 2015/02 [AK4432] 1. Grounding and Power Supply Decoupling The AK4432 requires careful attention to power supply and grounding arrangements. VSS must be connected to the same analog ground plane. Decoupling capacitors should be as near to the AK4432 as possible. 2. Voltage Reference VCOM is a signal ground of this chip and output the voltage AVDDx1/2. A 2.2F (50% includes temperature characteristics) ceramic capacitor attached between the VCOM pin and VSS eliminates the effects of high frequency noise. This capacitor should be as close to the pin as possible. No load current may be drawn from the VCOM pin. All signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the AK4432. The LDOO pin is a power supply for internal digital circuit and outputs 1.2V. A 1F (50% includes temperature characteristics) ceramic capacitor attached between the LDOO pin and VSS eliminates the effects of high frequency noise. This capacitor should be connected as close as possible to the pin. No load current may be drawn from the LDOO pin. 3. Analog Output The output signal range is nominally 0.86 x AVDD Vpp (typ.) centered around the VCOM voltage. The DAC input data format is 2's complement. The output voltage is a positive full scale for 7FFFFFFFH(@32bit) and a negative full scale for 80000000H(@32bit). The ideal output is VCOM voltage for 00000000H(@32bit). The internal analog filters remove most of the noise generated by the delta-sigma modulator of DAC beyond the audio passband, in single-ended input mode. DC offsets on analog outputs are eliminated by AC coupling since DAC outputs have DC offsets of a few mV. 015002029-E-00 - 47 - 2015/02 [AK4432] 14. Package Outline Dimensions 16-pin TSSOP (Unit: mm) Material & Lead Finish Package molding compound: Epoxy, Halogen (Br and Cl) free Lead frame material: Cu Lead frame surface treatment: Solder (Pb free) plate 015002029-E-00 - 48 - 2015/02 [AK4432] Marking AKM 4432 XXYYY 1) Pin #1 indication 2) Date Code: XXXX (4 digits) 3) Marking Code: 4432 15. Revision History Date (Y/M/D) 15/02/18 015002029-E-00 Revision 00 Reason Page First Edition Contents - 49 - 2015/02 [AK4432] IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation ("AKM") reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document ("Product"), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products. 1. All information included in this document are provided only to illustrate the operation and application examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of AKM or any third party with respect to the information in this document. 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