1
LT1189
Low Power
Video Difference Amplifier
Closed-Loop Gain vs FrequencyCable Sense Amplifier for Loop Through Connections
with DC Adjust
FREQUENCY (MHz)
0
VOLTAGE GAIN (dB)
10
20
30
40
0.1 10 100
LT1189 • TA02
1
V
S
= ±5V
R
L
= 1k
50
LT1189 • TA01
CABLE
V
DC
5V
7
6
LT1189
–5V
4
+
+
3
1
–
–
2
8
909Ω
V
OUT
V
IN
100Ω
D
U
ESCRIPTIO
S
FEATURE
The LT1189 is a difference amplifier optimized for opera-
tion on ±5V, or a single 5V supply, and gain ≥10. This
versatile amplifier features uncommitted high input im-
pedance (+) and (–) inputs, and can be used in differential
or single-ended configurations. Additionally, a second set
of inputs give gain adjustment and DC control to the
difference amplifier.
The LT1189’s high slew rate, 220V/µs, wide bandwidth,
35MHz, and ±20mA output current require only 13mA of
supply current. The shutdown feature reduces the power
dissipation to a mere 15mW, and allows multiple amplifi-
ers to drive the same cable.
The LT1189 is a low power, gain of 10 stable version of the
popular LT1193, and is available in 8-pin miniDIPs and SO
packages. For lower gain applications see the LT1187
data sheet.
■
Differential or Single-Ended Gain Block (Adjustable)
■
–3dB Bandwidth, A
V
= ±10 35MHz
■
Slew Rate 220V/µs
■
Low Supply Current 13mA
■
Output Current ±20mA
■
CMRR at 10MHz 48dB
■
LT1193 Pin Out
■
Low Cost
■
Single 5V Operation
■
Drives Cables Directly
■
Output Shutdown
U
S
A
O
PPLICATI
■
Line Receivers
■
Video Signal Processing
■
Cable Drivers
■
Tape and Disc Drive Systems
U
A
O
PPLICATITYPICAL
LT1189
2
A
U
G
W
A
W
U
W
ARBSOLUTEXI T
I
S
WU
U
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
Total Supply Voltage (V
+
to V
–
) ............................. 18V
Differential Input Voltage ........................................ ±6V
Input Voltage .......................................................... ±V
S
Output Short Circuit Duration (Note 1) ........ Continuous
Operating Temperature Range
LT1189M..................................... – 55°C to 150°C
LT1189C............................................. 0°C to 70°C
Junction Temperature (Note 2)
Plastic Package (CN8,CS8) ......................... 150°C
Ceramic Package (CJ8,MJ8) ....................... 175°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec.)................ 300°C
S8 PART MARKING
LT1189MJ8
LT1189CJ8
LT1189CN8
LT1189CS8
LT1189M/C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
OS
Input Offset Voltage Either Input, (Note 4) 1.0 3.0 mV
SOIC Package 1.0 4.0 mV
I
OS
Input Offset Current Either Input 0.2 1.0 µA
I
B
Input Bias Current Either Input ±0.5 ±2.0 µA
e
n
Input Noise Voltage f
O
= 10kHz 30 nV/√Hz
i
n
Input Noise Current f
O
= 10kHz 1.25 pA/√Hz
R
IN
Input Resistance Differential 30 kΩ
C
IN
Input Capacitance Either Input 2.0 pF
V
IN
LIM
Input Voltage Limit (Note 5) ±170 mV
Input Voltage Range –2.5 3.5 V
CMRR Common-Mode Rejection Ratio V
CM
= –2.5V to 3.5V 80 105 dB
PSRR Power Supply Rejection Ratio V
S
= ±2.375V to ±8V 75 90 dB
V
OUT
Output Voltage Swing V
S
= ±5V, R
L
= 1k, A
V
= 50 ±3.8 ±4.0 V
V
S
= ±8V, R
L
= 1k, A
V
= 50 ±6.7 ±7.0
V
S
= ±8V, R
L
= 300Ω, A
V
= 50, (Note 3) ±6.4 ±6.8
G
E
Gain Error V
O
= ±1.0V, A
V
= 10 1.0 3.5 %
SR Slew Rate (Note 6, 10) 150 220 V/µs
FPBW Full Power Bandwidth V
O
= 2V
P-P
, (Note 7) 35 MHz
BW Small Signal Bandwidth A
V
= 10 35 MHz
t
r
, t
f
Rise Time, Fall Time A
V
= 50, V
O
= ±1.5V, 20% to 80% (Note 10) 35 50 75 ns
t
PD
Propagation Delay R
L
= 1k, V
O
= ±125mV, 50% to 50% 12 ns
Overshoot V
O
= ±50mV 10 %
t
s
Settling Time 3V Step, 0.1%, (Note 8) 1 µs
Diff A
V
Differential Gain R
L
= 1k, A
V
= 10, (Note 9) 0.6 %
Diff Ph Differential Phase R
L
= 1k, A
V
= 10, (Note 9) 0.75 DEG
P-P
I
S
Supply Current 13 16 mA
Shutdown Supply Current Pin 5 at V
–
0.8 1.5 mA
VS = ±5V, VREF = 0V, RFB1 = 900Ω from pins 6 to 8, RFB2 = 100Ω from pin 8 to ground, RL = RFB1 + RFB2 = 1k, CL ≤ 10pF, pin 5 open.
ELECTRICAL C CHARA TERISTICS
TA = 25°C, (Note 3)
5V
–
+
8
7
6
54
3
2
1+/REF
–IN
+IN
V S/D
OUT
+
V
–/FB
TOP VIEW
S8 PACKAGE
8-LEAD PLASTIC SOIC
–
N8 PACKAGE
8-LEAD PLASTIC DIP
J8 PACKAGE
8-LEAD HERMETIC DIP
LT1189 • POI01
1189
TJMAX = 175°C, θJA = 100°C/W (J8)
TJMAX = 150°C, θJA = 100°C/W (N8)
TJMAX = 150°C, θJA = 150°C/W (S8)
3
LT1189
VS = ±5V, VREF = 0V, RFB1 = 900Ω from pins 6 to 8, RFB2 = 100Ω from pin 8 to ground, RL = RFB1 + RFB2 = 1k, CL ≤ 10pF, pin 5 open.
LT1189M
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
OS
Input Offset Voltage Either Input, (Note 4) 1.0 7.5 mV
∆V
OS
/∆T Input V
OS
Drift 10 µV/°C
I
OS
Input Offset Current Either Input 0.2 1.5 µA
I
B
Input Bias Current Either Input ±0.5 ±3.5 µA
Input Voltage Range –2.5 3.5 V
CMRR Common-Mode Rejection Ratio V
CM
= –2.5V to 3.5V 80 105 dB
PSRR Power Supply Rejection Ratio V
S
= ±2.375V to ±8V 65 90 dB
V
OUT
Output Voltage Swing V
S
= ±5V, R
L
= 1k, A
V
= 50 ±3.7 ±4.0 V
V
S
= ±8V, R
L
= 1k, A
V
= 50 ±6.6 ±7.0
V
S
= ±8V, R
L
= 300Ω, A
V
= 50, (Note 3) ±6.4 ±6.6
G
E
Gain Error V
O
= ±1V, A
V
= 10, R
L
= 1k 1.0 6.0 %
I
S
Supply Current 13 17 mA
Shutdown Supply Current Pin 5 at V
–
, (Note 11) 0.8 1.5 mA
I
S/D
Shutdown Pin Current Pin 5 at V
–
525 µA
V
S
= ±5V, VREF = 0V, RFB1 = 900Ω from pins 6 to 8, RFB2 = 100Ω from pin 8 to ground, RL = RFB1 + RFB2 = 1k, CL ≤ 10pF, pin 5 open.
ELECTRICAL C CHARA TERISTICS
TA = 25°C, (Note 3)
5V
–
+
LT1189M/C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
S/D
Shutdown Pin Current Pin 5 at V
–
525 µA
t
on
Turn On Time Pin 5 from V
–
to Ground, R
L
= 1k 500 ns
t
off
Turn Off Time Pin 5 from Ground to V
–
, R
L
= 1k 600 ns
LT1189M/C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
OS
Input Offset Voltage Either Input, (Note 4) 1.0 3.0 mV
SOIC Package 1.0 5.0 mV
I
OS
Input Offset Current Either Input 0.2 1.0 µA
I
B
Input Bias Current Either Input ±0.5 ±2.0 µA
Input Voltage Range 2.0 3.5 V
CMRR Common-Mode Rejection Ratio V
CM
= 2.0V to 3.5V 80 100 dB
V
OUT
Output Voltage Swing R
L
= 300Ω to Ground V
OUT
High 3.6 4.0 V
(Note 3) V
OUT
Low 0.15 0.4
SR Slew Rate V
O
= 1.5V to 3.5V 175 V/µs
BW Small-Signal Bandwidth A
V
= 10 30 MHz
I
S
Supply Current 12 15 mA
Shutdown Supply Current Pin 5 at V
–
0.8 1.5 mA
I
S/D
Shutdown Pin Current Pin 5 at V
–
525 µA
V
S
+
= 5V, VS– = 0V, VREF = 2.5V, RFB1 = 900Ω from pins 6 to 8, RFB2 = 100Ω from pin 8 to VREF, RL = RFB1 + RFB2 = 1k, CL ≤ 10pF, pin 5
open.
5V
–
+
ELECTRICAL C CHARA TERISTICS
–55°C ≤ TA ≤ 125°C, (Note 3)
TA = 25°C, (Note 3)
5V
ELECTRICAL C CHARA TERISTICS
LT1189
4
LT1189C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
OS
Input Offset Voltage Either Input 1.0 3.0 mV
(Note 4) SOIC Package 1.0 6.0 mV
∆V
OS
/∆T Input V
OS
Drift 5.0 µV/°C
I
OS
Input Offset Current Either Input 0.2 1.5 µA
I
B
Input Bias Current Either Input ±0.5 ±3.5 µA
Input Voltage Range –2.5 3.5 V
CMRR Common-Mode Rejection Ratio V
CM
= –2.5V to 3.5V 80 105 dB
PSRR Power Supply Rejection Ratio V
S
= ±2.375V to ±8V 70 90 dB
V
OUT
Output Voltage Swing V
S
= ±5V, R
L
= 1k, A
V
= 50 ±3.7 ±4.0 V
V
S
= ±8V, R
L
= 1k, A
V
= 50 ±6.6 ±7.0
V
S
= ±8V, R
L
= 300Ω, A
V
= 50, (Note 3) ±6.4 ±6.6
G
E
Gain Error V
O
= ±1V, A
V
= 10, R
L
= 1k 1.0 3.5 %
I
S
Supply Current 13 17 mA
Shutdown Supply Current Pin 5 at V
–
, (Note 11) 0.8 1.5 mA
I
S/D
Shutdown Pin Current Pin 5 at V
–
525 µA
V
S
= ±5V, VREF = 0V, RFB1 = 900Ω from pins 6 to 8, RFB2 = 100Ω from pin 8 to ground, RL = RFB1 + RFB2 = 1k, CL ≤ 10pF, pin 5 open.
Note 1: A heat sink may be required to keep the junction temperature below
absolute maximum when the output is shorted continuously.
Note 2: T
J
is calculated from the ambient temperature T
A
and power dissipation
P
D
according to the following formulas:
LT1189MJ8, LT1189CJ8: T
J
= T
A
+ (P
D
× 100°C/W)
LT1189CN8: T
J
= T
A
+ (P
D
× 100°C/W)
LT1189CS8: T
J
= T
A
+ (P
D
× 150°C/W)
Note 3: When R
L
= 1k is specified, the load resistor is R
FB1
+ R
FB2
, but when
R
L
= 300Ω is specified, then an additional 430Ω is added to the output such
that (R
FB1
+ R
FB2
) in parallel with 430Ω is R
L
= 300Ω.
Note 4: V
OS
measured at the output (pin 6) is the contribution from both input
pair, and is input referred.
Note 5: V
IN
LIM
is the maximum voltage between –V
IN
and +V
IN
(pin 2 and
pin 3) for which the output can respond.
Note 6: Slew rate is measured between ±1V on the output, with a V
IN
step of
±0.5V, A
V
= 10 and R
L
= 1k.
Note 7: Full power bandwidth is calculated from the slew rate measurement:
FPBW = SR/2πVp.
Note 8: Settling time measurement techniques are shown in “Take the
Guesswork Out of Settling Time Measurements,” EDN, September 19, 1985.
Note 9: NTSC (3.58MHz).
Note 10: AC parameters are 100% tested on the ceramic and plastic DIP
packaged parts (J8 and N8 suffix) and are sample tested on every lot of the SO
packaged parts (S8 suffix).
Note 11: See Application section for shutdown at elevated temperatures. Do
not operate shutdown above T
J
> 125°C.
5V
–
+
ELECTRICAL C CHARA TERISTICS
0°C ≤ TA ≤ 70°C, (Note 3)
LT1189C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
OS
Input Offset Voltage, (Note 4) Either Input 1.0 3.0 mV
∆V
OS
/∆T Input V
OS
Drift 5.0 µV/°C
I
OS
Input Offset Current Either Input 0.2 1.5 µA
I
B
Input Bias Current Either Input ±0.5 ±3.5 µA
Input Voltage Range 2.0 3.5 V
CMRR Common-Mode Rejection Ratio V
CM
= 2.0V to 3.5V 80 100 dB
V
OUT
Output Voltage Swing R
L
= 300Ω to Ground V
OUT
High 3.5 4.0 V
(Note 3) V
OUT
Low 0.15 0.4
I
S
Supply Current 12 16 mA
Shutdown Supply Current Pin 5 at V, (Note 11) 0.8 1.5 mA
I
S/D
Shutdown Pin Current Pin 5 at V
–
525 µA
5V
VS+ = +5V, VS– = 0V, VREF = 2.5V, RFB1 = 900Ω from pins 6 to 8, RFB2 = 100Ω from pin 8 to VREF, RL = RFB1 + RFB2 = 1k, CL ≤ 10pF, pin 5
open.
0°C ≤ TA ≤ 70°C, (Note 3)
ELECTRICAL C CHARA TERISTICS
5
LT1189
CCHARA TERISTICS
UW
AT
Y
P
I
CALPER
F
O
RC
E
Input Bias Current vs Common-Mode Voltage vs
Common-Mode Voltage Input Bias Current vs Temperature Temperature
COMMON-MODE VOLTAGE (V)
–5
–0.5
INPUT BIAS CURRENT ( A)
0
0.5
1.5
2.5
–3 0 2 4
LT1189 • TPC01
µ
–4 –2 1 3
125°C
–55°C
25°C
V
S
= ±5V
–1 5
1.0
2.0
3.0
TEMPERATURE (°C)
–50
–400
INPUT BIAS CURRENT (nA)
–300
–200
–100
0
100
0 25 75 125
LT1189 • TPC02
–25 50 100
+I
B
–I
B
I
OS
V
S
= ±5V
Equivalent Input Noise Voltage vs Equivalent Input Noise Current vs
Frequency Frequency Supply Current vs Supply Voltage
FREQUENCY (Hz)
EQUIVALENT INPUT NOISE VOLTAGE (nV/ Hz)
120
160
10 1k 10k 100k
LT1189 • TPC04
0100
80
√
V = ±5V
T = 25°C
R = 0
S
A
S
Ω
40
200
60
140
100
180
20
FREQUENCY (Hz)
2
EQUIVALENT INPUT NOISE CURRENT (pA/ Hz)
12
10 1k 10k 100k
LT1189 • TPC05
0100
6
√
4
8
10
V
S
= ±5V
T
A
= 25°C
R
S
= 100k
±SUPPLY VOLTAGE (V)
0
8
SUPPLY CURRENT (mA)
12
14
16
246 10
LT1189 • TPC06
8
–55°C
25°C
125°C
10
Shutdown Supply Current vs
Temperature Gain Error vs Temperature Open-Loop Gain vs Temperature
TEMPERATURE (°C)
–50
0
SHUTDOWN SUPPLY CURRENT (mA)
2.0
3.0
4.0
5.0
6.0
0 25 75 125
LT1189 • TPC07
1.0
–25 50 100
V = ±5V
S
VS/D = –VEE + 0.6V
VS/D = –VEE + 0.4V
VS/D = –VEE
VS/D = –VEE + 0.2V
TEMPERATURE (°C)
GAIN ERROR (%)
LT1189 • TPC08
–50
–2.4
–1.6
–1.2
0 50 100 125
–2.0
–25 25 75
–1.4
–1.8
–2.2
V
S
= ±5V
V
OUT
= ±1V
A
V
= 10
R
L
= 1k
0
OPEN-LOOP GAIN (kV/V)
4
8
12
16
TEMPERATURE (°C)
–50 0 50 100 125
LT1189 • TPC09
–25 25 75
RL = 1k
RL = 500Ω
VS = ±5V
VO = ±3V
14
10
6
2
TEMPERATURE (°C)
COMMON-MODE RANGE (V)
2.0
V
+
–50 25 75 125
LT1189 • TPC03
V
–
0
1.0
–1.0
–2.0
–0.5
–1.5
1.5
0.5
–25 50 100
V
+
= 1.8V TO 9V
V
+
= –1.8V TO –9V
LT1189
6
CCHARA TERISTICS
UW
AT
Y
P
I
CALPER
F
O
RC
E
FREQUENCY (Hz)
0
VOLTAGE GAIN (dB)
20
60
80
100
100k
LT1189 • TPC11
–20 1M 10M 100M
40
0
PHASE MARGIN (DEG)
20
60
80
100
–20
40
GAIN
PHASE
V
S
= ±5V
T
A
= 25°C
R
L
= 1k
Gain Bandwidth Product and Common-Mode Rejection Ratio
Phase Margin vs Temperature Output Impedance vs Frequency vs Frequency
TEMPERATURE (°C)
–50
100
GAIN BANDWIDTH PRODUCT (MHz)
200
250
0 50 100 125
LT1189 • TPC13
150
–25 25 75
PHASE MARGIN (DEG)
55
75
85
65
V = ±5V
R = 1k
A
V
= 20dB
S
L
GAIN BANDWIDTH
PRODUCT
PHASE MARGIN
FREQUENCY (Hz)
COMMON-MODE REJECTION RATIO (dB)
50
60
70
80
100k 10M 100M
LT1189 • TPC15
30 1M
40
90
V
S
= ±5V
T
A
= 25°C
R
L
= 1k
±SUPPLY VOLTAGE (V)
0
100
GAIN BANDWIDTH PRODUCT (MHz)
150
200
250
24 810
LT1189 • TPC12
6
T
A
= 25°C
T
A
= 125°C
T
A
= –55°C
A
V
= 20dB
Open-Loop Voltage Gain vs Gain Bandwidth Product vs
Gain, Phase vs Frequency Load Resistance Supply Voltage
FREQUENCY (Hz)
0.1
OUTPUT IMPEDANCE ( )
1
10
100
1k
LT1189 • TPC14
10k 100k 1M 10M 100M
Ω
V
S
= ±5V
T
A
= 25°C
A
V
= 10
Power Supply Rejection Ratio vs Output Short Circuit Current vs
Frequency Temperature ± Output Swing vs Supply Voltage
FREQUENCY (Hz)
0
POWER SUPPLY REJECTION RATIO (dB)
20
40
60
80
1k 100k 10M 100M
LT1189 • TPC16
–20 10k 1M
+PSRR
–PSRR
VS = ±5V
TA = 25°C
VRIPPLE = ±300mV
TEMPERATURE (°C)
–50
30
OUTPUT SHORT CIRCUIT CURRENT (mA)
34
36
0 25 75 125
LT1189 • TPC17
–25 50 100
VS = ±5V
32
31
33
35
±SUPPLY VOLTAGE (V)
OUTPUT SATURATION VOLTAGE (V)
V
+
LT1189 • TPC18
V
–
0.3
–0.8
–0.7
0.2
0246 108
–0.9
–1.0
0.4
0.5
0.1
–1.1 –55°C
125°C
25°C
–55°C
125°C
25°C
R
L
= 1k
±1.8V ≤ V
S
≤ ±9V
LOAD RESISTANCE (Ω)
100
0
OPEN-LOOP VOLTAGE GAIN (kV/V)
10
20
30
1k 10k
LT1189• TPC10
VS = ±5V
VO = ±3V
TA = 25°C
7
LT1189
CCHARA TERISTICS
UW
AT
Y
P
I
CALPER
F
O
RC
E
SETTLING TIME (ns)
100
–4
OUTPUT VOLTAGE STEP (V)
–2
2
4
140 340
LT1189 • TPC21
180 220 260 300
V
S
= ±5V
T
A
= 25°C
R
L
= 1k
0
10mV
10mV
Harmonic Distortion vs
Output Level
Output Voltage Swing vs
Load Resistance
Output Voltage Step vs
Settling Time, AV = 10
Slew Rate vs Temperature
TEMPERATURE (°C)
SLEW RATE (V/ s)
LT1189 • TPC20
µ
–50
200
250
300
–25 0 50 7525 100 125
VS = ±5V
RL = 1k
VO = ±2V
AV = 10
–SLEW RATE
+SLEW RATE
OUTPUT VOLTAGE (V
P-P
)
0
DISTORTION (dBc)
1234
LT1189 • TPC22
0
–10
–20
–30
–40
–50
–60
V
S
= ±5V
T
A
= 25°C
R
L
= 1k
f = 10MHz
A
V
= 10 HD
3
HD
2
Large-Signal Transient Reponse
AV = 10, RL = 1k, +SR = 223V/µs, –SR = 232V/µs
LT1189 • TPC23
LOAD RESISTANCE (Ω)
10
–5
OUTPUT VOLTAGE SWING (V)
–3
1
5
100 1000
LT1189 • TPC19
VS = ±5V
3
–1
TA = –55°C
TA = 25°C
TA = 25°C
TA = –55°C
TA = 25°C
TA = 25°C
AV = 10, RL = 1k, tr = 9.40ns
LT1189 • TPC24
Small-Signal Transient Reponse
LT1189
8
The primary use of the LT1189 is in converting high speed
differential signals to a single-ended output. The LT1189
video difference amplifier has two uncommitted high input
impedance (+) and (–) inputs. The amplifier has another
set of inputs which can be used for reference and feed-
back. Additionally, this set of inputs give gain adjust, and
DC control to the differential amplifier. The voltage gain of
the LT1189 is set like a conventional operational amplifier.
Feedback is applied to pin 8, and it is optimized for gains
of 10 or greater. The amplifier can be operated single-
ended by connecting either the (+) or (–) inputs to the
+/REF (pin 1). The voltage gain is set by the resistors:
(R
FB
+ R
G
)/R
G
.
Like the single-ended case, the differential voltage gain is
set by the external resistors: (R
FB
+ R
G
)/R
G
. The maximum
input differential signal for which the output will respond
is approximately ±170mV.
Power Supply Bypassing
The LT1189 is quite tolerant of power supply bypassing.
In some applications a 0.1µF ceramic disc capacitor
placed 1/2 inch from the amplifier is all that is required. In
applications requiring good settling time, it is important to
use multiple bypass capacitors. A 0.1µF ceramic disc in
parallel with a 4.7µF tantalum is recommended.
Calculating the Output Offset Voltage
Both input stages contribute to the output offset voltage at
pin 6. The feedback correction forces balance in the input
stages by introducing an Input V
OS
at pin 8. The complete
expression for the output offset voltage is:
V
OUT
= (V
OS
+ I
OS
(R
S
) + I
B
(R
REF
)) × (R
FB
+ R
G
)/R
G
+ I
B
(R
FB
)
R
S
represents the input source resistance, typically 75Ω,
and R
REF
represents finite source impedance from the
DC reference voltage, for V
REF
grounded, R
REF
= 0Ω the
I
OS
is normally a small contributor and the expression
simplifies to:
V
OUT
= V
OS
(R
FB
+ R
G
)/R
G
+ I
B
(R
FB
)
If R
FB
is limited to 1k, the last term of the equation
contributes only 2mV since I
B
is less than 2µA.
Figure 1. Simplified Input Stage Schematic
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S
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PPLICATI
WU
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I FOR ATIO
V+
7
6
LT1189
V–
4
1
8
OUT
V
+
3
–
2
IN
V
S/D
5
AV= + RFB +
RFB
7
6
LT1189
4
1
8
OUT
V
+
3
–
2
IN DIFF
V
S/D
5
RFB
LT1189 • AI01
7
6
LT1189
4
+/REF
1
–/FB
8
OUT
V
+
3
–
2
S/D
5
VO=RFB +
RFB
7
6
LT1189
4
1
8
OUT
V
+
3
–
2
IN
V
S/D
5
AV= – RFB +
RFB
IN
V
IN
V
(
(
VIN DIFF RFB
(
(
VIN
+/REF
–/FB
+/REF
–/FB
+/REF
–/FB
RG
RGRG
VO= (V RFB +
IN DIFF + VIN)RG
RG
RG
IN DIFF
V
RG
RG
RG
RG
–
RGRG
RG
V+
V–
V+
V–
V+
V–
LT1189 • AI02
+1REF
RREF
RG
8
RFB
6
350µA
Q3 Q4
+
3
RS
345µA
Q1 Q2
–
2
RS
7V
+
R
E
300
RE
300
4V
–
9
LT1189
Instrumentation Amplifier Rejects High Voltage
Instrumentation amplifiers are often used to process
slowly varying outputs from transducers. With the LT1189
it is easy to make an instrumentation amplifier that can
respond to rapidly varying signals. Attenuation resistors
in front of the LT1189 allow very large common-mode
signals to be rejected while maintaining good frequency
response. The input common-mode and differential-mode
signals are reduced by 100:1, while the closed-loop gain
is set to be 100, thereby maintaining unity-gain input to
output. The unique topology allows for frequency re-
sponse boost by adding 150pF to pin 8 as shown.
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PPLICATI
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3.5MHz Instrumentation Amplifier Rejects 120VP-P
LT1189 • AI03
–
+
100*
100*
V
CM
120V
P-P
V
IN
10k*
10k*
100Ω
150pF
REF
FB 4
7
5V
–5V
LT1189 6
2
1
3
8
* 0.1% RESISTORS
WORST CASE CMRR = 48dB
10k
Output of Instrumentation Amplifier with 1MHz Square Wave
Riding on 120VP-P at the Input
LT1189 • AI04
High Voltage Instrumentation Amplifier Response
Operating with Low Closed-Loop Gain
The LT1189 has been optimized for closed-loop gains of
10 or greater. The amplifier can be operated at much lower
closed-loop gains with the aid of a capacitor C
FB
across
the feedback resistor, (feedback zero). This capacitor
lowers the closed-loop 3dB bandwidth. The bandwidth
cannot be made arbitrarily low because C
FB
is a short at
high frequency and the amplifier will appear configured
unity-gain. As an approximate guideline, make BW × A
VCL
= 200MHz. This expression expands to:
A
RC MHz
VCL
FB FB
2200
π
()()
=
or:
CA
MHz R
FB VCL
FB
=
()()()
200 2π
The effect of the feedback zero on the transient and
frequency response is shown for A
V
= 4.
FREQUENCY (Hz)
VOLTAGE GAIN (dB)
20
LT1189 • AI05
100M10M1M100k
0
–20
–60
–40 COMMON-MODE RESPONSE
DIFFERENTIAL-MODE RESPONSE
LT1189
10
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PPLICATI
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Small-Signal Transient Response
Closed-Loop Voltage Gain vs Frequency
AV = 4, RFB = 910Ω, RG = 300ΩLT1189 • AI07
AV = 4, RFB = 910Ω, RG = 300Ω, CFB = 5pF
LT1189 • AI08
Small-Signal Transient Response
Reducing the Closed-Loop Bandwidth
Although it is possible to reduce the closed-loop band-
width by using a feedback zero, instability can occur if the
bandwidth is made too low. An alternate technique is to do
differential filtering at the input of the amplifier. This
technique filters the differential input signal, and the
differential noise, but does not filter common-mode noise.
Common-mode noise is rejected by the LT1189’s CMRR.
10MHz Bandwidth Limited Amplifier
Using the Shutdown Feature
The LT1189 has a unique feature that allows the amplifier
to be shutdown for conserving power, or for multiplexing
several amplifiers onto a common cable. The amplifier will
shutdown by taking pin 5 to V
–
. In shutdown, the amplifier
dissipates 15mW while maintaining a true high impedance
output state of about 20kΩ in parallel with the feedback
resistors. For MUX applications, the amplifiers may be
configured inverting, non-inverting, or differential. When
the output is loaded with as little as 1kΩ from the amplifier’s
feedback resistors, the amplifier shuts off in 600ns. This
shutoff can be under the control of HC CMOS operating
between 0V and –5V.
FREQUENCY (Hz)
CLOSED-LOOP VOLTAGE GAIN (dB)
30
LT1189 • AI06
100M10M1M100k
20
10
–20
–10
0
V
S
= ±5V
T
A
= 25°C
A
V
= 4
R
FB
= 900Ω
R
G
= 300Ω
C
FB
= 5pF
C
FB
= 0pF
LT1189 • AI09
5V
7
6
LT1189
–5V
4
+
REF
3
1
–
FB
2
8
VOUT
909Ω
R1
110Ω
R2
110Ω
C1
68pF
AV = 10
f–3dB =2π(R1 + R2)C1
1
VOUT =FILTER
SIG + eND+CMR
eNCM
eND
SIG
eNCM
100Ω
11
LT1189
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A
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PPLICATI
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I FOR ATIO
The ability to maintain shutoff is shown on the curve Shut
down Supply Current vs Temperature in the Typical Per-
formance Characteristics section. At very high elevated
temperature it is important to hold the shutdown pin close
to the negative supply to keep the supply current from
increasing.
SHUTDOWN
VOUT
AV = 10, RFB = 900Ω, RG = 100ΩLT1189 • AI10
1MHz Sine Wave Gated Off with Shutdown Pin
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A
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PPLICATITYPICAL
Differential Receiver MUX for Power Down Applications
LT1189 • TA03
–
REF
FB
+
V
DC
V
OUT
5V
–5V
CABLE 1
CABLE 2
15k
CMOS IN
CHANNEL SELECT
100Ω
1k
1.5k
1.5k
LT1189
15k
–
REF
FB
+
V
DC
1k
5V
–5V
15k
100Ω
1.5k
1.5k
LT1189
15k
1k
1k
–5V
2
6
7
54
8
1
3
2
6
7
5
4
8
1
3
74HC04 74HC04
1% RESISTORS WORST CASE CMRR = 28dB
TYPICALLY 35dB
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT1189
12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900
●
FAX
: (408) 434-0507
●
TELEX
: 499-3977
LINEAR TECHNOLOGY CORPORATION 1993
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
W
I
SPL
II
F
ED S
W
A
CHETIC
+
–
OUT
V
BIAS
V
LT1189 • SS
BIAS
V
M
C
FF
C
+V+V
3
2
5
1+/REF
S/D
6
*
V
7
+
V
4
–
* SUBSTRATE DIODE, DO NOT FORWARD BIAS
8–/FB
BA/LT/GP 0293 10K REV 0
0.045 ± 0.015
(1.143 ± 0.381)
0.100 ± 0.010
(2.540 ± 0.254)
0.065
(1.651)
TYP
0.045 – 0.065
(1.143 – 1.651)
0.130 ± 0.005
(3.302 ± 0.127)
0.020
(0.508)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
0.125
(3.175)
MIN
0.009 – 0.015
(0.229 – 0.381)
0.300 – 0.320
(7.620 – 8.128)
0.325 +0.025
–0.015
+0.635
–0.381
8.255
()
12 34
8765
0.250 ± 0.010
(6.350 ± 0.254)
0.400
(10.160)
MAX
1234
0.150 – 0.157
(3.810 – 3.988)
8765
0.189 – 0.197
(4.801 – 5.004)
0.228 – 0.244
(5.791 – 6.197)
0.010 – 0.020
(0.254 – 0.508)
0.016 – 0.050
0.406 – 1.270
× 45°
0°– 8° TYP
0.008 – 0.010
(0.203 – 0.254)
0.053 – 0.069
(1.346 – 1.752)
0.014 – 0.019
(0.355 – 0.483)
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
BSC
0.290 – 0.320
(7.366 – 8.128)
0.008 – 0.018
(0.203 – 0.460) 0° – 15°
0.385 ± 0.025
(9.779 ± 0.635)
0.005
(0.127)
MIN
0.405
(10.287)
MAX
0.220 – 0.310
(5.588 – 7.874)
1234
8765
0.025
(0.635)
RAD TYP
0.045 – 0.065
(1.14 – 1.65)
FULL LEAD
OPTION
0.023 – 0.045
(0.58 – 1.14)
HALF LEAD
OPTION
CORNER LEADS OPTION
(4 PLCS)
0.014 – 0.026
(0.360 – 0.660)
0.200
(5.080)
MAX
0.015 – 0.060
(0.381 – 1.524)
0.125
3.175
MIN
0.100 ± 0.010
(2.540 ± 0.254)
0.045 – 0.065
(1.14 – 1.65)
J8 Package
8-Lead Hermetic DIP
N8 Package
8-Lead Plastic DIP
S8 Package
8-Lead Plastic SOIC
