LT1189
4
LT1189C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
OS
Input Offset Voltage Either Input 1.0 3.0 mV
(Note 4) SOIC Package 1.0 6.0 mV
∆V
OS
/∆T Input V
OS
Drift 5.0 µV/°C
I
OS
Input Offset Current Either Input 0.2 1.5 µA
I
B
Input Bias Current Either Input ±0.5 ±3.5 µA
Input Voltage Range –2.5 3.5 V
CMRR Common-Mode Rejection Ratio V
CM
= –2.5V to 3.5V 80 105 dB
PSRR Power Supply Rejection Ratio V
S
= ±2.375V to ±8V 70 90 dB
V
OUT
Output Voltage Swing V
S
= ±5V, R
L
= 1k, A
V
= 50 ±3.7 ±4.0 V
V
S
= ±8V, R
L
= 1k, A
V
= 50 ±6.6 ±7.0
V
S
= ±8V, R
L
= 300Ω, A
V
= 50, (Note 3) ±6.4 ±6.6
G
E
Gain Error V
O
= ±1V, A
V
= 10, R
L
= 1k 1.0 3.5 %
I
S
Supply Current 13 17 mA
Shutdown Supply Current Pin 5 at V
–
, (Note 11) 0.8 1.5 mA
I
S/D
Shutdown Pin Current Pin 5 at V
–
525 µA
V
S
= ±5V, VREF = 0V, RFB1 = 900Ω from pins 6 to 8, RFB2 = 100Ω from pin 8 to ground, RL = RFB1 + RFB2 = 1k, CL ≤ 10pF, pin 5 open.
Note 1: A heat sink may be required to keep the junction temperature below
absolute maximum when the output is shorted continuously.
Note 2: T
J
is calculated from the ambient temperature T
A
and power dissipation
P
D
according to the following formulas:
LT1189MJ8, LT1189CJ8: T
J
= T
A
+ (P
D
× 100°C/W)
LT1189CN8: T
J
= T
A
+ (P
D
× 100°C/W)
LT1189CS8: T
J
= T
A
+ (P
D
× 150°C/W)
Note 3: When R
L
= 1k is specified, the load resistor is R
FB1
+ R
FB2
, but when
R
L
= 300Ω is specified, then an additional 430Ω is added to the output such
that (R
FB1
+ R
FB2
) in parallel with 430Ω is R
L
= 300Ω.
Note 4: V
OS
measured at the output (pin 6) is the contribution from both input
pair, and is input referred.
Note 5: V
IN
LIM
is the maximum voltage between –V
IN
and +V
IN
(pin 2 and
pin 3) for which the output can respond.
Note 6: Slew rate is measured between ±1V on the output, with a V
IN
step of
±0.5V, A
V
= 10 and R
L
= 1k.
Note 7: Full power bandwidth is calculated from the slew rate measurement:
FPBW = SR/2πVp.
Note 8: Settling time measurement techniques are shown in “Take the
Guesswork Out of Settling Time Measurements,” EDN, September 19, 1985.
Note 9: NTSC (3.58MHz).
Note 10: AC parameters are 100% tested on the ceramic and plastic DIP
packaged parts (J8 and N8 suffix) and are sample tested on every lot of the SO
packaged parts (S8 suffix).
Note 11: See Application section for shutdown at elevated temperatures. Do
not operate shutdown above T
J
> 125°C.
5V
–
+
ELECTRICAL C CHARA TERISTICS
0°C ≤ TA ≤ 70°C, (Note 3)
LT1189C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
OS
Input Offset Voltage, (Note 4) Either Input 1.0 3.0 mV
∆V
OS
/∆T Input V
OS
Drift 5.0 µV/°C
I
OS
Input Offset Current Either Input 0.2 1.5 µA
I
B
Input Bias Current Either Input ±0.5 ±3.5 µA
Input Voltage Range 2.0 3.5 V
CMRR Common-Mode Rejection Ratio V
CM
= 2.0V to 3.5V 80 100 dB
V
OUT
Output Voltage Swing R
L
= 300Ω to Ground V
OUT
High 3.5 4.0 V
(Note 3) V
OUT
Low 0.15 0.4
I
S
Supply Current 12 16 mA
Shutdown Supply Current Pin 5 at V, (Note 11) 0.8 1.5 mA
I
S/D
Shutdown Pin Current Pin 5 at V
–
525 µA
5V
VS+ = +5V, VS– = 0V, VREF = 2.5V, RFB1 = 900Ω from pins 6 to 8, RFB2 = 100Ω from pin 8 to VREF, RL = RFB1 + RFB2 = 1k, CL ≤ 10pF, pin 5
open.
0°C ≤ TA ≤ 70°C, (Note 3)
ELECTRICAL C CHARA TERISTICS