Ultra SeriesTM Crystal Oscillator Si549 Data Sheet Ultra Low Jitter I2C Programmable XO (95 fs), 0.2 to 1500 MHz The Si549 Ultra SeriesTM oscillator utilizes Silicon Laboratories' advanced 4th generation DSPLL(R) technology to provide an ultra-low jitter, low phase noise clock at any output frequency. The device is user-programmed via simple I2C commands to provide any frequency from 0.2 to 1500 MHz with <1 ppb resolution and maintains exceptionally low jitter for both integer and fractional frequencies across its operating range. The Si549 offers excellent reliability and frequency stability as well as guaranteed aging performance. On-chip power supply filtering provides industry-leading power supply noise rejection, simplifying the task of generating low jitter clocks in noisy systems that use switched-mode power supplies. The Si549 has a dramatically simplified supply chain that enables Silicon Labs to ship custom frequency samples 1-2 weeks after receipt of order. Unlike a traditional XO, where a different crystal is required for each output frequency, the Si549 uses one simple crystal and a DSPLL IC-based approach to provide the desired output frequency. The Si549 is factory-configurable for a wide variety of user specifications, including startup frequency, I2C address, output format, and OE pin location/ polarity. Specific configurations are factory-programmed at time of shipment, eliminating the long lead times associated with custom oscillators. Pin Assignments KEY FEATURES * I2C programmable to any frequency from 0.2 to 1500 MHz with < 1 ppb resolution * Ultra low jitter: 95 fs Typ RMS (12 kHz - 20 MHz) * Configure up to 4 pin-selectable startup frequencies * I2C interface supports 100 kbps, 400 kbps, and 1 Mbps (Fast Mode Plus) * Excellent PSRR and supply noise immunity: -80 dBc Typ * 3.3 V, 2.5 V and 1.8 V VDD supply operation from the same part number * LVPECL, LVDS, CML, HCSL, CMOS, and Dual CMOS output options * 3.2x5, 5x7 mm package footprints * Samples available with 1-2 week lead times APPLICATIONS SDA OE/FS/NC 1 NC/OE/FS GND 7 * 100G/200G/400G OTN, coherent optics, PAM4 6 VDD 2 5 CLK- 3 4 CLK+ * 10G/40G/100G optical ethernet * 3G-SDI/12G-SDI/24G-SDI broadcast video * Servers, switches, storage, search acceleration 8 SCL * Test and measurement * FPGA/ASIC clocking (Top View) Pin # 1, 2 Fixed Frequency Crystal Descriptions Selectable via ordering option OE = Output enable; FS = Frequency Select; NC = No connect 3 GND = Ground 4 CLK+ = Clock output 5 CLK- = Complementary clock output. Not used for CMOS. 6 VDD = Power supply 7 SDA = I2C Serial Data 8 SCL = I2C Serial Clock silabs.com | Building a more connected world. Frequency Flexible DSPLL DCO OSC Digital Phase Detector Low Noise Driver Digital Loop Filter Phase Error Cancellation Phase Error Fractional Divider Flexible Formats, 1.8V - 3.3V Operation NVM Control Power Supply Regulation OE, Frequency Select (I2C and Pin Control) Built-in Power Supply Noise Rejection Rev. 1.0 Si549 Data Sheet Ordering Guide 1. Ordering Guide The Si549 XO supports a variety of options including startup frequency, output format, and OE pin location/polarity, as shown in the chart below. Specific device configurations are programmed into the part at time of shipment, and samples are available in 1-2 weeks. Silicon Laboratories provides an online part number configuration utility to simplify this process. Refer to www.silabs.com/oscillators to access this tool and for further ordering instructions. XO Series 549 Description I2C Oscillator 549 Total Stability 2 50 ppm 25 ppm 20 ppm Temp Stability 20 ppm 10 ppm 7 ppm A B C A A A A - A B - - - - Package 5x7 mm 3.2x5 mm - A G B Temperature Grade -40 to 85 C G R Device Revision Signal Format VDD Range LVPECL LVDS CMOS CML HCSL Dual CMOS (In-Phase) Dual CMOS (Complementary) Custom 1 2.5, 3.3 V 1.8, 2.5, 3.3 V 1.8, 2.5, 3.3 V 1.8, 2.5, 3.3 V 1.8, 2.5, 3.3 V Order Option A B C D E 1.8, 2.5, 3.3 V F 1.8, 2.5, 3.3 V G 1.8, 2.5, 3.3 V X Code A B C Supported Frequency Range 0.2-1500 MHz 0.2-800 MHz 0.2-325 MHz (CMOS available to 250 MHz) Pinout Option Code OE Pin OE Polarity A B C D E F G H Pin 1 Pin 1 Pin 2 Pin 2 Pin 1 Pin 1 Pin 2 Pin 2 Active High Active Low Active High Active Low Active High Active Low Active High Active Low FS0 (Dual) ----Pin 2 Pin 2 Pin 1 Pin 1 J -- -- Pin 1 Single Dual Quad Codes A, B SDA Codes E, F SDA Code J SDA OE 1 NC GND 7 6 VDD 2 5 3 4 8 OE 1 CLK- FS0 2 CLK+ GND 3 SCL FS0 1 5 CLK- FS1 4 CLK+ GND 6 VDD 2 5 CLK- 3 4 CLK+ 8 Frequency Code 3 Description xxxxxx The Si549 supports one, two, or four user-defined startup frequencies in the range selected by the Supported Frequency Range code. A userdefined 7-bit I2C address is supported. Each unique startup configuration and I2C address combination is assigned a 6-digit code. SCL SDA 7 6 VDD FS0 1 6 VDD OE 2 5 CLK- OE 2 5 CLK- GND 3 4 CLK+ GND 3 4 CLK+ 8 7 Pin 2 Reel Tape and Reel Coil Tape Codes G, H SDA NC 1 8 6 VDD SCL Codes C, D 7 7 FS1 (Quad) --------- Code R <Blank> SCL 8 SCL If replacing Si570A-K, use Code C If replacing Si570M-W, use Code D Notes: 1. Contact Silicon Labs for non-standard configurations. 2. Total stability includes temp stability, initial accuracy, load pulling, VDD variation, and 20 year aging at 70 C. 3. Create custom part numbers at www.silabs.com/oscillators. silabs.com | Building a more connected world. Rev. 1.0 | 2 Si549 Data Sheet Ordering Guide 1.1 Technical Support Frequently Asked Questions (FAQ) www.silabs.com/Si549-FAQ Oscillator Phase Noise Lookup Utility www.silabs.com/oscillator-phase-noise-lookup Quality and Reliability www.silabs.com/quality Development Kits www.silabs.com/oscillator-tools silabs.com | Building a more connected world. Rev. 1.0 | 3 Si549 Data Sheet Electrical Specifications 2. Electrical Specifications Table 2.1. Electrical Specifications VDD = 1.8 V, 2.5 or 3.3 V 5%, TA = -40 to 85 C Parameter Temperature Range Frequency Range Supply Voltage Supply Current Symbol Rise/Fall Time (20% to 80% VPP) Min Typ Max Unit -40 -- 85 C LVPECL, LVDS, CML 0.2 -- 1500 MHz HCSL 0.2 -- 400 MHz CMOS, Dual CMOS 0.2 -- 250 MHz 3.3 V 3.135 3.3 3.465 V 2.5 V 2.375 2.5 2.625 V 1.8 V 1.71 1.8 1.89 V LVPECL (output enabled) -- 107 153 mA LVDS/CML (output enabled) -- 83 121 mA HCSL (output enabled) -- 86 126 mA CMOS (output enabled) -- 87 127 mA Dual CMOS (output enabled) -- 92 141 mA Tristate Hi-Z (output disabled) -- 73 112 mA Frequency stability Grade A -20 -- 20 ppm Frequency stability Grade B -10 -- 10 ppm Frequency stability Grade C -7 -- 7 ppm Frequency stability Grade A -50 -- 50 ppm Frequency stability Grade B -25 -- 25 ppm Frequency stability Grade C -20 -- 20 ppm LVPECL/LVDS/CML -- -- 350 ps CMOS / Dual CMOS (CL = 5 pF) -- 0.5 1.5 ns HCSL, FCLK >50 MHz -- -- 550 ps All formats 45 -- 55 % TA FCLK VDD IDD Temperature Stability Total Stability1 Test Condition/Comment FSTAB TR/TF Duty Cycle DC Output Enable (OE), VIH 0.7 x VDD -- -- V Frequency Select (FS0, FS1)2 VIL -- -- 0.3 x VDD V TD Output Disable Time, FCLK >10 MHz -- -- 3 s TE Output Enable Time, FCLK >10 MHz -- -- 20 s TFS Settling Time after FS Change -- -- 10 ms Powerup Time tOSC Time from 0.9 x VDD until output frequency (FCLK) within spec -- -- 10 ms LVPECL Output Option3 VOC Mid-level VDD - 1.42 -- VDD - 1.25 V VO Swing (diff) 1.1 -- 1.9 VPP silabs.com | Building a more connected world. Rev. 1.0 | 4 Si549 Data Sheet Electrical Specifications Parameter Symbol Test Condition/Comment Min Typ Max Unit VOC Mid-level (2.5 V, 3.3 V VDD) 1.125 1.20 1.275 V Mid-level (1.8 V VDD) 0.8 0.9 1.0 V VO Swing (diff) 0.5 0.7 0.9 VPP VOH Output voltage high 660 750 850 mV VOL Output voltage low -150 0 150 mV VC Crossing voltage 250 350 550 mV CML Output Option (AC-Coupled) VO Swing (diff) 0.6 0.8 1.0 VPP CMOS Output Option VOH IOH = 8/6/4 mA for 3.3/2.5/1.8V VDD 0.85 x VDD -- -- V VOL IOL = 8/6/4 mA for 3.3/2.5/1.8V VDD -- -- 0.15 x VDD V LVDS Output Option4 HCSL Output Option5 Notes: 1. Total Stability includes temperature stability, initial accuracy, load pulling, VDD variation, and aging for 20 yrs at 70 C. 2. OE includes a 50 k pull-up to VDD for OE active high. Includes a 50 k pull-down to GND for OE active low. FS0 and FS1 pins each include a 50 k pull-up to VDD. NC (No Connect) pins include a 50 k pull-down to GND. 3. 50 to VDD - 2.0 V. 4. Rterm = 100 (differential). 5. 50 to GND. Table 2.2. I2C Characteristics VDD = 1.8, 2.5, or 3.3 V 5%, TA = -40 to 85 C Parameter Symbol Test Condition/Comment Min Typ Max Unit SDA, SCL Input Voltage High VIH 0.70 x VDD -- -- V SDA, SCL Input Voltage Low VIL -- -- 0.30 x VDD V MRES -- 0.026 -- ppb From center frequency -950 -- +950 ppm Settling Time for Small Frequency Change < 950 ppm from center frequency -- -- 100 s Settling Time for Large Frequency Change (Output Squelched during Frequency Transition) > 950 ppm from center frequency -- -- 10 ms Frequency Reprogramming Resolution Frequency Range for Small Frequency Change (Continuous Glitchless Output) silabs.com | Building a more connected world. Rev. 1.0 | 5 Si549 Data Sheet Electrical Specifications Table 2.3. Clock Output Phase Jitter and PSRR VDD = 1.8 V, 2.5 or 3.3 V 5%, TA = -40 to 85 C Parameter Symbol Test Condition/Comment Min Typ Max Unit Phase Jitter (RMS, 12 kHz - 20MHz)1 All Differential Formats J FCLK 200 MHz -- 95 150 fs 100 MHz FCLK < 200 MHz -- 115 150 fs Phase Jitter (RMS, 12kHz - 20MHz)1 CMOS / Dual CMOS Formats J 10 MHz FCLK 250 MHz -- 200 -- fs PSRR 100 kHz sine wave -- -83 -- 200 kHz sine wave -- -83 -- 500 kHz sine wave -- -82 -- 1 MHz sine wave -- -85 -- Spurs Induced by External Power Supply Noise, 50 mVpp Ripple. LVDS 156.25 MHz Output dBc Note: 1. Guaranteed by characterization. Jitter inclusive of any spurs. Table 2.4. Clock Output Phase Noise (Typical) Offset Frequency (f) 156.25 MHz LVDS 200 MHz LVDS 644.53125 MHz LVDS 100 Hz -107 -104 -92 1 kHz -130 -126 -117 10 kHz -137 -135 -126 100 kHz -143 -140 -131 1 MHz -149 -147 -138 10 MHz -160 -161 -153 20 MHz -161 -161 -155 Offset Frequency (f) 156.25 MHz LVPECL 200 MHz LVPECL 644.53125 MHz LVPECL 100 Hz -106 -103 -93 1 kHz -129 -127 -118 10 kHz -137 -135 -124 100 kHz -142 -140 -130 1 MHz -149 -147 -137 10 MHz -160 -163 -153 20 MHz -161 -164 -154 silabs.com | Building a more connected world. Unit dBc/Hz Unit dBc/Hz Rev. 1.0 | 6 Si549 Data Sheet Electrical Specifications Figure 2.1. Phase Jitter vs. Output Frequency Phase jitter measured with Agilent E5052 using a differential-to-single ended converter (balun or buffer). Measurements collected for >700 commonly used frequencies. Phase noise plots for specific frequencies are available using our free, online Oscillator Phase Noise Lookup Tool at www.silabs.com/oscillators. Table 2.5. Environmental Compliance and Package Information Parameter Test Condition Mechanical Shock MIL-STD-883, Method 2002 Mechanical Vibration MIL-STD-883, Method 2007 Solderability MIL-STD-883, Method 2003 Gross and Fine Leak MIL-STD-883, Method 1014 Resistance to Solder Heat MIL-STD-883, Method 2036 Moisture Sensitivity Level (MSL) Contact Pads 1 Gold over Nickel Note: 1. For additional product information not listed in the data sheet (e.g. RoHS Certifications, MDDS data, qualification data, REACH Declarations, ECCN codes, etc.), refer to our "Corporate Request For Information" portal found here: www.silabs.com/support/ quality/Pages/RoHSInformation.aspx. silabs.com | Building a more connected world. Rev. 1.0 | 7 Si549 Data Sheet Electrical Specifications Table 2.6. Thermal Conditions Package 3.2 x 5 mm 8-pin CLCC 5 x 7 mm 8-pin CLCC Parameter Symbol Test Condition Value Unit Thermal Resistance Junction to Ambient JA Still Air, 85 C 79.1 C/W Thermal Resistance Junction to Board JB Still Air, 85 C 49.6 C/W Max Junction Temperature TJ Still Air, 85 C 125 C Thermal Resistance Junction to Ambient JA Still Air, 85 C 67.1 C/W Thermal Resistance Junction to Board JB Still Air, 85 C 51.7 C/W Max Junction Temperature TJ Still Air, 85 C 125 C Table 2.7. Absolute Maximum Ratings1 Parameter Symbol Rating Unit TAMAX 95 C TS -55 to 125 C Supply Voltage VDD -0.5 to 3.8 C Input Voltage VIN -0.5 to VDD + 0.3 V ESD HBM (JESD22-A114) HBM 2.0 kV Solder Temperature2 TPEAK 260 C TP 20-40 sec Maximum Operating Temp. Storage Temperature Solder Time at TPEAK2 Notes: 1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability. 2. The device is compliant with JEDEC J-STD-020. silabs.com | Building a more connected world. Rev. 1.0 | 8 Si549 Data Sheet Dual CMOS Buffer 3. Dual CMOS Buffer Dual CMOS output format ordering options support either complementary or in-phase signals for two identical frequency outputs. This feature enables replacement of multiple XOs with a single Si549 device. ~ Complementary Outputs ~ In-Phase Outputs Figure 3.1. Integrated 1:2 CMOS Buffer Supports Complementary or In-Phase Outputs silabs.com | Building a more connected world. Rev. 1.0 | 9 Si549 Data Sheet Recommended Output Terminations 4. Recommended Output Terminations The output drivers support both AC-coupled and DC-coupled terminations as shown in figures below. VDD VDD VDD (3.3V, 2.5V) CLK+ Rp R1 R1 CLK+ 50 CLK- Si54x VDD (3.3V, 2.5V) Rp R2 R2 LVPECL Receiver VDD (3.3V, 2.5V) CLK+ VDD Si54x Rp Rp 50 R2 VDD (3.3V, 2.5V) R1 VTT CLK+ 50 LVPECL Receiver 50 VDD CLK- 50 R2 R2 DC-Coupled LVPECL - Thevenin Termination 50 CLK- 50 Si54x AC-Coupled LVPECL - Thevenin Termination R1 50 CLK- 50 R1 LVPECL Receiver AC-Coupled LVPECL - 50 w/VTT Bias 50 Si54x R1 VTT R2 50 50 LVPECL Receiver DC-Coupled LVPECL - 50 w/VTT Bias Figure 4.1. LVPECL Output Terminations AC Coupled LVPECL Termination Resistor Values DC Coupled LVPECL Termination Resistor Values VDD R1 R2 Rp VDD R1 R2 3.3 V 127 82.5 130 3.3 V 127 82.5 2.5 V 250 62.5 90 2.5 V 250 62.5 silabs.com | Building a more connected world. Rev. 1.0 | 10 Si549 Data Sheet Recommended Output Terminations (3.3V, 2.5V, 1.8V) VDD CLK+ (3.3V, 2.5V, 1.8V) VDD 50 CLK+ 33 100 CLK50 Si54x LVDS Receiver CLK+ 50 HCSL Receiver Source Terminated HCSL (3.3V, 2.5V, 1.8V) VDD 50 CLK+ 100 CLK50 Si54x 50 50 Si54x DC-Coupled LVDS (3.3V, 2.5V, 1.8V) VDD 50 CLK- 33 50 CLK- LVDS Receiver 50 50 Si54x AC-Coupled LVDS 50 HCSL Receiver Destination Terminated HCSL Figure 4.2. LVDS and HCSL Output Terminations (3.3V, 2.5V, 1.8V) VDD CLK+ VDD (3.3V, 2.5V, 1.8V) 50 CLK 10 100 CLK- NC 50 Si54x CML Receiver CLK+ Single CMOS Termination VDD (3.3V, 2.5V, 1.8V) 50 50 CLK+ 50 CLK- VCM CLK- Si54x CMOS Receiver Si54x CML Termination without VCM (3.3V, 2.5V, 1.8V) VDD 50 50 CML Receiver CML Termination with VCM 10 10 Si54x 50 50 CMOS Receivers Dual CMOS Termination Figure 4.3. CML and CMOS Output Terminations silabs.com | Building a more connected world. Rev. 1.0 | 11 Si549 Data Sheet Configuring Si549 Output Frequency via I2C 5. Configuring Si549 Output Frequency via I2C The Si549 oscillator device contains a fixed frequency crystal and frequency synthesis IC using Silicon Labs patented DSPLLTM technology, all enclosed in a standard hermetically sealed crystal oscillator (XO) package. The internal crystal provides the reference frequency used by the DSPLL frequency synthesis IC. The output frequency of the Si549 oscillator device can be dynamically set via I2C register settings in the DSPLL frequency synthesis IC. DSPLL technology provides unmatched frequency flexibility with superior output jitter/ phase noise performance and part per trillion frequency accuracy. This document describes how to calculate the required Si549 register values used to set device output frequency, and how to load these values into the Si549 device. Digital Phase Detector Phase Error Cancellation Digital Loop Filter Digital VCO HSDIV LSDIV Driver OSC Out+ Out- Phase Error OE I2C / FS Control Logic and NVM Power Supply Processing FBDIV VDD GND Figure 5.1. Si549 Block Diagram The figure above is a simplified high-level block diagram of the Si549 oscillator device. The output frequency is set by a combination of three divider blocks highlighted in the above block diagram. 1. FBDIV - DSPLLTM Feedback Divider used to set Digital VCO frequency 2. HSDIV - High-Speed Output Divider 3. LSDIV - Low-Speed Output Divider The final device output frequency is based on the digital VCO frequency divided by the product of HSDIV and LSDIV divider settings. The limits of each of these internal blocks (both digital VCO and dividers) determines the valid operating frequency range of the device. The FBDIV divider, is a fractional fixed-point divider with a total length of 43 bits consisting of an 11-bit integer field (FBINT) and a 32 bit fractional field (FBFRAC) where total FBDIV = [FBINT].[FBFRAC] with an implied decimal point as shown. This bit format is known as an 11.32 fixed point format where the integer portion is 11 bits and fractional portion is 32 bits, for a total of 43 bits. The HSDIV divider is an integer divider, 11 bits in length, containing a binary divider value. One noteworthy feature of the HSDIV divider is a special duty cycle correction circuit that allows odd divide ratios of lower divider values (5-33 only) with 50% duty cycle output. This feature is useful when LSDIV divide ratio is set to 1. The LSDIV divider performs power-of-2 divides ranging from divide by 1 (20) to divide by 32 (25). The register controlling the LSDIV divider is 3 bits in length, holding the power-of-2 divide ratio (divider exponent). For example, if LSDIV register = 3 the LSDIV divide ratio is 23 = 8. Values greater than 5 (i.e. LSDIV register = 6 or 7) still map into a divide by 32. The tables below summarize the divider limits for LSDIV, HSDIV, FBDIV. These limits and restrictions must be observed when deriving divider register values, as will be explained in later sections. Table 5.1. Si549 Divider Range Limits Divider Upper Limit Lower Limit HSDIV[10:0] (unsigned) 2046 5 LSDIV[2:0] 1 (unsigned) 32 (2^5) 1 (2^0) FBDIV[42:0] hex (unsigned) 7FDFFFFFFFF 03C00000000 FBDIV[42:0] int.frac (unsigned) 2045.99999999976 60.0 Note: 1. LSDIV is power of 2 divider. See LSDIV table below for actual divide ratio based on LSDIV register value. silabs.com | Building a more connected world. Rev. 1.0 | 12 Si549 Data Sheet Configuring Si549 Output Frequency via I2C Table 5.2. Additional LSDIV and HSDIV Divider Restrictions LSDIV Divide Ratio HSDIV Value Restrictions 1 5-33 even or odd values 1 , Register Value 0 34-2046 even values only 1 2 5-2046 even or odd values 2 4 5-2046 even or odd values 3 8 5-2046 even or odd values 4 16 5-2046 even or odd values 5 32 5-2046 even or odd values 6 32 5-2046 even or odd values 7 32 5-2046 even or odd values Note: 1. HSDIV can implement low value (5-33) odd divide ratios while providing a 50% duty cycle output due to special duty cycle correction circuit. Note that all divider values (FBDIV, HSDIV, LSDIV) are unsigned and contain only positive values. The Si549 high-performance oscillator family has three different speed grade offerings, each covering a specific frequency range. The table below outlines the output frequency range coverage by each speed grade, the corresponding min and max VCO frequency for that speed grade, and the nominal crystal frequency. The information in the table below is needed when calculating divider settings for a given device, speed grade, and output frequency. Table 5.3. Si549 Speed Grades, Crystal Frequency, and VCO Range Limits Device Speed Grade Xtal freq (MHz) Min Output Freq (MHz) Max Output Freq (MHz) Min Fvco (GHz) Max Fvco (GHz) Si549 A 152.6 0.2 1500 10.8 12.511886114 B 152.6 0.2 800 10.8 12.206718160 C 152.6 0.2 325 10.8 12.206718160 silabs.com | Building a more connected world. Rev. 1.0 | 13 Si549 Data Sheet Configuring Si549 Output Frequency via I2C 5.1 Output Frequency Equations The basic equations used to derive the output frequency are given below and can be easily inferred from the device block diagram in Figure 5.2 Si549 Frequency Definition Block Diagram on page 14. Equation 1 is the relationship between the output frequency (Fout), and the VCO frequency (Fvco) and total output divider ratio (HSDIV * LSDIV). Equation 2 is the relationship between the VCO frequency (Fvco), the fixed crystal oscillator frequency (Fosc), and the feedback divider (FBDIV). Fout = Fvco / (HSDIV x LSDIV) Equation 1 Fvco = (Fosc x FBDIV) Equation 2 Digital Phase Detector Phase Error Cancellation Digital Loop Filter Digital VCO HSDIV LSDIV Driver OSC Out+ Out- Phase Error OE I2C / FS Control Logic and NVM Power Supply Processing FBDIV VDD GND Figure 5.2. Si549 Frequency Definition Block Diagram Equation 3a is a rearranged Equation 1 to solve for the total output divider (HSDIV *LSDIV) given Fout and Fvco. Equation 3b is rearranged again solving for Fvco given Fout and (HSDIV * LSDIV). (HSDIV x LSDIV) = Fvco / Fout Equation 3a Fvco = Fout x (HSDIV x LSDIV) Equation 3b Equation 4 is a rearranged Equation 2 to now solve for FBDIV given Fvco and Fosc. FBDIV = Fvco / Fosc Equation 4 Equations 3a, 3b, and 4 will be used in the process of deriving the required divider values to provide a desired output frequency. The basic process is outlined below. silabs.com | Building a more connected world. Rev. 1.0 | 14 Si549 Data Sheet Configuring Si549 Output Frequency via I2C 5.2 General Process Steps for Divider Calculation 1. Estimate a theoretical total output divider value (HSDIV * LSDIV) based on desired Fout while targeting the minimum valid Fvco frequency using Eqn. 3a and Table 5.3 Si549 Speed Grades, Crystal Frequency, and VCO Range Limits on page 13. Use floating point calculations for this step. * Result: Floating point value of total (HSDIV * LSDIV). 2. Derive a valid LSDIV divider value based on LSDIV and HSDIV divider limitations using the lowest possible value for LSDIV. For example, if (HSDIV * LSDIV) = 8.22, use LSDIV =1 and HSDIV = 8.22 versus LSDIV = 2 and HSDIV = 4.11. * Result: Valid LSDIV value. 3. Using LSDIV value from #2 above, find nearest valid integer HSDIV divider value resulting in Fvco being equal to or greater than Fvco min, which observing all HSDIV limitations. Use Eqns. 3a/3b as necessary. * Result: Valid HSDIV value. 4. With valid integer HSDIV and LSDIV values, calculate the required Fvco frequency with Eqn. 3b. (Fvco must remain in valid range per Table 5.3 Si549 Speed Grades, Crystal Frequency, and VCO Range Limits on page 13.) * Result: Valid VCO frequency. 5. With the derived valid Fvco frequency, use Eqn 4 to calculate required FBDIV based on device specific Fosc frequency from Table 5.3 Si549 Speed Grades, Crystal Frequency, and VCO Range Limits on page 13. * Result: Valid FBDIV value 6. At this point all FBDIV, HSDIV and LSDIV values required to generate the desired output frequency have been calculated. These three divider values must be now be appropriately formatted to fit the register format expected by the device. This is described in a later section. silabs.com | Building a more connected world. Rev. 1.0 | 15 Si549 Data Sheet Configuring Si549 Output Frequency via I2C 5.3 Example: Deriving Si549 Divider Settings for 156.75 MHz Output The general process of deriving divider values for a specific output frequency is outlined in the previous section and now will be used in this example. To reiterate, all calculations must be done while observing divider limits and valid VCO frequency range limits for your device. In this example, the device is Si549 and with a desired output frequency of 156.75 MHz, the speed grade required will be "C" or better. (One important note: All divider and register settings derived for any speed grade will work without modification for all faster speed grades on the same base part number device.) Example VB code that implements the following divider calculation process is given in 5.8 Si549 Frequency Planner VB Code and can be used for implementing any supported output frequency. Step 1: Find the valid theoretical lower limit of the total output divider (HSDIV*LSDIV) based on the desired output frequency and lowest valid VCO frequency. This will bias the divider solution to the lowest possible VCO frequency since this will provide the best performance solution. Given the valid Si549 VCO range is 10.8000 GHz to 12.1097 GHz, the minimum theoretical values for (HSDIV * LSDIV) for the example 156.75 MHz output frequency are given in Equation 3: Minimum (HSDIV*LSDIV) = (10.8000 GHz / 156.75 MHz) = 68.89952... Step 2: Find valid LSDIV divisor value given minimum (HSDIV*LSDIV) from step 1. For best performance, preference should be given to implementation of the total output divider (HSDIV*LSDIV) using HSDIV with LSDIV divide ratio = 1, if possible. Use LSDIV divide ratios > 1 only if HSDIV alone cannot implement the required output divider. Since the total (HSDIV*LSDIV) value of 68.8995... is less than the HSDIV maximum divider value of 2046, the LSDIV divide ratio value will be 1, which corresponds to a LSDIV register setting of 0, since the LSDIV divider can only be a power of 2 value (see Table 5.2 Additional LSDIV and HSDIV Divider Restrictions on page 13 for valid LSDIV settings). LSDIV divide ratio = 1, therefore LSDIV register value = 0 Step 3: Find HSDIV divisor value. Given LSDIV = 1, HSDIV must implement 68.8995... or greater. Since HSDIV is an integer divider, the next greatest integer is 69. But, checking valid HSDIV values when LSDIV divide ratio = 1, we see 69 is NOT valid since it is greater than 33 and an odd value. This means the next greater integer value must be used, which is 70 (now even value). Note that 68 would not be valid since 68 is less than 68.8995... and would result in a VCO frequency below the lower VCO frequency limit. HSDIV divide ratio = 70, which gives HSDIV register value = 70 decimal (or hex value = 0x46) Step 4: Calculate a valid VCO frequency and corresponding floating point FBDIV value. Given the calculated output divider value (HSDIV*LSDIV) = 70, the VCO frequency must be set to (156.75 MHz * 70) = 10.9725 GHz. Note that 10.9725 GHz is indeed within the valid VCO frequency range per Table 5.3 Si549 Speed Grades, Crystal Frequency, and VCO Range Limits on page 13. Fvco = 10.9725 GHz Step 5: Calculate the FBDIV value necessary to provide a 10.9725 GHz Fvco using a 55.05 MHz crystal as reference (Si549 device). The floating point FBDIV value required to attain 10.9725 GHz with a 55.05 MHz crystal reference can be calculated as follows: FBDIV (float) = 10.9725 GHz / 55.05 MHz = 199.318801089918 Step 6: Format each divider value into the required register format. LSDIV and HSDIV are simply binary values and can be directly used. FBDIV must first be put into 11.32 fixed point format. Converting the floating point FBDIV value into the 11.32 fixed point hex value required by the Si549 is done as follows: Integer value = 199 decimal. Convert 199 to 11 bit hex = 0x0C7. This is FBINT. Fractional value = 0.318801089918. Multiply fractional value by 2^32 = 1369240255.12805. Now extract only the integer part of the result which is 1369240255. Convert 1369240255 to 32 bit hex = 0x519CF2BF . This is FBFRAC. The resulting 11.32 fixed point hex number is therefore: FBDIV = FBINT.FBFRAC = 0x0C7519CF2BF silabs.com | Building a more connected world. Rev. 1.0 | 16 Si549 Data Sheet Configuring Si549 Output Frequency via I2C At this point we have calculated all the required divider values. The table below summarizes the resulting divider values for implementing a 156.75 MHz output clock on the Si549. Table 5.4. Divider Register Values for Si549 Configured for 156.75 MHz Output Clock Divider Register Decimal Value Hex Value Reg Length (bits) LSDIV 0 0x0 3 HSDIV 70 0x046 11 FBDIV 199.318801089918 0x0C7519CF2BF 43 (11+32) 5.4 Mapping Divider Settings into Register Values For the previous 156.75 MHz example, the divider value to register mapping is shown in the table below. Note that Register 24 is a packed register and contains bits from both LSDIV and HSDIV registers as follows: LSDIV[2:0] maps into Reg24[6:4] and HSDIV[10:8] maps into Reg24[2:0]. Note that bits Reg24[7] and Reg24[3] are not used and indicated with `x' in the RegName field below. See also the Register Map Reference section for specific bit positioning within registers. Table 5.5. Si549 Divider Register Values for 156.75 MHz Output Clock Configuration Register (Decimal) Hex Value Reg Name 23 46 HSDIV[7:0] 24 00 x:LSDIV[2:0]:x:HSDIV[10:8] 26 BF FBDIV[7:0] 27 F2 FBDIV[15:8] 28 9C FBDIV[23:16] 29 51 FBDIV[31:24] 30 C7 FBDIV[39:32] 31 00 FBDIV[42:40] silabs.com | Building a more connected world. Rev. 1.0 | 17 Si549 Data Sheet Configuring Si549 Output Frequency via I2C 5.5 I2C Register Write Procedure to Set Output Frequency After the frequency setting registers (Reg 23-Reg31) are calculated, there is a procedure that must be followed involving other specific control registers for the device to properly use the new frequency setting registers. Simply writing Reg23-Reg31 is not enough. The following procedure must be performed as shown to properly configure the Si549 for the desired output frequency. In other words, all the following register writes must be done, and in the exact sequence shown. This programming sequence consists of three distinct phases. 1. Writing to specific registers to get the device ready to be updated. 2. Writing the calculated frequency (divider) settings for the desired output frequency. 3. Writing to specific registers necessary to start-up the device after divider registers have been updated. The new output frequency will appear on output. The divider values shown in the table below are for the previously described Si549 example for an output frequency of 156.75 MHz (for other frequencies, replace the divider values in registers 23-31 with values specific to your frequency requirements). Table 5.6. Si549 Register Write Sequence to Set Output Frequency Register (decimal) Write Data (hex) Description Purpose 255 0x00 Set page register to point to page 0 Get Device Ready for Update 69 0x00 Disable FCAL override (to allow FCAL for this Freq Update) 17 0x00 Synchronously disable output 23 0x46 HSDIV[7:0] 24 0x00 LSDIV[2:0]:HSDIV[10:8] 26 0xBF FBDIV[7:0] 27 0xF2 FBDIV[15:8] 28 0x9C FBDIV[23:16] 29 0x51 FBDIV[31:24] 30 0xC7 FBDIV[39:32] 31 0x00 FBDIV[42:40] 7 0x08 Start FCAL using new divider values 17 0x01 Synchronously enable output Update Dividers Startup Device Note: Refer to the device data sheet for default Si549 I2C address or to the device data sheet addendum for your specific I2C address. silabs.com | Building a more connected world. Rev. 1.0 | 18 Si549 Data Sheet Configuring Si549 Output Frequency via I2C 5.6 Digitally Controlled Oscillator - ADPLL: Small, Fast Frequency Changes The Si549 can make small, fast frequency adjustments over a range of +/- 950 ppm (parts-per-million) around the device output frequency (set as described in previous sections). This mode is typically used in applications requiring a digitally controlled oscillator (DCO) for digital PLL or other types of frequency control loops. We refer to this type of application as an all-digital PLL or ADPLL. The ADPLL mode uses a single 24 bit register, ADPLL_DELTA_M[23:0], to add an offset to the VCO frequency to affect the small frequency change. This offset is added in a synchronous fashion to prevent frequency discontinuities and can be updated as fast as the max I2C bus speed of 1 MHz will allow. The frequency offset can be positive or negative over a range of -950 ppm to +950 ppm with 0.0001164 ppm resolution. The equation for this frequency change is simply, ADPLL_DELTA_M[23:0] = FoutPPM / 0.0001164 Where FoutPPM is the desired ppm change in output frequency, ADPLL_DELTA_M[23:0] is a two's complement 24 bit value, and 0.0001164 is a constant per-bit ppm value. The 24 bit ADPLL_DELTA_M[23:0] value is written into three sequential 8 bit registers in LSByte to MSByte order via I2C. Upon writing the MSByte, the frequency change takes effect. Below is an example VB to implement this feature. (Note that writing ADPLL_DELTA_M[23:0] = 0x000 will result in no frequency offset and return to the nominal output frequency.) VB Code example for ADPLL (small frequency change) calculation and operation: nAddr = Device I2C address PPM_Delta = desired PPM frequency shift Function Set_ADPLL(ByVal nAddr As UInteger, ByVal PPM_Delta As Double) As Integer Dim ADPLL_PPM_StepSize As Double = 0.0001164 Dim ADPLL_Delta_M As Integer Dim Reg231 As UInteger = 0 Dim Reg232 As UInteger = 0 Dim Reg233 As UInteger = 0 Dim ReturnCode As Integer = 0 '1=OK, -1 PPM requested is out of bounds If (PPM_Delta <= 950 And PPM_Delta >= -950) Then ADPLL_Delta_M = (PPM_Delta / ADPLL_PPM_StepSize) Reg231 = (ADPLL_Delta_M And &HFF) Reg232 = (ADPLL_Delta_M >> 8) And &HFF Reg233 = (ADPLL_Delta_M >> 16) And &HFF I2C_Write(nAddr, 0, 231, Reg231) 'write "Reg231" value to register 231 at nAddr, page 0 (LSByte) I2C_Write(nAddr, 0, 232, Reg232) 'write "Reg232" value to register 232 at nAddr, page 0 I2C_Write(nAddr, 0, 233, Reg233) 'write "Reg233" value to register 233 at nAddr, page 0 (MSByte) ReturnCode = 1 Else ReturnCode = -1 End If Return (ReturnCode) End Function silabs.com | Building a more connected world. Rev. 1.0 | 19 Si549 Data Sheet Configuring Si549 Output Frequency via I2C 5.7 Register Map Reference Table 5.7. Register Map Reference Summary Register (decimal) 7 Register Bit 7 RESET 6 5 4 <Reserved> = 3'b000 17 2 MS_ICAL 2 1 <Reserved> = 3'b000 ODC_OE HSDIV[7:0] <Unused> LSDIV[2:0] <Unused> Reset Value R/W 0x00 R/W 0x01 R/W 0x54 R/W 0x00 0 <Unused> 23 24 3 Type HSDIV[10:8] 26 FBDIV[7:0] R/W 0x00 27 FBDIV[15:8] R/W 0x00 28 FBDIV[23:16] R/W 0x00 29 FBDIV[31:24] R/W 0x00 30 FBDIV[39:32] R/W 0x64 R/W 0x00 R/W 0x01 31 69 <Unused> FCAL_OV R FBDIV[42:40] <Reserved> = 7'b0000001 231 ADPLL_DELTA_M[7:0] R/W 0x00 232 ADPLL_DELTA_M[15:8] R/W 0x00 233 ADPLL_DELTA_M[23:16] R/W 0x00 R/W 0x00 255 <Reserved> = 6'b000000 PAGE[1:0] Table 5.8. Register Bit Field Summary Register Bit Field Name Bit Field (#bits) Register RESET 1 7 Set to 1 to reset device. Self clearing. MS_ICAL2 1 7 Set to 1 to initiate FCAL. Self clearing. HSDIV[10:0] 11 23-24 HSDIV is High-speed output divider value in unsigned 11-bit binary format. Valid divide values are from 5 to 2046, with values of 5-33 even or odd, and values 34-2046 restricted to even values only. LSDIV[2:0] 3 24 LSDIV sets a power-of-2 output divider. Values of 0,1,2,3,4,5,6,7 result in divide ratio of 1,2,4,8,16,32,32,32 respectively. Note that a value of 0 (divide-by-1) essentially bypasses this divider. silabs.com | Building a more connected world. Description Rev. 1.0 | 20 Si549 Data Sheet Configuring Si549 Output Frequency via I2C Register Bit Field Name Bit Field (#bits) Register FBDIV[42:0] 43 26-31 FCAL_OVR 1 69 ADPLL_DELTA_M[23:0] 24 231-233 Digital word to effect small frequency shifts to base frequency. Value is 24 bit 2's complement causing a 0.0001164 ppm per bit shift in frequency. Positive values = positive freq shift, negative values = negative freq shift. Valid range is -8161513 to +8161512, representing a max PPM shift range of -950 ppm to +950 ppm, with 0 value representing 0 PPM shift. Writing a new ADPLL_DELTA_M value will take effect upon writing to the MSByte (Register 233). Therefore, value updates should follow the sequence of writing in register order Reg 231...Reg 232...Reg 233. PAGE[1:0] 2 255 Sets which page of registers the I2C port is reading/writing. The size of a page is 256 bytes which is the addressable range of an I2C "set address" command. The value of PAGE is multiplied by 256 and added to what "set address" has set. Physically, the 2 PAGE bits become bits [9:8] of the device's internal register map address. This mechanism allows for more than 256 registers to be addressed within the 8 bit I2C "set address" limitation. silabs.com | Building a more connected world. Description The main DSPLL system feedback divide (FBDIV) value for Si54x. This 43 bit value is composed of an unsigned 11-bit integer value (FBDIV[42:32]) concatenated with a 32-bit fractional value (FBDIV[31:0]), for an 11.32 fixed point binary format. The valid range of the 11-bit integer part is from 60 to 2045 FCAL Override: If set to 1, FCAL is bypassed. Clear to 0 to allow FCAL. Rev. 1.0 | 21 Si549 Data Sheet Configuring Si549 Output Frequency via I2C 5.8 Si549 Frequency Planner VB Code Module Main ' ' Si54x Frequency Planner Code ' ' 'Set Target device type, Speed grade, and desired output frequency ' Public Device As Integer = 549 ' 544 or 549 only Public SpeedGrade As String = "C" 'Can only be "A" or "B" or "C" Public Output_Freq As Double = 312500000.0 'Output frequency in Hz (initially set to 312.5 MHz) 'Set in 'SetLimits" function... Public Fvco_max As Double 'Fvco Max per Table 3 Public Fvco_min As Double 'Fvco Min per Table 3 Public Xtal_freq As Double 'Xtal_Freq per Table 3 Public Fout_min As Double 'Minimum output frequency Public Fout_max As Double 'Maximum output frequency Sub Main() ' ' Device divider limits (see Tables 1 & 2) ' Dim HSDIV_UpperLimit As Integer = 2046 Dim HSDIV_LowerLimit As Integer = 5 Dim HSDIV_LowerLimit_Odd As Integer = 5 'min count for odd HSDIV divisor Dim HSDIV_UpperLimit_Odd As Integer = 33 'max count for odd HSDIV divisor Dim LSDIV_UpperLimit As Integer = 5 Dim LSDIV_LowerLimit As Integer = 0 Dim FBDIV_UpperLimit As Double = 2045 + ((2 ^ 32 - 1) / (2 ^ 32)) Dim FBDIV_LowerLimit As Double = 60.0 ' ' Working variables ' Dim Min_HSLS_Div As Double Dim LSDIV_Div As Double ' actual LSDIV divide ratio Dim LSDIV_Reg As Integer ' LSDIV as encoded in power of 2 for device register use Dim HSDIV As Double Dim FBDIV As Double Dim Fvco As Double Dim FBDIV_Int As UInteger Dim FBDIV_Frac As UInteger Dim Reg23 As UInteger = 0 'HSDIV[7:0] Dim Reg24 As UInteger = 0 'OD_LSDIV[2:0],HSDIV[10:8] (*2^4,/2^8) Dim Reg26 As UInteger = 0 'FBDIV[7:0] Dim Reg27 As UInteger = 0 'FBDIV[15:8] (/2^8) Dim Reg28 As UInteger = 0 'FBDIV[23:16] (/2^16) Dim Reg29 As UInteger = 0 'FBDIV[31:24] (/2^24) Dim Reg30 As UInteger = 0 'FBDIV[39:32] (/2^32) Dim Reg31 As UInteger = 0 'FBDIV[42:40] (/2^40) ' ' Set device limits based on device type and speed grade. ' (Checks if desired output frequency is valid based on device and speed grade) ' If SetLimits(Device, SpeedGrade, Output_Freq) = 0 Then ' ' If limits are set and output frequency is valid, calculate frequency plan... '*********************************************************************************************** ' Step 1: Find theoretical HSDIV *LSDIV value based on lowest valid VCO frequency... ' (Assumes "Output_Freq" has been tested and is in valid range for the device grade according to Table 3) ' Min_HSLS_Div = Fvco_min / Output_Freq ' Floating point HS*LS div value. Remember to first bounds check Output_Freq! 'Step 2: Find LSDIV divisor value given Min_HSLS_Div value ' LSDIV_Div = Math.Ceiling(Min_HSLS_Div / HSDIV_UpperLimit) encoded as power of 2 silabs.com | Building a more connected world. ' Divisor value of LSDIV, NOT yet Rev. 1.0 | 22 Si549 Data Sheet Configuring Si549 Output Frequency via I2C If (LSDIV_Div > 32) Then LSDIV_Div = 32 ' clip at 32 (max LSDIV divisor) ' 'Encode LSDIV divisor value into next nearest 'power of 2' value if not already. This will be LSDIV_Reg ' LSDIV_Reg = Math.Ceiling(Math.Log(LSDIV_Div, 2)) 2. Will range from 0 to 5. ' LSDIV_Reg now encoded as proper power of ' Adjust LSDIV_Div (holder of divisor) based on rounded power of 2 value in LSDIV_Reg LSDIV_Div = 2 ^ LSDIV_Reg 'LSDIV_Div divisor now synchronized to actual LSDIV_Reg. ' 'Step 3: Find HSDIV divisor value using known LSDIV divisor ' HSDIV = Math.Ceiling(Min_HSLS_Div / LSDIV_Div) If ((LSDIV_Reg > 0) Or ((HSDIV >= HSDIV_LowerLimit_Odd) And (HSDIV <= HSDIV_UpperLimit_Odd))) Then HSDIV = HSDIV ' Leaves HSDIV as even or odd only if LSDIV_Div = 1 and HSDIV is from 5 to 33. Else If ((HSDIV Mod 2) <> 0) Then 'If HSDIV is an odd value... HSDIV = HSDIV + 1 '...make it even by rounding up End If 'If already even, leave it alone End If ' ' Step 4: Now calculate Fvco and FBDIV ' Fvco = (HSDIV * LSDIV_Div * Output_Freq) 'Calculate Fvco based on valid HSDIV,LSDIV, and Fout FBDIV = Fvco / Xtal_freq 'Finally, calculate FBDIV based on xtal freq 'Calculate 11.32 fixed point FBDIV value (MCTL_M) 'Extract Integer part FBDIV_Int = Int(FBDIV) 'Extract fractional part FBDIV = (FBDIV - FBDIV_Int) FBDIV = FBDIV * (2 ^ 32) FBDIV_Frac = Int(FBDIV) ' 'Generate Register values based on LSDIV, HSDIV, and FBDIV (MCTL_M) ' Reg23 = (HSDIV And &HFF) Reg24 = ((HSDIV >> 8) And &H7) Or ((LSDIV_Reg And &H7) << 4) Reg26 Reg27 Reg28 Reg29 Reg30 Reg31 = = = = = = (FBDIV_Frac And &HFF) (FBDIV_Frac >> 8) And &HFF (FBDIV_Frac >> 16) And &HFF (FBDIV_Frac >> 24) And &HFF (FBDIV_Int) And &HFF (FBDIV_Int >> 8) And &H7 '************************************************************************* Else Console.WriteLine("*** Device invalid or Device limits exceeded. Frequency plan not calculated.") End If End Sub ' ' Sets device limits according to Table 3 ' Returns 0 if limits are set and output frequency is valid ' Returns -1 if limits not found or output frequency is invalid Function SetLimits(ByVal Device As Integer, ByVal SpeedGrade As String, ByVal Output_Freq As Double) As Integer Dim ReturnCode As Integer ReturnCode = 0 If Device = 544 Then Xtal_freq = 55050000.0 If SpeedGrade = "A" Then Fvco_min = 10800000000.0 Fvco_max = 12550082103.0 Fout_min = 200000.0 Fout_max = 1500000000.0 If ((Output_Freq < Fout_min) Or (Output_Freq > Fout_max)) Then ReturnCode = -1 End If ElseIf SpeedGrade = "B" Then Fvco_min = 10800000000.0 silabs.com | Building a more connected world. Rev. 1.0 | 23 Si549 Data Sheet Configuring Si549 Output Frequency via I2C Fvco_max = 12109728345.0 Fout_min = 200000.0 Fout_max = 800000000.0 If ((Output_Freq < Fout_min) Or (Output_Freq > Fout_max)) Then ReturnCode = -1 End If ElseIf SpeedGrade = "C" Then Fvco_min = 10800000000.0 Fvco_max = 12109728345.0 Fout_min = 200000.0 Fout_max = 325000000.0 If ((Output_Freq < Fout_min) Or (Output_Freq > Fout_max)) Then ReturnCode = -1 End If Else ReturnCode = -1 End If ElseIf Device = 549 Then Xtal_freq = 152600000.0 If SpeedGrade = "A" Then Fvco_min = 10800000000.0 Fvco_max = 12511886114.0 Fout_min = 200000.0 Fout_max = 1500000000.0 If ((Output_Freq < Fout_min) Or (Output_Freq > Fout_max)) Then ReturnCode = -1 End If ElseIf SpeedGrade = "B" Then Fvco_min = 10800000000.0 Fvco_max = 12206718160.0 Fout_min = 200000.0 Fout_max = 800000000.0 If ((Output_Freq < Fout_min) Or (Output_Freq > Fout_max)) Then ReturnCode = -1 End If ElseIf SpeedGrade = "C" Then Fvco_min = 10800000000.0 Fvco_max = 12206718160.0 Fout_min = 200000.0 Fout_max = 325000000.0 If ((Output_Freq < Fout_min) Or (Output_Freq > Fout_max)) Then ReturnCode = -1 End If Else ReturnCode = -1 End If Else ReturnCode = -1 End If Return (ReturnCode) End Function End Module -------------------------------------------------------------------------- silabs.com | Building a more connected world. Rev. 1.0 | 24 Si549 Data Sheet Configuring Si549 Output Frequency via I2C 5.9 Table of Common Frequencies for Si549 (152.6 MHz xtal) Fout (MHz) LSDIV HSDIV FBDIV Fvco (GHz) Reg 23 Reg 24 Reg 26 Reg 27 Reg 28 Reg 29 Reg 30 Reg 31 70.656 0 154 71.30422018 10.881024 9Ah 00h BAh 5Fh E1h 4Dh 47h 00h 100 0 108 70.77326343 10.8 6Ch 00h A7h 97h F4h C5h 46h 00h 122.88 0 88 70.86133683 10.81344 58h 00h 04h 92h 80h DCh 46h 00h 125 0 88 72.08387942 11 58h 00h 34h 1Fh 79h 15h 48h 00h 148.351648 0 74 71.93985552 10.97802195 4Ah 00h 07h 5Fh 9Ah F0h 47h 00h 148.5 0 74 72.01179554 10.989 4Ah 00h 63h 08h 05h 03h 48h 00h 148.945454 0 74 72.22780862 11.0219636 4Ah 00h 7Dh AAh 51h 3Ah 48h 00h 150 0 72 70.77326343 10.8 48h 00h A7h 97h F4h C5h 46h 00h 153.6 0 72 72.47182176 11.0592 48h 00h 84h 4Fh C9h 78h 48h 00h 155.52 0 70 71.33944954 10.8864 46h 00h 46h 2Ah E6h 56h 47h 00h 156.25 0 70 71.67431193 10.9375 46h 00h D8h B4h 9Fh ACh 47h 00h 168.04 0 66 72.67785059 11.09064 42h 00h C2h 9Dh 87h ADh 48h 00h 168.75 0 64 70.77326343 10.8 40h 00h A7h 97h F4h C5h 46h 00h 200 0 54 70.77326343 10.8 36h 00h A7h 97h F4h C5h 46h 00h 212.5 0 52 72.41153342 11.05 34h 00h 17h 41h 5Ah 69h 48h 00h 245.76 0 44 70.86133683 10.81344 2Ch 00h 04h 92h 80h DCh 46h 00h 250 0 44 72.08387942 11 2Ch 00h 34h 1Fh 79h 15h 48h 00h 270 0 40 70.77326343 10.8 28h 00h A7h 97h F4h C5h 46h 00h 311.04 0 36 73.37771953 11.19744 24h 00h 1Ch 3Ah B2h 60h 49h 00h 312.5 0 36 73.72214941 11.25 24h 00h A3h C8h DEh B8h 49h 00h 322.265625 0 34 71.80230177 10.95703125 22h 00h 14h A6h 63h CDh 47h 00h 400 0 27 70.77326343 10.8 1Bh 00h A7h 97h F4h C5h 46h 00h 425 0 26 72.41153342 11.05 1Ah 00h 17h 41h 5Ah 69h 48h 00h 491.52 0 22 70.86133683 10.81344 16h 00h 04h 92h 80h DCh 46h 00h 500 0 22 72.08387942 11 16h 00h 34h 1Fh 79h 15h 48h 00h 614.4 0 18 72.47182176 11.0592 12h 00h 84h 4Fh C9h 78h 48h 00h 622.08 0 18 73.37771953 11.19744 12h 00h 1Ch 3Ah B2h 60h 49h 00h 644.53125 0 17 71.80230177 10.95703125 11h 00h 14h A6h 63h CDh 47h 00h 750 0 15 73.72214941 11.25 0Fh 00h A3h C8h DEh B8h 49h 00h 800 0 14 73.39449541 11.2 0Eh 00h C0h A6h FDh 64h 49h 00h silabs.com | Building a more connected world. Rev. 1.0 | 25 Si549 Data Sheet Configuring Si549 Output Frequency via I2C 5.10 I2C Interface Configuration and operation of the Si549 is controlled by reading and writing to the RAM space using the I2C interface. The device operates in slave mode with 7-bit addressing and can operate in Standard-Mode (100 kbps), Fast-Mode (400 kbps), or Fast-Mode Plus (1 Mbps). Burst data transfer with auto address increments are also supported. The I2C bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL). Both the SDA and SCL pins must be connected to the VDD supply via an external pull-up as recommended by the I2C specification. The Si549 7-bit I2C slave address is usercustomized during the part number configuration process. Data is transferred MSB first in 8-bit words as specified by the I2C specification. A write command consists of a 7-bit device (slave) address + a write bit, an 8-bit register address, and 8 bits of data as shown in the figure below. A write burst operation is also shown where every additional data word is written using an auto-incremented address. Write Operation - Single Byte S Slv Addr [6:0] 0 A Reg Addr [7:0] A Data [7:0] A P A Data [7:0] Write Operation - Burst (Auto Address Increment) S Slv Addr [6:0] 0 A Reg Addr [7:0] A Data [7:0] A P Reg Addr +1 1 - Read 0 - Write A - Acknowledge (SDA LOW) N - Not Acknowledge (SDA HIGH) S - START condition P - STOP condition From slave to master From master to slave Figure 5.3. I2C Write Operation A read operation is performed in two stages. A data write is used to set the register address, then a data read is performed to retrieve the data from the set address. A read burst operation is also supported. This is shown in the figure below. Read Operation - Single Byte S Slv Addr [6:0] 0 A Reg Addr [7:0] A S Slv Addr [6:0] 1 A Data [7:0] P N P Read Operation - Burst (Auto Address Increment) S Slv Addr [6:0] 0 A Reg Addr [7:0] A S Slv Addr [6:0] 1 A Data [7:0] A P Data [7:0] N P Reg Addr +1 From slave to master From master to slave 1 - Read 0 - Write A - Acknowledge (SDA LOW) N - Not Acknowledge (SDA HIGH) S - START condition P - STOP condition Figure 5.4. I2C Read Operation The timing specifications and timing diagram for the I2C bus is compatible with the I2C-Bus standard. SDA timeout is supported for compatibility with SMBus interfaces. The I2C bus can be operated at a bus voltage of 1.71 to 3.63 V and should be the same voltage as the Si549 VDD. silabs.com | Building a more connected world. Rev. 1.0 | 26 Si549 Data Sheet Package Outline 6. Package Outline 6.1 Package Outline (5x7 mm) The figure below illustrates the package details for the 5x7 mm Si549. The table below lists the values for the dimensions shown in the illustration. Figure 6.1. Si549 (5x7 mm) Outline Diagram Table 6.1. Package Diagram Dimensions (mm) Dimension Min Nom Max Dimension Min Nom Max A 1.07 1.18 1.33 E1 6.10 6.20 6.30 A2 0.40 0.50 0.60 L 1.07 1.17 1.27 A3 0.45 0.55 0.65 L1 1.00 1.10 1.20 b 1.30 1.40 1.50 p 1.70 -- 1.90 b1 0.50 0.60 0.70 R 0.70 REF c 0.50 0.60 0.70 aaa 0.15 bbb 0.15 ccc 0.08 D D1 5.00 BSC 4.30 4.40 4.50 e 2.54 BSC ddd 0.10 E 7.00 BSC eee 0.05 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. silabs.com | Building a more connected world. Rev. 1.0 | 27 Si549 Data Sheet Package Outline 6.2 Package Outline (3.2x5 mm) The figure below illustrates the package details for the 5x3.2 mm Si549. The table below lists the values for the dimensions shown in the illustration. Figure 6.2. Si549 (3.2x5 mm) Outline Diagram Table 6.2. Package Diagram Dimensions (mm) Dimension MIN NOM MAX Dimension MIN NOM MAX A 1.02 1.17 1.33 E1 A2 0.50 0.55 0.60 L 0.8 0.9 1.0 A3 0.45 0.50 0.55 L1 0.45 0.55 0.65 b 0.54 0.64 0.74 L2 0.05 0.10 0.15 b1 0.54 0.64 0.75 L3 0.15 0.20 0.25 2.85 BSC D 5.00 BSC aaa 0.15 D1 4.65 BSC bbb 0.15 e 1.27 BSC ccc 0.08 e1 1.625 TYP ddd 0.10 E 3.20 BSC eee 0.05 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. silabs.com | Building a more connected world. Rev. 1.0 | 28 Si549 Data Sheet PCB Land Pattern 7. PCB Land Pattern 7.1 PCB Land Pattern (5x7 mm) The figure below illustrates the 5x7 mm PCB land pattern for the Si549. The table below lists the values for the dimensions shown in the illustration. Figure 7.1. Si549 (5x7 mm) PCB Land Pattern Table 7.1. PCB Land Pattern Dimensions (mm) Dimension (mm) Dimension (mm) C1 4.20 Y1 1.95 C2 6.05 X2 1.80 E 2.54 Y2 0.75 X1 1.55 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020D specification for Small Body Components. silabs.com | Building a more connected world. Rev. 1.0 | 29 Si549 Data Sheet PCB Land Pattern 7.2 PCB Land Pattern (3.2x5 mm) The figure below illustrates the 3.2x5.0 mm PCB land pattern for the Si549. The table below lists the values for the dimensions shown in the illustration. Figure 7.2. Si549 (3.2x5 mm) PCB Land Pattern Table 7.2. PCB Land Pattern Dimensions (mm) Dimension (mm) Dimension (mm) C1 2.70 X2 0.90 E 1.27 Y1 1.60 E1 4.30 Y2 0.70 X1 0.74 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. silabs.com | Building a more connected world. Rev. 1.0 | 30 Si549 Data Sheet Top Marking 8. Top Marking The figure below illustrates the mark specification for the Si549. The table below lists the line information. Figure 8.1. Mark Specification Table 8.1. Si549 Top Mark Description Line Position Description 1 1-8 2 1 x = Frequency Range Supported as described in the 1. Ordering Guide 2-7 6-digit custom Frequency Code as described in the 1. Ordering Guide "Si549", xxx = Ordering Option 1, Option 2, Option 3 (e.g. Si549AAA) 3 Trace Code Position 1 Pin 1 orientation mark (dot) Position 2 Product Revision (B) Position 3-5 Tiny Trace Code (3 alphanumeric characters per assembly release instructions) Position 6-7 Year (last two digits of the year), to be assigned by assembly site (ex: 2017 = 17) Position 8-9 Calendar Work Week number (1-53), to be assigned by assembly site silabs.com | Building a more connected world. Rev. 1.0 | 31 Si549 Data Sheet Revision History 9. Revision History Revision 1.0 August, 2018 * Added 20 ppm total stability option. Revision 0.75 March, 2018 * Added 25 ppm total stability option. Revision 0.5 December 11, 2017 * Initial release. silabs.com | Building a more connected world. Rev. 1.0 | 32 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. Available for Windows and iOS (CBGo only). www.silabs.com/CBPro Timing Portfolio www.silabs.com/timing SW/HW www.silabs.com/CBPro Quality www.silabs.com/quality Support and Community community.silabs.com Disclaimer Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. 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