IDT71028 CMOS STATIC RAM 1 MEG (256K x 4-BIT) Integrated Device Technology, Inc. FEATURES: DESCRIPTION: * 256K x 4 advanced high-speed CMOS static RAM * Equal access and cycle times -- Commercial: 12/15/17/20ns * One Chip Select plus one Output Enable pin * Bidirectional data Inputs and outputs directly TTL-compatible * Low power consumption via chip deselect * Available in 400 mil Plastic SOJ package The IDT71028 is a 1,048,576-bit high-speed static RAM organized as 256K x 4. It is fabricated using IDT's highperfomance, high-reliability CMOS technology. This state-ofthe-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for high-speed memory needs. The IDT71028 has an output enable pin which operates as fast as 6ns, with address access times as fast as 12ns. All bidirectional inputs and outputs of the IDT71028 are TTLcompatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71028 is packaged in 28-pin 400 mil Plastic SOJ package. FUNCTIONAL BLOCK DIAGRAM A0 1,048,576-BIT MEMORY ARRAY ADDRESS DECODER A17 I/O0 - I/O3 4 CS WE OE 4 I/O CONTROL CONTROL LOGIC 2966 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE 1996 Integrated Device Technology, Inc. AUGUST 1996 9.4 DSC-2966/5 1 IDT71028 CMOS STATIC RAM 1 MEG (256K x 4-BIT) COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CS OE GND VCC A17 A16 A15 A14 A13 A12 A11 NC I/O3 I/O2 I/O1 I/O0 1 28 27 2 3 26 25 4 24 5 23 6 SO28-6 22 7 21 8 9 20 10 19 11 18 17 12 13 16 15 14 (2) Rating Unit -0.5 to +7.0 V 0 to +70 C VTERM Terminal Voltage with Respect to GND TA Operating Temperature TBIAS Temperature Under Bias -55 to +125 C TSTG Storage Temperature -55 to +125 C PT Power Dissipation 1.25 W IOUT DC Output Current 50 mA WE NOTES: 2966 tbl 02 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 0.5V. 2966 drw 02 SOJ TOP VIEW TRUTH TABLE(1,2) CAPACITANCE (TA = +25C, f = 1.0MHz, SOJ package) CS OE WE I/O L L H DATAOUT Read Data L X L DATAIN Write Data CIN Input Capacitance CI/O I/O Capacitance Function Symbol L H H High-Z Output Disabled H X X High-Z Deselected - Standby (ISB) X X High-Z Deselected - Standby (ISB1) VHC(3) Com'l. NOTES: 1. H = VIH, L = VIL, x = Don't care. 2. VLC = 0.2V, VHC = VCC -0.2V. 3. Other inputs VHC or VLC. Parameter(1) Conditions Max. Unit VIN = 3dV 8 pF VOUT = 3dV 8 pF NOTE: 2966 tbl 03 1. This parameter is guaranteed by device characterization, but not production tested. 2966 tbl 01 RECOMMENDED DC OPERATING CONDITIONS Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V GND Supply Voltage 0 0 0 V VIH Input High Voltage -- VCC+0.5 V -- 0.8 V VIL Input Low Voltage 2.2 (1) -0.5 NOTE: 2966 tbl 04 1. VIL (min.) = -1.5V for pulse width less than 10ns, once per cycle. DC ELECTRICAL CHARACTERISTICS VCC = 5.0V 10% IDT71028 Symbol Parameter Test Condition Min. Max. Unit |ILI| Input Leakage Current VCC = Max., VIN = GND to VCC -- 5 A |ILO| Output Leakage Current VCC = Max., CS = VIH, VOUT = GND to VCC -- 5 A VOL Output Low Voltage IOL = 8mA, VCC = Min. -- 0.4 V VOH Output High Voltage IOH = -4mA, VCC = Min. 2.4 -- V 2966 tbl 05 9.4 2 IDT71028 CMOS STATIC RAM 1 MEG (256K x 4-BIT) COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS(1) (VCC = 5.0V 10%, VLC = 0.2V, VHC = VCC - 0.2V) 71028S12(3) Symbol Parameter 71028S15 71028S17 71028S20 Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Unit ICC Dynamic Operating Current, CS VIL, Outputs Open, VCC = Max., f = fMAX(2) 155 -- 150 -- 145 -- 145 -- mA ISB Standby Power Supply Current (TTL Level), CS VIH, Outputs Open, VCC = Max., f = fMAX(2) 35 -- 35 -- 35 -- 35 -- mA ISB1 Full Standby Power Supply Current (CMOS Level), CS VHC, Outputs Open, VCC = Max., f = 0(2), VIN VLC or VIN VHC 10 -- 10 -- 10 -- 10 -- mA NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing. 3. 12ns specification is preliminary. 2966 tbl 06 AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V AC Test Load See Figures 1 and 2 2966 tbl 07 5V 5V 480 480 DATA OUT 30pF DATA OUT 255 5pF* 2966 drw 03 255 2966 drw 04 *Including jig and scope capacitance. Figure 1. AC Test Load Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ) 9.4 3 IDT71028 CMOS STATIC RAM 1 MEG (256K x 4-BIT) COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%, Commercial Temperature Range) Symbol 71028S12(1) 71028S15 71028S17 71028S20 Min. Max. Min. Max. Min. Max. Min. Max. Parameter Unit Read Cycle tRC Read Cycle Time 12 -- 15 -- 17 -- 20 -- ns tAA Address Access Time -- 12 -- 15 -- 17 -- 20 ns tACS Chip Select Access Time -- 12 -- 15 -- 17 -- 20 ns (2) Chip Select to Output in Low-Z 3 -- 3 -- 3 -- 3 -- ns (2) Chip Deselect to Output in High-Z 0 6 0 7 0 8 0 8 ns tCLZ tCHZ tOE tOLZ Output Enable to Output Valid -- 6 -- 7 -- 8 -- 8 ns (2) Output Enable to Output in Low-Z 0 -- 0 -- 0 -- 0 -- ns (2) Output Disable to Output in High-Z 0 5 0 5 0 6 0 7 ns Output Hold from Address Change 4 -- 4 -- 4 -- 4 -- ns tOHZ tOH tPU (2) tPD(2) Chip Select to Power Up Time 0 -- 0 -- 0 -- 0 -- ns Chip Deselect to Power Down Time -- 12 -- 15 -- 17 -- 20 ns Write Cycle tWC Write Cycle Time 12 -- 15 -- 17 -- 20 -- ns tAW Address Valid to End of Write 10 -- 12 -- 13 -- 15 -- ns tCW Chip Select to End of Write 10 -- 12 -- 13 -- 15 -- ns tAS Address Set-up Time 0 -- 0 -- 0 -- 0 -- ns tWP Write Pulse Width 10 -- 12 -- 13 -- 15 -- ns tWR Write Recovery Time 0 -- 0 -- 0 -- 0 -- ns tDW Data Valid to End of Write 7 -- 8 -- 9 -- 9 -- ns tDH Data Hold Time 0 -- 0 -- 0 -- 0 -- ns tOW(2) Output Active from End of Write 3 -- 3 -- 3 -- 4 -- ns tWHZ(2) Write Enable to Output in High-Z 0 5 0 5 0 7 0 8 ns NOTES: 1. 12ns specification is preliminary. 2. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested. 9.4 2966 tbl 08 4 IDT71028 CMOS STATIC RAM 1 MEG (256K x 4-BIT) COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF READ CYCLE NO. 1(1) tRC ADDRESS tAA OE tOE tOLZ (5) CS tCLZ DATAOUT VCC SUPPLY ICC CURRENT ISB (5) tACS (3) tCHZ HIGH IMPEDANCE (5) tOHZ (5) DATAOUT VALID tPD tPU 2966 drw 05 TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4) tRC ADDRESS tAA tOH DATAOUT tOH PREVIOUS DATAOUT VALID DATAOUT VALID 2966 drw 6 NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. Transition is measured 200mV from steady state. 9.4 5 IDT71028 CMOS STATIC RAM 1 MEG (256K x 4-BIT) COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING)(1,2,3,5) tWC ADDRESS tAW CS tWP(3) tAS tWR WE tWHZ DATAOUT (6) tOW (6) HIGH IMPEDANCE (4) tDW DATAIN tCHZ (6) (4) tDH DATAIN VALID 2966 drw 07 TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1,2,5) tWC ADDRESS tAW CS tAS tWR tCW WE tDW DATAIN tDH DATAIN VALID 2966 drw 08 NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap of a LOW CS and a LOW WE. 3. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 4. During this period, I/O pins are in the output state, and input signals must not be applied. 5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 6. Transition is measured 200mV from steady state. 9.4 6 IDT71028 CMOS STATIC RAM 1 MEG (256K x 4-BIT) COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT 71028 Device Type S XX XX X Power Speed Package Process/ Temperature Range Blank Commercial (0C to +70C) Y 400-mil Small Outline J-Bend (SO28-6) 12 15 17 20 Speed in nanoseconds 2966 drw 09 9.4 7