LT3751
1
3751fc
Typical applicaTion
FeaTures
applicaTions
DescripTion
High Voltage Capacitor
Charger Controller with Regulation
The LT
®
3751 is a high input voltage capable flyback con-
troller designed to rapidly charge a large capacitor to a
user-adjustable high target voltage set by the transformer
turns ratio and three external resistors. Optionally, a feed-
back pin can be used to provide a low noise high voltage
regulated output.
The LT3751 has an integrated rail-to-rail MOSFET gate
driver that allows for efficient operation down to 4.75V.
A low 106mV differential current sense threshold voltage
accurately limits the peak switch current. Added pro-
tection is provided via user-selectable overvoltage and
undervoltage lockouts for both VCC and VTRANS. A typical
application can charge a 1000µF capacitor to 500V in less
than one second.
The CHARGE pin is used to initiate a new charge cycle and
provides ON/OFF control. The DONE pin indicates when
the capacitor has reached its programmed value and the
part has stopped charging. The FAULT pin indicates when
the LT3751 has shut down due to either VCC or VTRANS
voltage exceeding the user-programmed supply tolerances.
n Charges Any Size Capacitor
n Low Noise Output in Voltage Regulation Mode
n Stable Operation Under a No-Load Condition
n Integrated 2A MOSFET Gate Driver with Rail-to-Rail
Operation for VCC ≤ 8V
n Selectable 5.6V or 10.5V Internal Gate Drive
Voltage Clamp
n User-Selectable Over/Undervoltage Detect
n Easily Adjustable Output Voltage
n Primary or Secondary Side Output Voltage Sense
n Wide Input VCC Voltage Range (5V to 24V)
n Available in 20-Pin QFN 4mm × 5mm and 20-Lead
TSSOP Packages
n High Voltage Regulated Supply
n High Voltage Capacitor Charger
n Professional Photoflash Systems
n Emergency Strobe
n Security/Inventory Control Systems
n Detonators
CHARGE
CLAMP
VCC
DONE
FAULT
UVLO1
OVLO1
UVLO2
OVLO2
RDCM
RVOUT
HVGATE
LVGATE
CSP
CSN
FB
RVTRANS
T1
1:10 D1 500V
0 TO 150mA
VTRANS
24V
VCC
10µF
×2
3751 TA01a
LT3751
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY
GND RBG
40.2k
OFF ON
330µF
×2
VCC
24V 10µF
•
•
18.2k
40.2k
6mΩ
+
+
100µF
715k
1.74k
10nF
732Ω
VTRANS
VCC
TO
MICRO
0.47µF
374k
475k
475k
374k
LOAD CURRENT (mA)
0
OUTPUT VOLTAGE (V)
EFFICIENCY (%)
500
498
494
496
492
490
90
84
72
78
66
60
10050
3751 TA01b
150
OUTPUT VOLTAGE
EFFICIENCY
Load Regulation and Efficiency
L, LT , LT C , LT M , Linear Technology and the Linear logo are registered trademarks and
ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents including 6518733 and 6636021.
LT3751
2
3751fc
absoluTe MaxiMuM raTings
VCC, CHARGE, CLAMP ..............................................24V
DONE, FA U LT ............................................................24V
LVGATE (Note 8) .......................................................24V
VCC – LVGATE .............................................................8V
HVGATE ................................................................Note 9
RBG, CSP, CSN ...........................................................2V
FB ..............................................................................5V
Current into DONE Pin ........................................... ±1mA
Current into FA U LT Pin ........................................... ±1mA
Current into RVTRANS Pin....................................... ±1mA
(Note 1)
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING*PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3751EFE#PBF LT3751EFE#TRPBF LT3751FE 20-Lead Plastic TSSOP –40°C to 125°C
LT3751IFE#PBF LT3751IFE#TRPBF LT3751FE 20-Lead Plastic TSSOP –40°C to 125°C
LT3751EUFD#PBF LT3751EUFD#TRPBF 3751 20-Pin (4mm × 5mm) Plastic QFN –40°C to 125°C
LT3751IUFD#PBF LT3751IUFD#TRPBF 3751 20-Pin (4mm × 5mm) Plastic QFN –40°C to 125°C
LEAD BASED FINISH TAPE AND REEL PART MARKING*PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3751EFE LT3751EFE#TR LT3751FE 20-Lead Plastic TSSOP –40°C to 125°C
LT3751IFE LT3751IFE#TR LT3751FE 20-Lead Plastic TSSOP –40°C to 125°C
LT3751EUFD LT3751EUFD#TR 3751 20-Pin (4mm × 5mm) Plastic QFN –40°C to 125°C
LT3751IUFD LT3751IUFD#TR 3751 20-Pin (4mm × 5mm) Plastic QFN –40°C to 125°C
Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
Current into RVOUT Pin ........................................ ±10mA
Current into RDCM Pin......................................... ±10mA
Current into UVLO1 Pin .......................................... ±1mA
Current into UVLO2 Pin.......................................... ±1mA
Current into OVLO1 Pin .......................................... ±1mA
Current into OVLO2 Pin .......................................... ±1mA
Maximum Junction Temperature .......................... 125°C
Operating Temperature Range (Note 2).. –40°C to 125°C
Storage Temperature Range .................. –65°C to 125°C
FE PACKAGE
20-LEAD PLASTIC TSSOP
1
2
3
4
5
6
7
8
9
10
TOP VIEW
20
19
18
17
16
15
14
13
12
11
RVTRANS
UVLO1
OVLO1
UVLO2
OVLO2
FAULT
DONE
CHARGE
CLAMP
FB
RDCM
NC
RVOUT
NC
RBG
HVGATE
LVGATE
VCC
CSP
CSN
21
TJMAX = 125°C, θJA = 38°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
20 19 18 17
7 8
TOP VIEW
UFD PACKAGE
20-PIN (4mm × 5mm) PLASTIC QFN
9 10
6
5
4
3
2
1
11
12
13
14
15
16
OVLO1
UVLO2
OVLO2
FAULT
DONE
CHARGE
RVOUT
NC
RBG
HVGATE
LVGATE
VCC
UVLO1
RVTRANS
NC
RDCM
CLAMP
FB
CSN
CSP
21
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE TIED TO PCB
pin conFiguraTion
LT3751
3
3751fc
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VCC = CHARGE = 5V, CLAMP = 0V, unless otherwise noted. Individual
25kΩ resistors tied from 5V VTRANS supply to RVTRANS, RVOUT, RDCM, unless otherwise noted. (Note 2)
PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Voltage l4.75 24 V
RVTRANS Voltage (Note 3) l4.75 65 V
VCC Quiescent Current Not Switching, CHARGE = 5V
Not Switching, CHARGE = 0.3V
5.5
0
8
1
mA
µA
RVTRANS, RDCM Quiescent Current (Note 4)
Not Switching, CHARGE = 5V
Not Switching, CHARGE = 0.3V
l
35
40
0
45
1
µA
µA
RVOUT Quiescent Current (Note 4)
Not Switching, CHARGE = 5V
Not Switching, CHARGE = 0.3V
l
42
47
0
52
1
µA
µA
UVLO1, UVLO2, OVLO1, OVLO2 Clamp Voltage Measured at 1mA into Pin, CHARGE = 0V 55 V
RVTRANS, RVOUT, RDCM Clamp Voltage Measured at 1mA into Pin, CHARGE = 0V 60 V
CHARGE Pin Current CHARGE = 24V
CHARGE = 5V
CHARGE = 0V
425
60
1
µA
µA
µA
CHARGE Minimum Enable Voltage l1.5 V
CHARGE Maximum Disable Voltage IVCC ≤ 1µA l0.3 V
Minimum CHARGE Pin Low Time 20 μs
One-Shot Clock Period l32 38 44 μs
VOUT Comparator Trip Voltage Measured at RBG Pin l0.955 0.98 1.005 V
VOUT Comparator Overdrive 2µs Pulse Width,
RVTRANS, RVOUT = 25kΩ
RBG = 0.83kΩ
20
40
mV
DCM Comparator Trip Voltage Measured as VDRAIN – VTRANS, RDCM = 25kΩ, VCC = 4.75V
(Note 5)
350 600 900 mV
Current Limit Comparator Trip Voltage FB Pin = 0V
FB Pin = 1.3V
l
l
100
7
106
11
112
15
mV
mV
FB Pin Bias Current Current Sourced from FB Pin, Measured at FB Pin Voltage 64 300 nA
FB Pin Voltage (Note 6) l1.19 1.22 1.25 V
FB Pin Charge Mode Threshold 1.12 1.16 1.2 V
FB Pin Charge Mode Hysteresis (Note 7) 55 mV
FB Pin Overvoltage Mode Threshold 1.29 1.34 1.38 V
FB Pin Overvoltage Hysteresis 60 mV
DONE Output Signal High 100kΩ to 5V 5 V
DONE Output Signal Low 100kΩ to 5V 40 200 mV
DONE Leakage Current DONE = 5V 5 200 nA
FAULT Output Signal High 100kΩ to 5V 5 V
FAULT Output Signal Low 100kΩ to 5V 40 200 mV
FAULT Leakage Current FAULT = 5V 5 200 nA
UVLO1 Pin Current UVLO1 Pin Voltage = 1.24V l48.5 50 51.5 μA
UVLO2 Pin Current UVLO2 Pin Voltage = 1.24V l48.5 50 51.5 μA
OVLO1 Pin Current OVLO1 Pin Voltage = 1.24V l48.5 50 51.5 μA
OVLO2 Pin Current OVLO2 Pin Voltage = 1.24V l48.5 50 51.5 μA
LT3751
4
3751fc
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VCC = CHARGE = 5V, CLAMP = 0V, unless otherwise noted. Individual
25kΩ resistors tied from 5V VTRANS supply to RVTRANS, RVOUT, RDCM, unless otherwise noted. (Note 2)
PARAMETER CONDITIONS MIN TYP MAX UNITS
UVLO1 Threshold Measured from Pin to GND l1.195 1.225 1.255 V
UVLO2 Threshold Measured from Pin to GND l1.195 1.225 1.255 V
OVLO1 Threshold Measured from Pin to GND l1.195 1.225 1.255 V
OVLO2 Threshold Measured from Pin to GND l1.195 1.225 1.255 V
Gate Minimum High Time 0.7 μs
Gate Peak Pull-Up Current VCC = 5V, LVGATE Active
VCC = 12V, LVGATE Inactive
2.0
1.5
A
A
Gate Peak Pull-Down Current VCC = 5V, LVGATE Active
VCC = 12V, LVGATE Inactive
1.2
1.5
A
A
Gate Rise Time 10% → 90%, CGATE = 3.3nF (Note 8)
VCC = 5V, LVGATE Active
VCC = 12V, LVGATE Inactive
40
55
ns
ns
Gate Fall Time 90% → 10%, CGATE = 3.3nF (Note 8)
VCC = 5V, LVGATE Active
VCC = 12V, LVGATE Inactive
30
30
ns
ns
Gate High Voltage (Note 8):
VCC = 5V, LVGATE Active
VCC = 12V, LVGATE Inactive
VCC = 12V, LVGATE Inactive, CLAMP Pin = 5V
VCC = 24V, LVGATE Inactive
4.98
10
5
10
5
10.5
5.6
10.5
11.5
6.5
11.5
V
V
V
V
Gate Turn-Off Propagation Delay CGATE = 3.3nF
25mV Overdrive Applied to CSP Pin
180 ns
Gate Voltage Overshoot 500 mV
CLAMP Pin Threshold 1.6 V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3751E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design
characterization and correlation with statistical process controls. The
LT3751I is guaranteed over the full –40°C to 125°C operating junction
temperature range.
Note 3: A 60V internal clamp is connected to RVTRANS, RDCM, RVOUT,
UVLO1, UVLO2, OVLO1 and OVLO2. Resistors should be used such that
the pin currents do not exceed the Absolute Maximum Ratings.
Note 4: Currents will increase as pin voltages are taken higher than the
internal clamp voltage.
Note 5: Refer to Block Diagram for VTRANS and VDRAIN definitions.
Note 6: Low noise regulation of the output voltage requires a resistive
voltage divider from output voltage to FB pin. FB pin should not be
grounded in this configuration. Refer to the Typical Application diagram for
proper FB pin configuration.
Note 7: The feedback pin has built-in hysteresis that defines the boundary
between charge-only mode and low noise regulation mode.
Note 8: LVGATE should be used in parallel with HVGATE when VCC is less
than or equal to 8V (LVGATE active). When not in use, LVGATE should be
tied to VCC (LVGATE inactive).
Note 9: Do not apply a positive or negative voltage or current source to
HVGATE, otherwise permanent damage may occur.
LT3751
5
3751fc
Typical perForMance characTerisTics
VCC Pin Current VTRANS Supply Current CHARGE Pin Current
CHARGE Pin Minimum
Enable Voltage
CHARGE Pin Maximum
Disable Voltage DONE, FAULT Pin Voltage Low
VOUT Comparator Trip Voltage UVLO1 Trip Voltage UVLO1 Trip Current
PIN VOLTAGE (V)
0
PIN CURRENT (mA)
7
6
4
2
5
3
1
0168 20
3751 G01
24124
–40°C
25°C
125°C
PIN VOLTAGE (V)
0
IVTRANS CURRENT (µA)
150
145
135
120
125
140
130
115
110 4020 50
3751 G02
603010
–40°C
25°C
125°C
RVTRANS, RVOUT, RDCM = 25k
VCC, CHARGE = 5V
IVTRANS = IRVTRANS + IRVOUT + IRDCM
PIN VOLTAGE (V)
0
CURRENT (µA)
450
400
300
150
200
350
250
100
50
0168 20
3751 G03
24124
–40°C
25°C
125°C
–40
CHARGE PIN VOLTAGE (V)
1.3
1.2
1.0
0.7
0.8
1.1
0.9
0.6 40 600 80 100
3751 G04
12020
TEMPERATURE (°C)
–20
VCC = 5V
VCC = 12V
VCC = 24V
–40
CHARGE PIN VOLTAGE (V)
1.2
1.1
0.9
0.6
0.7
1.0
0.8
0.5 40 600 80 100
3751 G05
12020
TEMPERATURE (°C)
–20
VCC = 5V
VCC = 12V
VCC = 24V
–40
PIN LOW VOLTAGE (mV)
400
350
200
250
50
100
300
150
040 600 80 100
3751 G06
12020
TEMPERATURE (°C)
–20
1mA SINK
100µA SINK
10µA SINK
–40
VDRAIN – VTRANS VOLTAGE (V)
30.8
30.4
29.2
29.6
30.0
28.8
28.4 40 600 80 100
3751 G07
12020
TEMPERATURE (°C)
–20
RVTRANS, RVOUT = 25.5k (RTOL = 1%)
RBG = 833Ω
VTRANS = 5V
VTRANS = 12V
VTRANS = 24V
VTRANS = 48V
VTRANS = 72V
–40
UVLO1 PIN VOLTAGE (V)
1.236
1.234
1.228
1.230
1.232
1.226
1.224 40 600 80 100
3751 G08
12020
TEMPERATURE (°C)
–20
VCC = 5V
VCC = 12V
VCC = 24V
–40
UVLO1 PIN CURRENT (µA)
50.5
50.4
49.9
50.2
50.1
50.0
50.3
49.8
49.7 40 600 80 100
3751 G09
12020
TEMPERATURE (°C)
–20
VCC = 5V
VCC = 12V
VCC = 24V
LT3751
6
3751fc
Typical perForMance characTerisTics
Current Comparator Trip Voltage
(Charge Mode)
Current Comparator Minimum
Trip Voltage (Regulation Mode)
FB Pin Regulation
Mode Threshold
FB Pin Regulation
Mode Hysteresis
FB Pin Overvoltage Mode
Threshold Voltage
FB Pin Overvoltage
Mode Hysteresis
–40
VTH VOLTAGE (mV)
109.0
108.5
107.5
108.0
107.0 40 600 80 100
3751 G10
12020
TEMPERATURE (°C)
–20
VCC = 5V
VCC = 12V
VCC = 24V
VTH = VCSP – VCSN
–40
VTH VOLTAGE (mV)
13.0
12.4
12.6
12.8
12.2
12.0
11.4
11.6
11.2
11.8
11.0 40 600 80 100
3751 G11
12020
TEMPERATURE (°C)
–20
VCC = 5V
VCC = 12V
VCC = 24V
VTH = VCSP – VCSN
FB = 1.3V
–40
FB PIN VOLTAGE (V)
1.168
1.164
1.160
1.156
1.152 40 600 80 100
3751 G14
12020
TEMPERATURE (°C)
–20
VCC = 5V
VCC = 12V
VCC = 24V
–40
HYSTERESIS (mV)
60
58
56
54
52
50 40 600 80 100
3751 G15
12020
TEMPERATURE (°C)
–20
VCC = 5V
VCC = 12V
VCC = 24V
–40
FB PIN VOLTAGE (V)
1.356
1.354
1.352
1.350
1.348
1.346
1.344 40 600 80 100
3751 G16
12020
TEMPERATURE (°C)
–20
VCC = 5V
VCC = 12V
VCC = 24V
–40
HYSTERESIS (mV)
61.0
60.6
60.2
59.8
59.4
59.0 40 600 80 100
3751 G17
12020
TEMPERATURE (°C)
–20
VCC = 5V
VCC = 12V
VCC = 24V
CLAMP Pin Threshold
–40
CLAMP PIN VOLTAGE (V)
1.9
1.8
1.7
1.6
1.5
1.4 400 80
3751 G18
120
TEMPERATURE (°C)
VCC = 12V
VCC = 24V
FB Pin Voltage
FB Pin Bias Current
–40
FB PIN VOLTAGE (V)
1.223
1.222
1.220
1.221
1.219 40 600 80 100
3751 G12
12020
TEMPERATURE (°C)
–20
VCC = 5V
VCC = 12V
VCC = 24V
–40
SOURCED PIN CURRENT (nA)
100
90
80
70
60
50
40 40 600 80 100
3751 G13
12020
TEMPERATURE (°C)
–20
MEASURED AT FB PIN VOLTAGE
VCC = 12V
LT3751
7
3751fc
Typical perForMance characTerisTics
RVTRANS (Pin 1/Pin 19): Transformer Supply Sense Pin.
Connect a resistor between the RVTRANS pin and the
VTRANS supply. Refer to Table 2 for proper sizing of the
RVTRANS resistor. The minimum operation voltage for
VTRANS is 4.75V.
UVLO1 (Pin 2/Pin 20): VTRANS Undervoltage Lockout Pin.
Senses when VTRANS drops below:
VUVLO1 =1.225+50µA•RUVLO1
and trips the FAULT latch low, disabling switching. After
VTRANS rises above VUVLO1, toggling the CHARGE pin
reactivates switching.
OVLO1 (Pin 3/Pin 1): VTRANS Overvoltage Lockout Pin.
Senses when VTRANS rises above:
VOVLO1 =1.225+50µA•ROVLO1
and trips the FAULT latch low, disabling switching. After
VTRANS drops below VOVLO1, toggling the CHARGE pin
reactivates switching.
UVLO2 (Pin 4/Pin 2): VCC Undervoltage Lockout Pin.
Senses when VCC drops below:
VUVLO2 =1.225+50µA•RUVLO2
and trips the FAULT latch low, disabling switching. After
VCC rises above VUVLO2, toggling the CHARGE pin reac-
tivates switching.
OVLO2 (Pin 5/Pin 3): VCC Overvoltage Lockout Pin. Senses
when VCC rises above:
VOVLO2 =1.225+50µA•ROVLO2
and trips the FAULT latch low, disabling switching. After
VCC drops below VOVLO2, toggling the CHARGE pin reac-
tivates switching.
FAULT (Pin 6/Pin 4): Open Collector Indication Pin. When
either VTRANS or VCC exceeds the user-selected voltage
range, or an internal UVLO condition occurs, a transistor
turns on. The part will stop switching. This pin needs a
proper pull-up resistor or current source.
HVGATE Pin Clamp Voltage HVGATE Pin Clamp Voltage
–40
HVGATE PIN VOLTAGE (V)
11.0
10.9
10.8
10.7
10.5
10.6
10.4 40 600 80 100
3751 G19
12020
TEMPERATURE (°C)
–20
VCC = 24V
CLAMP = 0V
–40
HVGATE PIN VOLTAGE (V)
5.70
5.65
5.60
5.55
5.50 40 600 80 100
3751 G20
12020
TEMPERATURE (°C)
–20
VCC = 12V
CLAMP = 12V
pin FuncTions
DCM Trip Voltage (VDRAIN – VTRANS),
RVTRANS = RDCM = 25kΩ
–40
DCM TRIP VOLTAGE (V)
0.64
0.62
0.60
0.58
0.56
0.54 400 80
3751 G21
120
TEMPERATURE (°C)
VTRANS = 5V
VTRANS = 12V
VTRANS = 24V
VTRANS = 48V
(TSSOP/QFN)
LT3751
8
3751fc
pin FuncTions
DONE (Pin 7/ Pin 5): Open Collector Indication Pin. When
the target output voltage (charge mode) is reached or the
FAULT pin goes low, a transistor turns on. This pin needs
a proper pull-up resistor or current source.
CHARGE (Pin 8/Pin 6): Charge Pin. Initiates a new charge
cycle (charge mode) or enables the part (regulation mode)
when driven higher than 1.5V. Bring this pin below 0.3V
to discontinue charging and put the part into shutdown.
Turn-on ramp rates should be between 10ns to 10ms.
CHARGE pin should not be directly ramped with VCC or
LT3751 may not properly initialize.
CLAMP (Pin 9/Pin 7): Internal Clamp Voltage Selection
Pin. Tie this pin to VCC to activate the internal 5.6V gate
driver clamp. Tie this pin to ground to activate the internal
10.5V gate driver clamp.
FB (Pin 10/Pin 8): Feedback Regulation Pin. Use this pin
to achieve low noise voltage regulation. FB is internally
regulated to 1.22V when a resistive divider is tied from
this pin to the output. FB pin should not float. Tie FB pin
to either a resistor divider or ground.
CSN (Pin 11/Pin 9): Negative Current Sense Pin. Senses
external NMOS source current. Connect to local RSENSE
ground connection for proper Kelvin sensing. The current
limit is set by 106mV/RSENSE.
CSP (Pin 12/Pin 10): Positive Current Sense Pin. Senses
NMOS source current. Connect the NMOS source terminal
and the current sense resistor to this pin. The current
limit is fixed at 106mV/RSENSE in charge mode. The cur-
rent limit can be reduced to a minimum 11mV/RSENSE in
regulation mode.
VCC (Pin 13/Pin 11): Input Supply Pin. Must be locally by-
passed with high grade (X5R or better) ceramic capacitor.
The minimum operating voltage for VCC is 4.75V.
LVGATE (Pin 14/Pin 12): Low Voltage Gate Pin. Connect
the NMOS gate terminal to this pin when operating VCC
below 8V. The internal gate driver will drive the voltage to
the VCC rail. When operating VCC higher than 8V, tie this
pin directly to VCC.
HVGATE (Pin 15/Pin 13): High Voltage Gate Pin. Connect
NMOS gate terminal to this pin for all VCC operating volt-
ages. Internal gate driver will drive the voltage to within
VCC – 2V during each switch cycle.
RBG (Pin 16/Pin 14): Bias Generation Pin. Generates a bias
current set by 0.98V/RBG. Select RBG to achieve desired
resistance for RDCM, RVOUT, and RVTRANS.
NC (Pins 17, 19/Pins 15, 18): No Connection.
RVOUT (Pin 18/Pin 16): Output Voltage Sense Pin. Devel-
ops a current proportional to the output capacitor volt-
age. Connect a resistor between this pin and the drain of
NMOS such that:
VOUT =0.98 •N•RVOUT
RBG
−VDIODE
when RVOUT is set equal to RVTRANS, otherwise:
VOUT =N•0.98 •RVOUT
RBG
+VTRANS
RVOUT
RVTRANS
−1
−VDIODE
where VDIODE = forward voltage drop of diode D1 (refer
to the Block Diagram).
RDCM (Pin 20/Pin 17): Discontinuous Mode Sense Pin.
Senses when the external NMOS drain is equal to 20µA •
RDCM + VTRANS and initiates the next switch cycle. Place
a resistor equal to 0.45 times the resistor on the RVTRANS
pin between this pin and VDRAIN.
GND (Pin 21/Pin 21): Ground. Tie directly to local ground
plane.
LT3751
9
3751fc
block DiagraM
+
FB
CSN
CSP
LVGATE
HVGATE
CLAMP
3751 BD
START-UP
ONE-SHOT
CHARGE
VCC
OTLO
MASTER
LATCH
S
Q
R
QENABLE
GATE
DRIVER
ONOFF
DONE
FAULT
100k
10µF
100k
S
Q
R
Q
VCC
12V
INTERNAL
UVLO
3.8V
VCC –
+
+
–
–
+
+
–
–
+
55V
55V
UVLO1
OVLO1
UVLO2
OVLO2
55V
55V
RUVLO1
191k
RUVLO2
191k
ROVLO1
240k
ROVLO2
240k
1.22V
REFERENCE
UVLO/OVLO
COMPARATORS
RBG
1.33k
GND RBG
TO VOUT
COMPARATOR
VOUT
COMPARATOR
–
+
DCM
ONE-SHOT
–
+
DCM
COMPARATOR
26kHz ONE-SHOT
CLOCK
S
R
Q
Q
COUNTER
26kHz
ONE-SHOT
CLOCK
SWITCH
LATCH
0.98V
REFERENCE
DIFF. AMP
COMPARATOR
WITH
INTERNAL
60V CLAMPS
1.22V
REFERENCE
GATE DRIVE
CIRCUITRY
60V
RVOUT
60V
RDCM
–
+
–
+
–
+
RESET
CLK
COUNT
+–
+–
TIMING AND PEAK
CURRENT CONTROL
–
+
26kHz
ONE-SHOT
CLOCK
MODE
CONTROL
DIE
TEMP 160ºC
1.22V
REFERENCE
•
•
60V
RVOUT
40.2k
RDCM
18.2k
M1
VCC
RSENSE
12mΩ
ERROR
AMP
A1
11mV TO 106mV
MODULATION
106mV
162mV
RVTRANS
RVTRANS
40.2k 10µF
47µF
×2
D1
T1
1:10
PRIMARY
SECONDARY
+
VOUT
450V
COUT
RFBH
3.65M
RFBL
10k
VTRANS
12V
VTRANS
VCC
TO CHARGE
ONE-SHOT
VCC
VCC
VDRAIN
10nF
AUXILIARY
MAIN
FAULT
LATCH
LT3751
10
3751fc
operaTion
The LT3751 can be used as either a fast, efficient high
voltage capacitor charger controller or as a high voltage,
low noise voltage regulator. The FB pin voltage determines
one of the three primary modes: charge mode, low noise
regulation, or no-load operation (see Figure 1).
Figure 1. FB Pin Modes
CHARGE MODE
When the FB pin voltage is below 1.16V, the LT3751 acts
as a rapid capacitor charger. The charging operation has
four basic states for charge mode steady-state operation
(see Figure 2).
1. Start-Up
The first switching cycle is initiated approximately 2µs
after the CHARGE pin is raised high. During this phase,
the start-up one-shot enables the master latch turning
on the external NMOS and beginning the first switching
cycle. After start-up, the master latch will remain in the
switching-enable state until the target output voltage is
reached or a fault condition occurs.
The LT3751 utilizes circuitry to protect against transformer
primary current entering a runaway condition and remains
in start-up mode until the DCM comparator has enough
headroom. Refer to the Start-Up Protection section for
more detail.
2. Primary-Side Charging
When the NMOS switch latch is set, and depending on the
use of LVGATE, the gate driver rapidly charges the gate
pin to VCC – 2V in high voltage applications or directly to
VCC in low voltage applications (refer to the Application
FB PIN
VOLTAGE
3751 F01
NO-LOAD
OPERATION
REGULATION
CHARGE
MODE
1.34V
1.16V
0.0V
Figure 2. Idealized Charging Waveforms
VTRANS – VDS(ON)
LPRI
VTRANS – VDS(ON)
–N (VTRANS – VDS(ON))
VOUT + VDIODE
VOUT + VDIODE
LSEC
IPK
IPK
N
–(VOUT + VDIODE)
N
ILPRI
ILSEC
VPRI
VSEC
VDRAIN
VOUT + VDIODE
N
VTRANS +
VTRANS
VDS(ON)
3751 F02
VDS(ON)
1.
PRIMARY-SIDE
CHARGING
2.
SECONDARY
ENERGY TRANSFER
AND OUTPUT
DETECTION
3.
DISCONTINUOUS
MODE
DETECTION
LT3751
11
3751fc
Information section for proper use of LVGATE). With the
gate driver output high, the external NMOS turns on,
forcing VTRANS – VDS(ON) across the primary winding.
Consequently, current in the primary coil rises linearly at
a rate (VTRANS – VDS(ON))/LPRI. The input voltage is mir-
rored on the secondary winding –N • (VTRANS – VDS(ON))
which reverse-biases the diode and prevents current flow
in the secondary winding. Thus, energy is stored in the
core of the transformer.
3. Secondary Energy Transfer
When current limit is reached, the current limit comparator
resets the NMOS switch latch and the device enters the
third phase of operation, secondary energy transfer. The
energy stored in the transformer core forward-biases the
diode and current flows into the output capacitor. During
this time, the output voltage (neglecting the diode drop)
is reflected back to the primary coil. If the target output
voltage is reached, the VOUT comparator resets the master
latch and the DONE pin goes low. Otherwise, the device
enters the next phase of operation.
4. Discontinuous Mode Detection
During secondary energy transfer to the output capaci-
tor, (VOUT + VDIODE)/N will appear across the primary
winding. A transformer with no energy cannot support a
DC voltage, so the voltage across the primary will decay
to zero. In other words, the drain of the NMOS will ring
down from VTRANS + (VOUT + VDIODE)/N to VTRANS. When
the drain voltage falls to VTRANS + 20µA • RDCM, the DCM
operaTion
Figure 3. Start-Up Protection Circuitry
Figure 4. DCM Comparator Thresholds
comparator sets the NMOS switch latch and a new switch
cycle begins. Steps 2-4 continue until the target output
voltage is reached.
Start-Up Protection
The LT3751 at start-up, when the output voltage is very
low (or shorted), usually does not have enough VDRAIN
node voltage to trip the DCM comparator. The part in start-
up mode uses the internal 26kHz clock and an auxiliary
current comparator. Figure 3 shows a simplified block
diagram of the start-up circuitry.
FROM AUXILIARY
CURRENT
COMPARATOR
3751 F03
FROM CLK
FROM GATE
DRIVER ON
FROM DCM
COMPARATOR
RESET
INCREMENT
COUNTER 2
RESET
INCREMENT
COUNTER 1
–
+
SWITCH
LATCH
START-UP
(DCM THRESHOLD = VTH1)
BELOW VTH2
(WAIT FOR TIME-OUT)
VDRAIN
3751 F04
VOUT
DCM
1-SHOT
VTH1 VTH2
V
!
BOUNDARY-MODE
(DCM THRESHOLD = VTH2)
t
Toggling the CHARGE pin always generates a start-up
one-shot to turn on the external switch, initiating the charg-
ing process. After the start-up one-shot, the LT3751 waits
for either the DCM comparator to generate a one-shot or
the output of the start-up protection circuitry going high,
which ever comes first. If the switch drain node, VDRAIN,
is below the DCM comparator threshold (see Entering
Normal Boundary Mode), the DCM comparator will never
fire and the start-up circuitry is dominant.
LT3751
12
3751fc
operaTion
At very low output voltages, the boundary-mode switching
cycle period increases significantly such that the energy
stored in the transformer core is not depleted before the
next clock cycle. In this situation, the clock may initiate
another switching cycle before the secondary winding
current reaches zero and cause the LT3751 to enter
continuous-mode conduction. Normally, this is not a
problem; however, if the secondary energy transfer time
is much longer than the CLK period, significant primary
current overshoot can occur. This is due to the non-zero
starting point of the primary current when the switch turns
on and the finite speed of the current comparator.
The LT3751 startup circuitry adds an auxiliary current
comparator with a trip level 50% higher than the nominal
trip level. Every time the auxiliary current comparator
trips, the required clock count between switching cycles is
incremented by one. This allows more time for secondary
energy transfer.
Counter 1 in Figure 3 is set to its maximum count when
the first DCM comparator one-shot is generated. If no
DCM one-shot is initiated in normal boundary-mode
operation during a maximum count of approximately
500µs, the LT3751 re-enters start-up mode and the count
is returned to zero.
Note that Counter 1 is initialized to zero at start-up. Thus,
the output of the startup circuitry will go high after one clock
cycle. Counter 2 is reset when the gate driver goes high.
This repeats until either the auxiliary current comparator
increments the required clock count or until VDRAIN is high
enough to sustain normal operation described in steps 2
through 4 in the previous section.
Entering Normal Boundary Mode
The LT3751 has two DCM comparator thresholds that
are dependent on what mode the part is in, either start-
up mode or normal boundary-mode, and the state of the
mode latch. For boundary-mode switching, the LT3751
requires the DCM sense voltage (VDRAIN) to exceed VTRANS
by the ΔDCM comparator threshold, ΔVDRAIN:
ΔVDRAIN = (40µA + IOFFSET) • RDCM – 40µA • RVTRANS
where IOFFSET is mode dependent. The DCM one-shot
signal is negative edge triggered by the switch node,
VDRAIN, and indicates that the energy in the secondary
winding has depleted. For this to happen, VDRAIN must
exceed VTRANS + ΔVDRAIN prior to its negative edge; oth-
erwise, the DCM comparator will not generate a one-shot
to initiate the next switching cycle. The part would remain
stuck in this state indefinitely; however, the LT3751 uses
the start-up protection circuitry to jumpstart switching if
the DCM comparator does not generate a one-shot after
a maximum time-out of 500µs.
Figure 4 shows a typical VDRAIN node waveform with
a test circuit voltage clamp applied to the output. VTH1
is the start-up threshold and is set internally by forcing
IOFFSET to 40μA. Once the first DCM one-shot is initiated,
the mode latch is set to boundary-mode. The mode latch
then sets the clock count to maximum (500µs) and lowers
the DCM comparator threshold to VTH2 (IOFFSET = 20μA).
This provides needed hysteresis between start-up mode
and boundary-mode operation.
LOW NOISE REGULATION
Low noise voltage regulation can be achieved by adding
a resistive divider from the output node to the LT3751 FB
pin. At start-up (FB pin below 1.16V), the LT3751 enters
the charge mode to rapidly charge the output capacitor.
Once the FB pin is within the threshold range of 1.16V
to 1.34V, the part enters into low noise regulation. The
switching methodology in regulation mimics that used
in the capacitor charging mode, but with the addition of
peak current and duty cycle control techniques. Figure 5
shows the steady state operation for both regulation
techniques. Figure 6 shows how both techniques are
combined to provide stable, low noise operation over a
wide load and supply range.
During heavy load conditions, the LT3751 sets the peak
primary current to its maximum value, 106mV/RSENSE and
sets the maximum duty cycle to approximately 95%. This
allows for maximum power delivery. At very light loads,
the opposite occurs, and the LT3751 reduces the peak
primary current to approximately one tenth its maximum
value while modulating the duty cycle below 10%. The
LT3751 controls moderate loads with a combination of
peak current mode control and duty cycle control.
LT3751
13
3751fc
operaTion
Figure 5. Modes of Operation (Steady State)
Figure 6. Regulation Technique
3751 F05
26kHz
ONE-SHOT
CLK
26kHz
ONE-SHOT
CLK
26kHz
ONE-SHOT
CLK
26kHz
ONE-SHOT
CLK
SWITCH
ENABLE
IPRI
SWITCH
ENABLE
IPRI
110%
VOUT, NOM
105%
VOUT, NOM
VOUT
1/10TH IPK
IPRI
MAXIMUM
PEAK CURRENT NO BLANKING
PEAK CURRENT
CONTROL
FORCED
BLANKING
tPER ≈ 38µs
CHARGE MODE
HEAVY LOAD OPERATION NO-LOAD OPERATION
...
...
...
...
...
...
t
tt
SWITCH
ENABLE
IPRI
tPER ≈ 38µs
DUTY CYCLE
CONTROL
DUTY CYCLE
CONTROL
FORCED
BLANKING
LIGHT LOAD OPERATION
...
...
...
...
...
...
t
3751 F06
LIGHT LOAD CHARGE
MODE
MODERATE
LOAD
HEAVY LOAD
ILIM( ) DUTY CYCLE ( )
IMAX
1/10
IMAX
95%
10%
LOAD
CURRENT
NO-LOAD
OPERATION
0
LT3751
14
3751fc
operaTion
Periodic Refresh
When the LT3751 enters regulation, the internal circuitry
deactivates switching when the internal one-shot clock
is high. The clock operates at a 1/20th duty cycle with a
minimum blank time of 1.5µs. This reset pulse is timed to
drastically reduce switching frequency content within the
audio spectrum and is active during all loading conditions.
Each reset pulse guarantees at least one energy cycle. A
minimum load is required to prevent the LT3751 from
entering no-load operation.
Heavy Load Operation
The LT3751 enters peak current mode control at higher
output load conditions. The control loop maximizes the
number of switch cycles between each reset pulse. Since
the control scheme operates in boundary mode, the reso-
nant boundary-mode period changes with varying peak
primary current:
Period=IPK •LPRI •1
VTRANS
+N
VOUT
and the power output is proportional to the peak primary
current:
POUT =1/ 2 •IPK
1
VTRANS
+N
VOUT
Noise becomes an issue at very low load currents. The
LT3751 remedies this problem by setting the lower peak
current limit to one tenth the maximum level and begins
to employ duty-cycle control.
Light Load Operation
The LT3751 uses duty cycle control to drastically reduce
audible noise in both the transformer (mechanical) and
the ceramic capacitors (piezoelectric effects). Internal
control circuitry forces a one-shot condition at a periodic
rate greater than 20kHz and out of the audio spectrum.
The regulation loop then determines the number of pulses
that are required to maintain the correct output voltage.
Figure 5 shows the use of duty-cycle control.
No-Load Operation
The LT3751 can remain in low noise regulation at very low
loading conditions. Below a certain load current threshold
(Light Load Operation), the output voltage would continue
to increase and a runaway condition could occur. This is
due to the periodic one-shot forced by the periodic refresh
circuitry. By design, the LT3751 has built-in overvoltage
protection associated with the FB pin.
When the FB pin voltage exceeds 1.34V (±20mV), the
LT3751 enters no-load operation. No-load operation does
not reset with the one-shot clock. Instead, the pulse train
is completely load-dependent. These bursts are asynchro-
nous and can contain long periods of inactivity. This allows
regulation at a no-load condition but with the increase of
audible noise and voltage ripple. Note that when operating
with no-load, the output voltage will increase 10% above
the nominal output voltage.
LT3751
15
3751fc
applicaTions inForMaTion
The LT3751 charger controller can be optimized for either
capacitor charging only or low noise regulation applica-
tions. Several equations are provided to aid in the design
process.
Safety Warning
Large capacitors charged to high voltage can deliver a lethal
amount of energy if handled improperly. It is particularly
important to observe appropriate safety measures when
designing the LT3751 into applications. First, create a
discharge circuit that allows the designer to safely dis-
charge the output capacitor. Second, adequately space
high voltage nodes from adjacent traces to satisfy printed
circuit board voltage breakdown requirements.
Selecting Operating Mode
Tie the FB pin to GND to operate the LT3751 as a capacitor
charger. In this mode, the LT3751 charges the output at
peak primary current in boundary mode operation. This
constitutes maximum power delivery and yields the fast-
est charge times. Power delivery is halted once the output
reaches the desired output voltage set by the RVOUT and
RBG pins.
Tie a resistor divider from the FB pin to VOUT and GND
to operate the LT3751 as a low noise voltage regulator
(refer to Low Noise regulation section for proper design
procedures). The LT3751 operates as a voltage regulator
using both peak current and duty cycle modulation to
vary output current during different loading conditions.
Selecting Component Parameters
Most designs start with the initial selection of VTRANS,
VOUT, COUT, and either charge time, tCHARGE, (capacitor
charger) or POUT,MAX (regulator). These design inputs
are then used to select the transformer ratio, N, the peak
primary current, IPK, and the primary inductance, LPRI.
Figure 7 can be used as a rough guide for maximum power
output for a given VTRANS and IPK.
Selecting Transformer Turns Ratio
The transformer ratio, N, should be selected based on
the input and output voltages. Smaller N values equate
to faster charge times and larger available output power.
Note that drastically reducing N below the VOUT/VTRANS
ratio will increase the flyback voltage on the drain of the
NMOS and increase the current through the output diode.
The ratio, N, should not be drastically increased either, due
to the increased capacitance, N2 • CSEC, reflected to the
primary. A good choice is to select N equal to VOUT/VTRANS.
N≤VOUT
VTRANS
Choosing Capacitor Charger IPK
When operating the LT3751 as capacitor charger, choose
IPK based on the required capacitor charge time, tCHARGE,
and the initial design inputs.
IPK =2•N•VTRANS +VOUT
( )
•COUT •VOUT
Efficiency •VTRANS •tCHARGE −td
( )
The converter efficiency varies over the output voltage
range. The IPK equation is based on the average effi-
ciency over the entire charging period. Several factors can
cause the charge time to increase. Efficiency is the most
dominant factor and is mainly affected by the transformer
winding resistance, core losses, leakage inductance, and
transistor RDS. Most applications have overall efficiencies
above 70%.
Figure 7. Maximum Power Output
PEAK PRIMARY CURRENT (A)
VTRANS (V)
3751 F07
100
10
20
30
40
50
60
70
80
90
01 10 100
P = 20 WATTS
P = 50 WATTS
P = 100 WATTS
LT3751
16
3751fc
applicaTions inForMaTion
The total propagation delay, td, is the second most dominant
factor that affects efficiency and is the summation of gate
driver on-off propagation delays and the discharge time
associated with the secondary winding capacitance. There
are two effective methods to reduce the total propagation
delay. First, reduce the total capacitance on the secondary
winding, most notably the diode capacitance. Second,
reduce the total required NMOS gate charge. Figure 8
shows the effect of large secondary capacitance.
The energy stored in the secondary winding capacitance
is ½ • CSEC • VOUT2. This energy is reflected to the primary
when the diode stops forward conduction. If the reflected
capacitance is greater than the total NMOS drain capaci-
tance, the drain of the NMOS power switch goes negative
and its intrinsic body diode conducts. It takes some time
for this energy to be dissipated and thus adds to the total
propagation delay.
Choosing Regulator Maximum IPK
The IPK parameter in regulation mode is calculated based
on the desired maximum output power instead of charge
time like that in a capacitor charger application.
IPK =2•POUT(AVG)
Efficiency •1
V
TRANS
+N
V
OUT
Note that the LT3751 regulation scheme varies the peak
current based on the output load current. The maximum
IPK is only reached during charge mode or during heavy
load conditions where output power is maximized.
Figure 8. Effect of Secondary Winding Capacitance
VDRAIN
3751 F08
ISEC
IPRI
NO SEC.
CAPACITANCE
SEC. DISCHARGE t
Transformer Design
The transformer’s primary inductance, LPRI, is determined
by the desired VOUT and previously calculated N and IPK
parameters. Use the following equation to select LPRI:
LPRI =3µs•VOUT
IPK •N
The previous equation guarantees that the VOUT comparator
has enough time to sense the flyback waveform and trip
the DONE pin latch. Operating VOUT significantly higher
than that used to calculate LPRI could result in a runaway
condition and overcharge the output capacitor.
The LPRI equation is adequate for most regulator applica-
tions. Note that if both IPK and N are increased significantly
for a given VTRANS and VOUT, the maximum IPK will not be
reached within the refresh clock period. This will result in
a lower than expected maximum output power. To prevent
this from occurring, maintain the condition in the follow-
ing equation.
LPRI <38µs
IPK •1
VTRANS
+N
VOUT
The upper constraint on LPRI can be reduced by increas-
ing VTRANS and starting the design process over. The best
regulation occurs when operating the boundary-mode
frequency above 100kHz (refer to Operation section for
boundary-mode definition).
Figure 9 defines the maximum boundary-mode switching
frequency when operating at a desired output power level
and is normalized to LPRI/POUT (μH/Watt). The relation-
ship of output power, boundary-mode frequency, IPK, and
primary inductance can be used as a guide throughout
the design process.
LT3751
17
3751fc
Figure 9. Maximum Switching Frequency
PEAK PRIMARY CURRENT (A)
LPRI/WATT (µH/WATT)
3751 F09
10.000
0.010
0.100
1.000
0.001 1 10 100
fMAX = 50kHz
fMAX = 100kHz
fMAX = 200kHz
applicaTions inForMaTion
Table 1. Recommended Transformers
MANUFACTURER PART NUMBER SIZE L × W × H (mm) MAXIMUM IPRI (A) LPRI (µH) TURNS RATIO (PRI:SEC)
Coilcraft
www.coilcraft.com
DA2033-AL
DA2034-AL
GA3459-BL
GA3460-BL
HA4060-AL
HA3994-AL
17.4 × 24.1 × 10.2
20.6 × 30 × 11.3
32.65 × 26.75 × 14
32.65 × 26.75 × 14
34.29 × 26.75 × 14
34.29 × 28.75 × 14
5
10
20
50
2
5
10
10
5
2.5
300
7.5
1:10
1:10
1:10
1:10
1:3
2:1:3:3*
Würth Elektronik/Midcom
www.we-online.com
750032051
750032052
750310349
750310355
28.7 × 22 × 11.4
28.7 × 22 × 11.4
36.5 × 42 × 23
36.5 × 42 × 23
5
10
20
50
10
10
5
2.5
1:10
1:10
1:10
1:10
Sumida
www.sumida.com
C8117
C8119
PS07-299
PS07-300
23 × 18.6 × 10.8
32.2 × 27 × 14
32.5 × 26.5 × 13.5
32.5 × 26.5 × 13.5
5
10
20
50
10
10
5
2.5
1:10
1:10
1:10
1:10
TDK
www.tdk.com
DCT15EFD-U44S003
DCT20EFD-U32S003
DCT25EFD-U27S005
22.5 × 16.5 × 8.5
30 × 22 × 12
27.5 × 33 × 15.5
5
10
20
10
10
5
1:10
1:10
1:10
*Transformer has three secondaries where the ratio is designated as PRI:SEC1:SEC2:SEC3
RVTRANS, RVOUT and RDCM Selection
RVTRANS sets the common-mode reference voltage for
both the DCM comparator and VOUT comparator. Select
RVTRANS from Table 2 based on the transformer supply
voltage range, VTRANS, and the maximum trip voltage,
ΔVDRAIN (VDRAIN-VTRANS).
The RVTRANS pin is connected to an internal 40µA current
source. Pin current increases as the pin voltage is taken
higher than the internal 60V Zener clamp. The LT3751 can
operate from VTRANS greater than the 60V internal Zener
clamps by limiting the RVTRANS pin current to 250µA.
Operating VTRANS above 200V requires the use of resis-
tor dividers. Tw o applications are presented that operate
Table 2. Suggested RVTRANS, RVOUT, and RDCM Values
VTRANS Range
(V)
∆VDRAIN RANGE
(V)
RVTRANS
(kΩ)
RVOUT
(kΩ)
RDCM
(kΩ)
4.75 to 55 0 to 5 5.11 5.11 2.32
4.75 to 60 2.5 to 50 25.5 25.5 11.5
5 to 80 40.2 40.2 18.2
8 to 80 8 to 160 80.6 80.6 36.5
80 to 200 2mA • RVOUT
VTRANS
−
55V
0.25
VTRANS
−
55V
0.25
0.86 • RVTRANS
>200 Resistor Divider Dependent Use Resistor Divider Use Resistor Divider Use Resistor Divider
LT3751
18
3751fc
applicaTions inForMaTion
with VTRANS between 100V and 400V (refer to Typical
Applications section). Consult applications engineering
for applications with VTRANS operating above 400V.
RVOUT is required for capacitor charger applications but
may be removed for regulator applications. Note that the
VOUT comparator can be used as secondary protection
for regulator applications. If the VOUT comparator is used
for protection, design VOUT,TRIP 15% to 20% higher than
the regulation voltage. Tie the RVOUT pin to ground when
RVOUT resistor is removed.
RDCM needs to be properly sized in relation to RVTRANS.
Improper selection of RDCM can lead to undesired switching
operation at low output voltages. Use Table 2 to size RDCM.
Parasitic capacitance on RVTRANS, RVOUT, and RDCM should
be minimized. Capacitances on these nodes slow down
the response times of the VOUT and DCM comparators.
Keep the distance between the resistor and pin short. It
is recommended to remove all ground and power planes
underneath these pins and their respective components
(refer to the recommended board layout at the end of
this section).
RBG Selection
RBG sets the trip current (0.98/RBG) and is directly related
to the selection of RVOUT. The best accuracy is achieved
with a trip current between 100µA and 2mA. Choosing
RVOUT from Table 2 meets this criterion. Use the following
Table 3. Recommended NMOS Transistors
MANUFACTURER PART NUMBER ID (A) VDS(MAX) (V) RDS(ON) (mΩ) QG(TOT) (nC) PACKAGE
Fairchild Semiconductor
www.fairchildsemi.com
FDS2582
FQB19N20L
FQP34N20L
FQD12N20L
FQB4N80
4.1
21
31
12
3.9
150
200
200
200
800
66
140
75
280
3600
11
27
55
16
19
SO-8
D2PAK
TO-220
DPAK
D2PAK
On Semiconductor
www.onsemi.com
MTD6N15T4G
NTD12N10T4G
NTB30N20T4G
NTB52N10T4G
6
12
30
52
150
100
200
100
300
165
81
30
15
14
75
72
DPAK
DPAK
D2PAK
D2PAK
Vishay
www.vishay.com
Si7820DN
Si7818DN
SUP33N20-60P
2.6
3.4
33
200
150
200
240
135
60
12.1
20
53
1212-8
1212-8
TO-220
equation to size RBG (VTRANS ≤ 80V):
RBG =0.98 •N•RVOUT
VOUT,TRIP +VDIODE
Tie RBG pin to ground when not using the VOUT compara-
tor. Consult applications engineering for calculating RBG
when operating VTRANS above 80V.
NMOS Switch Selection
Choose an external NMOS power switch with minimal gate
charge and on-resistance that satisfies current limit and
voltage break-down requirements. The gate is nominally
driven to VCC – 2V during each charge cycle. Ensure that
this does not exceed the maximum gate to source voltage
rating of the NMOS but enhances the channel enough to
minimize the on-resistance.
Similarly, the maximum drain-source voltage rating of the
NMOS must exceed VTRANS + VOUT/N or the magnitude of
the leakage inductance spike, whichever is greater. The
maximum instantaneous drain current rating must exceed
selected current limit. Because the switching period de-
creases with output voltage, the average current though
the NMOS is greatest when the output is nearly charged
and is given by:
IAVG,M =IPK •VOUT(PK)
2(V
OUT(PK)
+N•V
TRANS
)
See Table 3 for recommended external NMOS transistors.
LT3751
19
3751fc
applicaTions inForMaTion
Gate Driver Operation
The LT3751 gate driver has an internal, selectable 10.5V
or 5.6V clamp with up to 2A current capability (using
LVGATE). For 10.5V operation, tie CLAMP pin to ground,
and for 5.6V operation, tie the CLAMP pin to the VCC pin.
Choose a clamp voltage that does not exceed the NMOS
manufacturer’s maximum VGS ratings. The 5.6V clamp
can also be used to reduce LT3751 power dissipation
and increase efficiency when using logic-level FETs. The
typical gate driver overshoot voltage is 0.5V above the
clamp voltage.
The LT3751’s gate driver also incorporates a PMOS pull-
up device via the LVGATE pin. The PMOS pull-up driver
should only be used for VCC applications of 8V or below.
Operating LVGATE with VCC above 8V will cause perma-
nent damage to the part. LVGATE is active when tied to
HVGATE and allows rail-to-rail gate driver operation. This
is especially useful for low VCC applications, allowing bet-
ter NMOS drive capability. It also provides the fastest rise
times, given the larger 2A current capability verses 1.5A
when using only HVGATE.
Output Diode Selection
The output diode(s) are selected based on the maximum
repetitive reverse voltage (VRRM) and the average forward
current (IF(AV)). The output diode’s VRRM should exceed
VOUT + N • VTRANS. The output diode’s IF(AV) should exceed
IPK/2N, the average short-circuit current. The average diode
current is also a function of the output voltage.
Table 4. Recommended Output Diodes
MANUFACTURER PART NUMBER IF(AV) (A) VRRM (V) TRR (ns) PACKAGE
Central Semiconductor
www.centralsemi.com
CMR1U-10M
CMSH2-60M
CMSH5-40
1
2
5
1000
60
40
100 SMA
SMA
SMC
Fairchild Semiconductor
www.fairchildsemi.com
ES3J
ES1G
ES1J
3
1
1
600
400
600
35
35
35
SMC
SMA
SMA
On Semiconductor
www.onsemi.com
MURS360
MURA260
MURA160
3
2
1
600
600
600
75
75
75
SMC
SMA
SMA
Vishay
www.vishay.com
USB260
US1G
US1M
GURB5H60
2
1
1
5
600
400
1000
600
30
50
75
30
SMB
SMA
SMA
D2PAK
IAVG =IPK •VTRANS
2•(VOUT +N•VTRANS )
The highest average diode current occurs at low output
voltages and decreases as the output voltage increases.
Reverse recovery time, reverse bias leakage and junction
capacitance should also be considered. All affect the over-
all charging efficiency. Excessive diode reverse recovery
times can cause appreciable discharging of the output
capacitor, thereby increasing charge time. Choose a diode
with a reverse recovery time of less than 100ns. Diode
leakage current under high reverse bias bleeds the output
capacitor of charge and increases charge time. Choose a
diode that has minimal reverse bias leakage current. Diode
junction capacitance is reflected back to the primary, and
energy is lost during the NMOS intrinsic diode conduction.
Choose a diode with minimal junction capacitance. Table 4
recommends several output diodes for various output
voltages that have adequate reverse recovery times.
Setting Current Limit
Placing a sense resistor from the positive sense pin, CSP,
to the negative sense pin, CSN, sets the maximum peak
switch current. The maximum current limit is nominally
106mV/RSENSE. The power rating of the current sense
resistor must exceed:
P
RSENSE ≥I2PK •RSENSE
3
VOUT(PK)
VOUT(PK) +N•VTRANS
Additionally, there is approximately a 180ns propaga-
tion delay from the time that peak current limit is
LT3751
20
3751fc
applicaTions inForMaTion
detected to when the gate transitions to the low state.
This delay increases the peak current limit by (VTRANS)
(180ns)/LPRI.
Sense resistor inductance (LRSENSE) is another source of
current limit error. LRSENSE creates an input offset voltage
(VOS) to the current comparator and causes the current
comparator to trip early. VOS can be calculated as:
VOS =VTRANS •LRSENSE
LPRIMARY
The change in current limit becomes VOS/RSENSE. The error
is more significant for applications using large di/dt ratios
in the transformer primary. It is recommended to use very
low inductance (< 2nH) sense resistors. Several resistors
can be placed in parallel to help reduce the inductance.
Care should also be taken in placement of the sense lines.
The negative return line, CSN, must be a dedicated trace
to the low side resistor terminal. Haphazardly routing the
CSN connection to the ground plane can cause inaccurate
current limit and can also cause an undesirable discontinu-
ous charging profile.
DONE and FAULT Pin Design
Both the DONE and FAULT pins require proper pull-up
resistors or current sources. Limit pin current to 1mA
into either of these pins. 100kΩ pull-up resistors are
recommended for most applications. Both the DONE and
FAULT pins are latched in the low output state. Resetting
either latch requires the CHARGE pin to be toggled. A fault
condition will also cause the DONE pin to go low. A third,
non-latching condition occurs during startup when the
CHARGE pin is driven high. During this start-up condition,
both the DONE and FAULT
pins will go low for several micro
seconds. This indicates the internal rails are still ramping
to their proper levels. External RC filters may be added to
both indication pins to remove start-up indication. Time
constants for the RC filter should be between 5µs to 20µs.
Under/Overvoltage Lockout
The LT3751 provides user-programmable under and
overvoltage lockouts for both VCC and VTRANS. Use the
equations in the Pin Functions section for proper selection
of resistor values. When under/overvoltage lockout com-
parators are tripped, the master latch is disabled, power
delivery is halted, and the FAULT pin goes low.
Adequate supply bulk capacitors should be used to reduce
power supply voltage ripple that could cause false tripping
during normal switching operation. Additional filtering
may be required due to the high input impedance of the
under/overvoltage lockout pins to prevent false tripping.
Individual capacitors ranging from 100pF to 1nF may be
placed between each of the UVLO1, UVLO2, OVLO1 and
OVLO2 pins and ground. Disable the undervoltage lockouts
by directly connecting the UVLO1 and UVLO2 pins to VCC.
Disable the overvoltage lockouts by directly connecting
the OVLO1 and OVLO2 pins to ground.
The LT3751 provides internal Zener clamping diodes to
protect itself in shutdown when VTRANS is operated above
55V. Supply voltages should only be applied to UVLO1,
UVLO2, OVLO1 and OVLO2 with series resistance such
that the Absolute Maximum pin currents are not exceeded.
Pin current can be calculated using:
IPIN =VAPPLIED −55V
RSERIES
Note that in shutdown, RVTRANS, RVOUT
, RDCM, UVLO1,
UVLO2, OVLO1 and OVLO2 currents increase significantly
when operating VTRANS above the Zener clamp voltages
and are inversely proportional to the external series pin
resistances.
NMOS Snubber Design
The transformer leakage inductance causes a parasitic
voltage spike on the drain of the power NMOS switch dur-
ing the turn-off transition. Transformer leakage inductance
effects become more apparent at high peak primary cur-
rents. The worst-case magnitude of the voltage spike is
determined by the energy stored in the leakage inductance
and the total capacitance on the VDRAIN node.
VD,LEAK =LLEAK •I2PK
CVDRAIN
Tw o problems can arise from large VD,LEAK. First, the
magnitude of the spike may require an NMOS with an
LT3751
21
3751fc
Figure 11. Effects of RC Snubber
Figure 10. RC Snubber Circuit
applicaTions inForMaTion
unnecessarily high V(BR)DSS which equates to a larger
RDS(ON). Secondly, the VDRAIN node will ring—possibly
below ground—causing false tripping of the DCM com-
parator or damage to the NMOS switch (see Figure 11).
Both issues can be remedied using a snubber. If leakage
inductance causes issues, it is recommended to use a RC
snubber in parallel with the primary winding, as shown
in Figure 10. Size CSNUB and RSNUB based on the desired
leakage spike voltage, known leakage inductance, and an
RC time constant less than 1µs. Otherwise, the leakage
voltage spike can cause false tripping of the VOUT com-
parator and stop charging prematurely.
Figure 11 shows the effect of the RC snubber resulting in
a lower voltage spike and faster settling time.
3751 F11
LPRI
RSNUB
CSNUB
LLEAK
•
•
CVDRAIN
0V
0V
3751 F12
VDRAIN
(WITH
SNUBBER)
VDRAIN
(WITHOUT
SNUBBER)
IPRI
NMOS DIODE
CONDUCTS
LOW NOISE REGULATION
The LT3751 has the option to provide a low noise regu-
lated output voltage when using a resistive voltage divider
from the output node to the FB pin. Refer to the Selecting
Component Parameters section to design the transformer,
NMOS power switch, output diode, and sense resistor.
Use the following equations to select the feedback resis-
tor values based on the power dissipation and desired
output voltage:
RFBH =VOUT −1.22
( )
2
P
D
; Top Feedback Resistor
RFBL =1.22
VOUT −1.22
•RFBH ; Bottom Feedback Resistor
RFBH, depending on output voltage and type used, may
require several smaller values placed in series. This will
reduce the risk of arcing and damage to the feedback resis-
tors. Consult the manufacturer’s rated voltage specification
for safe operation of the feedback resistors.
The LT3751 has a minimum periodic refresh frequency
limit of 23kHz. This drastically reduces switching frequency
components in the audio spectrum. The LT3751 can oper-
ate with no-load, but the regulation scheme switches to
no-load operation and audible noise and output voltage
ripple increase. This can be avoided by operating with a
minimum load current.
Minimum Load Current
Periodic refresh circuitry requires an average minimum
load current to avoid entering no-load operation. Usually,
the feedback resistors should be adequate to provide this
minimum load current.
ILOAD(MIN) ≥LPRI •I
2
PK •23kHz
100 •V
OUT
IPK is the peak primary current at maximum power delivery.
The LT3751 will enter no-load operation if the minimum
load current is not met. No-load operation will prevent the
application from entering a runaway condition; however,
the output voltage will increase 10% over the nominal
regulated voltage.
LT3751
22
3751fc
applicaTions inForMaTion
Large Signal Stability
Large signal stability can be an issue when audible noise
is a concern. Figure 12 shows that the problem originates
from the one-shot clock and the output voltage ripple. The
load must be constrained such that the output voltage
ripple does not exceed the regulation range of the error
amplifier within one clock period (approximately 6mV
referred to the FB pin).
The output capacitance should be increased if oscillations
occur or audible noise is present. Use Figure 13 to deter-
mine the maximum load for a given output capacitance to
maintain low audible noise operation. A small capacitor
can also be added from the FB pin to ground to lower the
ripple injected into FB pin.
Small Signal Stability
The LT3751’s error amplifier is internally compensated to
increase its operating range but requires the converter’s
output node to be the dominant pole. Small signal stability
constraints become more prevalent during heavy load-
ing conditions where the dominant output pole moves
to higher frequency and closer to the internal feedback
poles and zeros. The feedback loop requires the output
pole frequency to remain below 200Hz to guarantee small
signal stability. This allows smaller RLOAD values than the
large signal constraint. Thus, small signal issues should
not arise if the large signal constraint is met.
Board Layout
The high voltage operation of the LT3751 demands care-
ful attention to the board layout, observing the following
points:
1. Minimize the area of the high voltage end of the second-
ary winding.
2. Provide sufficient spacing for all high voltage nodes
(NMOS drain, VOUT and secondary winding of the
transformer) in order to meet the breakdown voltage
requirements.
3. Keep the electrical path formed by CVTRANS, the primary
of T1, and the drain of the NMOS as short as possible.
Increasing the length of this path effectively increases
the leakage inductance of T1, potentially resulting in an
overvoltage condition on the drain of the NMOS.
4. Reduce the total node capacitance on the RVOUT and
RDCM pins by removing any ground or power planes
underneath the RDCM and RVOUT pads and traces.
Parasitic capacitance can cause unwanted behavior
on these pins.
5. Thermal vias should be added underneath the Exposed
Pad, Pin 21, to enhance the LT3751’s thermal perfor-
mance. These vias should go directly to a large area of
ground plane.
6. Isolated applications require galvanic separation of the
output-side ground and primary-side ground. Adequate
spacing between both ground planes is needed to meet
voltage safety requirements.
Figure 13. COUT(MIN) vs Output Power
OUTPUT POWER (W)
0
COUT, MIN (µF)
30
25
15
5
20
10
0150
3751 F14
20050 100
VOUT = 150V
VOUT = 300V
VOUT = 600V
Figure 12. Voltage Ripple Stability Constraint
VOUT
3751 F13
26kHz
ONE-SHOT
CLK
IPRI
LOAD
DROOP
LT3751
23
3751fc
applicaTions inForMaTion
1
2
3
4
5
6
3751 F15
16
15
14
13
12
11
LT3751
VCC
VTRANS
POWER
GND
CHARGE
ANALOG
GND
RUVLO2
ANALOG
GND VIAS
7 8 9 10
20 19 18 17
ROVLO2
RFAULT
RDONE
RUVLO1
ROVLO1
RVTRANS
RDCM
RBG
RVOUT
ANALOG
GND
VCC
CVCC
ANALOG
GND
SINGLE
POINT
GND
CFB
RFBL
RFBH3
POWER
GND RETURN
RSENSE
CVTRANS1
+
CVTRANS2 CVTRANS3
+
CVTRANS4
POWER
GND RETURN
••
SECONDARY
PRIMARY
T1
1:N
CVOUT1 CVOUT2
DVOUT
+
POWER
GND
VOUT
RFBH2 RFBH1
M1
REMOVE COPPER
FROM ALL SUB-LAYERS
(SEE ITEM 4)
Figure 14. QFN Package Recommended Board Layout (Not to Scale)
LT3751
24
3751fc
Figure 15. TSSOP Package Recommended Board Layout (Not to Scale)
3751 F16
LT3751
VCC
VTRANS
POWER
GND
CHARGE
RVTRANS
RUVLO1
ROVLO1
RUVLO2
ROVLO2
RFAULT
RDONE
RSENSE
RDCM
RBG
RVOUT
ANALOG
GND
ANALOG
GND
VCC
CVCC
ANALOG
GND
CFB
RFBL POWER
GND RETURN
CVTRANS1 CVTRANS2 CVTRANS3
+
CVOUT2
+
+
CVTRANS4
POWER
GND RETURN
•
•
SECONDARY
PRIMARY
T1
1:N
CVOUT1
DVOUT VOUT
RFBH2
RFBH1
M1
REMOVE COPPER
FROM ALL SUB-LAYERS
(SEE ITEM 4)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
applicaTions inForMaTion
LT3751
25
3751fc
Typical applicaTions
42A Capacitor Charger
CHARGE
CLAMP
VCC
DONE
FAULT
UVLO1
OVLO1
UVLO2
OVLO2
RDCM
RVOUT
HVGATE
LVGATE
CSP
CSN
FB
RVTRANS
T1**
1:10 D1 VOUT
500V
VTRANS
12V TO 24V
VCC
3751 TA02
LT3751
GND RBG
R6
40.2k
OFF ON
C3
1000µF
C2
10µF
×3
VCC
12V TO 24V C1
10µF
•
•
R7, 18.2k
R8, 40.2k
M1, M2*
R5
2.5mΩ
D2***
+
+
C4
1200µF
R9
787Ω
VTRANS
VCC
R10, 100k
R11, 100k
R1, 191k
R2, 475k
R3, 191k
R4, 475k
C1: 25V X5R OR X7R CERAMIC CAPACITOR
C2: 25V X5R OR X7R CERAMIC CAPACITOR
C3: 25V ELECTROLYTIC
C4: HITACHI FX22L122Y 1200µF, 550V ELECTROLYTIC
OR: CORNELL DUBILIER DCMC192T550CE2B 1900µF, 550V ELECTROLYTIC
D1, D2: VISHAY GURB5H60 600V, 5A ULTRAFAST RECTIFIER
M1, M2: 2 PARALLEL VISHAY SUP33N20-60P 200V, 33A NMOS
R1 THRU R4, R6 THRU R11: USE 1% 0805 RESISTORS
R5: USE 2 PARALLEL 5mΩ IRC LR SERIES 2512 RESISTORS
T1: COILCRAFT GA3460-BL 50A SURACE MOUNT TRANSFORMER
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY
FOR ANY VOUT VOLTAGE BETWEEN
50V AND 500V SELECT R9 ACCORDING TO:
4.7nF
Y-RATED
* M1, M2 REQUIRES PROPER
HEATSINK/THERMAL DISSIPATION
TO MEET MANUFACTURER’S SPECIFICATIONS
** THERMAL DISSIPATION OF T1 WILL LIMIT
THE CHARGE/DISCHARGE DUTY CYCLE OF C4
*** D2 MAY BE OMITTED FOR OUTPUT
VOLTAGE OPERATION BELOW 300V
Efficiency Output Capacitor Charge Times Charging Waveform
OUTPUT VOLTAGE (V)
50
EFFICIENCY (%)
85
80
75
70
65 450
3751 TA02b
250 350150
VTRANS = 12V
VTRANS = 24V
OUTPUT CAPACITANCE (µF)
200
CHARGE TIME (ms)
1200
800
400
01000
3751 TA02c
1200800600400
VOUT = 500V, VTRANS = 24V
VOUT = 500V, VTRANS = 12V
VOUT = 300V, VTRANS = 24V
VOUT = 300V, VTRANS = 12V
VOUT = 100V,
VTRANS = 24V
VOUT = 100V,
VTRANS = 12V
100ms/DIV 3751 TA02d
VOUT = 500V
VTRANS = 24V
C4 = 1200µF
AVERAGE
INPUT
CURRENT
5A/DIV
VOUT
100V/DIV
R9 =0.98 •N•40.2kΩ
VOUT +V
DIODE
LT3751
26
3751fc
Typical applicaTions
Efficiency (VOUT = 500V) Load Regulation (VOUT = 500V)
Steady-State Operation with
100mA Load Current
High Voltage Regulator
CHARGE
CLAMP
VCC
DONE
FAULT
UVLO1
OVLO1
UVLO2
OVLO2
RDCM
RVOUT
HVGATE
LVGATE
CSP
CSN
FB
RVTRANS
T1*
1:10 D1 VOUT
100V TO 500V
VTRANS
5V TO 24V
VCC
3751 TA04
LT3751
GND RBG
R6
40.2k
OFF ON
C3
680µF
C2
5× 2.2µF
C1
10µF
•
•
R7, 18.2k
R8, 40.2k
M1*
R5
6mΩ
+
+
C4***
100µF
R9
VTRANS
VCC
R2, 475k
R1, 69.8k
R4, 475k
R3, 69.8k
C1: 25V X5R OR X7R CERAMIC
C2: 25V X5R OR X7R CERAMIC
C3: 25V ELECTROLYTIC
C5: TDK CKG57NX7R2J474M
D1: VISHAY US1M 1000V
M1: FAIRCHILD FQP34N20L
R1 THRU R4, R6 THRU R9, R11: USE 1% 0805
R5: IRC LR SERIES 2512 RESISTORS
R10: USE 200V 1206 RESISTOR(S)
T1: COILCRAFT GA3459-AL
TO
MICRO
VCC
5V TO 24V
C5
0.47µF
R11
R10**
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY
C6
10nF
* M1 AND T1 REQUIRE PROPER
HEATSINK/THERMAL DISSIPATION
TO MEET MANUFACTURER’S SPECIFICATIONS
** DEPENDING ON DESIRED OUTPUT VOLTAGES,
R10 MUST BE SPLIT INTO MULTIPLE RESISTORS,
TO MEET MANUFACTURER’S VOLTAGE SPECIFICATION.
*** C4 MUST BE SIZED TO MEET LARGE SIGNAL
STABILITY CRITERIA DESCRIBED IN THE
APPLICATIONS INFORMATION SECTION
10µs/DIV 3751 TA03b
VDRAIN
50V/DIV
IPRI
10A/DIV
VOUT
AC COUPLED
2V/DIV
ILOAD (mA)
0
EFFICIENCY (%)
90
85
75
80
70
65
60 200
3751 TA03c
100 15050
VTRANS = 24V
VTRANS = 12V
VTRANS = 5V
ILOAD (mA)
0
OUTPUT VOLTAGE (V)
515
510
505
500
495 200
3751 TA03d
100 15050
VTRANS = 24V
VTRANS = 12V
VTRANS = 5V
10µs/DIV 3751 TA03e
VDRAIN
50V/DIV
IPRI
10A/DIV
VOUT
COUPLED
2V/DIV
Steady-State Operation with
1.1mA Load Current
Suggested Component Values
VOUT
(V)
IOUT(MAX) (mA)
AT VTRANS = 5V,
5% VOUT DEFLECTION
IOUT(MAX)
(mA)
AT VTRANS = 24V,
5% VOUT DEFLECTION
R9
(kΩ)
R11
(kΩ)
R10
(kΩ)
100 180 270 3.32 0.383 30.9
200 110 315 1.65 0.768 124
300 75 245 1.10 1.13 274
400 55 200 0.825 1.54 499
500†40 170 Tie to GND 1.74 715
†Transformer primary inductance limits VOUT comparator operation to VOUT = 400VMAX. RVOUT
and RBG should be tied to ground when operating VOUT above 400V.
LT3751
27
3751fc
VCC
DONE
FAULT
UVLO1
OVLO1
UVLO2
OVLO2
CHARGE
CLAMP
RDCM
RVOUT
HVGATE
LVGATE
FB
CSP
CSN
RVTRANS
T1*
1:3 D1F1, 1A VOUT
50V TO 500V
VTRANS
100V TO
400VDC
VCC
3751 TA04a
LT3751
GND RBG
R6
625k
OFF ON
C3
47µF
C2
2.2µF
×5
C1
10µF
•
•
R8
417k
R10
208k
R5
20Ω
R7, 96.2k
M1**
R13
68mΩ
R12
R9
67.3k
R11
32.1k
D2
+
+
C4
220µF
VTRANS
VCC
R2, 9M
R1, 1.5M
R4, 475k
R3, 154k
C1: 25V X5R OR X7R CERAMIC
C2: 630V X5R OR X7R CERAMIC
C3: 450V ILLINOIS CAP 476CKE450MQW
C4: 50V TO 500V ELECTROLYTIC
C5: TDK CKG57NX7R2J474M
D1, D2: VISHAY US1M 1000V
F1: BUSSMANN PCB-1-R
M1: FAIRCHILD FQB4N80
R1, R2: 2 X 1206 RESISTORS IN SERIES, 1%
R3 THRU R5, R9, R12: 0805 RESISTORS, 1%
R6, R10: 3 X 1206 RESISTORS IN SERIES, 0.1%
R7, R11: 0805 RESISTORS, 0.1%
R8: 3 X 1206 RESISTORS IN SERIES, 1%
R13: IRC LR SERIES 1206 RESISTOR, 1%
T1: COILCRAFT HA4060-AL
* T1 REQUIRES PROPER THERMAL MANAGEMENT
TO ACHIEVE DESIRED OUTPUT POWER LEVELS
** M1 REQUIRES PROPER HEAT SINK/THERMAL
DISSIPATION TO MEET MANUFACTURER’S
SPECIFICATIONS
FOR ANY OUTPUT VOLTAGE BETWEEN 50V
TO 500V, SET R12 GIVEN BY:
TO
MICRO
VCC
10V TO 24V
C5
0.47µF
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY
4.7nF
Y-RATED
INPUT VOLTAGE (V)
100
VOUT,TRIP (V)
520
510
300
200 400
500
490
530
850
700
550
400
1000
3751 TA04b
VOUT,TRIP
CHARGE TIME
CHARGE TIME (ms)
OUTPUT VOLTAGE (V)
50
EFFICIENCY (%)
85
90
95
80
75
250 450
150 350
70
65
100
3751 TA04c
VIN = 100V
VIN = 250V
VIN = 400V
100ms/DIV 3751 TA04d
VOUT = 500V
VTRANS = 300V
VOUT = 12V
AVERAGE
INPUT
CURRENT
200mA/DIV
CHARGE
10V/DIV
VOUT
100V/DIV
Output Trip Voltage
and Charge Time
(VOUT = 500V, COUT = 220µF) Efficiency Charging Waveform
1.6A High Input Voltage, Isolated Capacitor Charger
Typical applicaTions
R12 =0.98
VOUT,TRIP
3•R10
+40µA •2
LT3751
28
3751fc
CHARGE
CLAMP
VCC
DONE
FAULT
UVLO1
OVLO1
UVLO2
OVLO2
RDCM
RVOUT
HVGATE
LVGATE
CSP
CSN
FB
RVTRANS
T1*
1:3 D1F1, 1A VOUT
100V TO 500V
VTRANS
100V TO
400VDC
VCC
3751 TA05a
LT3751
GND RBG
R6, 625k
OFF ON
C3
47µF
C2
2.2µF
×5
C1
10µF
•
•
R8, 417k
R5, 20Ω
R7, 97.6k
M1**
R12
68mΩ
R9
67.3k
D2
+
+
C4
100µF
VTRANS
VCC
R2, 9M
R1, 1.5M
R4, 475k
R3, 154k
C1: 25V X5R OR X7R CERAMIC
C2: 630V X5R OR X7R CERAMIC
C3: 450V ILLINOIS CAP 476CKE450MQW
C4: 50V TO 500V ELECTROLYTIC
C5: TDK CKG57NX7R2J474M
C6: 6.3V X5R OR X7R CERAMIC
D1, D2: VISHAY US1M 1000V
F1: BUSSMANN PCB-1-R
M1: FAIRCHILD FQB4N80
R1, R2: 2 X 1206 RESISTORS IN SERIES, 1%
R3 THRU R5, R7, R9, R11: 0805 RESISTORS, 1%
R6, R8: 3 X 1206 RESISTORS IN SERIES, 1%
R10: 1206 RESISTOR(S), 1%
R12: IRC LR SERIES 1206 RESISTOR, 1%
T1: COILCRAFT HA4060-AL
* T1 REQUIRES PROPER THERMAL MANAGEMENT
TO ACHIEVE DESIRED OUTPUT POWER LEVELS
** M1 REQUIRES PROPER HEAT SINK/THERMAL
DISSIPATION TO MEET MANUFACTURER’S
SPECIFICATIONS
*** DEPENDING ON DESIRED OUTPUT VOLTAGE,
R10 MUST BE SPLIT INTO MULTIPLE RESISTORS
TO MEET MANUFACTURER’S VOLTAGE SPECIFICATION
TO
MICRO
VCC
10V TO
24V
C5
0.47µF
R11
R10***
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY
C6
10nF
OUTPUT CURRENT (mA)
0
40
EFFICIENCY (%)
50
60
70
80
90
25 50
3751 TA05b
75
VIN = 400V
VIN = 250V
VIN = 100V
INPUT VOLTAGE (V)
100
395
OUTPUT VOLTAGE (V)
396
397
398
200 300
3751 TA05c
400
IOUT = 25mA
IOUT = 50mA
IOUT = 10mA
10µs/DIV 3751 TA05d
VIN = 200V
VOUT = 400V
VDRAIN
100V/DIV
IPRI
2A/DIV
Efficiency Line Regulation
Steady-State Operation with
50mA Load Current
Typical applicaTions
High Input Voltage, High Output Voltage Regulator
Suggested Component Values
VOUT
(V)
IOUT(MAX) (mA)
AT VTRANS = 100V,
1% VOUT DEFLECTION
IOUT(MAX) (mA)
AT VTRANS = 400V,
1% VOUT DEFLECTION
R10
(kΩ)
R11
(kΩ)
100 55 130 30.9 0.383
200 110 150 124 0.768
300 95 175 274 1.13
400 80 130 499 1.54
500 65 140 715 1.74
LT3751
29
3751fc
Isolated 282V Voltage Regulator
Typical applicaTions
DONE
FAULT
UVLO1
OVLO1
UVLO2
OVLO2
VCC
CHARGE
CLAMP
RDCM
RVOUT
VIN
GND
OC
OPTO
VCC
COMP
FB
HVGATE
LVGATE
FB
CSP
CSN
RVTRANS
T1
D5 VOUT
282V
225mA
VTRANS
VCC
3751 TA06a
LT3751
GND RBG
R3
210k
OFF ON
C3
22µF
×2
C1
100pF
C4
1µF
×2
C2
1µF
•
•
•
R7
475Ω
R4
105k
R5
210k
M2
R6
40mΩ R18
1k
R8
2.49k
R17
221k
R16
249k
4.7nF
Y RATED
R1
49.9k
D1 D6 U2
LT4430
VTRANS
VCC
R10, 4.3M
R9, 2.7M
R2, 10Ω ISOLATION BOUNDARY
Npb
Np Ns
Nsb
R12, 442k
R11, 84.5k
C1, C8: 16V COG CERAMIC
C2: 16V X5R OR X74 CERAMIC
C3: 350V ELECTROLYTIC
C4: 250V X5R OR X7R CERAMIC
C5, C6, C11, C12: 630V X5R OR X7R CERAMIC
C7: 350V ELECTROLYTIC
C9, C10: 25V X5R OR X7R CERAMIC
F1: 250V, 2A FUSE
R1: 2010 RESISTOR, 1%
R2, R3, R6, R16, R17: 1206 RESISTORS, 1%
R4, R5: TWO 1206 RESISTORS IN SERIES, 1%
R7 THRU R12, R15 THRU R20: 0805 RESISTORS, 1%
D1: 12V ZENER
D2: VISHAY MURS140
D3: VISHAY P6KE200A
D4: VISHAY MURS160
D5: STMICROELECTRONICS STTH112A
D6: VISHAY BAT54
D7: NXP SEMICONDUCTORS BAS516
M1: VISHAY IRF830
M2: STMICROELECTRONICS STB11NM60FD
T1: TDK SRW24LQ
(Np:Ns:Npb:Nsb = 1:2:0.08:0.08)
U1: NEC PS2801-1
U2: LINEAR TECHNOLOGY LT4430
TO
MICRO
VTRANS
100V TO
200VDC
F1, 2A
C5
0.01µF
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY
D4
D3
M1
C9
3.3µF
C8
22nF
R19
3.16k
C10
0.47µF
•
R15
5.11Ω
D7
U1
D2
R20
274Ω
C6
0.1µF
+
+
C7
400µF
IOUT (mA)
0
–0.50
OUTPUT VOLTAGE ERROR (V)
0
50 100 200150
0.50
–0.25
0.25
250
3751 TA06b
100
EFFICIENCY (%)
100
95
90
85
80
75
70 180140
3751 TA06c
200160
INPUT VOLTAGE (V)
120
63W OUTPUT
48W OUTPUT
25W OUTPUT
20µs/DIV 3751 TA06d
IPRIMARY
2A/DIV
VDRAIN
100V/DIV
20µs/DIV 3751 TA06e
IPRIMARY
2A/DIV
VDRAIN
100V/DIV
Load Regulation Efficiency
Steady-State Operation with
225mA Load Current
Steady-State Operation with
7.1mA Load Current
LT3751
30
3751fc
–IVOUT2, IVOUT3** (mA)
–VOUT2, VOUT3 (V)
18
16
14
20
3751 TA07b
VIN = 24V
VIN = 12V
VIN = 5V
1 10 100 1000
**SOURCE/SINK IDENTICAL CURRENTS FROM BOTH VOUT2 AND VOUT3, RESPECTIVELY
Wide Input Voltage Range, 15 Watt, Triple Output Voltage Regulator
Typical applicaTions
DONE
FAULT
UVLO1
OVLO1
UVLO2
OVLO2
VCC
CHARGE
CLAMP
RDCM
RVOUT
HVGATE
LVGATE
FB
CSP
CSN
RVTRANS
D1
T1
2:1:3:3
(P1:S1:S2:S3)
VOUT3
+15V
VIN
5V TO 24V
VCC
3751 TA07a
LT3751
GND RBG
R5
25.5k
OFF ON
C4
470µF
C7
10µF
C1
10µF
•
•
C3
10µF
R12
4.99k
R7
25.5k
R6
11.5k
M1
R11
25mΩ
R10
100Ω
R8
2.21k
R9
309Ω
R4, 464k
R3, 66.5k
P1
S3
R2, 100k
R1, 100k
C1, C3: 25V X5R OR X7R CERAMIC
C2: 25V SANYO 25ME1000AX
C4, C5: 35V SANYO 35ME470AX
C6: 10V KEMET T520D107M010ASE055
C7, C8: 16V CERAMIC, TDK C4532X7R1E106M
C9: 6.3V CERAMIC, TDK C4532X5R0J107M
D1, D2: CENTRAL SEMI CMSH2-60M
D3: CENTRAL SEM1 CMSH5-40
M1: FAIRCHILD FQD12N20L
R1 THRU R10, R12, R13: 0805 RESISTOR, 1%
R11: 1206 RESISTOR, 1%
T1: COILCRAFT HA3994-AL, 2:1:3:3 (P1:S1:S2:S3)
D2
VOUT2
–15V
C5
470µF
C8
10µF
•
R13
4.99k
S2
D3 VOUT1
+5V
C6
100µF
×2
C9
100µF
•
S1
+
+
+
C2
1000µF
×2
+
–IVOUT2, IVOUT3** (mA)
–VOUT2, VOUT3 (V)
22
24
20
18
16
14
26
3751 TA07c
VIN = 24V
VIN = 12V
VIN = 5V
1 10 100 1000
–IVOUT2 + IVOUT3 (mA)
0
EFFICIENCY (%)
80
85
75
70
400
200 600 800
65
60
90
3751 TA07d
VIN = 24V
VIN = 12V
VIN = 5V
Cross Regulation
(IVOUT1 = 100mA)
Efficiency
(IVOUT1 = 500mA)
Maximum Output Conditions
VCC
(V)
POUT(MAX)
(W)
IOUT(MAX)* (mA)
VOUT1 VOUT2 VOUT3
5 6.5 750 300 300
12 10 1750 300 300
24 13 2500 300 300
*All other output currents set to 0mA
Cross Regulation
(IVOUT1 = 500mA)
LT3751
31
3751fc
FE20 (CB) TSSOP REV I 0211
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
RECOMMENDED SOLDER PAD LAYOUT
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
1 3 4 5678 9 10
111214 13
6.40 – 6.60*
(.252 – .260)
3.86
(.152)
2.74
(.108)
20 1918 17 16 15
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC 0.195 – 0.30
(.0077 – .0118)
TYP
2
2.74
(.108)
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
3.86
(.152)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev I)
Exposed Pad Variation CB
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LT3751
32
3751fc
UFD Package
20-Pin Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1711 Rev B)
package DescripTion
4.00 ± 0.10
(2 SIDES)
1.50 REF
5.00 ± 0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
19 20
1
2
BOTTOM VIEW—EXPOSED PAD
2.50 REF
0.75 ± 0.05
R = 0.115
TYP
PIN 1 NOTCH
R = 0.20 OR
C = 0.35
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UFD20) QFN 0506 REV B
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
2.65 ± 0.05
2.50 REF
4.10 ± 0.05
5.50 ± 0.05
1.50 REF
3.10 ± 0.05
4.50 ± 0.05
PACKAGE OUTLINE
R = 0.05 TYP
2.65 ± 0.10
3.65 ± 0.10
3.65 ± 0.05
0.50 BSC
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LT3751
33
3751fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
B 5/10 Updated FAULT (Pin 6/Pin 4) description in Pin Functions 7
Updated DONE (Pin 7/Pin 5) description in Pin Functions 8
Updated Block Diagram 9
Revised Applications Information section 17, 18
Revised Typical Applications illustration 30
C 6/12 Revised Applications Information section 20
Corrected Schematic R8 value from 3.40k to 2.21k 30
Updated FE package drawing 31
(Revision history begins at Rev B)
LT3751
34
3751fc
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2008
LT 0612 REV C • PRINTED IN USA
relaTeD parTs
Typical applicaTion
300V Regulated Power Supply
PART NUMBER DESCRIPTION COMMENTS
LTC3225 150mA Supercapacitor Charger VIN: 2.75V to 5.5V, Charges Two Supercapacitors in Series to 4.8V or 5.3V
LT3420/LT3420-1 1.4A/1A, Photoflash Capacitor Charger
with Automatic Top-Off
Charges 220µF to 320V in 3.7 Seconds from 5V, VIN: 2.2V to 16V, ISD < 1µA,
10-Lead MS Package
LT3468/LT3468-1/
LT3468-2
1.4A, 1A, 0.7A, Photoflash Capacitor Charger VIN: 2.5V to 16V, Charge Time: 4.6 Seconds for LT3468 (0V to 320V, 100µF,
VIN = 3.6V), ISD < 1µA, ThinSOT™ Package
LT3484-0/LT3484-1/
LT3484-2
1.4A, 0.7A, 1A Photoflash Capacitor Charger VIN: 1.8V to 16V, Charge Time: 4.6 Seconds for LT3484-0 (0V to 320V, 100µF,
VIN = 3.6V), ISD < 1µA, 2mm × 3mm 6-Lead DFN Package
LT3485-0/LT3485-1/
LT3485-2/LT3485-3
1.4A, 0.7A, 1A, 2A Photoflash Capacitor
Charger with Output Voltage Monitor and
Integrated IGBT
VIN: 1.8V to 10V, Charge Time: 3.7 Seconds for LT3485-0 (0V to 320V, 100µF,
VIN = 3.6V), ISD < 1µA, 3mm × 3mm 10-Lead DFN Package
LT3585-0/LT3585-1/
LT3585-2/LT3585-3
1.2A, 0.55A, 0.85A, 1.7A Photoflash
Capacitor Charger with Adjustable Input
Current and IGBT Drivers
VIN: 1.5V to 16V, Charge Time: 3.3 Seconds for LT3585-3 (0V to 320V, 100µF,
VIN = 3.6V), ISD < 1µA, 3mm × 2mm DFN-10 Package
LT3750 Capacitor Charger Controller VIN: 3V to 24V, Charge Time: 300ms for (0V to 300V, 100µF) MSOP-10 Package
UVLO1
OVLO1
UVLO2
OVLO2
RDCM
RVTRANS
T1
1:10 D1 VOUT
300V
0mA TO 270mA
VTRANS
24V
VCC
C3
680µF
3751 TA08
LT3751
GND RBG
R6
40.2k
OFF ON
C2
2.2µF
×5
VCC
24V C1
10µF
•
•
R7
18.2k
M1
R5
6mΩ
+
+
C4
20µF
R8*
274k
* DEPENDING ON DESIRED OUTPUT
VOLTAGE, R8 MUST BE SPLIT
INTO MULTIPLE RESISTORS TO
MEET MANUFACTURER’S VOLTAGE
SPECIFICATION.
VTRANS
VCC
R9
1.13k
R1
432k
R2
475k
R4
475k
R3
432k
TO
MICRO
C1: 25V X5R OR X7R CERAMIC CAPACITOR
C2: 25V X5R OR X7R CERAMIC CAPACITOR
C3: 25V ELECTROLYTIC
C4: 330V RUBYCON PHOTOFLASH CAPACITOR
D1: VISHAY US1M 1000V
M1: FAIRCHILD FQP34N20L
R1 THROUGH R4: USE 1% 0805 RESISTORS
R5: IRC LR SERIES 2512 RESISTOR
T1: SUMIDA PS07-299, 20A TRANSFORMER
CSN
FB
DONE
FAULT
VCC
CLAMP
CHARGE
RVOUT
HVGATE
LVGATE
CSP
C5
10nF
