White Electronic Designs W7NCFxxx-H Series CompactFlash(R) Card FEATURES Storage Capacities: * 128MB, 256MB, 512MB, 1GB, 2GB, 4GB and 8GB Environment conditions: * 8GB B 2GB 4G Operating temperature: -40C to 85C * Co 5V operation DESCRIPTION Write operation: 28 mA (Typ.), 30 mA (Max.) The W7NCFxxx-H Series CompactFlash(R) card is an ATA interface flash memory card based on flash technology. This CompactFlash(R) card series is constructed with a 32 bit RISC based controller and SLC NAND flash memory devices. The card operates from a single 5-Volt or 3.3-Volt power source, and is available in CompactFlash(R) type-I form factor with 128MB, 256MB, 512MB, 1GB, 2GB, 4GB and 8GB capacity. Able to emulate IDE hard disk drives and certified in accordance with the CompactFlash (R) Certification Plan. Sleep mode: 2.0mA (max.) 3.3V operation Active mode: Write operation: 28 mA (Typ.), 30 mA (Max.) Read operation: 23 mA (Typ.), 30 mA (Max.) Sleep mode: 2.0mA (max. RoHS compliant Interface modes * PC card memory mode * PC card I/O mode * True IDE mode Less than 1 Error in 1014 bits read MTBF > 4,000,000 hours High shock & vibration tolerance W/E Endurance: 4,000,000 write/erase cycles High performance * Interface Transfer speed in PIO mode 4 or Multi Word DMA mode 2 cycle timing; up to 16.7 MB/second (PIO mode 3 & 4 are available in IDE mode only). * Typical write: 5.0 MBytes/s in ATA PIO mode 4 * Typical read: 7.0 MBytes/s in ATA PIO mode 4 * On card ECC up to 6 Bytes per 512 Byte data sector March 2007 Rev. 10 Dimensions: * Type I card : 36.4mm(L) x 42.8mm(W) x 3.3mm(H) Highly resistant to data corruption due to power loss or card removal Active mode: Read operation: 23 mA (Typ.), 30 mA (Max.) * h (R) Flas lash(R) CompactF Com sh pact t Fla mpac (R) * Storage temperature: -55C to 125C CompactFlash(R) Compatibility * CFA standard 2.1 compliant * 3.3V or 5.0V single power supply * 50 pin connector with Type-I form factor (3.3mm thickness) * 256 Bytes of attribute memory Power consumption CompactFlash(R) is a trademark of SanDisk Corporation and is licensed royalty-free to the CFA, which in turn will license it royalty-free to CFA members. CFA: CompactFlash(R) Association. 1 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W7NCFxxx-H Series ENVIRONMENTAL CHARACTERIZATION Item Temperature Cycle Humidity Vibration Shock Altitude Performance JEDEC - JESD STD A104 Temp condition N (-40C to 85 C) and soak mode 3; 200 cycles MIL-STD 810F, Method 507.4, Paragraph 4.5.2 - 10 day test per figure 507.4-1, 10 day test MIL-STD 810F, Method 514.5, procedure 1, category 24, 1 hour per axis MIL-STD 810F, Method 516.5, procedure1, non-operational, 40g, SRS functional shock for ground equipment, three (3) shock per axis (positive or negative). JEDEC- JESD22-B, 104-A, test condition B,1500 g pulse, 0.5 msec MIL-STD 810F, Method 500.4, procedure II, modified to 80,000 ft and non operation 1 hr test duration at altitude PRODUCT RELIABILITY Item MTBF (@ 25C) Data reliability Endurance Value > 4,000,000 Hours < 1 Non-Recoverable Error in 1014 Bits Read > 4,000,000 write/erase cycles Item Read Transfer Rate (Typical) Write Transfer Rate (Typical) Burst Transfer Rate Controller Overhead (Command to DRQ) Performance (PIO mode 4 true IDE) 7MB/s 5MB/s up to 16.7MB/s PRODUCT PERFORMANCE March 2007 Rev. 10 1ms typical, 5ms (max) 2 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W7NCFxxx-H Series DC ELECTRICAL CHARACTERISTICS Symbol VIL VIH VOL VOH ICC ICC ILI ILO Parameter Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage Min -0.3 2.0 Max +0.8 VCC+0.3 0.45 Units V V V V Operating Current, VCC_R=5.0V Sleep Mode Operating, 20 MHz 0.2 30 mA mA Operating Current, VCC_R=3.3V Sleep Mode Operating, 20 MHz Input Leakage Current Output Leakage Current 0.2 30 10 10 mA mA A A 2.4 Notes at 4mA at 4mA Attribute Memory Read and Write AC Characteristics VCC = 5V 0.5V, 3.3 V 0.3V Symbol tcR ta(A) ta(CE) ta(OE) tdis(CE) tdis(OE) ten(CE) ten(OE) tV(A) tsu(A) th(A) tsu(CE) th(CE) tcW Parameter Read Cycle Time Address Access Time Card Enable Access Time Output Enable Access Time Output Disable time from CE Output Disable time from OE Output Enable time from CE Output Enable time from OE Data valid time from address change Address Setup Time Address Hold Time Card Enable Setup Time Card Enable Hold Time Write Cycle Time Min 250 tw(WE) tsu(A-WEH) tsu(CE-WEH) tsu(D-WEH) th(D) tdis(WE) ten(WE) tsu(OE-WE) th(OE-WE) Write Pulse TIme Address setup time for WE Card Enable setup time for WE Data setup time for WE Data hold time Output disable time from WE Output enable time from WE Output Enable setup time for WE Output Enable hold time from WE 150 180 180 80 30 March 2007 Rev. 10 Max 250 250 125 100 100 5 5 0 30 20 2 20 250 5 10 10 3 100 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W7NCFxxx-H Series Common Memory Read and Write AC Charateristics Symbol tcR ta(A) ta(CE) ta(OE) tdis(CE) tdis(OE) ten(CE) ten(OE) tV(A) tsu(A) th(A) tsu(CE) th(CE) tcW Parameter Read Cycle Time Address Access Time Card Enable Access Time Output Enable Access Time Output Disable time from CE Output Disable time from OE Output Enable time from CE Output Enable time from OE Data valid time from address change Address Setup Time Address Hold Time Card Enable Setup Time Card Enable Hold Time Write Cycle Time Min 150 tw(WE) tsu(A-WEH) tsu(CE-WEH) tsu(D-WEH) th(D) trec(WE) tdis(WE) ten(WE) tsu(OE-WE) th(OE-WE) Write Pulse TIme Address setup time for WE Card Enable setup time for WE Data setup time for WE Data hold time 80 100 100 50 20 20 March 2007 Rev. 10 Max 150 150 75 75 75 5 5 0 20 20 0 20 150 Output disable time from WE Output enable time from WE Output Enable setup time for WE Output Enable hold time from WE 5 10 10 4 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 75 ns ns ns ns White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W7NCFxxx-H Series I/O Access Read and Write AC Characteristic Symbol td(IORD) th(IORD) tw(IORD) tsuA(IORD) thA(IORD) tsuCE(IORD) thCE(IORD) tsuREG(IORD) thREG(IORD) tdflNP(IORD) tdrlNP(IORD) tdflO16(IORD) tdrlO16(IORD) tsu(IOWR) th(IOWR) tw(IOWR) tsuA(IOWR) thA(IOWR) Parameter Data Delay after IORD Data Hold following IORD IORD pulse width Address setup time for IORD Address hold time for IORD Card Enable setup time for IORD Card Enable hold time from IORD REG setup time for IORD REG Hold time from IORD INPACK delay falling from IORD INPACK delay rising from IORD IOIS16 delay falling from address IOIS16 delay rising from address Data setup time for IOWR Data hold time from IOWR IOWR pulse width Address setup time for IOWR Min 60 30 165 70 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0 165 70 20 5 20 5 0 0 Max 100 45 45 35 35 Address hold time from IOWR 20 ns tsuCE(IOWR) Card Enable setup time fro IOWR 5 ns thCE(IOWR) Card Enable hold time from IOWR 20 ns tsuREG(IOWR) REG setup time for IOWR 5 ns thREG(IOWR) REG hold tme from IOWR 0 ns True-IDE Mode I/O Access Read and Write AC Characteristics Symbol tcR tsuA thA tw trec tsuD(IORD) thD(IORD) tdis(IORD) Parameter Cycle time Address setup time for IORD/IOWR Address hold time from IORD/IOWR IORD/IORW pulse width IORD/IORW recovery time Data setup time for IORD Data hold time for IORD Output disable time from IORD tsuD(IOWR) Data setup time for IOWR 20 ns thD(IOWR) Data hold following IOWR 10 ns March 2007 Rev. 10 Min 120 25 10 70 25 20 5 Max 30 5 Units ns ns ns ns ns ns ns ns White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W7NCFxxx-H Series Pin Assignments & Pin Type PC Card Memory Mode Pin Number Signal Name 1 GND 2 D03 3 D04 4 D05 5 D06 6 D07 7 -CE1 8 A10 9 -OE 10 A09 11 A08 12 A07 13 VCC 14 A06 15 A05 16 A04 17 A03 18 A02 19 A01 20 A00 21 D00 22 D01 23 D02 24 WP 25 -CD2 26 -CD1 27 D111 28 D121 29 D131 30 D141 31 D151 32 -CE21 33 -VS1 34 -IORD 35 -IOWR 36 -WE 37 RDY 38 VCC 39 -CSEL4 40 -VS2 41 RESET 42 -WAIT 43 -INPACK 44 -REG 45 BVD2 46 BVD1 47 DO81 48 DO91 49 D101 50 GND Note: Pin Type I/O I/O I/O I/O I/O I I I I I I I I I I I I I I/O I/O I/O O O O I/O I/O I/O I/O I/O I O I I I O I O I O O I O O I/O I/O I/O PC Card I/O Mode In, Out Type Ground I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I3U IZ1 IU3 I1Z I1Z I1Z Power I1Z I1Z I1Z I1Z I1Z I1Z I1Z I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 OT3 Ground Ground I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I3U Ground I3U I3U I3U OT1 Power I2Z OPEN I2Z OT1 OT1 I3U OT1 OT1 I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 Ground Pin Number Signal Name 1 GND 2 D03 3 D04 4 D05 5 D06 6 D07 7 -CE1 8 A10 9 -OE 10 A09 11 A08 12 A07 13 VCC 14 A06 15 A05 16 A04 17 A03 18 A02 19 A01 20 A00 21 D00 22 D01 23 D02 24 -IOIS16 25 -CD2 26 -CD1 27 D111 28 D121 29 D131 30 D141 31 D151 32 -CE21 33 -VS1 34 -IORD 35 -IOWR 36 -WE 37 IREQ 38 VCC 39 -CSEL4 40 -VS2 41 RESET 42 -WAIT 43 -INPACK 44 -REG 45 -SPKR 46 -STSCHG 47 DO81 48 DO91 49 D101 50 GND These signals are required only for 16-bit access and are not required when installed in 8-bit systems. Devices should allow for 3-state signals not to consume current. 2 : Should be grounded by the host system. 3 : Should be tied to VCC by the host system. 1 March 2007 Rev. 10 6 True IDE Mode Pin Type I/O I/O I/O I/O I/O I I I I I I I I I I I I I I/O I/O I/O O O O I/O I/O I/O I/O I/O I O I I I O I O I O O I I/O I/O I/O I/O I/O In, Out Type Pin Number Signal Name Pin Type In, Out Type Ground 1 GND Ground I1Z, OZ3 2 D03 I/O I1Z, OZ3 I1Z, OZ3 3 D04 I/O I1Z, OZ3 I1Z, OZ3 4 D05 I/O I1Z, OZ3 I1Z, OZ3 5 D06 I/O I1Z, OZ3 I1Z, OZ3 6 D07 I/O I1Z, OZ3 I3U 7 -CS0 I I3U IZ1 8 A102 I IZ1 IU3 9 -ATA SEL I IU3 2 I1Z I I1Z 10 A09 I1Z 11 A082 I I1Z I1Z 12 A072 I I1Z 13 VCC Power Power I1Z 14 A062 I I1Z I1Z I I1Z 15 A052 I1Z 16 A042 I I1Z I1Z 17 A032 I I1Z I1Z 18 A02 I I1Z I1Z 19 A01 I I1Z I1Z 20 A00 I I1Z I1Z, OZ3 21 D00 I/O I1Z, OZ3 I1Z, OZ3 22 D01 I/O I1Z, OZ3 I1Z, OZ3 23 D02 I/O I1Z, OZ3 OT3 24 -IOIS16 O ON3 Ground 25 -CD2 O Ground Ground 26 -CD1 O Ground 27 D111 I1Z, OZ3 I/O I1Z, OZ3 28 D121 I1Z, OZ3 I/O I1Z, OZ3 29 D131 I1Z, OZ3 I/O I1Z, OZ3 30 D141 I1Z, OZ3 I/O I1Z, OZ3 I1Z, OZ3 I/O I1Z, OZ3 31 D151 32 -CS11 I3U I I3Z Ground 33 -VS1 O Ground I3U 34 -IORD I I3Z I3U 35 -IOWR I I3Z I3U 36 -WE3 I I3U OT1 37 IREQ O OZ1 38 VCC Power Power 39 -CSEL I I2U I2Z 40 -VS2 O OPEN OPEN 41 RESET I I2Z I2Z 42 -IORDY O ON1 OT1 43 DMARQ O OZ1 OT1 44 -DMACK5 I3U I I3U OT1 45 -DASP I/O I1U, ON1 OT1 46 PDIAG I/O I1U, ON1 47 DO81 I1Z, OZ3 I/O I1Z, OZ3 48 DO91 I1Z, OZ3 I/O I1Z, OZ3 49 D101 I1Z, OZ3 I/O I1Z, OZ3 Ground 50 GND Ground 4 : The -CSEL signal is ignored by the card in PC Card moudes. However, because it is not pulled up on the card in thses modes, it should not be left floating by the host in PC card modes. In these modes, the pin should be connected by th host to PC card A25 or grounded by the host. 5 : If DMA operations are not used, the signal should be held high or tied to VCC by the host. For proper operation in older hosts: while DMA operations are not active, the card shall ignore the signal, including a floating condition. White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W7NCFxxx-H Series Signal Description Signal Name Dir. A10-A0 (PC Card Memory Mode) I A10-A0 (PC Card I/O Mode) A2 - A0 (True IDE Mode) BVD1 (PC Card Memory Mode) -STSCHG (PC Card I/O Mde) Status Changed -PDIAG (True IDE Mode) BVD2 (PC Card Memory Mode) -SPKR (PC Card I/O Mode) -DASP (True IDE Mode) Pin Description 8, 10, 11, 12, 14, 15, 16, 17, 18, 19, 20 These address lines along with the -REG signal are used to select the following: The I/O port address registers within the CompactFlash(R) Storage Card or CF+ Card, the memory mapped port address registers within the CompactFlash(R) Storage Card or CF+ Card, a byte in the card's information structure and its configuration control and status registers. This signal is the same as the PC Card Memory Mode signal. 18, 19, 20 This signal is asserted high, as BVD1 is not supported. I/O 46 I/O 45 O 26, 25 -CSEL (True IDE Mode) March 2007 Rev. 10 This signal is the same for all modes. These input signals are used both to select the card and to indicate to the card whether a byte or a word operation is being performed. -CE2 always accesses the odd byte of the word. -CE1 accesses the even byte or the Odd byte of the word depending on A0 and -CE2. A multiplexing scheme based on A0, -CE1, -CE2 allows 8 bit hosts to access all data on D0-D7. I 7, 32 -CS0, CS1 (True IDE Mode) -CSEL (PC Card Memory Mode) -CSEL (PC Card I/O Mode) This line is the Binary Audio out put from the card. If the Card does not support the Binary Audio function, this line should be held negated. In the True IDE Mode, this input/output is the Disk Active/Slave Present signal in the Master/ Slave handshake protocol. These Card Detect pins are connected to ground on the CompactFlash(R) Storage Card or CF+ Card. They are used by the host to determine that the CompactFlash(R) Storage Card or CF+ Card is fully inserted into its socket. This signal is the same for all modes. -CE1, -CE2 (PC Card Memory Mode) Card Enable -CE1, -CE2 (PC Card I/O Mode) Card Enable This signal is asserted low to alert the host to changes in the READY and Write Protect states , while the I/O interface is configured. Its use is controlled by the Card Config and Status Register. In the True IDE Mode, this input / output is the Pass Diagnostic signal in the Master / Slave handshake protocol. This signal is asserted high, as BVD2 is not supported. -CD1, -CD2 (PC Card Memory Mode) -CD1, CD2 (PC Card I/O Mode) -CD1, CD2 (True IDE Mode) In True IDE Mode, only A[2:0] are used to select the one of eight registers in the Task File, the remaining address lines should be grounded by the host. I 39 This signal is the same as the PC Card Memory Mode signal. In the True IDE Mode, -CS0 is the chip select for the task file registers while -CS1 is used to select the Alternate Status Register and the Device Control Register. While -DMACK is asserted, -CS0 and -CS1 shall be held negated and the width of the transfers shall be 16 bits. This signal is not used for this mode, but should be connected by the host to PC Card A25 or grounded by the host. This signal is not used for this mode, but should be connected by the host to PC Card A25 or grounded by the host. This internally pulled up signal is used to configure this device as a Master or a Slave when configured in the True IDE Mode. When this pin is grounded, this device is configured as a Master. When the pin is open, this device is configured as a Slave. 7 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W7NCFxxx-H Series Signal Description (con'd) Signal Name Dir. Pin I/O 31, 30, 29, 28, 27, 49, 48, 47, 6, 5, 4, 3, 2, 23, 22, 21 D15 - D00 (PC Card Memory Mode) D15 - D00 (PC Card I/O Mode) D15 - D00 (True IDE Mode) GND (PC Card Memory Mode) GND (PC Card I/O Mode) GND (True IDE Mode) -INPACK (PC Card Memory Mode) Description These lines carry the Data, Commands and Status information between the host and the controller . D00 is the LSB of the Even Byte of the Word. D08 is the LSB of the Odd Byte of the Word. This signal is the same as the PC Card Memory Mode signal. In True IDE Mode, all Task File operations occur in byte mode on the low order bus D[7:0] while all data transfers are 16 bit using D[15:0]. Ground - 1, 50 This signal is the same for all modes. This signal is the same for all modes. This signal is the same for all modes. -INPACK (PC Card I/O Mode) Input Acknowledge O 43 The Input Acknowledge signal is asserted by the CompactFlash(R) Storage Card or CF+ Card when the card is selected and responding to an I/O read cycle at the address that is on the address bus. This signal is used by the host to control the enable of any input data buffers between the CompactFlash(R) Storage Card or CF+ Card and the CPU. This signal is a DMA Request that is used for DMA data transfers between host and device. It shall be asserted by the device when it is ready to transfer data to or from the host. For Multiword DMA transfers, the direction of data transfer is controlled by DIOR- and DIOW-. This signal is used in a handshake manner with DMACK-, i.e., the device shall wait until the host asserts DMACK- before negating DMARQ, and re asserting DMARQ if there is more data to transfer. While a DMA operation is in progress, -CS0 and -CS1 shall be held negated and the width of the transfers shall be 16 bits. DMARQ (True IDE Mode) If there is no hardware support for DMA mode in the host, this output signal is not used and should not be connected at the host. In this case, the BIOS must report that DMA mode is not supported by the host so that device drivers will not attempt DMA mode. A host that does not support DMA mode and implements both PCMCIA and True-IDE modes of operation need not alter the PCMCIA mode connections while in True-IDE mode as long as this does not prevent proper operation in any mode. -IORD (PC Card Memory Mode) -IORD (PC Card I/O Mode) -IORD (Tru IDE Mode) March 2007 Rev. 10 This signal is not used in this mode. I 34 This is an I/O Read strobe generated by the host. This signal gates I/O data onto the bus from the CompactFlash(R) Storage Card or CF+ Card when the card is configured to use the I/O interface. In True IDE Mode, this signal has the same function as in PC Card I/O Mode. 8 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W7NCFxxx-H Series Signal Description (con'd) Signal Name -IOWR (PC Card Memory Mode) -IOWR (PC Card I/O Mode) Dir. Pin Description This signal is not used in this mode. I 35 The I/O Write strobe pulse is used to clock I/O data on the Card Data bus into the CompactFlash(R) Storage Card or CF+ Card controller registers when the CompactFlash(R) Storage Card or CF+ Card is configured to use the I/O interface. The clocking shall occur on the negative to positive edge of the signal (trailing edge). -IOWR (True IDE Mode) In True IDE Mode, this signal has the same function as in PC Card I/O Mode. -OE (PC Card Memory Mode) This is an Output Enable strobe generated by the host interface. It is used to read data from the CompactFlash(R) Storage Card or CF+ Card in Memory Mode and to read the CIS and configuration registers. -OE (PC Card I/O Mode) -ATA SEL (True IDE Mode) I 9 In PC Card I/O Mode, this signal is used to read the CIS and configuration registers. To enable True IDE Mode this input should be grounded by the host. In Memory Mode, this signal is set high when the CompactFlash(R) Storage Card or CF+ Card is ready to accept a new data transfer operation and is held low when the card is busy. At power up and at Reset, the READY signal is held low (busy) until the CompactFlash(R) Storage Card or CF+ Card has completed its power up or reset function. No access of any type should be made to the CompactFlash(R) Storage Card or CF+ Card during this time. READY (PC Card Memory Mode) O 37 Dir. Pin -IREQ (PC Card I/O Mode) INTRQ Note, however, that when a card is powered up and used with RESET continuously disconnected or asserted, the Reset function of the RESET pin is disabled. Consequently, the continuous assertion of RESET from the application of power shall not cause the READY signal to remain continuously in the busy state. I/O Operation - After the CompactFlash(R) Storage Card or CF+ Card has been configured for I/O operation, this signal is used as -Interrupt Request. This line is strobed low to generate a pulse mode interrupt or held low for a level mode interrupt. In True IDE Mode signal is the active high Interrupt Request to the host. Signal Name -REG (PC Card Memory Mode) Attribute Memory Select -REG (PC Card I/O Mode) Description This signal is used during Memory Cycles to distinguish between Common Memory and Register (Attribute) Memory accesses. High for Common Memory, Low for Attribute Memory. The signal shall also be active (low) during I/O Cycles when the I/O address is on the Bus. This is a DMA Acknowledge signal that is asserted by the host in response to DMARQ to initiate DMA transfers. I -DMACK (True IDE Mode) 44 While DMA operations are not active, the card shall ignore the -DMACK signal, including a floating condition. If DMA operation is not supported by a True IDE Mode only host, this signal should be driven high or connected to VCC by the host. A host that does not support DMA mode and implements both PCMCIA and True-IDE modes of operation need not alter the PCMCIA mode connections while in True-IDE mode as long as this does not prevent proper operation all modes. March 2007 Rev. 10 9 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W7NCFxxx-H Series Signal Description (con'd) Signal Name Dir. Pin The host may leave the RESET pin open or keep it continually high from the application of power without causing a continuous Reset of the card. Under either of these conditions, the card shall emerge from power-up having completed an initial Reset. RESET (PC Card Memory Mode) I RESET (Card I/O Mode) -RESET (True IDE Mode) VCC (PC Card Memory Mode) VCC (Pc Card I/O Mode) VCC (True IDE Mode) -VS1 -VS2 (PC Card Memory Mode) -VS1 -VS2 (PC Card I/O Mode) -VS1 -VS2 (True IDE Mode) -WAIT (PC Card Memory Mode) -WAIT (PC Card I/O Mode) IORDY (True IDE Mode) 41 In the True IDE Mode, this input pin is the active low hardware reset from the host. +5 V, +3.3 V power. - 13, 38 -IOCS16 (True IDE Mode) March 2007 Rev. 10 This signal is the same for all modes. This signal is the same for all modes. Voltage Sense Signals. -VS1 is grounded on the Card and sensed by the Host so that the CompactFlash(R) Storage Card or CF+ Card CIS can be read at 3.3 volts and -VS2 is reserved by PCMCIA for a secondary voltage and is not connected on the Card. O 33, 40 This signal is the same for all modes. This signal is the same for all modes. The -WAIT signal is driven low by the CompactFlash(R) Storage Card or CF+ Card to signal the host to delay completion of a memory or I/O cycle that is in progress. O 42 This signal is the same as the PC Card Memory Mode signal. In True IDE Mode, this output signal may be used as IORDY. This is a signal driven by the host and used for strobing memory write data to the registers of the CompactFlash(R) Storage Card or CF+ Card when the card is configured in the memory interface mode. It is also used for writing the configuration registers. I 36 In PC Card I/O Mode, this signal is used for writing the configuration registers. In True IDE Mode, this input signal is not used and should be connected to VCC by the host. WP (PC Card Memory Mode) -IOIS16 (PC Card I/O Model) The CompactFlash(R) Storage Card or CF+ Card is also Reset when the Soft Reset bit in the Card Configuration Option Register is set. This signal is the same as the PC Card Memory Mode signal. -WE (PC Card Memory Moce) -WE (PC Card I/O Mode) -WE (True IDE Mode) Description The CompactFlash(R) Storage Card or CF+ Card is Reset when the RESET pin is high with the following important exception: O 24 Memory Mode - The CompactFlash(R) Storage Card or CF+ Card does not have a write protect switch. This signal is held low after the completion of the reset initialization sequence. I/O Operation - When the CompactFlash(R) Storage Card or CF+ Card is configured for I/O Operation Pin 24 is used for the -I/O Selected is 16 Bit Port (-IOIS16) function. A Low signal indicates that a 16 bit or odd byte only operation can be performed at the addressed port. In True IDE Mode this output signal is asserted low when this device is expecting a word data transfer cycle. 10 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W7NCFxxx-H Series PACKAGE DIMENSIONS 1.60mm .05 (.063 in .002) 1 1.01mm .07 (0.040 in. .003) 3.30mm .10 (.130 in .004) .99mm .05 (.039 in .002) 50 26 25 1.01mm .07 (0.040 in. .003) 2.44mm .07 (.096 in. .003 2 x 25.78mm .07(2 x 1.015 . 003) Optional Configuration (See note.) 1.65mm (.130 in.) 2.15mm .07 (.085 in x .003) 2 x 3.00mm .07 (2 x .118 in .003) 36.40mm .15(1.433 in . 006) 2 x 12.00mm .10 (2 x 472 in .004) .01mm .07(.039 in .003) 0.76mm .07(0.30 in .003) 41.66mm .13(1.640 in . 005) 4xR 0.5mm .1 (4xR.020 in .004) 42.80mm .10(1.685 in .004) 0.63mm .07(.025 in .003) Note: The optional notched configuration was shown in the CF Specification Rev. 1.0 in specification Rev. 1.2, the notch was removed for ease of tooling. This optional configuration can be used but it is not recommended. ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) March 2007 Rev. 10 11 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W7NCFxxx-H Series Part Numbering Guide W 7N CF xxx H x 0 x x x x x WEDC: Flash Card, SLC - NAND: CompactFlash(R): Memory Capacity: 128 = 128M Byte 256 = 256M Byte 512 = 512M Byte 01G = 1G Byte 02G = 2G Byte 04G = 4G Byte 08G = 8G Byte Controller manufacturer: H = H-Series Controller/Firmware Revision Number: 1, 2, 3... Labels or Custom Labeling: 0 = labels front and back 1 = label on back only Temperature: C = Commercial (0C - 70C) I = Industrial (-40C - +85C) Memory Mfg.: S = Samsung Memory Device Information: 2 = 512Mbit single die package 3 = 1Gb single die package 4 = 2Gb single die package 5 = 4Gb dual die package 6 = 4Gb single die package 7 = 8Gb dual die package 8 = 8Gb single die package 9 = 16Gb quad die package A = 16Gb dual die package B = 16Gb single die package Options: B = Standard CF card configuration A = Standard CF with conformal coating C = Standard card with DMA disabled D = Standard card with DMA disabled and conformal coating E = Fixed disk option (for compatibility with some embedded software) F = Fixed disk with conformal coating H = Fixed with DMA disable J = Fixed disk with DMA disable and conformal coating G = for RoHS: * For help selecting the proper and most current part number for your application please contact your local sales representative. March 2007 Rev. 10 12 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W7NCFxxx-H Series Document Title 128MB to 8GB Industrial CompactFlash(R) Revision History Rev # History Release Date Status Rev 0 Initial Release November 2005 Preliminary Rev 1 1.0 Preliminary Release February 2006 Preliminary Rev 2 2.0 Part numbering corrections March 2006 Preliminary Rev 3 3.0 Update to AC/DC specs and pin descriptors August 2006 Preliminary Rev 4 4.0 Added 8GB density October 2006 Preliminary Rev 5 5.0 Corrected data reliability to less than " < ". November 2006 Preliminary Rev 6 6.0 Updated to remove specific part numbering and update the part numbering guide to include new options. February 2007 Final 6.1 Moved from preliminary to final Rev 7 7.0 Added data corruption bullet February 2007 Final Rev 8 8.0 Updated CompactFlash(R) Trademark February 2007 Final Rev 9 9.0 Final update March 2007 Final Rev 10 10.0 Added 1GB density to storage capacites March 2007 Final March 2007 Rev. 10 13 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com