1. General description
The LPC546xx is a family of ARM Cortex-M4 based microcontrollers for embedded
applications featuring a rich peripheral set with very low power consumption and
enhanced debug features.
The ARM Cortex-M4 is a 32- bit core that of fer s system e nhancements such as low powe r
consumption, enhanced deb ug features, and a high level of support block integration. The
ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with
separate local instruction and data buses as well as a third bus for peripherals, and
includes an internal prefetch unit that supports speculative branching. The ARM
Cortex-M4 supp or ts single-cy cle dig ital signal processing and SIMD instructions. A
hardware floating-point processor is integrated into the core.
The LPC546xx family includes up to 512 KB of flash, 200 KB of on-chip SRAM, up to
16 kB of EEPROM memory, a quad SPI Flash Interface (SPIFI) for expanding program
memory, one high-speed and one full-speed USB host and device controller, Ethernet
AVB, LCD controller, Smart Card Interfaces, SD/MMC, CAN FD, an External Memory
Controller (EMC ), a DMIC su bs yste m with PDM micr op ho n e inte r fac e an d I2S, five
general-purpose timers, SCTimer/PWM, RTC/alarm timer, Multi-Rate Timer (MRT), a
Windowed Watchdog Timer (WWDT), ten flexible serial communication peripherals
(USART, SPI, I2S, I2C interface), 12-bit 5.0 Msamples/sec ADC, temperature sensor.
2. Features and benefits
ARM Cortex-M4 core (version r0p1):
ARM Cortex-M4 processor, running at a frequency of up to 180 MHz.
Floating Point Unit (FPU) and Memory Protection Unit (MPU).
ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).
Non-maskable Interrupt (NMI) input with a selection of sources.
Serial Wire Debug (SWD) with six instruction breakpoints, two literal comparators,
and four watch points. Includes Serial Wire Output and ET M Trace for enhanced
debug capabilities, and a debug timestamp counter.
System tick timer.
On-chip memory:
Up to 512 KB on-chip flash program memory with flash accelerator and 256 byte
page erase and write.
LPC546xx
32-bit ARM Cortex-M4 microcontroller; up to 512 KB flash and
200 kB SRAM; High-speed USB device/host + PHY; Full-speed
USB device/host; Ethernet AVB; LCD; EMC; SPIFI; CAN FD,
SDIO; 12-bit 5 Msamples/s ADC; DMIC subsystem
Rev. 1.6 — 21 April 2017 Product data sheet
LPC546xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 1.6 — 21 April 2017 2 of 160
NXP Semiconductors LPC546xx
32-bit ARM Cortex-M4 microcontroller
Up to 200 KB total SRAM consisting of 160 KB contiguous main SRAM and an
additional 32 KB SRAM on the I&D buses. 8 KB of SRAM bank inten ded for USB
traffic.
16 KB of EEPROM.
ROM API support:
Flash In-Application Programming (IAP) and In-System Programming (ISP).
ROM-based USB drivers (HID, CDC, MSC, and DFU). Flash updates via USB.
Booting from valid user code in flash, USART, SPI, and I2C.
Legacy, Single, and Dual image boot.
OTP API for programming OTP memory.
Random Numbe r Gene ra to r (RN G) API.
Serial interfaces:
Flexcomm Interface contains ten serial peripherals. Each Flexcomm Interface can
be selected by software to be a USART, SPI, or I2C interface. Two Flexcomm
Interfaces also include an I2S interface. Each Flexcomm Interface includes a FIFO
that supports USART, SPI, and I2S if supported by that Flexcomm Interface. A
variety of clocking options are available to each Fl excomm Interface and include a
shared fractional baud-rate generator.
I2C-bus interfaces support Fast-mode and Fast-mode Plus with data rates of up to
1Mbit/s and with multiple address recognition and monitor mode. Two sets of true
I2C pads also support High Speed Mode (3.4 Mbit/s) as a slave.
Two ISO 7816 Smart Card Interfaces with DMA support.
USB 2.0 high-speed host /d ev ice co nt ro ller with on -c hip high -speed PHY.
USB 2.0 full-speed host /d ev ice contro lle r with on-chip PHY and dedicated DMA
controller supporting crystal-less operation in device mode.
SPIFI with XIP feature uses up to four dat a lines to access off-chip SPI/DSPI/QSPI
flash memory at a much higher rate than standard SPI or SSP interfaces.
Ethernet MAC with MII/RMII interface with Audio Video Brid ging (AVB) support and
dedicated DMA controller.
Two CAN FD modules with dedicated DMA controller.
Digital peripherals:
DMA controller with 30 channels and up to 24 programmable triggers, able to
access all memories and DMA-capable peripherals.
LCD Controller su pp ortin g bo th Sup er- Twisted Nematic (STN) and Thin-Film
Transistor (TFT) displays. It has a dedicated DMA controller, selectable display
resolution (up to 1024 x 768 pixels), and supports up to 24-bit true-color mode.
External Memory Controller (EMC) provides support for asynchronous static
memory devices such as RAM, ROM and flash, in addition to dynamic memories
such as single data rate SDRAM with an SDRAM clock of up to 100 MHz.
Secured digital inp ut/output (SD/MMC and SDIO) card interface with DMA support.
CRC engine block can calculate a CRC on supplied data using one of three
standard polynomials with DMA support.
Up to 171 General-Purpose Input/Output (GPIO) pins.
GPIO registers are located on the AHB for fast access. The DMA supports GPIO
ports.
Up to eight GPIOs can be selected as Pin Interrupts (PINT), triggered by rising,
falling or both input edges.
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Product data sheet Rev. 1.6 — 21 April 2017 3 of 160
NXP Semiconductors LPC546xx
32-bit ARM Cortex-M4 microcontroller
Two GPIO Grouped Interrupt s (GINT) enable an interrupt based on a logical
(AND/OR) combination of input states.
CRC engine.
Analog peripherals:
12-bit ADC with 12 input channels and with multiple internal and exte rn al trig g er
inputs and sample rates of up to 5.0 MSamples/sec. The ADC supports two
independent conversion sequences.
Integrated temperature sensor connected to the ADC.
DMIC subsystem including a dual-channel PDM microphone interface, flexible
decimators, 16 entry FIFOs, optional DC locking, hardware voice activity detection,
and the option to stream the processed output data to I2S.
Timers:
Five 32-bit general purpose timers/counters, four of which support up to four
capture inputs and four compare outputs, PWM mode, and external count input.
Specific timer events can be selected to generate DMA requests. The fifth timer
does not have external pin connections and may be used for internal timing
operations.
One SCT imer/PWM with eight input and ten output functions (including capture and
match). Inputs and outputs can be routed to or from external pins and internally to
or from selected periph erals. Internally, the SCTimer/PWM supports 16
match/captures, 16 events, and 16 states.
32-bit Real-time clo ck (RTC) with 1 s resolution running in the always-on power
domain. A timer in the RTC can be used for wake-up from all low power modes
including deep po wer -d o w n, with 1 ms reso lu tion .
Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation at
up to four programmable, fixed rates.
Windowed Watchdog Timer (WWDT).
Repetitive Interrupt Timer (RIT) for debug time stamping and for general purpose
use.
Security features:
Random number generator can be used to create keys with DMA support.
enhanced Code Read Protection (eCRP) to protect user code.
OTP memory for EC RP set ting s an d us er applica tio n sp ecific data.
Clock generation :
12 MHz internal Free Running Oscillator (FRO). This oscillator provides a
selecta ble 48 MHz or 96 MHz output, and a 12 MHz output (divid ed down from the
selected higher frequency) that can be used as a system clock. The FRO is
trimmed to 1 % accuracy over the entire voltage and temperature range.
External clock input for clock frequencies of up to 25 MHz.
Crystal oscillator with an operating range of 1 MHz to 25 MHz.
Watchdog Oscillator (WDTOSC) with a frequency range of 6 kHz to 1.5 MHz.
32.768 kHz low-power RTC oscillator.
System PLL allows CPU operation up to the maximum CPU rate and can run from
the main oscillator, the internal FRO, the watchdog oscillator or the 32.768 KHz
RTC oscillator.
Two additional PLLs for USB clock and audio subsystem.
Independent clocks for the SPIFI interface, ADC, USBs, and the audio subsystem.
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Product data sheet Rev. 1.6 — 21 April 2017 4 of 160
NXP Semiconductors LPC546xx
32-bit ARM Cortex-M4 microcontroller
Clock output function with divider.
Frequency measurement unit for measuring the frequency of any on-chip or
off-chip clock signal.
Power control:
Programmable PMU (Power Management Unit) to minimize power consumption
and to match requirements at different performance levels.
Reduced power modes: sleep , deep-sleep, and deep power-down.
Wa ke- u p fro m deep- sle ep mo de s du e to activity on the USART, SPI, and I2C
peripherals when operating as slaves.
Ultra-low power Micro-tick Timer, running from the Watchdog oscillator that can be
used to wake up the device from low power modes.
Power-On Reset (POR).
Brown-Out Detect (BOD) with separate thresholds for interr upt and forced reset.
Single power supply 1.71 V to 3.6 V.
Power-On Reset (POR).
Brown-Out Detect (BOD) with separate thresholds for interr upt and forced reset.
JTAG boundary scan supported.
128 bit unique device serial number for identification.
Operating temperature range 40 °C to +105 °C.
Available in TFBGA180 and LQFP208 packages.
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Product data sheet Rev. 1.6 — 21 April 2017 5 of 160
NXP Semiconductors LPC546xx
32-bit ARM Cortex-M4 microcontroller
3. Ordering information
3.1 Ordering options
Table 1. Ordering information
Type number Package
Name Description Version
LPC54605J256ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3
LPC54605J512ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3
LPC54606J256ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3
LPC54606J512BD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1
LPC54607J256ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3
LPC54607J512ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3
LPC54607J256BD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1
LPC54608J512ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3
LPC54608J512BD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1
LPC54616J256ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3
LPC54616J512BD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1
LPC54618J512ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3
LPC54618J512BD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1
Table 2. Ordering options
Type number
Package Name
Flash/kB
SRAM/kB
FS USB
HS USB
Ethernet AVB
Classic CAN
CAN FD0/FD1
LCD
GPIO
LPC54618 devices (HS/FS USB, Ethernet, CAN FD, LCD)
LPC54618J512ET180 TFBGA180 512 200 yes yes yes yes yes yes 145
LPC54618J512BD208 LQFP208 512 200 yes yes yes yes yes yes 171
LPC54616 devices (HS/FS USB, Ethernet, CAN FD)
LPC54616J256ET180 TFBGA180 256 136 yes yes yes no yes no 145
LPC54616J512BD208 LQFP208 512 200 yes yes yes no yes no 171
LPC54608 devices (HS/FS USB, Ethernet, CAN 2.0, LCD)
LPC54608J512ET180 TFBGA180 512 200 yes yes yes yes no yes 145
LPC54608J512BD208 LQFP208 512 200 yes yes yes yes no yes 171
LPC54607 devices (HS/FS USB, LCD)
LPC54607J256ET180 TFBGA180 256 136 yes yes no no no yes 145
LPC54607J512ET180 TFBGA180 512 200 yes yes no no no yes 145
LPC54607J256BD208 LQFP208 256 136 yes yes no no no yes 171
LPC54606 devices (HS/FS USB, Ethernet, CAN 2.0)
LPC54606J256ET180 TFBGA180 256 136 yes yes yes yes no no 145
LPC54606J512BD208 LQFP208 512 200 yes yes yes yes no no 171
LPC546xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 1.6 — 21 April 2017 6 of 160
NXP Semiconductors LPC546xx
32-bit ARM Cortex-M4 microcontroller
LPC54605 devices (HS/FS USB)
LPC54605J256ET180 TFBGA180 256 136 yes yes no no no no 145
LPC54605J512ET180 TFBGA180 512 200 yes yes no no no no 145
Table 2. Ordering options …continued
Type number
Package Name
Flash/kB
SRAM/kB
FS USB
HS USB
Ethernet AVB
Classic CAN
CAN FD0/FD1
LCD
GPIO
LPC546xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 1.6 — 21 April 2017 7 of 160
NXP Semiconductors LPC546xx
32-bit ARM Cortex-M4 microcontroller
4. Marking
The LPC546xx TFBGA180 package has the following top-side marking:
•First line: LPC546xxJyyy
–yyy: flash size
•Second line: ET180
•Third line: xxxxxxxxxxxx
•Fourth line: xxxyywwx[R]x
–yyww: Date code with yy = year and ww = week.
–xR = boot code version and device re vision.
The LPC546xx LQFP208 package has the following top-side marking:
•First line: LPC546xxJyyy
–yyy: flash size
•Second line: BD208
•Third line: xxxxxxxxxxxx
•Fourth line: xxxyywwx[R]x
–yyww: Date code with yy = year and ww = week.
–xR = Boot code version and device revision.
Fig 1. TFBGA180 package marking Fig 2. LQFP208 package marking
Terminal 1 index area
aaa-025721
1
n
Terminal 1 index area
aaa-011231
Table 3. Device revision table
Revision identifier (R) Revision description
1A Initial device revision with Boo t ROM version 19.1
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Product data sheet Rev. 1.6 — 21 April 2017 8 of 160
NXP Semiconductors LPC546xx
32-bit ARM Cortex-M4 microcontroller
5. Block diagram
Figure 3 shows the LPC546xx block diagram. In this figure, orange shaded blocks support
general purpose DMA and yellow shaded blocks include dedicated DMA control.
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Product data sheet Rev. 1.6 — 21 April 2017 9 of 160
NXP Semiconductors LPC546xx
32-bit ARM Cortex-M4 microcontroller
Fig 3. LPC5 4 6x x Bloc k dia gram
DEBUG INTERFACE
ISP access
port
JTAG test and
boundary scan
interface
ethernet
PHY interface
LCD
panel
SDIO
interface
CAN
interface
FS USB
bus or
transceiver
ARM CORTEX-M4
WITH FPU/MPU
D-code
bus
system
bus
I-code
bus
aaa-026740
GENERAL
PURPOSE
DMA
CONTROLLER
ETHERNET
10/100
MAC
+AVB
LCD
PANEL
INTERFACE
USB 2.0
HOST/
DEVICE
HD
SDIO CAN
FD
CAN
FD
clocks
and
controls
internal
power
CLOCK GENERATION,
POWER CONTROL,
AND OTHER
SYSTEM FUNCTIONS
VOLTAGE REGULATOR
Xtalin Xtalout RST
CLK
OUT
SPIFI
ADC
inputs
D[31:0]
A[25:0]
control
GPIO
Vdd
HS USB
PHY
BOOT ROM
64 kB
SRAM
32 kB
SRAM
32 kB
SRAM
32 kB
SRAM
32 kB
12b ADC
12-CH
TEMP
SENSOR
POLYFUSE OTP
256 b
STATIC/DYNAMIC EXT
MEMORY CONTROLLER
HS USB
HOST
REGISTERS
FS USB
HOST
REGISTERS
USB RAM
INTERFACE
SRAM
8 kB
EEPROM
UP TO 16 kB
SPI FLASH
INTERFACE
SRAM
64 kB
FLASH
INTERFACE
AND
ACCELERATOR
FLASH
512 MB
HS USB
bus
HS GPIO
0-5
FS USB
DEVICE
REGISTERS
LCD
REGISTERS
DMA
REGISTERS
EMC
REGISTERS
SPIFI
REGISTERS
MULTILAYER
AHB MATRIX
SCTimer/
PWM
FlexComms 0-4
-UARTs 0-4 - I2Cs 0-4
-SPI0s 0-4
CRC
ENGINE
HS USB
DEVICE
REGISTERS
AUDIO SUBSYS
D-MIC,
DECIMATOR, ETC
ETHERNET
REGISTERS
CAN 1
REGISTERS
AHB TO
APB BRIDGE
AHB TO
APB BRIDGE
ASYNC AHB TO
APB BRIDGE
CAN 0
REGISTERS
SYSTEM CONTROL
APB slave group 0
SDIO
REGISTERS
FlexComms 5-9
-UARTs 5-9
-SPI0s 5-9
-I2Cs 5-9 - I2Ss 0,1
I/O CONFIGURATION
Note:
- Orange shaded blocks support Gen. Purpose DMA.
- Yellow shaded blocks include dedicated DMA Ctrl.
GPIO GLOBAL INTRPTS (0, 1)
GPIO INTERRUPT CONTROL
PERIPH INPUT MUX SELECTS
2 x 32-BIT TIMERS (T0, 1)
PMU REGS (+BB, PVT)
APB slave group 1
32-BIT TIMERS (T2)
SYSTEM CONTROL (async regs)
APB slave group 2
2 x 32-BIT TIMERS (T3, 4)
OS TIMER
FLASH 0 REGISTERS
2 x SMARTCARDS
RANDOM NUMBER GEN
REAL TIME
CLOCK
32 kHz
Osc
RTC ALARM RTC POWER
DOMAIN
DIVIDER
MULTI-RATE TIMER
EEPROM REGISTERS
OTP CONTROLLER
WATCHDOG
OSC
WINDOWED WDT
MICRO TICK TIMER
LPC546xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 1.6 — 21 April 2017 10 of 160
NXP Semiconductors LPC546xx
32-bit ARM Cortex-M4 microcontroller
6. Pinning information
6.1 Pinning
Fig 4. TFBGA 180 Pin configuration
Fig 5. LQFP 208 Pin c onfiguratio n
aaa-026026
2468101213141357911
ba ll A 1
inde x a re a
P
N
M
L
K
J
G
E
H
F
D
C
B
A
T ransparent top view
156
53
104
208
157
105
1
52
aaa-026027
LPC546xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 1.6 — 21 April 2017 11 of 160
NXP Semiconductors LPC546xx
32-bit ARM Cortex-M4 microcontroller
6.2 Pin description
On the LPC546xx, digita l pins are grouped into several port s. Each digit al pin can suppor t
several different digital functions (including General Purpose I/O (GPIO)) and an
additional analog function.
Table 4. Pin de scription
Symbol
180-pin, TFBGA
208-pin, LQFP
Reset state [1]
Type
Description
PIO0_0 D6 196 [2] PU I/O PIO0_0 — General-purpose digital input/output pin.
Remark: In ISP mode, this pin is set to the Flexcomm 3 SPI SCK function.
ICAN1_RD — Receiver input for CAN 1.
I/O FC3_SCK — Flexcomm 3: USART or SPI clock.
OCTimer_MAT0 — Match output 0 from Timer 0.
ISCT0_GPI[0] — Pin input 0 to SCTimer/PWM.
OPDM0_CLK — Clock for PDM interface 0, for digital microphone.
PIO0_1 A1 207 [2] PU I/O PIO0_1 — General-purpose digital input/output pin.
Remark: In ISP mode, this pin is set to the Flexcomm 3 SPI SSEL0
function.
OCAN1_TD — Transmitter ou tput for CAN 1.
I/O FC3_CTS_SDA_SSEL0 — Flexcomm 3: USART clear-to-send, I2C data
I/O, SPI Slave Select 0.
ICT0_CAP0 — Capture input 0 to Timer 0.
ISCT0_GPI[1] — Pin input 1 to SCTimer/PWM.
IPDM0_DATA — Data for PDM interface 0 (digital microphone).
PIO0_2/
TRST E9 174 [2] PU I/O PIO0_2 — General-purpose digital input/output pin. In boundary scan
mode: TRST (Test Reset).
Remark: In ISP mode, this pin is set to the Flexcomm 3 SPI MISO function.
I/O FC3_TXD_SCL_MISO — Flexcomm 3: USART transmitter, I2C clock, SPI
master-in/slave-out data.
ICT0_CAP1 — Capture input 1 to Timer 0.
OSCT0_OUT0 — SCTimer/PWM output 0.
ISCT0_GPI[2] — Pin input 2 to SCTimer/PWM.
I/O EMC_D[0] — External Memory interface data [0].
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Product data sheet Rev. 1.6 — 21 April 2017 12 of 160
NXP Semiconductors LPC546xx
32-bit ARM Cortex-M4 microcontroller
PIO0_3/
TCK A10 178 [2] PU I/O PIO0_3 — General-purpose digital input/output pin. In boundary scan
mode: TCK (Test Clock In).
Remark: In ISP mode, this pin is set to the Flexcomm 3 SPI MOSI function.
I/O FC3_RXD_SDA_MOSI — Flexcomm 3: USART receiver, I2C data I/O, SPI
master-out/slave-in data.
OCT0_MAT1 — Match output 1 from Timer 0.
OSCT0_OUT1 — SCTimer/PWM output 1.
ISCT0_GPI3 — Pin input 3 to SCTimer/PWM.
R — Reserved.
I/O EMC_D[1] — External Memory interface data [1].
PIO0_4/
TMS C8 185 [2] PU I/O PIO0_4 — General-purpose digital input/output pin. In boundary scan
mode: TMS (Test Mode Select).
Remark: The state of this pin at Reset in conjunction with PIO0_5 and
PIO0_6 will determine the boot source for the part or if ISP handler is
invoked. See the Boot Process chapter in UM10912 for more details.
ICAN0_RD — Receiver input for CAN 0.
I/O FC4_SCK — Flexcomm 4: USART or SPI clock.
ICT3_CAP0 — Capture input 0 to Timer 3.
ISCT0_GPI4 — Pin input 4 to SCTimer/PWM.
R — Reserved.
I/O EMC_D[2] — External Memory interface data [2].
OENET_MDC — Ethernet management data clock.
PIO0_5/
TDI E7 189 [2] PU I/O PIO0_5 — General-purpose digital input/output pin.
In boundary scan mode: TDI (Test Data In).
Remark: The state of this pin at Reset in conjunction with PIO0_4 and
PIO0_6 will determine the boot source for the part or if ISP handler is
invoked. See the Boot Process chapter in UM10912 for more details.
OCAN0_TD — Transmitter output for CAN 0.
I/O FC4_RXD_SDA_MOSI — Flexcomm 4: USART receiver, I2C data I/O, SPI
master-out/slave-in data.
OCT3_MAT0 — Match output 0 from Timer 3.
ISCT0_GPI5 — Pin input 5 to SCTimer/PWM.
R — Reserved.
I/O EMC_D[3] — External Memory interface data [3].
I/O ENET_MDIO — Ethernet management data I/O.
Table 4. Pin de scription …continued
Symbol
180-pin, TFBGA
208-pin, LQFP
Reset state [1]
Type
Description
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Product data sheet Rev. 1.6 — 21 April 2017 13 of 160
NXP Semiconductors LPC546xx
32-bit ARM Cortex-M4 microcontroller
PIO0_6/
TDO A5 191 [2] PU I/O PIO0_6 — General-purpose digital input/output pin. In boundary scan
mode: TDO (Test Data Out).
Remark: The state of this pin at Reset in conjunction with PIO0_4 and
PIO0_5 will determine the boot source for the part or if ISP handler is
invoked. See the Boot Process chapter in UM10912 for more details.
I/O FC3_SCK — Flexcomm 3: USART or SPI clock.
ICT3_CAP1 — Capture input 1 to Timer 3.
OCT4_MAT0 — Match output 0 from Timer 4.
ISCT0_GPI6 — Pin input 6 to SCTimer/PWM.
R — Reserved.
I/O EMC_D[4] — External Memory interface data [4].
IENET_RX_DV — Ethernet receive data valid.
PIO0_7 H12 125 [2] PU I/O PIO0_7 — General-purpose digital input/output pin.
I/O FC3_RTS_SCL_SSEL1 — Flexcomm 3: USART request-to-send, I2C
clock, SPI slave select 1.
OSD_CLK — SD/MMC clock.
I/O FC5_SCK — Flexcomm 5: USART or SPI clock.
I/O FC1_SCK — Flexcomm 1: USART or SPI clock.
OPDM1_CLK — Clock for PDM interface 1, for digital microphone.
I/O EMC_D[5] — External Memory interface data [5].
IENET_RX_CLK — Ethernet Receive Clock (MII interface) or Ethernet
Referenc e Cl o ck (RMII interface).
PIO0_8 H10 133 [2] PU I/O PIO0_8 — General-purpose digital input/output pin.
I/O FC3_SSEL3 — Flexcomm 3: SPI slave select 3.
I/O SD_CMD — SD/MMC card command I/O.
I/O FC5_RXD_SDA_MOSI — Flexcomm 5: USART receiver, I2C data I/O, SPI
master-out/slave-in data.
OSWO — Serial Wire Debug trace output.
IPDM1_DATA — Data for PDM interface 1 (digital microphone).
I/O EMC_D[6] — External Memory interface data [6].
PIO0_9 G12 136 [2] PU I/O PIO0_9 — General-purpose digital input/output pin.
I/O FC3_SSEL2 — Flexcomm 3: SPI slave select 2.
OSD_POW_EN — SD/MMC card power enable.
I/O FC5_TXD_SCL_MISO — Flexcomm 5: USART transmitter, I2C clock, SPI
master-in/slave-out data.
R — Reserved.
I/O SCI1_IO — SmartCard Interface 1 data I/O.
I/O EMC_D[7] — External Memory interface data [7].
Table 4. Pin de scription …continued
Symbol
180-pin, TFBGA
208-pin, LQFP
Reset state [1]
Type
Description
LPC546xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 1.6 — 21 April 2017 14 of 160
NXP Semiconductors LPC546xx
32-bit ARM Cortex-M4 microcontroller
PIO0_10/
ADC0_0 P2 50 [4] PU I/O;
AI PIO0_10/ADC0_0 — General-purpose digital input/output pin. ADC input
channel 0 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.
I/O FC6_SCK — Flexcomm 6: USART, SPI, or I2S clock.
ICT2_CAP2 — Capture input 2 to Timer 2.
OCT2_MAT0 — Match output 0 from Timer 2.
I/O FC1_TXD_SCL_MISO — Flexcomm 1: USART transmitter, I2C clock, SPI
master-in/slave-out data.
R — Reserved.
OSWO — Serial Wire Debug trace output.
PIO0_11/
ADC0_1 L3 51 [4] PU I/O;
AI PIO0_11/ADC0_1 — General-purpose digital input/output pin. ADC input
channel 1 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.
I/O FC6_RXD_SDA_MOSI_DATA — Flexcomm 6: USART receiver, I2C data
I/O, SPI master-out/slave-in data, I2S data I/O.
OCT2_MAT2 — Match output 2 from Timer 2.
IFREQME_GPIO_CLK_A — Frequency Measure pin clock input A.
R — Reserved.
R — Reserved.
ISWCLK — Serial Wire Debug clock. This is the default function after
booting.
PIO0_12/
ADC0_2 M3 52 [4] PU I/O;
AI PIO0_12/ADC0_2 — General-purpose digital input/output pin. ADC input
channel 2 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.
I/O FC3_TXD_SCL_MISO — Flexcomm 3: USART transmitter, I2C clock, SPI
master-in/slave-ou t data.
R — Reserved.
IFREQME_GPIO_CLK_B — Frequency Measure pin clock input B.
ISCT0_GPI7 — Pin input 7 to SCTimer/PWM.
R — Reserved.
I/O SWDIO — Serial Wire Debug I/O. This is the default function after booting.
PIO0_13 F11 141 [3] ZI/OPIO0_13 — General-purpose digital input/output pin.
Remark: In ISP mode, this pin is set to the Flexcomm 1 I2C SDA function.
I/O FC1_CTS_SDA_SSEL0 — Flexcomm 1: USART clear-to-send, I2C data
I/O, SPI Slave Select 0.
IUTICK_CAP0 — Micro-tick timer capture input 0.
ICT0_CAP0 — Capture input 0 to Timer 0.
ISCT0_GPI0 — Pin input 0 to SCTimer/PWM.
R — Reserved.
R — Reserved.
IENET_RXD0 — Ethernet receive data 0.
Table 4. Pin de scription …continued
Symbol
180-pin, TFBGA
208-pin, LQFP
Reset state [1]
Type
Description
LPC546xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 1.6 — 21 April 2017 15 of 160
NXP Semiconductors LPC546xx
32-bit ARM Cortex-M4 microcontroller
PIO0_14 E13 144 [3] ZI/OPIO0_14 — General-purpose digital input/output pin.
Remark: In ISP mode, this pin is set to the Flexcomm 1 I2C SCL function.
I/O FC1_RTS_SCL_SSEL1 — Flexcomm 1: USART request-to-send, I2C
clock, SPI slave select 1.
IUTICK_CAP1 — Micro-tick timer capture input 1.
ICT0_CAP1 — Capture input 1 to Timer 0.
ISCT0_GPI1 — Pin input 1 to SCTimer/PWM.
R — Reserved.
R — Reserved.
IENET_RXD1 — Ethernet receive data 1.
PIO0_15/
ADC0_3 L4 53 [4] PU I/O;
AI PIO0_15/ADC0_3 — General-purpose digital input/output pin. ADC input
channel 3 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.
I/O FC6_CTS_SDA_SSEL0 — Flexcomm 6: USART clear-to-send, I2C data
I/O, SPI Slave Select 0.
IUTICK_CAP2 — Micro-tick timer capture input 2.
ICT4_CAP0 — Capture input 4 to Timer 0.
OSCT0_OUT2 — SCTimer/PWM output 2.
R — Reserved.
OEMC_WEN — External memory interface Wr ite Enable (active low).
OENET_TX_EN — Ethernet transmit enable (RMII/MII inte rface).
PIO0_16/
ADC0_4 M4 54 [4] PU I/O;
AI PIO0_16/ADC0_4 — General-purpose digital input/output pin. ADC input
channel 4 if the DIGIMODE bit is set to 0 in the IOCON register for this
pin.ws
I/O FC4_TXD_SCL_MISO — Flexcomm 4: USART transmitter, I2C clock, SPI
master-in/slave-out data.
OCLKOUT — Ou tput of the CLKOUT function.
ICT1_CAP0 — Capture input 0 to Timer 1.
R — Reserved.
R — Reserved.
OEMC_CSN[0] — External memory interface static chip select 0 (active low).
OENET_TXD0 — Ethernet transmit data 0.
PIO0_17 E14 146 [2] PU I/O PIO0_17 — General-purpose digital input/output pin.
I/O FC4_SSEL2 — Flexcomm 4: SPI slave select 2.
ISD_CARD_DET_N — SD/MMC card detect (active low).
ISCT0_GPI7 — Pin input 7 to SCTimer/PWM.
OSCT0_OUT0 — SCTimer/PWM output 0.
R — Reserved.
OEMC_OEN — External memory interface o utput enable (active low)
OENET_TXD1 — Ethernet transmit data 1.
Table 4. Pin de scription …continued
Symbol
180-pin, TFBGA
208-pin, LQFP
Reset state [1]
Type
Description
LPC546xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 1.6 — 21 April 2017 16 of 160
NXP Semiconductors LPC546xx
32-bit ARM Cortex-M4 microcontroller
PIO0_18 C14 150 [2] PU I/O PIO0_18 — General-purpose digital input/output pin.
I/O FC4_CTS_SDA_SSEL0 — Flexcomm 4: USART clear-to-send, I2C data
I/O, SPI Slave Select 0.
ISD_WR_PRT — SD/MMC write protect.
OCT1_MAT0 — Match output 0 from Timer 1.
OSCT0_OUT1 — SCTimer/PWM output 1.
OSCI1_SCLK — SmartCard Interface 1 clock.
OEMC_A[0] — External memory interface address 0.
PIO0_19 C6 193 [2] PU I/O PIO0_19 — General-purpose digital input/output pin.
I/O FC4_RTS_SCL_SSEL1 — Flexcomm 4: USART request-to-send, I2C
clock, SPI slave select 1.
IUTICK_CAP0 — Micro-tick timer capture input 0.
OCT0_MAT2 — Match output 2 from Timer 0.
OSCT0_OUT2 — SCTimer/PWM output 2.
R — Reserved.
OEMC_A[1] — External memory interface address 1.
I/O FC7_TXD_SCL_MISO_WS — Flexcomm 7: USART transmitter, I2C clock,
SPI master-in/slave-out data I/O, I2S word-select/frame.
PIO0_20 D13 153 [2] PU I/O PIO0_20 — General-purpose digital input/output pin.
I/O FC3_CTS_SDA_SSEL0 — Flexcomm 3: USART clear-to-send, I2C data
I/O, SPI Slave Select 0.
OCT1_MAT1 — Match output 1 from Timer 1.
ICT3_CAP3 — Capture input 3 to Timer 3.
ISCT0_GPI2 — Pin input 2 to SCTimer/PWM.
I/O SCI0_IO — SmartCard Interface 0 data I/O.
OEMC_A[2] — External memory interface address 2.
I/O FC7_RXD_SDA_MOSI_DATA — Flexcomm 7: USART receiver, I2C data
I/O, SPI master-out/slave-in data, I2S data I/O.
PIO0_21 C13 158 [2] PU I/O PIO0_21 — General-purpose digital input/output pin.
I/O FC3_RTS_SCL_SSEL1 — Flexcomm 3: USART request-to-send, I2C
clock, SPI slave select 1.
IUTICK_CAP3 — Micro-tick timer capture input 3.
OCT3_MAT3 — Match output 3 from Timer 3.
ISCT0_GPI3 — Pin input 3 to SCTimer/PWM.
OSCI0_SCLK — SmartCard Interface 0 clock.
OEMC_A[3] — External memory interface address 3.
I/O FC7_SCK — Flexcomm 7: USART, SPI, or I2S clock.
Table 4. Pin de scription …continued
Symbol
180-pin, TFBGA
208-pin, LQFP
Reset state [1]
Type
Description
LPC546xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 1.6 — 21 April 2017 17 of 160
NXP Semiconductors LPC546xx
32-bit ARM Cortex-M4 microcontroller
PIO0_22 B12 163 [2] PU I/O PIO0_22 — General-purpose digital input/output pin.
I/O FC6_TXD_SCL_MISO_WS — Flexcomm 6: USART transmitter, I2C clock,
SPI master-in/slave-out data I/O, I2S word-select/frame.
IUTICK_CAP1 — Micro-tick timer capture input 1.
ICT3_CAP3 — Capture input 3 to Timer 3.
OSCT0_OUT3 — SCTimer/PWM output 3.
R — Reserved.
R — Reserved.
IUSB0_VBUS — Monitors the presence of USB0 bus power.
PIO0_23/
ADC0_11 N7 71 [4] PU I/O;
AI PIO0_23/ADC0_11 — General-purpose digital input/output pin. ADC input
channel 11 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.
I/O MCLK — MCLK input or output for I2S and/or digital microphone.
OCT1_MAT2 — Match output 2 from Timer 1.
OCT3_MAT3 — Match output 3 from Timer 3.
OSCT0_OUT4 — SCTimer/PWM output 4.
R — Reserved.
I/O SPIFI_CSN — SPI Flash Interface chip select (active low).
PIO0_24 M7 76 [2] PU I/O PIO0_24 — General-purpose digital input/output pin.
I/O FC0_RXD_SDA_MOSI — Flexcomm 0: USART receiver, I2C data I/O, SPI
master-out/slave-in data.
I/O SD_D[0] — SD/MMC data 0.
ICT2_CAP0 — Capture input 0 to Timer 2.
ISCT0_GPI0 — Pin input 0 to SCTimer/PWM.
R — Reserved.
I/O SPIFI_IO0 — Data bit 0 for the SPI Flash Interface.
PIO0_25 K8 83 [2] PU I/O PIO0_25 — General-purpose digital input/output pin.
I/O FC0_TXD_SCL_MISO — Flexcomm 0: USART transmitter, I2C clock, SPI
master-in/slave-out data.
I/O SD_D[1] — SD/MMC data 1.
ICT2_CAP1 — Capture input 1 to Timer 2.
ISCT0_GPI1 — Pin input 1 to SCTimer/PWM.
R — Reserved.
I/O SPIFI_IO1 — Data bit 1 for the SPI Flash Interface.
Table 4. Pin de scription …continued
Symbol
180-pin, TFBGA
208-pin, LQFP
Reset state [1]
Type
Description
LPC546xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 1.6 — 21 April 2017 18 of 160
NXP Semiconductors LPC546xx
32-bit ARM Cortex-M4 microcontroller
PIO0_26 M1
3110 [2] PU I/O PIO0_26 — General-purpose digital input/output pin.
I/O FC2_RXD_SDA_MOSI — Flexcomm 2: USART receiver, I2C data I/O, SPI
master-out/slave-in data.
OCLKOUT — Ou tput of the CLKOUT function.
ICT3_CAP2 — Capture input 2 to Timer 3.
OSCT0_OUT5 — SCTimer/PWM output 5.
OPDM0_CLK — Clock for PDM interface 0, for digital microphone.
OSPIFI_CLK — Clock output for the SPI Flash Interface.
IUSB0_IDVALUE — Indicates to the tran sceiver whether connected as an
A-device (USB0_ID LOW) or B-device (USB0_ID HIGH).
PIO0_27 L9 87 [2] PU I/O PIO0_27 — General-purpose digital input/output pin.
I/O FC2_TXD_SCL_MISO — Flexcomm 2: USART transmitter, I2C clock, SPI
master-in/slave-out data.
R — Reserved.
OCT3_MAT2 — Match output 2 from Timer 3.
OSCT0_OUT6 — SCTimer/PWM output 6.
IPDM0_DATA — Data for PDM interface 0 (digital microphone).
I/O SPIFI_IO3 — Data bit 3 for the SPI Flash Interface.
PIO0_28 M9 91 [2] PU I/O PIO0_28 — General-purpose digital input/output pin.
I/O FC0_SCK — Flexcomm 0: USART or SPI clock.
R — Reserved.
ICT2_CAP3 — Capture 3 input to Timer 2.
OSCT0_OUT7 — SCTimer/PWM output 7.
OTRACEDATA[3] — Trace data bit 3.
I/O SPIFI_IO2 — Data bit 2 for the SPI Flash Interface.
IUSB0_OVERCURRENTN — USB0 bus overcurrent indicator (active low).
PIO0_29 B13 167 [2] PU I/O PIO0_29 — General-purpose digital input/output pin.
Remark: In ISP mode, this pin is set to the Flexcomm 0 USART RXD
function.
I/O FC0_RXD_SDA_MOSI — Flexcomm 0: USART receiver, I2C data I/O, SPI
master-out/slave-in data.
R — Reserved.
OCT2_MAT3 — Match output 3 from Timer 2.
OSCT0_OUT8 — SCTimer/PWM output 8.
OTRACEDATA[2] — Trace data bit 2.
Table 4. Pin de scription …continued
Symbol
180-pin, TFBGA
208-pin, LQFP
Reset state [1]
Type
Description