LPC546xx 32-bit ARM Cortex-M4 microcontroller; up to 512 KB flash and 200 kB SRAM; High-speed USB device/host + PHY; Full-speed USB device/host; Ethernet AVB; LCD; EMC; SPIFI; CAN FD, SDIO; 12-bit 5 Msamples/s ADC; DMIC subsystem Rev. 1.6 -- 21 April 2017 Product data sheet 1. General description The LPC546xx is a family of ARM Cortex-M4 based microcontrollers for embedded applications featuring a rich peripheral set with very low power consumption and enhanced debug features. The ARM Cortex-M4 is a 32-bit core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching. The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A hardware floating-point processor is integrated into the core. The LPC546xx family includes up to 512 KB of flash, 200 KB of on-chip SRAM, up to 16 kB of EEPROM memory, a quad SPI Flash Interface (SPIFI) for expanding program memory, one high-speed and one full-speed USB host and device controller, Ethernet AVB, LCD controller, Smart Card Interfaces, SD/MMC, CAN FD, an External Memory Controller (EMC), a DMIC subsystem with PDM microphone interface and I2S, five general-purpose timers, SCTimer/PWM, RTC/alarm timer, Multi-Rate Timer (MRT), a Windowed Watchdog Timer (WWDT), ten flexible serial communication peripherals (USART, SPI, I2S, I2C interface), 12-bit 5.0 Msamples/sec ADC, temperature sensor. 2. Features and benefits ARM Cortex-M4 core (version r0p1): ARM Cortex-M4 processor, running at a frequency of up to 180 MHz. Floating Point Unit (FPU) and Memory Protection Unit (MPU). ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC). Non-maskable Interrupt (NMI) input with a selection of sources. Serial Wire Debug (SWD) with six instruction breakpoints, two literal comparators, and four watch points. Includes Serial Wire Output and ETM Trace for enhanced debug capabilities, and a debug timestamp counter. System tick timer. On-chip memory: Up to 512 KB on-chip flash program memory with flash accelerator and 256 byte page erase and write. LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Up to 200 KB total SRAM consisting of 160 KB contiguous main SRAM and an additional 32 KB SRAM on the I&D buses. 8 KB of SRAM bank intended for USB traffic. 16 KB of EEPROM. ROM API support: Flash In-Application Programming (IAP) and In-System Programming (ISP). ROM-based USB drivers (HID, CDC, MSC, and DFU). Flash updates via USB. Booting from valid user code in flash, USART, SPI, and I2C. Legacy, Single, and Dual image boot. OTP API for programming OTP memory. Random Number Generator (RNG) API. Serial interfaces: Flexcomm Interface contains ten serial peripherals. Each Flexcomm Interface can be selected by software to be a USART, SPI, or I2C interface. Two Flexcomm Interfaces also include an I2S interface. Each Flexcomm Interface includes a FIFO that supports USART, SPI, and I2S if supported by that Flexcomm Interface. A variety of clocking options are available to each Flexcomm Interface and include a shared fractional baud-rate generator. I2C-bus interfaces support Fast-mode and Fast-mode Plus with data rates of up to 1Mbit/s and with multiple address recognition and monitor mode. Two sets of true I2C pads also support High Speed Mode (3.4 Mbit/s) as a slave. Two ISO 7816 Smart Card Interfaces with DMA support. USB 2.0 high-speed host/device controller with on-chip high-speed PHY. USB 2.0 full-speed host/device controller with on-chip PHY and dedicated DMA controller supporting crystal-less operation in device mode. SPIFI with XIP feature uses up to four data lines to access off-chip SPI/DSPI/QSPI flash memory at a much higher rate than standard SPI or SSP interfaces. Ethernet MAC with MII/RMII interface with Audio Video Bridging (AVB) support and dedicated DMA controller. Two CAN FD modules with dedicated DMA controller. Digital peripherals: DMA controller with 30 channels and up to 24 programmable triggers, able to access all memories and DMA-capable peripherals. LCD Controller supporting both Super-Twisted Nematic (STN) and Thin-Film Transistor (TFT) displays. It has a dedicated DMA controller, selectable display resolution (up to 1024 x 768 pixels), and supports up to 24-bit true-color mode. External Memory Controller (EMC) provides support for asynchronous static memory devices such as RAM, ROM and flash, in addition to dynamic memories such as single data rate SDRAM with an SDRAM clock of up to 100 MHz. Secured digital input/output (SD/MMC and SDIO) card interface with DMA support. CRC engine block can calculate a CRC on supplied data using one of three standard polynomials with DMA support. Up to 171 General-Purpose Input/Output (GPIO) pins. GPIO registers are located on the AHB for fast access. The DMA supports GPIO ports. Up to eight GPIOs can be selected as Pin Interrupts (PINT), triggered by rising, falling or both input edges. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 2 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller LPC546xx Product data sheet Two GPIO Grouped Interrupts (GINT) enable an interrupt based on a logical (AND/OR) combination of input states. CRC engine. Analog peripherals: 12-bit ADC with 12 input channels and with multiple internal and external trigger inputs and sample rates of up to 5.0 MSamples/sec. The ADC supports two independent conversion sequences. Integrated temperature sensor connected to the ADC. DMIC subsystem including a dual-channel PDM microphone interface, flexible decimators, 16 entry FIFOs, optional DC locking, hardware voice activity detection, and the option to stream the processed output data to I2S. Timers: Five 32-bit general purpose timers/counters, four of which support up to four capture inputs and four compare outputs, PWM mode, and external count input. Specific timer events can be selected to generate DMA requests. The fifth timer does not have external pin connections and may be used for internal timing operations. One SCTimer/PWM with eight input and ten output functions (including capture and match). Inputs and outputs can be routed to or from external pins and internally to or from selected peripherals. Internally, the SCTimer/PWM supports 16 match/captures, 16 events, and 16 states. 32-bit Real-time clock (RTC) with 1 s resolution running in the always-on power domain. A timer in the RTC can be used for wake-up from all low power modes including deep power-down, with 1 ms resolution. Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation at up to four programmable, fixed rates. Windowed Watchdog Timer (WWDT). Repetitive Interrupt Timer (RIT) for debug time stamping and for general purpose use. Security features: Random number generator can be used to create keys with DMA support. enhanced Code Read Protection (eCRP) to protect user code. OTP memory for ECRP settings and user application specific data. Clock generation: 12 MHz internal Free Running Oscillator (FRO). This oscillator provides a selectable 48 MHz or 96 MHz output, and a 12 MHz output (divided down from the selected higher frequency) that can be used as a system clock. The FRO is trimmed to 1 % accuracy over the entire voltage and temperature range. External clock input for clock frequencies of up to 25 MHz. Crystal oscillator with an operating range of 1 MHz to 25 MHz. Watchdog Oscillator (WDTOSC) with a frequency range of 6 kHz to 1.5 MHz. 32.768 kHz low-power RTC oscillator. System PLL allows CPU operation up to the maximum CPU rate and can run from the main oscillator, the internal FRO, the watchdog oscillator or the 32.768 KHz RTC oscillator. Two additional PLLs for USB clock and audio subsystem. Independent clocks for the SPIFI interface, ADC, USBs, and the audio subsystem. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 3 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller LPC546xx Product data sheet Clock output function with divider. Frequency measurement unit for measuring the frequency of any on-chip or off-chip clock signal. Power control: Programmable PMU (Power Management Unit) to minimize power consumption and to match requirements at different performance levels. Reduced power modes: sleep, deep-sleep, and deep power-down. Wake-up from deep-sleep modes due to activity on the USART, SPI, and I2C peripherals when operating as slaves. Ultra-low power Micro-tick Timer, running from the Watchdog oscillator that can be used to wake up the device from low power modes. Power-On Reset (POR). Brown-Out Detect (BOD) with separate thresholds for interrupt and forced reset. Single power supply 1.71 V to 3.6 V. Power-On Reset (POR). Brown-Out Detect (BOD) with separate thresholds for interrupt and forced reset. JTAG boundary scan supported. 128 bit unique device serial number for identification. Operating temperature range 40 C to +105 C. Available in TFBGA180 and LQFP208 packages. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 4 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 3. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC54605J256ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 12 0.8 mm SOT570-3 LPC54605J512ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 12 0.8 mm SOT570-3 LPC54606J256ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 12 0.8 mm SOT570-3 LPC54606J512BD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1 LPC54607J256ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 12 0.8 mm SOT570-3 LPC54607J512ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 12 0.8 mm SOT570-3 LPC54607J256BD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1 LPC54608J512ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 12 0.8 mm SOT570-3 LPC54608J512BD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1 LPC54616J256ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 12 0.8 mm SOT570-3 LPC54616J512BD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1 LPC54618J512ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 12 0.8 mm SOT570-3 LPC54618J512BD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1 3.1 Ordering options Ordering options HS USB Ethernet AVB Classic CAN CAN FD0/FD1 LCD GPIO TFBGA180 512 200 yes yes yes yes yes yes 145 LPC54618J512BD208 LQFP208 512 200 yes yes yes yes yes yes 171 Flash/kB SRAM/kB LPC54618J512ET180 Type number FS USB Package Name Table 2. LPC54618 devices (HS/FS USB, Ethernet, CAN FD, LCD) LPC54616 devices (HS/FS USB, Ethernet, CAN FD) LPC54616J256ET180 TFBGA180 256 136 yes yes yes no yes no 145 LPC54616J512BD208 LQFP208 512 200 yes yes yes no yes no 171 LPC54608 devices (HS/FS USB, Ethernet, CAN 2.0, LCD) LPC54608J512ET180 TFBGA180 512 200 yes yes yes yes no yes 145 LPC54608J512BD208 LQFP208 512 200 yes yes yes yes no yes 171 LPC54607 devices (HS/FS USB, LCD) LPC54607J256ET180 TFBGA180 256 136 yes yes no no no yes 145 LPC54607J512ET180 TFBGA180 512 200 yes yes no no no yes 145 LPC54607J256BD208 LQFP208 256 136 yes yes no no no yes 171 LPC54606 devices (HS/FS USB, Ethernet, CAN 2.0) LPC54606J256ET180 TFBGA180 256 136 yes yes yes yes no no 145 LPC54606J512BD208 LQFP208 512 200 yes yes yes yes no no 171 LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 5 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Ordering options ...continued SRAM/kB FS USB HS USB Ethernet AVB Classic CAN CAN FD0/FD1 LCD GPIO LPC54605J256ET180 TFBGA180 256 136 yes yes no no no no 145 LPC54605J512ET180 TFBGA180 512 200 yes yes no no no no 145 Type number Flash/kB Package Name Table 2. LPC54605 devices (HS/FS USB) LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 6 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 4. Marking Terminal 1 index area n Terminal 1 index area 1 aaa-025721 Fig 1. TFBGA180 package marking aaa-011231 Fig 2. LQFP208 package marking The LPC546xx TFBGA180 package has the following top-side marking: * First line: LPC546xxJyyy - yyy: flash size * Second line: ET180 * Third line: xxxxxxxxxxxx * Fourth line: xxxyywwx[R]x - yyww: Date code with yy = year and ww = week. - xR = boot code version and device revision. The LPC546xx LQFP208 package has the following top-side marking: * First line: LPC546xxJyyy - yyy: flash size * Second line: BD208 * Third line: xxxxxxxxxxxx * Fourth line: xxxyywwx[R]x - yyww: Date code with yy = year and ww = week. - xR = Boot code version and device revision. Table 3. Device revision table Revision identifier (R) Revision description 1A Initial device revision with Boot ROM version 19.1 LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 7 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 5. Block diagram Figure 3 shows the LPC546xx block diagram. In this figure, orange shaded blocks support general purpose DMA and yellow shaded blocks include dedicated DMA control. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 8 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller JTAG test and ISP access boundary scan interface port DEBUG INTERFACE ARM CORTEX-M4 WITH FPU/MPU I-code bus FS USB bus or transceiver ethernet PHY interface LCD panel ETHERNET 10/100 MAC +AVB LCD PANEL INTERFACE GENERAL PURPOSE DMA CONTROLLER SDIO interface USB 2.0 HOST/ DEVICE H D SDIO CAN interface CAN FD Xtalin Xtalout CAN FD D-code system bus bus RST clocks and controls CLOCK GENERATION, POWER CONTROL, AND OTHER SYSTEM FUNCTIONS CLK OUT internal power VOLTAGE REGULATOR Vdd BOOT ROM 64 kB FLASH INTERFACE AND ACCELERATOR HS USB PHY HS USB bus FLASH 512 MB SRAM 32 kB SPI FLASH INTERFACE SPIFI SRAM 64 kB SRAM 32 kB MULTILAYER AHB MATRIX SRAM 32 kB SRAM 32 kB FS USB HOST REGISTERS EEPROM UP TO 16 kB HS USB HOST REGISTERS 12b ADC 12-CH POLYFUSE OTP 256 b USB RAM INTERFACE TEMP SENSOR SRAM 8 kB STATIC/DYNAMIC EXT MEMORY CONTROLLER HS GPIO 0-5 SPIFI REGISTERS EMC REGISTERS DMA REGISTERS LCD REGISTERS FS USB DEVICE REGISTERS CAN 0 REGISTERS CAN 1 REGISTERS ETHERNET REGISTERS HS USB DEVICE REGISTERS CRC ENGINE APB slave group 0 SYSTEM CONTROL AHB TO APB BRIDGE AHB TO APB BRIDGE FlexComms 0-4 -UARTs 0-4 - I2Cs 0-4 -SPI0s 0-4 FlexComms 5-9 -UARTs 5-9 -SPI0s 5-9 -I2Cs 5-9 - I2Ss 0,1 SYSTEM CONTROL (async regs) 2 x 32-BIT TIMERS (T3, 4) APB slave group 1 PMU REGS (+BB, PVT) PERIPH INPUT MUX SELECTS 32-BIT TIMERS (T2) 2 x 32-BIT TIMERS (T0, 1) OS TIMER MULTI-RATE TIMER FLASH 0 REGISTERS EEPROM REGISTERS 2 x SMARTCARDS OTP CONTROLLER RANDOM NUMBER GEN WINDOWED WDT RTC ALARM MICRO TICK TIMER REAL TIME CLOCK Note: - Orange shaded blocks support Gen. Purpose DMA. - Yellow shaded blocks include dedicated DMA Ctrl. Fig 3. D[31:0] A[25:0] control GPIO APB slave group 2 ASYNC AHB TO APB BRIDGE GPIO INTERRUPT CONTROL WATCHDOG OSC SDIO REGISTERS AUDIO SUBSYS D-MIC, DECIMATOR, ETC I/O CONFIGURATION GPIO GLOBAL INTRPTS (0, 1) SCTimer/ PWM ADC inputs RTC POWER DOMAIN DIVIDER 32 kHz Osc aaa-026740 LPC546xx Block diagram LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 9 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 6. Pinning information 6.1 Pinning ball A1 index area 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A B C D E F G H J K L M N P aaa-026026 Transparent top view 157 TFBGA 180 Pin configuration 208 156 52 105 53 1 104 Fig 4. aaa-026027 Fig 5. LPC546xx Product data sheet LQFP 208 Pin configuration All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 10 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 6.2 Pin description On the LPC546xx, digital pins are grouped into several ports. Each digital pin can support several different digital functions (including General Purpose I/O (GPIO)) and an additional analog function. D6 196 [2] Type PIO0_0 Description Reset state [1] Symbol 208-pin, LQFP Pin description 180-pin, TFBGA Table 4. PU I/O PIO0_0 -- General-purpose digital input/output pin. Remark: In ISP mode, this pin is set to the Flexcomm 3 SPI SCK function. PIO0_1 A1 207 [2] I CAN1_RD -- Receiver input for CAN 1. I/O FC3_SCK -- Flexcomm 3: USART or SPI clock. O CTimer_MAT0 -- Match output 0 from Timer 0. I SCT0_GPI[0] -- Pin input 0 to SCTimer/PWM. O PDM0_CLK -- Clock for PDM interface 0, for digital microphone. PU I/O PIO0_1 -- General-purpose digital input/output pin. Remark: In ISP mode, this pin is set to the Flexcomm 3 SPI SSEL0 function. PIO0_2/ TRST E9 174 [2] O CAN1_TD -- Transmitter output for CAN 1. I/O FC3_CTS_SDA_SSEL0 -- Flexcomm 3: USART clear-to-send, I2C data I/O, SPI Slave Select 0. I CT0_CAP0 -- Capture input 0 to Timer 0. I SCT0_GPI[1] -- Pin input 1 to SCTimer/PWM. I PDM0_DATA -- Data for PDM interface 0 (digital microphone). PU I/O PIO0_2 -- General-purpose digital input/output pin. In boundary scan mode: TRST (Test Reset). Remark: In ISP mode, this pin is set to the Flexcomm 3 SPI MISO function. LPC546xx Product data sheet I/O FC3_TXD_SCL_MISO -- Flexcomm 3: USART transmitter, I2C clock, SPI master-in/slave-out data. I CT0_CAP1 -- Capture input 1 to Timer 0. O SCT0_OUT0 -- SCTimer/PWM output 0. I SCT0_GPI[2] -- Pin input 2 to SCTimer/PWM. I/O EMC_D[0] -- External Memory interface data [0]. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 11 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Pin description ...continued A10 178 Reset state [1] [2] Type PIO0_3/ TCK Description 208-pin, LQFP Symbol 180-pin, TFBGA Table 4. PU I/O PIO0_3 -- General-purpose digital input/output pin. In boundary scan mode: TCK (Test Clock In). Remark: In ISP mode, this pin is set to the Flexcomm 3 SPI MOSI function. I/O FC3_RXD_SDA_MOSI -- Flexcomm 3: USART receiver, I2C data I/O, SPI master-out/slave-in data. O CT0_MAT1 -- Match output 1 from Timer 0. O SCT0_OUT1 -- SCTimer/PWM output 1. I SCT0_GPI3 -- Pin input 3 to SCTimer/PWM. R -- Reserved. I/O PIO0_4/ TMS C8 185 [2] PU I/O EMC_D[1] -- External Memory interface data [1]. PIO0_4 -- General-purpose digital input/output pin. In boundary scan mode: TMS (Test Mode Select). Remark: The state of this pin at Reset in conjunction with PIO0_5 and PIO0_6 will determine the boot source for the part or if ISP handler is invoked. See the Boot Process chapter in UM10912 for more details. I CAN0_RD -- Receiver input for CAN 0. I/O FC4_SCK -- Flexcomm 4: USART or SPI clock. I CT3_CAP0 -- Capture input 0 to Timer 3. I SCT0_GPI4 -- Pin input 4 to SCTimer/PWM. R -- Reserved. PIO0_5/ TDI E7 189 [2] I/O EMC_D[2] -- External Memory interface data [2]. O ENET_MDC -- Ethernet management data clock. PU I/O PIO0_5 -- General-purpose digital input/output pin. In boundary scan mode: TDI (Test Data In). Remark: The state of this pin at Reset in conjunction with PIO0_4 and PIO0_6 will determine the boot source for the part or if ISP handler is invoked. See the Boot Process chapter in UM10912 for more details. O CAN0_TD -- Transmitter output for CAN 0. I/O FC4_RXD_SDA_MOSI -- Flexcomm 4: USART receiver, I2C data I/O, SPI master-out/slave-in data. O CT3_MAT0 -- Match output 0 from Timer 3. I SCT0_GPI5 -- Pin input 5 to SCTimer/PWM. R -- Reserved. LPC546xx Product data sheet I/O EMC_D[3] -- External Memory interface data [3]. I/O ENET_MDIO -- Ethernet management data I/O. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 12 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller A5 191 [2] Type PIO0_6/ TDO Description Reset state [1] 208-pin, LQFP Pin description ...continued Symbol 180-pin, TFBGA Table 4. PU I/O PIO0_6 -- General-purpose digital input/output pin. In boundary scan mode: TDO (Test Data Out). Remark: The state of this pin at Reset in conjunction with PIO0_4 and PIO0_5 will determine the boot source for the part or if ISP handler is invoked. See the Boot Process chapter in UM10912 for more details. I/O FC3_SCK -- Flexcomm 3: USART or SPI clock. I CT3_CAP1 -- Capture input 1 to Timer 3. O CT4_MAT0 -- Match output 0 from Timer 4. I SCT0_GPI6 -- Pin input 6 to SCTimer/PWM. R -- Reserved. PIO0_7 PIO0_8 PIO0_9 H12 125 H10 133 G12 136 [2] [2] [2] I/O EMC_D[4] -- External Memory interface data [4]. I ENET_RX_DV -- Ethernet receive data valid. PU I/O PIO0_7 -- General-purpose digital input/output pin. I/O FC3_RTS_SCL_SSEL1 -- Flexcomm 3: USART request-to-send, I2C clock, SPI slave select 1. O SD_CLK -- SD/MMC clock. I/O FC5_SCK -- Flexcomm 5: USART or SPI clock. I/O FC1_SCK -- Flexcomm 1: USART or SPI clock. O PDM1_CLK -- Clock for PDM interface 1, for digital microphone. I/O EMC_D[5] -- External Memory interface data [5]. I ENET_RX_CLK -- Ethernet Receive Clock (MII interface) or Ethernet Reference Clock (RMII interface). PU I/O PIO0_8 -- General-purpose digital input/output pin. I/O FC3_SSEL3 -- Flexcomm 3: SPI slave select 3. I/O SD_CMD -- SD/MMC card command I/O. I/O FC5_RXD_SDA_MOSI -- Flexcomm 5: USART receiver, I2C data I/O, SPI master-out/slave-in data. O SWO -- Serial Wire Debug trace output. I PDM1_DATA -- Data for PDM interface 1 (digital microphone). I/O EMC_D[6] -- External Memory interface data [6]. PU I/O PIO0_9 -- General-purpose digital input/output pin. I/O FC3_SSEL2 -- Flexcomm 3: SPI slave select 2. O SD_POW_EN -- SD/MMC card power enable. I/O FC5_TXD_SCL_MISO -- Flexcomm 5: USART transmitter, I2C clock, SPI master-in/slave-out data. R -- Reserved. LPC546xx Product data sheet I/O SCI1_IO -- SmartCard Interface 1 data I/O. I/O EMC_D[7] -- External Memory interface data [7]. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 13 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller P2 50 [4] Type PIO0_10/ ADC0_0 Description Reset state [1] 208-pin, LQFP Pin description ...continued Symbol 180-pin, TFBGA Table 4. PU I/O; PIO0_10/ADC0_0 -- General-purpose digital input/output pin. ADC input AI channel 0 if the DIGIMODE bit is set to 0 in the IOCON register for this pin. I/O FC6_SCK -- Flexcomm 6: USART, SPI, or I2S clock. I CT2_CAP2 -- Capture input 2 to Timer 2. O CT2_MAT0 -- Match output 0 from Timer 2. I/O FC1_TXD_SCL_MISO -- Flexcomm 1: USART transmitter, I2C clock, SPI master-in/slave-out data. R -- Reserved. O PIO0_11/ ADC0_1 L3 51 [4] SWO -- Serial Wire Debug trace output. PU I/O; PIO0_11/ADC0_1 -- General-purpose digital input/output pin. ADC input AI channel 1 if the DIGIMODE bit is set to 0 in the IOCON register for this pin. I/O FC6_RXD_SDA_MOSI_DATA -- Flexcomm 6: USART receiver, I2C data I/O, SPI master-out/slave-in data, I2S data I/O. O CT2_MAT2 -- Match output 2 from Timer 2. I FREQME_GPIO_CLK_A -- Frequency Measure pin clock input A. R -- Reserved. R -- Reserved. I PIO0_12/ ADC0_2 M3 52 [4] SWCLK -- Serial Wire Debug clock. This is the default function after booting. PU I/O; PIO0_12/ADC0_2 -- General-purpose digital input/output pin. ADC input AI channel 2 if the DIGIMODE bit is set to 0 in the IOCON register for this pin. I/O FC3_TXD_SCL_MISO -- Flexcomm 3: USART transmitter, I2C clock, SPI master-in/slave-out data. R -- Reserved. I FREQME_GPIO_CLK_B -- Frequency Measure pin clock input B. I SCT0_GPI7 -- Pin input 7 to SCTimer/PWM. R -- Reserved. PIO0_13 F11 141 [3] Z I/O SWDIO -- Serial Wire Debug I/O. This is the default function after booting. I/O PIO0_13 -- General-purpose digital input/output pin. Remark: In ISP mode, this pin is set to the Flexcomm 1 I2C SDA function. I/O FC1_CTS_SDA_SSEL0 -- Flexcomm 1: USART clear-to-send, I2C data I/O, SPI Slave Select 0. I UTICK_CAP0 -- Micro-tick timer capture input 0. I CT0_CAP0 -- Capture input 0 to Timer 0. I SCT0_GPI0 -- Pin input 0 to SCTimer/PWM. R -- Reserved. R -- Reserved. I LPC546xx Product data sheet ENET_RXD0 -- Ethernet receive data 0. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 14 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Pin description ...continued [3] Type E13 144 Reset state [1] PIO0_14 Description 208-pin, LQFP Symbol 180-pin, TFBGA Table 4. Z I/O PIO0_14 -- General-purpose digital input/output pin. Remark: In ISP mode, this pin is set to the Flexcomm 1 I2C SCL function. I/O FC1_RTS_SCL_SSEL1 -- Flexcomm 1: USART request-to-send, I2C clock, SPI slave select 1. I UTICK_CAP1 -- Micro-tick timer capture input 1. I CT0_CAP1 -- Capture input 1 to Timer 0. I SCT0_GPI1 -- Pin input 1 to SCTimer/PWM. R -- Reserved. R -- Reserved. I PIO0_15/ ADC0_3 L4 53 [4] ENET_RXD1 -- Ethernet receive data 1. PU I/O; PIO0_15/ADC0_3 -- General-purpose digital input/output pin. ADC input AI channel 3 if the DIGIMODE bit is set to 0 in the IOCON register for this pin. I/O FC6_CTS_SDA_SSEL0 -- Flexcomm 6: USART clear-to-send, I2C data I/O, SPI Slave Select 0. I UTICK_CAP2 -- Micro-tick timer capture input 2. I CT4_CAP0 -- Capture input 4 to Timer 0. O SCT0_OUT2 -- SCTimer/PWM output 2. R -- Reserved. PIO0_16/ ADC0_4 M4 54 [4] O EMC_WEN -- External memory interface Write Enable (active low). O ENET_TX_EN -- Ethernet transmit enable (RMII/MII interface). PU I/O; PIO0_16/ADC0_4 -- General-purpose digital input/output pin. ADC input AI channel 4 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.ws I/O FC4_TXD_SCL_MISO -- Flexcomm 4: USART transmitter, I2C clock, SPI master-in/slave-out data. O CLKOUT -- Output of the CLKOUT function. I CT1_CAP0 -- Capture input 0 to Timer 1. R -- Reserved. R -- Reserved. PIO0_17 E14 146 [2] O EMC_CSN[0] -- External memory interface static chip select 0 (active low). O ENET_TXD0 -- Ethernet transmit data 0. PU I/O PIO0_17 -- General-purpose digital input/output pin. I/O FC4_SSEL2 -- Flexcomm 4: SPI slave select 2. I SD_CARD_DET_N -- SD/MMC card detect (active low). I SCT0_GPI7 -- Pin input 7 to SCTimer/PWM. O SCT0_OUT0 -- SCTimer/PWM output 0. R -- Reserved. LPC546xx Product data sheet O EMC_OEN -- External memory interface output enable (active low) O ENET_TXD1 -- Ethernet transmit data 1. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 15 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Pin description ...continued C14 150 PIO0_19 C6 193 Reset state [1] [2] [2] Type PIO0_18 Description 208-pin, LQFP Symbol 180-pin, TFBGA Table 4. PU I/O PIO0_18 -- General-purpose digital input/output pin. I/O FC4_CTS_SDA_SSEL0 -- Flexcomm 4: USART clear-to-send, I2C data I/O, SPI Slave Select 0. I SD_WR_PRT -- SD/MMC write protect. O CT1_MAT0 -- Match output 0 from Timer 1. O SCT0_OUT1 -- SCTimer/PWM output 1. O SCI1_SCLK -- SmartCard Interface 1 clock. O EMC_A[0] -- External memory interface address 0. PU I/O PIO0_19 -- General-purpose digital input/output pin. I/O FC4_RTS_SCL_SSEL1 -- Flexcomm 4: USART request-to-send, I2C clock, SPI slave select 1. I UTICK_CAP0 -- Micro-tick timer capture input 0. O CT0_MAT2 -- Match output 2 from Timer 0. O SCT0_OUT2 -- SCTimer/PWM output 2. R -- Reserved. PIO0_20 D13 153 [2] O EMC_A[1] -- External memory interface address 1. I/O FC7_TXD_SCL_MISO_WS -- Flexcomm 7: USART transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S word-select/frame. PU I/O I/O PIO0_21 LPC546xx Product data sheet C13 158 [2] PIO0_20 -- General-purpose digital input/output pin. FC3_CTS_SDA_SSEL0 -- Flexcomm 3: USART clear-to-send, I2C data I/O, SPI Slave Select 0. O CT1_MAT1 -- Match output 1 from Timer 1. I CT3_CAP3 -- Capture input 3 to Timer 3. I SCT0_GPI2 -- Pin input 2 to SCTimer/PWM. I/O SCI0_IO -- SmartCard Interface 0 data I/O. O EMC_A[2] -- External memory interface address 2. I/O FC7_RXD_SDA_MOSI_DATA -- Flexcomm 7: USART receiver, I2C data I/O, SPI master-out/slave-in data, I2S data I/O. PU I/O PIO0_21 -- General-purpose digital input/output pin. I/O FC3_RTS_SCL_SSEL1 -- Flexcomm 3: USART request-to-send, I2C clock, SPI slave select 1. I UTICK_CAP3 -- Micro-tick timer capture input 3. O CT3_MAT3 -- Match output 3 from Timer 3. I SCT0_GPI3 -- Pin input 3 to SCTimer/PWM. O SCI0_SCLK -- SmartCard Interface 0 clock. O EMC_A[3] -- External memory interface address 3. I/O FC7_SCK -- Flexcomm 7: USART, SPI, or I2S clock. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 16 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Pin description ...continued B12 163 Reset state [1] [2] Type PIO0_22 Description 208-pin, LQFP Symbol 180-pin, TFBGA Table 4. PU I/O PIO0_22 -- General-purpose digital input/output pin. I/O FC6_TXD_SCL_MISO_WS -- Flexcomm 6: USART transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S word-select/frame. I UTICK_CAP1 -- Micro-tick timer capture input 1. I CT3_CAP3 -- Capture input 3 to Timer 3. O SCT0_OUT3 -- SCTimer/PWM output 3. R -- Reserved. R -- Reserved. I PIO0_23/ ADC0_11 N7 71 [4] USB0_VBUS -- Monitors the presence of USB0 bus power. PU I/O; PIO0_23/ADC0_11 -- General-purpose digital input/output pin. ADC input AI channel 11 if the DIGIMODE bit is set to 0 in the IOCON register for this pin. I/O MCLK -- MCLK input or output for I2S and/or digital microphone. O CT1_MAT2 -- Match output 2 from Timer 1. O CT3_MAT3 -- Match output 3 from Timer 3. O SCT0_OUT4 -- SCTimer/PWM output 4. R -- Reserved. I/O PIO0_24 M7 76 [2] PU I/O SPIFI_CSN -- SPI Flash Interface chip select (active low). PIO0_24 -- General-purpose digital input/output pin. I/O FC0_RXD_SDA_MOSI -- Flexcomm 0: USART receiver, I2C data I/O, SPI master-out/slave-in data. I/O SD_D[0] -- SD/MMC data 0. I CT2_CAP0 -- Capture input 0 to Timer 2. I SCT0_GPI0 -- Pin input 0 to SCTimer/PWM. R -- Reserved. I/O PIO0_25 K8 83 [2] PU I/O SPIFI_IO0 -- Data bit 0 for the SPI Flash Interface. PIO0_25 -- General-purpose digital input/output pin. I/O FC0_TXD_SCL_MISO -- Flexcomm 0: USART transmitter, I2C clock, SPI master-in/slave-out data. I/O SD_D[1] -- SD/MMC data 1. I CT2_CAP1 -- Capture input 1 to Timer 2. I SCT0_GPI1 -- Pin input 1 to SCTimer/PWM. R -- Reserved. I/O LPC546xx Product data sheet SPIFI_IO1 -- Data bit 1 for the SPI Flash Interface. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 17 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Pin description ...continued PIO0_27 L9 110 87 [2] [2] Type M1 3 Reset state [1] PIO0_26 Description 208-pin, LQFP Symbol 180-pin, TFBGA Table 4. PU I/O PIO0_26 -- General-purpose digital input/output pin. I/O FC2_RXD_SDA_MOSI -- Flexcomm 2: USART receiver, I2C data I/O, SPI master-out/slave-in data. O CLKOUT -- Output of the CLKOUT function. I CT3_CAP2 -- Capture input 2 to Timer 3. O SCT0_OUT5 -- SCTimer/PWM output 5. O PDM0_CLK -- Clock for PDM interface 0, for digital microphone. O SPIFI_CLK -- Clock output for the SPI Flash Interface. I USB0_IDVALUE -- Indicates to the transceiver whether connected as an A-device (USB0_ID LOW) or B-device (USB0_ID HIGH). PU I/O I/O PIO0_27 -- General-purpose digital input/output pin. FC2_TXD_SCL_MISO -- Flexcomm 2: USART transmitter, I2C clock, SPI master-in/slave-out data. R -- Reserved. PIO0_28 M9 91 [2] O CT3_MAT2 -- Match output 2 from Timer 3. O SCT0_OUT6 -- SCTimer/PWM output 6. I PDM0_DATA -- Data for PDM interface 0 (digital microphone). I/O SPIFI_IO3 -- Data bit 3 for the SPI Flash Interface. PU I/O I/O PIO0_28 -- General-purpose digital input/output pin. FC0_SCK -- Flexcomm 0: USART or SPI clock. R -- Reserved. PIO0_29 B13 167 [2] I CT2_CAP3 -- Capture 3 input to Timer 2. O SCT0_OUT7 -- SCTimer/PWM output 7. O TRACEDATA[3] -- Trace data bit 3. I/O SPIFI_IO2 -- Data bit 2 for the SPI Flash Interface. I USB0_OVERCURRENTN -- USB0 bus overcurrent indicator (active low). PU I/O PIO0_29 -- General-purpose digital input/output pin. Remark: In ISP mode, this pin is set to the Flexcomm 0 USART RXD function. I/O FC0_RXD_SDA_MOSI -- Flexcomm 0: USART receiver, I2C data I/O, SPI master-out/slave-in data. R -- Reserved. LPC546xx Product data sheet O CT2_MAT3 -- Match output 3 from Timer 2. O SCT0_OUT8 -- SCTimer/PWM output 8. O TRACEDATA[2] -- Trace data bit 2. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 18 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller A2 200 [2] Type PIO0_30 Description Reset state [1] 208-pin, LQFP Pin description ...continued Symbol 180-pin, TFBGA Table 4. PU I/O PIO0_30 -- General-purpose digital input/output pin. Remark: In ISP mode, this pin is set to the Flexcomm 0 USART TXD function. I/O FC0_TXD_SCL_MISO -- Flexcomm 0: USART transmitter, I2C clock, SPI master-in/slave-out data. R -- Reserved. PIO0_31/ ADC0_5 PIO1_0/ ADC0_6 M5 N3 55 56 [4] [4] O CT0_MAT0 -- Match output 0 from Timer 0. O SCT0_OUT9 -- SCTimer/PWM output 9. O TRACEDATA[1] -- Trace data bit 1. PU I/O; PIO0_31/ADC0_5 -- General-purpose digital input/output pin. ADC input AI channel 5 if the DIGIMODE bit is set to 0 in the IOCON register for this pin. I/O FC0_CTS_SDA_SSEL0 -- Flexcomm 0: USART clear-to-send, I2C data I/O, SPI Slave Select 0. I/O SD_D[2] -- SD/MMC data 2. O CT0_MAT1 -- Match output 1 from Timer 0. O SCT0_OUT3 -- SCTimer/PWM output 3. O TRACEDATA[0] -- Trace data bit 0. PU I/O; PIO1_0/ADC0_6 -- General-purpose digital input/output pin. ADC input AI channel 6 if the DIGIMODE bit is set to 0 in the IOCON register for this pin. I/O FC0_RTS_SCL_SSEL1 -- Flexcomm 0: USART request-to-send, I2C clock, SPI slave select 1. I/O SD_D[3] -- SD/MMC data 3. I CT0_CAP2 -- Capture 2 input to Timer 0. I SCT0_GPI4 -- Pin input 4 to SCTimer/PWM. O PIO1_1 K12 109 [2] PU I/O I/O TRACECLK -- Trace clock. PIO1_1/ -- General-purpose digital input/output pin. FC3_RXD_SDA_MOSI -- Flexcomm 3: USART receiver, I2C data I/O, SPI master-out/slave-in data. R -- Reserved. I CT0_CAP3 -- Capture 3 input to Timer 0. I SCT0_GPI5 -- Pin input 5 to SCTimer/PWM. R -- Reserved. R -- Reserved. I LPC546xx Product data sheet USB1_OVERCURRENTN -- USB1 bus overcurrent indicator (active low). All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 19 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Pin description ...continued L14 117 Reset state [1] [2] Type PIO1_2 Description 208-pin, LQFP Symbol 180-pin, TFBGA Table 4. PU I/O O PIO1_2 -- General-purpose digital input/output pin. CAN0_TD -- Transmitter output for CAN0. R -- Reserved. O CT0_MAT3 -- Match output 3 from Timer0. I SCT0_GPI6 -- Pin input 6 to SCTimer/PWM. O PDM1_CLK -- Clock for PDM interface 1, for digital microphone. R -- Reserved. O PIO1_3 J13 120 [2] PU I/O I USB1_PORTPWRN -- USB1 VBUS drive indicator (Indicates VBUS must be driven). PIO1_3 -- General-purpose digital input/output pin. CAN0_RD -- Receiver input for CAN0. R -- Reserved. R -- Reserved. PIO1_4 PIO1_5 D4 E4 3 5 [2] [2] O SCT0_OUT4 -- SCTimer/PWM output 4. I PDM1_DATA -- Data for PDM interface 1 (digital microphone). O USB0_PORTPWRN -- USB0 VBUS drive indicator (Indicates VBUS must be driven). PU I/O PIO1_4 -- General-purpose digital input/output pin. I/O FC0_SCK -- Flexcomm 0: USART or SPI clock. I/O SD_D[0] -- SD/MMC data 0. O CT2_MAT1 -- Match output 1 from Timer 2. O SCT0_OUT0 -- SCTimer/PWM output 0. I FREQME_GPIO_CLK_A -- Frequency Measure pin clock input A. I/O EMC_D[11]) -- External Memory interface data [11]. PU I/O PIO1_5 -- General-purpose digital input/output pin. I/O FC0_RXD_SDA_MOSI -- Flexcomm 0: USART receiver, I2C data I/O, SPI master-out/slave-in data. I/O SD_D[2] -- SD/MMC data 2. O CT2_MAT0 -- Match output 0 from Timer 2. I SCT0_GPI0 -- Pin input 0 to SCTimer/PWM. R -- Reserved. O LPC546xx Product data sheet EMC_A[4] -- External memory interface address 4. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 20 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller G4 30 [2] Type PIO1_6 Description Reset state [1] 208-pin, LQFP Pin description ...continued Symbol 180-pin, TFBGA Table 4. PU I/O PIO1_6 -- General-purpose digital input/output pin. I/O FC0_TXD_SCL_MISO -- Flexcomm 0: USART transmitter, I2C clock, SPI master-in/slave-out data. I/O SD_D[3] -- SD/MMC data 3. O CT2_MAT1 -- Match output 1 from Timer 2. I SCT0_GPI3 -- Pin input 3 to SCTimer/PWM. R -- Reserved. O PIO1_7 N1 38 [2] PU I/O EMC_A[5] -- External memory interface address 5. PIO1_7 -- General-purpose digital input/output pin. I/O FC0_RTS_SCL_SSEL1 -- Flexcomm 0: USART request-to-send, I2C clock, SPI slave select 1. I/O SD_D[1] -- SD/MMC data 1. O CT2_MAT2 -- Match output 2 from Timer 2. I SCT0_GPI4 -- Pin input 4 to SCTimer/PWM. R -- Reserved. O PIO1_8 P8 72 [2] PU I/O EMC_A[6] -- External memory interface address 6. PIO1_8 -- General-purpose digital input/output pin. I/O FC0_CTS_SDA_SSEL0 -- Flexcomm 0: USART clear-to-send, I2C data I/O, SPI Slave Select 0. O SD_CLK -- SD/MMC clock. R -- Reserved. PIO1_9 LPC546xx Product data sheet K6 78 [2] O SCT0_OUT1 -- SCTimer/PWM output 1. I/O FC4_SSEL2 -- Flexcomm 4: SPI slave select 2. O EMC_A[7] -- External memory interface address 7. PU I/O PIO1_9 -- General-purpose digital input/output pin. O ENET_TXD0 -- Ethernet transmit data 0. I/O FC1_SCK -- Flexcomm 1: USART or SPI clock. I CT1_CAP0 -- Capture 0 input to Timer 1. O SCT0_OUT2 -- SCTimer/PWM output 2. I/O FC4_CTS_SDA_SSEL0 -- Flexcomm 4: USART clear-to-send, I2C data I/O, SPI Slave Select 0. O EMC_CASN -- External memory interface column access strobe (active low). All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 21 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller N9 84 [2] Type PIO1_10 Description Reset state [1] 208-pin, LQFP Pin description ...continued Symbol 180-pin, TFBGA Table 4. PU I/O PIO1_10 -- General-purpose digital input/output pin. O ENET_TXD1 -- Ethernet transmit data 1. I/O FC1_RXD_SDA_MOSI -- Flexcomm 1: USART receiver, I2C data I/O, SPI master-out/slave-in data. O CT1_MAT0 -- Match output 0 from Timer 1. O SCT0_OUT3 -- SCTimer/PWM output 3. R -- Reserved. O PIO1_11 B4 198 [2] PU I/O EMC_RASN -- External memory interface row address strobe (active low). PIO1_11 -- General-purpose digital input/output pin. O ENET_TX_EN -- Ethernet transmit enable (RMII/MII interface). I/O FC1_TXD_SCL_MISO -- Flexcomm 1: USART transmitter, I2C clock, SPI master-in/slave-out data. I CT1_CAP1 -- Capture 1 input to Timer 1. I USB0_VBUS -- Monitors the presence of USB0 bus power. R -- Reserved. O PIO1_12 PIO1_13 LPC546xx Product data sheet K9 128 G10 139 [2] [2] PU I/O EMC_CLK[0] -- External memory interface clock 0. PIO1_12 -- General-purpose digital input/output pin. I ENET_RXD0 -- Ethernet receive data 0. I/O FC6_SCK -- Flexcomm 6: USART, SPI, or I2S clock. O CT1_MAT1 -- Match output 1 from Timer 1. O USB0_PORTPWRN -- USB0 VBUS drive indicator (Indicates VBUS must be driven). O EMC_DYCSN[0] -- External Memory interface SDRAM chip select 0 (active low). PU I/O PIO1_13 -- General-purpose digital input/output pin. I ENET_RXD1 -- Ethernet receive data 1. I/O FC6_RXD_SDA_MOSI_DATA -- Flexcomm 6: USART receiver, I2C data I/O, SPI master-out/slave-in data, I2S data I/O. I CT1_CAP2 -- Capture 2 input to Timer 1. I USB0_OVERCURRENTN -- USB0 bus overcurrent indicator (active low). O USB0_FRAME -- USB0 frame toggle signal. O EMC_DQM[0] -- External memory interface data mask 0. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 22 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Pin description ...continued C12 160 PIO1_15 PIO1_16 A11 176 B7 187 Reset state [1] [2] [2] [2] Type PIO1_14 Description 208-pin, LQFP Symbol 180-pin, TFBGA Table 4. PU I/O PIO1_14 -- General-purpose digital input/output pin. I ENET_RX_DV -- Ethernet receive data valid. I UTICK_CAP2 -- Micro-tick timer capture input 2. O CT1_MAT2 -- Match output 2 from Timer 1. I/O FC5_CTS_SDA_SSEL0 -- Flexcomm 5: USART clear-to-send, I2C data I/O, SPI Slave Select 0. O USB0_LEDN -- USB0-configured LED indicator (active low). O EMC_DQM[1] -- External memory interface data mask 0. PU I/O PIO1_15 -- General-purpose digital input/output pin. I ENET_RX_CLK -- Ethernet Receive Clock (MII interface) or Ethernet Reference Clock (RMII interface). I UTICK_CAP3 -- Micro-tick timer capture input 3. I CT1_CAP3 -- Capture 3 input to Timer 1. I/O FC5_RTS_SCL_SSEL1 -- Flexcomm 5: USART request-to-send, I2C clock, SPI slave select 1. I/O FC4_RTS_SCL_SSEL1 -- Flexcomm 4: USART request-to-send, I2C clock, SPI slave select 1. O EMC_CKE[0] -- External memory interface SDRAM clock enable 0. PU I/O PIO1_16 -- General-purpose digital input/output pin. O ENET_MDC -- Ethernet management data clock. I/O FC6_TXD_SCL_MISO_WS -- Flexcomm 6: USART transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S word-select/frame. O CT1_MAT3 -- Match output 3 from Timer 1. I/O SD_CMD -- SD/MMC card command I/O. R -- Reserved. O PIO1_17 N12 98 [2] PU I/O EMC_A[10] -- External memory interface address 10. PIO1_17 -- General-purpose digital input/output pin. I/O ENET_MDIO -- Ethernet management data I/O. I/O FC8_RXD_SDA_MOSI -- Flexcomm 8: USART receiver, I2C data I/O, SPI master-out/slave-in data. R -- Reserved. LPC546xx Product data sheet O SCT0_OUT4 -- SCTimer/PWM output 4. O CAN1_TD -- Transmitter output for CAN 1. O EMC_BLSN[0] -- External memory interface byte lane select 0 (active low). All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 23 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller D1 15 [2] Type PIO1_18 Description Reset state [1] 208-pin, LQFP Pin description ...continued Symbol 180-pin, TFBGA Table 4. PU I/O PIO1_18 -- General-purpose digital input/output pin. R -- Reserved. I/O FC8_TXD_SCL_MISO -- Flexcomm 8: USART transmitter, I2C clock, SPI master-in/slave-out data. R -- Reserved. PIO1_19 PIO1_20 L1 M1 33 35 [2] [2] O SCT0_OUT5 -- SCTimer/PWM output 5. I CAN1_RD -- Receiver input for CAN 1. O EMC_BLSN[1] -- External memory interface byte lane select 1 (active low). PU I/O PIO1_19 -- General-purpose digital input/output pin. I/O FC8_SCK -- Flexcomm 8: USART or SPI clock. O SCT0_OUT7 -- SCTimer/PWM output 7. O CT3_MAT1 -- Match output 1 from Timer 3. I SCT0_GPI7 -- Pin input 7 to SCTimer/PWM. I/O FC4_SCK -- Flexcomm 4: USART or SPI clock. I/O EMC_D[8] -- External Memory interface data [8]. PU I/O I/O PIO1_20 -- General-purpose digital input/output pin. FC7_RTS_SCL_SSEL1 -- Flexcomm 7: USART request-to-send, I2C clock, SPI slave select 1. R -- Reserved. I CT3_CAP2 -- Capture 2 input to Timer 3. R -- Reserved. PIO1_21 N8 74 [2] I/O FC4_TXD_SCL_MISO -- Flexcomm 4: USART transmitter, I2C clock, SPI master-in/slave-out data. I/O EMC_D[9] -- External Memory interface data [9]. PU I/O I/O PIO1_21 -- General-purpose digital input/output pin. FC7_CTS_SDA_SSEL0 -- Flexcomm 7: USART clear-to-send, I2C data I/O, SPI Slave Select 0. R -- Reserved. O CT3_MAT2 -- Match output 2 from Timer 3. R -- Reserved. LPC546xx Product data sheet I/O FC4_RXD_SDA_MOSI -- Flexcomm 4: USART receiver, I2C data I/O, SPI master-out/slave-in data. I/O EMC_D[10] -- External Memory interface data [10]. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 24 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Pin description ...continued P11 89 PIO1_23 M1 0 97 Reset state [1] [2] [2] Type PIO1_22 Description 208-pin, LQFP Symbol 180-pin, TFBGA Table 4. PU I/O PIO1_22 -- General-purpose digital input/output pin. I/O FC8_RTS_SCL_SSEL1 -- Flexcomm 8: USART request-to-send, I2C clock, SPI slave select 1. I/O SD_CMD -- SD/MMC card command I/O. O CT2_MAT3 -- Match output 3 from Timer 2. I SCT0_GPI5 -- Pin input 5 to SCTimer/PWM. I/O FC4_SSEL3 -- Flexcomm 4: SPI slave select 3. O EMC_CKE[1] -- External memory interface SDRAM clock enable 1. PU I/O PIO1_23 -- General-purpose digital input/output pin. I/O FC2_SCK -- Flexcomm 2: USART or SPI clock. O SCT0_OUT0 -- SCTimer/PWM output 0. R -- Reserved. PIO1_24 N14 111 [2] I/O ENET_MDIO -- Ethernet management data I/O. I/O FC3_SSEL2 -- Flexcomm 3: SPI slave select 2. O EMC_A[11] -- External memory interface address 11. PU I/O PIO1_24 -- General-purpose digital input/output pin. I/O FC2_RXD_SDA_MOSI -- Flexcomm 2: USART receiver, I2C data I/O, SPI master-out/slave-in data. O SCT0_OUT1 -- SCTimer/PWM output 1. R -- Reserved. R -- Reserved. PIO1_25 M1 2 119 [2] I/O FC3_SSEL3 -- Flexcomm 3: SPI slave select 3. O EMC_A[12] -- External memory interface address 12. PU I/O PIO1_25 -- General-purpose digital input/output pin. I/O FC2_TXD_SCL_MISO -- Flexcomm 2: USART transmitter, I2C clock, SPI master-in/slave-out data. O SCT0_OUT2 -- SCTimer/PWM output 2. R -- Reserved. I UTICK_CAP0 -- Micro-tick timer capture input 0. R -- Reserved. O LPC546xx Product data sheet EMC_A[13] -- External memory interface address 13. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 25 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Pin description ...continued J10 131 Reset state [1] [2] Type PIO1_26 Description 208-pin, LQFP Symbol 180-pin, TFBGA Table 4. PU I/O PIO1_26 -- General-purpose digital input/output pin. I/O FC2_CTS_SDA_SSEL0 -- Flexcomm 2: USART clear-to-send, I2C data I/O, SPI Slave Select 0. O SCT0_OUT3 -- SCTimer/PWM output 3. I CT0_CAP3 -- Capture 3 input to Timer 0. I UTICK_CAP1 -- Micro-tick timer capture input 1. R -- Reserved. O PIO1_27 F10 142 [2] PU I/O EMC_A[8] -- External memory interface address 8. PIO1_27 -- General-purpose digital input/output pin. I/O FC2_RTS_SCL_SSEL1 -- Flexcomm 2: USART request-to-send, I2C clock, SPI slave select 1. I/O SD_D[4] -- SD/MMC data 4. O CT0_MAT3 -- Match output 3 from Timer 0. O CLKOUT -- Output of the CLKOUT function. R -- Reserved. O PIO1_28 E12 151 [2] PU I/O EMC_A[9] -- External memory interface address 9. PIO1_28 -- General-purpose digital input/output pin. I/O FC7_SCK -- Flexcomm 7: USART, SPI, or I2S clock. I/O SD_D[5] -- SD/MMC data 5. I CT0_CAP2 -- Capture 2 input to Timer 0. R -- Reserved. R -- Reserved. I/O PIO1_29 LPC546xx Product data sheet C11 165 [2] PU I/O EMC_D[12] -- External Memory interface data [12]. PIO1_29 -- General-purpose digital input/output pin. I/O FC7_RXD_SDA_MOSI_DATA -- Flexcomm 7: USART receiver, I2C data I/O, SPI master-out/slave-in data, I2S data I/O. I/O SD_D[6] -- SD/MMC data 6. I SCT0_GPI6 -- Pin input 6 to SCTimer/PWM. O USB1_PORTPWRN -- USB1 VBUS drive indicator (Indicates VBUS must be driven). O USB1_FRAME -- USB1 frame toggle signal. I/O EMC_D[13] -- External Memory interface data [13]. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 26 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller A8 182 PIO1_31 C5 195 [2] [2] Type PIO1_30 Description Reset state [1] 208-pin, LQFP Pin description ...continued Symbol 180-pin, TFBGA Table 4. PU I/O PIO1_30 -- General-purpose digital input/output pin. I/O FC7_TXD_SCL_MISO_WS -- Flexcomm 7: USART transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S word-select/frame. I/O SD_D[7] -- SD/MMC data 7. I SCT0_GPI7 -- Pin input 7 to SCTimer/PWM. I USB1_OVERCURRENTN -- USB1 bus overcurrent indicator (active low). O USB1_LEDN -- USB1-configured LED indicator (active low). I/O EMC_D[14] -- External Memory interface data [14]. PU I/O I/O PIO1_31 -- General-purpose digital input/output pin. MCLK -- MCLK input or output for I2S and/or digital microphone. R -- Reserved. PIO2_0/ ADC0_7 P3 57 [4] O CT0_MAT2 -- Match output 2 from Timer 0. O SCT0_OUT6 -- SCTimer/PWM output 6. I/O FC8_CTS_SDA_SSEL0 -- Flexcomm 8: USART clear-to-send, I2C data I/O, SPI Slave Select 0. I/O EMC_D[15] -- External Memory interface data [15]. PU I/O; PIO2_0/ADC0_7 -- General-purpose digital input/output pin. ADC input AI channel 7 if the DIGIMODE bit is set to 0 in the IOCON register for this pin. R -- Reserved. I/O FC0_RXD_SDA_MOSI -- Flexcomm 0: USART receiver, I2C data I/O, SPI master-out/slave-in data. R -- Reserved. O PIO2_1/ ADC0_8 P4 58 [4] CT1_CAP0 -- Capture input 0 to Timer 1. PU I/O; PIO2_1/ADC0_8 -- General-purpose digital input/output pin. ADC input AI channel 8 if the DIGIMODE bit is set to 0 in the IOCON register for this pin. R -- Reserved. I/O FC0_TXD_SCL_MISO -- Flexcomm 0: USART transmitter, I2C clock, SPI master-in/slave-out data. R -- Reserved. O PIO2_2 LPC546xx Product data sheet C3 4 [2] PU I/O CT1_MAT0 -- Match output 0 from Timer 1. PIO2_2 -- General-purpose digital input/output pin. I ENET_CRS -- Ethernet Carrier Sense (MII interface) or Ethernet Carrier Sense/Data Valid (RMII interface). I/O FC3_SSEL3 -- Flexcomm 3: SPI slave select 3. O SCT0_OUT6 -- SCTimer/PWM output 6. O CT1_MAT1 -- Match output 1 from Timer 1. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 27 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller B1 7 PIO2_4 PIO2_5 PIO2_6 PIO2_7 PIO2_8 D3 C1 F3 J2 F4 9 12 17 29 32 [2] [2] [2] [2] [2] [2] Type PIO2_3 Description Reset state [1] 208-pin, LQFP Pin description ...continued Symbol 180-pin, TFBGA Table 4. PU I/O PIO2_3 -- General-purpose digital input/output pin. O ENET_TXD2 -- Ethernet transmit data 2 (MII interface). O SD_CLK -- SD/MMC clock. I/O FC1_RXD_SDA_MOSI -- Flexcomm 1: USART receiver, I2C data I/O, SPI master-out/slave-in data. O CT2_MAT0 -- Match output 0 from Timer 2. PU I/O PIO2_4 -- General-purpose digital input/output pin. O ENET_TXD3 -- Ethernet transmit data 3 (MII interface). I/O SD_CMD -- SD/MMC card command I/O. I/O FC1_TXD_SCL_MISO -- Flexcomm 1: USART transmitter, I2C clock, SPI master-in/slave-out data. O CT2_MAT1 -- Match output 1 from Timer 2. PU I/O PIO2_5 -- General-purpose digital input/output pin. O ENET_TX_ER -- Ethernet Transmit Error (MII interface). O SD_POW_EN -- SD/MMC card power enable I/O FC1_CTS_SDA_SSEL0 -- Flexcomm 1: USART clear-to-send, I2C data I/O, SPI Slave Select 0. O CT1_MAT2 -- Match output 2 from Timer 1. PU I/O PIO2_6 -- General-purpose digital input/output pin. I ENET_TX_CLK -- Ethernet Transmit Clock (MII interface). I/O SD_D[0] -- SD/MMC data 0. I/O FC1_RTS_SCL_SSEL1 -- Flexcomm 1: USART request-to-send, I2C clock, SPI slave select 1. I CT0_CAP0 -- Capture input 0 to Timer 0. PU I/O PIO2_7 -- General-purpose digital input/output pin. I ENET_COL -- Ethernet Collision detect (MII interface). I/O SD_D(1) -- SD/MMC data 1. I FREQME_GPIO_CLK_B -- Frequency Measure pin clock input B. I CT0_CAP1 -- Capture input 1 to Timer 0. PU I/O PIO2_8 -- General-purpose digital input/output pin. I ENET_RXD2 -- Ethernet Receive Data 2 (MII interface). I/O SD_D[2] -- SD/MMC data 2. R -- Reserved. O LPC546xx Product data sheet CT0_MAT0 -- Match output 0 from Timer 0. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 28 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller K2 36 [2] Type PIO2_9 Description Reset state [1] 208-pin, LQFP Pin description ...continued Symbol 180-pin, TFBGA Table 4. PU I/O PIO2_9 -- General-purpose digital input/output pin. I ENET_RXD3 -- Ethernet Receive Data 3 (MII interface). I/O SD_D[3] -- SD/MMC data 3. R -- Reserved. O PIO2_10 PIO2_11 P1 K3 39 43 [2] [2] PU I/O CT0_MAT1 -- Match output 0 from Timer 1. PIO2_10 -- General-purpose digital input/output pin. I ENET_RX_ER -- Ethernet receive error (RMII/MII interface). I SD_CARD_DET_N -- SD/MMC card detect (active low). PU I/O PIO2_11 -- General-purpose digital input/output pin. O LCD_PWR -- LCD panel power enable. O SD_VOLT[0] -- SD/MMC card regulator voltage control [0]. R -- Reserved. I/O PIO2_12 M2 45 [2] PU I/O FC5_SCK -- Flexcomm 5: USART or SPI clock. PIO2_12 -- General-purpose digital input/output pin. O LCD_LE -- LCD line end signal. O SD_VOLT[1] -- SD/MMC card regulator voltage control [1]. I USB0_IDVALUE -- Indicates to the transceiver whether connected as an A-device (USB0_ID LOW) or B-device (USB0_ID HIGH). R -- Reserved. I/O PIO2_13 P7 70 [2] PU I/O FC5_RXD_SDA_MOSI -- Flexcomm 5: USART receiver, I2C data I/O, SPI master-out/slave-in data. PIO2_13 -- General-purpose digital input/output pin. O LCD_DCLK -- LCD panel clock. O SD_VOLT[2] -- SD/MMC card regulator voltage control [2]. R -- Reserved. I/O PIO2_14 LPC546xx Product data sheet L7 77 [2] PU I/O FC5_TXD_SCL_MISO -- Flexcomm 5: USART transmitter, I2C clock, SPI master-in/slave-out data. PIO2_14 -- General-purpose digital input/output pin. O LCD_FP -- LCD frame pulse (STN). Vertical synchronization pulse (TFT). O USB0_FRAME -- USB0 frame toggle signal. O USB0_PORTPWRN -- USB0 VBUS drive indicator (Indicates VBUS must be driven). O CT0_MAT2 -- Match output 2 from Timer 0. I/O FC5_CTS_SDA_SSEL0 -- Flexcomm 5: USART clear-to-send, I2C data I/O, SPI Slave Select 0. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 29 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller M8 79 PIO2_16 PIO2_17 PIO2_18 PIO2_19 LPC546xx Product data sheet L8 81 P10 86 N10 90 P12 93 [2] [2] [2] [2] [2] Type PIO2_15 Description Reset state [1] 208-pin, LQFP Pin description ...continued Symbol 180-pin, TFBGA Table 4. PU I/O PIO2_15 -- General-purpose digital input/output pin. O LCD_AC -- LCD STN AC bias drive or TFT data enable output. O USB0_LEDN -- USB0-configured LED indicator (active low). I USB0_OVERCURRENTN -- USB0 bus overcurrent indicator (active low). O CT0_MAT3 -- Match output 3 from Timer 0. I/O FC5_RTS_SCL_SSEL1 -- Flexcomm 5: USART request-to-send, I2C clock, SPI slave select 1. PU I/O PIO2_16 -- General-purpose digital input/output pin. O LCD_LP -- LCD line synchronization pulse (STN). Horizontal synchronization pulse (TFT). O USB1_FRAME -- USB1 frame toggle signal. O USB1_PORTPWRN -- USB1 VBUS drive indicator (Indicates VBUS must be driven). O CT1_MAT3 -- Match output 3 from Timer 1. I/O FC8_SCK -- Flexcomm 8: USART or SPI clock. PU I/O PIO2_17 -- General-purpose digital input/output pin. I LCD_CLKIN -- LCD clock input. O USB1_LEDN -- USB1-configured LED indicator (active low). I USB1_OVERCURRENTN -- USB1 bus overcurrent indicator (active low). I CT1_CAP1 -- Capture 1 input to Timer 1. I/O FC8_RXD_SDA_MOSI -- Flexcomm 8: USART receiver, I2C data I/O, SPI master-out/slave-in data. PU I/O PIO2_18 -- General-purpose digital input/output pin. O LCD_VD[0] -- LCD Data [0]. I/O FC3_RXD_SDA_MOSI -- Flexcomm 3: USART receiver, I2C data I/O, SPI master-out/slave-in data. I/O FC7_SCK -- Flexcomm 7: USART, SPI, or I2S clock. O CT3_MAT0 -- Match output 0 from Timer 3. PU I/O PIO2_19 -- General-purpose digital input/output pin. O LCD_VD[1] -- LCD Data [1]. I/O FC3_TXD_SCL_MISO -- Flexcomm 3: USART transmitter, I2C clock, SPI master-in/slave-out data. I/O FC7_RXD_SDA_MOSI_DATA -- Flexcomm 7: USART receiver, I2C data I/O, SPI master-out/slave-in data, I2S data I/O. O CT3_MAT1 -- Match output 1 from Timer 3. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 30 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Pin description ...continued P13 95 PIO2_21 PIO2_22 L10 99 K10 113 Reset state [1] [2] [2] [2] Type PIO2_20 Description 208-pin, LQFP Symbol 180-pin, TFBGA Table 4. PU I/O PIO2_20 -- General-purpose digital input/output pin. O LCD_VD[2] -- LCD Data [2]. I/O FC3_RTS_SCL_SSEL1 -- Flexcomm 3: USART request-to-send, I2C clock, SPI slave select 1. I/O FC7_TXD_SCL_MISO_WS -- Flexcomm 7: USART transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S word-select/frame. O CT3_MAT2 -- Match output 2 from Timer 3. I CT4_CAP0 -- Capture input 4 to Timer 0. PU I/O PIO2_21 -- General-purpose digital input/output pin. O LCD_VD[3] -- LCD Data [3]. I/O FC3_CTS_SDA_SSEL0 -- Flexcomm 3: USART clear-to-send, I2C data I/O, SPI Slave Select 0. I/O MCLK -- MCLK input or output for I2S and/or digital microphone. O CT3_MAT3 -- Match output 3 from Timer 3. PU I/O PIO2_22 -- General-purpose digital input/output pin. O LCD_VD[4] -- LCD Data [4]. O SCT0_OUT7 -- SCTimer/PWM output 7. R -- Reserved. I PIO2_23 PIO2_24 PIO2_25 PIO2_26 M1 4 115 K14 118 J11 121 H11 124 [2] [2] [2] [2] PU I/O CT2_CAP0 -- Capture input 0 to Timer 2. PIO2_23 -- General-purpose digital input/output pin. O LCD_VD[5] -- LCD Data [5]. O SCT0_OUT8 -- SCTimer/PWM output 8. PU I/O PIO2_24 -- General-purpose digital input/output pin. O LCD_VD[6] -- LCD Data [6]. O SCT0_OUT9 -- SCTimer/PWM output 9. PU I/O PIO2_25 -- General-purpose digital input/output pin. O LCD_VD[7] -- LCD Data [7]. I USB0_VBUS -- Monitors the presence of USB0 bus power. PU I/O O PIO2_26 -- General-purpose digital input/output pin. LCD_VD[8] -- LCD Data [8]. R -- Reserved. PIO2_27 LPC546xx Product data sheet H14 130 [2] I/O FC3_SCK -- Flexcomm 3: USART or SPI clock. I CT2_CAP1 -- Capture input 1 to Timer 2. PU I/O PIO2_27 -- General-purpose digital input/output pin. O LCD_VD[9] -- LCD Data [9]. I/O FC9_SCK -- Flexcomm 9: USART or SPI clock. I/O FC3_SSEL2 -- Flexcomm 3: SPI slave select 2. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 31 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Pin description ...continued G13 134 Reset state [1] [2] Type PIO2_28 Description 208-pin, LQFP Symbol 180-pin, TFBGA Table 4. PU I/O PIO2_28 -- General-purpose digital input/output pin. O LCD_VD[10]) -- LCD Data [10]. I/O FC7_CTS_SDA_SSEL0 -- Flexcomm 7: USART clear-to-send, I2C data I/O, SPI Slave Select 0. R -- Reserved I PIO2_29 PIO2_30 G11 137 F12 143 [2] [2] PU I/O CT2_CAP2 -- Capture input 2 to Timer 2. PIO2_29 -- General-purpose digital input/output pin. O LCD_VD[11] -- LCD Data [11]. I/O FC7_RTS_SCL_SSEL1 -- Flexcomm 7: USART request-to-send, I2C clock, SPI slave select 1. I/O FC8_TXD_SCL_MISO -- Flexcomm 8: USART transmitter, I2C clock, SPI master-in/slave-out data. I CT2_CAP3 -- Capture 3 input to Timer 2. O CLKOUT -- Output of the CLKOUT function. PU I/O O PIO2_30 -- General-purpose digital input/output pin. LCD_VD[12] -- LCD Data [12]. R -- Reserved. R -- Reserved. O PIO2_31 D14 149 [2] D12 155 [2] PU I/O O PIO3_0 PU I/O CT2_MAT2 -- Match output 2 from Timer 2. PIO2_31 -- General-purpose digital input/output pin. LCD_VD[13] -- LCD Data [13]. PIO3_0 -- General-purpose digital input/output pin. O LCD_VD[14] -- LCD Data [14]. O PDM0_CLK -- Clock for PDM interface 0, for digital microphone. R -- Reserved. O PIO3_1 D11 159 [2] PU I/O CT1_MAT0 -- Match output 0 from Timer 1. PIO3_1 -- General-purpose digital input/output pin. O LCD_VD[15] -- LCD Data [15]. I PDM0_DATA -- Data for PDM interface 0 (digital microphone). R -- Reserved. O PIO3_2 C10 164 [2] PU I/O CT1_MAT1 -- Match output 1 from Timer 1. PIO3_2 -- General-purpose digital input/output pin. O LCD_VD[16] -- LCD Data [16]. I/O FC9_RXD_SDA_MOSI -- Flexcomm 9: USART receiver, I2C data I/O, SPI master-out/slave-in data. R -- Reserved. O LPC546xx Product data sheet CT1_MAT2 -- Match output 2 from Timer 1. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 32 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Pin description ...continued A13 169 PIO3_4 B11 172 Reset state [1] [2] [2] Type PIO3_3 Description 208-pin, LQFP Symbol 180-pin, TFBGA Table 4. PU I/O PIO3_3 -- General-purpose digital input/output pin. O LCD_VD[17] -- LCD Data [17]. I/O FC9_TXD_SCL_MISO -- Flexcomm 9: USART transmitter, I2C clock, SPI master-in/slave-out data. PU I/O O PIO3_4 -- General-purpose digital input/output pin. LCD_VD[18] -- LCD Data [18]. R -- Reserved. PIO3_5 B10 177 [2] I/O FC8_CTS_SDA_SSEL0 -- Flexcomm 8: USART clear-to-send, I2C data I/O, SPI Slave Select 0. I CT4_CAP1 -- Capture input 4 to Timer 1. PU I/O O PIO3_5 -- General-purpose digital input/output pin. LCD_VD[19] -- LCD Data [19]. R -- Reserved. PIO3_6 C9 180 [2] I/O FC8_RTS_SCL_SSEL1 -- Flexcomm 8: USART request-to-send, I2C clock, SPI slave select 1. O CT4_MAT1 -- Match output 1 from Timer 4. PU I/O PIO3_6 -- General-purpose digital input/output pin. O LCD_VD[20] -- LCD Data [20]. O LCD_VD[0] -- LCD Data [0]. R -- Reserved. O PIO3_7 B8 184 [2] PU I/O CT4_MAT2 -- Match output 2 from Timer 4. PIO3_7 -- General-purpose digital input/output pin. O LCD_VD[21] -- LCD Data [21]. O LCD_VD[1] -- LCD Data [1]. R -- Reserved. I PIO3_8 A7 186 [2] PU I/O CT4_CAP2 -- Capture input 2 to Timer 4. PIO3_8 -- General-purpose digital input/output pin. O LCD_VD[22] -- LCD Data [22]. O LCD_VD[2] -- LCD Data [2]. R -- Reserved. I PIO3_9 C7 192 [2] PU I/O CT4_CAP3 -- Capture input 3 to Timer 4. PIO3_9 -- General-purpose digital input/output pin. O LCD_VD[23] -- LCD Data [23]. O LCD_VD[3] -- LCD Data [3]. R -- Reserved. I LPC546xx Product data sheet CT0_CAP2 -- Capture input 2 to Timer 0. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 33 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller A3 199 [2] Type PIO3_10 Description Reset state [1] 208-pin, LQFP Pin description ...continued Symbol 180-pin, TFBGA Table 4. I/O PIO3_10 -- General-purpose digital input/output pin. O SCT0_OUT3 -- SCTimer/PWM output 3. R -- Reserved. O CT3_MAT0 -- Match output 0 from Timer 3. R -- Reserved. R -- Reserved. PIO3_11 B2 208 [2] O EMC_DYCSN[1] -- External Memory interface SDRAM chip select 1(active low). O TRACEDATA[0] -- Trace data bit 0. PU I/O PIO3_11 -- General-purpose digital input/output pin. I/O MCLK -- MCLK input or output for I2S and/or digital microphone. I/O FC0_SCK -- Flexcomm 0: USART or SPI clock. I/O FC1_SCK -- Flexcomm 1: USART or SPI clock. R -- Reserved. R -- Reserved. R -- Reserved. O PIO3_12 L2 37 [2] PU I/O O TRACEDATA[3] -- Trace data bit 3. PIO3_12 -- General-purpose digital input/output pin. SCT0_OUT8 -- SCTimer/PWM output 8. R -- Reserved. I CT3_CAP0 -- Capture input 0 to Timer 3. R -- Reserved. PIO3_13 H4 75 [2] O CLKOUT -- Output of the CLKOUT function. O EMC_CLK[1] -- External memory interface clock 1. O TRACECLK -- Trace clock. PU I/O PIO3_13 -- General-purpose digital input/output pin. O SCT0_OUT9 -- SCTimer/PWM output 9. I/O FC9_CTS_SDA_SSEL0 -- Flexcomm 9: USART clear-to-send, I2C data I/O, SPI Slave Select 0. I CT3_CAP1 -- Capture input 1 to Timer 3. R -- Reserved. R -- Reserved. LPC546xx Product data sheet I EMC_FBCK -- External memory interface feedback clock. O TRACEDATA[1] -- Trace data bit 1. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 34 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller E3 13 [2] Type PIO3_14 Description Reset state [1] 208-pin, LQFP Pin description ...continued Symbol 180-pin, TFBGA Table 4. PU I/O PIO3_14 -- General-purpose digital input/output pin. O SCT0_OUT4 -- SCTimer/PWM output 4. I/O FC9_RTS_SCL_SSEL1 -- Flexcomm 9: USART request-to-send, I2C clock, SPI slave select 1. O CT3_MAT1 -- Match output 1 from Timer 3. R -- Reserved. R -- Reserved. R -- Reserved. O PIO3_15 PIO3_16 PIO3_17 PIO3_18 PIO3_19 LPC546xx Product data sheet D2 E1 K1 M6 J3 11 19 31 68 44 [2] [2] [2] [2] [2] PU I/O TRACEDATA[2] -- Trace data bit 2. PIO3_15 -- General-purpose digital input/output pin. I/O FC8_SCK -- Flexcomm 8: USART or SPI clock. I SD_WR_PRT -- SD/MMC write protect. PU I/O PIO3_16 -- General-purpose digital input/output pin. I/O FC8_RXD_SDA_MOSI -- Flexcomm 8: USART receiver, I2C data I/O, SPI master-out/slave-in data. I/O SD_D[4] -- SD/MMC data 4. PU I/O PIO3_17 -- General-purpose digital input/output pin. I/O FC8_TXD_SCL_MISO -- Flexcomm 8: USART transmitter, I2C clock, SPI master-in/slave-out data. I/O SD_D[5] -- SD/MMC data 5. PU I/O PIO3_18 -- General-purpose digital input/output pin. I/O FC8_CTS_SDA_SSEL0 -- Flexcomm 8: USART clear-to-send, I2C data I/O, SPI Slave Select 0. I/O SD_D[6] -- SD/MMC data 6. O CT4_MAT0 -- Match output 0 from Timer 4. O CAN0_TD -- Transmitter output for CAN 0. O SCT0_OUT5 -- SCTimer/PWM output 5. PU I/O PIO3_19 -- General-purpose digital input/output pin. I/O FC8_RTS_SCL_SSEL1 -- Flexcomm 8: USART request-to-send, I2C clock, SPI slave select 1. I/O SD_D[7] -- SD/MMC data 7. O CT4_MAT1 -- Match output 1 from Timer 4. I CAN0_RD -- Receiver input for CAN 0. O SCT0_OUT6 -- SCTimer/PWM output 6. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 35 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller N2 46 [2] Type PIO3_20 Description Reset state [1] 208-pin, LQFP Pin description ...continued Symbol 180-pin, TFBGA Table 4. PU I/O PIO3_20 -- General-purpose digital input/output pin. I/O FC9_SCK -- Flexcomm 9: USART or SPI clock. I SD_CARD_INT_N -- O CLKOUT -- Output of the CLKOUT function. R -- Reserved. O PIO3_21/ ADC0_9 PIO3_22/ ADC0_10 P5 N5 61 62 [4] [4] I/O FC9_RXD_SDA_MOSI -- Flexcomm 9: USART receiver, I2C data I/O, SPI master-out/slave-in data. O SD_BACKEND_PWR -- SD/MMC back-end power supply for embedded device. O CT4_MAT3 -- Match output 3 from Timer 4. I UTICK_CAP2 -- Micro-tick timer capture input 2. PU I/O; PIO3_22/ADC0_10 -- General-purpose digital input/output pin. ADC input AI channel 10 if the DIGIMODE bit is set to 0 in the IOCON register for this pin. I/O PIO3_23 C2 8 [2] SCT0_OUT7 -- SCTimer/PWM output 7. PU I/O; PIO3_21/ADC0_9 -- General-purpose digital input/output pin. ADC input AI channel 9 if the DIGIMODE bit is set to 0 in the IOCON register for this pin. PU I/O I/O FC9_TXD_SCL_MISO -- Flexcomm 9: USART transmitter, I2C clock, SPI master-in/slave-out data. PIO3_23 -- General-purpose digital input/output pin. FC2_CTS_SDA_SSEL0 -- Flexcomm 2: USART clear-to-send, I2C data I/O, SPI Slave Select 0. R -- Reserved. I PIO3_24 PIO3_25 E2 P9 16 82 [2] [2] PU I/O UTICK_CAP3 -- Micro-tick timer capture input 3. PIO3_24 -- General-purpose digital input/output pin. I/O FC2_RTS_SCL_SSEL1 -- Flexcomm 2: USART request-to-send, I2C clock, SPI slave select 1. I CT4_CAP0 -- Capture input 4 to Timer 0. I USB0_VBUS -- Monitors the presence of USB0 bus power. PU I/O PIO3_25 -- General-purpose digital input/output pin. R -- Reserved. I CT4_CAP2 -- Capture input 2 to Timer 4. I/O FC4_SCK -- Flexcomm 4: USART or SPI clock. R -- Reserved. R -- Reserved. O LPC546xx Product data sheet EMC_A[14] -- External memory interface address 14. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 36 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller K5 88 [2] Type PIO3_26 Description Reset state [1] 208-pin, LQFP Pin description ...continued Symbol 180-pin, TFBGA Table 4. PU I/O PIO3_26 -- General-purpose digital input/output pin. R -- Reserved. O SCT0_OUT0 -- SCTimer/PWM output 0. I/O FC4_RXD_SDA_MOSI -- Flexcomm 4: USART receiver, I2C data I/O, SPI master-out/slave-in data. R -- Reserved. R -- Reserved. O PIO3_27 P14 96 [2] PU I/O EMC_A[15] -- External memory interface address 15. PIO3_27 -- General-purpose digital input/output pin. R -- Reserved. O SCT0_OUT1 -- SCTimer/PWM output 1. I/O FC4_TXD_SCL_MISO -- Flexcomm 4: USART transmitter, I2C clock, SPI master-in/slave-out data. R -- Reserved. R -- Reserved. O PIO3_28 M11 100 [2] PU I/O EMC_A[16] -- External memory interface address 16. PIO3_28 -- General-purpose digital input/output pin. R -- Reserved. O SCT0_OUT2 -- SCTimer/PWM output 2. I/O FC4_CTS_SDA_SSEL0 -- Flexcomm 4: USART clear-to-send, I2C data I/O, SPI Slave Select 0. R -- Reserved. R -- Reserved. O PIO3_29 L13 112 [2] PU I/O EMC_A[17] -- External memory interface address 17. PIO3_29 -- General-purpose digital input/output pin. R -- Reserved. O SCT0_OUT3 -- SCTimer/PWM output 3. I/O FC4_RTS_SCL_SSEL1 -- Flexcomm 4: USART request-to-send, I2C clock, SPI slave select 1. R -- Reserved. R -- Reserved. O LPC546xx Product data sheet EMC_A[18] -- External memory interface address 18. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 37 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Pin description ...continued K13 116 Reset state [1] [2] Type PIO3_30 Description 208-pin, LQFP Symbol 180-pin, TFBGA Table 4. PU I/O PIO3_30 -- General-purpose digital input/output pin. I/O FC9_CTS_SDA_SSEL0 -- Flexcomm 9: USART clear-to-send, I2C data I/O, SPI Slave Select 0. O SCT0_OUT4 -- SCTimer/PWM output 4. I/O FC4_SSEL2 -- Flexcomm 4: SPI slave select 2. R -- Reserved. R -- Reserved. O PIO3_31 J14 123 [2] PU I/O EMC_A[19] -- External memory interface address 19. PIO3_31 -- General-purpose digital input/output pin. I/O FC9_RTS_SCL_SSEL1 -- Flexcomm 9: USART request-to-send, I2C clock, SPI slave select 1. O SCT0_OUT5 -- SCTimer/PWM output 5. O CT4_MAT2 -- Match output 2 from Timer 4. R -- Reserved. PIO4_0 H13 127 [2] I SCT0_GPI0 -- Pin input 0 to SCTimer/PWM. O EMC_A[20] -- External memory interface address 20. PU I/O PIO4_0 -- General-purpose digital input/output pin. R -- Reserved. I/O FC6_CTS_SDA_SSEL0 -- Flexcomm 6: USART clear-to-send, I2C data I/O, SPI Slave Select 0. I CT4_CAP1 -- Capture input 4 to Timer 1. R -- Reserved. PIO4_1 G14 132 [2] I SCT0_GPI1 -- Pin input 1 to SCTimer/PWM. O EMC_CSN[1] -- External memory interface static chip select 1(active low). PU I/O PIO4_1 -- General-purpose digital input/output pin. R -- Reserved. I/O FC6_SCK -- Flexcomm 6: USART, SPI, or I2S clock. R -- Reserved. R -- Reserved. LPC546xx Product data sheet I SCT0_GPI2 -- Pin input 2 to SCTimer/PWM. O EMC_CSN[2] -- External memory interface static chip select 2 (active low). All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 38 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Pin description ...continued F14 138 Reset state [1] [2] Type PIO4_2 Description 208-pin, LQFP Symbol 180-pin, TFBGA Table 4. PU I/O PIO4_2 -- General-purpose digital input/output pin. R -- Reserved. I/O FC6_RXD_SDA_MOSI_DATA -- Flexcomm 6: USART receiver, I2C data I/O, SPI master-out/slave-in data, I2S data I/O. R -- Reserved. R -- Reserved. PIO4_3 F13 140 [2] I SCT0_GPI3 -- Pin input 3 to SCTimer/PWM. O EMC_CSN[3] -- External memory interface static chip select 3 (active low). PU I/O PIO4_3 -- General-purpose digital input/output pin. R -- Reserved. I/O FC6_TXD_SCL_MISO_WS -- Flexcomm 6: USART transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S word-select/frame. I CT0_CAP3 -- Capture 3 input to Timer 0. R -- Reserved. PIO4_4 D9 147 [2] I SCT0_GPI4 -- Pin input 4 to SCTimer/PWM. O EMC_DYCSN[2] -- External Memory interface SDRAM chip select 2 (active low). PU I/O PIO4_4 -- General-purpose digital input/output pin. R -- Reserved. I/O FC4_SSEL3 -- Flexcomm 4: SPI slave select 3. I/O FC0_RTS_SCL_SSEL1 -- Flexcomm 0: USART request-to-send, I2C clock, SPI slave select 1. R -- Reserved. PIO4_5 E10 154 [2] I SCT0_GPI5 -- Pin input 5 to SCTimer/PWM. O EMC_DYCSN[3] -- External Memory interface SDRAM chip select 3 (active low). PU I/O PIO4_5 -- General-purpose digital input/output pin. R -- Reserved. LPC546xx Product data sheet I/O FC9_CTS_SDA_SSEL0 -- Flexcomm 9: USART clear-to-send, I2C data I/O, SPI Slave Select 0. I/O FC0_CTS_SDA_SSEL0 -- Flexcomm 0: USART clear-to-send, I2C data I/O, SPI Slave Select 0. O CT4_MAT3 -- Match output 3 from Timer 4. I SCT0_GPI6 -- Pin input 6 to SCTimer/PWM. O EMC_CKE[2] -- External memory interface SDRAM clock enable 2. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 39 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Pin description ...continued D10 161 Reset state [1] [2] Type PIO4_6 Description 208-pin, LQFP Symbol 180-pin, TFBGA Table 4. PU I/O PIO4_6 -- General-purpose digital input/output pin. R -- Reserved. I/O FC9_RTS_SCL_SSEL1 -- Flexcomm 9: USART request-to-send, I2C clock, SPI slave select 1. R -- Reserved. R -- Reserved. PIO4_7 A14 166 [2] I SCT0_GPI7 -- Pin input 7 to SCTimer/PWM. O EMC_CKE[3] -- External memory interface SDRAM clock enable 3. PU I/O PIO4_7 -- General-purpose digital input/output pin. R -- Reserved. PIO4_8 PIO4_9 PIO4_10 B14 170 A12 173 B9 181 [2] [2] [2] I CT4_CAP3 -- Capture input 3 to Timer 4. O USB0_PORTPWRN -- USB0 VBUS drive indicator (Indicates VBUS must be driven). O USB0_FRAME -- USB0 frame toggle signal. I SCT0_GPI0 -- Pin input 0 to SCTimer/PWM. PU I/O PIO4_8 -- General-purpose digital input/output pin. O ENET_TXD0 -- Ethernet transmit data 0. I/O FC2_SCK -- Flexcomm 2: USART or SPI clock. I USB0_OVERCURRENTN -- USB0 bus overcurrent indicator (active low). O USB0_LEDN -- USB0-configured LED indicator (active low). I SCT0_GPI1 -- Pin input 1 to SCTimer/PWM. PU I/O PIO4_9 -- General-purpose digital input/output pin. O ENET_TXD1 -- Ethernet transmit data 1. I/O FC2_RXD_SDA_MOSI -- Flexcomm 2: USART receiver, I2C data I/O, SPI master-out/slave-in data. O USB1_PORTPWRN -- USB1 VBUS drive indicator (Indicates VBUS must be driven). O USB1_FRAME -- USB1 frame toggle signal. I SCT0_GPI2 -- Pin input 2 to SCTimer/PWM. PU I/O PIO4_10 -- General-purpose digital input/output pin. I ENET_RX_DV -- Ethernet receive data valid. I/O FC2_TXD_SCL_MISO -- Flexcomm 2: USART transmitter, I2C clock, SPI master-in/slave-out data. I USB1_OVERCURRENTN -- USB1 bus overcurrent indicator (active low). O USB1_LEDN -- USB1-configured LED indicator (active low). SCT0_GPI3 -- Pin input 3 to SCTimer/PWM. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 40 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller A9 183 [2] Type PIO4_11 Description Reset state [1] 208-pin, LQFP Pin description ...continued Symbol 180-pin, TFBGA Table 4. PU I/O PIO4_11 -- General-purpose digital input/output pin. I ENET_RXD0 -- Ethernet receive data 0. I/O FC2_CTS_SDA_SSEL0 -- Flexcomm 2: USART clear-to-send, I2C data I/O, SPI Slave Select 0. I USB0_IDVALUE -- Indicates to the transceiver whether connected as an A-device (USB0_ID LOW) or B-device (USB0_ID HIGH). R -- Reserved. I PIO4_12 A6 188 [2] PU I/O SCT0_GPI4 -- Pin input 4 to SCTimer/PWM. PIO4_12 -- General-purpose digital input/output pin. I ENET_RXD1 -- Ethernet receive data 1. I/O FC2_RTS_SCL_SSEL1 -- Flexcomm 2: USART request-to-send, I2C clock, SPI slave select 1. R -- Reserved. I PIO4_13 B6 190 [2] PU I/O SCT0_GPI5 -- Pin input 5 to SCTimer/PWM. PIO4_13 -- General-purpose digital input/output pin. O ENET_TX_EN -- Ethernet transmit enable (RMII/MII interface). O CT4_MAT0 -- Match output 0 from Timer 4. R -- Reserved. I PIO4_14 B5 194 [2] PU I/O SCT0_GPI6 -- Pin input 6 to SCTimer/PWM. PIO4_14 -- General-purpose digital input/output pin. I ENET_RX_CLK -- Ethernet Receive Clock (MII interface) or Ethernet Reference Clock (RMII interface). O CT4_MAT1 -- Match output 1 from Timer 4. I/O FC9_SCK -- Flexcomm 9: USART or SPI clock. R -- Reserved. I PIO4_15 PIO4_16 LPC546xx Product data sheet A4 C4 197 203 [2] [2] PU I/O SCT0_GPI7 -- Pin input 7 to SCTimer/PWM. PIO4_15 -- General-purpose digital input/output pin. O ENET_MDC -- Ethernet management data clock. O CT4_MAT2 -- Match output 2 from Timer 4. I/O FC9_RXD_SDA_MOSI -- Flexcomm 9: USART receiver, I2C data I/O, SPI master-out/slave-in data. PU I/O PIO4_16 -- General-purpose digital input/output pin. I/O ENET_MDIO -- Ethernet management data I/O. O CT4_MAT3 -- Match output 3 from Timer 4. I/O FC9_TXD_SCL_MISO -- Flexcomm 9: USART transmitter, I2C clock, SPI master-in/slave-out data. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 41 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller - 6 [2] Type PIO4_17 Description Reset state [1] 208-pin, LQFP Pin description ...continued Symbol 180-pin, TFBGA Table 4. PU I/O PIO4_17 -- General-purpose digital input/output pin. R -- Reserved. O CAN1_TD -- Transmitter output for CAN 1. I CT1_CAP2 -- Capture 2 input to Timer 1. I UTICK_CAP0 -- Micro-tick timer capture input 0. R -- Reserved. O PIO4_18 - 10 [2] PU I/O EMC_BLSN[2] -- External memory interface byte lane select 2 (active low). PIO4_18 -- General-purpose digital input/output pin. R -- Reserved. I CAN1_RD -- Receiver input for CAN 1. I CT1_CAP3 -- Capture 3 input to Timer 1. I UTICK_CAP1 -- Micro-tick timer capture input 1. R -- Reserved. O PIO4_19 - 14 [2] PU I/O EMC_BLSN[3] -- External memory interface byte lane select 3 (active low). PIO4_19 -- General-purpose digital input/output pin. O ENET_TXD0 -- Ethernet transmit data 0. O SD_CLK -- SD/MMC clock. I/O FC2_SCK -- Flexcomm 2: USART or SPI clock. I CT4_CAP2 -- Capture input 2 to Timer 4. R -- Reserved. O PIO4_20 - 18 [2] PU I/O O EMC_DQM[2] -- External memory interface data mask 2. PIO4_20 -- General-purpose digital input/output pin. ENET_TXD1 -- Ethernet transmit data 1. I/O SD_CMD -- SD/MMC card command I/O. I/O FC2_RXD_SDA_MOSI -- Flexcomm 2: USART receiver, I2C data I/O, SPI master-out/slave-in data. I CT4_CAP3 -- Capture input 3 to Timer 4. R -- Reserved. O LPC546xx Product data sheet EMC_DQM[3] -- External memory interface data mask 3. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 42 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller - 34 [2] Type PIO4_21 Description Reset state [1] 208-pin, LQFP Pin description ...continued Symbol 180-pin, TFBGA Table 4. PU I/O PIO4_21 -- General-purpose digital input/output pin. O ENET_TXD2 -- Ethernet transmit data 2 (MII interface). O SD_POW_EN -- SD/MMC card power enable. I/O FC2_TXD_SCL_MISO -- Flexcomm 2: USART transmitter, I2C clock, SPI master-in/slave-out data. O CT2_MAT3 -- Match output 3 from Timer 2. R -- Reserved. I/O PIO4_22 - 47 [2] PU I/O EMC_D[16] -- External Memory interface data [16]. PIO4_22 -- General-purpose digital input/output pin. O ENET_TXD3 -- Ethernet transmit data 3 (MII interface). I SD_CARD_DET_N -- SD/MMC card detect (active low). I/O FC2_RTS_SCL_SSEL1 -- Flexcomm 2: USART request-to-send, I2C clock, SPI slave select 1. O CT1_MAT3 -- Match output 3 from Timer 1. R -- Reserved. I/O PIO4_23 - 42 [2] PU I/O EMC_D[17] -- External Memory interface data [17]. PIO4_23 -- General-purpose digital input/output pin. I ENET_RXD0 -- Ethernet receive data 0. I SD_WR_PRT -- SD/MMC write protect. I/O FC2_CTS_SDA_SSEL0 -- Flexcomm 2: USART clear-to-send, I2C data I/O, SPI Slave Select 0. R -- Reserved. PIO4_24 - 67 [2] O CT1_MAT0 -- Match output 0 from Timer 1. I/O EMC_D[18] -- External Memory interface data [18]. PU I/O PIO4_24 -- General-purpose digital input/output pin. I ENET_RXD1 -- Ethernet receive data 1. I SD_CARD_INT_N -- Card interrupt line. I/O FC7_RTS_SCL_SSEL1 -- Flexcomm 7: USART request-to-send, I2C clock, SPI slave select 1. R -- Reserved. LPC546xx Product data sheet O CT1_MAT1 -- Match output 1 from Timer 1. I/O EMC_D[19] -- External Memory interface data [19]. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 43 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller - 69 [2] Type PIO4_25 Description Reset state [1] 208-pin, LQFP Pin description ...continued Symbol 180-pin, TFBGA Table 4. PU I/O PIO4_25 -- General-purpose digital input/output pin. I ENET_RXD2 -- Ethernet Receive Data 2 (MII interface). I/O SD_D[0] -- SD/MMC data 0. I/O FC7_CTS_SDA_SSEL0 -- Flexcomm 7: USART clear-to-send, I2C data I/O, SPI Slave Select 0. R -- Reserved. PIO4_26 - 73 [2] O CT1_MAT2 -- Match output 2 from Timer 1. I/O EMC_D[20] -- External Memory interface data [20]. PU I/O PIO4_26 -- General-purpose digital input/output pin. I ENET_RXD3 -- Ethernet Receive Data 3 (MII interface). I/O SD_D[1] -- SD/MMC data 1. R -- Reserved. PIO4_27 - 85 [2] I UTICK_CAP2 -- Micro-tick timer capture input 2. O CT1_MAT3 -- Match output 3 from Timer 1. I/O EMC_D[21] -- External Memory interface data [21]. PU I/O O I/O PIO4_27 -- General-purpose digital input/output pin. ENET_TX_EN -- Ethernet transmit enable (RMII/MII interface). SD_D[2] -- SD/MMC data 2. R -- Reserved. PIO4_28 - 92 [2] I/O FC1_SCK -- Flexcomm 1: USART or SPI clock. I CT1_CAP0 -- Capture input 0 to Timer 1. I/O EMC_D[22] -- External Memory interface data [22]. PU I/O PIO4_28 -- General-purpose digital input/output pin. O ENET_TX_ER -- Ethernet Transmit Error (MII interface). I/O SD_D[3] -- SD/MMC data 3. R -- Reserved. PIO4_29 - 102 [2] I/O FC1_RXD_SDA_MOSI -- Flexcomm 1: USART receiver, I2C data I/O, SPI master-out/slave-in data. I CT1_CAP1 -- Capture 1 input to Timer 1. I/O EMC_D[23] -- External Memory interface data [23]. PU I/O PIO4_29 -- General-purpose digital input/output pin. I ENET_RX_ER -- Ethernet receive error (RMII/MII interface). I/O SD_D[4] -- SD/MMC data 4. R -- Reserved. LPC546xx Product data sheet I/O FC1_TXD_SCL_MISO -- Flexcomm 1: USART transmitter, I2C clock, SPI master-in/slave-out data. I CT1_CAP2 -- Capture 2 input to Timer 1. I/O EMC_D[24] -- External Memory interface data [24]. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 44 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller - 80 PIO4_31 - 114 [2] [2] Type PIO4_30 Description Reset state [1] 208-pin, LQFP Pin description ...continued Symbol 180-pin, TFBGA Table 4. PU I/O PIO4_30 -- General-purpose digital input/output pin. I ENET_TX_CLK -- Ethernet Transmit Clock (MII interface). I/O SD_D[5] -- SD/MMC data 5. O CT3_MAT0 -- Match output 0 from Timer 3. I/O FC1_RTS_SCL_SSEL1 -- Flexcomm 1: USART request-to-send, I2C clock, SPI slave select 1. I CT1_CAP3 -- Capture 3 input to Timer 1. I/O EMC_D[25] -- External Memory interface data [25]. PU I/O PIO4_31 -- General-purpose digital input/output pin. I ENET_RX_CLK -- Ethernet Receive Clock (MII interface) or Ethernet Reference Clock (RMII interface). I/O SD_D[6] -- SD/MMC data 6. O CT3_MAT1 -- Match output 1 from Timer 3. I/O FC4_SCK -- Flexcomm 4: USART or SPI clock. R -- Reserved. PIO5_0 - 122 [2] I/O EMC_D[26] -- External Memory interface data [26]. PU I/O PIO5_0 -- General-purpose digital input/output pin. I ENET_RX_DV -- Ethernet receive data valid. I/O SD_D[7] -- SD/MMC data 7. O CT3_MAT2 -- Match output 2 from Timer 3. I/O FC4_RXD_SDA_MOSI -- Flexcomm 4: USART receiver, I2C data I/O, SPI master-out/slave-in data. R -- Reserved. PIO5_1 - 126 [2] I/O EMC_D[27] -- External Memory interface data [27]. PU I/O PIO5_1 -- General-purpose digital input/output pin. I ENET_CRS -- Ethernet Carrier Sense (MII interface) or Ethernet Carrier Sense/Data Valid (RMII interface). O SD_VOLT[0] -- SD/MMC card regulator voltage control [0]. O CT3_MAT3 -- Match output 3 from Timer 3. I/O FC4_TXD_SCL_MISO -- Flexcomm 4: USART transmitter, I2C clock, SPI master-in/slave-out data. R -- Reserved. I/O LPC546xx Product data sheet EMC_D[28] -- External Memory interface data [28]. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 45 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller - 202 [2] Type PIO5_2 Description Reset state [1] 208-pin, LQFP Pin description ...continued Symbol 180-pin, TFBGA Table 4. PU I/O PIO5_2 -- General-purpose digital input/output pin. I ENET_COL -- Ethernet Collision detect (MII interface). O SD_VOLT[1] -- SD/MMC card regulator voltage control [1]. I CT3_CAP0 -- Capture input 0 to Timer 3. I/O FC4_CTS_SDA_SSEL0 -- Flexcomm 4: USART clear-to-send, I2C data I/O, SPI Slave Select 0. R -- Reserved. PIO5_3 - 129 [2] I/O EMC_D[29] -- External Memory interface data [29]. PU I/O PIO5_3 -- General-purpose digital input/output pin. O ENET_MDC -- Ethernet management data clock. O SD_VOLT[2] -- SD/MMC card regulator voltage control [2]. I CT3_CAP1 -- Capture input 1 to Timer 3. I/O FC4_RTS_SCL_SSEL1 -- Flexcomm 4: USART request-to-send, I2C clock, SPI slave select 1. R -- Reserved. PIO5_4 - 135 [2] I/O EMC_D[30] -- External Memory interface data [30]. PU I/O PIO5_4 -- General-purpose digital input/output pin. I/O ENET_MDIO -- Ethernet management data I/O. O SD_BACKEND_PWR -- SD/MMC back-end power supply for embedded device. I CT3_CAP2 -- Capture input 2 to Timer 3. I/O FC4_SSEL2 -- Flexcomm 4: SPI slave select 2. R -- Reserved. PIO5_5 PIO5_6 - - 145 152 [2] [2] I/O EMC_D[31] -- External Memory interface data [31]. PU I/O PIO5_5 -- General-purpose digital input/output pin. I SCT0_GPI0 -- Pin input 0 to SCTimer/PWM. O PDM1_CLK -- Clock for PDM interface 1, for digital microphone. I CT3_CAP3 -- Capture input 3 to Timer 3. I/O FC4_SSEL3 -- Flexcomm 4: SPI slave select 3. O TRACECLK -- Trace clock. O EMC_A[21] -- External memory interface address 21. PU I/O I LPC546xx Product data sheet PIO5_6 -- General-purpose digital input/output pin. SCT0_GPI1 -- Pin input 1 to SCTimer/PWM. I PDM1_DATA -- Data for PDM interface 1 (digital microphone). I/O FC5_SCK -- Flexcomm 5: USART or SPI clock. O SCT0_OUT5 -- SCTimer/PWM output 5. O TRACEDATA[0] -- Trace data bit 0. O EMC_A[22] -- External memory interface address 22. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 46 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller - 171 [2] Type PIO5_7 Description Reset state [1] 208-pin, LQFP Pin description ...continued Symbol 180-pin, TFBGA Table 4. PU I/O PIO5_7 -- General-purpose digital input/output pin. I SCT0_GPI2 -- Pin input 2 to SCTimer/PWM. I/O MCLK -- MCLK input or output for I2S and/or digital microphone. I/O FC5_RXD_SDA_MOSI -- Flexcomm 5: USART receiver, I2C data I/O, SPI master-out/slave-in data. PIO5_8 PIO5_9 PIO5_10 - - - 175 179 168 [2] [2] [2] O SCT0_OUT6 -- SCTimer/PWM output 6. O TRACEDATA[1] -- Trace data bit 1. O EMC_A[23] -- External memory interface address 23. PU I/O PIO5_8 -- General-purpose digital input/output pin. I SCT0_GPI3 -- Pin input 3 to SCTimer/PWM. O PDM0_CLK -- Clock for PDM interface 0, for digital microphone. I/O FC5_TXD_SCL_MISO -- Flexcomm 5: USART transmitter, I2C clock, SPI master-in/slave-out data. O SCT0_OUT7 -- SCTimer/PWM output 7. O TRACEDATA[2] -- Trace data bit 2. O EMC_A[24] -- External memory interface address 24. PU I/O PIO5_9 -- General-purpose digital input/output pin. I SCT0_GPI4 -- Pin input 4 to SCTimer/PWM. I PDM0_DATA -- Data for PDM interface 0 (digital microphone). I/O FC5_CTS_SDA_SSEL0 -- Flexcomm 5: USART clear-to-send, I2C data I/O, SPI Slave Select 0. O SCT0_OUT8 -- SCTimer/PWM output 8. O TRACEDATA[3] -- Trace data bit 3. O EMC_A[25] -- External memory interface address 25. PU I/O I PIO5_10 -- General-purpose digital input/output pin. SCT0_GPI5 -- Pin input 5 to SCTimer/PWM. R -- Reserved. I/O FC5_RTS_SCL_SSEL1 -- Flexcomm 5: USART request-to-send, I2C clock, SPI slave select 1. O SCT0_OUT9 -- SCTimer/PWM output 9. I UTICK_CAP3 -- Micro-tick timer capture input 3. USB1_AVSSC F2 20 USB1 analog 3.3 V ground. USB1_REXT F1 21 USB1 analog signal for reference resistor, 12.4 k +/-1% USB1_ID G1 22 Indicates to the transceiver whether connected as an A-device (USB1_ID LOW) or B-device (USB1_ID HIGH). USB1_VBUS G2 23 USB1_AVDDC3V3 G3 24 USB1 analog 3.3 V supply. USB1_AVDDTX3V3 H1 25 USB1 analog 3.3 V supply for line drivers. LPC546xx Product data sheet [6] I/O VBUS pin (power on USB cable). All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 47 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 4. Description 27 [6] I/O USB1 bidirectional D+ line. H2 26 [6] I/O USB1 bidirectional D- line. USB1_AVSSTX3V3 J1 28 USB1_DM Type H3 Reset state [1] 208-pin, LQFP USB1_DP Pin description ...continued 180-pin, TFBGA Symbol USB1 analog ground for line drivers. 204 [6] I/O USB0 bidirectional D+ line. 205 [6] I/O USB0 bidirectional D- line. RESETN N13 101 [5] VDD E6; E8; F5; G5; J12; L6; L11 1; 48; 65; 104; 108; 156; 157; 206 - - Single 1.71 V to 3.6 V power supply powers internal digital functions and I/Os. VSS B3; D7; D8; E11 ; H5; J5; K7 2; 49; 66; 103; 107; 148; 162; 201 - - Ground. VDDA N6 64 - - Analog supply voltage. VREFN N4 59 - - ADC negative reference voltage. VREFP P6 63 - - ADC positive reference voltage. VSSA L5 60 - - Analog ground. - - Main oscillator input. USB0_DP USB0_DM XTALIN E5 D5 K4 41 [7] 40 [7] External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and the boot code to execute. Wakes up the part from deep power-down mode. XTALOUT J4 - - Main oscillator output. VBAT N11 94 - - Battery supply voltage. If no battery is used, tie VBAT to VDD or to ground. RTCXIN L12 105 - - RTC oscillator input. RTCXOUT K11 106 - - RTC oscillator output. [1] PU = input mode, pull-up enabled (pull-up resistor pulls up pin to VDD). Z = high impedance; pull-up or pull-down disabled, AI = analog input, I = input, O = output, F = floating. Reset state reflects the pin state at reset without boot code operation. For pin states in the different power modes, see Section 6.2.2 "Pin states in different power modes". For termination on unused pins, see Section 6.2.1 "Termination of unused pins". [2] 5 V tolerant pad with programmable glitch filter (5 V tolerant if VDD present; if VDD not present, do not exceed 3.6 V); provides digital I/O functions with TTL levels and hysteresis; normal drive strength. See Figure 41. Pulse width of spikes or glitches suppressed by input filter is from 3 ns to 16 ns (simulated value). [3] True open-drain pin. I2C-bus pins compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 48 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller [4] 5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant. [5] Reset pad.5 V tolerant pad with glitch filter with hysteresis. Pulse width of spikes or glitches suppressed by input filter is from 3 ns to 20 ns (simulated value) [6] 5 V tolerant transparent analog pad. [7] The oscillator input pin (XTALIN) cannot be driven by an external clock. Must connect a crystal between XTALIN and XTALOUT. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 49 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 6.2.1 Termination of unused pins Table 5 shows how to terminate pins that are not used in the application. In many cases, unused pins should be connected externally or configured correctly by software to minimize the overall power consumption of the part. Unused pins with GPIO function should be configured as outputs set to LOW with their internal pull-up disabled. To configure a GPIO pin as output and drive it LOW, select the GPIO function in the IOCON register, select output in the GPIO DIR register, and write a 0 to the GPIO PORT register for that pin. Disable the pull-up in the pin's IOCON register. In addition, it is recommended to configure all GPIO pins that are not bonded out on smaller packages as outputs driven LOW with their internal pull-up disabled. Table 5. Termination of unused pins Pin Default state[1] Recommended termination of unused pins RESET I; PU The RESET pin can be left unconnected if the application does not use it. all PIOn_m (not open-drain) I; PU Can be left unconnected if driven LOW and configured as GPIO output with pull-up disabled by software. PIOn_m (I2C open-drain) IA Can be left unconnected if driven LOW and configured as GPIO output by software. RTCXIN - Connect to ground. When grounded, the RTC oscillator is disabled. RTCXOUT - Can be left unconnected. XTALIN - Connect to ground. When grounded, the RTC oscillator is disabled. XTALOUT - Can be left unconnected. VREFP - Tie to VDD. VREFN - Tie to VSS. VDDA - Tie to VDD. VSSA - Tie to VSS. VBAT - Tie to VDD. USBn_DP F Can be left unconnected. If USB interface is not used, pin can be left unconnected except in deep power-down mode where it must be externally pulled low. When the USB PHY is disabled, the pins are floating. USBn_DM F Can be left unconnected. If USB interface is not used, pin can be left unconnected except in deep power-down mode where it must be externally pulled low. When the USB PHY is disabled, the pins are floating. USB1_AVSCC F Tie to VSS. USB1_VBUS F Tie to VDD. USB1_AVDDC3V3 F Tie to VDD. USB1_AVDDTX3V3 F Tie to VDD. USB1_AVSSTX3V3 F Tie to VSS. [1] I = Input, IA = Inactive (no pull-up/pull-down enabled), PU = Pull-Up enabled, F = Floating LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 50 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 6.2.2 Pin states in different power modes Table 6. Pin states in different power modes Pin Active Sleep IOCON[1]. Deep-sleep Deep power-down PIOn_m pins (not I2C) As configured in the PIO0_13 to PIO0_14 (open-drain I2C-bus pins) As configured in the IOCON[1]. Floating PIO3_23 to PIO3_24 (open-drain I2C-bus pins) As configured in the IOCON[1]. Floating RESET Reset function enabled. Default: input, internal pull-up enabled. Default: internal pull-up enabled. Floating Reset function disabled. [1] Default and programmed pin states are retained in sleep and deep-sleep. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 51 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7. Functional description 7.1 Architectural overview The ARM Cortex-M4 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus. The I-code and D-code core buses allow for concurrent code and data accesses from different slave ports. The LPC546xx uses a multi-layer AHB matrix to connect the ARM Cortex-M4 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slave ports of the matrix to be accessed simultaneously by different bus masters. 7.2 ARM Cortex-M4 processor The ARM Cortex-M4 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. The ARM Cortex-M4 offers many new features, including a Thumb-2 instruction set, low interrupt latency, hardware multiply and divide, interruptable/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller with wake-up interrupt controller, and multiple core buses capable of simultaneous accesses. A 3-stage pipeline is employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. 7.3 ARM Cortex-M4 integrated Floating Point Unit (FPU) The FPU fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and square root operations. It also provides conversions between fixed-point and floating-point data formats, and floating-point constant instructions. The FPU provides floating-point computation functionality that is compliant with the ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic, referred to as the IEEE 754 standard. 7.4 Memory Protection Unit (MPU) The Cortex-M4 includes a Memory Protection Unit (MPU) which can be used to improve the reliability of an embedded system by protecting critical data within the user application. The MPU allows separating processing tasks by disallowing access to each other's data, disabling access to memory regions, allowing memory regions to be defined as read-only and detecting unexpected memory accesses that could potentially break the system. The MPU separates the memory into distinct regions and implements protection by preventing disallowed accesses. The MPU supports up to eight regions each of which can be divided into eight subregions. Accesses to memory locations that are not defined in the MPU regions, or not permitted by the region setting, will cause the Memory Management Fault exception to take place. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 52 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.5 Nested Vectored Interrupt Controller (NVIC) for Cortex-M4 The NVIC is an integral part of the Cortex-M4. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.5.1 Features * * * * * * Controls system exceptions and peripheral interrupts. Supports up to 54 vectored interrupts. Eight programmable interrupt priority levels, with hardware priority level masking. Relocatable vector table. Non-Maskable Interrupt (NMI). Software interrupt generation. 7.5.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. 7.6 System Tick timer (SysTick) The ARM Cortex-M4 includes a system tick timer (SysTick) that is intended to generate a dedicated SYSTICK exception. The clock source for the SysTick can be the FRO or the Cortex-M4 core clock. 7.7 On-chip static RAM The LPC546xx support 200 kB SRAM with separate bus master access for higher throughput and individual power control for low-power operation. 7.8 On-chip flash The LPC546xx supports up to 512 kB of on-chip flash memory. 7.9 On-chip ROM The 64 kB on-chip ROM contains the boot loader and the following Application Programming Interfaces (API): * Flash In-Application Programming (IAP) and In-System Programming (ISP). * ROM-based USB drivers (HID, CDC, MSC, and DFU). Supports flash updates via USB. * * * * LPC546xx Product data sheet Supports booting from valid user code in flash, USART, SPI, and I2C. Legacy, Single, and Dual image boot. OTP API for programming OTP memory. Random Number Generator (RNG) API. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 53 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.10 EEPROM The LPC546xx contains up to 16 kB byte of on-chip word-erasable and word-programmable EEPROM data memory. EEPROM is not accessible in deep-sleep and deep-power-down modes. 7.11 Memory mapping The LPC546xx incorporates several distinct memory regions. The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.Each peripheral is allocated 4 kB of space simplifying the address decoding. The registers incorporated into the CPU, such as NVIC, SysTick, and sleep mode control, are located on the private peripheral bus. The ARM Cortex-M4 processor has a single 4 GB address space. The following table shows how this space is used on the LPC546xx. Table 7. Memory usage and details Address range General Use Address range details and description 0x0000 0000 to 0x1FFF FFFF On-chip non-volatile memory 0x0000 0000 - 0x0007 FFFF Flash memory (512 kB). Boot ROM 0x0300 0000 - 0x0300 FFFF Boot ROM with flash services in a 64 kB space. SRAMX 0x0400 0000 - 0x0400 7FFF I&D SRAM bank (32 kB). 0x2000 0000 to 0x3FFF FFFF 0x4000 0000 to 0x7FFF FFFF LPC546xx Product data sheet SPI Flash 0x1000 0000 - 0x17FF FFFF Interface (SPIFI) SPIFI memory mapped access space (128 MB). SRAM Banks SRAM banks (160 kB). 0x2000 0000 - 0x2002 7FFF SRAM bit band 0x2200 0000 - 0x23FF FFFF alias addressing SRAM bit band alias addressing (32 MB) APB peripherals 0x4000 0000 - 0x4001 FFFF APB slave group 0 up to 32 peripheral blocks of 4 kB each (128 kB). 0x4002 0000 - 0x4003 FFFF APB slave group 1 up to 32 peripheral blocks of 4 kB each (128 kB). 0x4004 0000 - 0x4005 FFFF APB asynchronous slave group 2 up to 32 peripheral blocks of 4 kB each (128 kB). AHB peripherals 0x4008 0000 - 0x400B FFFF AHB peripherals (256 kB). Peripheral bit band alias addressing Peripheral bit band alias addressing (32 MB) 0x4200 0000 - 0x43FF FFFF All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 54 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 7. Memory usage and details ...continued Address range General Use Address range details and description 0x8000 0000 to 0xDFFF FFFF Off-chip Memory Four static memory chip selects: via the External 0x8000 0000 - 0x83FF FFFF Static memory chip select 0 (up to 64 Memory MB)[1] Controller 0x8800 0000 - 0x8BFF FFFF Static memory chip select 1 (up to 64 MB)[2] 0x9000 0000 - 0x93FF FFFF Static memory chip select 2 (up to 64 MB) 0x9800 0000 - 0x9BFF FFFF Static memory chip select 3 (up to 64 MB) Four dynamic memory chip selects: 0xA000 0000 - 0xA7FF FFFF Dynamic memory chip select 0 (up to 256MB) 0xA800 0000 - 0xAFFF FFFF Dynamic memory chip select 1 (up to 256MB) 0xB000 0000 - 0xB7FF FFFF Dynamic memory chip select 2 (up to 256MB) 0xB800 0000 - 0xBFFF FFFF Dynamic memory chip select 3 (up to 256MB) 0xE000 0000 to 0xE00F FFFF Cortex-M4 Private Peripheral Bus 0xE000 0000 - 0xE00F FFFF Cortex-M4 related functions, includes the NVIC and System Tick Timer. [1] Can be up to 256 MB, upper address 0x8FFF FFFF, if the address shift mode is enabled. See the EMCSYSCTRL register bit 0 in the UM10912 LPC546xx user manual. [2] Can be up to 128 MB, upper address 0x97FF FFFF, if the address shift mode is enabled. See the EMCSYSCTRL register bit 0 in the UM10912 LPC546xx user manual. Figure 6 shows the overall map of the entire address space from the user program viewpoint following reset. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 55 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller AHB peripherals Memory space 0xFFFF FFFF (reserved) private peripheral bus 0x4010 BFFF 0xE010 0000 EPROM (16 kB) 0xE000 0000 (EMC) (reserved) 0x8000 0000 (reserved) USB SRAM (8 kB) 0x4400 0000 (reserved) peripheral bit-band addressing (reserved) (reserved) 0x4200 0000 HS USB host registers 0x400C 0000 FS USB host registers AHB peripheral (reserved) (reserved) Asynchronous APB peripherals 0x4008 0000 ADC 0x4006 0000 CAN 1 CAN 0 0x4004 0000 APB peripherals on APB bridge 1 0x4002 0000 see APB memory map figure APB peripherals on APB bridge 0 0x4000 0000 (reserved) ISP-AP interface SDIO Flexcomm 9 Flexcomm 8 Flexcomm 7 0x2400 0000 SRAM bit-band addressing 0x2200 0000 (reserved) Flexcomm 6 Flexcomm 5 CRC engine 0x2002 0000 SRAM2 (up to 32 kB) 0x2002 0000 SRAM1 (up to 64 kB) 0x2001 0000 SRAM0 (up to 64 kB) (reserved) Ethernet (reserved) D-Mic interface High Speed GPIO 0x2000 0000 (reserved) 0x1800 0000 Flexcomm 4 SPIFI Flash Interface memory mapped space (reserved) HS USB device Flexcomm 3 0x1000 0000 Flexcomm 2 0x0401 0000 Flexcomm 1 SRAMX (32 kB) Flexcomm 0 0x0400 0000 (reserved) 0x0300 0000 Boot ROM 0x0300 0000 (reserved) 0x0008 0000 Flash memory (up to 512 kB) 0x0000 0000 active interrupt vectors SC Timer / PWM FS USB device registers LCD registers DMA registers EMC registers SPIFI registers 0x0000 00C0 0x0000 0000 0x4010 8000 0x4010 2000 0x4010 0000 0x400A 5000 0x400A 4000 0x400A 3000 0x400A 2000 0x400A 1000 0x400A 0000 0x4009 E000 0x4009 D000 0x4009 C000 0x4009 B000 0x4009 A000 0x4009 9000 0x4009 8000 0x4009 7000 0x4009 6000 0x4009 5000 0x4009 4000 0x4009 2000 0x4009 1000 0x4009 0000 0x4008 C000 0x4008 B000 0x4008 A000 0x4008 9000 0x4008 8000 0x4008 7000 0x4008 6000 0x4008 5000 0x4008 4000 0x4008 3000 0x4008 2000 0x4008 1000 0x4008 0000 aaa-026742 The private peripheral bus includes CPU peripherals such as the NVIC, SysTick, and the core control registers. Fig 6. LPC546xx Memory mapping LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 56 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller APB bridge 1 APB bridge 0 31-22 21 (reserved) OTP controller 20 EEPROM controller (reserved) 19-15 14 Micro-Tick 13 MRT 12 WDT 11-10 (reserved) 9 CTIMER1 8 CTIMER0 7-6 (reserved) 5 Input muxes 4 Pin Interrupts (PINT) 3 GINT1 2 GINT0 1 IOCON 2 Syscon 0x4001 FFFF 0x4001 6000 0x4001 5000 0x4001 4000 31-27 (reserved) 26 RNG (reserved) 25-24 0x4003 FFFF 0x4003 B000 0x4003 A000 0x4003 8000 0x4001 F000 23 22 0x4000 E000 21 Smard card 1 Smart card 0 (reserved) 0x4000 D000 0x4000 C000 20 19-14 Flash controller (reserved) 0x4000 A000 13 RIT 0x4002 D000 0x4000 9000 12 RTC 0x4002 C000 0x4000 8000 11-9 (reserved) 0x4002 9000 0x4000 6000 8 7-0 CTIMER2 (reserved) 0x4002 8000 0x4002 0000 0x4000 5000 0x4000 4000 0x4003 7000 0x4003 6000 0x4003 5000 0x4003 4000 0x4002 E000 Asynchronous APB bridge 0x4000 3000 0x4005 FFFF 0x4000 2000 31-10 (reserved) 0x4000 1000 9 CTIMER4 0x4000 0000 8 CTIMER3 7-1 (reserved) 0 Asynch. Syscon 0x4004 A000 0x4004 9000 0x4004 8000 0x4004 1000 0x4004 0000 aaa-023944 Fig 7. LPC546xx APB Memory map 7.12 System control 7.12.1 Clock sources The LPC546xx supports one external and two internal clock sources: * Free Running Oscillator (FRO). * Watchdog oscillator (WDOSC). * Crystal oscillator. 7.12.1.1 Free Running Oscillator (FRO) The FRO 12 MHz oscillator provides the default clock at reset and provides a clean system clock shortly after the supply pins reach operating voltage. * 12 MHz internal FRO oscillator, factory trimmed for accuracy, that can optionally be used as a system clock as well as other purposes. * Selectable 48 MHz or 96 MHz FRO oscillator, factory trimmed for accuracy, that can optionally be used as a system clock as well as other purposes. 7.12.1.2 Watchdog oscillator (WDOSC) The watchdog oscillator is a low-power internal oscillator. The WDOSC can be used to provide a clock to the WWDT and to the entire chip. The low-power watchdog oscillator provides a selectable frequency in the range of 6 kHz to 1.5 MHz. The accuracy of this clock is limited to 40% over temperature, voltage, and silicon processing variations. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 57 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.12.1.3 Crystal oscillator The LPC546xx include four independent oscillators. These are the main oscillator, the FRO, the watchdog oscillator, and the RTC oscillator. Following reset, the LPC546xx will operate from the Internal FRO until switched by software. This allows systems to operate without any external crystal and the boot loader code to operate at a known frequency. See Figure 8 and Figure 9 for an overview of the LPC546xx clock generation. 7.12.2 System PLL (PLL0) The system PLL accepts an input clock frequency in the range of 32.768 kHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The PLL can be enabled or disabled by software. 7.12.3 USB PLL (PLL1) The USB PLL accepts an input clock frequency in the range of 1 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The PLL can be enabled or disabled by software. 7.12.4 Audio PLL (PLL2) The audio PLL accepts an input clock frequency in the range of 1 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The PLL can be enabled or disabled by software. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 58 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.12.5 Clock Generation fro_12m clk_in wdt_clk fro_hf 00 pll_clk 10 32k_clk 11 00 01 32k_clk "none" (1) MAINCLKSELB[1:0] 000 001 fro_hf 000 pll_clk 001 usb_pll_clk 010 audio_pll_clk 011 "none" 111 to EMC (function clock) EMCCLKDIV ADC CLOCK DIVIDER to ADC pll_clk SYSTEM PLL 011 ADC clock select ADCCLKSEL[2:0] 111 fro_hf pll_clk System PLL settings usb_pll_clk "none" 000 001 010 USB0 CLOCK DIVIDER to USB0 (FS USB) 111 USB0CLKDIV clk_in Crystal oscillator USB0 clock select USB0CLKSEL[2:0] Range select SYSOSCCTRL[1:0] fro_hf EMC ClOCK DIVIDER ADCCLKDIV PLL clock select SYSPLLCLKSEL[2:0] xtalin xtalout to CPU, AHB bus, Sync APB Main clock select B Main clock select A MAINCLKSELA[1:0] fro_12m clk_in main_clk AHBCLKDIV 10 11 (1) CPU CLOCK DIVIDER main_clk pll_clk fro_hf_div FRO Clock Divider 000 001 usb_pll_clk 010 "none" USB1 CLOCK DIVIDER to USB1 PHY 111 USB1CLKDIV USB1 clock select USB1CLKSEL[2:0] FROHFCLKDIV usb_pll_clk clk_in fro_12 fro_hf_div USB PLL 000 001 audio_pll_clk USB PLL settings fro_12m clk_in "none" 010 011 111 mclk_in "none" 000 001 Audio PLL audio_pll_clk to DMIC subsystem DMICCLKDIV DMIC clock select DMICCLKSEL[2:0] 111 fro_hf_div Audio clock select AUDIO PLL Settings AUDPLLCKSEL[2:0] main_clk fro_12m audio_pll_clk fc6_fclk 000 001 MCLK DIVIDER to MCLK pin (output) 111 MCLK clock select MCLKCLKSEL[1:0] 00 01 10 11 audio_pll_clk "none" MCLKDIV to Async APB (1) APB clock select B ASYNCAPBCLKSELA[1:0] main_clk pll_clk usb_pll_clk fro_hf audio_pll_clk "none" (1): synchronized multiplexer, see register descriptions for details. 000 001 010 011 100 111 SDIO clock select SDIOCLKSEL[2:0] Fig 8. DMIC CLOCK DIVIDER SDIO CLOCK DIVIDER to SDIO (function clock) SDIOCLKDIV aaa-023922 LPC546xx clock generation LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 59 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller (1 per Flexcomm) main_clk pll_clk fro_12m fro_hf 000 001 fro_12m fro_hf_div 010 audio_pll_clk "none" main_clk 000 001 fcn_fclk (function clock of Flexcomm[n]) 010 mclk_in 011 FRG CLOCK DIVIDER 111 FRG clock select FRGCTRL[15:0] FRGCLKSEL[2:0] main_clk FCLKSEL[n] main_clk main_clk pll_clk fro_hf audio_pll_clk "none" 000 001 SCTimer/PWM Clock Divider 010 011 111 MCAN0 clock divider to MCAN0 function clock CAN0CLKDIV to CLK32K of all Flexcomms 32k_clk to systick function clock SYSTICKCLKDIV 011 (up to 10 Flexcomm 100 Interfaces on these devices) 111 frg_clk "none" Systick clock divider to SCTimer/PWM input clock 7 MCAN1 clock divider to MCAN1 function clock CAN1CLKDIV SCTCLKDIV main_clk SCT clock select SCTCLKSEL[2:0] Smartcard0 clock divider to Smartcard0 function clock SC0CLKDIV main_clk lcdclkin fro_hf "none" 00 01 to LCD LCD CLOCK (function clock) DIVIDER 10 11 main_clk Smartcard1 clock divider to Smartcard1 function clock SC1CLKDIV LCDCLKDIV LCD clock select LCDCLKSEL[1:0] main_clk clk_in wdt_clk fro_hf pll_clk usb_pll_clk audio_pll_clk 32k_clk main_clk to ARM Trace function clock ARMTRACECLKDIV 000 001 main_clk pll_clk 010 011 100 CLKOUT DIVIDER CLKOUT usb_pll_clk fro_hf audio_pll_clk 101 CLKOUTDIV 110 111 "none" 000 001 010 011 100 SPIFI CLOCK DIVIDER 111 SPIFI CLKDIV SPIFI clock select SPIFICLKSEL[2:0] CLKOUT select CLKOUTSEL[2:0] Fig 9. ARM Trace clock divider to SPIFI (function clock) aaa-023923 LPC546xx clock generation (continued) 7.12.6 Brownout detection The LPC546xx includes a monitor for the voltage level on the VDD pin. If this voltage falls below a fixed level, the BOD sets a flag that can be polled or cause an interrupt. In addition, a separate threshold level can be selected to cause chip reset. 7.12.7 Safety The LPC546xx includes a Windowed WatchDog Timer (WWDT), which can be enabled by software after reset. Once enabled, the WWDT remains locked and cannot be modified in any way until a reset occurs. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 60 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.13 Power control The LPC546xx support a variety of power control features. In Active mode, when the chip is running, power and clocks to selected peripherals can be adjusted for power consumption. In addition, there are three special modes of processor power reduction with different peripherals running: sleep mode, deep-sleep mode, and deep power-down mode that can be activated using the power API library from the LPCOpen software package. 7.13.1 Sleep mode In sleep mode, the system clock to the CPU is stopped and execution of instructions is suspended until either a reset or an interrupt occurs. Peripheral functions, if selected to be clocked can continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, internal buses, and unused peripherals. The processor state and registers, peripheral registers, and internal SRAM values are maintained, and the logic levels of the pins remain static. 7.13.2 Deep-sleep mode In deep-sleep mode, the system clock to the processor is disabled as in sleep mode. All analog blocks are powered down by default but can be selected to keep running through the power API if needed as wake-up sources. The main clock and all peripheral clocks are disabled. The FRO is disabled. The flash memory is put in standby mode. Deep-sleep mode eliminates all power used by analog peripherals and all dynamic power used by the processor itself, memory systems and related controllers, and internal buses. The processor state and registers, peripheral registers, and internal SRAM values are maintained, and the logic levels of the pins remain static. GPIO Pin Interrupts, GPIO Group Interrupts, and selected peripherals such as USB0, USB1, DMIC, SPI, I2C, USART, WWDT, RTC, Micro-tick Timer, and BOD can be left running in deep sleep mode The FRO, RTC oscillator, and the watchdog oscillator can be left running.In some cases, DMA can operate in deep-sleep mode. For more details, see UM10912, LPC546xx user manual. 7.13.3 Deep power-down mode In deep power-down mode, power is shut off to the entire chip except for the RTC power domain and the RESET pin. The LPC546xx can wake up from deep power-down mode via the RESET pin and the RTC alarm. The ALARM1HZ flag in RTC control register generates an RTC wake-up interrupt request, which can wake up the part. During deep power-down mode, the contents of the SRAM and registers are not retained. All functional pins are tri-stated in deep power-down mode. Table 8 shows the peripheral configuration in reduced power modes. Table 8. Peripheral configuration in reduced power modes Peripheral Reduced power mode FRO Software configured Software configured Off Flash Software configured Standby Off BOD Software configured Software configured Off PLL Software configured Off Off Sleep LPC546xx Product data sheet Deep-sleep All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 Deep power-down (c) NXP Semiconductors N.V. 2017. All rights reserved. 61 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 8. Peripheral configuration in reduced power modes Peripheral Reduced power mode Sleep Deep-sleep Deep power-down Watchdog osc and WWDT Software configured Software configured Off Micro-tick Timer Software configured Software configured Off DMA Active Off USART Software configured Off; but can create a wake-up interrupt in synchronous Off slave mode or 32 kHz clock mode SPI Software configured Off; but can create a wake-up interrupt in slave mode Off I2C Software configured Off; but can create a wake-up interrupt in slave mode Off USB0 Software configured Software configured Off USB1 Software configured Software configured Off Ethernet Software configured Off Off DMIC Software configured Software configured Off Configurable some for operations. For more details, see UM10912, LPC546xx user manual. Other digital peripherals Software configured Off Off RTC oscillator Software configured LPC546xx Product data sheet Software configured Software configured All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 62 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 9 shows wake-up sources for reduced power modes. Table 9. Wake-up sources for reduced power modes Power mode Wake-up source Conditions Sleep Any interrupt Enable interrupt in NVIC. HWWAKE Certain Flexcomm Interface and DMIC subsystem activity. Pin interrupts Enable pin interrupts in NVIC and STARTER0 and/or STARTER1 registers. Deep-sleep BOD interrupt BOD reset Watchdog interrupt Watchdog reset Reset pin RTC 1 Hz alarm timer RTC 1 kHz timer time-out and alarm Micro-tick timer (intended for ultra-low power wake-up from deep-sleep mode * * * Enable interrupt in NVIC and STARTER0 registers. Enable interrupt in BODCTRL register. Configure the BOD to keep running in this mode with the power API. Enable reset in BODCTRL register. * * * * * * * Enable the watchdog oscillator in the PDRUNCFG0 register. Enable the watchdog interrupt in NVIC and STARTER0 registers. Enable the watchdog in the WWDT MOD register and feed. Enable interrupt in WWDT MOD register. Configure the WDTOSC to keep running in this mode with the power API. Enable the watchdog oscillator in the PDRUNCFG0 register. Enable the watchdog and watchdog reset in the WWDT MOD register and feed. Always available. * * * * * Enable the RTC 1 Hz oscillator in the RTCOSCCTRL register. * * * * * * Start RTC 1 kHz timer by writing a value to the WAKE register of the RTC. Enable the RTC bus clock in the AHBCLKCTRL0 register. Start RTC alarm timer by writing a time-out value to the RTC COUNT register. Enable the RTCALARM interrupt in the STARTER0 register. Enable the RTC 1 Hz oscillator and the RTC 1 kHz oscillator in the RTC CTRL register. Enable the RTC wake-up interrupt in the STARTER0 register. Enable the watchdog oscillator in the PDRUNCFG0 register. Enable the Micro-tick timer clock by writing to the AHBCLKCTRL1 register. Start the Micro-tick timer by writing UTICK CTRL register. Enable the Micro-tick timer interrupt in the STARTER0 register. I2C interrupt Interrupt from I2C in slave mode. SPI interrupt Interrupt from SPI in slave mode. USART interrupt Interrupt from USART in slave or 32 kHz mode. USB0 need clock interrupt Interrupt from USB0 when activity is detected that requires a clock. USB1 need clock interrupt Interrupt from USB1 when activity is detected that requires a clock. Ethernet interrupt Interrupt from ethernet. DMA interrupt Interrupt from DMA. HWWAKE Certain Flexcomm Interface and DMIC subsystem activity. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 63 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 9. Wake-up sources for reduced power modes Power mode Wake-up source Deep power-down RTC 1 Hz alarm timer RTC 1 kHz timer time-out and alarm Reset pin Conditions * * * Enable the RTC 1 Hz oscillator in the RTC CTRL register. * * Enable the RTC bus clock in the AHBCLKCTRL0 register. Start RTC alarm timer by writing a time-out value to the RTC COUNT register. Enable the RTC 1 Hz oscillator and the RTC 1 kHz oscillator in the RTCOSCCTRL register. Start RTC 1 kHz timer by writing a value to the WAKE register of the RTC. Always available. 7.14 General Purpose I/O (GPIO) The LPC546xx provides six GPIO ports with a total of up to 171 GPIO pins. Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The current level of a port pin can be read back no matter what peripheral is selected for that pin. 7.14.1 Features * Accelerated GPIO functions: - GPIO registers are located on the AHB so that the fastest possible I/O timing can be achieved. - Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. - All GPIO registers are byte and half-word addressable. - Entire port value can be written in one instruction. * Bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port. * Direction control of individual bits. * All I/O default to inputs after reset. * All GPIO pins can be selected to create an edge or level-sensitive GPIO interrupt request. * One GPIO group interrupt can be triggered by a combination of any pin or pins. 7.15 Pin interrupt/pattern engine The pin interrupt block configures up to eight pins from all digital pins for providing eight external interrupts connected to the NVIC. The pattern match engine can be used in conjunction with software to create complex state machines based on pin inputs. Any digital pin, independent of the function selected through the switch matrix can be configured through the SYSCON block as an input to the pin interrupt or pattern match engine. The registers that control the pin interrupt or pattern match engine are located on the I/O+ bus for fast single-cycle access. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 64 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.15.1 Features * Pin interrupts: - Up to eight pins can be selected from all GPIO pins on ports 0 and 1 as edge-sensitive or level-sensitive interrupt requests. Each request creates a separate interrupt in the NVIC. - Edge-sensitive interrupt pins can interrupt on rising or falling edges or both. - Level-sensitive interrupt pins can be HIGH-active or LOW-active. - Level-sensitive interrupt pins can be HIGH-active or LOW-active. - Pin interrupts can wake up the device from sleep mode and deep-sleep mode. * Pattern match engine: - Up to eight pins can be selected from all digital pins on ports 0 and 1 to contribute to a boolean expression. The boolean expression consists of specified levels and/or transitions on various combinations of these pins. - Each bit slice minterm (product term) comprising of the specified boolean expression can generate its own, dedicated interrupt request. - Any occurrence of a pattern match can also be programmed to generate an RXEV notification to the CPU. The RXEV signal can be connected to a pin. - Pattern match can be used in conjunction with software to create complex state machines based on pin inputs. - Pattern match engine facilities wake-up only from active and sleep modes. 7.16 Serial peripherals 7.16.1 Full-speed USB Host/Device interface (USB0) The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot plugging and dynamic configuration of the devices. All transactions are initiated by the host controller. 7.16.1.1 USB0 device controller The device controller enables 12 Mbit/s data exchange with a USB host controller. It consists of a register interface, serial interface engine, endpoint buffer memory. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. Features * * * * * * LPC546xx Product data sheet Supports 10 physical (5 logical) endpoints including two control endpoints. Single and double-buffering supported. Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types. Supports wake-up from reduced power mode on USB activity and remote wake-up. Supports SoftConnect. Link Power Management (LPM) supported. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 65 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.16.1.2 USB0 host controller The host controller enables full- and low-speed data exchange with USB devices attached to the bus. It consists of register interface, serial interface engine and DMA controller. The register interface complies with the Open Host Controller Interface (OHCI) specification. Features * OHCI compliant. * Two downstream ports. 7.16.2 High-speed USB Host/Device interface (USB1) The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot plugging and dynamic configuration of the devices. All transactions are initiated by the host controller. 7.16.2.1 USB1 device controller The device controller enables 480 Mbit/s data exchange with a USB host controller. It consists of a register interface, serial interface engine, endpoint buffer memory. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. Features * * * * * Fully compliant with USB 2.0 Specification (high speed). Supports 8 physical (16 logical) endpoints with up to 8 kB endpoint buffer RAM. Supports Control, Bulk, Interrupt and Isochronous endpoints. Scalable realization of endpoints at run time. Endpoint Maximum packet size selection (up to USB maximum specification) by software at run time. * While USB is in the Suspend mode, the LPC546xx can enter one of the reduced power modes and wake up on USB activity. * Double buffer implementation for Bulk and Isochronous endpoints. 7.16.2.2 USB1 host controller The host controller enables high speed data exchange with USB devices attached to the bus. It consists of register interface and serial interface engine. The register interface complies with the Enhanced Host Controller Interface (EHCI) specification. Features * EHCI compliant. * Two downstream ports. * Supports per-port power switching. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 66 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.16.3 Ethernet AVB The Ethernet block enables a host to transmit and receive data over Ethernet in compliance with the IEEE 802.3-2008 standard. The Ethernet interface contains a full featured 10 Mbps or 100 Mbps Ethernet MAC (Media Access Controller) designed to provide optimized performance through the use of DMA hardware acceleration. 7.16.3.1 Features * * * * 10/100 Mbit/s DMA support Power management remote wake-up frame and magic packet detection Supports both full-duplex and half-duplex operation - Supports CSMA/CD Protocol for half-duplex operation. - Supports IEEE 802.3x flow control for full-duplex operation. - Optional forwarding of received pause control frames to the user application in full-duplex operation. - Supports IEEE 802.1AS-2011 and 802.1-Qav-2009 for Audio Video (AV) traffic. - Software support for AVB feature is available from NXP Professional Services. See nxp.com for more details. - Back-pressure support for half-duplex operation. - Automatic transmission of zero-quanta pause frame on deassertion of flow control input in full-duplex operation. * Supports IEEE1588 time stamping and IEEE 1588 advanced time stamping (IEEE 1588-2008 v2). 7.16.4 SPI Flash Interface (SPIFI) The SPI Flash Interface allows low-cost serial flash memories to be connected to the LPC546xx microcontroller with little performance penalty compared to parallel flash devices with higher pin count. After a few commands configure the interface at startup, the entire flash content is accessible as normal memory using byte, halfword, and word accesses by the processor and/or DMA channels. Simple sequences of commands handle erasure and programming. Many serial flash devices use a half-duplex command-driven SPI protocol for device setup and initialization and then move to a half-duplex, command-driven 4-bit protocol for normal operation. Different serial flash vendors and devices accept or require different commands and command formats. SPIFI provides sufficient flexibility to be compatible with common flash devices and includes extensions to help insure compatibility with future devices. 7.16.4.1 Features * * * * LPC546xx Product data sheet Interfaces to serial flash memory in the main memory map. Supports classic and 4-bit bidirectional serial protocols. Half-duplex protocol compatible with various vendors and devices. Quad SPI Flash Interface with 1-, 2-, or 4-bit data at rates of up to 52 MB per second. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 67 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller * Supports DMA access. * Provides XIP (execute in place) feature to execute code directly from serial flash. 7.16.5 CAN Flexible Data (CAN FD) interface The LPC546xx contains two CAN FD interfaces, CAN FD 1 and CAN FD 2. 7.16.5.1 Features * * * * * * Conforms with CAN protocol version 2.0 part A, B and ISO 11898-1. CAN FD with up to 64 data bytes supported. CAN Error Logging. AUTOSAR support. SAE J1939 support. Improved acceptance filtering. 7.16.6 DMIC subsystem 7.16.6.1 Features * Pulse-Density Modulation (PDM) data input for left and/or right channels on 1 or 2 buses. * * * * Flexible decimation. 16 entry FIFO for each channel. DC blocking or unaltered DC bias can be selected. Data can be transferred using DMA from deep-sleep mode without waking up the CPU, then automatically returning to deep-sleep mode. * Data can be streamed directly to I2S on Flexcomm Interface 7. 7.16.7 Smart card interface 7.16.7.1 Features * Two DMA supported ISO 7816 Smart Card Interfaces. * Both asynchronous protocols, T = 0 and T = 1 are supported. 7.16.8 Flexcomm Interface serial communication 7.16.8.1 Features * * * * * LPC546xx Product data sheet USART with asynchronous operation or synchronous master or slave operation. SPI master or slave, with up to 4 slave selects. I2C, including separate master, slave, and monitor functions. Two I2S functions using Flexcomm Interface 6 and Flexcomm Interface 7. Data for USART, SPI, and I2S traffic uses the Flexcomm Interface FIFO. The I2C function does not use the FIFO. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 68 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.16.8.2 SPI serial I/O controller Features * Maximum data rates of 71 Mbit/s in master mode and 14 Mbit/s in slave mode for SPI functions. * Data frames of 1 to 16 bits supported directly. Larger frames supported by software or DMA set-up. * Master and slave operation. * Data can be transmitted to a slave without the need to read incoming data. This can be useful while setting up an SPI memory. * Control information can optionally be written along with data. This allows very versatile operation, including "any length" frames. * Four Slave Select input/outputs with selectable polarity and flexible usage. * Activity on the SPI in slave mode allows wake-up from deep-sleep mode on any enabled interrupt. Remark: Texas Instruments SSI and National Microwire modes are not supported. 7.16.8.3 I2C-bus interface The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line (SCL) and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (for example, an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it. Features * All I2Cs support standard, Fast-mode, and Fast-mode Plus with data rates of up to 1 Mbit/s. * * * * * All I2Cs support high-speed slave mode with data rates of up to 3.4 Mbit/s. Independent Master, Slave, and Monitor functions. Supports both Multi-master and Multi-master with Slave functions. Multiple I2C slave addresses supported in hardware. One slave address can be selectively qualified with a bit mask or an address range in order to respond to multiple I2C-bus addresses. * 10-bit addressing supported with software assist. * Supports SMBus. * Activity on the I2C in slave mode allows wake-up from deep-sleep mode on any enabled interrupt. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 69 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.16.8.4 USART Features * Maximum bit rates of 6.25 Mbit/s in asynchronous mode. * The maximum supported bit rate for USART master synchronous mode is 24 Mbit/s, and the maximum supported bit rate for USART slave synchronous mode is 12.5 Mbit/s. * 7, 8, or 9 data bits and 1 or 2 stop bits. * Synchronous mode with master or slave operation. Includes data phase selection and continuous clock option. * * * * * * * Multiprocessor/multidrop (9-bit) mode with software address compare. * * * * * * Received data and status can optionally be read from a single register RS-485 transceiver output enable. Autobaud mode for automatic baud rate detection Parity generation and checking: odd, even, or none. Software selectable oversampling from 5 to 16 clocks in asynchronous mode. One transmit and one receive data buffer. RTS/CTS for hardware signaling for automatic flow control. Software flow control can be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an RTS output. Break generation and detection. Receive data is 2 of 3 sample "voting". Status flag set when one sample differs. Built-in Baud Rate Generator with auto-baud function. A fractional rate divider is shared among all USARTs. Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS detect, and receiver sample noise detected. * Loopback mode for testing of data and flow control. * In synchronous slave mode, wakes up the part from deep-sleep mode. * Special operating mode allows operation at up to 9600 baud using the 32.768 kHz RTC oscillator as the UART clock. This mode can be used while the device is in deep-sleep mode and can wake-up the device when a character is received. * USART transmit and receive functions work with the system DMA controller. 7.16.8.5 I2S-bus interface The I2S bus provides a standard communication interface for streaming data transfer applications such as digital audio or data collection. The I2S bus specification defines a 3-wire serial bus, having one data, one clock, and one word select/frame trigger signal, providing single or dual (mono or stereo) audio data transfer as well as other configurations. In the LPC546xx, the I2S function is included in Flexcomm Interface 6 and Flexcomm Interface 7. Each of the Flexcomm Interface implements four I2S channel pairs. The I2S interface within one Flexcomm Interface provides at least one channel pair that can be configured as a master or a slave. Other channel pairs, if present, always operate as slaves. All of the channel pairs within one Flexcomm Interface share one set of I2S LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 70 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller signals, and are configured together for either transmit or receive operation, using the same mode, same data configuration and frame configuration. All such channel pairs can participate in a time division multiplexing (TDM) arrangement. For cases requiring an MCLK input and/or output, this is handled outside of the I2S block in the system level clocking scheme. Features * A Flexcomm Interface may implement one or more I2S channel pairs, the first of which could be a master or a slave, and the rest of which would be slaves. All channel pairs are configured together for either transmit or receive and other shared attributes. The number of channel pairs is defined for each Flexcomm Interface, and may be from 0 to 4. * Configurable data size for all channels within one Flexcomm Interface, from 4 bits to 32 bits. Each channel pair can also be configured independently to act as a single channel (mono as opposed to stereo operation). * All channel pairs within one Flexcomm Interface share a single bit clock (SCK) and word select/frame trigger (WS), and data line (SDA). * Data for all I2S traffic within one Flexcomm Interface uses the Flexcomm Interface FIFO. The FIFO depth is 8 entries. * Left justified and right justified data modes. * DMA support using FIFO level triggering. * TDM (Time Division Multiplexing) with a several stereo slots and/or mono slots is supported. Each channel pair can act as any data slot. Multiple channel pairs can participate as different slots on one TDM data line. * The bit clock and WS can be selectively inverted. * Sampling frequencies supported depends on the specific device configuration and applications constraints (for example, system clock frequency and PLL availability.) but generally supports standard audio data rates. See the data rates section in I2S chapter in the LPC546xx user manual to calculate clock and sample rates. Remark: The Flexcomm Interface function clock frequency should not be above 48 MHz. 7.17 Digital peripheral 7.17.1 LCD controller The LCD controller provides all of the necessary control signals to interface directly to various color and monochrome LCD panels. Both STN (single and dual panel) and TFT panels can be operated. The display resolution is selectable and can be up to 1024 768 pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode. An on-chip 512 byte color palette allows reducing bus utilization (that is, memory size of the displayed data) while still supporting many colors. The LCD interface includes its own DMA controller to allow it to operate independently of the CPU and other system functions. A built-in FIFO acts as a buffer for display data, providing flexibility for system timing. Hardware cursor support can further reduce the amount of CPU time required to operate the display. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 71 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.17.1.1 Features * * * * AHB master interface to access frame buffer. Setup and control via a separate AHB slave interface. Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data. Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays with 4-bit or 8-bit interfaces. * Supports single and dual-panel color STN displays. * Supports Thin Film Transistor (TFT) color displays. * Programmable display resolution including, but not limited to: 320 200, 320 240, 640 200, 640 240, 640 480, 800 600, and 1024 768. * * * * * * * * * * * * Hardware cursor support for single-panel displays. 15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support. 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN. 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT. 16 bpp true-color non-palettized for color STN and TFT. 24 bpp true-color non-palettized for color TFT. Programmable timing for different display panels. 256 entry, 16-bit palette RAM, arranged as a 128 32-bit RAM. Frame, line, and pixel clock signals. AC bias signal for STN, data enable signal for TFT panels. Supports little and big-endian, and Windows CE data formats. LCD panel clock may be generated from the peripheral clock, or from a clock input pin. 7.17.2 SD/MMC card interface The SD/MMC card interface supports the following modes to control: 7.17.2.1 Features * * * * * Secure Digital memory (SD version 1.1). Secure Digital I/O (SDIO version 2.0). Consumer Electronics Advanced Transport Architecture (CE-ATA version 1.1). MultiMedia Cards (MMC version 4.1). Supports up to a maximum of 50 MHz of interface frequency. 7.17.3 External memory controller The LPC546xx EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM, and flash. In addition, it can be used as an interface with off-chip memory-mapped devices and peripherals. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant peripheral. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 72 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.17.3.1 Features * Read and write buffers to reduce latency and to improve performance. * Low transaction latency. * Asynchronous static memory device support including RAM, ROM, and flash, with or without asynchronous page mode. * 8/16/32 data and 16/20/26 address lines wide static memory support. * Static memory features include: - Asynchronous page mode read. - Programmable Wait States. - Bus turnaround delay. - Output enable and write enable delays. - Extended wait. * Dynamic memory interface support including single data rate SDRAM. * 16 bit and 32 bit wide chip select SDRAM memory support. * Four chip selects for synchronous memory and four chip selects for static memory devices. * Power-saving modes dynamically control EMC_CKE and EMC_CLK outputs to SDRAMs. * Dynamic memory self-refresh mode controlled by software. * Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB parts, with 4, 8, 16, or 32 data bits per device. * Separate reset domains allow the for auto-refresh through a chip reset if desired. Note: Synchronous static memory devices (synchronous burst mode) are not supported. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 73 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.17.4 DMA controller The DMA controller allows peripheral-to memory, memory-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional DMA transfers for a single source and destination. 7.17.4.1 Features * One channel per on-chip peripheral direction: typically one for input and one for output for most peripherals. * * * * * * * DMA operations can optionally be triggered by on- or off-chip events. Priority is user selectable for each channel. Continuous priority arbitration. Address cache. Efficient use of data bus. Supports single transfers up to 1,024 words. Address increment options allow packing and/or unpacking data. 7.18 Counter/timers 7.18.1 General-purpose 32-bit timers/external event counter The LPC546xx includes five general-purpose 32-bit timer/counters. The timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts, generate timed DMA requests, or perform other actions at specified timer values, based on four match registers. Each timer/counter also includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.18.1.1 Features * A 32-bit timer/counter with a programmable 32-bit prescaler. * Counter or timer operation. * Up to four 32-bit captures can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt. The number of capture inputs for each timer that are actually available on device pins may vary by device. * Four 32-bit match registers that allow: - Continuous operation with optional interrupt generation on match. - Stop timer on match with optional interrupt generation. - Reset timer on match with optional interrupt generation. - Shadow registers are added for glitch-free PWM output. * For each timer, up to four external outputs corresponding to match registers with the following capabilities (the number of match outputs for each timer that are actually available on device pins may vary by device): - Set LOW on match. - Set HIGH on match. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 74 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller - Toggle on match. - Do nothing on match. * Up to two match registers can be used to generate timed DMA requests. * The timer and prescaler may be configured to be cleared on a designated capture event. This feature permits easy pulse width measurement by clearing the timer on the leading edge of an input pulse and capturing the timer value on the trailing edge. * Up to four match registers can be configured for PWM operation, allowing up to three single edged controlled PWM outputs. (The number of match outputs for each timer that are actually available on device pins may vary by device.) 7.18.2 SCTimer/PWM The SCTimer/PWM allows a wide variety of timing, counting, output modulation, and input capture operations. The inputs and outputs of the SCTimer/PWM are shared with the capture and match inputs/outputs of the 32-bit general-purpose counter/timers. The SCTimer/PWM can be configured as two 16-bit counters or a unified 32-bit counter. In the two-counter case, in addition to the counter value the following operational elements are independent for each half: * State variable. * Limit, halt, stop, and start conditions. * Values of Match/Capture registers, plus reload or capture control values. In the two-counter case, the following operational elements are global to the SCTimer/PWM, but the last three can use match conditions from either counter: * * * * * 7.18.2.1 Clock selection Inputs Events Outputs Interrupts Features * * * * * * Two 16-bit counters or one 32-bit counter. Counter(s) clocked by bus clock or selected input. Up counter(s) or up-down counter(s). State variable allows sequencing across multiple counter cycles. Event combines input or output condition and/or counter match in a specified state. Events control outputs, interrupts, and the SCTimer/PWM states. - Match register 0 can be used as an automatic limit. - In bi-directional mode, events can be enabled based on the count direction. - Match events can be held until another qualifying event occurs. * Selected event(s) can limit, halt, start, or stop a counter. * Supports: LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 75 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller - 8 inputs - 10 outputs - 16 match/capture registers - 16 events - 16 states * PWM capabilities including dead time and emergency abort functions 7.18.3 Windowed WatchDog Timer (WWDT) The purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window. 7.18.3.1 Features * Internally resets chip if not periodically reloaded during the programmable time-out period. * Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. * Optional warning interrupt can be generated at a programmable time prior to watchdog time-out. * Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. * * * * Incorrect feed sequence causes reset or interrupt if enabled. Flag to indicate watchdog reset. Programmable 24-bit timer with internal prescaler. Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in multiples of Tcy(WDCLK) 4. * The Watchdog Clock (WDCLK) uses the WDOSC as the clock source. 7.18.4 Real Time Clock (RTC) timer The RTC timer is a 32-bit timer which counts down from a preset value to zero. At zero, the preset value is reloaded and the counter continues. The RTC timer uses the 32.768 kHz clock input to create a 1 Hz or 1 kHz clock. 7.18.5 Multi-Rate Timer (MRT) The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each channel can be programmed with an independent time interval, and each channel operates independently from the other channels. 7.18.5.1 Features * 24-bit interrupt timer. * Four channels independently counting down from individually set values. * Repeat and one-shot interrupt modes. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 76 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.18.6 Repetitive Interrupt Timer (RIT) The repetitive interrupt timer provides a free-running 48-bit counter which is compared to a selectable value, generating an interrupt when a match occurs. Any bits of the timer/compare can be masked such that they do not contribute to the match detection. The repetitive interrupt timer can be used to create an interrupt that repeats at predetermined intervals. 7.18.6.1 Features * 48-bit counter running from the main clock. Counter can be free-running or can be reset when an RIT interrupt is generated. * 48-bit compare value. * 48-bit compare mask. An interrupt is generated when the counter value equals the compare value, after masking. This allows for combinations not possible with a simple compare. * Can be used for ETM debug time stamping. 7.19 12-bit Analog-to-Digital Converter (ADC) The ADC supports a resolution of 12-bit and fast conversion rates of up to 5 Msamples/s. Sequences of analog-to-digital conversions can be triggered by multiple sources. Possible trigger sources are the SCTimer/PWM, external pins, and the ARM TXEV interrupt. The ADC supports a variable clocking scheme with clocking synchronous to the system clock or independent, asynchronous clocking for high-speed conversions The ADC includes a hardware threshold compare function with zero-crossing detection. The threshold crossing interrupt is connected internally to the SCTimer/PWM inputs for tight timing control between the ADC and the SCTimer/PWM. 7.19.1 Features * * * * * 12-bit successive approximation analog to digital converter. Input multiplexing among up to 12 pins. Two configurable conversion sequences with independent triggers. Optional automatic high/low threshold comparison and "zero crossing" detection. Measurement range VREFN to VREFP (typically 3 V; not to exceed VDDA voltage level). * 12-bit conversion rate of 5.0 Msamples/s. Options for reduced resolution at higher conversion rates. * Burst conversion mode for single or multiple inputs. * Synchronous or asynchronous operation. Asynchronous operation maximizes flexibility in choosing the ADC clock frequency, Synchronous mode minimizes trigger latency and can eliminate uncertainty and jitter in response to a trigger. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 77 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.20 CRC engine The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings supports several CRC standards commonly used. To save system power and bus bandwidth, the CRC engine supports DMA transfers. 7.20.1 Features * Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32. - CRC-CCITT: x16 + x12 + x5 + 1 - CRC-16: x16 + x15 + x2 + 1 - CRC-32: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 * Bit order reverse and 1's complement programmable setting for input data and CRC sum. * Programmable seed number setting. * Supports CPU PIO or DMA back-to-back transfer. * Accept any size of data width per write: 8, 16 or 32-bit. - 8-bit write: 1-cycle operation. - 16-bit write: 2-cycle operation (8-bit x 2-cycle). - 32-bit write: 4-cycle operation (8-bit x 4-cycle). 7.21 Temperature sensor The temperature sensor transducer uses an intrinsic pn-junction diode reference and outputs a CTAT voltage (Complement To Absolute Temperature). The output voltage varies inversely with device temperature with an absolute accuracy of better than 5 C over the full temperature range (40 C to +105 C). The temperature sensor is only approximately linear with a slight curvature. The output voltage is measured over different ranges of temperatures and fit with linear-least-square lines. After power-up, the temperature sensor output must be allowed to settle to its stable value before it can be used as an accurate ADC input. For an accurate measurement of the temperature sensor by the ADC, the ADC must be configured in single-channel burst mode. The last value of a nine-conversion (or more) burst provides an accurate result. 7.22 Security features The OTP memory contains a memory bank of 128 bits each. OTP bank contains 4 words: word 0 for ECRP, word 1 is reserved, words 2 and 3 can be used by user application for storing application specific options. 7.22.1 Features * OTP memory. * Random number generator (RNG). LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 78 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.23 Code security (enhanced Code Read Protection - eCRP) eCRP is a mechanism that allows the user to enable different features in the security system. The features are specified using a combination of OTP and flash values. Some levels are only controlled by either flash or OTP, but the majority have dual control. The overlap allows higher security by specifying access using OTP bits, which cannot be changed (except to increase security) while allowing customers who are less concerned about security the ability to change levels in the flash image. eCRP is calculated by reading the ECRP from the flash boot sector (offset 0x0000 0020) and then masking it with the value read from OTP. The OTP bits are more restrictive (that is, disable access) than equivalent values in flash. Certain aspects of eCRP are only specified in the OTP (that is, Mass Erase disable), while others are only specified in flash (that is, Sector Protection count). For Dual Enhanced images, eCRP is calculated by reading the eCRP from the bootable image sector. The bootable image is defined as the highest revision image that passes the required validation methods. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 79 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.24 Emulation and debugging Debug and trace functions are integrated into the ARM Cortex-M4. Serial wire debug and trace functions are supported. The ARM Cortex-M4 is configured to support up to eight breakpoints and four watch points. The ARM SYSREQ reset is supported and causes the processor to reset the peripherals, execute the boot code, restart from address 0x0000 0000, and break at the user entry point. The SWD pins are multiplexed with other digital I/O pins. On reset, the pins assume the SWD functions by default. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 80 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 8. Limiting values Table 10. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions [2] Min Max Unit -0.5 +4.6 V VDD supply voltage (core and on pin VDD external rail) VDDA analog supply voltage on pin VDDA -0.5 +4.6 V VBAT battery supply voltage on pin VBAT -0.5 +4.6 V Vref reference voltage on pin VREFP VI input voltage only valid when the VDD > 1.8 V; - -0.5 +4.6 V [6][7] -0.5 +5.0 V [5] -0.5 +5.0 V -0.5 +5.0 V -0.5 VDD V [3] - 200 mA [3] - 300 mA [3] - 200 mA [3] - 300 mA - 100 mA -65 +150 C - +150 C 5 V tolerant I/O pins on I2C open-drain pins USB_DM, USB_DP pins VIA analog input voltage on digital pins configured for an analog function IDD supply current per supply pin, supply current per supply pin, [8][9] 1.71 V VDD < 2.7 V 2.7 V VDD < 3.6 V ISS ground current per ground pin, 1.71 V VDD < 2.7 V ground current per ground pin, 2.7 V VDD < 3.6 V Ilatch I/O latch-up current Tstg storage temperature Tj(max) maximum junction temperature Ptot(pack) total power dissipation (per package) (0.5VDD) < VI < (1.5VDD); Tj < 125 C VESD electrostatic discharge voltage LPC546xx Product data sheet [10] LQFP208, based on package heat transfer, not device power consumption [11] - 1.2 W LQFP208, based on package heat transfer, not device power consumption [12] - 0.95 W TFBGA180, based on package heat transfer, not device power consumption [11] - 0.95 W TFBGA180, based on package heat transfer, not device power consumption [13] - 1.2 W [4] - 2000 V human body model; all pins All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 81 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller [1] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. c) The limiting values are stress ratings only and operating the part at these values is not recommended and proper operation is not guaranteed. The conditions for functional operation are specified in Table 21. [2] Maximum/minimum voltage above the maximum operating voltage (see Table 21) and below ground that can be applied for a short time (< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device. [3] The peak current is limited to 25 times the corresponding maximum current. [4] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. [5] VDD present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD is powered down. [6] Applies to all 5 V tolerant I/O pins except true open-drain pins. [7] Including the voltage on outputs in 3-state mode. [8] An ADC input voltage above 3.6 V can be applied for a short time without leading to immediate, unrecoverable failure. Accumulated exposure to elevated voltages at 4.6 V must be less than 106 s total over the lifetime of the device. Applying an elevated voltage to the ADC inputs for a long time affects the reliability of the device and reduces its lifetime. [9] It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin. [10] Dependent on package type. [11] JEDEC (4.5 in 4 in); still air. [12] Single layer (4.5 in 3 in); still air. [13] 8-layer (4.5 in 3 in); still air. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 82 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 9. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: T j = T amb + P D R th j - a (1) * Tamb = ambient temperature (C), * Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) * PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of the I/O pins is often small and many times can be negligible. However it can be significant in some applications. Table 11. Thermal resistance Symbol Parameter Conditions Max/Min JEDEC (4.5 in 4 in); still air Unit LQFP208 Package Rth(j-a) Rth(j-c) thermal resistance from junction to ambient 33 15 % C/W Single-layer (4.5 in 3 in); still air 41 15 % C/W 16 15 % C/W JEDEC (4.5 in 4 in); still air 41 15 % C/W 8-layer (4.5 in 3 in); still air 33 15 % C/W 14 15 % C/W thermal resistance from junction to case TFBGA180 Package Rth(j-a) Rth(j-c) LPC546xx Product data sheet thermal resistance from junction to ambient thermal resistance from junction to case All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 83 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 10. Static characteristics 10.1 General operating conditions Table 12. General operating conditions Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions fclk CPU clock frequency Typ[1] Max Unit - - 180 MHz CPU clock frequency For USB high-speed device and host operations 60 - 180 MHz CPU clock frequency For USB full-speed device and host operations 12 - 180 MHz 1.71 - 3.6 V 2.7 - 3.6 V supply voltage (core and external rail) VDD Min [2] For OTP programming only 3.0 - 3.6 V VDDA analog supply voltage For USB operation only 1.71 - 3.6 V VBAT battery supply voltage 1.71 - 3.6 V Vrefp ADC positive reference voltage VDDA 2 V 2.0 - VDDA V VDDA < 2 V VDDA - VDDA V For EEPROM operation 40.0 - +85 C on pin RTCXIN -0.5 - +3.6 V on pin RTCXOUT -0.5 - +3.6 V Tamb Temperature RTC oscillator pins Vi(rtcx) 32.768 kHz oscillator input voltage Vo(rtcx) 32.768 kHz oscillator output voltage Vi(xtal) crystal input voltage on pin XTALIN 0.5 - 1.95 V Vo(xtal) crystal output voltage on pin XTALOUT 0.5 - 1.95 V [1] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages. [2] Attempting to program below 2.7 V will result in unpredictable results and the part might enter an unrecoverable state. 10.2 Power-up ramp conditions Table 13. Power-up characteristics[1] Tamb = 40 C to +105 C. Symbol Parameter Min Typ Max Unit twd Window duration - - 170 s (time where V1<VDD<V2) V1 V2 LPC546xx Product data sheet Window low voltage [2] 1.4 - - V Window high voltage [3] - - 1.62 V [1] Assert the external reset pin until VDD is > 1.62 V if the power-up characteristic specification cannot be implemented. [2] VDD to stay above V1 for the entire duration twd. [3] VDD to stay below V2 for the minimum duration of twd. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 84 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller twd VDD V2 V1 0 t1 aaa-025788 t1: The time when there is no restriction on the ramp rate. Fig 10. Power-up ramp 10.3 CoreMark data Table 14. CoreMark score Tamb = 25C, VDD = 3.3V Parameter Conditions Typ Unit ARM Cortex-M4 in active mode CoreMark score CoreMark score CoreMark code executed from SRAMX; CCLK = 12 MHz [1][3][4][6][7] 2.62 (Iterations/s) / MHz CCLK = 96 MHz [1][3][4][6][7] 2.62 (Iterations/s) / MHz CCLK = 180 MHz [2][3][4][6][7] 2.62 (Iterations/s) / MHz [1][3][4][5][7] 2.61 (Iterations/s) / MHz CCLK = 96 MHz; 5 system clock flash access time. [1][3][4][5][7] 2.18 (Iterations/s) / MHz CCLK = 180 MHz; 9 system clock flash access time. [2][3][4][5][7] 1.98 (Iterations/s) / MHz CoreMark code executed from flash; CCLK = 12 MHz; 1 system clock flash access time. [1] Clock source FRO. PLL disabled. [2] Clock source 12 MHz FRO. PLL enabled. [3] Characterized through bench measurements using typical samples. [4] Compiler settings: Keil Vision v.5.21, optimization level 3, optimized for time on. [5] See the FLASHCFG register in the LPC546xx User Manual for system clock flash access time settings. Acceleration enable bit in the FLASHCFG register is set to 1. [6] Flash is powered down [7] SRAM1, SRAM2, SRAM3, and USB SRAM powered down. SRAM0 and SRAMX powered. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 85 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller DDD &RUHPDUNVFRUH LWHUDWLRQVV0+] 065$0 0)ODVK )UHTXHQF\ 0+] Conditions: VDD = 3.3 V; Tamb = 25 C; active mode; all peripherals disabled; BOD disabled; See the FLASHCFG register in the LPC546xx User Manual for system clock flash access time settings. Acceleration enable bit in the FLASHCFG register is set to 1. Measured with Keil uVision v.5.21. Optimization level 3, optimized for time ON. 12 MHz, 24 MHz, 48 MHz, and 96 MHz: FRO enabled; PLL disabled. 36 MHz, 60 MHz, 72 MHz, 84 MHz, 108 MHz, 120 MHz, 132 MHz, 144 MHz, 156 MHz, 168 MHz, and 180 MHz: FRO enabled; PLL enabled. CoreMark score from flash: SRAM1, SRAM2, SRAM3, and USB SRAM powered down. SRAM0 and SRAMX powered. CoreMark score from SRAMX: SRAM0 is powered; flash is powered down. Fig 11. Typical CoreMark score ((iterations/s)/MHz) vs. Frequency (MHz) from flash and SRAMX LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 86 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 10.4 Power consumption Power measurements in Active, sleep, and deep-sleep modes were performed under the following conditions: * * * * Configure all pins as GPIO with pull-up resistor disabled in the IOCON block. Configure GPIO pins as outputs using the GPIO DIR register. Write 1 to the GPIO CLR register to drive the outputs LOW. All peripherals disabled. Table 15. Static characteristics: Power consumption in active and sleep mode Tamb = 40 C to +105 C, unless otherwise specified.1.71 V VDD 3.6 V. Symbol Parameter Conditions supply current CoreMark code executed from SRAMX; flash powered down Min Typ[1] Max Unit Active mode IDD supply current IDD CCLK = 12 MHz [2][3][4][6] - 3.3 - mA CCLK = 96 MHz [2][3][4][6] - 11 - mA CCLK = 180 MHz [3][4][6][7] - 24 - mA [2][3][4][5] - 4 - mA CCLK = 96 MHz; 5 system clock flash access time. [2][3][4][5] - 9.4 - mA CCLK = 180 MHz; 9 system clock flash access time. [3][4][5][7] - 18 - mA CCLK = 12 MHz [2][3][4][6] - 1.7 - mA CCLK = 96 MHz [2][3][4][6] - 4.1 - mA CCLK = 180 MHz [3][4][7] - 8.3 - mA CoreMark code executed from flash; CCLK = 12 MHz; 1 system clock flash access time. Sleep mode supply current IDD [1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C), 3.3V. [2] Clock source FRO. PLL disabled. [3] Characterized through bench measurements using typical samples. [4] Compiler settings: Keil uVision v.5.21, optimization level 0, optimized for time off. [5] Acceleration enable bit in the FLASHCFG register is set to 0. SRAM0 powered. SRAM1, SRAM2, SRAM3, USB SRAM and SRAMX powered down. [6] Flash is powered down; SRAM0 and SRAMX are powered; SRAM1, SRAM2, SRAM3, and USB SRAM are powered down. All peripheral clocks disabled. [7] Clock source FRO. PLL enabled. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 87 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller DDD $0+] 065$0 )523// 065$0 )52 0)/$6+ )52 0)/$6+ )523// )UHTXHQF\ 0+] Conditions: VDD = 3.3 V; Tamb = 25 C; active mode; all peripherals disabled; BOD disabled; Acceleration enable bit in the FLASHCFG register is set to 0. See the FLASHCFG register in the LPC546xx User Manual for system clock flash access time settings. Measured with Keil uVision v.5.21. Optimization level 0, optimized for time off. 12 MHz, 24 MHz, 48 MHz, and 96 MHz: FRO enabled; PLL disabled. 36 MHz, 60 MHz, 72 MHz, 84 MHz, 108 MHz, 120 MHz, 132 MHz, 144 MHz, 156 MHz, 168 MHz, and 180 MHz: FRO enabled; PLL enabled. CoreMark A/MHz from flash: SRAM1, SRAM2, SRAM3, and USB SRAM powered down. SRAM0 and SRAMX powered. CoreMark A/MHz from SRAMX: SRAM0 is powered; flash is powered down. Fig 12. CoreMark power consumption: typical A/MHz vs. frequency (MHz) from flash and SRAMX Table 16. Static characteristics: Power consumption in deep-sleep and deep power-down modes Tamb = 40 C to +105 C, unless otherwise specified, 1.71 V VDD 2.7 V. Symbol Parameter Conditions IDD supply current Deep-sleep mode; Flash is powered down SRAMX (32 KB) powered Min Typ[1][2] Max[3] Unit - 22 64 A - - 800 A - 326 1000 nA - - 27 A - 340 - nA Tamb = 25 C SRAMX (32 KB) powered Tamb = 105 C Deep power-down mode RTC oscillator input grounded (RTC oscillator disabled) Tamb = 25 C RTC oscillator input grounded (RTC oscillator disabled) Tamb = 105 C RTC oscillator running with external crystal VDD = VDDA = VREFP = VBAT = 1.8 V [1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C), VDD = 1.8 V. [2] Characterized through bench measurements using typical samples. [3] Guaranteed by characterization, not tested in production. VDD = 2.7 V. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 88 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 17. Static characteristics: Power consumption in deep-sleep and deep power-down modes Tamb = 40 C to +105 C, unless otherwise specified, 2.7 V VDD 3.6 V. Min Typ[1][2] Max[3] Unit - 23 68 A - - 1150 A - 464 1500 nA - - 42 A - 550 - nA Min Typ[1][2] Max Unit VDD = VDDA= VREFP = 3.3 V, VBAT = 3.0 V - 0 - nA VDD = VDDA= VREFP = 0 V or tied to ground, VBAT = 3.0 V - 340 - nA Symbol Parameter Conditions IDD supply current Deep-sleep mode; Flash is powered down SRAMX (32 KB) powered Tamb = 25 C SRAMX (32 KB) powered Tamb = 105 C Deep power-down mode RTC oscillator input grounded (RTC oscillator disabled) Tamb = 25 C RTC oscillator input grounded (RTC oscillator disabled) Tamb = 105 C RTC oscillator running with external crystal VDD = VDDA= VREFP = 3.3 V, VBAT = 3.0 V [1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C), VDD = 3.3 V. [2] Characterized through bench measurements using typical samples. [3] Tested in production, VDD = 3.6 V. Table 18. Static characteristics: Power consumption in deep power-down mode Tamb = 40 C to +105 C, unless otherwise specified, 2.7 V VDD 3.6 V. Symbol Parameter Conditions IBAT battery supply Deep power-down mode; current RTC oscillator running with external crystal [1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C). [2] Characterized through bench measurements using typical samples. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 89 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller DDD ,'' $ 9 9 9 9 7HPSHUDWXUH & Conditions: BOD disabled; all oscillators and analog blocks disabled; all SRAM disabled except 32 KB SRAMX. Fig 13. Deep-sleep mode: Typical supply current IDD versus temperature for different supply voltages VDD DDD ,'' $ 9 9 9 9 7HPSHUDWXUH & RTC disabled (RTC oscillator input grounded). Fig 14. Deep power-down mode: Typical supply current IDD versus temperature for different supply voltages VDD Table 19 shows the typical peripheral power consumption measured on a typical sample at Tamb = 25 C and VDD = 3.3 V. The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled using ASYNCAPBCLKCTRL, AHBCLKCTRL0/1/2, and PDRUNCFG0/1 registers. All other blocks are disabled and no code accessing the peripheral is executed. The supply currents are shown for system clock frequencies of 12 MHz, 48 MHz, 96 MHz and 180MHz. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 90 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 19. Typical peripheral power consumption[1][2] VDD = 3.3 V; Tamb = 25 C Peripheral IDD in uA FRO 100 WDT OSC 2.0 Flash 200 BOD 2.0 [1] The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled using PDRUNCFG0/1 registers. All other blocks are disabled and no code accessing the peripheral is executed. [2] Typical ratings are not guaranteed. Characterized through bench measurements using typical samples. Table 20. Typical AHB/APB peripheral power consumption [3][4][5] Tamb = 25 C, VDD = 3.3 V; Peripheral IDD in uA/MHz AHB peripheral CPU: 12 MHz, sync CPU: 48 MHz, sync CPU: 96 MHz, sync CPU: 180 MHz, sync APB bus: 12 MHz APB bus: 48 MHz APB bus: 96 MHz APB bus: 180 MHz USB0 device 0.3 0.3 0.3 0.4 USB1 device 4.4 4.4 4.4 5.0 DMIC IDD in uA/MHz IDD in uA/MHz IDD in uA/MHz 0.2 0.2 0.2 0.2 GPIO0 [1] 0.9 0.9 0.9 1.0 GPIO1 [1] 0.8 0.8 0.8 1.0 GPIO2 [1] 1.0 1.0 1.0 1.1 GPIO3 [1] 1.1 1.1 1.1 1.3 GPIO4 [1] 1.0 1.0 1.0 1.2 GPIO5 [1] 0.7 0.7 0.7 0.8 0.7 0.7 0.7 0.8 DMA CRC 1.0 1.0 1.0 1.0 ADC0 1.6 1.6 1.6 1.9 SCTimer/PWM 4.5 4.5 4.5 5.3 Ethernet AVB 24.0 24.0 24.0 28.0 LCD 13.0 13.0 13.0 15.0 EEPROM 1.1 1.1 1.1 1.2 EMC 39.0 39.0 39.0 45.4 CAN0 10.8 10.8 10.8 12.6 CAN1 10.7 10.7 10.7 12.4 SD/MMC 7.9 7.9 7.9 9.3 Flexcomm Interface 0 (USART, SPI, I2C) 1.6 1.6 1.6 1.9 Flexcomm Interface1 (USART, SPI, I2C) 1.6 1.6 1.6 1.8 Flexcomm Interface 2 (USART, SPI, I2C) 1.7 1.7 1.7 1.9 Flexcomm Interface 3 (USART, SPI, I2C) 1.4 1.4 1.4 1.6 LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 91 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 20. Typical AHB/APB peripheral power consumption [3][4][5] Tamb = 25 C, VDD = 3.3 V; Peripheral IDD in uA/MHz IDD in uA/MHz IDD in uA/MHz IDD in uA/MHz Flexcomm Interface 4 (USART, SPI, I2C) 1.4 1.5 1.5 1.7 Flexcomm Interface 5 (USART, SPI, I2C) 1.7 1.7 1.7 1.9 Flexcomm Interface 6 (USART, SPI, I2C, I2S) 2.0 2.0 2.0 2.3 Flexcomm Interface 7 (USART, SPI, I2C, I2S) 1.6 1.6 1.6 1.9 Flexcomm Interface 8 (USART, SPI, I2C) 1.5 1.5 1.5 1.8 Flexcomm Interface 9 (USART, SPI, I2C) 1.5 1.5 1.5 1.8 Sync APB peripheral CPU: 12 MHz, sync CPU: 48 MHz, sync CPU: 96 MHz, sync CPU: 180 MHz, sync APB bus: 12 MHz APB bus: 48 MHz APB bus: 96 MHz APB bus: 180 MHz INPUTMUX [1] 0.83 0.85 0.86 1.0 IOCON [1] 2.67 2.65 2.65 3.13 PINT 1.1 1.1 1.1 1.3 GINT0 and GINT1 1.33 1.35 1.34 1.52 WWDT 0.42 0.42 0.42 0.46 RTC 0.3 0.3 0.3 0.3 MRT 0.3 0.3 0.3 0.3 RIT 0.1 0.1 0.1 0.1 UTICK 0.2 0.2 0.2 0.2 CTimer0 0.8 0.8 0.8 0.9 CTimer1 0.8 0.9 0.9 1.0 CTimer2 0.83 0.85 0.88 0.99 Smart card0 2.5 2.5 2.5 2.8 Smart card1 2.5 2.5 2.5 2.8 RNG 1.4 1.4 1.4 1.5 OTP controller 4.0 4.0 4.0 4.5 LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 92 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 20. Typical AHB/APB peripheral power consumption [3][4][5] Tamb = 25 C, VDD = 3.3 V; Peripheral IDD in uA/MHz IDD in uA/MHz IDD in uA/MHz IDD in uA/MHz Async APB peripheral CPU: 12 MHz, CPU: 48 MHz, sync CPU: 96 MHz, CPU: 180 MHz, Async APB bus: 12 APB bus: 12 MHz[2] Async APB bus: 12 Async APB bus: MHz MHz[2] 12 MHz[2] Timer3 0.9 0.9 0.9 0.9 Timer4 0.9 0.9 0.9 0.9 [1] Turn off the peripheral when the configuration is done. [2] For optimal system power consumption, use fixed low frequency Async APB bus when the CPU is at a higher frequency. [3] The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled using ASYNCAPBCLKCTRL, AHBCLKCTRL0/1, and PDRUNCFG0/1 registers. All other blocks are disabled and no code accessing the peripheral is executed. [4] The supply currents are shown for system clock frequencies of 12 MHz, 48 MHz, 96 MHz and 180 MHz. [5] Typical ratings are not guaranteed. Characterized through bench measurements using typical samples. 10.5 Pin characteristics Table 21. Static characteristics: pin characteristics Tamb = 40 C to +105 C, unless otherwise specified. 1.71 V VDD 3.6 V unless otherwise specified. Values tested in production unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit 0.8 VDD - 5.0 V 0.5 - 0.3 VDD V RESET pin VIH HIGH-level input voltage VIL LOW-level input voltage Vhys [14] hysteresis voltage 0.05 VDD - - V - 3.0 180 nA 3.0 180 nA - 3.0 180 nA 0 - 5.0 V 0 - 3.6 V 1.5 - 5.0 V Standard I/O pins Input characteristics IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled. IIH HIGH-level input current VI = VDD; VDD = 3.6 V; for RESETN pin. IIH HIGH-level input current VI = VDD; on-chip pull-down resistor disabled VI input voltage pin configured to provide a digital function; [3] VDD 1.8 V VDD = 0 V VIH HIGH-level input voltage VIL LOW-level input voltage 1.71 V VDD < 2.7 V 2.7 V VDD 3.6 V 2.0 - 5.0 V 1.71 V VDD < 2.7 V 0.5 - +0.4 V 0.5 - +0.8 V 0.1 VDD - - V 0 - VDD V 2.7 V VDD 3.6 V Vhys [14] hysteresis voltage Output characteristics VO output voltage LPC546xx Product data sheet output active All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 93 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 21. Static characteristics: pin characteristics ...continued Tamb = 40 C to +105 C, unless otherwise specified. 1.71 V VDD 3.6 V unless otherwise specified. Values tested in production unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit IOZ OFF-state output current VO = 0 V; VO = VDD; on-chip pull-up/pull-down resistors disabled - 3 180 nA VOH HIGH-level output voltage IOH = 4 mA; 1.71 V VDD < 2.7 V VDD 0.4 - - V IOH = 6 mA; 2.7 V VDD 3.6 V VOL VDD 0.4 LOW-level output voltage IOL = 4 mA; 1.71 V VDD < 2.7 V IOL = 6 mA; 2.7 V VDD 3.6 V IOH HIGH-level output current VOH = VDD 0.4 V; 1.1.71 V VDD < 2.7 V VOH = VDD 0.4 V; 2.7 V VDD 3.6 V IOL LOW-level output current VOL = 0.4 V; 1.71 V VDD < 2.7 V VOL = 0.4 V; 2.7 V VDD 3.6 V IOHS IOLS HIGH-level short-circuit output current 1.71 V VDD < 2.7 V drive HIGH; connected to ground; 2.7 V VDD 3.6 V LOW-level short-circuit output current 1.71 V VDD < 2.7 V drive LOW; connected to VDD 2.7 V VDD 3.6 V [2][4] [2][4] - - 0.4 V - - 0.4 V 4.0 - - mA 6.0 - - mA 4.0 - - mA 6.0 - - mA - - 35 mA - - 87 mA - - 30 mA - - 77 mA 25 80 A 80 100 A 25 80 A 6 30 A Weak input pull-up/pull-down characteristics Ipd pull-down current VI = VDD [2] VI = 5 V Ipu pull-up current VI = 0 V VDD < VI < 5 V [2][7] Open-drain I2C pins VIH VIL Vhys HIGH-level input voltage LOW-level input voltage 1.71 V VDD < 2.7 V 0.7 VDD - - V 2.7 V VDD 3.6 V 0.7 VDD - - V 1.71 V VDD < 2.7 V 0 - 0.3 VDD V 2.7 V VDD 3.6 V 0 - 0.3 VDD V 0.1 VDD - - V - 2.5 3.5 A VI = 5 V - 5.5 10 A VOL = 0.4 V; pin configured for standard mode or fast mode 4.0 - - mA VOL = 0.4V; pin configured for Fast-mode Plus 20 - - mA hysteresis voltage ILI input leakage current IOL LOW-level output current LPC546xx Product data sheet [5] VI = VDD All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 94 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 21. Static characteristics: pin characteristics ...continued Tamb = 40 C to +105 C, unless otherwise specified. 1.71 V VDD 3.6 V unless otherwise specified. Values tested in production unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit USB0_DM and USB0_DP pins VI input voltage 0 - VDD V VIH HIGH-level input voltage 2.0 - - V VIL LOW-level input voltage - - 0.8 V Vhys hysteresis voltage 0.4 - - V Zout output impedance [11] 33.0 - 44 VOH HIGH-level output voltage [12] 2.8 - - V VOL LOW-level output voltage [13] IOH IOL - - 0.3 V HIGH-level output current VOH = VDD 0.3 V [9][10] 38 - 74 mA VOH = VDD 0.3 V [10][11] 6.0 9.0 mA LOW-level output current VOL = 0.3 V [9][10] 38 74 mA VOL = 0.3 V [10][11] 6.0 9.0 mA - IOLS LOW-level short-circuit output current drive LOW; pad connected to ground [10] IOHS HIGH-level short-circuit output current drive HIGH; pad connected to ground [10] - - 100 mA I2C-bus pins [8] - - 6.0 pF pins with digital functions only [6] - - 2.0 pF Pins with digital and analog functions [6] - - 7.0 pF - - 100 mA Pin capacitance input/output capacitance Cio [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltage. [2] Based on characterization. Not tested in production. [3] With respect to ground. [4] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [5] To VSS. [6] The values specified are simulated and absolute values, including package/bondwire capacitance. [7] The weak pull-up resistor is connected to the VDD rail and pulls up the I/O pin to the VDD level. [8] The value specified is a simulated value, excluding package/bondwire capacitance. [9] Without 33 2 % series external resistor. [10] The parameter values specified are simulated and absolute values. [11] With 33 2 % series external resistor. [12] With 15 K 5 % resistor to VSS. [13] With 1.5 K 5% resistor to 3.6 V external pull-up. [14] Guaranteed by design, not tested in production. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 95 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller VDD IOL Ipd + - pin PIO0_n A IOH Ipu - + pin PIO0_n A aaa-010819 Fig 15. Pin input/output current measurement 10.5.1 Electrical pin characteristics DDD & & & & ,2/ P$ DDD ,2/ P$ & & & & 92/ 9 Conditions: VDD = 1.8 V; on pins PIO0_13 to PIO0_14. Fig 16. I2C-bus 92/ 9 Conditions: VDD = 3.3 V; on pins PIO0_13 to PIO0_16. pins (high current sink): Typical LOW-level output current IOL versus LOW-level output voltage VOL LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 96 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller DDD ,2/ P$ DDD & & & & ,2/ P$ & & & & 92/ 9 Conditions: VDD = 1.8 V; on standard port pins. 92/ 9 Conditions: VDD = 3.3 V; on standard port pins. Fig 17. Typical LOW-level output current IOL versus LOW-level output voltage VOL DDD 92+ 9 DDD 92+ 9 & & & & & & & & ,2+ P$ Conditions: VDD = 1.8 V; on standard port pins. ,2+ P$ Conditions: VDD = 3.3 V; on standard port pins. Fig 18. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 97 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller DDD ,SX $ DDD ,SX $ & & & & & & & & 9, 9 Conditions: VDD = 1.8 V; on standard port pins. 9, 9 Conditions: VDD = 3.3 V; on standard port pins. Fig 19. Typical pull-up current IPU versus input voltage VI DDD ,SG $ & & & & 9, 9 DDD ,SG $ & & & & Conditions: VDD = 1.8V; on standard port pins. 9, 9 Conditions: VDD = 3.3 V; on standard port pins. Fig 20. Typical pull-down current IPD versus input voltage VI LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 98 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 11. Dynamic characteristics 11.1 Flash memory Table 22. Flash characteristics Tamb = 40 C to +105 C, unless otherwise specified. VDD = 1.71 V to 3.6 V Symbol Parameter Conditions Nendu endurance sector erase/program [1] page erase/program; page in a sector retention time tret ter erase time tprog programming time Min Typ Max Unit 10000 - - cycles 1000 - - cycles powered 10 - - years unpowered 10 - - years page, sector, or multiple consecutive sectors - 100 - ms - 1 - ms [2] [1] Number of erase/program cycles. [2] Programming times are given for writing 512 bytes from RAM to the flash. Data must be written to the flash in blocks of 512 bytes. 11.2 EEPROM Table 23. EEPROM characteristics Tamb = 40 C to +85 C; VDD = 1.71 V to 3.6 V. Symbol Parameter Min Typ Max Unit fclk clock frequency 800 1500 1600 kHz Nendu endurance 100000 - - cycles tret retention time Tamb = 40 C to +85 C 20 - - years ta access time read - 100 - ns erase/program; fclk = 1500 kHz - 1.99 - ms erase/program; fclk = 1600 kHz - 1.87 - ms twait wait time [1] Conditions read; RPHASE1 [1] 70 - - ns read; RPHASE2 [1] 35 - - ns write; PHASE1 [1] 20 - - ns write; PHASE2 [1] 40 - - ns write; PHASE3 [1] 10 - - ns See the LPC546xx user manual, UM10912 on how to program the wait states for the different read (RPHASEx) and erase/program phases (PHASEx). Remark: EEPROM is not accessible in deep-sleep and deep power-down modes LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 99 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 11.3 I/O pins Table 24. Dynamic characteristic: I/O pins[1] Tamb = 40 C to +105 C; 1.71 V VDD 3.6 V Symbol Parameter Conditions Min Typ Max Unit Standard I/O pins - normal drive strength tr tf rise time pin configured as output; SLEW = 1 (Fast-mode); fall time [2][3] 2.7 V VDD <= 3.6 V 1.0 - 2.5 ns 1.71 V VDD <= 1.98 V 1.6 - 3.8 ns 0.9 - 2.5 ns 1.7 - 4.1 ns 1.9 - 4.3 ns 2.9 - 7.8 ns 1.9 - 4.0 ns pin configured as output; SLEW = 1 (Fast-mode); [2][3] 2.7 V VDD <= 3.6 V 1.71 V VDD <= 1.98 V tr rise time pin configured as output; SLEW = 0 (standard mode); [2][3] 2.7 V VDD 3.6 V 1.71 V VDD 1.98 V tf fall time pin configured as output; SLEW = 0 (standard mode); [2][3] 2.7 V VDD 3.6 V 1.71 V VDD 1.98 V tr tf rise time fall time LPC546xx Product data sheet 2.7 - 6.7 ns pin configured as input [4] 0.3 - 1.3 ns pin configured as input [4] 0.2 - 1.2 ns [1] Simulated data, not tested in production. [2] Simulated using 10 cm of 50 PCB trace with 5 pF receiver input. Rise and fall times measured between 80 % and 20 % of the full output signal level. [3] The slew rate is configured in the IOCON block the SLEW bit. See the LPC546xx user manual. [4] CL = 20 pF. Rise and fall times measured between 90 % and 10 % of the full input signal level. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 100 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 11.4 Wake-up process Table 25. Dynamic characteristic: Typical wake-up times from low power modes VDD = 3.3 V;Tamb = 25 C; using FRO as the system clock. Symbol Parameter twake wake-up time Min Typ[1] from sleep mode [2][3] - 2.0 - s from deep-sleep mode; SRAMx powered. [2][5] - 19 - s [4][5] - 1.2 - ms Conditions Max Unit SRAM0, SRAM1, SRAM2, SRAM3, and USB SRAM powered down. from deep power-down mode; RTC disabled; using RESET pin. [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] The wake-up time measured is the time between when a GPIO input pin is triggered to wake the device up from the low power modes and from when a GPIO output pin is set in the interrupt service routine (ISR) wake-up handler. [3] FRO enabled, all peripherals off. PLL disabled. [4] RTC disabled. Wake up from deep power-down causes the part to go through entire reset process. The wake-up time measured is the time between when the RESET pin is triggered to wake the device up and when a GPIO output pin is set in the reset handler. [5] LPC546xx Product data sheet FRO disabled. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 101 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 11.5 External memory interface Table 26. Dynamic characteristics: Static external memory interface CL = 10 pF balanced loading on all pins, Tamb = 40 C to 105 C, VDD = 2.7 V to 3.6 V. Max EMC clock = 100 MHz. Input slew = 1 ns; SLEW set to fast-mode. Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Excluding delays introduced by external device and PCB; Values based on simulation. Symbol Parameter[1] Conditions[1] Min Typ Max Unit 1.2 - 1.6 ns 0.4+ Tcy(clk) WAITOEN - 0.8+ Tcy(clk) WAITOEN ns 1.6 - 0 ns (WAITRD WAITOEN + 1) Tcy(clk) - 0.3 ns 6.7 - - ns Read cycle parameters tCSLAV CS LOW to address valid time RD1 tCSLOEL CS LOW to OE LOW time RD2 tCSLBLSL CS LOW to BLS LOW time RD3; PB = 1 tOELOEH OE LOW to OE HIGH time RD4 memory access time RD5 tam [2] [2][6] [2] [2][3] + (WAITRD WAITOEN + 1) Tcy(clk) + (WAITRD WAITOEN +1) Tcy(clk) 4.8 - - ns tCSHBLSH CS HIGH to BLS HIGH PB = 1 time [6] 0.8 - 1.5 ns tCSHOEH CS HIGH to OE HIGH time [2] 0.5 - 0.9 ns tOEHANV OE HIGH to address invalid time [2] 0.4 - 0 ns tdeact deactivation time [2] 0.5 - 0.9 ns th(D) data input hold time [2][4] RD6 RD7 Write cycle parameters tCSLAV CS LOW to address valid time WR1 0.1 - 0.5 ns tCSLDV CS LOW to data valid time WR2 1.0 - 2.2 ns tCSLWEL CS LOW to WE LOW time WR3; PB =1 [2][6] 0.6 - 0 ns tCSLBLSL CS LOW to BLS LOW time WR4; PB = 1 [2][6] 1.2 - 0 ns tWELWEH WE LOW to WE HIGH time WR5; PB =1 [2][6] (WAITWR WAITWEN + 1) Tcy(clk) - 0.1 ns [2][6] 2.5 - 5.5 ns [2][6] 1.6 - 2.9 ns [2][5][6] 0.6 - 0.9 ns tBLSLBLSH BLS LOW to BLS HIGH time tWEHDNV WE HIGH to data invalid time tWEHEOW WE HIGH to end of write time LPC546xx Product data sheet PB = 1 WR6; PB =1 WR7; PB = 1 + (WAITWR WAITWEN + 1) Tcy(clk) All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 102 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 26. Dynamic characteristics: Static external memory interface ...continued CL = 10 pF balanced loading on all pins, Tamb = 40 C to 105 C, VDD = 2.7 V to 3.6 V. Max EMC clock = 100 MHz. Input slew = 1 ns; SLEW set to fast-mode. Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Excluding delays introduced by external device and PCB; Values based on simulation. Symbol Parameter[1] tBLSHDNV BLS HIGH to data invalid time Conditions[1] Min Typ Max Unit PB = 1 [6] 0.8 - 0 ns [6] 0.6 - 0.9 ns tWEHANV WE HIGH to address invalid time PB = 1 tdeact deactivation time WR8; PB = 0; PB = 1 [2][6] 0.8 - 0 ns tCSLBLSL CS LOW to BLS LOW WR9; PB = 0 [2][6] 1.2 - (WAITWEN + 1) Tcy(clk) ns - 5.5 ns + (WAITWEN + 1) Tcy(clk) tBLSLBLSH BLS LOW to BLS HIGH time WR10; PB = 0 tBLSHEOW BLS HIGH to end of write time WR11; PB = 0 tBLSHDNV BLS HIGH to data invalid time WR12; PB = 0 [2][6] 2.5 + (WAITWR WAITWEN + 1) Tcy(clk) [2][5][6] 0.8 + (WAITWR WAITWEN + 1) Tcy(clk) - Tcy(clk) ns - 0.5 + Tcy(clk) ns + Tcy(clk) [2][6] 0.2 + Tcy(clk) [1] Parameters are shown as RDn or WDn in Figure 21 as indicated in the Conditions column. [2] Tcy(clk) = 1/EMC_CLK (see UM10912 LPC546xx manual). [3] Latest of address valid, EMC_CSx LOW, EMC_OE LOW, EMC_BLSx LOW (PB = 1). [4] After End Of Read (EOR): Earliest of EMC_CSx HIGH, EMC_OE HIGH, EMC_BLSx HIGH (PB = 1), address invalid. [5] End Of Write (EOW): Earliest of address invalid, EMC_CSx HIGH, EMC_BLSx HIGH (PB = 1). [6] The byte lane state bit, PB, enables different types of memory to be connected (see the STATICCONFIG[0:3] register in the UM10912 LPC546xx manual). Table 27. Dynamic characteristics: Static external memory interface CL = 20 pF balanced loading on all pins, Tamb = 40 C to 105 C, VDD = 2.7 V to 3.6 V. Max EMC clock = 100 MHz. Input slew = 1 ns; SLEW set to fast-mode. Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Excluding delays introduced by external device and PCB; Values based on simulation. Symbol Parameter[1] Conditions[1] Min Typ Max Unit 1.2 - 1.6 ns 0.5+ Tcy(clk) WAITOEN - 0.8+ Tcy(clk) WAITOEN ns 2.3 - 0 ns (WAITRD WAITOEN + 1) Tcy(clk) - 0.3 ns 7.9 - Read cycle parameters tCSLAV CS LOW to address valid time RD1 tCSLOEL CS LOW to OE LOW time RD2 tCSLBLSL CS LOW to BLS LOW time RD3; PB = 1 tOELOEH OE LOW to OE HIGH time RD4 memory access time RD5 tam [2] [2][6] [2] [2][3] + (WAITRD WAITOEN + 1) Tcy(clk) - ns + (WAITRD WAITOEN +1) Tcy(clk) LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 103 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 27. Dynamic characteristics: Static external memory interface ...continued CL = 20 pF balanced loading on all pins, Tamb = 40 C to 105 C, VDD = 2.7 V to 3.6 V. Max EMC clock = 100 MHz. Input slew = 1 ns; SLEW set to fast-mode. Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Excluding delays introduced by external device and PCB; Values based on simulation. Symbol Parameter[1] Conditions[1] th(D) data input hold time RD6 Min Typ Max Unit 5.5 - - ns [6] 0.7 - 1.5 ns [2] 0.5 - 0.9 ns [2][4] tCSHBLSH CS HIGH to BLS HIGH PB = 1 time tCSHOEH CS HIGH to OE HIGH time tOEHANV OE HIGH to address invalid time RD8 [2] 0.4 - 0 ns tdeact deactivation time RD7 [2] 0.5 - 0.9 ns Write cycle parameters[2] tCSLAV CS LOW to address valid time WR1 0.1 - 0.5 ns tCSLDV CS LOW to data valid time WR2 1 - 2.2 ns tCSLWEL CS LOW to WE LOW time WR3; PB =1 [2][6] 0.5 + (WAITWEN + 1) Tcy(clk) (WAITWEN + 1) Tcy(clk) ns tCSLBLSL CS LOW to BLS LOW time WR4; PB = 1 [2][6] 1.9 0 tWELWEH WE LOW to WE HIGH time WR5; PB =1 [2][6] 0.1 + (WAITWEN + 1) Tcy(clk) (WAITWEN + 1) Tcy(clk) ns [2][6] 3.1 - 6.7 ns [2][6] 1.6 + Tcy(clk) - 2.8 + Tcy(clk) ns 0.5+Tcy(clk) - 0.8 + Tcy(clk) ns tBLSLBLSH BLS LOW to BLS HIGH time PB = 1 tWEHDNV WR6; PB =1 WE HIGH to data invalid time [2][5][6] - ns tWEHEOW WE HIGH to end of write time WR7; PB = 1 tBLSHDNV BLS HIGH to data invalid time PB = 1 [6] 0.8 - 0 ns tWEHANV WE HIGH to address invalid time PB = 1 [6] 0.5 - 0.8 ns tdeact deactivation time WR8; PB = 0; PB = 1 [2][6] 0.8 - 0 ns tCSLBLSL CS LOW to BLS LOW WR9; PB = 0 [2][6] 1.9 - (WAITWEN + 1) Tcy(clk) ns 3.1+ (WAITWR WAITWEN + 1) Tcy(clk) - 6.7+ (WAITWR WAITWEN + 1) Tcy(clk) ns 0.8 - Tcy(clk) ns - 0.5 + Tcy(clk) ns + (WAITWEN + 1) Tcy(clk) tBLSLBLSH BLS LOW to BLS HIGH time WR10; PB = 0 [2][6] tBLSHEOW BLS HIGH to end of write time WR11; PB = 0 [2][5][6] tBLSHDNV BLS HIGH to data invalid time [1] + Tcy(clk) WR12; PB = 0 [2][6] 0.2 + Tcy(clk) Parameters are shown as RDn or WDn in Figure 21 as indicated in the Conditions column. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 104 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller [2] Tcy(clk) = 1/EMC_CLK (see UM10912 LPC546xx manual). [3] Latest of address valid, EMC_CSx LOW, EMC_OE LOW, EMC_BLSx LOW (PB = 1). [4] After End Of Read (EOR): Earliest of EMC_CSx HIGH, EMC_OE HIGH, EMC_BLSx HIGH (PB = 1), address invalid. [5] End Of Write (EOW): Earliest of address invalid, EMC_CSx HIGH, EMC_BLSx HIGH (PB = 1). [6] The byte lane state bit, PB, enables different types of memory to be connected (see the STATICCONFIG[0:3] register in the UM10912 LPC546xx manual). EMC_Ax RD1 WR1 EMC_CSx WR8 RD8 RD2 RD4 EMC_OE RD7 WR9 WR10 WR11 EMC_BLSx EMC_WE RD5a RD5b RD5 RD6 WR2 WR12 EMC_Dx EOR EOW aaa-026103 Fig 21. External static memory read/write access (PB = 0) LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 105 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller EMC_Ax RD1 WR1 EMC_CSx RD2 WR8 RD8 RD4 EMC_OE RD3 RD7 WR4 EMC_BLSx WR8 RD7 WR3 WR5 WR7 EMC_WE RD5a RD5b RD5c RD6 RD5 WR2 WR6 EMC_Dx EOR EOW aaa026104 Fig 22. External static memory read/write access (PB =1) EMC_Ax EMC_CSx EMC_OE EMC_BLSx EMC_WE RD5 RD5 RD5 RD5 EMC_Dx 002aag216 Fig 23. External static memory burst read cycle LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 106 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 28. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 01 [2] CL = 10 pF balanced loading on all pins, Tamb = 40 C to 105 C, VDD = 2.7 V to 3.6 V. Max EMC clock = 100 MHz. Input slew = 1 ns; SLEW set to fast-mode. Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Excluding delays introduced by external device and PCB. Values based on simulation. tcmddly is programmable delay value for EMC command outputs in command delayed mode; tfbdly is programmable delay value for the feedback clock that controls input data sampling. Symbol Parameter Min Typ Max Unit 10 - - ns For RD = 1 Common to read and write cycles Tcy(clk) clock cycle time [1] td(SV) chip select valid delay time - - tcmddly + 3.7 ns th(S) chip select hold time tcmddly + 1.7 - - ns td(RASV) row address strobe valid delay time - - tcmddly + 4.1 ns th(RAS) row address strobe hold time tcmddly + 1.8 - - ns td(CASV) column address strobe valid delay time - - tcmddly + 4.4 ns th(CAS) column address strobe hold time tcmddly + 1.9 - - ns td(WV) write valid delay time - - tcmddly + 5.1 ns th(W) write hold time tcmddly + 2.4 - - ns td(AV) address valid delay time - - tcmddly + 4.8 ns th(A) address hold time tcmddly + 1.7 - - ns Read cycle parameters tsu(D) data input set-up time 0.5 - - ns th(D) data input hold time 2.1 - - ns Write cycle parameters td(QV) data output valid delay time - - 8.1 ns th(Q) data output hold time 1.7 - - ns [1] Refers to SDRAM clock signal EMC_CLKOUTn where n = 0 and 1. [2] See Table 30 for internal programmable delay. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 107 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 29. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 01 [2] CL = 20 pF balanced loading on all pins, Tamb = 40 C to 105 C, VDD = 2.7 V to 3.6 V. Max EMC clock = 100 MHz. Input slew = 1 ns; SLEW set to fast-mode. Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Excluding delays introduced by external device and PCB. Values based on simulation. tcmddly is programmable delay value for EMC command outputs in command delayed mode; tfbdly is programmable delay value for the feedback clock that controls input data sampling. Symbol Parameter Min Typ Max Unit 10 - - ns For RD = 1 Common to read and write cycles Tcy(clk) clock cycle time [1] td(SV) chip select valid delay time - - tcmddly + 4.9 ns th(S) chip select hold time tcmddly + 2.4 - - ns td(RASV) row address strobe valid delay time - - tcmddly + 5.4 ns th(RAS) row address strobe hold time tcmddly + 2.5 - - ns td(CASV) column address strobe valid delay time - - tcmddly + 5.6 ns th(CAS) column address strobe hold time tcmddly + 2.6 - - ns td(WV) write valid delay time - - tcmddly + 6.3 ns th(W) write hold time tcmddly + 3.1 - - ns td(AV) address valid delay time - - tcmddly + 6.1 ns th(A) address hold time tcmddly + 2.4 - - ns Read cycle parameters tsu(D) data input set-up time 0.5 - - ns th(D) data input hold time 2.1 - - ns Write cycle parameters td(QV) data output valid delay time - - 9.3 ns th(Q) data output hold time 2.4 - - ns [1] Refers to SDRAM clock signal EMC_CLKOUTn where n = 0 and 1. [2] See Table 30 for internal programmable delay. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 108 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Tcy(clk) EMC_CLKOUT0 EMC_CLKOUT1 EMC_DYCSn, EMC_RAS, EMC_CAS, EMC_WE, EMC_CKEOUTn, EMC_A[22:0], EMC_DQMOUTn td(xV) th(x) td(QV) th(Q) EMC_D[31:0] write tsu(D) th(D) EMC_D[31:0] read aaa-024988 Fig 24. Dynamic external memory interface signal timing LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 109 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 30. Dynamic characteristics: Dynamic external memory interface programmable clock delays (CMDDLY, FBCLKDLY) Tamb = 40 C to 105 C, VDD = 2.7 V to 3.6 V.Values guaranteed by design. tcmddly is programmable delay value for EMC command outputs in command delayed mode; tfbdly is programmable delay value for the feedback clock that controls input data sampling. Symbols Parameter tcmddly, tfbdly delay time [1] LPC546xx Product data sheet Five bit value for each delay in EMCDLYCTL[1] Min Typ Max Unit b00000 0.41 0.66 0.77 ns b00001 0.52 0.85 1.03 ns b00010 0.69 1.11 1.3 ns b00011 0.8 1.3 1.56 ns b00100 0.95 1.53 1.77 ns b00101 1.06 1.72 2.03 ns b00110 1.23 1.98 2.3 ns b00111 1.34 2.17 2.56 ns b01000 1.45 2.3 2.67 ns b01001 1.56 2.49 2.93 ns b01010 1.73 2.75 3.2 ns b01011 1.84 2.94 3.46 ns b01100 1.99 3.17 3.67 ns b01101 2.1 3.36 3.93 ns b01110 2.27 3.62 4.2 ns b01111 2.38 3.81 4.46 ns b10000 2.45 3.86 4.46 ns b10001 2.56 4.05 4.72 ns b10010 2.73 4.31 4.99 ns b10011 2.84 4.5 5.25 ns b10100 2.99 4.73 5.46 ns b10101 3.1 4.92 5.72 ns b10110 3.27 5.18 5.99 ns b10111 3.38 5.37 6.25 ns b11000 3.49 5.5 6.36 ns b11001 3.6 5.69 6.62 ns b11010 3.77 5.95 6.89 ns b11011 3.88 6.14 7.15 ns b11100 4.03 6.37 7.36 ns b11101 4.14 6.56 7.62 ns b11110 4.31 6.82 7.89 ns b11111 4.42 7.01 8.15 ns The programmable delay blocks are controlled by the EMCDLYCTL register in the EMC register block. All delay times are incremental delays for each element starting from delay block 0. See the LPC546xx user manual for details. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 110 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 11.6 System PLL (PLL0) Table 31. PLL lock times and current Tamb = 40 C to +105 C, unless otherwise specified. VDD = 1.71 V to 3.6 V Symbol Parameter Conditions Min Typ Max Unit PLL0 configuration: input frequency 12 MHz; output frequency 100 MHz tlock(PLL0) IDD(PLL0) PLL0 lock time [1] PLL0 current [1][2] when locked - - 96 s 2.0 mA PLL0 configuration: input frequency 32 kHz; output frequency 100 MHz Table 32. tlock(PLL0) PLL0 lock time IDD(PLL0) PLL0 current when locked [1] - - 108 s [1][2] - - 1.6 mA [1] Data based on characterization results, not tested in production. [2] PLL current measured using lowest CCO frequency to obtain the desired output frequency. Dynamic characteristics of the PLL0[1] Symbol Parameter Conditions Min Typ Max Unit Reference clock input Fin input frequency 32.768 kHz - 25 MHz 4.3 - 550 MHz 46 - 54 % 275 - 550 MHz 1 2 4 ns Clock output fo output frequency for PLL0 clkout output do output duty cycle for PLL0 clkout output fCCO CCO frequency [2] Lock detector output lock(PFD) [3] PFD lock criterion Dynamic parameters at fout = fCCO = 540 MHz; standard bandwidth settings Jrms-interval Jpp-period RMS interval jitter peak-to-peak, period jitter LPC546xx Product data sheet fref = 10 MHz [4][5] - 15 30 ps fref = 10 MHz [4][5] - 40 80 ps [1] Data based on characterization results, not tested in production. [2] Excluding under- and overshoot which may occur when the PLL is not in lock. [3] A phase difference between the inputs of the PFD (clkref and clkfb) smaller than the PFD lock criterion means lock output is HIGH. [4] Actual jitter dependent on amplitude and spectrum of substrate noise. [5] Input clock coming from a crystal oscillator with less than 250 ps peak-to-peak period jitter. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 111 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 11.7 USB PLL (PLL1) Table 33. PLL1 lock times and current Tamb = 40 C to +105 C, unless otherwise specified. VDD = 1.71 V to 3.6 V Symbol Parameter Conditions Min Typ Max Unit PLL1 configuration: input frequency 12 MHz; output frequency 48 MHz tlock(PLL1) IDD(PLL1) PLL1 lock time [1] - 7.4 - s PLL1 current [1][2] - 260 - A When locked [1] Data based on characterization results, not tested in production. [2] PLL current measured using lowest CCO frequency to obtain the desired output frequency. Table 34. Symbol Dynamic characteristics of the PLL1[1] Parameter Conditions Min Typ Max Unit 1 - 25 MHz 9.75 - 160 MHz 45 - 55 % 156 - 320 MHz Reference clock input input frequency Fin Clock output fo output frequency for PLL1 clkout output do output duty cycle for PLL1 clkout output fCCO CCO frequency [2] Dynamic parameters at fout = fCCO = 320 MHz; standard bandwidth settings Jpp-period peak-to-peak, period jitter fref = 4 MHz [3][4] - - 300 ps [1] Data based on simulation, not tested in production. [2] Excluding under- and overshoot which may occur when the PLL is not in lock. [3] Actual jitter dependent on amplitude and spectrum of substrate noise. [4] Input clock coming from a crystal oscillator with less than 250 ps peak-to-peak period jitter. 11.8 Audio PLL (PLL2) Table 35. PLL2 lock times and current Tamb = 40 C to +105 C, unless otherwise specified. VDD = 1.71 V to 3.6 V Symbol Parameter Conditions Min Typ Max Unit PLL2 configuration: input frequency 12 MHz; output frequency 100 MHz tlock(PLL2) IDD(PLL2) PLL2 lock time [1] - - 96 s PLL2 current [1][2] - - 2.0 mA when locked PLL2 configuration: input frequency 12 MHz; output frequency 100 MHz tlock(PLL2) IDD(PLL2) LPC546xx Product data sheet PLL2 lock time [1] - - 108 s PLL2 current [1][2] - - 1.6 mA when locked [1] Data based on characterization results, not tested in production. [2] PLL current measured using lowest CCO frequency to obtain the desired output frequency. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 112 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 36. Symbol Dynamic characteristics of the PLL2[1] Parameter Conditions Min Typ Max Unit 1 - 25 MHz 4.3 - 550 MHz 46 - 54 % 275 - 550 MHz 1 2 4 ns Reference clock input input frequency Fin Clock output fo output frequency for PLL2 clkout output do output duty cycle for PLL2 clkout output fCCO CCO frequency [2] Lock detector output lock(PFD) [3] PFD lock criterion Dynamic parameters at fout = fCCO = 540 MHz; standard bandwidth settings Jrms-interval Jpp-period RMS interval jitter peak-to-peak, period jitter fref = 10 MHz [4][5] - 15 30 ps fref = 10 MHz [4][5] - 40 80 ps [1] Data based on characterization results, not tested in production. [2] Excluding under- and overshoot which may occur when the PLL is not in lock. [3] A phase difference between the inputs of the PFD (clkref and clkfb) smaller than the PFD lock criterion means lock output is HIGH. [4] Actual jitter dependent on amplitude and spectrum of substrate noise. [5] Input clock coming from a crystal oscillator with less than 250 ps peak-to-peak period jitter. 11.9 FRO The FRO is trimmed to 1 % accuracy over the entire voltage and temperature range. Table 37. Dynamic characteristic: FRO Tamb = 40 C to +105 C; 1.71 V VDD 3.6 V. Symbol Parameter Conditions Min Typ[1] Max Unit fosc(RC) FRO clock frequency - 11.88 12 12.12 MHz fosc(RC) FRO clock frequency - 47.52 48 48.48 MHz fosc(RC) FRO clock frequency - 95.04 96 96.96 MHz [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. 11.10 Crystal oscillator Table 38. Dynamic characteristic: oscillator Tamb = 40 C to +105 C; 1.71 V VDD 3.6 V.[1] Symbol Parameter Min Typ[2] Max Unit - 13.2 - ps 10 MHz crystal - 6.6 - ps 15 MHz crystal - 4.8 - ps Conditions Low-frequency mode (1-20 MHz)[4] tjit(per) LPC546xx Product data sheet period jitter time 5 MHz crystal [3] All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 113 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 38. Dynamic characteristic: oscillator ...continued Tamb = 40 C to +105 C; 1.71 V VDD 3.6 V.[1] Symbol Parameter Conditions High-frequency mode (20 - 25 tjit(per) period jitter time Min Typ[2] Max Unit - 4.3 - ps - 3.7 - ps MHz)[5] 20 MHz crystal [3] 25 MHz crystal [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [3] Indicates RMS period jitter. [4] Select Low Frequency range = 0 in the SYSOSCCTRL register. [5] Select High Frequency = 1 in the SYSOSCCTRL register. 11.11 RTC oscillator See Section 13.5 for connecting the RTC oscillator to an external clock source. Table 39. Dynamic characteristic: RTC oscillator Tamb = 40 C to +105 C; 1.71 VDD 3.6[1] LPC546xx Product data sheet Symbol Parameter Conditions Min Typ[1] Max Unit fi input frequency - - 32.768 - kHz [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 114 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 11.12 Watchdog oscillator Table 40. Dynamic characteristics: Watchdog oscillator Tamb = 40 C to +105 C; 1.71 VDD 3.6[1] Symbol Parameter Conditions fosc(int) internal watchdog oscillator frequency Dclkout clkout duty cycle JPP-CC tstart Min [2] Typ[1] Max Unit 200 - 1500 kHz 48 - 52 % peak-peak period jitter [3][4] - 1 20 ns start-up time [4] - 4 - s LPC546xx Product data sheet [1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages. [2] The typical frequency spread over processing and temperature (Tamb = 40 C to +105 C) is 40 %. [3] Actual jitter dependent on amplitude and spectrum of substrate noise. [4] Guaranteed by design. Not tested in production samples. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 115 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 11.13 I2C-bus Table 41. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +105 C; 1.71 V VDD 3.6 V.[2] Symbol Parameter Conditions Min Max Unit fSCL SCL clock frequency Standard-mode 0 100 kHz Fast-mode 0 400 kHz Fast-mode Plus 0 1 MHz Both SDA and SCL signals - 300 ns Fast-mode 20 + 0.1 Cb 300 ns Fast-mode Plus [4][5][6][7] fall time tf Standard-mode tLOW tHIGH tHD;DAT tSU;DAT LOW period of the SCL clock HIGH period of the SCL clock [3][4][8] data hold time [9][10] data set-up time - 120 ns Standard-mode 4.7 - s Fast-mode 1.3 - s Fast-mode Plus 0.5 - s Standard-mode 4.0 - s Fast-mode 0.6 - s Fast-mode Plus 0.26 - s Standard-mode 0 - s Fast-mode 0 - s Fast-mode Plus 0 - s Standard-mode 250 - ns Fast-mode 100 - ns Fast-mode Plus 50 - ns [1] Guaranteed by design. Not tested in production. [2] Parameters are valid over operating temperature range unless otherwise specified. See the I2C-bus specification UM10204 for details. [3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. [4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. [5] Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed. [6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. [7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. [8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. [9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge. [10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 116 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller tf SDA tSU;DAT 70 % 30 % 70 % 30 % tHD;DAT tf 70 % 30 % SCL tVD;DAT tHIGH 70 % 30 % 70 % 30 % 70 % 30 % tLOW S 1 / fSCL 002aaf425 Fig 25. I2C-bus pins clock timing LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 117 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 11.14 I2S-bus interface Table 42. Dynamic characteristics: I2S-bus interface pins [1][4] Tamb = 40 C to 105 C; VDD = 1.71 V to 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1.0 ns, SLEW setting = standard mode for all pins; Parameters sampled at the 50 % level of the rising or falling edge. Symbol Parameter Conditions Min Typ[3] Max Unit Common to master and slave tWH tWL on pins I2Sx_TX_SCK and I2Sx_RX_SCK[5] pulse width HIGH CCLK 100 MHz (Tcyc/2) -1 - (Tcyc/2) +1 ns CCLK > 100 MHz (Tcyc/2) -1 - (Tcyc/2) +1 ns on pins I2Sx_TX_SCK and I2Sx_RX_SCK[5] pulse width LOW CCLK 100 MHz (Tcyc/2) -1 - (Tcyc/2) +1 ns CCLK > 100 MHz (Tcyc/2) -1 - (Tcyc/2) +1 ns CCLK 100 MHz 26.0 - 40.3 ns CCLK > 100 MHz 25.0 - 39.0 ns 26.0 - 41.0 ns 25.0 - 39.6 ns Master; 1.71 V VDD 2.7 V tv(Q) data output valid time on pin I2Sx_TX_SDA [2] on pin I2Sx_WS CCLK 100 MHz CCLK > 100 MHz tsu(D) th(D) data input set-up time on pin I2Sx_RX_SDA data input hold time [2] CCLK 100 MHz 0 - - ns CCLK > 100 MHz 0 - - ns CCLK 100 MHz 6.1 - - ns CCLK > 100 MHz 6.4 - - ns 18.8 - 37.1 ns 18.0 - 35.5 ns CCLK 100 MHz 4.8 - - ns CCLK > 100 MHz 4.4 - - ns 0 - - ns 0 - - ns on pin I2Sx_RX_SDA [2] Slave; 1.71 V VDD 2.7 V tv(Q) data output valid time on pin I2Sx_TX_SDA [2] CCLK 100 MHz CCLK > 100 MHz tsu(D) data input set-up time on pin I2Sx_RX_SDA [2] on pin I2Sx_WS CCLK 100 MHz CCLK > 100 MHz th(D) data input hold time on pin I2Sx_RX_SDA [2] CCLK 100 MHz 0 - - ns CCLK > 100 MHz 0 - - ns CCLK 100 MHz 3.2 - - ns CCLK > 100 MHz 3.2 - - ns on pin I2Sx_WS LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 118 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 42. Dynamic characteristics: I2S-bus interface pins [1][4] Tamb = 40 C to 105 C; VDD = 1.71 V to 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1.0 ns, SLEW setting = standard mode for all pins; Parameters sampled at the 50 % level of the rising or falling edge. Symbol Parameter Min Typ[3] Max Unit CCLK 100 MHz 21.4 - 30.4 ns CCLK > 100 MHz 20.6 - 28.7 ns 21.1 - 29 ns 20.3 - 28.3 ns Conditions Master; 2.7 V VDD 3.6 V tv(Q) data output valid time on pin I2Sx_TX_SDA [2] on pin I2Sx_WS CCLK 100 MHz CCLK > 100 MHz tsu(D) th(D) data input set-up time on pin I2Sx_RX_SDA data input hold time [2] CCLK 100 MHz 1.3 - - ns CCLK > 100 MHz 1.0 - - ns CCLK 100 MHz 2.9 - - ns CCLK > 100 MHz 3.3 - - ns 13.8 - 23.6 ns 13 - 21.9 ns CCLK 100 MHz 4.7 - - ns CCLK > 100 MHz 4.2 - - ns 0.9 - - ns 0.7 - - ns on pin I2Sx_RX_SDA [2] Slave; 2.7 V VDD 3.6 V tv(Q) data output valid time on pin I2Sx_TX_SDA [2] CCLK 100 MHz CCLK > 100 MHz tsu(D) data input set-up time on pin I2Sx_RX_SDA [2] on pin I2Sx_WS CCLK 100 MHz CCLK > 100 MHz th(D) data input hold time on pin I2Sx_RX_SDA [2] CCLK 100 MHz 0 - - ns CCLK > 100 MHz 0 - - ns CCLK 100 MHz 1.5 - - ns CCLK > 100 MHz 1.3 - - ns on pin I2Sx_WS LPC546xx Product data sheet [1] Based on characterization; not tested in production. [2] Clock Divider register (DIV) = 0x0. [3] Typical ratings are not guaranteed. [4] The Flexcomm Interface function clock frequency should not be above 48 MHz. See the data rates section in the I2S chapter (UM10912) to calculate clock and sample rates. [5] Based on simulation. Not tested in production. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 119 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Tcy(clk) tf tr I2Sx_SCK tWH tWL I2Sx_TX_SDA tv(Q) I2Sx_RX_SDA tsu(D) th(D) I2Sx_WS tv(Q) aaa-026799 Fig 26. I2S-bus timing (master) Tcy(clk) tf tr I2Sx_SCK tWH tWL I2Sx_TX_SDA tv(Q) I2Sx_RX_SDA tsu(D) th(D) I2Sx_WS tsu(D) th(D) aaa-026800 Fig 27. I2S-bus timing (slave) LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 120 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 11.15 SPI interfaces The actual SPI bit rate depends on the delays introduced by the external trace, the external device, system clock (CCLK), and capacitive loading. Excluding delays introduced by external device and PCB, the maximum supported bit rate for SPI master mode is 71 Mbit/s, and the maximum supported bit rate for SPI slave mode is 14 Mbit/s. Table 43. SPI dynamic characteristics[1] Tamb = 40 C to 105 C; 1.71 V VDD 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting = standard mode for all pins;. Parameters sampled at the 50 % level of the rising or falling edge. Symbol Parameter Conditions Min Typ Max Unit CCLK 100 MHz 2.2 - - ns CCLK > 100 MHz 1.9 - - ns CCLK 100 MHz 6.3 - - ns CCLK > 100 MHz 6.7 - - ns CCLK 100 MHz 2.6 - 5.0 ns CCLK > 100 MHz 0.3 - 4.7 ns CCLK 100 MHz 1.1 - - ns CCLK > 100 MHz 0.9 - - ns SPI master 1.71 V VDD 2.7 V tDS data set-up time tDH data hold time tv(Q) data output valid time SPI slave 1.71 V VDD 2.7 V tDS tDH tv(Q) data set-up time data hold time data output valid time CCLK 100 MHz 2.1 - - ns CCLK > 100 MHz 2.2 - - ns CCLK 100 MHz 18.8 - 37.0 ns CCLK > 100 MHz 18.0 - 36.0 ns CCLK 100 MHz 2.4 - - ns CCLK > 100 MHz 2.2 - - ns CCLK 100 MHz 4.2 - - ns CCLK > 100 MHz 4.5 - - ns CCLK 100 MHz 1.8 - 4.6 ns CCLK > 100 MHz 1.7 - 4.0 ns SPI master 2.7 V VDD 3.6 V tDS data set-up time tDH data hold time tv(Q) data output valid time SPI slave 2.7 V VDD 3.6 V tDS tDH tv(Q) data set-up time data hold time data output valid time [1] LPC546xx Product data sheet CCLK 100 MHz 1.2 - - ns CCLK > 100 MHz 1.0 - - ns CCLK 100 MHz 0 - - ns CCLK > 100 MHz 0 - - ns CCLK 100 MHz 14 - 23.9 ns CCLK > 100 MHz 13.3 - 22.2 ns Based on characterization; not tested in production. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 121 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) SSEL MOSI (CPHA = 0) tv(Q) tv(Q) DATA VALID (MSB) DATA VALID DATA VALID (MSB) MOSI (CPHA = 1) IDLE DATA VALID (MSB) DATA VALID (LSB) IDLE DATA VALID (MSB) tDH tDS MISO (CPHA = 0) DATA VALID (LSB) DATA VALID tv(Q) tv(Q) DATA VALID (LSB) DATA VALID tDS MISO (CPHA = 1) DATA VALID (LSB) DATA VALID (MSB) IDLE DATA VALID (MSB) DATA VALID (MSB) IDLE DATA VALID (MSB) tDH DATA VALID aaa-014969 Fig 28. SPI master timing LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 122 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) SSEL MISO (CPHA = 0) tv(Q) tv(Q) DATA VALID (MSB) DATA VALID DATA VALID (MSB) MISO (CPHA = 1) IDLE DATA VALID (MSB) DATA VALID (LSB) IDLE DATA VALID (MSB) tDH tDS MOSI (CPHA = 0) DATA VALID (LSB) DATA VALID tv(Q) tv(Q) DATA VALID (LSB) DATA VALID tDS MOSI (CPHA = 1) DATA VALID (LSB) DATA VALID (MSB) IDLE DATA VALID (MSB) DATA VALID (MSB) IDLE DATA VALID (MSB) tDH DATA VALID aaa-014970 Fig 29. SPI slave timing LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 123 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 11.16 SPIFI The actual SPIFI bit rate depends on the delays introduced by the external trace, the external device, system clock (CCLK), and capacitive loading. Excluding delays introduced by external device and PCB, the maximum supported bit rate for SPIFI mode is 100 Mbit/s. Table 44. Dynamic characteristics: SPIFI[1] Tamb = 40 C to 105 C; VDD = 1.71 V to 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW set to standard mode for all pins; Parameters sampled at the 50 % level of the rising or falling edge. Symbol Parameter Conditions Min Typ Max Unit CCLK 100 MHz 4 - - ns CCLK > 100 MHz 4 - - ns CCLK 100 MHz 6.4 - - ns CCLK > 100 MHz 6.6 - - ns CCLK 100 MHz 5.7 - 13.7 ns CCLK > 100 MHz 5.7 - 13.7 ns CCLK 100 MHz 4 - - ns CCLK > 100 MHz 4 - - ns SPIFI 1.71 V VDD 2.7 V tDS data set-up time tDH data hold time tv(Q) data output valid time SPIFI 2.7 V VDD 3.6 V tDS tDH tv(Q) data set-up time data hold time data output valid time [1] CCLK 100 MHz 3.5 - - ns CCLK > 100 MHz 3.6 - - ns CCLK 100 MHz 3.3 - 11.5 ns CCLK > 100 MHz 3.3 - 11.5 ns Based on simulation; not tested in production. Tcy(clk) SPIFI_SCK tv(Q) SPIFI data out DATA VALID th(Q) DATA VALID tDS SPIFI data in DATA VALID tDH DATA VALID 002aah409 In mode 0, MODE3 bit (23) in SPIFI CTRL register is set to '0' (default). The SPIFI drives SCK low after the rising edge at which the last bit of each command is captured, and keeps it LOW while CS is HIGH. Fig 30. SPIFI control register (Mode 0) LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 124 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 11.17 DMIC subsystem Table 45. Dynamic characteristics[1] Tamb = 40 C to 105 C; VDD = 2.7 V to 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW set to standard mode for all pins; Bypass bit = 0; Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Symbol Parameter Conditions Min Typ Max Unit tDS data set-up time CCLK 100 MHz 14.3 - - ns CCLK > 100 MHz 14.3 - - ns CCLK 100 MHz 0 - - ns CCLK > 100 MHz 0 - - ns tDH data hold time [1] Based on simulated values. CLOCK tSU tDH DATA aaa-017025 Fig 31. DMIC timing diagram LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 125 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 11.18 Smart card interface Table 46. Dynamic characteristics[1] Tamb = 40 C to 105 C; VDD = 1.71 V to 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting = standard mode for all pins; Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Symbol Parameter Conditions Min Typ Max Unit CCLK 100 MHz 2.1 - - ns CCLK > 100 MHz 2.1 - - ns 2.7 V VDD 3.6 V tDS tDH tv(Q) data set-up time CCLK 100 MHz 0 - - ns CCLK > 100 MHz 0 - - ns data output valid time CCLK 100 MHz 11.0 - 22.5 ns CCLK > 100 MHz 11.0 - 22.5 ns data hold time [1] LPC546xx Product data sheet Based on simulated values. VDD = 2.7 V - 3.6 V. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 126 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 11.19 USART interface The actual USART bit rate depends on the delays introduced by the external trace, the external device, system clock (CCLK), and capacitive loading. Excluding delays introduced by external device and PCB, the maximum supported bit rate for USART master synchronous mode is 24 Mbit/s, and the maximum supported bit rate for USART slave synchronous mode is 12.5 Mbit/s. Table 47. USART dynamic characteristics[1] Tamb = 40 C to 105 C; VDD = 1.71 V to 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting = standard mode for all pins; Parameters sampled at the 50 % level of the rising or falling edge. Symbol Parameter Conditions Min Typ Max Unit CCLK 100 MHz 21.2 - - ns CCLK > 100 MHz 19.7 - - ns USART master (in synchronous mode) 1.71 V VDD 2.7 V tsu(D) th(D) tv(Q) data input set-up time data input hold time data output valid time CCLK 100 MHz 0 - - ns CCLK > 100 MHz 0 - - ns CCLK 100 MHz 0 - 4.9 ns CCLK > 100 MHz 0 - 4.5 ns CCLK 100 MHz 1.7 - - ns CCLK > 100 MHz 1.5 - - ns - - ns USART slave (in synchronous mode)1.71 V VDD 2.7 V tsu(D) data input set-up time th(D) data input hold time CCLK 100 MHz 1.2 CCLK > 100 MHz 1.4 - - ns tv(Q) data output valid time CCLK 100 MHz 20.2 - 39.5 ns CCLK > 100 MHz 19.3 - 37.7 ns USART master (in synchronous mode) 2.7 V VDD 3.6 V tsu(D) data input set-up time CCLK 100 MHz 20.5 - - ns CCLK > 100 MHz 18.9 - - ns ns th(D) data input hold time CCLK 100 MHz 0 - - CCLK > 100 MHz 0 - - ns tv(Q) data output valid time CCLK 100 MHz 1.5 - 3.6 ns CCLK > 100 MHz 1.3 - 3.2 ns USART slave (in synchronous mode) 2.7 V VDD 3.6 V tsu(D) data input set-up time CCLK 100 MHz 1.2 - - ns CCLK > 100 MHz 1 - - ns th(D) data input hold time CCLK 100 MHz 0 - - ns CCLK > 100 MHz 0 - - ns CCLK 100 MHz 15.2 - 26.1 ns CCLK > 100 MHz 14.3 - 24.2 ns tv(Q) data output valid time [1] LPC546xx Product data sheet Based on characterization; not tested in production. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 127 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Tcy(clk) Un_SCLK (CLKPOL = 0) Un_SCLK (CLKPOL = 1) tv(Q) tvQ) START TXD BIT0 BIT1 tsu(D) th(D) START RXD BIT1 BIT0 aaa-015074 Fig 32. USART timing 11.20 SCTimer/PWM output timing Table 48. SCTimer/PWM output dynamic characteristics Tamb = 40 C to 105 C; 1.71 V VDD 3.6 V CL = 30 pF. Simulated skew (over process, voltage, and temperature) of any two SCT fixed-pin output signals; sampled at the 90 % and 10 % level of the rising or falling edge; values guaranteed by design. Symbol Parameter Conditions Min Typ Max Unit tsk(o) output skew time - 3.4 - 4.5 ns 11.21 USB interface characteristics Table 49. Dynamic characteristics: USB0 pins (full-speed) CL = 50 pF; Rpu = 1.5 k on D+ to VDD, unless otherwise specified; 3.0 V VDD 3.6 V. Symbol Parameter Conditions Min Typ Max Unit tr rise time 10 % to 90 % 4.0 20 ns tf fall time 10 % to 90 % 4.0 20 ns tFRFM differential rise and fall time matching tr / tf 90 111.11 % VCRS output signal crossover voltage 1.3 2.0 V tFEOPT source SE0 interval of EOP see Figure 33 160 175 ns tFDEOP source jitter for differential transition to SE0 transition see Figure 33 2 +5 ns tJR1 receiver jitter to next transition 18.5 +18.5 ns tJR2 receiver jitter for paired transitions 10 % to 90 % 9 - tEOPR1 EOP width at receiver must reject as EOP; see Figure 33 [1] 40 - tEOPR2 EOP width at receiver must accept as EOP; see Figure 33 [1] 82 - [1] +9 ns ns - ns Characterized but not implemented as production test. Guaranteed by design. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 128 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 11.22 TPERIOD crossover point extended crossover point differential data lines source EOP width: tFEOPT differential data to SE0/EOP skew n x TPERIOD + tFDEOP receiver EOP width: tEOPR1, tEOPR2 002aab561 Fig 33. Differential data-to-EOP transition skew and EOP width 11.23 Ethernet AVB Remark: The timing characteristics of the ENET_MDC and ENET_MDIO signals comply with the IEEE standard 802.3. Table 50. Dynamic characteristics: Ethernet Tamb = 40 C to 105 C, VDD = 2.7 V to 3.6 V. CL = 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting = standard mode for all pins; Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Based on simulation. Symbol Parameter Conditions Min Typ Max fclk clock frequency for ENET_RX_CLK clk clock duty cycle tsu data input set-up time Unit [1] - - 50.0 MHz [1] 45.0 - 55.0 % 4.4 - - ns 4.4 - - ns 1.3 - 0 ns 1.3 - 0 ns CCLK 100 MHz 9.9 - 17.3 ns CCLK > 100 MHz 9.9 - 17.3 ns [1] - - 25.0 MHz clock duty cycle [1] 45.0 - 55.0 % fclk clock frequency [1] - - 25.0 MHz clk clock duty cycle [1] 45.0 - 55.0 % tsu data input set-up time CCLK 100 MHz 4.7 - - ns CCLK > 100 MHz 4.7 - - ns RMII mode ENET_RXDn, ENET_RX_ER, ENET_RX_DV [1][2] CCLK 100 MHz CCLK > 100 MHz th data input hold time for ENET_RXDn, ENET_RX_ER, ENET_RX_DV [1][2] CCLK 100 MHz CCLK > 100 MHz tv(Q) data output valid time for ENET_TXDn, ENET_TX_EN [1][2] MII mode fclk clk clock frequency LPC546xx Product data sheet for ENET_TX_CLK for ENET_RX_CLK for ENET_RXDn, ENET_RX_ER, ENET_RX_DV [1][2] All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 129 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 50. Dynamic characteristics: Ethernet Tamb = 40 C to 105 C, VDD = 2.7 V to 3.6 V. CL = 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting = standard mode for all pins; Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Based on simulation. Symbol th Parameter Conditions Min Typ Max Unit 1.2 - 0 ns 1.2 - 0 ns CCLK 100 MHz 10.0 - 18.2 ns CCLK > 100 MHz 10.0 - 18.2 ns [1][2] data input hold time for ENET_RXDn, ENET_RX_ER, ENET_RX_DV CCLK 100 MHz CCLK > 100 MHz tv(Q) data output valid time [1][2] for ENET_TXDn, ENET_TX_EN, ENET_TX_ER [1] Output drivers can drive a load 25 pF accommodating over 12 inch of PCB trace and the input capacitance of the receiving device. [2] Timing values are given from the point at which the clock signal waveform crosses 1.4 V to the valid input or output level. ENET_RX_CLK tv(Q) ENET_TX_EN ENET_TXDn tsu th ENET_RXDn ENET_RX_DV aaa-025108 Fig 34. Ethernet RMII timing ENET_RX_CLK tsu th ENET_RXDn ENET_RX_DV ENET_RX_ER ENET_TX_CLK tv(Q) ENET_TX_EN ENET_TXDn aaa-025109 Fig 35. Ethernet MII timing LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 130 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 11.24 SD/MMC and SDIO Table 51. Dynamic characteristics: SD/MMC and SDIO Tamb = 40 C to +105 C, VDD = 2.7 V to 3.6 V; CL = 20 pF. SAMPLE_DELAY = 0, DRV_DELAY = 0 in the SDDELAY register, SDIOCLKCTRL = 0x84, sampled at 90 % and 10 % of the signal level, SLEW = 1 ns for SD_CLK pin, SLEW = 1 ns for SD_DATn and SD_CMD pins. Simulated values in high-speed mode. Symbol Parameter Conditions Min Typ Max Unit fclk clock frequency on pin SD_CLK; data transfer mode - - 50 MHz tsu(D) data input set-up time on pins SD_DATn as inputs CCLK 100 MHz 14.4 - - ns CCLK > 100 MHz 14.4 - - ns CCLK 100 MHz 14.4 - - ns CCLK > 100 MHz 14.4 - - ns CCLK 100 MHz 1.5 - - ns CCLK > 100 MHz 1.5 - - ns CCLK 100 MHz 1.5 - - ns CCLK > 100 MHz 1.5 - - ns on pins SD_CMD as inputs th(D) data input hold time on pins SD_DATn as inputs on pins SD_CMD as inputs tv(Q) data output valid time on pins SD_DATn as outputs CCLK 100 MHz 1.9 - 3.5 ns CCLK > 100 MHz 1.9 - 3.5 ns CCLK 100 MHz 1.9 - 3.5 ns CCLK > 100 MHz 1.9 - 3.5 ns on pins SD_CMD as outputs Tcy(clk) SD_CLK td(QV) th(Q) SD_CMD (O) SD_DATn (O) tsu(D) th(D) SD_CMD (I) SD_DATn (I) 002aag204 Fig 36. SD/MMC and SDIO timing LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 131 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 11.25 LCD Table 52. Dynamic characteristics: LCD Tamb = 40 C to 105 C; VDD = 2.7 V to 3.6 V; CL = 30 pF. Simulated values. Symbol Parameter Conditions Min Typ Max Unit fclk clock frequency on pin LCD_DCLK - - 50 MHz tv(Q) data output valid time on all LCD output pins CCLK 100 MHz 0.9 - 1.6 ns CCLK > 100 MHz 0.9 - 1.6 ns LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 132 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 12. Analog characteristics 12.1 BOD Table 53. BOD static characteristics Tamb = 25 C; based on characterization; not tested in production. Symbol Parameter Conditions Vth threshold voltage interrupt level 0 Min Typ Max Unit assertion 1.5 - 1.63 V de-assertion 1.55 - 1.69 V assertion 1.5 - 1.62 V de-assertion 1.55 - 1.69 V reset level 0 Vth threshold voltage interrupt level 1 assertion 1.54 - 1.68 V de-assertion 1.6 - 1.75 V assertion 1.55 - 1.68 V de-assertion 1.61 - 1.74 V assertion 1.79 - 1.95 V de-assertion 1.85 - 2.02 V assertion 2.04 - 2.21 V de-assertion 2.19 - 2.38 V reset level 1 Vth threshold voltage interrupt level 2 reset level 2 Vth threshold voltage interrupt level 3 assertion 2.62 - 2.86 V de-assertion 2.77 - 3.03 V assertion 2.62 - 2.85 V de-assertion 2.78 - 3.02 V reset level 3 LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 133 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 12.2 12-bit ADC characteristics Table 54. 12-bit ADC static characteristics Tamb = 40 C to +105 C; 1.71 V VDD 3.6 V; VSSA = VREFN = GND. ADC calibrated at Tamb = 25C. Min Typ[2] Max Unit [3] 0 - VDDA V [4] - 5.0 - pF - 80 MHz - - 5.0 Msamples/s [1][5] - 3.0 - LSB [1][5] - 4.5 - LSB [1][5] - - LSB 2.0 V VDDA 3.6 V 2.0 V < VREFP 3.6 V fclk(ADC) = 80 MHz [1][6] - 4.0 - LSB 1.71 V VDDA 2.0 V 1.71 V VREFP 2.0 V fclk(ADC) = 80 MHz [1][6] - 7.5 - LSB [1][6] - Symbol Parameter Conditions VIA analog input voltage Cia analog input capacitance fclk(ADC) ADC clock frequency fs sampling frequency ED differential linearity 2.0 V VDDA 3.6 V error 2.0 V < VREFP 3.6 V fclk(ADC) = 80 MHz 1.71 V VDDA 2.0 V 1.71 V VREFP 2.0 V fclk(ADC) = 80 MHz EL(adj) integral non-linearity - LSB EO offset error calibration enabled [1][7] - 2.2 - mV Verr(FS) full-scale error voltage 2.0 V VDDA 3.6 V 2.0 V < VREFP 3.6 V fclk(ADC) = 80 MHz [1][8] - 3.0 - LSB - 2.5 - LSB 17.0 - - k 1.71 V VDDA 2.0 V 1.71 V VREFP 2.0 V fclk(ADC) = 80 MHz Zi input impedance LPC546xx Product data sheet fs = 5.0 Msamples/s [9][10] [1] Based on characterization; not tested in production. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [3] The input resistance of ADC channels 6 to 11 is higher than ADC channels 0 to 5. [4] Cia represents the external capacitance on the analog input channel for sampling speeds of 5.0 Msamples/s. No parasitic capacitances included. [5] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 37. [6] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 37. [7] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 37. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 134 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller [8] The full-scale error voltage or gain error (EG) is the difference between the straight-line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 37. [9] Tamb = 25 C; maximum sampling frequency fs = 5.0 Msamples/s and analog input capacitance Cia = 5 pF. [10] Input impedance Zi is inversely proportional to the sampling frequency and the total input capacity including Cia and Cio: Zi 1 / (fs Ci). See Table 21 for Cio. See Figure 38. offset error EO gain error EG 4095 4094 4093 4092 4091 4090 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095 4096 VIA (LSBideal) offset error EO 1 LSB = VREFP - VREFN 4096 aaa-016908 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve. Fig 37. 12-bit ADC characteristics LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 135 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 55. ADC sampling times[1] -40 C Tamb <= 85 C; 1.71 V VDDA 3.6 V; 1.71 V VDD 3.6 V Symbol Parameter Conditions Min Typ Max Unit 20 - - ns 0.05 k <= Zo < 0.1 k 23 - - ns 0.1 k <= Zo < 0.2 k 26 - - ns 0.2 k <= Zo < 0.5 k 31 - - ns 0.5 k <= Zo < 1 k 47 - - ns 1 k <= Zo < 5 k 75 - - ns 15 - - ns 0.05 k <= Zo < 0.1 k 18 - - ns 0.1 k <= Zo < 0.2 k 20 - - ns 0.2 k <= Zo < 0.5 k 24 - - ns 0.5 k <= Zo < 1 k 38 - - ns 1 k <= Zo < 5 k 62 - - ns ADC inputs ADC_5 to ADC_0 (fast channels); ADC resolution = 12 bit ts sampling time [3] Zo < 0.05 k ADC inputs ADC_5 to ADC_0 (fast channels); ADC resolution = 10 bit ts sampling time [3] Zo < 0.05 k ADC inputs ADC_5 to ADC_0 (fast channels); ADC resolution = 8 bit ts sampling time [3] Zo < 0.05 k 12 - - ns 0.05 k <= Zo < 0.1 k 13 - - ns 0.1 k <= Zo < 0.2 k 15 - - ns 0.2 k <= Zo < 0.5 k 19 - - ns 0.5 k <= Zo < 1 k 30 - - ns 1 k <= Zo < 5 k 48 - - ns 9 - - ns ADC inputs ADC_5 to ADC_0 (fast channels); ADC resolution = 6 bit ts sampling time [3] Zo < 0.05 k 0.05 k <= Zo < 0.1 k 10 - - ns 0.1 k <= Zo < 0.2 k 11 - - ns 0.2 k <= Zo < 0.5 k 13 - - ns 0.5 k <= Zo < 1 k 22 - - ns 1 k <= Zo < 5 k 36 - - ns 43 - - ns 0.05 k <= Zo < 0.1 k 46 - - ns 0.1 k <= Zo < 0.2 k 50 - - ns 0.2 k <= Zo < 0.5 k 56 - - ns 0.5 k <= Zo < 1 k 74 - - ns 1 k <= Zo < 5 k 105 - - ns ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 12 bit ts sampling time LPC546xx Product data sheet [3] Zo < 0.05 k All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 136 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 55. ADC sampling times[1] ...continued -40 C Tamb <= 85 C; 1.71 V VDDA 3.6 V; 1.71 V VDD 3.6 V Symbol Parameter Conditions Min Typ Max Unit ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 10 bit ts sampling time [3] Zo < 0.05 k 35 - - ns 0.05 k <= Zo < 0.1 k 38 - - ns 0.1 k <= Zo < 0.2 k 40 - - ns 0.2 k <= Zo < 0.5 k 46 - - ns 0.5 k <= Zo < 1 k 61 - - ns 1 k <= Zo < 5 k 86 - - ns 27 - - ns ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 8 bit ts sampling time [3] Zo < 0.05 k 0.05 k <= Zo < 0.1 k 29 - - ns 0.1 k <= Zo < 0.2 k 32 - - ns 0.2 k <= Zo < 0.5 k 36 - - ns 0.5 k <= Zo < 1 k 48 - - ns 1 k <= Zo < 5 k 69 - - ns 20 - - ns 0.05 k <= Zo < 0.1 k 22 - - ns 0.1 k <= Zo < 0.2 k 23 - - ns 0.2 k <= Zo < 0.5 k 26 - - ns 0.5 k <= Zo < 1 k 36 - - ns 1 k <= Zo < 5 k 51 - - ns ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 6 bit ts sampling time [3] Zo < 0.05 k [1] Characterized through simulation. Not tested in production. [2] The ADC default sampling time is 2.5 ADC clock cycles. To match a given analog source output impedance, the sampling time can be extended by adding up to seven ADC clock cycles for a maximum sampling time of 9.5 ADC clock cycles. See the TSAMP bits in the ADC CTRL register. [3] Zo = analog source output impedance. [4] For VDD 2.5 V, add one additional clock cycle to the values in Table 55. 12.2.1 ADC input impedance Figure 38 shows the ADC input impedance. In this figure: * * * * ADCx represents slow ADC input channels 6 to 11. ADCy represents fast ADC input channels 0 to 5. R1 and Rsw are the switch-on resistance on the ADC input channel. If fast channels (ADC inputs 0 to 5) are selected, the ADC input signal goes through Rsw to the sampling capacitor (Cia). * If slow channels (ADC inputs 6 to 11) are selected, the ADC input signal goes through R1 + Rsw to the sampling capacitor (Cia). * Typical values, R1 = 487 , Rsw = 278 * See Table 21 for Cio. * See Table 54 for Cia. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 137 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller ADC R1 ADCx Cia Cio Rsw ADCy DAC Cio aaa-017600 Fig 38. ADC input impedance 12.3 Temperature sensor Table 56. Temperature sensor static and dynamic characteristics VDD = VDDA = 1.71 V to 3.6 V Symbol Parameter Conditions DTsen sensor temperature accuracy Tamb = 40 C to +105 C EL linearity error Tamb = 40 C to +105 C ts(pu) LPC546xx Product data sheet power-up settling time to 99% of temperature sensor output value [1] Absolute temperature accuracy. [2] Based on simulation. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 Min [1] [2] Typ - Max Unit 3.7 C - - 3.7 C - 10.0 15.0 s (c) NXP Semiconductors N.V. 2017. All rights reserved. 138 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 57. Temperature sensor Linear-Least-Square (LLS) fit parameters VDD = VDDA = 1.71 V to 3.6 V Fit parameter Range Min Typ Max Unit LLS slope Tamb = 40 C to +105 C [1] - 2.04 - mV/C LLS intercept at 0 C Tamb = 40 C to +105 C [1] - 584.0 - mV [2] 515.9 - 531.5 mV Value at 30 C [1] Measured over typical samples. [2] Measured for samples over process corners. DDD 9R P9 //6ILW 7HPSHUDWXUH & VDD = VDDA 3.3 V; measured on matrix samples. Fig 39. LLS fit of the temperature sensor output voltage LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 139 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 13. Application information 13.1 Start-up behavior Figure 40 shows the start-up timing after reset. The FRO 12 MHz oscillator provides the default clock at Reset and provides a clean system clock shortly after the supply pins reach operating voltage. FRO starts FRO status internal reset VDD valid threshold = 1.71 V ta s tb s GND boot time supply ramp-up time user code tc s processor status boot code execution finishes; user code starts aaa-024049 Fig 40. Start-up timing Table 58. LPC546xx Product data sheet Typical start-up timing parameters Parameter Description Value ta FRO start time 20 s tb Internal reset de-asserted 151 s tc Legacy image 262 s Single image without CRC 245 s Dual image without CRC 289 s All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 140 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 13.2 Standard I/O pin configuration Figure 41 shows the possible pin modes for standard I/O pins: * * * * * Digital output driver: enabled/disabled. Digital input: Pull-up enabled/disabled. Digital input: Pull-down enabled/disabled. Digital input: Repeater mode enabled/disabled. Z mode; High impedance (no cross-bar currents for floating inputs). The default configuration for standard I/O pins is Z mode. The weak MOS devices provide a drive capability equivalent to pull-up and pull-down resistors. VDD ESD enable output driver data output from core PIN slew rate bit SLEW input buffer enable bit EZI data input to core GLITCH FILTER filter select bit ZIF pull-up enable bit EPUN ESD pull-down enable bit EPD analog I/O VSS aaa-015595 The glitch filter rejects pulses of typical 12 ns width. Fig 41. Standard I/O and RESET pin configuration LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 141 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 13.3 Connecting power, clocks, and debug functions Figure 42 shows the basic board connections used to power the LPC546xx devices, connect the external crystal and the 32 kHz oscillator for the RTC, and provide debug capabilities via the serial wire port. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 142 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 3.3 V 3.3 V SWD connector (4) ~10 k - 100 k (6) XTALIN SWDIO/PIO0_12 1 C1 2 (1) 3.3 V C2 XTALOUT DGND ~10 k - 100 k 3 SWCLK/PIO0_11 4 (6) n.c. 5 6 n.c. 7 8 n.c. 9 10 RTCXIN C3 (1) C4 RTCXOUT DGND RESETN VSS (2) VDD DGND 3.3 V 0.1 F DGND 0.01 F VSSA DGND LPC546xx AGND (3) VDDA PIO0_4 ISP select pins 3.3 V 10 F 0.1 F PIO0_5 DGND PIO0_6 (5) ADCx (3) VREFP 3.3 V 0.1 F 10 F 0.1 F VREFN AGND AGND (7) VBAT 3.3 V 0.1 F AGND DGND DGND aaa-026743 (1) See Section 13.6 "XTAL oscillator" for the values of C1, C2, C3, and C4. (2) Position the decoupling capacitors of 0.1 F and 0.01 F as close as possible to the VDD pin. Add one set of decoupling capacitors to each VDD pin. (3) Position the decoupling capacitors of 0.1 F as close as possible to the VREFN and VDDA pins. The 10 F bypass capacitor filters the power line. Tie VDDA and VREFP to VDD if the ADC is not used. Tie VREFN to VSS if ADC is not used. (4) Uses the ARM 10-pin interface for SWD. (5) When measuring signals of low frequency, use a low-pass filter to remove noise and to improve ADC performance. Also see Ref. 3. (6) External pull-up resistors on SWDIO and SWCLK pins are optional because these pins have an internal pull-up enabled by default. (7) Position the decoupling capacitor of 0.1 F as close as possible to the VBAT pin. Tie VBAT to VDD if not used. Fig 42. Power, clock, and debug connections LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 143 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 13.4 I/O power consumption I/O pins are contributing to the overall dynamic and static power consumption of the part. If pins are configured as digital inputs, a static current can flow depending on the voltage level at the pin and the setting of the internal pull-up and pull-down resistors. This current can be calculated using the parameters Rpu and Rpd given in Table 21 for a given input voltage VI. For pins set to output, the current drive strength is given by parameters IOH and IOL in Table 21, but for calculating the total static current, you also need to consider any external loads connected to the pin. I/O pins also contribute to the dynamic power consumption when the pins are switching because the VDD supply provides the current to charge and discharge all internal and external capacitive loads connected to the pin in addition to powering the I/O circuitry. The contribution from the I/O switching current Isw can be calculated as follows for any given switching frequency fsw if the external capacitive load (Cext) is known (see Table 21 for the internal I/O capacitance): Isw = VDD x fsw x (Cio + Cext) LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 144 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 13.5 RTC oscillator In the RTC oscillator circuit, only the crystal (XTAL) and the capacitances CX1 and CX2 need to be connected externally on RTCXIN and RTCXOUT. See Figure 43. LPC546xx L RTCXIN RTCXOUT = CL CP XTAL RS CX1 CX2 aaa-025723 Fig 43. RTC oscillator components For best results, it is very critical to select a matching crystal for the on-chip oscillator. Load capacitance (CL), series resistance (RS), and drive level (DL) are important parameters to consider while choosing the crystal. After selecting the proper crystal, the external load capacitor CX1 and CX2 values can also be generally determined by the following expression: CX1 = CX2 = 2CL (CPad + CParasitic) Where: CL - Crystal load capacitance CPad - Pad capacitance of the RTCXIN and RTCXOUT pins (~3 pF). CParasitic - Parasitic or stray capacitance of external circuit. Although CParasitic can be ignored in general, the actual board layout and placement of external components influences the optimal values of external load capacitors. Therefore, it is recommended to fine tune the values of external load capacitors on actual hardware board to get the accurate clock frequency. For fine tuning, output the RTC Clock to the CLOCKOUT pin and optimize the values of external load capacitors for minimum frequency deviation. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 145 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 13.5.1 RTC Printed Circuit Board (PCB) design guidelines * Connect the crystal and external load capacitors on the PCB as close as possible to the oscillator input and output pins of the chip. * The length of traces in the oscillation circuit should be as short as possible and must not cross other signal lines. * Ensure that the load capacitors CX1, CX2, and CX3, in case of third overtone crystal usage, have a common ground plane. * Loops must be made as small as possible to minimize the noise coupled in through the PCB and to keep the parasitics as small as possible. * Lay out the ground (GND) pattern under crystal unit. * Do not lay out other signal lines under crystal unit for multi-layered PCB. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 146 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 13.6 XTAL oscillator In the XTAL oscillator circuit, only the crystal (XTAL) and the capacitances CX1 and CX2 need to be connected externally on XTALIN and XTALOUT. See Figure 44. LPCxxxx L XTALIN XTALOUT = CL CP XTAL RS CX2 CX1 aaa-025725 Fig 44. XTAL oscillator components For best results, it is very critical to select a matching crystal for the on-chip oscillator. Load capacitance (CL), series resistance (RS), and drive level (DL) are important parameters to consider while choosing the crystal. After selecting the proper crystal, the external load capacitor CX1 and CX2 values can also be generally determined by the following expression: CX1 = CX2 = 2CL (CPad + CParasitic) Where: CL - Crystal load capacitance CPad - Pad capacitance of the XTALIN and XTALOUT pins (~3 pF). CParasitic - Parasitic or stray capacitance of external circuit. Although CParasitic can be ignored in general, the actual board layout and placement of external components influences the optimal values of external load capacitors. Therefore, it is recommended to fine tune the values of external load capacitors on actual hardware board to get the accurate clock frequency. For fine tuning, measure the clock on the XTALOUT pin and optimize the values of external load capacitors for minimum frequency deviation. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 147 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 13.6.1 XTAL Printed Circuit Board (PCB) design guidelines * Connect the crystal and external load capacitors on the PCB as close as possible to the oscillator input and output pins of the chip. * The length of traces in the oscillation circuit should be as short as possible and must not cross other signal lines. * Ensure that the load capacitors CX1, CX2, and CX3, in case of third overtone crystal usage, have a common ground plane. * Loops must be made as small as possible to minimize the noise coupled in through the PCB and to keep the parasitics as small as possible. * Lay out the ground (GND) pattern under crystal unit. * Do not lay out other signal lines under crystal unit for multi-layered PCB. 13.7 Suggested USB interface solutions The USB device can be connected to the USB as self-powered device (see Figure 45) or bus-powered device (see Figure 46). On the LPC546xx, the USB_VBUS pin is 5 V tolerant only when VDD is applied and at operating voltage level. Therefore, if the USB_VBUS function is connected to the USB connector and the device is self-powered, the USB_VBUS pin must be protected for situations when VDD = 0 V. If VDD is always at operating level while VBUS = 5 V, the USB_VBUS pin can be connected directly to the VBUS pin on the USB connector. For systems where VDD can be 0 V and VBUS is directly applied to the VBUS pin, precautions must be taken to reduce the voltage to below 3.6 V, which is the maximum allowable voltage on the USB_VBUS pin in this case. One method is to use a voltage divider to connect the USB_VBUS pin to the VBUS on the USB connector. The voltage divider ratio should be such that the USB_VBUS pin is greater than 0.7 VDD to indicate a logic HIGH while below the 3.6 V allowable maximum voltage. For the following operating conditions VBUSmax = 5.25 V VDD = 3.6 V, the voltage divider should provide a reduction of 3.6 V/5.25 V or ~0.686 V. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 148 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller LPCxxxx VDD R2 R3 USB R1 1.5 k USB_VBUS USB_DP RS = 33 USB_DM RS = 33 D+ D- USB-B connector VSS aaa-023996 Fig 45. USB interface on a self-powered device where USB_VBUS = 5 V The internal pull-up (1.5 k) can be enabled by setting the DCON bit in the DEVCMDSTAT register to prevent the USB from timing out when there is a significant delay between power-up and handling USB traffic. External circuitry is not required. LPCxxxx VDD USB R1 1.5 k REGULATOR USB_VBUS(1) USB_VBUS(2) USB_DP RS = 33 USB_DM RS = 33 VBUS D+ D- USB-B connector VSS aaa-023997 Two options exist for connecting VBUS to the USB_VBUS pin: (1) Connect the regulator output to USB_VBUS. In this case, the USB_VBUS signal is HIGH whenever the part is powered. (2) Connect the VBUS signal directly from the connector to the USB_VBUS pin. In this case, 5 V are applied to the USB_VBUS pin while the regulator is ramping up to supply VDD. Since the USB_VBUS pin is only 5 V tolerant when VDD is at operating level, this connection can degrade the performance of the part over its lifetime. Simulation shows that lifetime is reduced to 15 years at Tamb = 45 C and 8 years at Tamb = 55 C assuming that USB_VBUS = 5 V is applied continuously while VDD = 0 V. Fig 46. USB interface on a bus-powered device Remark: In certain applications, when a self-powered circuit is used without connecting the VBUS, configure the USB_VBUS pin for GPIO and provide software that can detect the host presence before enabling the internal pull-up resistor (1.5 k) and the SoftConnect feature. Enabling the SoftConnect without host presence leads to USB compliance failure. LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 149 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 14. Package outline LQFP208; plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm SOT459-1 c y X A 105 156 157 104 ZE e E HE (A 3) A A2 A1 wM Lp bp L detail X pin 1 index 208 53 1 52 v M A ZD wM bp e D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 28.1 27.9 28.1 27.9 0.5 HD HE 30.15 30.15 29.85 29.85 L Lp v w y ZD ZE 1 0.75 0.45 0.12 0.08 0.08 1.43 1.08 1.43 1.08 7o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT459-1 136E30 MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-02-06 03-02-20 Fig 47. LQFP208 package LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 150 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller TFBGA180: thin fine-pitch ball grid array package; 180 balls SOT570-3 A B D ball A1 index area E A2 A A1 detail X e1 e 1/2 e v w b M M C C A B C y y1 C P N M L K J H G F E D C B A ball A1 index area e e2 1/2 e 1 2 3 4 5 6 7 8 9 10 11 12 13 X 14 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm max nom min A A1 A2 b D E e e1 e2 v w y y1 1.20 1.06 0.95 0.40 0.35 0.30 0.80 0.71 0.65 0.50 0.45 0.40 12.1 12.0 11.9 12.1 12.0 11.9 0.8 10.4 10.4 0.15 0.05 0.12 0.1 OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 08-07-09 10-04-15 SOT570-3 Fig 48. TFBGA180 package LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 151 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 15. Soldering Footprint information for reflow soldering of LQFP208 package SOT459-1 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8x) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 31.300 31.300 28.300 28.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 28.500 28.500 31.550 31.550 sot459-1_fr Fig 49. Reflow soldering of the LQFP208 package LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 152 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Footprint information for reflow soldering of TFBGA180 package SOT570-3 Hx P P Hy see detail X Generic footprint pattern Refer to the package outline drawing for actual layout solder land solder paste deposit solder land plus solder paste SL SP occupied area SR solder resist detail X DIMENSIONS in mm P SL SP SR 0.80 0.400 0.400 0.550 Hx Hy 12.575 12.575 sot570-3_fr Fig 50. Reflow soldering of the TFBGA180 package LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 153 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 16. Abbreviations Table 59. Abbreviations Acronym Description AHB Advanced High-performance Bus APB Advanced Peripheral Bus API Application Programming Interface DMA Direct Memory Access FRO oscillator Internal Free-Running Oscillator, tuned to the factory specified frequency GPIO General Purpose Input/Output FRO Free Running Oscillator LSB Least Significant Bit MCU MicroController Unit PDM Pulse Density Modulation PLL Phase-Locked Loop SPI Serial Peripheral Interface TCP/IP Transmission Control Protocol/Internet Protocol TTL Transistor-Transistor Logic USART Universal Asynchronous Receiver/Transmitter 17. References LPC546xx Product data sheet [1] LPC546xx User manual UM10912. [2] LPC546xx Errata sheet. [3] Technical note ADC design guidelines: http://www.nxp.com/documents/technical_note/TN00009.pdf All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 154 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 18. Revision history Table 60. Revision history Document ID Release date Data sheet status LPC546xx v.1.6 20170421 Modifications: LPC546xx v.1.5 Modifications: LPC546xx v.1.4 Modifications: LPC5460x v.1.3 Modifications: LPC5460x v.1.2 Modifications: LPC5460x v.1.1 LPC546xx Product data sheet * Change notice Supersedes LPC546xx v.1.5 Updated Table 42 "Dynamic characteristics: 20170403 Product data sheet I2S-bus - interface pins [1][4]". LPC546xx v.1.4 * Updated Table 51 "Dynamic characteristics: SD/MMC and SDIO". The max clock frequency is 50 MHz. * Updated Section 7.17.2 "SD/MMC card interface": Supports up to a maximum of 50 MHz of interface frequency. * * * Updated Table 42 "Dynamic characteristics: I2S-bus interface pins [1][4]". * Added Section 11.4 "Wake-up process". Updated Figure 26 "I2S-bus timing (master)" and Figure 27 "I2S-bus timing (slave)". Updated Table 2 "Ordering options". Parts LPC54618J512ET180 and LPC54618J512BD208 have Classic CAN. 20170307 * * - LPC5460x v.1.3 Updated Table 16 "Static characteristics: Power consumption in deep-sleep and deep power-down modes" and Table 17 "Static characteristics: Power consumption in deep-sleep and deep power-down modes". 20170224 * * * * * * * Product data sheet Changed data sheet title to LPC546xx. Product data sheet - LPC5460x v.1.2 Removed S parts. Data sheet title renamed to LPC5460x. Removed AES-256 engine and SHA references throughout the document. Security peripherals renamed to Security features. Updated Section 4 "Marking". Updated Section 5 "Block diagram". Updated Figure 6 "LPC546xx Memory mapping". Updated Table 20 "Typical AHB/APB peripheral power consumption [3][4][5]". 20170206 Product data sheet - LPC5460x v.1.1 * Updated address range details and description of the address range: 0x8000 0000 to 0xDFFF FFFF: See Table 7 "Memory usage and details": Static memory chip select: was 0x9000 0000 - 0x93 FFFF, now, 0x9000 0000 - 0x93FF FFFF. * * Updated Figure 8 "LPC5460x clock generation". * * * Updated Table 4 "Pin description": PIO0_26, USB0_IDVALUE, Type is Input (I). Updated Power control in Section 2 "Features and benefits": Ultra-low power Micro-tick Timer, running from the Watchdog oscillator that can be used to wake up the device from low power modes. Updated Section 7.18.1.1 "Features". Updated Table 31 "Dynamic characteristics of the PLL0[1]": Input frequency, Fin, Max value is 25 MHZ. 20170124 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 LPC5460x v.1 (c) NXP Semiconductors N.V. 2017. All rights reserved. 155 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 60. Revision history ...continued Document ID Modifications: LPC5460x v.1 LPC546xx Product data sheet Release date Data sheet status Change notice Supersedes * * Regrouped Table 2 "Ordering options". * Removed Table note 2: fclk = cclk/CLKDIV +1. See LPC5460x UM10912 and updated Table note 1 "See the LPC5460x user manual, UM10912 on how to program the wait states for the different read (RPHASEx) and erase/program phases (PHASEx)."of Section 11.2 "EEPROM". * Updated Table 50 "Dynamic characteristics: SD/MMC and SDIO": changed the maximum clock frequency to 52 MHz. * Updated address range details and description of the address range: 0x8000 0000 to 0xDFFF FFFF: See Table 7 "Memory usage and details": Added text to Section 7.15.3.1 "Features": Software support for AVB feature is available from NXP Professional Services. See nxp.com for more details. 20161215 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 - (c) NXP Semiconductors N.V. 2017. All rights reserved. 156 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 19.3 Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. LPC546xx Product data sheet Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 157 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications. 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V. 20. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 158 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 21. Contents 1 2 3 3.1 4 5 6 6.1 6.2 6.2.1 6.2.2 7 7.1 7.2 7.3 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 5 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pinning information . . . . . . . . . . . . . . . . . . . . . 10 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 11 Termination of unused pins. . . . . . . . . . . . . . . 50 Pin states in different power modes . . . . . . . . 51 Functional description . . . . . . . . . . . . . . . . . . 52 Architectural overview . . . . . . . . . . . . . . . . . . 52 ARM Cortex-M4 processor . . . . . . . . . . . . . . . 52 ARM Cortex-M4 integrated Floating Point Unit (FPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.4 Memory Protection Unit (MPU). . . . . . . . . . . . 52 7.5 Nested Vectored Interrupt Controller (NVIC) for Cortex-M4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.5.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 53 7.6 System Tick timer (SysTick) . . . . . . . . . . . . . . 53 7.7 On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 53 7.8 On-chip flash . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.9 On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.10 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.11 Memory mapping . . . . . . . . . . . . . . . . . . . . . . 54 7.12 System control . . . . . . . . . . . . . . . . . . . . . . . . 57 7.12.1 Clock sources . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.12.1.1 Free Running Oscillator (FRO) . . . . . . . . . . . . 57 7.12.1.2 Watchdog oscillator (WDOSC) . . . . . . . . . . . . 57 7.12.1.3 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 58 7.12.2 System PLL (PLL0) . . . . . . . . . . . . . . . . . . . . 58 7.12.3 USB PLL (PLL1) . . . . . . . . . . . . . . . . . . . . . . . 58 7.12.4 Audio PLL (PLL2) . . . . . . . . . . . . . . . . . . . . . . 58 7.12.5 Clock Generation . . . . . . . . . . . . . . . . . . . . . . 59 7.12.6 Brownout detection . . . . . . . . . . . . . . . . . . . . . 60 7.12.7 Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.13 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.13.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.13.2 Deep-sleep mode . . . . . . . . . . . . . . . . . . . . . . 61 7.13.3 Deep power-down mode . . . . . . . . . . . . . . . . 61 7.14 General Purpose I/O (GPIO) . . . . . . . . . . . . . 64 7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.15 Pin interrupt/pattern engine . . . . . . . . . . . . . . 64 7.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.16 Serial peripherals . . . . . . . . . . . . . . . . . . . . . . 65 7.16.1 7.16.1.1 7.16.1.2 7.16.2 7.16.2.1 7.16.2.2 7.16.3 7.16.3.1 7.16.4 7.16.4.1 7.16.5 7.16.5.1 7.16.6 7.16.6.1 7.16.7 7.16.7.1 7.16.8 7.16.8.1 7.16.8.2 7.16.8.3 7.16.8.4 7.16.8.5 7.17 7.17.1 7.17.1.1 7.17.2 7.17.2.1 7.17.3 7.17.3.1 7.17.4 7.17.4.1 7.18 7.18.1 7.18.1.1 7.18.2 7.18.2.1 7.18.3 7.18.3.1 7.18.4 7.18.5 7.18.5.1 7.18.6 7.18.6.1 7.19 7.19.1 Full-speed USB Host/Device interface (USB0) 65 USB0 device controller . . . . . . . . . . . . . . . . . USB0 host controller . . . . . . . . . . . . . . . . . . . High-speed USB Host/Device interface (USB1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB1 device controller . . . . . . . . . . . . . . . . . USB1 host controller . . . . . . . . . . . . . . . . . . . Ethernet AVB . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Flash Interface (SPIFI) . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAN Flexible Data (CAN FD) interface . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMIC subsystem . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Smart card interface. . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flexcomm Interface serial communication. . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI serial I/O controller . . . . . . . . . . . . . . . . . I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2S-bus interface . . . . . . . . . . . . . . . . . . . . . . Digital peripheral . . . . . . . . . . . . . . . . . . . . . . LCD controller . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . SD/MMC card interface . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . External memory controller . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA controller . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Counter/timers . . . . . . . . . . . . . . . . . . . . . . . . General-purpose 32-bit timers/external event counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCTimer/PWM . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Windowed WatchDog Timer (WWDT) . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Real Time Clock (RTC) timer . . . . . . . . . . . . . Multi-Rate Timer (MRT) . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Repetitive Interrupt Timer (RIT) . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-bit Analog-to-Digital Converter (ADC). . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 65 66 66 66 66 67 67 67 67 68 68 68 68 68 68 68 68 69 69 70 70 71 71 72 72 72 72 73 74 74 74 74 74 75 75 76 76 76 76 76 77 77 77 77 continued >> LPC546xx Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.6 -- 21 April 2017 (c) NXP Semiconductors N.V. 2017. All rights reserved. 159 of 160 LPC546xx NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.20 7.20.1 7.21 7.22 7.22.1 7.23 7.24 8 9 10 10.1 10.2 10.3 10.4 10.5 10.5.1 11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 11.12 11.13 11.14 11.15 11.16 11.17 11.18 11.19 11.20 11.21 11.23 11.24 11.25 12 12.1 12.2 12.2.1 12.3 13 13.1 CRC engine . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Temperature sensor . . . . . . . . . . . . . . . . . . . . 78 Security features. . . . . . . . . . . . . . . . . . . . . . . 78 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Code security (enhanced Code Read Protection eCRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Emulation and debugging . . . . . . . . . . . . . . . . 80 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 81 Thermal characteristics . . . . . . . . . . . . . . . . . 83 Static characteristics. . . . . . . . . . . . . . . . . . . . 84 General operating conditions . . . . . . . . . . . . . 84 Power-up ramp conditions . . . . . . . . . . . . . . . 84 CoreMark data . . . . . . . . . . . . . . . . . . . . . . . . 85 Power consumption . . . . . . . . . . . . . . . . . . . . 87 Pin characteristics . . . . . . . . . . . . . . . . . . . . . 93 Electrical pin characteristics . . . . . . . . . . . . . . 96 Dynamic characteristics . . . . . . . . . . . . . . . . . 99 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . 99 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Wake-up process . . . . . . . . . . . . . . . . . . . . . 101 External memory interface . . . . . . . . . . . . . . 102 System PLL (PLL0) . . . . . . . . . . . . . . . . . . . 111 USB PLL (PLL1) . . . . . . . . . . . . . . . . . . . . . 112 Audio PLL (PLL2) . . . . . . . . . . . . . . . . . . . . . 112 FRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . 113 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 114 Watchdog oscillator . . . . . . . . . . . . . . . . . . . 115 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 I2S-bus interface . . . . . . . . . . . . . . . . . . . . . . 118 SPI interfaces . . . . . . . . . . . . . . . . . . . . . . . . 121 SPIFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 DMIC subsystem . . . . . . . . . . . . . . . . . . . . . 125 Smart card interface . . . . . . . . . . . . . . . . . . . 126 USART interface. . . . . . . . . . . . . . . . . . . . . . 127 SCTimer/PWM output timing . . . . . . . . . . . . 128 USB interface characteristics . . . . . . . . . . . . 128 Ethernet AVB . . . . . . . . . . . . . . . . . . . . . . . . 129 SD/MMC and SDIO . . . . . . . . . . . . . . . . . . . 131 LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Analog characteristics . . . . . . . . . . . . . . . . . 133 BOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 12-bit ADC characteristics . . . . . . . . . . . . . . 134 ADC input impedance. . . . . . . . . . . . . . . . . . 137 Temperature sensor . . . . . . . . . . . . . . . . . . . 138 Application information. . . . . . . . . . . . . . . . . 140 Start-up behavior . . . . . . . . . . . . . . . . . . . . . 140 13.2 13.3 13.4 13.5 13.5.1 13.6 13.6.1 13.7 14 15 16 17 18 19 19.1 19.2 19.3 19.4 20 21 Standard I/O pin configuration . . . . . . . . . . . Connecting power, clocks, and debug functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O power consumption . . . . . . . . . . . . . . . . RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . RTC Printed Circuit Board (PCB) design guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . XTAL oscillator . . . . . . . . . . . . . . . . . . . . . . . XTAL Printed Circuit Board (PCB) design guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . Suggested USB interface solutions . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 142 144 145 146 147 148 148 150 152 154 154 155 157 157 157 157 158 158 159 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP Semiconductors N.V. 2017. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 21 April 2017 Document identifier: LPC546xx