ST75C530FP-A - STMicroelectronics

ST75C530

ST75C540

SUPER INTEGRATED DEVICES WITH DSP, AFE & MEMORIES

FOR TELEPHONY, MODEM, F AX OVER INTERNET & POTS LINES

February 1999

TQFP80 (14 x 14 x 1.4mm)

(Full Thin Plastic Quad Flat Pack)

ORDER CODE : ST75C530FP-A

ST75C540FP-A

SUMMAR IZED FEATURES

(for detailed features, see page 4)

.SINGLE CHIP FAX Up to 14.4Kbps (V. 17)

.FULL DUPLEX DATA MODEM UP TO

14.4Kbps (V.32Bis)

.DIGITAL ANSWERING MACHINE :

- 4.8Kbps VOCODER

- V ARIABLE PLA YBACK SPEED (+50% to -50%)

- ADPCM 32, 34, 16Kbps VOCO DE R

.FULL-DUPLEX DIGITAL SPEAKERPHONE

W ITH ECHO CANCE LLATION

.PROGRAMMABLE RING DETECTION

.16 PROGRAMMABLE TONE DETECTORS

FOR CLID AND SCWID

.DTMF DETECT ION

.VERSATILE HOST INTERF ACES

.16 GENERA L PURP OS E I/O POR TS

.2 RELAY DRIVE OUTP UTS

.SINGLE 5V POWE R SUP P LY

.TYPICAL ACTIVE POWER CONSUMPTION :

650mW (ST75C530), 750 mW (ST75C540)

.LOW POWE R MODE < 30mW

.80- PIN TQFP PACKAGE (1 4 mm x 14mm)

DESCRIPTION

ST75C530 and ST75C540 are two super-inte-

grated devices including DSP, Modem and Audio

Analog Front Ends and memories for Telephony,

Modem and FAX applications.

These devices can be used for classical applica-

tions over POTS lines or over Internet.

The super integration technology allows a signifi-

cant cost reduction on bill of materials for equip-

ment like High-End phones, INTERNET phones,

phone-Fax, INTERNET FAX, ...

The devices are used with a host processor

through a Dual P ort RAM allowing the use of any

kind of microcontroller (RISC, CISC, General Pur-

pose 8-bit µC, .. .).

The embedded software includes :

- handset with listening group capability,

- full duplex handsfree,

- voice coder/decoder at 4.8Kbps for static answer-

ing machine applications and ADPCM 16Kbps,

24Kbps and 32Kbps for high quality message

recording,

- Tone and DTMF generators,

- Tone and DTMF detectors,

- FAX up to 14.4Kbps,

- Data-Modem up to 14.4Kbps (ST75C540 only).

The DSP so fware is extensively user configurable

allowing specific functions to be supported like

Caller Identifier (CLID) and Second Call Waiting

Identifier (SCWID).

The DSP software includes a transparent mode

allowing the host controller to access directly the

modem Analog Front End and the Audio AFE

through the dual Port RA M. This is v ery useful for

hostprocessing modem solutions (or soft modem)

where the m odulation and the demodulation (V.34,

V.90) are done by the application main pr ocessor.

In transparent m ode, the embedded DSP can be

used simultaneously with the same samp les.

The transparent mode for audio AFE is provided to

play audio files or to record voice and/or audio.

1/84

CONTENTS Page

I DE TAIL ED FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

II PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

II.1 PIN CONNECTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

II.2 HOST INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

II.3 ANALOG INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

II.4 GENERAL PURPOSE IO AND RELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

II.5 MISCELLANEOUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

II.6 POWER SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

III BLOCK DIAGRAMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

III.1 ANALOG INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

III.2 INTERNAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

IV ELECTRICAL SPECIFICA TIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

IV.1 MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

IV.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

IV.3 DI GITAL IN TERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

IV.4 MODEM ANALOG INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

IV.5 AUDIO ANALOG INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

IV.6 AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

V FUNCTIONA L DESCR IPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

V.1 SYSTEM ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

V.2 MODES OF OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3

V.3 OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

V.3.1 Modem Transmitter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

V.3.2 Modem Receiver Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

V.3.3 Tone Generator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

V.3.4 Tone Detector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

V.3.5 V.21 Channel 2 Flag Detector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

V.3.6 HDLC Descriptio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

V.3.7 UART Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

V.3.8 DTMF Detector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

V.3.9 Ring Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

V.3.10 VOCODER Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

V.3.11 Voice Activity Detector (VAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

V.3.12 Telephon y Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

V.3.13 Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

V.3.14 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

V.4 MODEM INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

V.4.1 Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

V.4.2 General I/O and Relay Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

V.4.3 Crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

V.4.4 Typical Applicat ion Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

V.4.5 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

VI US ER INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

VI.1 DUAL PORT RAM DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

VI.2 COMMAND SET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

VI.3 COMMAND SET SHORT FORM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

VI.4 STATUS - REPORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

VI.5 DATA EXCHANGE S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7

ST75C 530 - ST75C540

2/84

VII COMMAND SET DESCRIPT ION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

VIII STATU S DESCR IPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

VIII.1 COMMAND ACKNOWLEDGE AND REPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

VIII.2 MODEM STATUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

IX TONE DETECTORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

IX.1 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

IX.2 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

IX.3 EXAMPLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

X PARALLEL DATA EXCHANGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

X.1 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

X.2 TRANSMIT BUFFER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

X.3 RECEIVE BUFFER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

X.4 INTERRUPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

X.5 DATA FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

X.6 FORM COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

XI TRANSM IT TING DATA IN PARALLEL MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

XI.1 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

XI.2 MODEM FLOW CHART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

XI.3 HOST FLOW CHART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

XI.4 ERROR DETECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

XI.5 SYNCHRONOUS MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

XI.6 HDLC MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

XI.7 UART MODE DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

XI I RE C EI VI NG IN PA RALLEL MO D E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

XII.1 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

XII.2 MODEM FLOW CHART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

XII.3 HOST FLOW CHART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

XII.4 ERROR DETECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

XII.5 SYNCHRONOUS MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

XII.6 HDLC MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2

XII.7 UART MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

XIII VOCODER DATA EX CHANGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

XIII.1 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

XIII.2 VOCODER BUFFER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

XIII.3 TRANSMIT (DECODER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

XIII.4 RECEIVE (CODER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

XIV TRANSPARENT MODE DATA EXCHANGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

XV DEFAULT CALL PROGRESS TONE DETECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

XV I DEFAULT ANSWER TONE DETECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

XVII ELECTRICAL SCHEMATICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

XVIII PCB DESIGN GUIDELINES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

XIX APPENDIX A : MODES OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

XX PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

ST75C 530 - ST75C540

3/84

I - DETAILED FEATURES

Single Chip Fax

- ITU-T V.17, V.29, V.27ter, V.21 with Fax support

- V.17, V.29 (T104), V.27ter short trains,

V.33 half- duplex

- V.21 flag detection and 4 tone detection during

high speed reception modes

- V.21 flag detection, DTMF detection and 4

tone detection duringV.21 channel 2 reception

modes

- Programmable call progress and call waiting

detection

- Parallel data handling

- HDLC and UA RT framing support

- 1700Hz and 1800Hz carrier

- Full implementation of the V.17, V.33, V.29 and

V.27 handshakes

- 0 to -15dBm programmable transmit power

- 0 to -47dBm receiver dynamic range (ST75C530)

0 to -45dBm receiver dynamic range (ST75C540)

Full Du ple x D a ta Modem

- ITU-T V.32bis, V.3 2 ( 14400, 12000, 9600, 7200,

4800bps) (*)

- Maximum round trip delay : 1.2s (satellite hops)

(*)

- Up to 10Hz of phase roll on far end echo (*)

- ITU-T V.22bis, V.22 (2400, 1200bps) (*)

- V.32bis/V.32/V.22bis/V.22 automode (*)

- ITU- V.23, V. 21, bell 103 full-duplex,

Bell202 demodulator

- -10 to -25dBm programmable transmit power

- -10 to -38dB m receiv er dynam ic range (*)

- HDLC and UA RT framing support

- Train based on quality line sampling (*)

(*) ST75C540 only

Digital Answerin g Machine

- Low bit rate speech coder (4800bps)

- Variable playback speed (+50% to -50%)

- ARAM compatibility (error correction)

- ADP CM 32, 24, 16Kbps

- Line echo cancellation

- Voice activity detector

- Concurrent DTMF and tone detection

Handset Mode

- Rx and Tx AGC versus line current for line

losses compensation comply with most of

coun try regu lation s

- Dynamic limiter in transmit path to prevent

distortion

- Two way conversation recording

Hands-free Mode

- Full duplex speakerphone using LMS adaptative

filtering including line echo cancellation and

acoustic echo canc ellation

- Rx and Tx AGC versus line current for line

losses compensation comply with most of

coun try regu lation s

- Dynamic limiter in transmit path to prevent

distortion

- Loudspeaker volume control

- Two way conversation recording

Extended Modes of Operations

- Programmable ring detection

- 16 programmable tone detectors

- Tone and DTMF generator s

- Caller ID reception

- T ransparent mode allowing direct transfer of Mo-

dem AFE and audio AFE samples to and from

host processor for soft Modem applications and

sound files playing

- DTMF detection

- Wide dynamic range (>48dB)

Versatile Interfaces

- Parallel 128 x 8-bit dual port RAM

- General purpose 16 I/O ports

- 2 relay drive outputs

- Full diagnostic capability

- Dual 8-bit DAC for constellation display

Single 5V Power Supply

- T y pical active power consumption :

650mW (ST75C530), 725mW (ST75C540)

- L ow power mode < 30mW

ST75C 530 - ST75C540

4/84

6566676869707172737475

26 27 28 29 30 31 32 33 34 35 3621 22 23 24 25

7677787980

37 38 39 40

61626364

GIO10

DD4

DGND4

GIO07

GIO06

GIO05

GIO04

GIO03

GIO02

DD3

DGND3

GIO01

GIO00

RING

RELAY1

RELAY0

RGND

INT/MOT

SINTR

SCS

SPK1N

AGNDTA

REFN

REFP

SPK1P

AGNDRA

MIC1

MIC2

MIC3

RxA

DDM

AGNDM

TxA2

TxA1

EYEX

EYEY

DGND6

DD6

DGND1

DD1

SD0

SD1

SD2

SD3

SD4

SD5

SD6

SD7

DGND2

DD2

SR/W

SDS

SA0

SA1

SA2

SA3

SA4

SA5

SA6

DDA

SPK2P

SPK2N

SPK3P

SPK3N

RESET

TEST0

EXTALL

XTALL

DD5

DGND5

XPLL

CLKOUT

GIO17

GIO16

GIO15

GIO14

GIO13

GIO12

GIO11

75C53001.EPS

II - PIN DESCRIPTION

II.1 - Pin Connec tions

ST75C 530 - ST75C540

5/84

II.2 - Host Interface

The exchanges with the control processor proceed through a 128 x 8 DUAL port RA M shared between the

ST75C530/540 and the Host. The signals associated with this interface are :

Pin Name Type Description

SD0..SD7 I/O System Data Bus. 8-bit data bus used for asynchronous exchanges between the

ST75C530/540 and the Host through the dual port RAM. High impedance when exchanges

are not active.

SA0..SA6 I System Address Bus. 7-bit address bus for dual port RAM, IO and interrupt registers.

SDS (SRD) I System Data Strobe. In Motorola mode SDS initiates the exchange, active low. In Intel mode

SRD initiates a read exchange, active low.

SR/W (SWR) I System Read/Write. In Motorola mode SR/W defines the type of exchange read/write. In Intel

mode SWR initiates a write exchange, active low.

SCS I System Chip Select. Active low.

SINTR OD System Interrupt Request. Open drain. Active low. This signal is asserted by the ST75C530/540

and negated by the host.

RESET I Reset. Active low.

INT/MOT I Select Intel or Motorola Interface

II.3 - Analog Interface

Pin Name Type Description

TxA1 O Transmit Analog Output 1

TxA2 O Transmit Analog Output 2

RxA I Receive Analog Input

SPK1P O Speaker Output 1, (differential positive), must be connected through Amplifier to the

loudspeaker.

SPK1N O Speaker Output 1, (differential negative)

SPK2P O Speaker Output 2, (differential positive), must be connected through Amplifier to the Handset

loudspeaker.

SPK2N O Speaker Output 2, (differential negative)

SPK3P O Speaker Output 3, (differential positive)

SPK3N O Speaker Output 3, (differential negative)

MIC1 I Microphone Input 1

MIC2 I Microphone Input 2

MIC3 I Microphone Input 3

VCM I/O Analog Common Voltage (nominal +2.5V). This input must be decoupled with respect to AGND.

VREFN I Analog Negative Reference (nominal 1.25V). This input must be decoupled with respect to

VCM.

VREFP I Analog Positive Reference (nominal 3.75V). This input must be decoupled with respect to VCM.

II.4 - General Purpose IO and Relay

Pin Name Type Description

GIO[0,7] I/O General Purpose I/O Pins, can be independently selected as input or output.

GIO[10,17] I/O General Purpose I/O Pins, can be independently selected as input or output.

RELAY0,

RELAY1 OD Relay Outputs, Open Drain, Active Low. Can sink -10mA to RGND.

RING I Ring detect signal. Active low. If the ST75C530/540 is in low power mode, a low level wil l awake

the chip. This input is a Schmidt’s trigger.

RGND PWR Relay Digital Ground. To connect to GND.

II - PIN DESCRIPTION (continued)

ST75C 530 - ST75C540

6/84

II.5 - Miscellaneous

Pin Name Type Description

EYEX O Constellation X analog coordinate

EYEY O Constellation Y analog coordinate

XTAL O Internal Oscillator Output. Left open if not used.

EXTAL I Internal Oscillator Input, or External Clock Input.

XPLL I Reserved for future use, must be connected to digital ground.

CLKOUT O Output Clock, EXTAL/2 (not available in low power mode).

TEST0 I Test pin for normal operation, must be connected to digital ground.

Not e : The nominal frequency of the crystal oscillato r is 44.2368MHz with a precision better than ± 100ppm.

II.6 - Power Supply

Symbol Nber Parameter

DVDD 6 Digital +5V.

DGND 6 Digital Ground.

AVDD 2 Analog +5V.

AGND 3 Analog Ground.

II - PIN DESCRIPTION (continued)

ST75C 530 - ST75C540

7/84

ADC

MUTE

DAC Line

HYBRID

TXA1

TXA2

RXA

ADC

MIC3

MIC1

MIC2

SPK2

MUTE

SPK3

MUTE

SPK1

MUTE

[0..-30]dB

Step 3dB

DAC

ST75C530/540

75C53002.EPS

III - BLOCK DIAG RAMS

III.1 - Analog Interface

III.2 - Internal Block Diagram

DUAL

PORT RAM

GIO AND RELAY

EYE DAC

PROM

26624

INSTRUCTIONS

ANALOG

FRONT

END

TIME BASE

OSC

ST18932

DSP

(24Mips)

RAM

6144 WORDS

ROM

16368 WORDS

AUTOTEST

1024

INSTRUCTIONS

AUTOTEST

1024

INSTRUCTIONS

EYEX

EYEY

XTAL

EYEY

CLKOUT

EXTAL

RING

RELAY0

RELAY1

Pins 48-49

Pins 52 to 57

GIO0[0..7]

Pins 60 to 67

GIO1[10..17]

Pins 22 to 29

SD[0..7]

Pins 34 to 40

SA[0..6]

SINTR

Instruction

Bus Data Bus

45 46

ST75C530/540

75C53003.EPS

ST75C 530 - ST75C540

8/84

IV - ELECTRICAL SPECIFICA TIONS

IV.1 - Maximum Ratings (AG ND = DGND = RGND = 0V, all voltages with respect to 0V)

Symbol Parameter Value Unit

AVDD Analog Power Supply -0.3, 6.0 V

DVDD Digital Power Supply -0.3, 6.0 V

IIInput Current per Pin (except supply pins and RELAY0 and RELAY1) -10, +10 mA

IOOutput Current per Pin (except supply pins and RELAY0 and RELAY1) -20, +20 mA

IO2 Output Current per Pin RELAY0 or RELAY1 (respect to RGND) -40, 0 mA

VIA Analog Input Voltage -0.3, AVDD + 0.3 V

VID Digital Input Voltage -0.3, DVDD + 0.3 V

VIDGPIO Digital Input Voltage at GPIO 5.25 V

Toper Operating Temperature 0, +70 °C

Tstg Storage Temperature - 40, +125 °C

Ptot Maximum Power Dissipation 1500 mW

Warning : Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranted at these extremes.

IV.2 - Recommended Operating Conditions

(AGND = DGND = RGND = 0V, all voltages with respect to 0V)

Symbol Parameter Min. Typ. Max. Unit

VDD Supply Voltage 4.75 5 5.25 V

IDD Supply Current ST75C530

ST75C540 130

145 150

165 mA

PDLP Low Power 30 mW

PDPower ST75C530

ST75C540 650

725 790

866 mW

VCM Common Mode Voltage Output (refer to AVDD/2) -5 +5 %

ICM Common Mode Current (see Note 1) 100 µA

Note 1 : DC current only. If dynam ic load exis ts , the VCM output must be buffered or the performances of ADCs and DACs will be degraded.

ST75C 530 - ST75C540

9/84

IV.3 - Digital Int e r face

(AVDD = DVDD = 5V, AG ND = DGND = RGND = 0V) except XTAL, EXTAL, RING.

Symbol Parameter Min. Typ. Max. Unit

VIH High Level Input Voltage 2.2 V

VIL Low Level Input Voltage -0.3 0.8 V

VOH High Level Output Voltage (Iload = -2mA, Iload = -4mA for SD[7..0]) 2.4 V

VOL Low Level Output Voltage (Iload = 2mA, Iload = 4mA for SD[7..0]) 0.4 V

ILEAK Input Leakage Current -10 10 µA

IOL Low Level Output Current (except RELAY0 and RELAY1, and SINTR)

(0 < VOL < VOLMax.)-2 mA

IOH High Level Output Current (except RELAY0 and RELAY1, and SINTR)

(0 < VOL < VOLMax.)2mA

OZ GIO Three State Input Leakage Current (GND < VO < VDD)-50050µA

OZ SD Three State Input Leakage Current (GND < VO < VDD)-50050µA

OLRELAY Low Level Output Current RELAY0 or RELAY1 (VOL = 0.8V) -10 0 mA

CRYSTAL OSCILLATOR

VIH High Level Input Voltage 3.5 V

VIL Low Level Input Voltage 1.5 V

IHHigh Level Input Current -20 µA

ILLow Level Input Current 20 µA

RING (this input have hysteresis)

VIH High Level Input Voltage 2.4 2.8 V

VIL Low Level Input Voltage 1 1.2 V

IHHigh Level Input Current -20 µA

ILLow Level Input Current 20 µA

IV - ELECTRICAL SPECIFICA TIONS (continued)

ST75C 530 - ST75C540

10/84

IV.4 - Modem Analog Interface

AVDD = DVDD = 5V, Tamb = 25oC

Measurement bandwidth is flat from 100Hz to 4800Hz ;Load impedance 10kΩ, 20pF

For differential output (TxA1/TxA2) : 0dBr = 1.77VRMS 1kHz sinwave (equivalent to 5VPP).

For single input (RxA) : 0dBr = 886mVRMS 1kHz sinwave (equivalent to 2.5VPP).

Symbol Pin Name Parameter Min. Typ. Max. Unit

Rxrin RxA Input Impedance 100 kΩ

Rxmac Maximum AC Input Voltage = 0dBr 2.5 VPP

Rxdc DC Reference Voltage 2.5 V

Rxsndr Signal to (Noise + Distortion), at -6dBr 75 dB

Rxin Idle Noise -81 dBr

Rxov DC Offset Voltage (Input = VCM) -50 100 mV

TxAdrl TxA1/TxA2 Minimum Differential Load 10 kΩ

TxAcl Maximum Differential Load 20 pF

TxArout Output Impedance 100 Ω

TxAmac Maximum AC Differential Output = 0dBr 5 VPP

TxAdc DC Reference Voltage 2.5 V

TxAov DC Offset Voltage -200 200 mV

TxAsndr Signal to (Noise + Distortion), at -6dBr 79 dB

TxAin Idle Noise -85 dBr

IV.5 - Audio Analog Interface

AVDD = DVDD = 5V, Tamb = 25oC

Measurement bandwidth is flat from 100Hz to 4800Hz ;Load impedance 10kΩ, 20pF

For differential output (SPK1N /SPK1P, SPK2N/SP K2P, SPK3N/SP K3P) : 0dBr = 1.77V RMS 1kH z sinwave

(equivalent to 5VPP).

For single input (MIC1, MIC2, MIC3) : 0dBr = 886mVRMS 1kHz sinwave (equivalent to 2.5VPP).

Symbol Pin Name Parameter Min. Typ. Max. Unit

RArin MIC1,

MIC2,

MIC3

Input Impedance 100 kΩ

RAmac Maximum AC Input Voltage = 0dBr 2.5 VPP

RAdc DC Reference Voltage 2.5 V

RAdis Distortion at -6dBr 2 %

RAin Idle Noise -81 dBr

RAov DC Offset Voltage (Input = VCM) -50 50 mV

TAdrl SPK1N/SPK1P,

SPK2N/SPK2P,

SPK3N/SPK3P

Minimum Differential Load 10 kΩ

TArout Output Impedance 100 Ω

TAmac Maximum AC Differential Output = 0dBr 5 VPP

TAdc DC Reference Voltage 2.5 V

TAov DC Offset Voltage -200 200 mV

TAdis Distortion at -6dBr 1 %

TAin Idle Noise -81 dBr

IV - ELECTRICAL SPECIFICA TIONS (continued)

ST75C 530 - ST75C540

11/84

IV.6 - AC Electrical Characteristics

IV - ELECTRICAL SPECIFICA TIONS (continued)

SCS

WRITE CYCLE READ CYCLE

Intel mode

132

142

OUTIN

6 7

13 14

SA[0..6]

SR/W

SDS

SD[0..7]

SINTR

GIO(out),

RELAY

GIO(in)

Motorola mode

75C53004.EPS

Number Description Min. Typ. Max. Unit

1 Address and Control Set-up Time 5 ns

2 Address and Control Hold Time 20 ns

3 Write Enable Low State 45 ns

4 Read Enable Low State 45 ns

5 Access Inhibition High State 70 ns

6 Data Set-up Time 10 ns

7 Data Hold Time 5 ns

8 GIO Output, Relay, SINTR Clear Delay 50 ns

9 GIO Output Hold Time 0 ns

10 Read Data Access Time 35 ns

11 Data Valid to Tristate Time 15 ns

12 Data Hold Time 5 ns

13 GIO Input Delay Time 40 ns

14 GIO Input Hold Time 0 ns

ST75C 530 - ST75C540

12/84

V - FUNCTIONAL DESCRIPTION

V.1 - System Architecture

The chip allows the design of a complete F AX, Data

Modem, Hands-Free Telephone and Answering

Machine system. A versatile dual port RAM allows

an easy interface with most micro-controllers.

V.2 - Modes of Operation

Refer to Appendix A for B lock Diagram s.

V. 3 - Operat ions

V.3.1 - Modem Transmitter Description

The signal pulses are shaped in a dedicated filter

further combined with a compromise transmit

equalizer suited for transmission over strongly dis-

torted lines. 3 different compromise equalizers are

available and can be selected by software.

V.3.2 - Modem Receiver Description

The receiver section handles complex signals and

uses a f r actionally spaced complex equalizer. It is

able to cope wit h distant modem timing dr ifts up to

10-4 as s pecified in the I TU-T recommendations. It

also compensates for frequency drift up to 10Hz

and for phase jitter at multiple and simultaneous

frequencies.

V.3.3 - T o ne Generat or Description

Four tones can be simultaneously generated by the

ST75C530/540. These tones are determined by

their frequencies and by the output amplitude level.

A set of specific commands are also available for

DTMF generation. Any of the 4 tone generators can

be output independently either on t he Audio DAC

or the line DAC.

V.3.4 - T o ne Detector Description

During TONE (respectively TONECID) Mode six-

teen (respectively eight) tones can be simultane-

ously detected by the ST75C530/540. Each of the

tones to be detected is defined by the co efficien ts

of a 4th order programmable IIR. Detection thresh-

olds are programmable f rom -51dBm up to -6dBm.

These primary detectors can detect tone up to

3.3kHz (sampling rate 7.2kHz in all modes). They

also have a programmable internal wiring feature

(see Chap ter IX).

In all modes, except Handset (HANDSET) and Full

Duplex V.32bis/V.32/V.22bis/V.22 (Modem)

modes, 4 additional tone detectors (each of them

being a 4th order programmable IIR) are concur-

rently running. In Handset mode only 2 additional

tone detectors ar e av ailable. Detection thresholds

are programmable from -51dBm up to -6dBm. This

secondary programmable detector can detect

tones up t o 1.8kHz by default set-up with a sam-

pling rate at 4.8kHz. But this 4 additional tone

detectors can also detect tones up to 3.3kHz with

a sampling rate at 9.6kHz. In order to avoid wrong

detectgion, relative detectgion is also provided.

V.3.5 - V.21 C h an ne l 2 Fla g D e t ect or Des c ri ption

In all the Receive F AX Modes, including V .21 Chan-

nel 2 Mode, the ST75C530/540 processes a V.21

Flag “7E” detector, either in the idle state, the train

sequence or the data mode. The detection time is

3 consecutive flags to detect and 1 byte to loose

the detection.

V.3.6 - HDLC Description

In all F AX Modes (MODEM), including V.21 Chan-

nel 2 Mode, and also Full Duplex

V.32bis/V.32/V.22bis/V.22 (Modem) modes, a

HDLC framing and deframing is supported by the

ST75C530/540. The number of transmitted flags

can be pr ogr ammed.

V.3.7 - UART Description

In Full Duplex V.32bis/V.32/V.22bis/V.22 Modem

Modes and TONECID V .23 receive mode, a parallel

UART is performed by the ST75C530/540. This

UART manage the Break signal either at the trans-

mit and the receive bit stream. The Data format

supported are 7 and 8 bit of Data; even, odd or no

Parity, 1 or 2 stop bits.

V.3.8 - DTMF Detector Description

A DTMF Detector is included in the ST75C530/540,

it allows detection of valid DTMF Digits. A valid

DTMF Digit is defined as a dual tone with a total

power higher than -43dBm, a duration higher than

40ms and a differential amplitude within ±8dB. This

DTMF Detector is enabled in all modes except in

Fax Modem, Data Modem and Handset modes. It

is also enabled in V.21 Channel 2 Receive Mode.

The DTMF thresholds and duration can be

changed from they default value by overwriting

DSP’s RAM locations. In the default setup, this

detector is compliant with the NE T4 standard. The

frequency deviation can be changed by overwriting

the default DTMF’s filters coefficients.

V.3.9 - Ring Detector

This detector detects RING signal from 15Hz to

68Hz, it can be programmed to expand the mini-

mum and maximum detection frequency up to

12Hz (for min) and 144Hz (for max). The detection

time is equal to one period of the ring signal, and

the loose t ime to t he minimum between one period

of the ring signal and the inverse of the minimum

frequency.

The associated STA_RING status is as Figure 1.

ST75C 530 - ST75C540

13/84

V.3.10 - VOCODE R Description

The Vocoder mode allows the implementation of

an answering machine function. In the CODER

mode the received samples from one of the two

analog inputs, Line or Audio, are compressed by

the ST75C530/540 and written into the dual port

RAM Voc oder Buffer (VOCxxx). At t he same time

the ST75C530/540 is looking for an incoming

DTMF tone and 4 different programmable tones.

In the DECODER mode the compressed samples

are read from the dual port RAM, decompressed

and transmitted to one of the two analog output,

Line or Micx. The ST75C530/540 synthesises an

estimation of its echo and subtracts it from the

received signal. At the same time the

ST75C530/540 is looking for an incoming DTMF

tone and 4 different tones.

Two algorithms of voice coding are implemented :

- Low bit rate speech cod er (4800bps or 5300bps

with forward error correction).

- ADPCM (ST proprietary algorithm) at 32, 24 and

16Kbps.

If the low bit rate coder algorithm is selected the

ST75C530/540 has the capability to slow down or

speed up the DECODER flow up to ±50%. This

function allows a quick message listening if speed

up is us ed, or at t he opposite if s low down is used,

an enhancement of the voice intelligibility.

V.3.11 - Voice Activity Detector (VAD)

In CODER Mode, for both of the Voice Coding

algorithms, a Voice Activity Detector is imple-

mented while coding by the ST75C530/540. The

STA_109 bit and STA_109F bit refle ct the stat e of

the VAD. After the CONF command the VAD is on

(assume voice). The default time-out to detect si-

lence is 2 seconds and the set-up time to detect the

voice is 15ms. This V A D information is also copied

into the Receive Buffer Status Word MSB (VOC-

STA bit7). This detector is fully programmable in

level sensitivity (down to -60dB m), hysteresis, and

various criteria.

An optional silence suppressor is implemented in

the Coder section to suppress long silence in the

incoming message. When enabled (CONF_SUP-

SIL equal 1) if a long silence is detected (STA_109

equal 0) the ST75C530/ 540 stops generating B uff-

er Interrupts. After that if a voice is again detected

the ST75C530/540 will resume the Buff er Interrupt

mechanism.

RING

STA_RING

1/Fmax prog. < T1 < 1/Fmin prog.

T2 < 1/Fmax prog.

T3 1/Fmin prog.

T2 T3

75C53005.EPS

Figure 1

V - FUNCTIONAL DESCRIPTION (continued)

Rx Signal

STA_109

(or VOCSTA bit 7)

Interrupt (IT1)

75C53006.EPS

Figure 2

ST75C 530 - ST75C540

14/84

V.3.12 - Tele phony Func ti ons

ST75C530/540 telephony software provides both

handset and handsfree modes. ST75C530/540 is

connected to the phone line through a D.A.A.,

handset and loudspeaker are connected to

ST75C530/540 through amplifiers.

Though the D.A.A. has to comply with modem/fax

regulations in most of the applications, the m icro-

phone and the earphone amplifier gains will be

adjusted in compliance with the telephony regula-

tions. The software implemented in ST75C530/540

allows functions such as softclipping, AGC in both

modes, and full duplex mode in handsfree (see Fig-

ure 3).

V.3.12.1 - Handset Mode

In handset mode, all the attenuations (_SPKGAIN,

_TXGAIN, _MIKGAIN) are from 0dB to -inf

(32768 steps). AGC and softclipping functions can

be enabled and disabled by software (see Figure 4).

DUAL

RAM

INTERFACE

ADC

MUTE

DAC Line

HYBRID

TxA1

TxA2

RxA

ADC

MIC3

MIC1

MIC2

SPK2

MUTE

SPK3

MUTE

SPK1

MUTE

[0..-30]dB

Step 3dB

DAC

ATT_TX

CODER

HANDSFREE/

HANDSET

ALGORITHMS

ATT_MIC

2 TONE

GENERATOR

AGC

2 TONE

DETECTORS

AGC

75C53007.EPS

Figure 3 : Handset/Handsfree Mode Operation

V - FUNCTIONAL DESCRIPTION (continued)

MIC2

SPK2_1

SPK2_2

_MIKGAIN

_SPKGAIN

Softclipping

AGC = F(I

LINE

)

RxA

DP_RING

TxA1

TxA2

_TXGAIN

AGC = F(I

LINE

)

75C53008.EPS

Figure 4 : Handset Mode

ST75C 530 - ST75C540

15/84

Tx Characteristics

Symbol Parameter Test Conditions Min. Typ. Max. Unit

Gtx Transmit Gain _MIKGAIN=7FFF,_TXGAIN=7FFF, AGC disabled

VMIC2 = -21dBV

VMIC2 = -9dBV 18

8dB

Ntx Transmit noise 2kΩ between MIC2 and GND -73 dBmp

Mmic Microphone mute VMIC2 = -21dBV 60 dB

VLpeak Transmit softclipping

level on TxA1-TxA2 _MIKGAIN=7FFF,_TXGAIN=7FFF, AGC disabled

see Figure 3, VMIC2 = -9dBV 2.5 Vpp

Dtx Transmit distortion _MIKGAIN=7FFF,_TXGAIN=7FFF, AGC disabled

see Figure 3, VMIC2 = -9dBV 2%

Rx Characteristics

Symbol Parameter Test Conditions Min. Typ. Max. Unit

Grx Receive Gain _SPKGAIN=7FFF, AGC disabled, VRXA = -16 dBV 6 dB

Nrx Receive noise -79 dBmp

Mrx Mute VRXA = dBV 60 dB

Dtx Receive distortion

(SPK2 output) _SPKGAIN=7FFF, AGC Disabled, VRXA = -16dBV 2 %

AGC

The line current information is coming from the

D.A.A. on DP_RING pin (frequency coded informa-

tion using by example a TS555 general purpose

timer). The AGC has a 6dB depth . The attenuation

table can be loaded to comply with each country

regulation. The default table has the following val-

ues. The value of the AGC gain is applied to both

Tx and Rx path (see Table 1).

The address of the table is given in the register

@_TABLE.

The table length is 5 3. The AGC is enabled using

CONF or MODC command (see paragr aph "VII -

COMMAND SET DESCRIPTION".

Once the AGC is running, it is possible to freeze the

AGC gain with the register AGC_F RZ.

Softclipping

The softclipping introduces a 12dB gain and has a

18dB depth.

The softclipping value is half digital range

(4000 Hex) (see Figure 5).

V - FUNCTIONAL DESCRIPTION (continued)

10 V

MICX

(mV

RMS

)10

(mV

RMS

)D (%)

VTxA1-TxA2 (V

RMS

)

Distortion

Tx Softclipping and Distortion

75C53009.EPS

Figure 5 : Softclipping Static Gain

Table 1 : AGC Gain versus Period Information

Period (ms) <9 10 10.8 11.6 14.5 13.3 14.1 15.5 16.6 17.5 18.3 19.1 20 >20

Table Index <13 13 14 15 16 17 18 19 20 21 22 23 24 >24

Gain (dB) 0 0.7 1.5 2.2 3 3.4 4 4.5 4.8 5.1 5.4 5.6 5.8 6

ST75C 530 - ST75C540

16/84

V - FUNCTIONAL DESCRIPTION (continued)

SPK1P

SPK1N

_SPKGAIN

RxA

TxA1

TxA2

ADAPTIVE

FIR

FILTER

MIC1

_MIKGAIN ACOUSTIC

FILTER ADAPTIVE

ATTENUATOR

NLMS CONTROL NLMS

ADAPTIVE

FIR

FILTER

AGC = F(I

)

_TXGAIN

Softclipping

AGC = F(I

)ADAPTIVE

ATTENUATOR

75C53010.EPS

Figure 6 : Handsfree Mode : Full Duplex

V.3.12.2 - Handsf ree Mode

The ha ndsfree us es a MIC1 a nd a SPK1 as microp hone and lo udspea ker i nterf ace (se e Figure 6) .

Tx Characteristics

Symbol Parameter Test Conditions Min. Typ. Max. Unit

Gtx Transmit Gain _MIKGAIN=7FFF,_TXGAIN=7FFF, AGC disabled,

VMIC1 = -21dBV 24 dB

Ntx Transmit noise 2kΩ between MIC1 and GND -70 dBmp

Mmic Microphone mute VMIC1 = - dBV 60 dB

Dtx Transmit distortion _MIKGAIN=7FFF,_TXGAIN=7FFF, AGC disabled,

VMIC1 = -9dBV 2%

Rx Characteristics

Symbol Parameter Test Conditions Min. Typ. Max. Unit

Grx Receive Gain _SPKGAIN=7FFF, AGC disabled, VRXA = -33dBV 24 dB

Mrx Mute 60 dB

Dtx Receive distortion

(SPK1 output) _SPKGAIN=7FFF, AGC disabled, VRXA = -33dBV 2 %

AGC

The AGC has the same behavior as in Handset mode. Furthermore, the maximum gain added by AGC can

be fixed by using the RX_GAINMAX and TX_ GAINMAX registers.

Softclipping

See Figure 7.

System Stability

Parameter Test Conditions Min. Typ. Max. Unit

Loop attenuation in Rx RxA to TxA1-TxA2 Speaker gain is 12dB, Mike gain is 14dB 20 dB

Loop attenuation in Tx MICx to SPK1P-SPK1N Analogique sidetone not used

(see DAA schematics) 20 dB

It is possible to add some gain switching in the Tx and Rx path (t o reduce the gain of the loop) by using

the GAIN_RCV and GAIN_XMT registers.

ST75C 530 - ST75C540

17/84

V - FUNCTIONAL DESCRIPTION (continued)

VSPK1 (V

RMS

)

Distortion

Rx Softclipping and Distortion

(mV

RMS

)D (%)

10 V

MIC2

(mV

RMS

)

75C53011.EPS

Figure 7 : SP K1 Distortion versus RxA

POWER SPEC1

POWER SPEC2 64Avg

64Avg 0%Ovlp

0%Ovlp Ftop

Ftop

0.0

dBm

RMS

Vv2

-80.0

Fxd Y O Hz 5k

Line Tx

Speaker Output

75C53012.EPS

Note : Acoustic ech o from speaker to microphone input with no

local speech. Receiving speech on line input.

Figure 8 : Speaker and Line Tx Pow er S pectrums

V.3.13 - Low Power Mode

Sleep state can be attained by a SLEEP command.

When in sleep mode, the dual port RAM is unavail-

able and the clocks are disabled.

When entering the low power mode, the

ST75C530/540 stops it s oscillator , all the peripher-

als of the DS P c ore are s topped in order to reduce

the power consumption. The dual port RAM is

made inaccessible.

The ST75C530/540 can be awakened by a hard-

ware reset, a RING s ignal or a dummy write at any

location in the dual port RAM.

There is a maximum time of 20ms to restart the

oscillator after waking up and an additional 5ms

after the interrupt to be able to accept any com-

mand co ming from the host.

V.3.14 - Reset

After a hardware reset, or an INIT command, the

ST75C530/540 clears all its internal memories,

clea rs the whole dual port RA M and start s to initial-

ize the delta sigma analog converters. As soon as

these initializations are completed, the

ST75C530/540 generates an interrupt IT6 (com-

mand ack noledge ) and is pr ogra mmed t o se nd and

receive ton es, the sampl e clock are programmed to

9600H z. T he total duratio n of the r eset seque nce i s

about 5ms. After that time the ST75C530/540 is

ready to execute commands sent by the host micro-

controller. The duration of the reset signal should be

grea te r tha n 700ns.

V.4 - Modem Interface

V.4.1 - Analog Interface

Refer to Block Diagram on page 7.

V.4.2 - General I/O and Relay Interface

16 pins are dedicated to the general I/O port. Two

are dedicated to Relay driver. The equivalent sche-

matic is as follows : see Figure 9.

GIO0[x]

IODIR0[x]

IODATA0[x]

(write)

IODATA0[x]

(read)

RELAY[y]

IORELAY[y]

(write)

IORELAY[y]

(read) RGND

75C53013.EPS

Figure 9

ST75C 530 - ST75C540

18/84

V.4.3 - Crystal

The crystal frequency must be 44.2368MHz for

ST75C530 and 49.152MHz for ST75C540 with an

accuracy better that ±100 ppm. W hen using a third

harmonic crystal the schematic must be as follow :

see Figure 10.

The crystal features are :

- third harmonic,

- parallel, load capacitance = 10pF,

- æ 100ppm from 0oC to 70oC,

-R

< 50Ω,

- ATcut (example : SM55-10 MATEL).

XTAL H3 **

27pF

COG

0.82

H (ST75C530)

0.68µH (ST75C540)

10nF

10pF

COG

ST75C540

73 72

EXTALL XTALL

Wire wound inductor recommanded (Example : SIGMA-SC30)

Thrird harmonic (Example : MATEL-SM55-10)

XTAL H3 : 44.2368MHz (ST75C530)

49.152MHz (ST75C540)

75C53014.EPS

Figure 10

V.4.4 - T ypi cal Application Schematic

The Figure 1 1 is a block diagram designed to allow

transmission of fax signals up to +0dBm and sine

wave up to +6dBm on the telephone line. It allows

reception of fax signals up to 0dBm and sine waves

up to +6dBm. Figure 12 is a block diagram designed

V - FUNCTIONAL DESCRIPTION (continued)

-1/2

600

1:1 Line

2.2nF

+8dB

-10dB

TxA1

TxA2

RxA

75C53015.EPS

Figure 11

-1/2

600

1:1 Line

2.2nF

0dB

TxA1

TxA2

RxA

75C53016.EPS

Figure 12

to allow transmission of Modem signal up to -

10dBm and reception up to -10dBm. T he OPAmps

are +12/0V powered. With this application sche-

matic the out of band transmit spectrum (from 4kHz

to 50kHz) is below -72dBm.

Figures 13 and 14 are examples of application sche-

matics which respects gain value (respectively for fax

and voice application and for Modem application)

and the minimum differential load on TxA1 and TxA2.

V.4.5 - Host Interface

The host interface is seen by the micro as a 128x8

RAM, with additional regis ters accessible through

an 8-bit address space. A selec tion Pin (INT/MOT)

allows to configure the hos t bus for either I NTEL or

MOTOROLA ty pe control signals.

ST75C 530 - ST75C540

19/84

V - FUNCTIONAL DESCRIPTION (continued)

GND

+12V

47.5k

+6V+6V

470pF

18.2k

470nF

270pF

24k

TxA1

TxA2

1.2k

33k

24.3k

1% 470nF

560

470nF

30k

6.21k

+6V

RxA 2.2nF

VCM

+6V +6V

22nF

+6V470nF

1:1 *

* Insertion loss = 2.5dB between 0 and 3.4kHz

GND

+12V

75C53018.EPS

Figure 14 : Data Mode

GND

+12V

47.5k

+6V+6V

470pF

18.2k

470nF

270pF

56.2k

TxA1

TxA2

1.2k

10k

24.3k

1% 470nF

560

470nF

30k

6.21k

+6V

RxA 2.2nF

VCM

+6V +6V

22nF

+6V470nF

1:1 *

* Insertion loss = 2.5dB between 0 and 3.4kHz

+12V

GND

75C53017.EPS

Figure 13 : Fax Mode

ST75C 530 - ST75C540

20/84

VI - USER INTERFACE

VI.1 - Dual Port Ram Description

The dual port RAM is the standard interface be-

tween the host controller and t he ST75C530/540,

for either commands or data. This memory is ad-

dressed through a 7-bit address bus. The locations

from $00 to $3F are RAM location, while locations

from $40 to $60 ar e cont rol registers dedicated to

the interrupt handling and the general I O port and

Relay output.

Several functional areas are defined in the dual port

RAM mapping :

- the command area,

- the report area,

- the status area,

- the optional status area,

- the data buffer area,

- the interrupt control area,

- the general I/O and Relay Output area.

VI.1.1 - Mapping

VI.1.1.1 - Command Area

The command area is located from $00 to $04.

Address $00 holds the command byte COMSYS,

and the next four locations hold the parameters

COMPAR[0..3]. The command parameters must be

ent er ed be f ore the c om ma nd word is is su ed. O n ce

the command has been entered, the command byte

is reset and an acknow ledge report is issued. A new

co mmand should not be issued before the acknow-

ledge counte r CO MA C K is inc re m ent ed .

VI.1.1.2 - Report Area

The report area is located from address $05 to

address $07. Location $05 holds the acknowledge

counter COMACK. Each time a command is ac-

knowledged, the report bytes COMREP[0..1] (if

any) are written by the ST75C530/540 into loca-

tions $06 and $07, and the content of COMACK is

incremented. This counter allows the

ST75C530/540 to accurately monitor the com-

mand processing.

VI.1.1.3 - Status Area

The status area is located from address $08 to $0B.

The error status word SYSERR is located at address

$08. This err or st atus w ord i s upd ated each time an

error condition occurs. An optional interruption I T0

may additionally be triggered in the case of an error

condition. Locations $09 and $0A hold the general

stat us b ytes STATUS[0.. 1]. The meani ng of t he bits

depends on the mode of operation, and is described

in C hapter V III. T he third by te at addr ess $0 B hol ds

th e Quality Monit or by te S TAQ UA .

VI.1.1.4 - Optional Status Area

The user can program (through the DOSR com-

mand) t he four locations STAOPT[0..3] of the Op-

tional Status Area ($0C to $0F) for the real time

monitoring of four arbitrary memory locations.

VI.1.1.5 - Data Buffer Area

The data area is made of four 8-byte buffers

(see Paragraph VI.1.3 “Host Interface Summary”) .

Two are dedicated to transmission and the two

others to reception. Each of the four buffers is

attached to a status byte. the meaning of the status

byte depends on the selected format of transmis-

sion. Within each buffer, D0 represents the first bit

in time.

VI.1.1.6 - VOCO DE R Buffer Area

(VOCODER Mode)

This area is made of a 18+2 byte buffer . This buffer

contains the VOCODER frame. The first 18 bytes

VOCDATA contain the coded frame and the other

2 bytes VOCCORR the Error corrections bit (only

valid in low bit rate mode).

In the Receive Mode (CODER) the ST75C530/540

codes the received samples and writes the corres-

ponding bytes in the buffer . If the low bit rate mode

is selected, the ST75C530/540 computes the Error

corrections 2 bytes and writes them in the buffer.

In the Transmit Mode (DECODER) the

ST75C530/540 reads the 18 coded by tes decodes

them and sends the signal to the analog output. In

the low bit rate mode if the Error Correction is

enabled, prior the decoding, the ST75C530/540

reads the 2 Error Correction Bytes and, if any,

corrects the first 18 bytes.

A mechanism of flags to share the buffer access

between the ST75C530/540 and the host controller

is controlled by the VOCSTA byte :

- In CODER mode, when the ST75C530/540 has

finis-hed writing the VOCDATA and VOCCORR

bytes, it writes $14 in VOCSTA and generate an

Interrupt IT1. The host m ust read the Data buf fer

then clear the VOCSTA byte.

- In DECODER mode, the host must feed the

VOCDA T A and, optionaly , the VOCCORR bytes,

then write $14 (if low bit rate) or $12 (if ADPCM)

in VOCSTA. The ST75C530/540 will read the

VOCDATA and VOCCORR bytes, clear the

VOCSTA and generate an Interrupt IT1. A si-

lenc e frame can be genera ted, i n either low bit

rate or ADPCM mode, by writing 00 in all the

VOCDATA buffer, in cluding the Error Correction

Byt es VOCCORR.

ST75C 530 - ST75C540

21/84

VI.1.1.7 - Interrupt Control Area

The interrupt area, that start after the address $40

controls the behaviour of the Interrupts mecha-

nism. Register ITSRCR defines the source of the

interrupt, the register ITMAS K allows independent

enabling or disabling of any of the interrupt’s

source, registers ITREST0 to ITREST6 reset the

corresponding interrupt source.

These registers are not affected by a INIT command,

they are only reseted by a Hardware RESET signal.

VI.1.1.8 - General IO and Relay Output Area

A set of 5 registers is directly accessible by the

controller to program the General IO pins and

Relay Outputs (see Paragraph VI.1.3 “Host Inter-

face Summary”). Two registers IODIR0 and IO-

DIR1 define the type of the IO pin, either Input or

Output (0 = input, 1 = output), and two registers

IODATA0 and IODATA1 define the IO pin signals.

The fifth register defines the Relay output signals.

These registers are not affected by a INIT command,

they are only reseted by a Hardware RESET signal.

The general IO are setup as input after the power

up or an hardware RESET. The relay output are

open after power up or an hardware RESET.

VI.1.2 - Interruptions

The ST75C530/540 can generate 7 interrupts for

the controller. The interrupt handling is made with

a set of registers located from $40 to $5F.

The interruptions generated by the ST75C530/540

come from several sources. Once the

ST75C530/540 raises an interrupt, a signal (SINTR)

is sent to the controller. The controller has then to

process the interrupt and clear it. The interrupt source

can be examined in the interrupt source register

ITSRCR located a $50. According to the ITSRCR

bits, the interrupt source can be determined. Then

writ ing a z er o at one of the m em ory locat ion $40 to

$46 (Reset Interrupt Register ITRES[0..6]) will re-

set the corresponding interrupt (and thus acknow-

ledge it). T he sour c e of t he inter r u pt ca n be mas ked

globally or individually using the Interrupt Mast

The interrupt sources are :

- I T0 : Error

This signifies that an error has oc curred and the

error code is available in the error status byte

SYSERR. This byte can be selectively cleared by

the CSE command.

- IT1 : VOCODER Buffer

Each time the ST75C530/540 have coded a

frame (CODER Mode) o r decoded a frame (DE-

CODER Mode) this interrupt is generated.

- IT2 : Tx Buffer

Each time the ST75530/C540 frees a data buffer ,

this interrupt is generated.

- IT3 : Rx Buffer

Each time the ST75C530/540 has filled a data

buffer, this interrupt is generated.

- IT4 : Status Byte

This signifies that the status byte has changed

and must be checked by the controller.

- IT5 : Low Power Mode

The ST75C530/540 has been awakened from the

low power mode by a low level on the RING pin

or a dummy write issued by the host.

- IT6 : Command Acknowledge

This signifies that the ST75C530/540 has read

the last command entered by the host, incre-

mented the command counter COMACK, and is

ready for a new command.

Note : Interrupt r egisters are cleared after a Hard-

ware RESET. These registers are not affected by

a INIT Command.

VI - USER INTERFACE (continued)

ST75C 530 - ST75C540

22/84

SINTR

(open drain)

0123456

01234567

IT6 : Comma nd

ITREST 6

(write only)

ITSRCR

(read only)

ITMASK

(read write)

IT5 : Low Power

ITREST 5

(write only)

IT4 : Status

ITREST 4

(write only)

IT3 : Rx Buffer

ITREST 3

(write only)

IT2 : Tx Buffer

ITREST 2

(write only)

IT1 : VOCODER

Buffer

ITREST 1

(write only)

IT0 : Error

ITREST 0

(write only)

75C53019.EPS

Figure 15 : Functional Schematic

VI - USER INTERFACE (continued)

ST75C 530 - ST75C540

23/84

VI.1.3 - Host Interface Summary

Address (hex) Description Size (Byte) Mnemonic

COMMAND AREA

$00 Command 1 COMSYS

$01-$04 Command Parameters 4 COMPAR[0..3]

REPORT AREA

$05 Acknowledge Counter 1 COMACK

$06-$07 Report 2 COMREP[0..1]

STATUS AREA

$08 Error Status 1 SYSERR

$09-$0A General Status 2 STATUS[0..1]

$0B Quality Monitor 1 STAQUA

$0C-$0F Optional Report 3 STAOPT[0..3]

DATA BUFFER AREA (FAX Modes and Data Modes)

$1C Data Rx Buffer 0 Status 1 DTRBS0

$1D-$24 Data Rx Buffer 0 8 DTRBF0[0..7]

$25 Data Rx Buffer 1 Status 1 DTRBS1

$26-$2D Data Rx Buffer 1 8 DTRBF1[0..7]

$2E Data Tx Buffer 0 Status 1 DTTBS0

$2F-$36 Data Tx Buffer 0 8 DTTBF0[0..7]

$37 Data Tx Buffer 1 Status 1 DTTBS1

$38-$3F Data Tx Buffer 1 8 DTTBF1[0..7]

VOCODER BUFFER AREA (Vocoder Mode)

$1C Vocoder Buffer Status 1 VOCSTA

$1D-$2E Vocoder Buffer Data 18 VOCDATA

$2F-$30 Vocoder Buffer Corrector 2 VOCCORR

INTERRUPT AREA

$40-$46 Reset Interrupt Register 7 ITREST[0..6]

$4F Interrupt Mask Register 1 ITMASK

$50 Interrupt Source Register 1 ITSRCR

GENERAL IO AND RELAY

$60 I/O Direction 0 1 IODIR0

$61 I/O Direction 1 1 IODIR1

$62 I/O Data 0 1 IODATA0

$63 I/O Data 1 1 IODATA1

$64 I/O Relay Register 1 IORELAY

Note : Registers which address is higher or equal to $40 are not affected by a INIT Command or a Low Power wake-up. They are reseted

only by a Hardware RESET.

VI - USER INTERFACE (continued)

ST75C 530 - ST75C540

24/84

VI.2 - Comm and Set

The Command Set has the following attractive

features :

- user friendly with easy to remember mnemonics,

- possibility of straightforward expansion with new

commands to suit specific customer require-

ments,

- easy upgrade of existing software using previous

modem based SGS-THOMS ON products.

The command set has been designed to provide the

nec essary fun ctional control on the ST75C530/540.

Eac h co mm a nd is classified accord ing to its sy n ta x

and the presence/absence of parameters. In the

case of a parametric command, parameters must

first be written into the dual port RAM before the

command is issued. Acknowledge and error report

is is s ued fo r ea ch co mmand entere d.

VI.2.1 - Comman d Set Summ ary

VI.2.1.1 - Operational Control Commands

INIT Initialize. Initialize the modem engine.

Set all parameters to their default values

and wait for commands of the control

processor. Non parametric command.

IDT Identify . Ret urn the pr oduct identification

code. Non parametric command.

SLEEP Turn to low power mode, the

ST75C530/540 enters the low power

mode and stops its crystal oscillator to

reduce power consumption. In this mode

all the clocks are stopped and the dual

RAM is unreachable.

HSHK Handshake. Begins the handshake

sequence. The modem engine generates

all the sequences defined in the ITU-T

recommendations. A status report

indicates to the control processor the state

of the handshake. This command only

applies to modes where a handshake

sequ ence is def ine d. A CON F comma nd

mu st h ave be en is s ued p rio r to t he u se of

HSHK. Non parametric command.

STOP FAX Stop. Stop FAX Half-duplex

transmitter. Non parametric command.

RTRA Retrain. Begin a retrain sequence in

V.32bis/V.32 or V.22bis modes as

described in the ITU-T

recommendations (ST75C540 only).

SYNC FAX Synchronize. Start/Stop of FAX Half-

duplex re ce iv er. Para me tric c om m and .

CSE Clear Status Error. Selectively clears the Error

status byte SYSERR. Parametric command.

SETGN Set Gain. This comm and s ets the global

gain factor, which is used for the transmit

samples. Parametric command.

VI.2.1.2 - Data Commu nication Commands

XMIT Transmit Data. Start/stop the

transmission of data. After a XMIT

command, the ST75C530/540 sends the

data contained in its dual port RAM.

FORM Selects the Transmission Format. This

command configures the data interface

for both receiver and transmitter

according to the selected data format.

Parametric command (HDLC, UART or

synchronous).

VI.2.1.3 - Memory Handling Commands

MWI

MWLO

Memory Write Indirect

Memory Write Low W ord

Memory Wr ite. This command is used to

write an arbitrary 16-bit value into the

writable memory location currently

specified by a parameter. Parametric

command.

MRI

MRLO

Memory Read Indirect

Memory Read Low Word

Memory Read. This command allows the

controller to read any of the ERAM or

CROM (ST75C530/540 memory

spaces) location without interrupting the

processor. Parametric command.

CR Complex Read. This command allows

th e cont roller to re ad at the same time

the real and imaginary part of a complex

value stored in a double ERAM or

CROM location. This feature is very

interesting for eye pattern software

co ntrol an d fo r equal izatio n monit ori ng.

This command insures that the real and

imaginary parts are sampled in the

memory at the same time (integrity).

Parametric command.

VI - USER INTERFACE (continued)

ST75C 530 - ST75C540

25/84

VI.2.1 .4 - Config ur a tion Control Com mands

ASEL Select the Analog path option, like

Microphone input, Speaker attenuation.

Parametric command.

CONF Configure. This command c onfigures the

modem engine for data transm ission and

handshake procedures (if any) in any of

the supported modes. The transmission

parameters are set to their default values

and can be modified with the MODC

command. Parametric command.

MODC Modify Configuration. This command

allows modification of some of the

parameters which have been set up by

the CONF command. It c an als o be used

to alter the mode of operations (short

train). Parametric command.

DOSR Define Optional Status Report. This

command allows the modification of the

optional status report located in the status

area of the dual port RAM. One can thus

select a particular parameter to be

monitored during all modes of operation.

Parametric command.

DSIT Define Status Interrupt. This command

allows the programming of the status

word bit that will generate an Interrupt to

the controller . Parametric command.

VI.2.1.5 - Tone Generation Commands

TONE Select Tone. Programs the tone generator(s)

for the desired default tone(s). Additional

mnemonics provide quick programming of

DTMF tones or other currently used tones.

Parametric command.

DEFT Define Tone. Programs the tone

generator(s) f or arbitrary tone s ynthesis.

Parametric command.

TGEN Tone Generator Control. Enables or

disables the tone generator(s).

Parametric command.

VI.2.1 .6 - To ne Det e c tion Commands

TDRC Read Tone Detector Coefficient. Read

one Tone Detector Coefficient.

Parametric command.

TDWC Write Tone Detector Coefficient. Write

one Tone Detector Coefficient.

Parametric command.

TDRW Read Tone Detector Wiring. Read one

Tone Detector Wiring connection.

Parametric command.

TDWW Write Tone Detector Wiring. Write one

Tone Detector Wiring connection.

Parametric command.

TDZ Clear Tone Detector Cell. Clear internal

variables of a Tone Detector Cell.

Parametric command.

VI.2.1.7 - Miscell aneous Commands

CALL Call a Subroutine. Call a subroutine with

one Parameter. Parametric command.

JSR Call a Low Level Subroutine. Call an

internal subroutine with one parameter.

Parametric command.

VI.3 - Command Set Short Form

CCI Command

Mnemonic Value Description

XMIT 0x01 Transmit Data

SETGN 0x02 Set Transmit Gain

SLEEP 0x03 Power Down the ST75C530/540

HSHK 0x04 FAX Start Transmitter

RTRA* 0x05 Re train (V .32b is /V. 32 an d V. 22 bi s)

INIT 0x06 Initialize (Software Reset)

CSE 0x08 Clear Error Status Word

FORM 0x09 Define Data Format

DOSR 0x0A Define Optional Status Report

ASEL 0x0B Select the Analog Path Options

TONE 0x0C Generate Predefined Tones

TGEN 0x0D Enable Tone Generator

DEFT 0x0E Define Arbitrary Tone

MR 0x10 Memory Read

CR 0x11 Complex Read

MW 0x12 Memory Write

DSIT 0x13 Define Status Interrupt

IDT 0x14 Return Product Identification Code

JSR 0x18 Call a Low Level Routine

CALL 0x19 Call a Routine

TDRC 0x1A Tone Detector Read Coefficient

TDRW 0x1B Tone Detector Read Wiring

TDWC 0x1C Tone Detector Write Coefficient

TDWW 0x1D Tone Detector Write Wiring

TDZ 0x1E Tone Detector Clear Cell

CONF 0x20 Configure

MODC 0x21 Modify Default Configuration

STOP 0x25 FAX Stop Transmitter

SYNC 0x26 FAX Synchronize Receiver

MRI 0x28 Memory Read Indirect

MRLO 0x29 Memory Read Low Word

MWI 0x2A Memory Write Indirect

MWLO 0x2B Memory Write Low Word

* ST75C540 only.

VI - USER INTERFACE (continued)

ST75C 530 - ST75C540

26/84

VI.4 - Status - Reports

VI. 4.1 - Sta t u s

The ST75C530/540 has a dedicated status report-

ing area located in its dual port RAM. This allow a

continuous monitoring of the status variables with-

out interrupting the ST75C530/540.

The first status byte gives the error status. Issui ng

of an error status can also be flagged by a mask-

able interrupt for the controller. The signification of

the error codes are given in Chapter VIII.

The second and third status bytes give the general

status of the modem. These status include for

example the ITU-T circuit status and other items

described in Chapter VIII “STATUS DESCRIP-

TION”. These two status can generate, when a

change occurs, an interrupt to the controller ; each

bit of the two byte word can be masked inde-

pendently.

The forth byte gives in real time a measure of the

reception quality . This information may be used b y the

contr oller to mon itor the qu ality of the rec eived bits .

Four other locations are dedicated for custom

status reporting. The controller can program the

ST75C530/540 for a real time monitoring of any of

its internal RAM location. High byte or low byte of

any word can thus be monitored.

VI.4.2 - Reports

The ST75C530/540 features an acknowledge and

report facility. The acknowledge of a command is

monitored by a counter COMACK located in the

dual port RAM . Each time a com mand is read from

the command area, the ST75C530/540 will incre-

ment this counter . For instance, when a MR (Mem-

ory Read) command is issued, the data is first

written in the report area, and the counter is incre-

mented afterwards. This way of processing insures

data integrity and gives additional synchronizati on

between the contr oller and the da ta pump.

VI.5 - Data Exchanges

The ST75C530/540 accepts many kinds of data

exchange : the default mode uses the synchronous

parallel exchange. Other modes include HDLC

framing support and UAR T. Detailed description of

the Data Buffer Exchanges modes is available in

the paragraph X.

VI.5.1 - Synchronous Parallel Mode

The data exchanges are made through the dual

port RAM and are by te synchronous oriented. The

double buffer facilities of the ST75C530/540 allow

an efficient buffering of the data.

VI.5.1.1 - Transmit

The controller must first fill at least the first buffer

of data (Tx Buf fer 0) with the bits to be transmitted.

In order to perform this operation, the controller

must first check the Tx Buffer 0 status word

DTTBS0. If this buffer is empty, the controller fills

the data buffer locations (up to 64 bits), and then

writes in DTTBS0 the number of bytes contained in

the buffer. The controller can then either proceed

with the second buffer or initiate the transmission

with a XMIT command.

The ST75C530/540 copies the contents of the data

buffer and then clears the buffer status word in

order to make it again available, then generates an

IT2 interrupt. The number of bytes specified by the

status word is t hen queued for transmission. The

process goes on with the two buf fers until an XMIT

command stops t he transmission. After t he finish-

ing XMIT command has been issued, the last buff-

ers are emptied by the ST75C530/540.

Errors occur when both buffers are empty while the

transmit bit queue is also empty. Error is signalled

with an IT0 interruption to the controller .

VI.5.1.2 - Receive

The controller should take care of releasing the Rx

buffers before the Data Carrier Detect goes true.

This is made by writing zero in the Rx Buffer Status

0 and 1. The ST75C530/540 then fills the first

buf fer, and once filled sets the status word with t he

number of bytes received and then generates an

IT3 interrupt. It then takes control of the second

buffer and oper ates the same way. The controller

must check the status of the buffers and empty

them. Once the data read, the controller must

release the used buffer and wait for the next buffer

to be filled.

Error occurs when both buffers are declared full,

and incoming bits continue to arrive from the line.

Error is signaled by an IT0 interru pt.

VI.5.2 - HDLC Parallel Mode

This m ode implem ents part of t he High Level Dat a

Link Control formats and procedures. It is well

suited for error correcting protocols like ECM or

FAX T4/T30 recommendations. It supports the flag-

ging generation, 16-bit Frame Check Sequence, as

well as the Zero insertion/deletion mechanism.

VI.5.3 - UART Parallel Mode

This mode implement a 7 or 8 bit data format, it is

well suited for Caller ID or Minitel applications.

VI - USER INTERFACE (continued)

ST75C 530 - ST75C540

27/84

VII - COMM A N D SET DESCRIPTION

Commands are presented acco rding to the following form :

COMMAND Co mmand Name Mean ing COMMAND

Opcode Hexadecimal digit

XXXXXXXX

Synopsis Short description of the functions perf ormed by the command.

Parameters Field Byte Pos. Value Definition

Name X b..a xx * Explanation of the parameter

Default value

Field Name of the addressed bit field.

Byte Index (or address in the dual port RAM) of the parameter byte (from 1 to 4).

Pos. Bit field position inside the parameter byte. Can either be a single position (from 0 to 7, 0

being LSB) or a range.

V alue P ossible val ues for the bit (resp. bit field ). Ran ge means all va lues are al lowed. A sta r means a defau lt

value. V alues are expressed either under the form of a bit string, or under hexadecimal format.

ASEL ASEL

Opcode: 0B 00001011

Synopsis Select the analog path options. This command select the Attenuation/Mute of the outputs

TxA1/TxA2 and SPK1/SPK2/SPK3. This c ommand select als o the source of the Mic signal

MIC1/MIC2/MIC2 and the source of the Line Signal RxA/MIC3.

Parameters Field Byte Pos. Value Definition

ASEL_ASPK1 1 7..4 0000*

0001

0010

...

1010

1011

Other

Infinity attenuation

30dB attenuation

27dB attenuation

...

3dB attenuation

0dB attenuation

Reserved

ASEL_MICSEL 2 1..0 00*

Select Rx input as MIC1

Select Rx input as MIC2

Select Rx input as MIC3

ASEL_LINESEL 2 2 0*

1Select RxA as line input

Select Mic3 as line input

ASEL_ESPK1 2 3 0*

1SPK1 output muted

SPK1 output normal

ASEL_ESPK2 2 4 0*

1SPK2 output muted

SPK2 output normal

ASEL_ESPK3 2 5 0*

1SPK3 output muted

SPK3 output normal

ASEL_MTXA 2 7 0*

1TxA output normal

TxA output muted

CALL Call a Subroutine CALL

Opcode: 19 00011001

Synopsis CALL allows to execute a part of the ST75C530/540 firmware with a specific argument.

Parameters Field Byte Pos. Value Definition

C_ADDR_L 1 7..0 Low byte of the call address

C_ADDR_H 2 7..0 High byte of the call address

C_DATA_L 3 7..0 Low byte of the argument

C_DATA_H 4 7..0 High byte of the argument

This instruction can be used with SGS-THOMSON Microelectronics Application Laboratory Support for

special applications development or debugging needs. Contact your local representative.

ST75C 530 - ST75C540

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CONF Configure for Operations CONF

Opcode : 20 00100000

Synopsis CONF allows the complete definition of the ST75C530/540 operation, including the mode of

operation (Tone, F A X Transmit, Voice Transm it, Voice Receive, DTMF Rec eiver, ...) and the

Modem or Vocoder Parameters (Standard, speed, ...). According with the 4 first bits of the

CONF Parameter the ST75C530/540 is put into the following mode of operation.

CONF_

OPER Mode Detectors

Tone (2) Tone (3) DTMF Ring VAD V.21 Flag CPT (5) Answ (6)

0000*

0001

0010

0100

1000

1001

1100

1111

Other

TONE

TONECID(1)

DECODER

TRANSPARENT

CODER

ROOM-MONITOR

HANDSET/HANDSFREE

MODEM

Reserved

4 (7)

Yes

Yes (4)

Yes

Yes (4)

Yes

Notes : 1.This mode includes V.23/Bell202 FSK Demodulator and UART.

2.This primary Tone Detectors allows Detection of signal up to 3.3kHz. (Sampling Rate 7.2kHz).

3. This secondary Tone Detectors allows Detection of signal up to 1.8kHz (with Sampling Rate 4.8kHz) or up to 3.3kHz (with Sampling Rate 9.6kHz).

4.The DTMF detector and Call Progress Tone detector (CPT) are available only for V.21 Channel 2.

5.STA_CPT0, STA_CPT1 and STA_CPT10 in STATUS0.

6.STA_CCITT an d S T A_ AT in ST A T US 1 .

7.Not available in V.32bis /V .32.

VII - COMM AN D SET DES CRIPTION (continued)

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Parameters When the CONF_OPER is s et to F, selecting the Modem Mode of operation, the parameters

have the following meaning :

Field Byte Pos. Value Definition

CONF_OPER 1 3..0 1111 Select Modem Mode

CONF_ANAL 1 4 0

1Normal mode

Analog loop back (test mode only)

CONF_PSTN 1 5 0

1PSTN (carrier detect set to -43/-48dBm)

Leased line (carrier detect -33/-38dBm)

CONF_AO 1 6 0

1Answer mode

Originate mode

CONF_DTINIT

(only in tone mode) 170

Global init of secondary tone detector

Partial init of secondary tone detector (8)

CONF_MODE 2 5..0 0

Other

Automode (V.32bis/V.32/V.22bis/V.22) (9)

Bell 103 (full duplex)

Bell 212A (full duplex) (9)

V.21 (full duplex)

V.23 (full duplex)

V.22 (full duplex) (9)

V.22bis (full duplex) (9)

V.27ter

V.29

V.17

V.32 (full duplex) (9)

V.32bis (full duplex) (9)

V.33 (half duplex)

V.21 channel 2

Reserved

CONF_TXEQ 2 7..6 0

No transmit equalizer

Transmit equalizer #1

Transmit equalizer #2

Transmit equalizer #3 (V.17/V.33/V.29/V.27ter)

CONF_CAR 3 0 0

11800Hz carrier (V.17/V.33 only)

1700Hz carrier (V.17/V.33 only)

CONF_TCM 3 1 0

1Treillis coding not allowed (V.32 only)

Treillis coding allowed (V.32bis, V.32)

CONF_SP0 3 7..4 xxx1

xx1x

x1xx

1xxx

1200bps allowed (V.22, V.22bis) (10)

2400bps allowed (V.22bis, V.27) (10)

4800bps allowed (V.32bis, V.32, V.27, V.29) (10)

7200bps allowed (V.32bis, V.29, V.17) (10)

CONF_SP1 4 2..0 xx1

x1x

1xx

9600bps allowed (V.32bis, V.32, V.29, V.17) (10)

12000bps allowed (V.32bis, V.17, V.33) (10)

14400bps allowed (V.32bis, V.17, V.33) (10)

Notes : 8. With conf 80 00 00 00 the coefficients of secondary tone detectors are not initialized.

9. ST75C540 only.

10. V.22b is, V.22, V.32bis and V.32 modes ST75C540 onl y.

VII - COMM AN D SET DES CRIPTION (continued)

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Parameter s C O D E R and DECODE R M o des

In the VOCODER Modes , eit her CODER o r DECODER, (CONF_OPER equals 2 or 8) t he

parameters have the following meaning :

Field Byte Pos. Value Definition

CONF_OPER 1 3..0 - Define mode : see table above

CONF_CODE 3 0 0

1Low bit rate coded

ADPCM coded

CONF_VPF 3 1 0

1Decoder post filter off

Decoder post filter on (not in ADPCM)

CONF_VASP 3 3..2 00

ADPCM 32000 bps

ADPCM 24000 bps

ADPCM 16000 bps

Reserved

CONF_EC 3 4 0

1Line echo canceller disabled

Line echo canceller enabled

CONF_SRC 3 5 0

1Coder source is line input

Coder source is audio input

CONF_SUPSIL 3 6 0

1Coder silence supressor disabled

Coder silence supressor enabled

CONF_ERCOR 3 7 0

1Low bit rate decoder disable error correction

Low bit rate decoder enable error correction

Parameters ROOM-MONITOR Mode

In the ROOM MONITOR Mode (CONF _OPER equa ls 9) t he parame ters have the f ollowing

meaning :

Field Byte Pos. Value Definition

CONF_OPER 1 3..0 1001 Define ROOM-MONITOR mode

CONF_EC 3 4 0

1Line echo canceller disabled

Line echo canceller enabled

Parameter s H ANDSE T/HANDSFRE E Mode

In the HANDSET/HANDSFREE mode (CONF_OPER equals C), the parameters have the

following meaning :

Field Byte Pos. Value Definition

CONF_OPER 1 3..0 1100 Define HANDSET/HANDSFREE mode

CONF_INHINI 3 6 0

1Init all telephony parameters

Disable init of telephony parameters

CONF_HFREE 3 7 0

1Handset mode

Handsfree mode

CONF_LEC 4 0 0

1Line echo canceller enabled

Line echo canceller disabled

CONF_AEC 4 1 0

1Audio echo canceller enabled

Audio echo canceller disabled

CONF_FULLD 4 2 0

1Full duplex mode enabled

Half duplex mode enabled

CONF_SOFTRx 4 3 0

1Softclipping enabled on Rx

Softclipping disabled on Tx

CONF_AGC 4 4 0

1AGC active

AGC frozen

CONF_SOFTTx 4 5 0

1Softclipping enabled on Tx

Softclipping disabled on Rx

VII - COMM A N D SET DESCRIPTION (continued)

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CR Complex Read CR

Opcode: 11 00010001

Synopsis CR allows the reading of a complex parameter. The parameter specifies the parameter address (for

the real part : t he imaginary par t i s nex t lo c ation). CR returns the h igh byte value of both real and

imagina ry part o f the addre ssed co mplex para meter ( see Cha pter VIII “S T ATUS DES CRIP TION ”).

Parameters Field Byte Pos. Value Definition

CR_ADDR_L 1 7..0 Low byte of the 16-bit address

CR_ADDR_H 2 7..0 High byte of the 16-bit address

CSE Clear Error Status CSE

Opcode: 08 00001000

Synopsis CSE is used to clear the ST75C530/540 error status SYS ERR byte. It is also used as an

acknowledge to the error condition handler.

Parameters Field Byte Pos. Value Definition

ERR_MASK 1 7..0 Error mask. See report appendix for detailed meaning

DEFT Define Arbitrary Tone DEFT

Opcode: 0E 00001110

Synopsis DEFT programs one of the four tone generator for arbitrary tone generation. The parameter

is the frequency of the generated tone expressed in Hertz between 0 and 3600Hz.

Parameters Field Byte Pos. Value Definition

TONE_GEN_SL 1 1..0 Index of the tone generator (3..0)

TONE_FREQ_L 2 7..0 Low byte of the frequency

TONE_FREQ_H 3 7..0 High byte of the frequency (internally masked with 0F)

TONE_SCALE 4 7..0 Amplitude scaling factor (high byte)

3F gives the nominal amplitude

DOSR Define Optional Status Report DOSR

Opcode: 0A 00001010

Synopsis DOSR specifies the address of the RAM variables to be monitored in the 4 locations

STAOPT[0..3] of the dual port RAM. It also s pecifies the assignment within the 4 locations.

Parameters Field Byte Pos. Value Definition

STA_OPT_ASS 1 1..0 0..3 Index of the STAOPT destination

STA_OPT_ADL 2 7..0 Low byte of source address

STA_OPT_ADH 3 3..0 High byte of source address

STA_OPT_HL 3 7 0

1Select low byte of source

Select high byte of source

VII - COMM A N D SET DESCRIPTION (continued)

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DSIT Define Status Interrupt DSIT

Opcode: 13 00010011

Synopsis DSIT specifies the bit mask used with the STATUS[0] and STATUS[1] byte to generate an

interrupt IT4 to controller. Each time a bit change happens in the status words, assuming

the corresponding bit mask will be set, an interrupt will be generated.

Parameters Field Byte Pos. Value Definition

STA_IT_MSK0 1 7..0 Status[0] bit mask pattern

STA_IT_MSK1 2 7..0 Status[1] bit mask pattern

Note : The default IT Status is 0x3F for ST ATUS[0] and 0xFF for STATUS[1].

FORM Select Transmission Format FORM

Opcode: 09 00001001

Synopsis FORM defines the type of transmission used on the line.

Parameters Field Byte Pos. Value Definition

X_SYNC 1 2..0 000*

001

010

011

100

Synchronous format

Transmit continous “1" (1)

HDLC framing

Transmit continous ”0" (1)

UART

X_ANBIT 2 1..0 00

01 7 Bit per character

8 Bit per character

X_APAR 2 3..2 00

No parity

Even parity

Odd parity

X_ASTOP 2 5 0

11 stop bit(1)

2 stop bit(1)

Note : 1. Va lid only when tr ansm i tti ng.

HSHK Handshake HSHK

Opcode: 04 00000100

Synopsis HSHK is used to command the ST75C530/540 to begin the tr ansmit handshake sequence

processing. The progress of the handshake is reported to the control processor.

Parameter Non parametric command.

VII - COMM A N D SET DESCRIPTION (continued)

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IDT Identify IDT

Opcode: 14 00010100

Synopsis IDT Return the ST75C530/540 Hardware and Software release number. See paragraph VIII.1.4.

Parameter Non parametric command.

INIT Initialization INIT

Opcode: 06 00000110

Synopsis INIT forces the ST75C530/540 to reset all parameters to their default conditions and restart

operations.

Parameter Non parametric command.

Note : This command makes a software reset of the ST75C530/540 and so cannot have the regular handshake protocol. It

does not increment the COMACK, neither generate an Interrupt.

JSR Call a Low Level Subroutine JSR

Opcode: 18 00011000

Synopsis JSR allows to execute a part of the ST75C530/540 firmware with a specific argument.

Parameters Field Byte Pos. Value Definition

C_ADDR_L 1 7..0 Low byte of the call address

C_ADDR_H 2 7..0 High byte of the call address

C_DATA_L 3 7..0 Low byte of the argument

C_DATA_H 4 7..0 High byte of the argument

This instruction can be used with SGS-THOMSON Microelectronics Application Laboratory Support for

special applications development or debugging needs. Contact your local representative.

VII - COMM A N D SET DESCRIPTION (continued)

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MODC Modify Configuration MODC

Opcode: 21 00100001

Synopsis MODC allows the modification of the parameters defined by the CONF command.

Parameters Field Byte Pos. Value Definition

MODC_SDM 1 0 0

1Normal data mode

Short data mode (e.g. TVR) (5)

MODC_DV21F 1 1 0

1Normal V.21ch2 (1)

Disable V.21ch2 flag detector

MODC_DDTMF 1 2 0

1Normal DTMF detector (1)

Disable DTMF detector

MODC_DTDT4 1 3 0

1Normal secondary tone detector (1)

Disable secondary tone detector

MODC_DTDT16 1 4 0

1Normal primary tone detector (1)

Disable primary tone detector

MODC_SH 1 6 0*

1Normal training sequence

Short training sequence (2)

MODC_FS 1 7 0*

1Secondary tone detector sampling frequency is 4.8kHz

Secondary tone detector sampling frequency is 9.6kHz

MODC_V22G (6) 2 1..0 00*

No guard tone

1800Hz guard tone (V.22bis/V.22)

550Hz guard tone (V.22bis/V.22)

MODC_FPT 2 3..2 00*

No echo protection tone

Long echo protection tone (180ms) (4)

Short echo protection tone (30ms) (4)

MODC_NOTA (6) 240*

Answer mode : generate answer tone for handshake

Originate mode : wait answer tone for handshake

Answer mode : do not generate answer

Originate mode : do not wait answer tone

MODC_NOSA (6) 260*

Cut answer tone when receiving AA (V.32bis, V.32)

Continue answer tone when receiving AA.

MODC_NOQA (6) 270*

Enable V.32bis/V.32 autoretrain on quality.

Disable V.32bis/V.32 autoretrain on quality.

MODC_ADCFD 3 0..3 0000*

0001

0010

0011

1111

1110

1101

0111

Other

Low bit rate decoder voice frame duration 30ms (nominal)

Low bit rate decoder voice frame duration 35ms (+16%)

Low bit rate decoder voice frame duration 40ms (+33%)

Low bit rate decoder voice frame duration 45ms (+50%)

Low bit rate decoder voice frame duration 25ms (-16%)

Low bit rate decoder voice frame duration 20ms (-33%)

Low bit rate decoder voice frame duration 15ms (-50%)

Low bit rate decoder pause

Reserved

MODC_COD 3 5 0

1Low bit rate coder disabled

Low bit rate coder enabled(3)

MODC_LEC 4 0 0

1Line echo canceller enabled

Line echo canceller disabled

MODC_AEC 4 1 0

1Audio echo canceller enabled

Audio echo canceller disabled(3)

MODC_FULLD 4 2 0

1Full duplex mode enabled

Half duplex mode enabled

MODC_SOFTRx 4 3 0

1Softclipping enabled on Rx

Softclipping disabled on Rx

MODC_AGC 4 4 0

1AGC active

AGC frozen

MODC_SOFTTx 4 5 0

1Softclipping enabled on Tx

Softclipping disabled on Tx

Notes : 1. In the modes where they are active.

2. Short train sequence must be preceded by at least one successful long train sequence at the same data rate. For

V.17 a successful long train at any data rate must preceded the short train.

3. Only coder or decoder can be enabled at the same time.

4. Only when sending V.17, V.33, V.29 or V . 27ter.

5. French Minitel Application (TVR : Teletel Vitesse Rapide).

6. ST75C540 only

VII - COMM A N D SET DESCRIPTION (continued)

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MR Memory Read MR

Opcode: 10 00010000

Synopsis MR allows the reading of a 16-bit parameter. The parameter specifies the parameter address.

Parameters Field Byte Pos. Value Definition

MR_ADDR_L 1 7..0 Low byte of the 16-bit address

MR_ADDR_H 2 7..0 High byte of the 16-bit address

MRI Memory Read Indirect MRI

Opcode: 28 00101000

Synopsis MRI allows the reading of a 16-bit parameter. The parameter specifies an indirect address.

Refer to the “RAM Mapping Application Note” (delivered on request according to revision

number). The advantage t o us e MRI instead of MR is that the Indirect Address is constant

over the different release of the product.

Parameters Field Byte Pos. Value Definition

MRI_IADDR 1 7..0 Indirect Address

MRLO Memory Read Low Word MRLO

Opcode: 29 00101001

Synopsis MRLO allows the reading of the memory location which address coresponds to the previous

MR or MRI Absolute Adress minus 1. This command must be preceded by a MR or MRI

command. This command does not have any parameter. The double word reading is

executed by the MR or MRI previous command.

MW Memory Wri t e MW

Opcode: 12 00010010

Synopsis MW allows the writing of a 16-bit parameter. The paramet er specifies the address as well

as the value to be transferred.

Parameters Field Byte Pos. Value Definition

MW_ADDR_L 1 7..0 Low byte of the 16-bit address

MW_ADDR_H 2 7..0 High byte of the 16-bit address

MW_VALUE_L 3 7..0 Low byte of the 16-bit value

MW_VALUE_H 4 7..0 High byte of the 16-bit value

VII - COMM A N D SET DESCRIPTION (continued)

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MWI Memory Write Indirect MWI

Opcode: 2A 00101010

Synopsis MWI allows the writing of a 16-bit parameter . The parameters specifies an indirect address as w ell

as the v alue to be transferred. Refer to the “RAM Mappi ng Application Note” (delivered on request

according to revision number). The advantage to use MWI instead of MW is that the Indirect Address

is con stant over the diff erent rel ease of the prod uct.

Parameters Field Byte Pos. Value Definition

MWI_IADDR 1 7..0 Indirect address

MWI_IVALUE_L 2 7..0 Low byte of the 16-bit value

MWI_IVALUE_H 3 7..0 High byte of the 16-bit value

MWLO Memor y Write Low Wor d MWLO

Opcode: 2B 00101011

Synopsis MWLO allows the writing of a 16-bit parameter at the address defined by the following MW

or MW Absolute Address minus 1. This command must be followed by a MW or MWI

command.The double word writing is executed by the MW or MWI following command.

Parameters Field Byte Pos. Value Definition

MWLO_VALUE_L 1 7..0 Low byte of the 16-bit value

MWLO_VALUE_H 2 7..0 High byte of the 16-bit value

RTRA ( ST75C540 only) Retrain RTRA

Opcode: 02A 00000101

Synopsis RTRA is used to force the ST75C530/540 to initiate a retrain sequence or a rate negotiation.

If MODC_NOQUA bit is set, the ST75C530/540 will initiate a transmission at the maximum

speed defined by the RTRA parameter , otherwise it w ill found the best reliable speed bas ed

on the quality of the line (within the RTRA allowed speed).

Parameters Field Byte Pos. Value Definition

RTRA_NEG0 1 0 0

1Retrain (V.22bis, V.32, V.32bis)

Ratr negotiation (V.32bis, V.22bis)

RTRA_SP0 1 7..4 xxx1

xx1x

x1xx

1xxx

1200bps allowed (V.22bis)

2400bps allowed (V.22bis)

4800bps allowed (V.32bis, V.32)

7200bps allowed (V.32bis)

RTRA_SP1 2 2..0 xx1

x1x

1xx

9600bps allowed (V.32bis, V.32)

12000bps allowed (V.32bis)

14400bps allowed (V.32bis)

VII - COMM A N D SET DESCRIPTION (continued)

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SETGN Set Output Gain SETGN

Opcode: 02 00000010

Synopsis SETGN is a command which sets the scaling factor of the transmit samples. It is used for

setting the output level or for setting the level of the tone generators. The gain value is given

in the form of a 2’s complement 16-bit value.

Parameter Field Byte Pos. Value Definition

GAIN_L 1 7..0 range FF* Low byte of the 16-bit gain value

GAIN_H 2 7..0 range 7F* High byte of the 16-bit gain value

Example

Gain (dB) Gain (Hex) Gain (dB) Gain (Hex) Gain (dB) Gain (Hex)

0 7FFF -5 47FA -10 287A

-1 7214 -6 4026 -11 2413

-2 65AC -7 392C -12 2026

-3 5A9D -8 32F5 -13 1CA7

-4 50C3 -9 2D6A -14 198A

The multiplication factor i s : 10(-1/20) = 0.89125 for 1dB step.

SLEEP Turn to Sleep Mode SLEEP

Opcode: 03 00000011

Synopsis S LEEP is used to fo rce t he ST 75C530/540 to turn to lo w power mo de.

Parameter Non parametric command.

Note : When receiving this command the ST75C530/540 will stop processing and so cannot have the regular handshake protocol.

It does not increment the COMACK, neither generate an Interrupt.

STOP FAX Stop Transmitter STOP

Opcode: 25 00100101

Synopsis STOP is used, in FAX Modes, to force the ST75C530/540 to turn off the transmitter in

accordance with the corresponding ITU-T V.33/V.17/V.29/V.27 recommendation.

Parameter Non parametric command.

Note : Wh en receiving this command th e ST75C530/ 540 wil l stop s endi ng regul ar Dat a. Thi s command m ust be precede d by a

XMIT Stop command. The ST75C530/540 will wait un til all the tran smit buff ers are sent befo re starti ng the Stop sequence.

SYNC FAX Synchronize the Receiver SYNC

Opcode: 26 00100110

Synopsis SYNC is used, in FAX Modes, to force the ST75C530/540 to Start/Stop the receiver in

accordance with the corresponding ITU-T V.33/V.17/V.29/V .27 recommendation.As soon as

the ST75C530/540 receives the SYNC Start command it sets its receiv er to detect the FAX

synchronization signal.This command is the equivalent HSHK c ommand for the receiver.

Parameters Field Byte Pos. Value Definition

RX_SYNC 1 0 0*

1 Stop receiver

Start receiver synchronization

VII - COMM A N D SET DESCRIPTION (continued)

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TDRC Tone Detector Read Coefficient TDRC

Opcode: 1A 00011010

Synopsis TDRC Read one Coefficient of the selected Tone Detector Cell.

Parameters Field Byte Pos. Value Definition

TD_CELL 1 4..0 0..13 Tone detector cell number

TD_C_ADDR 2 7..0 0..B

30 (1)

40 (1)

Biquad co efficient

Energy coefficient

Static level

Energy coefficient for relative comparison

Gain for relative comparison

The command answer is : Low Byte of Coefficient followed by High Byte of Coefficient.

Note 1 : Value 30 and 40 of byte 2 are available only for secondary tone detector.

TDRW Tone Detector Read Wiring TDRW

Opcode: 1B 00011011

Synopsis TDRW Read Wiring of the selected Tone Detector Cell.

Parameters Field Byte Pos. Value Definition

TD_CELL 1 4..0 0..13 Tone detector cell number

For primary tone detector

TD_W_ADDR 2 0 0

Other

Biquad and energy input

Comparator inputs

Reserved

The command answer is :

a) If TD_W_ADDR = 0 :

- First Byte is the Node Num ber of the Signal connected to Biquadrat ic Filter input.

- Second Byte is the Node Number of the Signal connected to the Energy estimator input.

b) if TD_W_ADDR = 1 :

- First Byte is the Node Num ber of the Signal connected to Comparat or Negative input.

- Se cond By te i s the No de Num ber of t he S ignal c onnec ted to the Com para tor P ositiv e inp ut.

For secondary tone detector TD_W_ADDR is not defined.

- First byte is 00 if relative comparison is not mandatory,

First byte is 01 if re lative comparison is mandatory.

- Second byte is for the configuration of the secondary tone detector :

C0 configuration 1+1 of secondary tone detectors,

E0 configuration 1+1+2,

F0 configuration 1+1+1.

VII - COMM A N D SET DESCRIPTION (continued)

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TDWC Tone D e tec tor Write Coefficient TDWC

Opcode: 1C 00011100

Synopsis TDWC Wr ite one Coefficient of the selected Tone Detector C ell.

Parameters Field Byte Pos. Value Definition

TD_CELL 1 4..0 0..13 Tone detector cell number

TD_C_ADDR 2 7..0 0..B

30 (1)

40 (1)

Biquad co efficient

Energy coefficient

Static level

Energy coefficient for relative comparison

Gain for relative comparison

TD_COEFL 3 7..0 Low byte of coefficient

TD_COEFH 4 7..0 High byte of coefficient

Note 1 : Value 30 and 40 of byte 2 are available only for secondary tone detector.

TDWW Tone Detector Write Wiring TDWW

Opcode: 1D 00011101

Synopsis TDWW Write Wiring of the selec ted Tone Detector Cell.

Parameters Field Byte Pos. Value Definition

TD_CELL 1 4..0 0..13 Tone detector cell number

For Primary Tone Detector

Field Byte Pos. Value Definition

TD_W_ADDR 2 0 0

Other

Biquad and energy input

Comparator inputs

Reserved

If TD_W_ADDR = 0 (Select Biquad and Energy Inputs)

Field Byte Pos. Value Definition

TD_W_ERN 3 0..3F Energy estimator signal input

TD_W_BIQ 4 0..3F Biquad filter signal input

If TD_W_A DDR = 1 (Select Comparator Inputs)

Field Byte Pos. Value Definition

TD_W_CN 3 0..3F Negative comparator signal input

TD_W_CP 4 0..3F Positive comparator signal input

For Secondary Tone Detector

Field Byte Pos. Value Definition

TD_4DIFF 2 7..0 00

other

Relative comparison not enable

Relative comparison enable

Reserved

TD_4_CONF 3 7..0 0 Mandatory

TD_4_CONF2 4 7..0 C0

other

1+1 configuration

1+1+2 configuration

1+1+1+1 configuration

Reserved

VII - COMM A N D SET DESCRIPTION (continued)

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TDZ Tone Detector Clear Cell TDZ

Opcode: 1E

00011110

Synopsis TDZ Clears all internal variables of one Tone detector cell including Filter local variables and

energy estimator. This command must be sent after changing coefficients of a cell to avoid

instability.

Parameters Field Byte Pos. Value Definition

TD_CELL 1 4..0 0..13 Tone detector cell number

TGEN Enable /Disable Tone Generators TGEN

Opcode: 0D 00001101

Synopsis Enable or disable one of the four tone generator, define the output of the tone generator

either Line or Audio.

Parameters Field Byte Pos. Value Definition

TONE_0_ENA 1 0 0*

1 Generator #0 disabled

Generator #0 enabled

TONE_1_ENA 1 1 0*

1 Generator #1 disabled

Generator #1 enabled

TONE_2_ENA 1 2 0*

1 Generator #2 disabled

Generator #2 enabled

TONE_3_ENA 1 3 0*

1 Generator #3 disabled

Generator #3 enabled

TONE_0_OUT 1 4 0*

1 Generator #0 output to line

Generator #0 output to audio

TONE_1_OUT 1 5 0*

1 Generator #1 output to line

Generator #1 output to audio

TONE_2_OUT 1 6 0*

1 Generator #2 output to line

Generator #2 output to audio

TONE_3_OUT 1 7 0*

1 Generator #3 output to line

Generator #3 output to audio

VII - COMM A N D SET DESCRIPTION (continued)

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TONE Pre de fined Tones TONE

Opcode: 0C 00001100

Synopsis TONE programs the tone generator for the predifined tones. The tone generator #0 and

eventualy #1 are reprogrammed with this command. The tone generator #0 and eventualy

the #1 are enabled. Using a v alue not in the following table will disable tone gene rator #0

and #1.

Parameters Field Byte Pos. Value Definition

TONE_SELECT 1 5..0 0

DTMF digit 0

DTMF digit 1

DTMF digit 2

DTMF digit 3

DTMF digit 4

DTMF digit 5

DTMF digit 6

DTMF digit 7

DTMF digit 8

DTMF digit 9

DTMF digit A

DTMF digit B

DTMF digit C

DTMF digit D

DTMF digit *

DTMF digit #

Answer tone 2100Hz

Tone 1650Hz

Tone 2225Hz

Tone 1300Hz

Tone 1100Hz

TONE_OUT 1 7 0

1Output on line

Output on audio

XMIT Start/stop Transmission XMIT

Opcode: 01 00000001

Synopsis XMIT start or stop the transmission of the Trans mit Data.

Parameters Field Byte Pos. Value Definition

TX_START 1 0 0*

1Stop transmission

Start transmission

VII - COMM A N D SET DESCRIPTION (continued)

ST75C 530 - ST75C540

42/84

This appendix is dedicated t o the ST75C530/540

reporting features. In the following sections the

command acknowledge process and the report

and status definitions are explained.

VIII.1 - Command Acknowled ge and Report

VIII.1.1 - Command Acknowledge Proc e s s

The ST75C530/540 features an acknowledge

process based on a counter COMACK. On power-

on reset (or INIT c ommand), this counter’ s value is

set to 0. Each time a command is successfully

executed by the ST75C530/540, the ack nowledge

counter COMACK is incremented. This allows a

precise monitoring of the command entered and

avoids command collision.

In the case of a memory reading command (CR,

TDRC, TDRW, IDT or MR) once the command

entered is executed, the report area is filled and the

acknowledge counter is incremented afterwards.

This insures t hat the controller will r ead the value

corresponding to its request.

Furthermore, the ST75C530/540 resets the value

of the COMSYS register and the interruption IT6

is raised.

VIII.1.2 - Reports Specification

The report section of the Dual Port RAM is dedi-

cated to memory reading. In response to a CR, MR,

MRI, MRLO, TDRC, TDRW, IDT commands, the

value read is transferred to the report registers

COMREP[0..1].

VIII - STATUS DESCRIPTION

ASSERT

INTERRUPT

IT0

SET SYSERR

ERR_IOCD

SET SYSERR

ERR_IPRM

EXECUTE

COMMAND

CLEAR

ANSWER

END

Yes

BEGIN

COMSYS = 0

COMMAND EXIST

Yes

CLEAR

COMSYS

ASSERT

INTERRUPT

IT6

COPY ANSWER

INTO

COMREP

ASSERT

INTERRUPT

IT0

INCREMENT

COMACK

75C53020.EPS

Figure 16 : Command Acknowledge P rocess

ST75C 530 - ST75C540

43/84

VIII.1.3 - CR Command

Issuing a CR com mand causes the S T 75C530/540 to dump a specific mem ory loc ation in complex mode.

This instruction is particularly useful for equalizer state analysis or for software eye-pattern display. The

report area has this meaning :

RP7 RP6 RP5 RP4 RP3 RP2 RP1 RP0 COMREP[0]

IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 COMREP[1]

RP0..RP7 is t he M SB par t of the 16- bit value of the real part and IP0..IP7 is the MS B part of t he im aginary

part. The CR command insures that the real and imaginary part of the desired complex value ar e sampled

internally at the same time. The address given in the parameter field of CR is the address of the real part.

VIII.1.4 - MR/TDRC/TDRW/IDT/MRI/MRLO Commands

The report issued by the MR/TDRC/TDRW/IDT/MRI/MRLO commands follow t he same rules as for CR.

The report meaning is :

D7 D6 D5 D4 D3 D2 D1 D0 COMREP[0]

D15 D14 D13 D12 D11 D10 D9 D8 COMREP[1]

D0..D15 is the 16-bit value requested by the command.

In the case of IDT , D15..D12 contains the product identification (3 for ST75C530, 7 for ST75C5540), D11..D8

contains the hardware revision identific ation and D7..D0 cont ains the software revision identification.

VIII.2 - Modem Status

VIII.2.1 - Modem Status Description

The Status of ST75C530/540 is divided into 4 fields :

- The error status byte SYSERR that provides information about error. This status can trigger an IT0

interrupt,

- The general status by te STATUS[0] and STAT US[1] that contains all the modem signals. These status

bytes can trigger an IT4 interrupt,

- The quality status STAQUA, that contains the quality of the received transmission,

- The optional status bytes STAOP[0], STAOP[1], STAOP[2] and STAOP[3], that contains additional

information regarding the ST75C530/540 operating mode. This default information can be changed to

monitor any internal variables using the DOSR command.

All these informations are updated on a Baud basis :

Mode Baud Rate (2) (Hz)

V.32bis/V.32 (ST75C540 only) 2400

V.22bis/V.22/Bell 212A (ST75C540 only) 2400

Tone 2400

Bell 103 (full duplex) 2400

V.21 (full duplex) 2400

V.23 (full duplex) 2400

V.27ter 2400bps 1200

V.27ter 4800bps 1600 (1)

V.29 2400

V.17/V.33 2400

V.21 channel 2 2400

HANDSET, CODER or DECODER Modes 1200

Notes : 1. In this mode the tone detectors outputs are update 800 times by second.

2. This bau d rate defines als o, the maximum c ommand rate. Eac h baud time the ST75C5 30/540 looks at the COMSYS location

(Address $00) t o see if a c om man d have been s ent by the host processor. If the conte nt of this lo cat io n is different from zero the

ST75C530/540 execute the command.

VIII - STATUS DESCRIPTION (continued)

ST75C 530 - ST75C540

44/84

Starting at the adddress $08 the status area have the following format :

Add. Name Bit

765 43210

$08 SYSERR ERR_RTK - - ERR_IPRM ERR_IOCD ERR_VOCO ERR_RX ERR_TX

$09 STATUS0 STA_109F STA_CPT10 STA_CPT1 STA_CPT0 STA_RING STA_106 STA_107 STA_109

STA_VAD

$0A STATUS1 STA_DTMF STA_FLAG

STA_CLR* STA_RNEG STA_HR

STA_RTRN* STA_AT STA_CCITT STA-TIM STA_H

$0B STAQUA - Quality

$0C STAOP0 Depend on operating mode (see below)

$0D STAOP1

$0E STAOP2

$0F STAOP3

* ST75C 540 onl y

VIII.2.2 - Error Status

The error status changes each time an error occurs. When the ST75C530/540 signals an error by setting

one of the SYSERR bit, it generates an interrupt IT0. These bits can only be cleared by the host controler

using the CSE command.

The meaning of the dif ferent bits of the SYS ERR byte is discribed below :

SYSERR

Field Pos. Meaning when set

ERR_TX 0 Transmit buffer underflow. Loss of synchronisation between the host and ST75C530/540 transmit

data buffer managment.

ERR_RX 1 Receive buffer overflow. Loss of synchronisation between the host and ST75C530/540 receive

data buffer managment.

ERR_VOCO 2 Vocoder buffer underflow (Decoder) or overflow (Coder). Lost of synchronisation between the

Host and ST75C530/540 VOCODER Buffer management.

ERR_IOCD 3 Incorrect command

ERR_IPRM 4 Incorrect parameter for the command

ERR_RTK 7 Real time kernel error. ST75C530/540 not able to perform all its tasks within the baud period

(transmit or receive samples lost).

VIII - STATUS DESCRIPTION (continued)

ST75C 530 - ST75C540

45/84

VIII.2.3 - Modem General Status

The modem general status word is composed of two bytes STA TUS[0] and ST A TUS[1]. Any bit change can

generate an IT4 interrupt. Using the DSIT command allows the selection of the corresponding bit that will

generate an interrupt each time they will change. The default pattern is $3F for STATUS[0] and $FF for

STATUS[1].

The different bits have the following meaning :

STATUS[0]

Field Pos. Meaning when set

STA_109

STA_VAD 0 In FAX MODEM and TONECID modes STA_ 109 : CCITT Cir cuit 109 ( Carrier Detect). Indica tes

that valid data are received.

In CODER and DECODER modes : VAD: Voice Activity Detected

STA_107 1 CCITT Circuit 107 (Data Set Ready). Valid only in FAX & DATA MODEM modes.

STA_106 2 CCITT Circuit 106 (Clear T o Send). Indicates that the training sequence has been completed

and that any data in the Transmit Buffer will be transmitted. Valid only in FAX & DATA MODEM

modes.

STA_RING 3 Ring Detected. A valid ring signal is present at the Ring pin. Valid only in Tones modes. T he

precise frequency can be read in the optional status byte STAOP2.

STA_CPT0 4 In TONE and TONECID modes STA_CPT0: Call progress tone detector #0. Low pass filter

650Hz.

STA_CPT1 5 In TONE and TONECID modes STA_CPT1: Call progress tone detector #1. High pass filter

600Hz.

STA_CPT10 6 In TONE and TONECID modes STA_CPT10: Signal in Filter #0 is higher than #1.

STA_109F 7 In FAX MODEM mode, V.22bis mode* and TONECID mode STA_109F: Fast Carrier Detect.

* ST75C540 only

STATUS[1]

Field Pos. Meaning

STA_H 0 Transmit synchronisation in progress. Valid only in FAX & DATA MODEM modes.

STA_TIM* 1 Handshake timeout. Valid only in Data Modem mode.

STA_CCITT 2 CCITT 2100Hz versus 2225Hz answer tone detect. Valid if STA_AT is set. Valid only in Tone

mode.

STA_AT 3 Answer tone (either 2100Hz or 2225Hz) detected. Valid only in Tone mode.

STA_HR

STA_RTRN* 4 STA_HR : Receive synchronisation in progress. Valid only in Fax Modem mode.

STA_RTRN : Remote retrain detec, valid only in V.32bis/V.32/V.22bis Data Modem modes.

STA_RENEG* 5 Remote rate negotiation detected, valid only in V.32bis/V.32/V.22bis Data Modem modes.

STA_FLAG

STA_CLR* 6 STA_FLAG : V.21 channel 2 flag detect. Valid only in FAX Modem mode and Tone mode.

STA_CLR : Remote clear down detected V.32bis/V.32 Data Modem modes.

STA_DTMF 7 DTMF digit detect. The digit itself is available in the optional status byte STAOP3.

* ST75C540 only

VIII - STATUS DESCRIP TION (continued)

ST75C 530 - ST75C540

46/84

VIII.2.4 - Quality Status

The quality bytes ST AQUA and ST AQUAS monitor an evaluation of the line quality . They are updated once

per baud and their value ranges from 127 (perfect quality) to 0 (terrible quality). This value is automaticaly

adjusted according to the current receiving mode. Refer to the following chart to convert the value of

STAQUA into its Bit Error Rat e equivalence. The time constant for STAQUA is 100ms. The slow quality

byte (available on ST AOP1 in Fax and Data mode except FSK) ST AQUAS gives the equivalent quality with

a 1 sec onde time constant.

VIII - STATUS DESCRIP TION (continued)

-3

-4

-5

-6

-7

-8

-9

0 316395127

STAQUA

BER

-2

75C53021.EPS

VIII.2.5 - Optional Status

According to the operat ing mode of the ST75C530/540 the optional status is displaying different informa-

tions.

The optional status ar e automatically reprogrammed aft er eac h CONF command with the addres s of the

variables to monitor according with the operating mode selected (CONF_OPER). After the CONF command

the user must overwrite this default programming by using the DOSR command. I n order t o change the

default set-up please refer to the “RAM Mapping application note” (delivered on request according to

revision number) to obtain the addresses of the DSP Internal variables.

VIII.2.5.1 - Default Optional Status in All modes Except MODEM

W hile in Tone mode the format of the STAOP word is as follows :

Optional Status Words

Add. Name Bit

76543210

$0C STAOP0 TDT7 TDT6 TDT5 TDT4 TDT3 TDT2 TDT1 TDT0

$0D STAOP1 TDT15 TDT14 TDT13 TDT12 TDT11 TDT10 TDT9 TDT8

$0E STAOP2 RING_PERIOD (1)

$0F STAOP3 TDT19 TDT18 TDT17 TDT16 DTMF_DIGIT(4)

Notes : 1. RING_PERIOD is valid when the Bit 3 of the STA TUS0 (ST A_RING goes high. This value is updated at each falling edge of the

RING Signal. The RING_PERIOD value must be multiplied by 2400 to obtain the Peri od in second.

2. TDTx (x in [0..15]) is the Output of the 16 Tone detecto rs x (s amp ling rat e 7200Hz).

3. TDT y (y in [16..19] is the Output of the secondary Tone detectors (sampling rate 4800Hz or 9600Hz) with absolute comparison

or relati ve comparison.

4. DTMF_DIGIT is valid when the Bit 7 of STATUS1 (ST A_DTMF) goes high. This value remains unchanged until a new DTMF

Digit is detected.

ST75C 530 - ST75C540

47/84

VIII.2.5.2 - Default Optional Status in Fax Mode

While in Fax Modem mode the form at of the STA OP word is as follows :

Optional Status Words in MODEM Mode

Add. Name Bit

7654321 0

$0C STAOP0 x x x SPEED (2)(5) SPVAL (1) (5)

$0D STAOP1 STAQUAS

$0E STAOP2 PNSUCs PRDETs PNDETs SCR1s PRs PNs P2s P1s

$0F STAOP3 TDT19 TDT18 TDT17 TDT16 DTMF_DIGIT(4)

Notes : 1. SPVAL is active in V.33 receiver only at the same time as the rising transition of the SCR1s signal. When SPVAL is set, it indic a te s

that the SPEED bits contain the Data speed information.

2. SPEED is valid in V.33 receiver only it can hav e 2 values, a fter the SC R1s s ignal goes high : 1000 for 14400b ps a nd 0111 for

12000bps.

3. The STAOP2 Bit reflects the progression of the Synchronisation.

4. Only valid in V.21 Channel 2 Receive mode.

The STAOP2 Bits have the following meanings :

STAOP2 in Fax Modem Mode

Name Position Description

P1s 0 Unmodulated carrier sequence. Optional, used for echo protection.

P2s 1 Continuous 180° phase reversal sequence

PNs 2 Equalizer trainning sequence

PRs 3 V.33 and V.17 rate sequence

SCR1s 4 Continuous scrambled 1 sequence

PNDETs 5 Turned on after PN sequence detection

PRDETs 6 Turned on after PR sequence detection (V.33 and V.17 only)

PNSUCs 7 Turned on after succesfull training of the receive equalizer. When on at the end of the

synchronization, the transmition BER is statisticaly bellow 10ppm.

VIII - STATUS DESCRIP TION (continued)

ST75C 530 - ST75C540

48/84

With the following timing :

VIII - STATUS DESCRIP TION (continued)

Transmit

SCR1

Data

T2 T3 T4 T5 T6

STA_H

P1s

P2s

PNs

PRs

SCR1s

(7)

Receive

T8T7 T8 T8 T8

STA_HR

STA_109F

P2s

PRDETs

PNSUCs

SCR1s

STA_109

RxData

PNs

PNDETs

(1)

(2) (8)

(6)

75C53022.EPS

Mode T1 (4) T1p (5) T2 T3 T4 T5 T6 T7 T8 Unit

V.17 192 30 22 107 1240 27 20 5 7 ms

V.17 short 192 30 22 107 16 0 20 5 7 ms

V.29 192 30 22 53 160 0 20 5 7 ms

V.29 short 192 30 22 41 26 0 8 5 7 ms

V.27 4800 192 30 22 31 670 0 5 5 7 ms

V.27 4800 short 192 30 22 9 36 0 5 5 7 ms

V.27 2400 192 30 22 42 895 0 7 6 7 ms

V.27 2400 short 192 30 22 12 48 0 7 6 7 ms

ST75C 530 - ST75C540

49/84

Transmit

SCR1

Data

T10

T11 min

STA_H

P1s

PNs

PRs

SCR1s

Receive

T13

STA_HR

STA_109F

PRDETs

PNSUCs

STA_109

RxData

PNs

PNDETs

(3)

P2s

T12

(3)

(6)

75C53023.EPS

Mode T10 T11 T12 T13 Unit

V.17 13 20 8 25 ms

V.17 short 13 20 8 25 ms

V.29 13 20 8 25 ms

V.29 short 13 20 8 25 ms

V.27 4800 20 30 8 25 ms

V.27 4800 short 20 30 8 25 ms

V.27 2400 27 40 8 25 ms

V.27 2400 short 27 40 8 25 ms

Notes : 1. In the case of V.29 or V.27, PRs and PRDETs bits are not active.

2. PNSUCs indicates the quality of the Rx signal that will g ive a ber of approximation of 1e-5.

3. After sending the command SYNC0, all bits are reset.

4. When using l ong echo prot ect io n tone, otherwi se 0.

5. When using short echo protec tion tone, otherwi se 0.

6. ST A-106 is set at the end of T6 and reset at the beginning of T10.

7. After sending the command SYNC1, this bit is set.

8. PNSUC is evaluated twice, first at SCR1 detection and further 256 baud (V.29, V.17, V.33 : 106ms ; V.27 4800bps : 160ms ;

V.27 2400bps : 212ms) after ST A_109.

9. For V.21 channel 2, timing for loss of STA_109 is 25ms and timing for detection of STA_109 is 7ms.

10. F or V.2 1 channel 2 after a STOP com m and, STA _H i s set to “1" during 13ms when the last HDLC flag is transm itted.

VIII - STATUS DESCRIP TION (continued)

ST75C 530 - ST75C540

50/84

VIII.2.5.3 - Default Optional Status in DATA MODEM Mode (ST75C540 only)

While in Data Modem mode the format of the STAOP word is as follows :

Optional Status Words in MODEM Mode

Add. Name Bit

7654321 0

$0C STAOP0 x x x SPEED (2)(5) SPVAL (1) (5)

$0D STAOP1 STAQUAS

$0E STAOP2 HSHK_PHA

$0F STAOP3 TDT19 TDT18 TDT17 TDT16 Not Used

Notes : 1. SP VAL i s active in V.33 receiver only at the same time as the rising transition of the SCR1s signal . When SPVAL is set, it

indicates that the SPEED bits contain the Data speed information.

2. SPEED is valid in V .32bis, V.32, V.22bis, V.22, Bell 212A and V.33 receiver only with the following meaning :

Bit 4 Bit 3 Bit 2 Bit 1 Data Speed

00101200bps

00112400bps

01004800bps

01017200bps

01109600bps

011112000bps

100014400bps

Other Reserved

3. The STAOP2 Bit reflects the progression of the Synchronisation.

4. Only valid in V.21 Channel 2 Receive mode.

5. SPVA L is ac tive in V.32bis/V. 32/V.22bis/V.22 at the end of the training se quence and at least 8 baud before ente ri ng Data mode.

SPVAL and SPEED are also updated with each retrain and rate negotiation.

6. The SP AOP1 bits reflect the progression of the synchronization in Data modes.

VIII - STATUS DESCRIP TION (continued)

ST75C 530 - ST75C540

51/84

The STAOP2 Bits have the following meanings in Data Modem mode :

HSHK_PHA (R) Handshake progression counter contains information about the progress of the

hadshake in V.32 and V.22bis modes. This 8-bit value is av ailable in STAOP2 in modem

mode. It can be read to examine the progressio of the handshake and it contains normal

values and error values as below :

AUTOBAUD ORIG MODE

Event HSHK_PHA Value

Wait Answer Tone

Wait End Answer Tone

Not Autobaud and Waiting

USC1

Autobaud Waiting AC or USC1

$01

$02

$03

$04

AUTOBAUD ANSW MODE

Event HSHK_PHA Value

Waiting HSK Command

Generating Answer Tone

Generating Silence

$10

$11

$12

V.32 ORIG MODE

EVENT HSHK_PHA Normal Value HSHK_PHA Error Value

AC_DET

AC/CA DET

CA/AC DET

NO AC DET

S_DET

SB_DET

R1_DET

S_DET

SB_DET

R3_DET

E_DET

DATA_MODE

$20

$21

$22

$23

$24

$25

$26

$27

$28

$29

$2A

$30

$B for RTN, $C for RTN

$9, $D no R5 det after RRN

V.32 ANSW MODE

EVENT HSHK_PHA Normal Value HSHK_PHA Error Value

AA_DET

AA/CC DET

NO CC DET

S_DET

SB_DET2

SB_DET

R2_DET

E_DET

DATA_MODE

$40

$41

$42

$43

$44

$45

$46

$47

$50

$8 for RTN, $9 for RRN

$6, $A if no R det after RRN

V.22bis ORIG MODE

EVENT HSHK_PHA Normal Value

HSHK

USC1_DET

SCR1_DET

S1_DET

DATA_MODE

$60

$61

$62

$63

$70

V.22bis ANSW MODE

EVENT HSHK_PHA Normal Value

HSHK

SCR1_DET

S1_DET

DATA_MODE

$80

$82

$83

$90

VIII - STATUS DESCRIP TION (continued)

ST75C 530 - ST75C540

52/84

IX - TONE DETECTORS

-1

C0 C5

-1

OUT

75C53024.EPS

Figure 17 : Biquadratic IIR Filter

IX.1 - Overview

The general purpose ST75C530/540 tone detec-

tors block is a powerful module that covers a lot of

applications :

- call progress tone det ection, f ully programmable

for all countries,

- FAX, voice, data automatic detection,

- call waiting detection, while in vocoder or data

mode.

IX.2 - Description

The primary tone detector block is a set of 16

identical Cells. Each cell is composed of a Double

Biquadratic Filter, a Power estimator section, a

Static level and a Level comparator.

Each Biquadratic Filter, Power Estimator and Static

Level can be programmed using a com plete set of

commands ( TDRC, TDRW, TDWC, TDWW, TDZ).

The wiring between t he different Cells can be de-

fined by the user, using the associated comma nd

allowing a wide range of applications.

Th e sampli ng fr equenc y is 7 200H z, all owing detec -

tion of signal s less than 3300Hz. The level of detec-

tio n is program mabl e from -6dBm dow n to -51 dBm.

The 16 Comparator Outputs give, on a baud basis,

the information into two 8 bits words TONEDET0

(for cells number 0 to 7) and TONEDET1 (for cells

number 8 to F). These TONEDET variables can be

accessed using a MRI command or, more easily,

monitored on a baud basis using the DOSR com-

mand.

The 16 p rimary tone detectors are initia lized each time

ent eri ng the tone m ode. However the p rev io us c oef fi -

cie nt values cou ld be kept using a MW comman d.

The secondary tone detector have been added to

the ST 75C530/540. The filter structure is the same

as the primary tone detector.

The sampling rate is 4800Hz allowing detection of

signal less than 1800Hz by default programming or

with a MODC command, the sampling rate is

9600Hz allowing detection of signal less than

3300Hz. The level of detection is programmable

from -6dBm down to -51dBm. In order to increase

the reliability of the detection, using a TDWW com-

mand, 2 comparisons are provided, one with a fixed

level (absolute) or with the receive signal (relative).

The 4 secondary tone detectors are initialiazed

each time entering the tone mode. However the

previous coefficient values could be kept using a

CONF command.

The command TDRC, TDWC, TDWW, TDRW, TDZ

with the TD_CELL parameter of 0x10, 0x11, 0x12

or 0x13 can be used to program these filters.

IX.2.1 - Biquadratic Filters

Each Biquadratic Filter is a double regular section

that can perform any Transfer function with 4 Poles

and 4 Zeros.

This routine is run on a sa mple basis.

The corresponding transfer function is :

Out

Input = C0 ⋅ C5 + 2 ⋅ C3 ⋅ z−1 + 2 ⋅ C4 ⋅ z−2

1 − 2 ⋅ C1 ⋅ z−1 − 2 ⋅ C2 ⋅ z−2 ⋅ C6 ⋅ CB + 2 ⋅ C9 ⋅ z−1 + 2 ⋅ CA ⋅ z−2

1 − 2 ⋅ C7 ⋅ z−1 − 2 ⋅ C8 ⋅ z−2 ⋅ z−1

Note : All coefficients are coded on 16 bits 2’s complement in the range +1, -1 (Q15). To avoid the possibility of overflow the user must check

that the internal node must not be h igh er that 0.5 (in Q15 representation).

ST75C 530 - ST75C540

53/84

IX. 2.2 - Po w e r Es ti ma t io n

The Power estimation Cell is needed to measure

the amplitude of the different tones. It is run on a

sample basis.

IX - TONE DETECTORS (continued)

-1

OUT

ABS(.) P1

-1

75C53025.EPS

Figure 18 : Power Estimator

The corresponding transfer function is :

Out = | Input | ⋅ z−1 ⋅ P1

1 − (1 − P1) ⋅ z−1

IX.2.3 - Static Level

A single Threshold level is associated with each

Cell. It can be use to compare the output of a Power

Es timation with an Absolute Value.

IX.2.4 - Comparator

The Comparator computes, on a baud basis, the

difference of the signal on its Positive and Negative

Inputs. If the result is Higher that zero it sets the

corresponding bit into the TONEDET[0..1] word; if

not it cl ear this bit.

IX.2.5 - Wiring

The user must specify the connection (wiring) be-

tween the input/output of the Filter, the input/output

of the Power estimator, the output of the static

levels and the two inputs of the Comparators.

The output signals have an absolute address:

Node Address

Signal

Name Address Description

Ground 00 Signal always equal to 0000

RxSig 01 Receive signal from the

Analog front end

RxSig2 02 Receive signal multiplied by 2

RxSig4 03 Receive signal multiplied by 4

04..0F Reserved

Filter[0..F] 10..1F Biquadratic Filter Outputs

Power[0..F] 20..2F Power Estimator Outputs

Level[0..F] 30..3F Static Levels

The user will specify t he inputs of the filters, Power

and Comparator. At least one input must come from

the RxSig (node 01, 02 or 03). It is mandatory to

connect all unused cell inputs to the Ground signal

(node 00).

ST75C 530 - ST75C540

54/84

Rx SIGNAL

GROUND

@00

@01

@02

@03

TONEDET0

@10 @20

@30

@11 @21

@31

@12 @22

@32

@13

LEVEL #3

POWER

#3 @23

@33

@14 @24

@34

@15 @25

@35

@16 @26

@36

@17 @27

@37

BIQUADRATIC

FILTER

BIQUADRATIC

FILTER

BIQUADRATIC

FILTER

BIQUADRATIC

FILTER

BIQUADRATIC

FILTER

BIQUADRATIC

FILTER

BIQUADRATIC

FILTER

BIQUADRATIC

FILTER

LEVEL #0

POWER

LEVEL #1

POWER

LEVEL #2

POWER

LEVEL #4

POWER

LEVEL #5

POWER

LEVEL #6

POWER

LEVEL #7

POWER

COMP.

75C53026.EPS

Figure 19 : Tone D etector Wiring Address (first half)

IX - TONE DETECTORS (continued)

ST75C 530 - ST75C540

55/84

TONEDET1

@18 @28

@38

@19 @29

@39

@1A @2A

@3A

@1B @2B

@3B

@1C @2C

@3C

@1D @2D

@3D

@1E @2E

@3E

@1F @2F

@3F

LEVEL #9

COMP.

BIQUADRATIC

FILTER

BIQUADRATIC

FILTER

BIQUADRATIC

FILTER

BIQUADRATIC

FILTER

BIQUADRATIC

FILTER

BIQUADRATIC

FILTER

POWER

LEVEL #B

POWER

LEVEL #E

POWER

LEVEL #F

LEVEL #D

LEVEL #C

LEVEL #A

LEVEL #8

BIQUADRATIC

FILTER

BIQUADRATIC

FILTER

75C53027.EPS

Figure 20 : Tone D etector Wiring Address (second half)

IX - TONE DETECTORS (continued)

ST75C 530 - ST75C540

56/84

AND

TDT17

Relative

-TD4DIFF or

TDWW 1100 00C0

FOURTH ORDER

IIR FILTER #16 POW ()

#16

LEVEL #16

POW ()

#20 GAIN

#16

COMPARATOR

#16

COMPARATOR

#16

INPUT SIGNAL

FOURTH ORDER

IIR FILTER #17 POW ()

#17

LEVEL #17

POW ()

#20 GAIN

#17

COMPARATOR

#17

COMPARATOR

#17

AND

TDT16

Relative

-TD4DIFF or

TDWW 1001 00C0

absolu

75C53028.EPS

Figure 21a : Secondary Tone Detector Configuration (2 tone detectors 1 + 1)

AND

TDT17

Relative

-TD4DIFF or

TDWW 1100 00E0

FOURTH ORDER

IIR FILTER #16 POW ()

#16

LEVEL #16

POW ()

#20 GAIN

#16

COMPARATOR

#16

INPUT SIGNAL

FOURTH ORDER

IIR FILTER #17 POW ()

#17

LEVEL #17

POW ()

#20 GAIN

#17

COMPARATOR

#17

COMPARATOR

#17

AND

TDT16

Relative

-TD4DIFF or

TDWW 1001 00E0

AND

TDT18

Relative

-TD4DIFF or

TDWW 1200 00E0

FOURTH ORDER

IIR FILTER #18 POW ()

#18

LEVEL #18

POW ()

#20 GAIN

#18

COMPARATOR

#18

COMPARATOR

#18

FOURTH ORDER

IIR FILTER #19

COMPARATOR

#16

absolu

75C53029.EPS

Figure 21b : Secondary Tone Detector Configuration (3 tone detectors 1 + 1 + 2)

IX - TONE DETECTORS (continued)

ST75C 530 - ST75C540

57/84

AND

TDT17

Relative

-TD4DIFF or

TDWW 1100 00F0

FOURTH ORDER

IIR FILTER #16 POW ()

#16

LEVEL #16

POW ()

#20 GAIN

#16

COMPARATOR

#16

COMPARATOR

#16

INPUT SIGNAL

FOURTH ORDER

IIR FILTER #17 POW ()

#17

LEVEL #17

POW ()

#20 GAIN

#17

COMPARATOR

#17

COMPARATOR

#17

AND

TDT16

Relative

-TD4DIFF or

TDWW 1001 00F0

absolu

AND

TDT18

Relative

-TD4DIFF or

TDWW 1201 00F0

FOURTH ORDER

IIR FILTER #18 POW ()

#18

LEVEL #18

POW ()

#20 GAIN

#18

COMPARATOR

#18

COMPARATOR

#18

absolu

AND

TDT19

Relative

-TD4DIFF or

TDWW 1300 00F0

FOURTH ORDER

IIR FILTER #19 POW ()

#19

LEVEL #19

POW ()

#20 GAIN

#19

COMPARATOR

#19

COMPARATOR

#19

absolu

75C53030.EPS

Figure 21c : Secondary Tone Detector Configuration (4 tone detectors 1 + 1 + 1 + 1)

IX - TONE DETECTORS (continued)

ST75C 530 - ST75C540

58/84

BIQUADRATIC

FILTER

LEVEL #3

POWER

LEVEL #4

LEVEL #5

COMP.

BIQUADRATIC

FILTER

BIQUADRATIC

FILTER

Rx SIGNAL

GROUND

@00

@01

@02

@03

@13

@14

@15

@23

@33

@24

@34

@25

@35

TONEDET0

75C53031.EPS

Figure 22 : Wiring Example

IX.3 - Example

IX - TONE DETECTORS (continued)

Hereunder is an exam ple of progr amming a s ingle

Tone det ection (using Cell #3) and a complex dif -

ferential tone detection (using Cell #4 and #5) .

Bit 3 of the TONEDET variable will be triggered

each time the energy of that filtered signal is higher

than Static Level number 3.

Bit 4 of the TONEDET variable will be on each time

a receive signal has an energy higher than the

Static Level number 4. Bit 5 will be on only when

the Filtered (Filter section 4 and 5) receiv ed signal

higher than the energy of the wide-band signal

number 4 ; this prevents triggering on noise.

Program Cell #3 :

TDWW 03 00 13 01

Connect Received signal to Filter and Filter to Energy.

TDWW 03 01 33 23

Connect Level to Comparator Neg Input and Energy to Pos Input.

Program Cell #4 and #5 :

TDWW 04 00 01 01

Connect Received Signal to Filter and Energy.

TDWW 04 01 34 24

Connect Level to Comparator Neg Input and Energy to Pos Input.

TDWW 05 00 15 14

Connect Filter#4 Output to Filter and Filter to Energy.

TDWW 05 01 24 25

Connect Wide-band Energy to Neg Input and Energy to Pos Input.

ST75C 530 - ST75C540

59/84

X - PARALLEL DATA EXCHANGE

HDLC

UART

BUFFERS

MODUL.

DEMOD.

BUFFERS

IT2

IT3

Telephone

Line

Control

Data

HOST INTERFACE

HDLC

UART

75C53032.EPS

Figure 23

X.1 - Overview

While transmiting (respectively receiving) data to

(from) the telephone line data are exchanged be-

tween the host and the ST75C530/540.

Two t otaly independent channels are prov ived for

transmit and receive data. Even while using half

duplex modes of operation, the transmitted data

comes from the transmit buffers and the receive

data arrives in the receive buffers.

Two independent interr upts,

IT2

(for transmit) a nd

IT3

(for receive) are available for synchronizing the

ST75C530/540 and the host. An additional

IT0

interrupt will signal the errors in the synchronization

mechanism.

The equivalent data flow is as follows (see Fig-

ure 20).

The ST75C530/540 has a buit-in HDLC capability.

This feature automatically performs HDLC fram-

ing/deframing, CRC generation/detection and “0"

insertion/deletion. The ST75C530/540 have also

UART cap ability, t he format of data is selected by

the

FORM

command described bellow.

X.2 - Transmit Buffers

T wo identical buff ers are provided to exchange the

data between the host interface and the

ST75C530/540. When th e host is writing data into

a buffer, the ST75C530/540 is transmitting the

other one. After that, both the host and the

ST75C530/540 switch to us e the ot her buff er. This

mechanism, called “Double-Buffering”, ensures

that the host has the maximum time to fill one

buffer.

The DUAL Ram area associated with t he transmit

buffers is as following table.

Name Address Description

DTTBS0 $2E Buffer 0 Status Byte

DTTBS0 [0] $2F Buffer 0 Data Byte 0

DTTBS0 [1] $30 Buffer 0 Data Byte 1

DTTBS0 [2] $31 Buffer 0 Data Byte 2

DTTBS0 [3] $32 Buffer 0 Data Byte 3

DTTBS0 [4] $33 Buffer 0 Data Byte 4

DTTBS0 [5] $34 Buffer 0 Data Byte 5

DTTBS0 [6] $35 Buffer 0 Data Byte 6

DTTBS0 [7] $36 Buffer 0 Data Byte 7

DTTBS1 $37 Buffer 1 Status Byte

DTTBS1 [0] $38 Buffer 1 Data Byte 0

DTTBS1 [1] $39 Buffer 1 Data Byte 1

DTTBS1 [2] $3A Buffer 1 Data Byte 2

DTTBS1 [3] $3B Buffer 1 Data Byte 3

DTTBS1 [4] $3C Buffer 1 Data Byte 4

DTTBS1 [5] $3D Buffer 1 Data Byte 5

DTTBS1 [6] $3E Buffer 1 Data Byte 6

DTTBS1 [7] $3F Buffer 1 Data Byte 7

Bit 0 (LSB) of the Buffer 0 Data Byte 0 is the first in

time to be transmited.

Ac cording to the Data F ormat, the S tatus byte of a

buf fer has different meanings. However a value of

0 signals to the host that a buffer is empty. This

value is s et by the ST75C530/540 each time it has

emptied the buffer. After having used one buffer,

the host must select the other buffer for the next

operation. The host must start with the Buffer 0 as

soon as the

ST_106

signal goes on and BEFORE

the

XMIT 1

command is sent.

A mechanism of interruption (

IT2

for Transmit) is

associated with the data buffer managment. Each

time a buffer is emptied by the ST75C530/540 it

generates an interrupt.

ST75C 530 - ST75C540

60/84

X.3 - Receive Buffers

Symetrically two identical buffers are provided to

exchange receive data between the

ST75C530/540 and the host processor. While the

ST75C530/540 is filling one of the buffers with the

receive bits, the host processor is reading the other

buffer. As soon as the host has emptied a buffer it

frees it by writ ing 0 in the buffer status byte.

The DUAL Ram ar ea associated with the receive

buffer s is as following table.

Name Address Description

DTRBS0 $1C Buffer 0 Status Byte

DTRBS0 [0] $1D Buffer 0 Data Byte 0

DTRBS0 [1] $1E Buffer 0 Data Byte 1

DTRBS0 [2] $1F Buffer 0 Data Byte 2

DTRBS0 [3] $20 Buffer 0 Data Byte 3

DTRBS0 [4] $21 Buffer 0 Data Byte 4

DTRBS0 [5] $22 Buffer 0 Data Byte 5

DTRBS0 [6] $23 Buffer 0 Data Byte 6

DTRBS0 [7] $24 Buffer 0 Data Byte 7

DTRBS1 $25 Buffer 1 Status Byte

DTRBS1 [0] $26 Buffer 1 Data Byte 0

DTRBS1 [1] $27 Buffer 1 Data Byte 1

DTRBS1 [2] $28 Buffer 1 Data Byte 2

DTRBS1 [3] $29 Buffer 1 Data Byte 3

DTRBS1 [4] $2A Buffer 1 Data Byte 4

DTRBS1 [5] $2B Buffer 1 Data Byte 5

DTRBS1 [6] $2C Buffer 1 Data Byte 6

DTRBS1 [7] $2D Buffer 1 Data Byte 7

The Bit 0 (LSB) of t he Buffer 0 Data Byte 0 is the

first received bit in time (the oldest).

Ac cording to the Data F ormat, the S tatus byte of a

buf fer has different meaning. H owever a v alue of 0

signals to the ST75C530/540 that a buffer is empty.

This value is set by the Host each time it has

emptied the buffer. After having used one buffer,

the host must select the other buffer for the next

operation. The Host must start with the Buffer 0 as

soon as the

STA_109

signal goes.

A mechanism of interruption (

IT3

for Receive) is

associated with the Data Buffer managment. Each

time a buffer is filled by the ST75C530/540 it gen-

erates an interrupt.

X.4 - Interruption

Two Inter rupt signals are provided in order to syn-

chronize the Data Buffer Exchanges.

IT2

is asso-

ciated with the T ransmit Buffer mechanism and

IT3

with the Receive Buffer mechanism.

In order to enable these interrupts, the Host proc-

essor must set the bit 2 (for

IT2

) and the bit 3 (for

IT3

) of the

ITMASK

Regist er to 1. It must also set

the Bit 7 of the

ITMASK

globally enable all the selected sources of interrup-

tion.

When an Interrupt occurs (low level on

SINTR

pin)

the user must read the

ITSRCR

mine the source of the interrupt, either

IT2

for Tx (if

the bit 2 is 1) or

IT3

for Rx (if the bit 3 is 1).

Once the Interrupt has been serviced, the host

must acknowledge it by writing a $00 value into the

ITRES2

for

IT2

, or

ITRES3

for

IT3

These registers have the following address :

Name Address Type Description

ITRES2 $42 Write only Clear IT2

ITRES3 $43 Write only Clear IT3

ITMASK $4F Read/Write Interrupt Mask

ITSRCR $50 Read Only Interrupt Source

Notes : 1. The ST75C530/540 does not check that the interrupt has

been acknow le dged.

2. Even if the Host does not use the interruption, the

ST75C530/540 will set the bit 2 (for

IT2

) and/or bit 3 (for

T3)

of the

ITSRCR.

3. The ST75C530/540 uses only the Data Buffer Status

Bytes to detect Overrun or Underrun Error. These errors

are reported into the

SYSERR

byte, and could generate

an interr upt I

T0.

The equivalent schematic is : see Figure 21.

The interrupt mechanism assumes that the Host

processor uses a Level sensitive interrupt (active

low). The F low chart of the Host interrupt service

routine looks generaly like Figure 22.

X.5 - Data Format

Different Formats of Data can be Transmitted/Re-

ceived to/from the Telephone Line.

These Formats can be selected when entering the

Data Mode by using the

FORM

command.

The Format of the Data can be changed, on the fly

in the Data Mode during the same communication,

by sending a different

FORM

command at any time.

Not e tha t for F ul l Duple x op erat io n the Data F or-

mat is the same for the transmitter and the re-

ceiver.

X - PARALLEL DATA E XCHANG E (continued)

ST75C 530 - ST75C540

61/84

SINTR

0123456

01234567

(Rx buffer filled)

ITRES 3

(write only)

(Tx buffer emptied)

ITRES 2

(write only)

From

ST75C540

DSP

ITSRCR

(read only)

ITMASK

(read write)

75C53033.EPS

Figure 24

Yes

= 0

Yes

RETURN

READ ITSRCR

MASK UNWANTED BITS

BIT 2 = 1

EXECUTE IT_TRANSMIT

WRITE 00 INTO ITRES2

Yes

BIT 3 = 1

EXECUTE IT_RECEIVE

WRITE 00 INTO ITRES3

(Other Interrupts)

Execute Tx Buffer

Management

Reset IT2

Execute Rx Buffer

Management

Reset IT3

If all sources served return from interrupt

Check only the Interrupt sources

that we want to manage under Interrupt

75C53034.EPS

Figure 25

X - PARALLEL DATA E XCHANG E (continued)

ST75C 530 - ST75C540

62/84

X.6 - FORM Command

The

FORM

command allows the selection of the

Data Format. The Par ameter syntax is as follows :

Field Byte Pos. Value Definition

X_SYNC 1 2..0 000*

001

010

011

100

Synchronous format

Transmit continuous

“1"(1)

HDLC framming

Transmit continuous

”0"(1)

UART

X_ANBIT 2 1..0 00

01 7 Bit per character

8 Bit per character

X_APAR 2 3..2 00

No parity

Even parity

Odd parity

X_ASTOP 2 5 0

11 stop bit(1)

2 stop bit(1)

Note : 1. Transmit only

X.6.1 - Synchr onous Mode

The synchronous mode is the default mode, if no

FORM

command is used.

The transmitter reads the bits in the DUAL Ram

Buffer

DTTBFx

(starting with the Bit 0 of Byte 0 of

Buffer 0) and send them over the Telephone line.

The Buffer Status Byte

DTTBSx

contains the num-

ber of Data Bytes to transmit.

T he Rece iv er writ e the rec eiv ed bits com ing from the

Telephone line and write them into the DUAL Ram

Buffer

DTRBFx

(star tin g with the Bit 0 of th e Byte 0 of

the Buffer 0). The Buffer Status Byte

DTRBSx

contains

the n um ber of Data B y tes r ec eiv ed (general y 8) .

The time between each

IT2

interrupts (or

IT3

) i s equa l

to 64-b it if the number of Data By tes is set to 8. The

Hos t has the full 64 bits tim e to serv e th e interrupt :

Bit Rate (bps) Interrupt Time (ms)

14400

12000

9600

7200

4800

2400

1200

300

4.4

5.3

6.6

8.8

13.3

26.6

53.3

213.3

853.3

X.6.2 - HDLC Mode

The HDLC Format can be used for T.30 or ECM

implementations

X.6.2.1 - HDLC Tran smit

The HDLC Transmitter performs the following tasks :

- Flag generation (7E) while in inter-frame.

- Flag generation (7E) at the begining of a frame.

- Zero insertion (after 5 consecutive “1").

- CRC16 computation.

- CRC16 transmission at the end of a frame.

- Flag generation (7E) at the end of a frame.

- Abort frame.

- Programmable number of Starting flags.

- Programmable number of Inter frame flags.

- Programmable number of Ending flags.

The Buf fer S tatus Byte

DTTBSx

defines the frame

type, and the number of Data Bytes to transmit.

X.6.2.2 - HDLC Receive

The HDLC Receiver performs the following tasks :

- Flag recognition.

- Opening flag recognition.

- Zero deletion.

- CRC16 computation.

- CRC16 check ; error CRC16 detection.

- Closing flag recognition.

- Abort frame detection.

- Received CRC.

The Buffer Status Byte

DTRBSx

contains the frame

type, the number of Data Bytes and the error report

if any. The errors detected are :

- CRC16 Error : Wrong CRC received.

- Non byte-alligned frame : The number of Data bits

between the begining of the frame and the end of the

frame ( after “zero” delet ion) is not a byte- mult iple.

- Aborted fr ame : More that 6 cons ecutive “1" re-

ceived.

X.6.3 - UART Mode

In the UART mode the buffers contains only one

Character to transmit or received. The worse c ase

of interrupt rate is obtained with the lower character

bit length (7bit of data, no parity and 1 stop bit) and

is provided in the following table.

Bit Rate (bps) Interrupt Time (ms)

14400

12000

9600

7200

4800

2400

1200

300

0.41

0.82

1.25

1.64

3.75

7.5

120

X.6.3.1 - UART Transmit

The UART Transmitter performs the following tasks :

- Start bit generation.

- Parity Computation.

- Stop Bit generation.

- Break generation.

X.6.3.2 - UART Receive

The UART Rec eiver performs the following tasks :

- Start bit recognition.

- Parity Checking.

- Stop bit Checking.

- Break detection.

X - PARALLEL DATA E XCHANG E (continued)

ST75C 530 - ST75C540

63/84

FORM 3

XMIT 1

XMIT 0

XMIT 1

FORM 2

XMIT 0

STA_106

DATA

TRANSMITTED

COMMANDS :

10 $7E

101

75C53035.EPS

Figure 26

XI - TRANSMITTING DATA IN PARALLEL MODE

XI.1 - Description

XI.1.1 - XMIT Command

The

XMIT

Command works lik e a CTS signal for

the Parallel Data process.

When

XMIT

is off, the ST75C530/540 transmits

continuous “1". When on the ST75C530/540 trans-

mits Data in acc ordance with the

FORM

co mmand

and starts to manage the Data Buffer.

This command can be sent at any time, while in

Data Mode (see Table below).

XI.1.2 - FORM Command

The

FORM

Command can be sent at any time to

redefine the current format. The effect will take

place only when

XMIT

is on.

Here is a formal example s howing the relationship

between

XMIT

, and

FORM

Commands (see Fig-

ure 26).

XI.1.3 - STOP Command

The

STOP

command is used, at the end of the

transmission, to stop sending the carrier on the

telephone line.

Prior to the

STOP

command the user must have

stop the parallel transmition with a

XMIT off

com-

mand.

When the current data buffer will be totaly transmit-

ted, and that no more buffers will be available, that

is to said both

DTTBF0

and

DTTBF1

will be $00

(equivalent to an Under r un condition).

XI.1.4 - Timing

Here are regular sequences to stop properly the

transmition (see Figure 27).

Field Byte Pos. Value Definition

TX_START 1 0 0 *

1(Off) Send

continuous “1" (**).

(On) Send Data

according with the

Format defined in the

FORM

command.

** The

XMIT Off

command takes effect only when the two Transmit

buffers are empty :

DTTBF0

and

DTTBF1

equal to $00.

Feed Last Buffer

XMIT 0

STOP

Feed Last Buffer

XMIT 0

STOP

DATA

TRANSMITTED

STA_106

DATA

TRANSMITTED

STA_106

(ignored until here)

$7ECRC16Last Buffer

Last Buffer

Case # 1 Synchronous Format

Case # 2 HDLC Format

Case # 3 UART Format

XMIT 0

STOP

DATA

TRANSMITTED

STA_106

(ignored until here)

Last Buffer 1

75C53036.EPS

Figure 27

ST75C 530 - ST75C540

64/84

XI - TRANSMITTING DATA IN PARALLEL MODE (continued)

XI.1.5 - FSK Full Duplex Mode

In FSK Full duplex Mode the parallel mode as-

sumes that the Bit time duration is the nominal Bit

rate.

Eac h bit element from the T ransmit buf fer is m ain-

tained during the full bit time.

The Nominal bit clock is defined as follows :

FSK Standard Nominal Transmit Bit Rate (Hz) (1)

V.21 300

Bell 103 300

V.23 Originate 75

V.23 Answer 1200

Note 1 : The accuracy of the Bit clock is given by the

ST75C530/540 os cillato r, a nd mus t be tt e r than 100ppm.

XI.2 - Modem Flow Chart

When Data Mode, each time the ST75C530/540

need a bit to transmit it executes the following

routine (see Figure 28). Where x starts with the

value 0 and toggle thereaf ter between 1 and 0.

XI.3 - Host Flow Chart

Here after are Flowcharts to :

- Establish a V. 29 transmission

- Send Synchronous continuous “$AA, $55, $AA,

$55, ...” sequence. The managment of the Buffers

are done under Interrupt.

- Stop properly the transmition.

Yes

BEGIN

READ BIT IN

INTERNAL BUFFER

EMPTY

SELECT NEXT DUAL

RAM BUFFER X

Yes

DTTBSx = 0

MOVE DTTBFx DATA

TO INTERNAL BUFFER

CLEAR DTTBSx

RAISE IT2 INTERRUPT

RETURN

SIGNAL ERROR

INTO ERR_TX

RAISE IT0 INTERRUPT

SELECT DUAL

RAM BUFFER x = 0

RETURN

75C53037.EPS

Figure 28

Establish a V.29 transmition and send the v ery first

Buffer (see Figure 29).

CONF 0F 08 00 01

HSHK

Yes

STA_106 = 1

FORM 00 (opt)

XMIT 1

FILL FIRST BUFFER

Select V.29 9600bps

Start V.29 sequence

Wait until end

of training

Format synchronous

Fill the first buffer # 0

Start to transmit

the first buffer

FILL FIRST BUFFER

WRITE AA, 55 ...

INTO DTTBF [0..7]

WRITE 08 INTO DTTBFS0

SELECT NEXT BUFFER

IBUF = 1

Tx_COMPLETED = FALSE

ENABLE IT2

ITMASK = 0 x 84

RET

Subroutine :

75C53038.EPS

Figure 29

ST75C 530 - ST75C540

65/84

These flowcharts s how two CP U v ariables labeled

IBUF and Tx_Completed, they are necessary for

the understanding of the mechanism, but there is

differ ent manner s to impl ement it. These two var i-

ables have the following meanning :

- IBUF : This is the number of the DUAL RAM Buffer

currently in use by the Host processor. It starts

with 0 and then alternate 1, 0, 1, 0, ...

- Tx_Completed : This is a Flag to dialog with the

interrupt process in order to stop properly the

transmition.

The other Buffers are sent under interrupt control

(refer to the interrupt flow chart, Figure 30).

To stop properly the transmition, without loss of

Data (see Figure 31).

XI - TRANSMITTING DATA IN PARALLEL MODE (continued)

RETURN

EXECUTE_IT_TRANSMIT

Yes

Tx_COMPLETED ?

Yes

IBUF = 1

WRITE AA, 55, ...

INTO DTTBF1

WRITE 08 INTO DTTBS1

IBUF = 0

WRITE AA, 55, ...

INTO DTTBF0

WRITE 08 INTO DTTBS0

IBUF = 1

(1) (1)

75C53039.EPS

Figure 30

XMIT 00

STOP

Tx_COMPLETED = TRUE

Yes

STA_106 = 1

Stop sending parallel

data (delayed)

Stop signal

Semaphore with interrupt

Wait until last buffer is

transmitted and CCITT

stop sequence completed

75C53040.EPS

Figure 31

XI.4 - Error Detection

Error occurs when the ST75C530 /540 need some

bits from the transmit buffer

DTTBSx

and this buffer

is empty. This condition is called “Underflow”.

This error is signaled in the bit

ERR_TX

of the

SYSERR

byte, and generates an interrupt

IT0

. To

clear the error a

CSE 01

command must be issued.

An Underflow contition occurs when :

- In synchronous mode: the host processor “for-

gets” to feed the current

DTTBSx

buffer.

- In HDLC mode: when, while inside a frame, the

host processor “forgets” to feed the current

DTTBSx

buffer. An abort frame is transmitted in

place of the regular Buffer.

- This condition cannot append in UART mode.

When an underflow condition occur the hos t must

restart the whole parallel initialization, as explained

above.

XI.5 - Synchronous Mode

XI.5.1 - Description

In synchronous mode the ST75C530/540 transmits

the bits contained in the DUAL RAM Buf fer without

any modification. It starts with the Bit 0 of the

DTTBF0[0]

byte.

XI.5.2 - Status Word Format

The Transmit Status Bytes

DTTBS0

DTTBS1

have the same following meaning (see table below).

DTTBSx in Synchronous Mode

Field Pos. Value Definition

BUFF_LENG 3 .. 0 0

Other

Buffer empty.

1 Byte to transmit

(

DTTBFx[0]

2 Bytes to transmit

(

DTTBFx[0]

and

DTTBFx[1]

8 Bytes to transmit

(

DTTBFx[0 .. 7]

Not allowed.

Other 7 .. 4 0 Reserved, must be 0.

This status byte must be written by the Host, after

filing the corresponding dat a buffer

DTTBFx[0..7]

with the right number of data bytes to transmit.

This status byt e is cleared by the ST75C530/540,

just before generating the

IT2

interrupt.

ST75C 530 - ST75C540

66/84

XI.6 - HDLC Mode

XI.6.1 - Description

In HDLC mode the ST75C530/540 transmits the

data bytes contained into the DUAL Ram buffer

packed in side an HDLC frame. The mechanism is

as follows :

- While the Host has no frame to transmit, that is:

as long as

DTTBSx

equals $00, the

ST75C530/540 transmits the HDLC Flag $7E.

- When the Host wants to send some data, it feeds

the buffer with some data bytes to transmit (be-

tween 1 and 8) and set the

BUFF_SFRM

bit in

the

DTTBSx

status buffer. At that time the

ST75C530/540 start sending data contained in

the Buffer, computin the CRC and performing

“zero intertion” if needed.

- When the host wants to send additional data

(within t he same frame) it feeds the buffers just

like in synchronous mode. If an Underflow condi-

tion occurs, the ST75C530/540 will abort the

frame by sending 8 consecutive “1", and the Host

must restart the whole parallel initialization.

- When the host wants to close a frame, it set the

BUFF_EFRM

bit in the

DTTBSx

status buffer . At

that time the ST75C530/540 will send the con-

tents of the buffer, then send the CRC and an

HDLC closing flag $7E.

- If the Host, wants to abort a frame (while sending

a frame) it set the

BUFF_FRAB

bit in the

DTTBSx

status buffer. At that time, as soon as the last buffer

will be transmitted, the ST75C530/540 will send

8 consecutive “1" and wait for the next buffer.

XI.6.2 - Status Word Form at

DTTBSx in HDLC Mode

Field Pos. Value Definition

BUFF_LENG 3 .. 0 0

other

Buffer empty.

1 Byte to transmit

(

DTTBFx[0]

2 Bytes to transmit

(

DTTBFx[0]

and

DTTBFx[1]

8 Bytes to transmit

(

DTTBFx[0 .. 7]

Not allowed.

BUFF_SFRM 4 0

1Data stream.

Start of frame : the buffer

is a beginning of frame.

BUFF_EFRM 5 0

1Data stream.

End of frame : the buffer

will be followed by the

transmission of the CRC

and closing flag.

BUFF_FRAB 6 0

1Data stream.

Abort frame :

8 consecutive “1" will be

transmitted (whatever

BUFF_LENG

is).

Other 7 0 Reserved, must be 0.

Notes : 1. A buffer can have

BUFF_SFRM

and

BUFF_EFRM s

in the same

DTTBSx

byte, this means that the frame

transmitted is short (between 1 and 8 Bytes long).

2. A n ending frame (with

BUFF_EFRM

set) must have at

least ONE byte of data to transmit.

XI - TRANSMITTING DATA IN PARALLEL MODE (continued)

TRANSMITTED

DATA

BUFF_FRAB

BUFF_SFRM

BUFF_EFRM

BUFF_LENG

(BUFF_DATA)

$7E D0 CRC D1 D2 D3

062 8 5

$7E CRC CRC CRC$7E $7E $7E

D0 D1 D2 D3

000

75C53041.EPS

Figure 32

XI.6.3 - Single Short Frame (see Figure 32)

ST75C 530 - ST75C540

67/84

XI.6.4 - Long Frame

XI - TRANSMITTING DATA IN PARALLEL MODE (continued)

TRANSMITTED

DATA

BUFF_FRAB

BUFF_SFRM

BUFF_EFRM

BUFF_LENG

(BUFF_DATA)

$7E

CRC

$7E

D0 D1 D2 D3

08 4

D0 D1 D2 D3

75C53042.EPS

Figure 33

XI.6.5 - Abort Frame

TRANSMITTED

DATA

BUFF_FRAB

BUFF_SFRM

BUFF_EFRM

BUFF_LENG

(BUFF_DATA)

$7E D0 D1 D2 D3

$7E D5

ABORT D4

D0 D1 D2 D3 D5

D4x

588

x68

75C53043.EPS

Figure 34

XI.6.6 - Abort Due to Underflow

TRANSMITTED

DATA

BUFF_FRAB

BUFF_SFRM

BUFF_EFRM

BUFF_LENG

(BUFF_DATA)

$7E D0 D1 D2 D3

ABORT

$7E D4 D5

D0 D1 D2 D3 D4 D5

ERR_TX

(1) (2) (3)

58 8 0 6 88

75C53044.EPS

Figure 35

Where : 1. The Underflow condition appears when the ST75C530/540 needs, inside a frame, some bytes to transmit and that the

corresponding buffer is empty.

2. The

ERR_TX

bit is cleared with a

CS E 01

Command.

3. After an Underflow condition restart the initialization of the parallel mode and use the buffer number 0.

ST75C 530 - ST75C540

68/84

XI - TRANSMITTING DATA IN PARALLEL MODE (continued)

XI.6.7 - HDLC Special Timming

DATA TRANSMITTED

7E..7E

DATA CRC

_NHFBF

7E..7E

CRC

_NHFCF

7E..7E

_NHFST

Time to fill the Buffer 0

(Otherwise Extra

Flags Added)

Time

to fill the

Buffer 1

Time

to fill the

Buffer 0

DATA

Time to fill the

Buffer 1(Otherwise

Extra Flags Added)

Time

to fill the

Buffer 0

Tx IT

FORM 2 XMIT 1 XMIT 0 STOP

75C53045.EPS

Figure 36

A set of global variables allows the programmation

of the number of flags (7E) generated by the

ST75C530/540 :

- _NHFBF : Number of flags before the first frame.

- _NHFCF : Number of flags between fr ames.

- _NHFST : Number of flags after the last frame.

The default value for all these variables is 0, the

programming range is from 0 to 7FFF (32767).

These varaibales must be modified with a MW or

MWI command (see Figure 36).

XI.7 - UART Mode Description

In UART mode the ST75C530/540 transmits the

data Character contained into the DUAL Ram

buf fe. The mechanism is as follows :

- While the Host has no character to transmit, that

is: as long as

DTTBSx

equals $00, the

ST75C530/540 transmits continuous “1".

- When the Host wants to send a chacarter, it feeds

the buffer with the character to transmit.

- The ST75C530/540 start to send a stop bit (“0" )

then the cha racter con tained in the Buffer, comput-

ing the parity. It send the parity bit, if needed, and

the stop bits (1 or 2 according with the

FORM

command).

- If the user wants to send a break signal, he has

to set the

BUFF_UBRK

bit within the correspond-

ing Status Word (

DTTBSx

). A break signal is

defined as a totaly null character with all s top bits

duration maintained to “0" (e.g: if format is 7 bit,

even parity and 2 stop bit , break is a ”0" durring

10 bit). Multiple continuous breaks (“0" continu-

ous signal) can be send by using consecutive

buffers with

BUFF_UBRK

set to 1.

XI.7.1 - Status Word Form at

DTTBSx in UART Mode

Field Pos. Value Definition

BUFF_LENG 3 .. 0 0

other

Buffer empty.

1 character to transmit

(

DTTBFx[0]

Not allowed.

BUFF_UBRK 6 0

1Normal character.

Break signal : a complete

“0" character with all stop

bits equal to ”0".

Other 7 0 Reserved, must be 0.

ST75C 530 - ST75C540

69/84

XII - RECEIVING IN PARALLEL MODE

XII.1 - Description

When the STA_109 (CD) signal goes on, the

ST75C530/540 will write received data into the

DUAL RAM buffer DTRBS0 at first.

XII.1.1 - Initialization

The host processor must enable the IT3 receive

interrupt first.

Then it m ust empty the two DTR BS0 and DTR BS1

registers by writting $00 at these locations.

As soon as the first IT3 interrupt appears, the host

must proceed with the DTRBS0 buffer.

XII.1.2 - Loss of Carrier

Each time a loss of carrier appears the

ST75C530/540 stops updating the Data buffer. If

the carrier reappers the host must proceed again

with the initialisation sequence.

XII.1.3 - FSK Synchronization

The FSK Full Duplex demodulator uses an algo-

rithm based on the transitions of the received sig-

nal. The synchronization mechanism is adjusted

with each signal transiton in order to sample the

demodulated signal at the middle of the bit

(see Figure 37).

XII.2 - Modem Flow Chart

When in parallel data mode, each time the

ST75C530/540 has receive some bit of data it

executes the following routine (see Figure 38).

W here x start with the value 0 and toggle between

1 and 0.

DEMODULATED

SIGNAL

SAMPLE TIME

RECEIVE BIT 01

00 100

75C53046.EPS

Figure 37

Yes

BEGIN

WRITE BIT IN

INTERNAL BUFFER

FULL

SELECT NEXT DUAL

RAM BUFFER X

Yes

DTRBSx = 0

MOVE DATA FROM INTERNAL

BUFFER TO DTRBFx

WRITE DTRBSx

RAISE IT3 INTERRUPT

RETURN

SIGNAL ERROR

INTO ERR_Rx

RAISE IT0 INTERRUPT

SELECT DUAL

RAM BUFFER x = 0

RETURN

75C53047.EPS

Figure 38

XII.3 - Host Flow Chart

Hereafter are flowcharts to :

- Establish a V.29 reception.

- Receive synchronous data. This task is per-

formed under interrupt.

- Handle properly some temporary loss of carrier.

ST75C 530 - ST75C540

70/84

Es tablish the reception (see Figure 39).

XII - RECEIVING IN PARALLEL MODE (continued)

CONF 0F 08 00 01

SYNC1

Yes

STA_109 = 1

FORM 00 (opt)

Select V.29 9600bps

Arm V.29 receiver

Wait until V.29

carrier detected

Format synchronous

Clear the first

buffers #0 and #1

In case of lost of carrier

while in data mode

CLEAR FIRST BUFFER

WRITE 00 INTO DTRBFS0

WRITE 00 INTO DTRBFS1

SELECT NEXT BUFFER

IBUF = 0

ENABLE IT3

ITMASK = 0 x 88

RET

Subroutine :

CLEAR FIRST BUFFER

Yes

STA_109 = 0

75C53048.EPS

Figure 39

Notes : 1. At that step the host c an check t hat the co rresponding

DTRBSx

buffer is full (different from $00), otherwise it is

an error.

2. This means read

BUFF_LENG

bytes, inside the Receive

buffer

DTRBFx

starting from location

DTRBFx[0]

DTRBFx[BUFF_LENG - 1]

. In synchronous mode, the

BUFF_LENG

is always 8 bytes, except when a

STA_109

lost appears in the middle of the buffer.

RETURN

Yes

IBUF = 1

READ DTRBS1

EXTRACT BUFF_LENG

IBUF = 0

EXECUTE_IT_RECEIVE

READ DTRBF1 DATA

BUFF_LENG TIMES (2)

WRITE 00 INTO DTRBS1

READ DTRBS0

EXTRACT BUFF_LENG

IBUF = 1

READ DTRBF0 DATA

BUFF_LENG TIMES (2)

WRITE 00 INTO DTRBS0

(1) (1)

75C53049.EPS

Figure 40

These flowcharts show one CPU variable labeled

IBUF which is necessary for t he understanding of

the mechanism, but there ar e different manners to

implement it.

- IBUF : this is the number of the DUAL RAM buffer

currently in use by the Host processor. It starts wit

0 an then alternates 1, 0, 1, 0, ...

The received bits are read by an interrupt routine

(See Figure 40).

XII.4 - Error Detection

Error occurs when the ST75C530/540 has re-

ceived some bits and that the buffer

DTRBSx

is not

empty, this condition is called “Overflow”.

This error is signaled in the bit

ERR_RX

of the

SYSERR

byte, and generates an interrupt

IT0.

clear the error a

CSE 02

command must be issued.

An Overflow condition occurs when :

- In synchronous mode: the host processor “for-

gets” to empty the current

DTRBSx

buffer.

- In HDLC mode: when, while inside a frame, the

host processors “forgets” to empty the current

DTRBSx

buffer.

- In UART mode, this cannot happen.

When an Overflow condition occurs the host must

restart the whole parallel initialisation.

ST75C 530 - ST75C540

71/84

XII - RECEIVING IN PARALLEL MODE (continued)

XII.5 - Synchronous Mode

XII.5.1 - Description

In synchronous mode the ST75C530/540 writes

the received bit into the DUAL RAM Buffer without

any modification. It starts with the Bit 0 of the

DTRBF0[0]

byte.

XII.5.2 - Status W or d Format

The receive Status Byte

DTRBS0

DTRBS1

have

the same following meaning (See Table below).

The

BUFF_LENG is always 8 except when a lost

of carrier (

STA_109

going to 0) happens.

This status byte is set by the ST75C530/540, just

before generating the

IT3

interrupt.

XII.6 - HDLC Mode

XII.6.1 - Description

In HDLC mode the ST75C530/540 extracts from

the received HDLC frame the Data information

only. It report s, trough t he DUAL Ram buffer, only

data information and frame validity. The mecha-

nism is as follows :

- As long as the ST75C530/540 receives continu-

ous HDLC Flag $7E, nothing happens. Note t hat

the ST75C530/540 allows zero sharing between

adjacent flags.

- When the ST75C530/540 receives some data, it

removes inserted “zero” if needed, and starts t o

compute the CRC. As soon as its internal buffer

is full, the ST75C530/540 writes the received data

into the

DTRBFx

buffer and sets the

BUFF_SFRM

inside the

DTRBSx

status byte.

- When receiving additional data, the

ST75C530/540 feeds the buffer just like in syn-

chronous mode.

- When the ST75C530/540 receives a closing flag

(which can be shared with the f ollowing opening

flag) it compares the received CRC with its inter-

nal computation. It writes the contents of the

received last data into the

DTRBFx

buffer, sets

the

BUFF_EFRM

bit and reports any frame error

in the

DTRBSx

BUFF_ERRS

bits.

Reported errors are :

•CRC error (lowest priority): the received CRC

is not equal to the computed CRC. Some bits,

inside the frame, are erroneous.

•Non Byte-Aligned frame (middle priority): the

received data bit count (after deletion of the

“zero inserted”), between the opening and the

closing flag, is not a multiple of 8.

•Aborted frame (highest priority): the frame was

aborted with at least 7 consecutive “1"

- An abort frame can be also detected, while in the

inter frame mode, if instead of receiving $7E flag,

the ST75C530/540 receive more than 7 consecu-

tive “1". In this case only one Aborted frame is

signaled, event if the ”1" condition is maintained.

DTRBSx in Synchronous Mode

Field Pos. Value Definition

BUFF_LENG 3 .. 0 0

Other

Buffer empty.

1 Byte received

(

DTRBFx[0]

2 Bytes received

(

DTRBFx[0]

and

DTRBFx[1]

8 Bytes received

(

DTRBFx[0 .. 7]

Not used.

Other 7 .. 4 0 Not used.

XII.6.2 - Status Word Format

DTRBSx in HDLC Mode

Field Pos. Value Definition

BUFF_LENG 3 .. 0 0

other

Buffer empty.

1 Byte received

(

DTRBFx[0]

2 Bytes received

(

DTRBFx[0]

and

DTRBFx[1]

8 Bytes received

(

DTRBFx[0 .. 7]

Not allowed.

BUFF_ERRS 5 .. 4 0 0

0 1

1 0

1 1

No error.

CRC error.

Non Byte-Aligned frame.

Aborted frame.

BUFF_SFRM 6 0

1Data stream.

Start of frame : the buffer

is a beginning of frame.

BUFF_EFRM 7 0

1Data stream.

End of frame : the buffer

is a closing frame.

ST75C 530 - ST75C540

72/84

XII - RECEIVING IN PARALLEL MODE (continued)

XII.6.3 - Single Short frame

RECEIVED

DATA

BUFF_ERRS

BUFF_SFRM

BUFF_EFRM

BUFF_LENG

(BUFF_DATA)

$7E D0 CRC D1 D2 D3

062 8

$7E CRC CRC CRC$7E $7E $7E

D0 D1 D2

75C53050.EPS

Figure 41

XII.6.4 - Long Frame

RECEIVED

DATA

BUFF_ERRS

BUFF_SFRM

BUFF_EFRM

BUFF_LENG

(BUFF_DATA)

$7E

CRC $7E

D0 D1 D2 D3

(1)

75C53051.EPS

Figure 42

Note : 1. If error occurs during the reception, it is signaled in this last buffer.

XII.6.5 - Aborted Frame

RECEIVED

DATA

BUFF_ERRS

BUFF_SFRM

BUFF_EFRM

BUFF_LENG

(BUFF_DATA)

$7E D0 D1 D2 D3

$7E D5

ABORT D4

D0 D1 D3

88x 8

75C53052.EPS

Figure 43

ST75C 530 - ST75C540

73/84

XII - RECEIVING IN PARALLEL MODE (continued)

XII.7 - UART Mode

XII.7.1 - Description

In UART mode t he ST75C530/540 extracts from the

received Characters the Data information only. It re-

ports, trough the DUAL Ram buffer , only data informa-

tion character validity. The mechanism is as follows :

- As long as the ST75C530/540 receives continu-

ous “1" nothing happens.

- When the ST75C530/540 receives the start bit

(“0") it starts to compute the parity . As soon as the

number of data bit (defined by the FORM com-

mand) is received, the ST75C530/540 writes the

received character into the DTRBFx buffer and

update the receiv e Status word DTRBSx.

- The Reported errors are :

•Parity error (lowest priority): the received parity

is not equal to the computed parity. Some bits,

inside the char ac ter, are erroneous.

•Stop bit error ( middle priority): the bit after the

parity was not a stop bit (“1"). Note that if the

two stop bit format was sel ected, only the first

stop bit will be checked.

•Bre ak De te ction ( highest priority) : the c haract er is

a break signal as defined in the transmit section. If

the dur ation of the br eak is lon ger t han one char-

acter, only one br eak buf fer will be re ported.

XI.7.2 - Status Word Format

DTRBSx in UART Mode

Field Pos. Value Definition

BUFF_LENG 3 .. 0 0

Other

Buffer empty.

1 character received

(DTRBFx[0]).

Not allowed.

BUFF_ERRS 5..4 00

No error.

Parity error

Stop bit error

Break signal detected

XIII - VOCODER DATA EX CHANGE

XIII.1 - Overview

The ST75C530/540 can receive (or transmit)

coded voice from (to) the telephone line or the

audio interface. The receiving mode is the CODER

mode while the transmit is the D ECODE R mode.

Two format s o f Voice c om press io n ar e pr ov ided: Low

bit ra te and A DPCM. In all the format s and spe ed the

man agement o f the Code d Voice is exactl y the s ame.

In any format a frame of all dat a equal to zero will

be sy nthesised (DECODER ) as a frame of silence.

XIII.2 - Vocoder Buffer

A buffer area is reserved in the DUAL ram to

exchange Voice between the ST75C530/540 and

the Host processor. This area is used either for record-

ing (CODER) or playing back (DECODER) the voi ce

signal.

The DUAL Ram area associated with the VO-

CO DER is as follows :

Name Address Description

VOCSTA $1C Vocoder Buffer Status

VOCDATA $1D..$2E Vocoder Buffer Data

VOCCORR $2F..$30 Vocoder Buffer Corrector

The IT1 interrupt signal is dedicated to the V ocoder

Buff er Management.

XIII.3 - Transmit (DECODER)

This mode is entered with the CONF DECODER

command.

If the ADPCM or Low bit rate without error correc-

tion mode (CONF _ERCOR = 0) are selected, the

user needs to feed the vocoder buffer with 18 bytes

of voice data, then set the VOCSTA byte with a

value different from zero.

In the low bit rate w ith error m ode (CONF_ER COR

= 1), the user needs to feed the vocoder buffer with

20 bytes of voice data, then set the VOCSTA byte

with a value different from zero.

Once the ST75C530/540 have read the buffer, it

clears the VOCST A byte and raise the IT1 interrupt.

The IT1 interrupt rate is as follows :

Mode Interrupt

Time (ms)

Number of

Voice Samples

in the Buffer

(8kHz sampling)

ADPCM 32Kpbs 4.5 36

ADPCM 24Kpbs 6 48

ADPCM 16Kpbs 9 72

Low Bit Rate Nominal

(with and without

error correction)

30 240

Low Bit Rate

Fast/Slow Playback Depends on

speed 15 to 45 Depends on

speed 120 to 360

Low Bit Rate Pause 0 -

A silence can be generated by writing zero to all the

VOCDATA bytes (and VOCCORR bytes if

CONF_ERCOR = 1). The duration of the silence

will be the same as the other fram es of signal.

As the buffer contains always a complete number

of samples representing the same duration, it is

easy to randomly advance forward/backward in a

message.

If the user does not feed the Buffer within the

Interrupt time, the ST75C530/540 will signal this

error by rising the ERR_VOCO in the SYSERR byte

and rising the IT0 Interrupt. In this case the pre-

vious frame will be re-transmited.

ST75C 530 - ST75C540

74/84

XIII.4 - Receive (CODER)

This function can be entered either by :

- The CONF CODER Command. This corresponds

to the “Normal Answering Mac hine” function.

- The MODC Command with MODC_COD = 1, in

the HANDSET Mode. This corresponds, in the

HANDSET mode to the “Conversation Record-

ing” function. This reduced sub-mode does not

allow ADPCM format and does not perform VAD

(V oice Activity Detector).

Once this function is selected, the ST75C530/540

starts to code the voic e s ignal, writes one frame of

compressed voice into the V OCDATA bytes (if the

low bit rate mode is selected, computes always the

Corrector bytes and writes them in the VOCCORR

bytes) then writes the VOCSTA byte and generates

the IT1 interrupt.

The IT1 interrupt rate is as follows :

Mode Interrupt

Time

(ms)

Number of Voice

Samples

in the Buffer

(8kHz sampling)

ADPCM 32Kpbs 4.5 36

ADPCM 24Kpbs 6 48

ADPCM 16Kpbs 9 72

Low Bit Rate (with and

without error correction) 30 240

Note that the VOCCORR are always computed,

whatever the value of CONF_ERCO R.

The format of the VOCSTA byte is as follows :

VOCSTAT

Format Field Pos. Value Definition

Low Bit

Rate VOC

_VAD 70

VAD Unvoiced Signal.

VAD Voice Signal.

VOC

_NUM 4..0 10100 (20 decimal) Number

of VOCDATA Bytes

ADPCM VOC

_VAD 70

VAD Unvoiced Signal.

VAD Voice Signal.

VOC

_NUM 4..0 10010 (18 decimal) Number

of VOCDATA Bytes

Note that in “Conversation recording” the VOCST A

byte is always $14.

The user must read the VOCDATA (and optionally

the VOCCORR) bytes and clear the VOCSTA byte

(writing $00).

If the us er does not clear the VOCSTA byte within

the interrupt time, the ST75C530/540 will signal

this error by rising the ERR_VOCO in the SYSERR

byte and rising the IT0 Interrupt. In this case the

current frame is lost.

If the CONF_S UPSI L bit is 1 in the CONF CODE R

command, the interrupts IT1 appears only when

the VAD has detected a v oiced signal.

XIII - VOCODER DATA EX CHANGE (continued)

ST75C 530 - ST75C540

75/84

XIV - TRANSPARENT MODE DA TA EXCHANGE

The mode uses the DPR locations to exchange

samples between the host and the AFE’s . To allow

maximum int errupt latency, the DSP uses intern al

buffers to store samples and updates the DPR

buffers when internal buffers are ready. The DPR

buffers are bidirectional, thus doubling the effective

DPR capacity.

The transfer mechanism is depicted below :

1. At baud rate (every 4 samples at 9.6kHz), the

DSP transfers 4 samples from the M odem AFE

to the internal receive buffer , after sending them

through a high-pass filter with a transfer function

H(z) = (z-1)/ (z-0.875) used to remove all DC

components from the signal, and transfers

4 samples from the Internal transmit buffer to the

Modem AFE. This comes from the currently

implemented internal scheduling. The same

operation is performed for the voice AFE.

2. After 3 bauds, the int ernal receive buffer is full

(the int ernal transmit buffer is also empty), the

DPR buffer is copied to the internal transmit

buffer, then the internal receive buffer is copied

into th e D PR .

3. A host interrupt is generated : during servicing,

the host reads the DPR sample buffer then

writes it with new transmitted samples.

XIV.1 - Samp le buffers

The mode uses the DPR locations to exchange

samples between the host and the AFE’s ; since no

data t ransfer (HDLC, UART) occurs in this mode,

the full 0x10 .. 0x3F DPR locations are available.

The Modem sample buffer (MODEMDPR) uses

locations 0x10 to 0x27 (24 bytes) to exchange

12 MAFE samples. The audio sample buffer

(AUDIODPR) uses locations 0x28 to 0x3F to ex-

change 12 VAFE samples. Samples are repre-

sented in 16-bit linear data format, byte order is

little-Endian (Intel-like, LSByte at low address), and

consecutive locations correspond to consecutive

samples in time. Example : locations ( 0x10, 0x11)

correspond to the first sample (LSB, MSB) re-

ceived from the line AF E.

XIV.2 - Interrupts

The DSP signal events to the host using the inter-

rupt mailbox (ITREST[0..6], ITMASK, ITSRCR).

IT2 is set by the DSP whenever the DPR buffers

are ready. This interrupt source can be masked

through ITMASK, and acknowledged using

ITSRCR[0..6]. The host interrupt service routine

should read received samples from the DPR, write

transmitted samples to the DPR, then acknow-

ledge by clearing the IT2 flag. The interrupt latency

is approximately equal to the interrupt period, i.e.

T = 1/800 = 1.25ms. Overrun and underrun condi-

tions may occur if the host interrupt latency ex-

ceeds the previous value. Since this situation is

unrecoverable, no specific action is taken. Never-

theless, for debug purposes the user can detect

this condition by probing the interrupt line (SINTR),

and trigger on a pulse width greater than the maxi-

mum allowed latency.

ST75C 530 - ST75C540

76/84

XV - DEFAULT CALL PRO GRES S TO NE DETECTORS

-10

-20

-30

-40

-50 0 200 400 600 800 1000

dB no detection

detection

step = 10Hz

reference level = 0dB

f (Hz)

75C53053.EPS

Figure 44 : Call Progress Tone Detector Band 1

-10

-20

-30

-40

-50

2000 2040 2080 2120 2160 2200

f (Hz)

no detection

detection

reference level = 0dB

step = 10Hz

75C53055.EPS

Figure 46 : 2100Hz Answer Tone Detector

-10

-20

-30

-40

-50200 320 440 560 680 800

f (Hz)

no detection

detection

step = 10Hz

reference level = 0dB

75C53056.EPS

Figure 47 : 440Hz Tone Detector

-8

-16

-24

-32

-40 0 720 1440 2160 2880 3600

f (Hz)

no detection

detection

step = 100Hz

reference level = 0dB

75C53054.EPS

Figure 45 : Call Progress Tone Detector Band 2

XV I - DEFAULT ANSWE R T ONE DETE CT ORS

ST75C 530 - ST75C540

77/84

XVII - ELECTRICAL SCHEMATICS

ST75C530

ST75C540

6162636465666768697071727374757677787980

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

GIO00

RING

RELAY0

RGND

INT/MOT

SCS

SINTR

RELAY1

GIO01

GIO02

GIO03

GIO04

GIO05

GIO06

GIO07

DD3

DGND3

DD4

DGND4

GIO10

SPK1N

SPK1P

AGNDTA

REFN

REFP

AGNDRA

MIC1

MIC2

MIC3

DDM

AGNDM

TxA2

TxA1

EYEX

EYEY

RxA

DGND6

DD6

DGND1

SA6

SA5

SA4

SA3

SA2

SA1

SA0

SDS

SR/W

DD2

DGND2

DD1

SD7

SD6

SD5

SD4

SD3

SD2

SD1

SD0

GIO11

GIO12

GIO13

GIO14

GIO15

GIO16

GIO17

CLKOUT

DGND5

XTALL

EXTALL

TEST0

RESET

SPK3N

SPK3P

SPK2N

SPK2P

DDA

XPLL

C14 (1)

100nF

C13 (1)

100nF

C15

10mF

C12 (1)

100nF

C3 (1)

100nF

2.2mF

C10 (1)

100nF C11

4.7mF

2.2mFC16 (1)

100nF

2.2mF

2.2mFC7 (1)

100nF

C5 (1)

100nF

R1 1.2kW

R2 1.2kW

R3 1.2kW

C17 (1)

2.2nF

R4 1.2kW

C18 (1)

2.2nF

C19 (1)

2.2nF

C20 (1)

2.2nF

4.7mFC9 (1)

100nF

MIC1

MIC2

MIC3

RxA

0VA

+5VA

AGNDM

AGNDRA

75C53057.EPS

Figure 48

ST75C 530 - ST75C540

78/84

XVIII - PCB DESIGN GUIDELINES

Performances of the FAX modem depends on the

ST75C530/540 intrinsic performances and on the

proper PC board layout.

All aspects of the proper engineering practices, for

PC board design, are beyond the scope of this

paragraph.

We recommend the following points :

- in a 4- layer PC boar d : Separated digital ground

and analog ground, connected together at one

point, as close as possible to the ST75C530/540,

- in a 2-layer PC board : Provide a ground grid in all

space around and under components on both sides

of the ban d an d conn ect to avoid s mall islands,

- both AGNDR and AGNDT must be connected

with very low impedance to a single point, (see

Chapter I.6, Pow er Supply),

- the four 2. 2nF capacitors connected to the RxA

and MIC1, MIC2, MIC3 Pins must be as close as

possible to them,

- the two 100nF capacitors connected to the VREFP and

VREFN pins mu st be as clos e as possib le to them,

- analog and digital supplies must be connected

together , at a single point, as close as possible to

the chip.

ADC

MUTE

DAC Line

HYBRID

TxA1

TxA2

RxA

ADC

MIC3

MIC1

MIC2

SPK2

MUTE

SPK3

MUTE

SPK1

MUTE

[0..-30]dB

Step 3dB

DAC

ATT_SPK

ATT_LOC

ATT_TX

4 TONES

GENERATOR

DTMF

DETECTOR

16 TONE

DETECTORS

4 TONE

DETECTORS

V.21 FLAG

DETECTOR

RING

DETECTOR

DUAL

RAM

INTERFACE

Programmable

Attenuation Addition

of Signals Automatic

Gain

75C53058.EPS

Figure 49 : Tone Mode (TONE)

ADC

MUTE

DAC Line

HYBRID

TxA1

TxA2

RxA

ADC

MIC3

MIC1

MIC2

SPK2

MUTE

SPK3

MUTE

SPK1

MUTE

[0..-30]dB

Step 3dB

DAC

ATT_SPK

ATT_LOC

ATT_TX

4 TONES

GENERATOR

DTMF

DETECTOR

6 TONE

DETECTORS

4 TONE

DETECTORS

V.21 FLAG

DETECTOR

UART

DUAL

RAM

INTERFACE

Programmable

Attenuation Addition

of Signals Automatic

Gain

RING

DETECTOR

V.23

DEMODULATOR

75C53059.EPS

Figure 50 : Tone Mode with Caller ID (TONE CI D)

XIX - APPENDIX A : MO D E S O F OP ERATION

ST75C 530 - ST75C540

79/84

XIX - A P PENDIX A : MOD E S O F O PERATION (continued)

DUAL

RAM

INTERFACE

ADC

MUTE

DAC Line

HYBRID

TxA1

TxA2

RxA

ADC

MIC3

MIC1

MIC2

SPK2

MUTE

SPK3

MUTE

SPK1

MUTE

[0..-30]dB

Step 3dB

DAC

ATT_LOC

ATT_TX

FAX

TRANSMITTER

FAX

RECEIVER

4 TONE

DETECTORS

V.21 FLAG

DETECTOR

Programmable

Attenuation Addition

of Signals Automatic

Gain

DTMF

DETECTOR

(V.21ch2 only)

HANDSHAKE

AND STATUS

REPORT

HDLC

SINTR

SD[0..7]

75C53060.EPS

Figure 51 : Fax Modem Mode (MODEM)

ECHO

CANCELLER

DUAL

RAM

INTERFACE

ADC

MUTE

DAC Line

HYBRID

TxA1

TxA2

RxA

ADC

MIC3

MIC1

MIC2

SPK2

MUTE

SPK3

MUTE

SPK1

MUTE

[0..-30]dB

Step 3dB

DAC

ATT_LOC

ATT_TX

MODEM

TRANSMITTER

MODEM

RECEIVER

Programmable

Attenuation Addition

of Signals Automatic

Gain

HANDSHAKE

AND STATUS

REPORT

SINTR

SD[0..7]

UART

HDLC

UART

HDLC

75C53061.EPS

Figure 52 : Data Modem Mode (Full Duplex Modem ) (ST75C540 only)

ST75C 530 - ST75C540

80/84

XIX - A P PENDIX A : MOD E S O F O PERATION (continued)

ADC

MUTE

DAC Line

HYBRID

TxA1

TxA2

RxA

ADC

MIC3

MIC1

MIC2

SPK2

MUTE

SPK3

MUTE

SPK1

MUTE

[0..-30]dB

Step 3dB

DAC

ATT_MIC

VOICE

ACTIVITY

DETECTOR

RING

DETECTOR

DUAL

RAM

INTERFACE

Programmable

Attenuation Addition

of Signals Automatic

Gain

ATT_SEL

ATT_LOC

4 TONE

DETECTORS

DTMF

DETECTOR

AGC

CODER

4 TONE

GENERATORS

75C53063.EPS

Figure 54 : Coder Mode (CODER)

DUAL

RAM

INTERFACE

ADC

MUTE

DAC Line

HYBRID

TxA1

TxA2

RxA

ADC

MIC3

MIC1

MIC2

SPK2

MUTE

SPK3

MUTE

SPK1

MUTE

[0..-30]dB

Step 3dB

DAC

ATT_LOC

ATT_TX

4 TONE

DETECTORS

Programmable

Attenuation Addition

of Signals Automatic

Gain

DTMF

DETECTOR

LINE ECHO

CANCELLER

RING

DETECTOR

DECODER

4 TONE

GENERATORS

75C53062.EPS

Figure 53 : Decoder Mode (DECODER)

ST75C 530 - ST75C540

81/84

XIX - A P PENDIX A : MOD E S O F O PERATION (continued)

AGC

DUAL

RAM

INTERFACE

4 TONE *

DETECTORS

AGC

CODER

4 TONE *

GENERATOR

* default is 2.

RING

DETECTOR

ADC

MUTE

DAC Line

HYBRID

TxA1

TxA2

RxA

ADC

MIC3

MIC1

MIC2

SPK2

MUTE

SPK3

MUTE

SPK1

MUTE

[0..-30]dB

Step 3dB

DAC

ATT_MIC

HALF/FULL DUPLEX

SPEAKER-PHONE

ALGORITHMS

ATT_TX

75C53065.EPS

Figure 56 : Telephone Mode (HANDSET)

ADC

MUTE

DAC Line

HYBRID

TxA1

TxA2

RxA

ADC

MIC3

MIC1

MIC2

SPK2

MUTE

SPK3

MUTE

SPK1

MUTE

[0..-30]dB

Step 3dB

DAC

ATT_MIC

Programmable

Attenuation Addition

of Signals

Automatic

Gain

4 TONE

DETECTORS

DTMF

DETECTOR

AGC

LINE ECHO

CANCELLER

DUAL

RAM

INTERFACE

ATT_TX

75C53064.EPS

Figure 55 : Room Monitoring Mode (ROOM)

ST75C 530 - ST75C540

82/84

XIX - A P PENDIX A : MOD E S O F O PERATION (continued)

ADC

MUTE

DAC Line

HYBRID

TxA1

TxA2

RxA

ADC

MIC3

MIC1

MIC2

SPK2

MUTE

SPK3

MUTE

SPK1

MUTE

[0..-30]dB

Step 3dB

DAC

Programmable

Attenuation Addition

of Signals Automatic

Gain

ATT_MIC

DC-

BLOCKA

DC-

BLOCK

ATT_SPK

ATT_LOC

6 PRIMARY

TONE

DETECTORS

DTMF

DETECTOR

4 SECONDARY

TONE

DETECTORS

4 TONE

GENERATORS

ATT_MODRX

ATT_MODTX

ATT_TX

ATT_AUDTX

ATT_AUDRX

DUAL RAM

INTERFACE

ATT_SEL

(*)

(*) H(z) = z - 1

z - 0.875

75C53066.EPS

Figure 57 : Transparent Mode

ST75C 530 - ST75C540

83/84

80 61

21 40

A1 A2

0,25 mm

.010 inch

GAGE PLANE

0,10 mm

.004 inch

SEATING PLANE

PM-1S.EPS

XX - PACKAG E MECHANICAL DATA

80 PINS - FULL THIN PLASTIC QUAD FLAT PACK (TQFP)

Dimensions Millimeters Inches

Min. Typ. Max. Min. Typ. Max.

A 1.60 0.063

A1 0.05 0.15 0.002 0.006

A2 1.35 1.40 1.45 0.053 0.055 0.057

B 0.22 0.32 0.38 0.010 0.012 0.014

C 0.09 0.20 0.004 0.008

D 16.00 0.630

D1 14.00 0.551

D3 12.35 0.486

e 0.65 0.026

E 16.00 0.630

E1 14.00 0.551

E3 12.35 0.486

L 0.45 0.60 0.75 0.020 0.024 0.030

L1 1.00 0.039

o (Min.), 7o (Max.)

1S.TBL

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the

conseque nces of use of such informa tion nor for any infringement of patents or other rights of third parties which m ay resul t from

its use. No licence is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications

mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information

previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems

without expr ess wri tte n approv al of STMi croe lect roni cs.

The ST logo is a registered tradema rk of STMicroelectronics

Purchase of I2C Components of STMicroelectronics, conveys a license under the Philips I2C Patent.

Rights to use these components in a I2C system, is granted provided that the system conforms to

the I2C Standa rd Speci fic at ions as defined by Phi lips .

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ST75C 530 - ST75C540

84/84