F8680A - Asiliant Technologies

F8680A

PC/CHIP

A True Single-Chip PC

Data Sheet

June 1994

PRELIMINARY

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CHIPS logotype, CHIPSLink, CHIPSPort, ELEAT, LeAPSet, NEAT, NEATsx, PEAK, SCAT,

SuperMathDX, SuperState, and Wingine are registered trademarks of Chips and Technologies,

Inc.

CHIPSet, PrintGine, PC/CHIP, Visual Map, WinPC, and XRAM Video Cache are trademarks of

Chips and Technologies, Inc.

IBM AT, XT, PS/2, Micro Channel, Personal System/2, Enhanced Graphics Adapter, Color

Graphics Adapter, Video Graphics Adapter, IBM Color Display, and IBM Monochrome Display

are trademarks of International Business Machines Corporation.

AT&T® is a registered trademark of AT&T Bell Laboratories.

National® is a registered trademark of National Semiconductor Corp.

386SX is a trademark of Intel Corp.

VESA® is a registered trademark of Video Electronics Standards Association.

VL-Bus is a trademark of Video Electronics Standards Association.

Disclaimer

This document is provided for the general information of the customer. Chips and Technologies,

Inc., reserves the right to modify the information contained herein as necessary and the customer

should ensure that it has the most recent revision of the document. CHIPS makes no warranty for

the use of its products and bears no responsibility for any errors which may appear in this

document. The customer should be on notice that the field of personal computers is the subject of

many patents held by different parties. Customers should ensure that they take appropriate action

so that their use of our products does not infringe upon any patents. It is the policy of Chips and

Technologies, Inc. to respect the valid patent rights of third parties and not to infringe upon or

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F8680A PC/CHIP

Product Overview

A true single-chip PC, the F8680A PC/CHIP features the SuperState® R

management system, low power consumption, high performance, direct support of

PCMCIA 2.0 memory and I/O cards, and flexible memory support.

Chips and Technologies, Inc. has designed the F8680A microchip to accommodate a

wide variety of low power, cost-sensitive DOS applications: palmtop, laptop, and

desktop computers, electronic notebooks and handhelds, and embedded controller

systems. Third-party designers can build complete systems around the F8680A chip

by adding only memory, storage, and peripheral devices.

Features

The F8680A PC/CHIP has the following features:

•3.3V/5V operation, fully static design,

and intelligent sleep mode reduce

power consumption approximately

60 percent and allow direct battery

drive.

•PC-compatible design supports PC

software and 8-bit ISA cards.

•SuperState R mode provides a separate

operating environment and enables

complete I/O and interrupt monitoring

without BIOS modification.

•Virtual I/O feature allows device

emulation as well as I/O monitoring

and control.

•Virtual Interrupts feature allows

interrupts to be monitored and/or

redirected before any operating system,

application program, or TSR sees them.

•Full PCMCIA 2.0 memory and I/O

card support ensure compatibility with

current and future expansions.

•26-bit address bus enables 64MB

memory map and allows direct support

of PCMCIA memory card.

•Four-stage pipeline and 14MHz

operation give performance comparable

to a 286 or 386SX system.

•Flexible memory management supports

PCMCIA cards and up to three banks

of PSRAM, SRAM, and/or DRAM.

•Bank switching and high memory

access overcome the 1MB addressing

limitation of the 8086 processor, and

enable PCMCIA and EMS support.

•Single CGA controller manages a CRT

or LCD panel display and requires only

a single 32Kx8 SRAM to minimize

power consumption and board space.

•Visual Map gray scaling provides

excellent visual contrast on any LCD

panel.

•16C450-compatible UART supports

COM1 or COM2 or can be disabled.

•Over 100 configuration registers allow

flexibility, control, and differentiation

in system design.

F8680A PC/CHIP Product Overview ■

Chips and Technologies, Inc. P R E L I M I N A R Y -- Revision 2.0 -- 6/2/94 iii

A block diagram of the F8680A PC/CHIP is shown in Figure 1.

Figure 1. F8680A Block Diagram

PCMCIA 2.0

PCMCIA

Card

Slots A, B

■ Product Overview F8680A PC/CHIP

iv P R E L I M I N A R Y -- Revision 2.0 -- 6/2/94 Chips and Technologies, Inc.

Contents

F8680A PC/CHIP

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Chip TEST Mode . . . . . . . . . . . . . . . . . . . . . . . . 13

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . 15

Central Processor . . . . . . . . . . . . . . . . . . . . . . . . 15

SuperState R Logic . . . . . . . . . . . . . . . . . . . . . . . 15

XT Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . 22

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Memory Subsystem . . . . . . . . . . . . . . . . . . . . . . . 24

CGA-Compatible Graphics Controller . . . . . . . . . . . . . 47

DC Electrical Characteristics . . . . . . . . . . . . . . . . . . 53

AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . 79

Sales Representatives . . . . . . . . . . . . . . . . . . . . . . . . . 80

List of Figures

Figure 1. F8680A Block Diagram . . . . . . . . . . . . . . . . . iv

Figure 2. F8680A Pinout . . . . . . . . . . . . . . . . . . . . . . 1

Figure 3. Bank Switching Logic . . . . . . . . . . . . . . . . . 27

Figure 4. Memory Mapping Logic . . . . . . . . . . . . . . . . 28

Figure 5. Interface to 4-bit DRAM . . . . . . . . . . . . . . . . 32

Figure 6. Interface to 8-bit DRAM . . . . . . . . . . . . . . . . 33

Figure 7. Interface to 1-bit DRAM . . . . . . . . . . . . . . . . 34

Figure 8. Interface to SRAM . . . . . . . . . . . . . . . . . . . 37

Figure 9. Interface to 8-bit ROM . . . . . . . . . . . . . . . . . 39

F8680A PC/CHIP Contents ■

Chips and Technologies, Inc. P R E L I M I N A R Y -- Revision 2.0 -- 6/2/94 v

Figure 10. Chip Pinout Changes for One-Card Configuration . . . 42

Figure 11. Connections for Fully Buffered One-Slot System . . . 43

Figure 12. Chip Pinout for Two-Card Configuration . . . . . . . 44

Figure 13. Connections for Fully Buffered Two-Slot System . . . 45

Figure 14. Circuitry Needed for Sharing the MCCD1-2* Inputs . 46

Figure 15. Connection of Display SRAM . . . . . . . . . . . . . 48

Figure 16. Display Controller Signals to the LCD Panel . . . . . 49

Figure 17. Display Controller Signals to the CRT . . . . . . . . . 52

Figure 18. Typical Output Transition Time

vs Load Capacitance . . . . . . . . . . . . . . . . . . 54

Figure 19. Minimum Output Transition Time

vs Load Capacitance . . . . . . . . . . . . . . . . . . 54

Figure 20. Output Source Current vs Output Voltage, Vcc=4.5V . 55

Figure 21. Output Sink Current vs Output Voltage, Vcc=4.5V . . 56

Figure 22. Output Source Current vs Output Voltage, Vcc=3V . . 57

Figure 23. Output Sink Current vs Output Voltage, Vcc=3V . . . 57

Figure 24. Output Delay Parameters----General Case . . . . . . . 60

Figure 25. Input Setup and Hold Parameters----General Case . . . 60

Figure 26. Timing for System Clocks . . . . . . . . . . . . . . . 62

Figure 27. Timing for Non-page-mode DRAM Cycles . . . . . . 63

Figure 28. Timing for Page-mode DRAM Cycles . . . . . . . . . 63

Figure 29. Timing for SRAM/PSRAM Standard Access . . . . . 64

Figure 30. Timing for SRAM/PSRAM Access

with Early Chip Select . . . . . . . . . . . . . . . . . 65

Figure 31. Timing for DRAM Suspend Mode Refresh . . . . . . 66

Figure 32. Functional Timing for PSRAM Active Mode Refresh . 66

Figure 33. Functional Timing for PSRAM Suspend Mode Refresh 66

Figure 34. Timing for DMA Read Cycles . . . . . . . . . . . . . 67

Figure 35. Timing for DMA Write Cycles . . . . . . . . . . . . . 68

Figure 36. Timing for I/O Read . . . . . . . . . . . . . . . . . . 69

Figure 37. Timing for I/O Write . . . . . . . . . . . . . . . . . . 70

■ Contents F8680A PC/CHIP

vi P R E L I M I N A R Y -- Revision 2.0 -- 6/2/94 Chips and Technologies, Inc.

Figure 38. Timing for XT Bus Memory Read . . . . . . . . . . . 71

Figure 39. Timing for XT Bus Memory Write . . . . . . . . . . . 72

Figure 40. Timing for PCMCIA Memory Read

(1 Cycle Per State) . . . . . . . . . . . . . . . . . . . 73

Figure 41. Timing for PCMCIA Memory Read

(2 Cycles Per State) . . . . . . . . . . . . . . . . . . . 73

Figure 42. Timing for PCMCIA Memory Write

(1 Cycle Per State) . . . . . . . . . . . . . . . . . . . 74

Figure 43. Timing for PCMCIA Memory Write

(2 Cycles Per State) . . . . . . . . . . . . . . . . . . . 74

Figure 44. Timing for Graphics SRAM . . . . . . . . . . . . . . 75

Figure 45. Functional Horizontal Sync Timing for CRT . . . . . 76

Figure 46. Functional Vertical Sync Timing for CRT . . . . . . . 76

Figure 47. Functional Timing for LCD Panel Signals . . . . . . . 77

Figure 48. Timing for RESET . . . . . . . . . . . . . . . . . . . 78

Figure 49. Timing for UART . . . . . . . . . . . . . . . . . . . . 78

Figure 50. 160-Pin Plastic Flat Pack . . . . . . . . . . . . . . . . 79

List of Tables

Table 1. F8680A Pin Allocation . . . . . . . . . . . . . . . . . . 2

Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. Programmable Pin Functions . . . . . . . . . . . . . . 20

Table 4. XT-Compatible I/O Port Assignment . . . . . . . . . 23

Table 5. System Memory Usage . . . . . . . . . . . . . . . . . 24

Table 6. Bank Switch Register Ranges . . . . . . . . . . . . . 26

Table 7. Pin Assignments - DRAM Interface Signals . . . . . . 30

Table 8. Address Multiplexing . . . . . . . . . . . . . . . . . . 31

Table 9. Pin Assignments - SRAM Interface Signals . . . . . . 35

Table 10. Address Bus Connections for Various

SRAM Device Capacities . . . . . . . . . . . . . . . . 36

F8680A PC/CHIP Contents ■

Chips and Technologies, Inc. P R E L I M I N A R Y -- Revision 2.0 -- 6/2/94 vii

Table 11. Pin Assignments - ROM/PROM Interface Signals . . . 39

Table 12. PCMCIA Signal Name Equivalents . . . . . . . . . . 40

Table 13. Operating Conditions . . . . . . . . . . . . . . . . . . 53

Table 14. Capacitance . . . . . . . . . . . . . . . . . . . . . . . 53

Table 15. DC Characteristics at 5V . . . . . . . . . . . . . . . . 55

Table 16. DC Characteristics at 3.3V . . . . . . . . . . . . . . . 56

Table 17. Timing Symbols Associated with Signal Types . . . . 58

Table 18. Timing Parameters, Commercial . . . . . . . . . . . . 59

Table 19. Timing Parameters, Industrial . . . . . . . . . . . . . 59

Table 20. AC Characteristics - System Clock Timings . . . . . . 61

Table 21. AC Characteristics - DRAM Signal Timings . . . . . 63

Table 22. AC Characteristics - SRAM/PSRAM

Standard Signal Timings . . . . . . . . . . . . . . . . 64

Table 23. AC Characteristics - SRAM/PSRAM

Signal Timings with Early Chip Select . . . . . . . . . 65

Table 24. AC Characteristics - Suspend Refresh Signal Timings 66

Table 25. AC Characteristics - DMA Signal Timings . . . . . . 67

Table 26. AC Characteristics - XT Bus I/O Cycle Signal Timings 69

Table 27. AC Characteristics - XT Bus Memory Signal Timings 71

Table 28. AC Characteristics - PCMCIA Memory Interface

Signal Timings . . . . . . . . . . . . . . . . . . . . . 73

Table 29. AC Characteristics - Graphics Controller

Signal Timings . . . . . . . . . . . . . . . . . . . . . 75

Table 30. AC Characteristics - RESET Signal Timing . . . . . . 78

■ Contents F8680A PC/CHIP

viii P R E L I M I N A R Y -- Revision 2.0 -- 6/2/94 Chips and Technologies, Inc.

Introduction

The F8680A PC/CHIP microchip is designed for use in low-power and cost-sensitive

DOS applications such as small entry-level computers, electronic hand-held

computers, and embedded controller systems. The F8680A design integrates a

high-speed 8086-compatible microprocessor with an XT subsystem, SuperState R

management logic, a memory controller/manager, a PCMCIA 2.0 interface, a

graphics controller, and a UART.

Pin Description

The F8680A single-chip PC is packaged in a 160-pin plastic flat pack package.

Figure 2 shows the top view of the chip layout.

Figure 2. F8680A Pinout, Top View

160-Pin Plastic Flat Pack

F8680A PC/CHIP Introduction ■

Chips and Technologies, Inc. P R E L I M I N A R Y -- Revision 2.0 -- 6/2/94 1

Table 1 lists the chip signal assignment by pin number. Those pins whose functions

are programmable through the configuration registers have the additional signal

possibilities listed for ‘‘1 PCMCIA’’ and ‘‘2 PCMCIA’’ card configurations.

Power-up default is always ‘‘No PCMCIA’’.

Table 1. F8680A Pin Allocation

Pin No. Signal

No PCMCIA Type Description Signal

1 PCMCIA Signal

2 PCMCIA

VCCPAD

IOCHCK*

IRQ2

DRQ2

GND

IOCHRDY

AEN

MEMW*

ADR19

MEMR*

Power

I/O Channel Check

Interrupt Request

DMA Request

Ground

I/O Channel Ready

Address Enable

Memory Write

Address Bus

Memory Read

----

IOCS16*

IOIS16*(A)

----

WAIT*

AEN & REG*

----

IOCS16*

MCRDY(B)

----

WAIT*

AEN & REG*

----

ADR18

IOW*

GND

ADR17

IOR*

ADR16

DACK3*

ADR15

VCC

DRQ3

Address Bus

I/O Write

Ground

Address Bus

I/O Read

Address Bus

DMA Acknowledge

Address Bus

Core Power

DMA Request

----

WAIT*(A)

----

RESET(B)

----

MCBAT2(B)

ADR14

DACK1*

ADR13

DRQ1

ADR12

DACK0*

ADR11

CLK

ADR10

GND

Address Bus

DMA Acknowledge

Address Bus

DMA Request

Address Bus

DMA Acknowledge

Address Bus

XT bus clock

Address Bus

Ground

----

ENA*(A)

----

ENA*(B)

----

MCBAT1(B)

----

ENA*(A)

----

IRQ7

ADR9

IRQ6

ADR8

IRQ5

ADR7

IRQ4

ADR6

IRQ3

ADR5

Interrupt Request

Address Bus

Interrupt Request

Address Bus

Interrupt Request

Address Bus

Interrupt Request

Address Bus

Interrupt Request

Address Bus

----

■ Pin Description F8680A PC/CHIP

2P R E L I M I N A R Y -- Revision 2.0 -- 6/2/94 Chips and Technologies, Inc.

Pin No. Signal

No PCMCIA Type Description Signal

1 PCMCIA Signal

2 PCMCIA

VCCPAD

DACK2*

ADR4

ADR3

ALE

ADR2

ROMCS*

GND

ADR1

Power

DMA Acknowledge

Address Bus

Terminal Count

Address Bus

Address Latch Enable

Address Bus

ROM Chip Select

Ground

Address Bus

----

CLK14

ADR0

ADR25

ADR24

ADR23

ADR22

ADR21

ADR20

VCCPAD

RD0

I/O

14MHz timer channels clock

Address Bus

Power

Data Bus

----

RD1

RD2

RD3

RD4

GND

RD5

RD6

RD7

CS10*

OE0*

I/O

Data Bus

Ground

Data Bus

High byte/low byte select

Output Enable

----

WE0*

GND

CS20*

CS21*

CS22*

REFRESH*

RD8

RD9

RD10

RD11

I/O

Write Enable

Ground

Bank select

Refresh

Data Bus

----

RD12

VCCPAD

RD13

RD14

RD15

CS11*

OE1*

WE1*

GND

MCCE2*

I/O

Data Bus

Power

Data Bus

High byte/low byte select

Output Enable

Write Enable

Ground

Mem. Card Chip Slct. High

----

WE1* & MDIR

----

MCCE2*(A)

----

WE1* & MDIR

----

MCCE2*(A/B)

F8680A PC/CHIP Pin Description ■

Chips and Technologies, Inc. P R E L I M I N A R Y -- Revision 2.0 -- 6/2/94 3

Pin No. Signal

No PCMCIA Type Description Signal

1 PCMCIA Signal

2 PCMCIA

100

MCCE1*

MCRDY

MCCD1*

MCCD2*

MCBAT1

MCBAT2

CARDB

DOT0/B

DOT1/G

GND

Mem. Card Chip Slct. Low

Memory Card Ready

Memory Card Detect

Memory Card Battery

Card B pin

Display data output

Ground

MCCE1*(A)

MCRDY(A)

MCCD1*(A)

MCCD2*(A)

MCBAT1(A)

MCBAT2(A)

RESET(A)

----

MCCE1*(A/B)

MCRDY(A)

MCCD1*(A)

MCCD2*(A)

MCBAT1(A)

MCBAT2(A)

RESET(A)

----

101

102

103

104

105

106

107

108

109

110

DOT2/R

DOT3/I

HS/LP

VS/FLM

DOTCLOCK

RTS*

CTS*

RI*

Display data output

Hor. Sync/Latch Pulse

Ver. Sync/First Line Marker

Dot Clock

Receive Data

Transmit Data

Ready To Send

Clear To Send

Ring Indicator

----

111

112

113

114

115

116

117

118

119

120

DSR*

CD*

DTR*

UARTCLK

VCC

FLOAT

RESET

GND

CPUCLK

CLK32K

Data Set Ready

Carrier Detect

Data Terminal Ready

UART clock

Core Power

Float all pins

Chip Reset

Ground

Processor clock

32kHz SuperState R clock

----

121

122

123

124

125

126

127

128

129

130

VCCPAD

GRD3

GRD2

GRD4

GND

GRD1

GRD5

GRD0

GRD6

GRA0

Power

Graphics Data

Ground

Graphics Data

Graphics Address

----

131

132

133

134

135

136

137

138

139

140

GRD7

GRA1

GRACS*

GRA2

GRA10

GRA3

GND

GRAOE*

GRA4

GRA11

Graphics Data

Graphics Address

Graphics Chip Select

Graphics Address

Ground

Graphics Output Enable

Graphics Address

----

■ Pin Description F8680A PC/CHIP

4P R E L I M I N A R Y -- Revision 2.0 -- 6/2/94 Chips and Technologies, Inc.

Pin No. Signal

No PCMCIA Type Description Signal

1 PCMCIA Signal

2 PCMCIA

141

142

143

144

145

146

147

148

149

150

GRA5

GRA9

GRA6

GRA8

VCCPAD

GRA7

GRA13

GRA12

GRAWE*

GRA14

Graphics Address

Power

Graphics Address

Graphics Write Enable

Graphics Address

----

151

152

153

154

155

156

157

158

159

160

PS1

PS2

PS3

PS4

PWRUP

OSCPW

GND

SPKR

KBDATA*

KBCLK*

I/O

Programmable Pin

Power Up

Power to Oscillator

Ground

Speaker data

Keyboard Data

Keyboard Clock

----

Alt. RESET(B)

----

MCCD1*(B)

MCCD2*(B)

F8680A PC/CHIP Pin Description ■

Chips and Technologies, Inc. P R E L I M I N A R Y -- Revision 2.0 -- 6/2/94 5

Signal Description

The signal groups of the F8680A single-chip PC are summarized in Table 2, along

with the state of each signal during suspend mode. In certain cases this state is

selectable if programmed where indicated in the CREG/bit column. A signal

description follows the table. The term ‘inactive’ as used here indicates that a signal

is driven to the logic level opposite of its active state.

Table 2. Signal Names

Function Symbol Type Description State During

Suspend Mode CREG

/bit Notes

Address and Data ADR25:0

RD15:0 O

I/O Address Bus

Data Bus Low or tri-state

Low 1E/3

XT Bus Control AEN

ALE

DRQ1-3

DACK0-3*

IOCHCK*

IOCHRDY

IOR*

IOW*

IRQ2-7

MEMR*

MEMW*

Address Enable

Address Latch Enable

DMA Request

DMA Acknowledge

I/O Channel Check

I/O Channel Ready

I/O Read

I/O Write

Interrupt Request

Memory Read

Memory Write

Terminal Count

Inactive or tri-state

Input (use 10k pullup)

Tri-state (use 10k pulldn)

Input

Inactive or tri-state

Input (use 10k pullup)

Inactive or tri-state

1E/0

04/0

Clocks CLK

CLK14

CLK32K

CPUCLK

UARTCLK

XT bus clock

Timer channels clock

SuperState R time-of-day clock

Processor clock

UART clock

Inactive or tri-state

Input (drive low)

Input (always active)

Input (drive low)

04/0

Memory Interface CS10-11*

CS20-22*

OE0-1*

WE0-1*

ROMCS*

High byte/low byte select

Bank select

Output Enable

Write Enable

ROM Chip Select

Inactive or tri-state

Tri-state

1E/3

Graphics Controller DOT3:0

DOTCLOCK

GRA14:0

GRACS*

GRAOE*

GRAWE*

GRD7:0

HS/LP

VS/FLM

Display data output

Dot Clock

Graphics Address

Graphics Chip Select

Graphics Output Enable

Graphics Write Enable

Graphics Data

Hor. Sync/Latch Pulse

Ver. Sync/First Line Marker

Low or tri-state

Stopped or tri-state

Low or tri-state

Inactive or tri-state

Low or tri-state

Stopped or tri-state

0E/0

3,4

3,5

Keyboard Interface KBCLK*

KBDATA* I/O

I/O Keyboard Clock

Keyboard Data Input

Input

■ Signal Description F8680A PC/CHIP

6P R E L I M I N A R Y -- Revision 2.0 -- 6/2/94 Chips and Technologies, Inc.

Function Symbol Type Description State During

Suspend Mode CREG

/bit Notes

PCMCIA 1.0

Memory Card

Interface

MCBAT1-2

MCCD1-2*

MCCE2*

MCCE1*

MCRDY

REFRESH*

Memory Card Battery

Memory Card Detect

Memory Card Chip Select High

Memory Card Chip Select Low

Memory Card Ready

Card Refresh

Input

Inactive or tri-state

Input

Inactive or tri-state

1E/1,2

1E/3

PCMCIA 2.0

Card Interface ENA*(A/B))

IOIS16*

MCBAT1-2(A/B)

MCCD1-2*(A/B)

MCCE1-2*

MCRDY (A/B)

MDIR

REFRESH*

REG*

RESET(A)

RESET(B)

WAIT*(A)

Card Buffer Enables

I/O Is 16-bit

Memory Card Battery

Memory Card Detect

Memory Card Chip Selects

Memory Card Ready

Card Buffer Direction

Card Refresh

Attribute Space Selection

Memory Card A Reset

Memory Card B Reset

Wait (cycle extender)

Inactive or tri-state

Input

Low, high, or tri-state

Input

Driven low

Should be tri-stated

Input

1E/7:6

1E/1,2

1E/7

90/6

40/5:4

Programmable Pins CARDB

PS1-4 O

I/O Card B pin

Programmable Pins Stays as last set

Stays as last set 6

Power Control OSCPW

PWRUP O

IPower to Oscillator

Power Up Low

Input

UART CD*

CTS*

DSR*

DTR*

RI*

RTS*

Carrier Detect

Clear To Send

Data Set Ready

Data Terminal Ready

Ring Indicator

Ready To Send

Receive Data

Transmit Data

Input

Active or tri-state

Input

Active or tri-state

Input

Active or tri-state

0F/0

1,4

Miscellaneous SPKR

RESET

FLOAT*

VCC

VCCPAD

GND

Speaker data

Chip Reset

Float all pins

Power to core of chip

Power to pad ring of chip

Ground

Tri-state

Input

1 Should be left in inactive state; set as tri-state only if connected to powered-down device

2 Tri-state only if memory is powered off during suspend mode

3 Should always be tri-state during suspend

4 State depends on programming of signal polarity

5 If stopped, state depends on phase in which clock was stopped

6 Do not tri-state during suspend mode without external pull-up or pull-down resistors

7 Bits 7:6=11, ENA* tri-stated during suspend mode; bits 7:6=10, ENA* always driven; bits 7:6=0x, ENA* always tri-stated.

8 The polarity of the MCCE1-2 lines is programmable through CREG 13h bits MCE1-2P.

9 CREG 1E bit 7=1: these lines are driven low; otherwise: MDIR and REFRESH* are controlled by CREG 1E bit 3, REG* by

CREG 04 bit 0 and CREG 1E bit 0.

Table 2. Signal Names (continued)

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The following list describes all of the pin signals and is arranged in alphabetical

order by signal name. An asterisk (*) indicates that the signal is active when low.

The signal direction input (I), output (O), or bidirectional (I/O) is also noted.

ADR25:0 Address Bus (O) - provides system addresses for linear addressing

on any byte boundary.

AEN Address Enable (O) - indicates that the currently active memory

and I/O cycles are part of a DMA cycle. It will not be driven if the

XT bus is disabled (CREG 04).

ALE Address Latch Enable (O) - indicates that a valid address is

available on the system address bus. It will not be driven if the XT

bus is disabled (CREG 04).

CARDB Card B (I/O) - programmed through CREG 90h. Usually used to

indicate that the current PCMCIA address refers to the second of

two memory card slots.

CLK Clock (O) - XT bus clock. It will not be driven if the XT bus is

disabled (CREG 04).

CD* Carrier Detect (I) - TTL-level input to UART.

CLK14 Clock 14 (I) - 14.31818MHz input clock used by the timer

channels. Should have a 50% +10% duty cycle.

CLK32K Clock 32K (I) - 32767Hz input for the clock used by the internal

clock logic. This clock must continue to run when the chip is in

standby mode or the time of day will be lost.

CPUCLK CPU Clock (I) - processor clock input that also sets memory

timings.

CS10-11* RAM Chip Select (O) - CS10* selects the low byte and CS11*

selects the high byte. Also function as CAS* for DRAM accesses.

CS20-22* RAM Bank Select (O) - CS20* selects bank 0, CS21* selects bank

1, and CS22* selects bank 2. The active low sense can be changed

to active high through CREG 0D.

CTS* Clear To Send (I) - TTL-level input to UART.

DACK0-3* DMA Acknowledge (O) - response to corresponding DRQ1-3

signal (DACK0* indicates that refresh is active). These will not

be driven if the XT bus is disabled (CREG 04).

DOT3:0 Display Data (O) - used as output to both CRTs and LCD panels.

DOTCLOCK Dot Clock (O) - output to LCD panels.

■ Signal Description F8680A PC/CHIP

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DRQ1-3 DMA Request (I) - receive DMA requests from external

peripherals. Ignored if the XT bus is disabled (CREG 04).

DSR* Data Set Ready (I) - TTL-level input to UART.

DTR* Data Terminal Ready (O) - TTL-level output from UART.

ENA*(A) Card A Buffer Enable (O) - enables the signal buffers to PCMCIA

card A for the duration of the PCMCIA memory or I/O cycle. The

ENA*(A) signal is available only when programmed to replace the

DACK0* signal through CREG 40h bit ENA/A.

ENA*(B) Card B Buffer Enable (O) - enables the signal buffers to PCMCIA

card B for the duration of the PCMCIA memory or I/O cycle. The

ENA*(B) signal is available only when programmed to replace the

DACK1* signal through CREG 41h bit ENA/B.

FLOAT* Float Outputs (I) - commands chip to tri-state all its outputs for

testing purposes.

GND Ground for the chip.

GRA14:0 Graphics Address (O) - address bus to graphics SRAM.

GRACS* Graphics Chip Select (O) - chip select to graphics SRAM.

GRAOE* Graphics Output Enable (O) - output enable to graphics SRAM.

GRAWE* Graphics Write Enable (O) - write enable to graphics SRAM.

GRD7:0 Graphics Data (O) - data bus to graphics SRAM.

HS/LP Horizontal Sync / Latch Pulse (O) - horizontal synchronization

signal to CRT when in CRT mode, latch pulse signal when in LCD

mode.

IOCHCK* I/O Channel Check (I) - input from XT bus that can trigger an

NMI. Ignored if the XT bus is disabled (CREG 04).

IOCHRDY I/O Channel Ready (I) - pulled inactive (low) by slow devices on

the XT bus to lengthen a memory or I/O cycle.

IOIS16* I/O Is 16-bit (I) - input from PCMCIA I/O interface indicating that

the currently addressed I/O port is 16-bits wide. The IOIS16*

signal input is available only when programmed to replace

IOCHCK* for a two-card system, or IRQ2 for a one-card system,

through CREG 40h bits MRDB1:0, or CREG 41h bit IO16. The

IOIS16* signals from each card must be ORed together along with

any IOCS16* signal from the XT bus and presented to a single

input on the F8680A chip.

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IOR* I/O Read (O) - indicates that the current cycle is an I/O read cycle.

It will not be driven if the XT bus is disabled (CREG 04). This

signal also provides the PCMCIA IORD* command.

IOW* I/O Write (O) - indicates that the current cycle is an I/O write

cycle. It will not be driven if the XT bus is disabled (CREG 04).

This signal also provides the PCMCIA IOWR* command.

IREQ* Interrupt Request from PCMCIA I/O Card (I) - receives interrupt

requests from the PCMCIA I/O card interface. The IREQ* signal

name does not appear in the F8680A pin list; the F8680A signal

name MCRDY must be assumed to refer to IREQ* instead of

RDY/BSY* whenever the I/O interface is selected.

IRQ2-7 Interrupt Request (I) - receive interrupt requests from external

peripherals. Ignored if the XT bus is disabled (CREG 04).

KBCLK* Keyboard Clock (I/O) - receives clock pulses from the keyboard

when the keyboard sends data. It can be pulled low (Control Port

B) to inhibit keyboard transmission.

KBDATA* Keyboard Data (I/O) - receives serial data from the keyboard.

MCBAT1-2

(A/B) Memory Card Battery (I) - indicate the status of the battery on

PCMCIA memory cards (PCMCIA name BVD1-2), act as status

change (STSCHG*) and speaker input (SPKR*) signals on

PCMCIA I/O cards. Can be read at SDATA 0A. MCBAT1-2(B)

are available only when programmed to replace DRQ1 and DRQ3,

respectively, through CREG 40h bits BDB1:0.

MCCD1-2*

(A/B) Memory Card Detect (I) - both pulled low by the PCMCIA

memory card to indicate that the card is properly inserted.

PCMCIA name is CD1-2. MCCD1-2*(B) are available only when

programmed to replace the KBDATA* and KBCLK* signals,

respectively, through CREG 41h bit CDB. Alternatively, CD1-2

from card A can be ANDed and input on the MCCD1*(A) input to

the chip, and CD1-2 from card B on the MCCD2*(A) input, if the

keyboard signal inputs are needed.

MCCE1* Memory Card Select Low (O) - enables the low (even) bytes for

I/O on the data bus. PCMCIA name is CE1. If two cards are used,

MCCE1* must be gated only to the card being accessed through

the ENA*(A/B) signals.

MCCE2* Memory Card Select High (O) - enables the high (odd) bytes for

I/O on the data bus. PCMCIA name is CE2. If two cards are used,

MCCE2* must be gated only to the card being accessed through

the ENA*(A/B) signals.

■ Signal Description F8680A PC/CHIP

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MCRDY

(A/B) Memory Card Ready (I) - indicates whether the memory card

circuits are busy. PCMCIA name is RDY/BSY*. MCRDY(B) is

available only if programmed to replace IRQ2 through CREG 40h

bits MRDB1:0.

MDIR Memory Card Buffers Direction (O) - controls the direction of the

transceivers used to buffer the PCMCIA card to the system data

bus. MDIR is generated on the WE1* line only during PCMCIA

cycles; no programming is needed to enable this signal.

MEMR* Memory Read (O) - indicates that the current XT bus cycle is a

memory read. It will not be driven if the XT bus is disabled

(CREG 04).

MEMW* Memory Write (O) - indicates that the current XT bus cycle is a

memory write. It will not be driven if the XT bus is disabled

(CREG 04).

OE0-1* Output Enables (O) - indicate to the low (OE0*) and high (OE1*)

bytes of the currently selected RAM bank whether they should

enable data from memory onto the RD bus.

PS1-4 Programmable Pins (I/O) - can be used for a wide variety of

functions according to their programming through CREGs 80-8F.

OSCPW Power Oscillator (O) - provides sequenced power to the CPU

oscillators.

PWRUP Power Up (I) - indicates that the power control state machine

should power-up/power-down the system according to the

programming in CREG 1C.

RD15:0 Data (I/O) - connected to system memory. RD7:0 also serve as the

XT data bus.

RESET Reset (I) - system reset input, synchronized with CPUCLK inside

the chip. It must remain high for at least three CLK32K clock

cycles.

REFRESH* Refresh (O) - indicates when pseudo-SRAM should perform a

refresh operation. Also provides the RFSH* signal to PCMCIA

cards that require it.

REG* Register/Memory Access (O) - indicates whether a PCMCIA card

access should be decoded as a common memory space cycle or an

attribute register space cycle. REG* is generated on the AEN line

only during PCMCIA cycles; no programming is needed to enable

this signal.

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RESET(A)

RESET(B) Card Reset (O) - signals with software-selectable low, high, or

tri-state output for the PCMCIA card reset function. RESET(A)

replaces the CARDB line and comes up tri-stated at system reset.

RESET(B) is available only if programmed to replace the

DACK3* signal though CREG 40h bits DK3/1:0, and comes up

high at system reset. Therefore, system designs in which card B is

powered at system reset must use a PS pin for the RESET(B)

function: the PS pins all come up tri-stated at system reset.

RI* Ring Indicator (I) - TTL-level input to UART.

ROMCS* ROM Chip Select (O) - activates the ROM for accesses to the

BIOS (when not shadowed in RAM). It will not be driven if the

XT bus is disabled (CREG 04).

RTS* Ready To Send (O) - TTL-level output from the UART.

Rx Receive Data (I) - TTL-level serial data input to the UART.

SPKR Speaker (O) - timer channel output to an external speaker. The

drive is a 4mA CMOS driver, and external conditioning may be

required to match the selected sounding device.

SPKRIN* Speaker Input (I) - speaker data input from a PCMCIA I/O card for

combination with system speaker data to be output on the SPKR

line. The SPKRIN* signal name does not appear in the F8680A

pin list; the signal name MCBAT2 must be assumed to refer to

SPKRIN* instead of BVD2 whenever the I/O interface is selected.

STSCHG* Status Change (I) - receives status change interrupt from the

PCMCIA I/O card. The STSCHG* signal name does not appear in

the F8680A pin list; the signal name MCBAT1 must be assumed

to refer to STSCHG* instead of BVD1 whenever the I/O interface

is selected.

TC Terminal Count (O) - indicates that the current DMA transfer is

the last byte programmed for transfer. TC is not generated when

DACK0* is active. It will not be driven if the XT bus is disabled

(CREG 04).

Tx Transmit Data (O) - TTL-level serial data output from the UART.

UARTCLK UART Clock (I) - 1.8432MHz input clock for the UART.

VCC Power to the core of the chip. This input can supply the core

processor at lower voltage (nominal 3.3V) than the remaining chip

circuits to save power, if desired. Otherwise it is tied to VCCPAD.

VCCPAD Power to all chip circuits except the core processor of the chip.

■ Signal Description F8680A PC/CHIP

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VS/FLM Vertical Sync / First Line Marker (O) - vertical synchronization

signal to CRT when in CRT mode, first line indicator signal when

in LCD mode.

WAIT* Wait (I) - delays completion of memory or I/O cycle until

peripheral is ready to respond. WAIT*(A) and WAIT*(B) can

always be gated in, along with any IOCHRDY signal from the XT

bus, on the IOCHRDY input to the F8680A chip; no programming

is necessary for this performance. However, WAIT*(A) alone can

replace the DRQ3 input to the chip if programmed through CREG

40h bits BDB1:0; this scheme eliminate the external gate needed

to combine the XT bus IOCHRDY signal with WAIT*(A).

WE0-1* Write Enables (O) - indicate to the low (WE0*) and high (WE1*)

bytes of the currently selected RAM bank whether they should

write the data on the RD bus to memory. WE0* acts as the write

enable command WE*/PGM* to the PCMCIA interface, and

WE1* as the MDIR signal to PCMCIA signal buffers, during

PCMCIA cycles.

WP* Write Protect (I) - indicates that a memory card is write-protected.

This signal is available only on the memory card interface; when

the I/O interface is selected, the card signal becomes IOIS16*.

The WP* signal name does not appear in the F8680A pin list; the

signal name IOIS16* must be assumed to refer to WP* instead of

IOIS16* whenever the memory interface is selected.

Chip TEST Mode

The F8680A chip enters a TEST mode whenever its FLOAT* input is driven low

and its RESET input is held high. In TEST mode, all pins except for DACK3*

become inputs to a single large AND gate; DACK3* becomes the output to this

AND gate. Putting the chip in TEST mode is useful for checking pin continuity at

the board level.

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■ Signal Description F8680A PC/CHIP

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Functional Description

The principal components of the F8680A architecture include:

•Fully static CMOS microprocessor

•SuperState R logic

•XT subsystem

•Memory controller/memory manager

•Graphics controller

•UART.

Refer to the system block diagram, Figure 1, for a graphic representation and to the

following paragraphs for a description of these systems.

Central Processor

The F8680A microprocessor, a Chips and Technologies, Inc. innovation, is fully

compatible with the 8086 processor but executes faster. It has the instruction set of

an 8086 processor but performs like an 80286. In addition the processor provides:

•Full 26-bit address bus

•24-bit internal registers

•New SuperState R operating mode and instruction set

•Microcode link to new Virtual I/O mechanism

•Microcode link to new Virtual Interrupts mechanism

•80186 instruction set execution capability.

SuperState R Logic

The SuperState R operating environment of the CPU is separate from the normal

operating environment of DOS and the BIOS. The SuperState R logic provides the

mechanism for entering SuperState R mode. The switch can occur when:

•The chip is reset (always).

•A hardware or software interrupt is set to be intercepted (Virtual Interrupts

feature).

•An IN or OUT instruction has executed and a device on the I/O bus must be

emulated or monitored (Virtual I/O feature).

•A specified period of time elapses.

•A DMA channel must be set up or auto-initialized.

•An external request made on one of the programmable pins must be serviced.

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•The PWRUP input changes state.

•An invalid opcode is encountered (always).

•A segment register is loaded.

The SuperState R logic involves the programmable pins, power control logic,

configuration space, performance control feature, Virtual I/O feature, and Virtual

Interrupts feature, as described in the following paragraphs.

Configuration Space

SuperState R mode provides the means of setting system configuration parameters,

using a new CPU instruction. Applications cannot modify this information with any

I/O or memory instruction.

Performance Control

The performance control feature allows the amount of time the CPU waits between

executing instructions to be set anywhere from no delay to 128 cycles. Since RAM

will be inactive during this time, performance control realizes a significant reduction

in power consumption while allowing the CPU to remain active.

Virtual I/O Feature

The Virtual I/O feature, which is implemented as part of the SuperState R logic,

allows I/O operations to every port to be monitored, redirected, emulated, or

suppressed as needed. The Virtual I/O feature can be used to emulate the operation

of a device that is not actually present.

Virtual Interrupts Feature

The Virtual Interrupts feature allows the SuperState R logic to trap any system

interrupt, whether caused by a hardware IRQ or by a software INT instruction.

SuperState R code can examine the interrupt before any TSR programs or interrupt

handlers see the interrupt. Once trapped, the SuperState R code can either substitute

interrupt handler itself and bypass the normal mechanism.

Power Control Subsystem

The F8680A chip provides many hardware and software features that allow design of

an effective yet unobtrusive power management mechanism. The most basic level of

management involves only two chip modes:

■ Functional Description F8680A PC/CHIP

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•The F8680A chip is in active mode when it is powered and its state machines for

timing are running.

•The F8680A chip is in suspend mode when a programmed power-down has

occurred. The core logic is powered but only the 32kHz clock is running. The

chip continues to keep time and maintain configuration parameters while in

suspend mode.

Power must be maintained to the F8680A chip at all times. When the terms "power

on," "power up," and "power down" are used in this document, they do not refer to

the actual application of power to and removal of power from the F8680A chip.

Rather, these terms refer to the transition between active mode and suspend mode.

Power Planes. The internal logic of the chip is supplied on two totally separate

power planes.

•The core power plane (pins VCC) supplies power to the core processor logic, the

32kHz time-of-day count clock logic, and the power-up comparator logic. Core

power must always be present. When the chip is in suspend mode, core power

consumption is extremely low (refer the the ‘‘DC Characteristics’’ section of this

document for the exact value).

•The pad power plane (pins VCCPAD) supplies power to the chip I/O interface.

All data and command lines are powered on the pad power plane. Pad power can

be removed when the chip is in suspend mode, if desired, but doing so does not

save power: when the chip is in suspend mode, pad power consumption drops to

zero. Pad power cannot be controlled by OSCPW because the OSCPW logic is

The core power plane can be supplied by 3.3V instead of 5V if desired to reduce

power consumption. However, the setup time for accessing system memory will

increase.

A system design should leave power connected to the F8680A chip VCC pins and to

the 32kHz clock generation logic at all times. This arrangement is sufficient to keep

all configuration information active in the F8680A chip and maintain the time-of-day

count.

The PWRUP input commands the power-up of the F8680A chip into active mode

and power-down into suspend mode. Power-up or power-down can be commanded

through either a pulse or a steady signal sense. Pad power (VCCPAD pins) must be

supplied for PWRUP to be sensed.

Logic Level Sensing. The F8680A chip interfaces equally well to logic operating at

TTL voltage levels or at CMOS voltage levels. The chip circuitry assumes a +5V

system (TTL) at power-up. CREG 32h must then be written with bit VL=0 to reset

the input buffer sensing to 3.3V levels (CMOS). When the system is powered up at

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3.3V but before it is programmed to this level, instruction fetches from ROM will

still occur reliably; only the upper limit of VIL is affected. However, it is

recommended that CREG 32h be reprogrammed immediately on power-up.

Note that when designing a system with CMOS logic to operate at 3.3V, any clock

oscillator ‘‘cans’’ to be designed in must be CMOS also.

Power-On Clock Comparator. Power-up can be commanded through the clock

comparator register of the F8680A chip. When in suspend mode, power will be

restored when the time in the power control comparator matches the time-of-day

count value. Operation will resume regardless of the PWRUP input signal level.

CREGs 18h through 1B comprise the 32-bit comparator register. If the F8680A chip

is already active when the time-of-day reaches the comparator value, the comparator

will have no effect. Refer to the F8680A PC/CHIP Programmer’s Reference

Manual for details of this comparator.

Power Control State Machine. The power control state machine can be instructed

to remove power from the oscillators through the POFF bit at CREG 1C. When

POFF is set to 1, the power control state machine will begin to sequence the F8680A

chip into suspend mode. Refer to the F8680A PC/CHIP Programmer’s Reference

Manual for programming details. The power control sequencing operates as follows.

•Upon receiving a power-up request (initiated by either the PWRUP input or the

power control comparator), the power control state machine sets the OSCPW

output active within 0.5s. It then enables the various timing state machines in the

F8680A chip 0.5s after setting OSCPW active.

•Upon receiving a software-commanded power-down request (the only kind

possible), the power control state machine disables the various timing state

machines within 0.5s. It then sets the OSCPW output inactive 0.5s after disabling

the timing state machines.

Therefore, power-up and power-down sequences always require at least 0.5s, but

always less than 1.0s, to execute.

In designs where the oscillator stabilization time is of less importance than the need

for a rapid resume sequence, the QR bit is provided in CREG 1C. When QR=1, the

power control state machine restarts the timing state machines within 0.1ms after

setting OSCPW active.

Connections to the PWRUP Input. The power-up pin PWRUP indicates when the

F8680A chip should exit suspend mode and begin normal operation. Once the

F8680A chip is operational, the PWRUP signal can be used to initiate a power-down

into suspend mode.

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Note: PWRUP by itself cannot cause a power-down; it can only request a power-down.

Software must command a power-down. However, PWRUP can be programmed

to cause a switch to SuperState R mode, which in turn can power down the

F8680A chip.

Two choices are available when incorporating the power switch into a system

design: a toggle switch or a momentary switch. The SuperState R configuration

PWRUP will cause a switch to SuperState R mode. The programming of this

If an SPDT toggle switch is connected, the PWRUP input is pulled to logic ground

to turn the system off, and is pulled up to VCC to activate the F8680A chip.

Software that recognizes a low signal at PWRUP as a power-down request must be

provided.

If a momentary switch is connected, it pulls PWRUP to VCC to activate the F8680A

chip. A pull-down resistor allows PWRUP to go back to logic ground as soon as the

momentary switch is released. Software that recognizes a high pulse at PWRUP as a

power-down request must be provided.

Programmable Pins

The chip provides five pins with programmable functions. These pins can be used

for such functions as programmable chip selects, clock outputs, and status

monitoring inputs.

The programmable pins can be used in a variety of ways. Software control makes

these pins extremely flexible and easy to incorporate in any design. The pins can

operate as either inputs or outputs and can source/sink 4mA minimum (refer to the

‘‘DC Characteristics’’ section for specific values) when used as outputs. Table 3 lists

the specific functions available through the programmable pins.

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Table 3. Programmable Pin Functions

Function Type Available on:

PS1 PS2 PS3 PS4 CARDB

CLK32

CLK1/16

CLK1/32

PCS

FR0

512Hz

256Hz

16384Hz

8192Hz

IFACTIVE

IFBRNCH

CLKCANRUN

FLAG9

ACDCLK

ICMPLT

CLKCANRUN

EXTSS

DOTCLK

where: CLK32 32kHz Clock - PS1-PS4 and CARDB can provide a 32kHz clock

pulse.

CLK1/16 1/16 32kHz Clock - PS1-PS4 and CARDB can provide a clock

with a positive pulse that occurs once every sixteen 32kHz clock

cycles. The programmable pin stays high only for the duration of

one phase (1/2 clock period) of the 32kHz clock.

CLK1/32 1/32 32kHz Clock - PS1-PS4 and CARDB can provide a clock

with a positive pulse that occurs once every thirty-two 32kHz

clock cycles. The programmable pin stays high only for the

duration of one phase (1/2 clock period) of the 32kHz clock.

PCS Programmable Chip Select - PS1-PS4 can decode I/O reads and/or

writes at any I/O address or range of addresses.

FR0 Frame Rate 0 - PS1-PS2 can provide the vertical interval signal

divided by 2.

256Hz

512Hz

8192Hz

16384Hz

These frequencies can be output on PS2, PS1, PS4, and PS3

respectively.

IFACTIVE Instruction Fetch Active - PS2-PS4 can indicate whether the

current memory request is for instruction data.

■ Functional Description F8680A PC/CHIP

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IFBRNCH Instruction Fetch on Branch - PS2 can indicate whether the current

memory request is for the first instruction after a program branch

(jump, call, etc.)

ICMPLT Instruction Complete - PS3 can output a pulse at the end of each

instruction executed. This signal can be counted to indicate true

MIPS. PS3 stays high only for the duration of one phase (1/2

clock period) of the CPU clock.

FLAG9 Flag bit 9 - PS3-PS4 can indicate whether maskable interrupts are

enabled.

ACDCLK AC Drive Clock - PS2-PS4 can output a square wave with a 50

percent duty cycle and a programmable period for use with LCD

panels.

CLKCANRUN Clock Can Run - PS4 can indicate whether the power control state

machine has completed the power-up sequence and instruction

execution is allowed.

EXTSS External SuperState R Switch - PS1-PS4 can be used as inputs to

trigger a switch to SuperState R mode.

DOTCLK Dot Clock - PS4 can be used to input a non-standard dot clock

frequency for the graphics controller.

Programming Simultaneous Input and Output. If a pin is programmed to input

an external SuperState R switch request, it can be simultaneously used for output.

For example, selecting a 256Hz output on PS2 and programming PS2 for SuperState

R input at the same time would result in a periodic switch to SuperState R mode (like

the timer tics provide). However, PS2 should not be driven by external circuitry in

this configuration.

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XT Subsystem

The F8680A chip logic supports the functions of the following components found in

the standard XT subsystem:

•Interrupt controller

•Direct memory access (DMA) controller

•Timer

•Keyboard interface

•External XT bus.

For the most part, the XT subsystem is implemented in hardware.

For performance of the functions available in an XT environment, the interrupt

controller is functionally equivalent to the 8259A component, and the timer to the

8254 component.

The F8680A microchip implements the functions normally associated with the 8237

DMA Controller through a combination of hardware, CPU microcode, and software.

The keyboard interface and associated circuitry is compatible with that of the XT,

including read access to the XT configuration switch settings. These switch settings

are programmed through a configuration register.

Table 4 shows the system I/O address space occupied by the F8680A chip.

■ Functional Description F8680A PC/CHIP

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Table 4. XT-Compatible I/O Port Assignment

Range IOR* Cycle

Internal/External IOW* Cycle

Internal/External Usage

000-01F Internal Internal DMA Controller

020-03F Internal Internal Interrupt Controller

040-05F Internal Internal Timer

060, 064, 068, 06C,

070, 074, 078, 07C Internal External Keyboard Data Port

061, 065, 069, 06D,

071, 075, 079, 07D Internal Internal Control Port B

062, 066, 06A, 06E,

072, 076, 07A, 07E Internal External Status Port C

063, 067, 06B, 06F,

073, 077, 07B, 07F External External Not used by the F8680A chip

080-09F External External DMA Page Registers

0A0-2F7 External External Not used by the F8680A chip

2F8-2FF Internal + External Internal + External If UART enabled and set as COM2

External External If UART disabled or set as COM1

300-3CF External External Not used by the F8680A chip

3D0-3DF External External If on-board CGA disabled

Internal Internal On-board CGA enabled

3E0-3F7 External External Not used by the F8680A chip

3F8-3FF Internal + External Internal + External If UART enabled and set as COM1

External External If UART disabled or set as COM2

UART

A Universal Asynchronous Receiver/Transmitter, compatible with the National®

NS16C450 asynchronous communications element, is provided for serial

communications. The device can be assigned to respond as either COM1 or COM2,

or it can be disabled.

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Memory Subsystem

The F8680A single-chip PC provides an extremely versatile memory management

and control system, as described in the following paragraphs.

Memory Management

The memory manager maps CPU addresses to physical RAM in 32kB or 64kB

segments. Once mapped, segments can be bank-switched for implementation of

EMS memory and a PCMCIA memory card interface. The maximum local system

memory that is directly managed is 4MB. A total of 64MB memory can be

addressed through the 26-bit address bus ADR25:0.

The system memory usage is shown in Table 5.

Table 5. System Memory Usage

Memory Range Size

(kB) Usage

0F0000-0FFFFF 64 BIOS ROM (can be shadowed)

0E0000-0EFFFF 64 Often used for PCMCIA memory card access or ROM applications

0DC000-0DFFFF

0D8000-0DBFFF

0D4000-0D7FFF

0D0000-0D3FFF

Often used for EMS memory page frames

0CF000-0CFFFF

0CE000-0CEFFF

0CD000-0CDFFF

0CC000-0CCFFF

0C0000-0CFFFF

Often used for PCMCIA memory windows

(if used, 64kB segment starting at 0C0000 becomes only 48kB)

Often used for ROM applications or PCMCIA memory card access

0B8000-0BFFFF 32 CGA graphics memory

0A0000-0B7FFF 96 Often used for alternate video controller

000000-09FFFF 640 MS-DOS and applications

■ Functional Description F8680A PC/CHIP

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Memory Controller

The memory controller of the F8680A chip supports most of the commonly used

memory types. The controller provides chip-select decoding for up to three banks of

memory. External address decoding must be provided for any additional banks.

Each bank can be any one of the following types:

•256k x 1, 256k x 4, 512k x 8, 1M x 1, 1M x 4, and 4M x 1 DRAM

•Any type of SRAM or PSRAM (such as 32k x 8, 128k x 8, and 512k x 8)

•PCMCIA memory card

•ROM

•Memory on the XT bus.

The three types can be mixed in any way. The best choices are DRAM,

SRAM/PSRAM, and PCMCIA memory, all of which provide good performance

when configured for word (16-bit) access. DRAM page mode is supported with both

byte and word requests. The controller provides all timing and control signals to

allow direct support for up to three banks of 8-bit or 16-bit memory. Both 8-bit and

16-bit banks can be used in the same system.

Connecting the memory is generally very routine and predictable. The only

decisions to make on the hardware side are the memory type and capacity. All

mapping and configuration choices are made through software. The memory

configuration worksheet provided in the "Memory" chapter of the F8680A PC/CHIP

Programmer’s Reference Manual simplifies the programming calculations needed

for mapping memory into the system address space.

Memory Operational Theory

This section provides only a brief summary of the concepts involved in system

memory mapping. For a more detailed explanation, refer to the F8680A PC/CHIP

Programmer’s Reference Manual.

The memory manager provides independent bank switching and memory mapping

mechanisms to deal with the translation from logical CPU addresses to physical

addresses in RAM. The bank switching mechanism takes linear CPU addresses that

fall in the B0000 to FFFFF range and moves them so that the effective logical

address can fall anywhere in the 64MB address space of the F8680A chip. The

memory mapping mechanism takes the logical address, after any possible shifting by

the bank switching mechanism, and maps it on a block-by-block basis to available

space in physical RAM. Either 32kB or 64kB blocks can be selected.

Bank Switching Logic. Figure 3 illustrates the bank switching logic used in the

system. The logic first decodes address bits A19:16 from the CPU. If the address is

in the B0000 to FFFFF range, the decoder signals the multiplexer to use the contents

of one of the nine Bank Switch Registers instead of the upper bits of the address

from the CPU.

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The decoder selects the Bank Switch Register whose contents will substitute the

upper address bits from the CPU according to the nine subranges listed in Table 6.

Address bits A15:14 may or may not be substituted by the Bank Switch Register

address bits, depending on the size of the subrange decoded.

Table 6. Bank Switch Register Ranges

Bank Switch Register Corresponding Subrange

B0000-B7FFF

B8000-BFFFF

C0000-CFFFF

D0000-D3FFF

D4000-D7FFF

D8000-DBFFF

DC000-DFFFF

E0000-EFFFF

F0000-FFFFF

The multiplexer passes on the substituted address bits only when enabled by the

EMB bit in CREG 0C. The resulting 26-bit address A25:0 is passed on to the

memory mapping logic. Note that bank switching is disabled on power-up.

Memory Window Logic. The chip also provides four Memory Window Registers

that may or may not be enabled. The memory windowing logic is not shown as part

of Figure 3, but it operates in a manner similar to the Bank Switch Registers.

However, unlike the Bank Switch Registers, the output of the memory windowing

logic does not pass to the Memory Mapping Registers. Each Memory Window

performed for accesses in that window.

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Figure 3. Bank Switching Logic

Note: A23:0 from the CPU address logic comes after Gate A20.

Memory Mapping Logic. Figure 4 illustrates the logic used to map the logical

addresses from the bank switch mechanism to locations in physical RAM. The

upper address bits A25:15 are decoded to select one of 34 address ranges. The

USE64 bit in CREG 0D selects the decoding method. If USE64=0, each of the first

thirty-two 32kB blocks of logical addresses corresponds to a separate mapping

If USE64=1, each of the first thirty-two 64kB blocks of logical addresses

corresponds to a separate mapping register, with the next two 1MB blocks each

corresponding to a mapping register.

Unlike the Bank Switch Registers, the Memory Mapping Registers do not contain

replacements for the logical address bits from the CPU. The mapping registers

simply select the physical bank of RAM to which the logical address should be

directed. However, the registers do provide mapping bits. These bits serve to shift

the address up or down in multiples of 128kB within the physical RAM bank,

allowing "lost" RAM (such as RAM whose address would overlap the display

SRAM address range) to be utilized elsewhere.

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Each Memory Mapping Register selects one of four Bank Select Registers, which in

turn activates the control signals for the selected bank of RAM. If the CPU

generates an address outside the range of the 34 Memory Mapping Registers, the

logic automatically selects one of four out-of-range Bank Select Registers reserved

for this purpose. No mapping bits are provided for out-of-range accesses.

Figure 4. Memory Mapping Logic

8 Bank

Select

Registers

■ Functional Description F8680A PC/CHIP

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How to Approach Memory Design

The memory controller handles three banks of RAM, providing the bank select

signals CS20, CS21, and CS22 to activate banks 0, 1, and 2, respectively (see Figure

4). Additional banks can be used, but the F8680A chip provides no additional bank

select signals and external decoding logic would be needed.

The memory controller is programmed through CREG locations for each bank

according to the following parameters: memory cycle type (DRAM, SRAM, XT bus,

or PCMCIA); bank width (one or two bytes); address multiplexing (for DRAM

only); and required ROMCS line status (active/inactive) for that bank.

DRAM, SRAM, or PSRAM can be used, and all three can be mixed. Different

RAM types cannot be mixed within the same bank, but different size devices of the

same type can be. A PC/CHIP Application Note is available that describes an

interesting application where RAMs of different sizes and widths are used to

optimize performance in a certain addressing range.

Refer to the following sections for basic examples of the connections required to

interface each type of memory to a bank. Then refer to the F8680A PC/CHIP

Programmer’s Reference Manual to determine the most effective way to utilize the

RAM for a given hardware design.

Note: When the graphics subsystem is enabled, all accesses at segment 0B800 are

considered graphics cycles and are automatically forwarded to the graphics

controller.

DRAM

DRAM provides efficient, high-performance, low-cost memory space. There are

drawbacks, however. For example, DRAM consumes a lot of power when compared

to SRAM. Special features of the F8680A chip, such as page mode operation, slow

refresh, and performance control, help to lessen the impact of this power

consumption. However, a mix of DRAM, SRAM, and PCMCIA memory may yield

a more efficient design.

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Signals. Table 7 lists the pin assignments and signals provided for the DRAM

interface. Refer to the ‘‘Signal Description’’ section of this manual for signal

descriptions.

Table 7. Pin Assignments - DRAM Interface Signals

Address Bus Data Bus Control Bus

Pin Signal Pin Signal Pin Signal

ADR0

ADR1

ADR2

ADR3

ADR4

ADR5

ADR6

ADR7

ADR8

ADR9

ADR10

ADR11

RD0

RD1

RD2

RD3

RD4

RD5

RD6

RD7

RD8

RD9

RD10

RD11

RD12

RD13

RD14

RD15

CS10*

CS11*

CS20*

CS21*

CS22*

OE0*

OE1*

WE0*

WE1*

Memory Address Multiplexing. The MEM bits and the WID bit of the Bank Select

Registers select the type of address multiplexing that will be performed during

DRAM cycles. Refer to the F8680A PC/CHIP Programmer’s Reference Manual for

Bank Select Register programming details.

Connect one-byte-wide RAM to the address bus starting with bit 0, and

two-bytes-wide RAM starting with bit 1. The address bits are multiplexed according

to Table 8. Address bits above bit 11 are not changed during a DRAM cycle. These

bits can be decoded with external chip select decode logic if it is necessary to support

more than three banks of memory and no more CS2x lines are available.

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Table 8. Address Multiplexing

Period MEM Bits WID Bit ADR25:0 bit

11 10 9876543210

T1/RAS 00

256kx1 020 19 18 17 16 15 14 13 12 11 10 9

1Mx1 0x19 18 17 16 15 14 13 12 11 10 19

4Mx1 0x19 18 17 16 15 14 13 12 11 20 21

256kx2 1xx18 17 16 15 14 13 12 11 10 x

1Mx2 1x19 18 17 16 15 14 13 12 11 20 x

4Mx2 120 19 18 17 16 15 14 13 12 21 22 x

T2/CAS -------- -------- 11 10 9876543210

Refresh. The F8680A chip generates the periodic refresh necessary to keep DRAM

contents alive. The refresh timing is set by programming timer channel 1 just as it

would be for the XT. The banks to receive refresh are programmed through CREG

16h; this CREG also provides a setting for 512k x 8 DRAM refresh on the OE0-1*

lines. Refer to "Refresh" in Chapter 5 of the F8680A PC/CHIP Programmer’s

Reference Manual for details on refresh.

The memory controller provides a CAS before RAS type of refresh: the controller

activates the CS1x line (CAS) first, and follows this by activating the CS2x (RAS)

line. This method reduces the power required to perform refresh when compared to

a RAS-only refresh.

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Interface to All Common Types. Figures 5 through 7 illustrate the connections

necessary to interface each type of DRAM to the F8680A chip.

Figure 5 shows the connections to a bank of DRAM made up of 4-bit devices

(256k x 4 or 1M x 4 DRAM).

Figure 5. Interface to 4-bit DRAM

Notes:

1. Use limiting resistors in connections to DRAM; 33 ohm resistors are recommended.

2. The polarity of the CS2x lines is programmable.

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Figure 6 shows the connections to a bank of DRAM made up of 8-bit devices

(512k x 8 DRAM).

Figure 6. Interface to 8-bit DRAM

Notes:

1. Use limiting resistors in connections to DRAM; 33 ohm resistors are recommended.

2. The polarity of the CS2x lines is programmable.

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Figure 7 shows the connections to a bank of DRAM made up of 1-bit devices

(256k x 1, 1M x 1, or 4M x 1 DRAM).

Figure 7. Interface to 1-bit DRAM

Notes:

1. Use limiting resistors in connections to DRAM; 33 ohm resistors are recommended.

2. The polarity of the CS2x lines is programmable.

3. Connect one each of data bus lines RD15:0 to each 1-bit DRAM.

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SRAM/PSRAM

Table 9 lists the pin assignments and signals provided for the SRAM interface.

Refer to the ‘‘Signal Description ’’ section of this manual for signal descriptions.

Table 9. Pin Assignments - SRAM Interface Signals

Address Bus Data Bus Control Bus

Pin Signal Pin Signal Pin Signal

ADR0

ADR1

ADR2

ADR3

ADR4

ADR5

ADR6

ADR7

ADR8

ADR9

ADR10

ADR11

ADR12

ADR13

ADR14

ADR15

ADR16

ADR17

ADR18

RD0

RD1

RD2

RD3

RD4

RD5

RD6

RD7

RD8

RD9

RD10

RD11

RD12

RD13

RD14

RD15

CS20*

CS21*

CS22*

OE0*

OE1*

REFRESH*

WE0*

WE1*

Refresh for PSRAM. PSRAM provides its own internal refresh logic, allowing the

PSRAM to maintain its contents when the system stops sending REFRESH* pulses.

The memory controller provides a refresh signal REFRESH* that is compatible with

the internal refresh logic of the PSRAM. CREG 16h bit ERPSR enables PSRAM

refresh on the REFRESH* line.

CREG 0B can select the appropriate signal pulse to initiate the internal standby

refresh of the PSRAM. In this mode, just before the F8680A chip goes into suspend

mode it emits a final REFRESH* pulse of minimum 8µs duration to enable the

internal refresh logic of the PSRAM. The PSRAM contents cannot be accessed, but

they are maintained. As soon as the F8680A chip leaves suspend mode and begins

to send regular REFRESH* pulses, the PSRAM goes active and disables its internal

refresh logic.

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Interface to All Common Types. Figure 8 illustrates the connections necessary to

interface a word-wide bank of SRAM to the F8680A chip. The interface

accomodates 32k x 8, 128k x 8, and 512k x 8 devices with the same connections.

Only the number of address lines connected varies, as shown in Table 10. To

interface a byte-wide bank of SRAM, connect the system address lines ADR18:0

directly to the SRAM address lines A18:0.

Table 10. Address Bus Connections for Various SRAM Device Capacities

System Address SRAM Address

32k x 8 128k x 8 512k x 8

ADR15:1 A14:0 A14:0 A14:0

ADR17:16 n/c A16:15 A16:15

ADR19:18 n/c n/c A18:17

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Figure 8. Interface to SRAM

Notes:

1. No limiting resistors are needed in connections to SRAM.

2. The polarity of the CS2x lines is programmable.

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ROM

The memory controller supports ROM as a device on the XT bus. Either 8-bit or

16-bit accesses can be made to ROM according to the setting made in the Bank

Select Register that points to the ROM.

BIOS ROM. The most common use of ROM is to provide the system BIOS. After

reset the F8680A chip sets its ROMCS* line active and begins executing from bank

0 (BS0), which points to the XT bus by default. The BIOS ROM bank will normally

be 8-bits wide. The BIOS ROM contents are usually copied from ROM to system

RAM at boot time, a process known as shadowing ROM in RAM. Running the

BIOS from RAM is much faster because ROM must be accessed with slow XT bus

cycles that take at least two times as long as SRAM access.

Shadowing ROM in RAM is a decision made in software; it does not impact

hardware design. However, the SuperState R code portion of the BIOS must always

be RAM-resident. Refer to Chapter 5 of the F8680A PC/CHIP Programmer’s

Reference Manual for more information on shadowing the BIOS in RAM.

Applications in ROM. A system design might provide application programs in

ROM. Generally these programs will be copied as needed from ROM to RAM for

execution, then deleted from RAM when their execution is complete. Running

applications from 8-bit ROM is not recommended, as performance is poor.

If applications are to be run from ROM, the ROM devices can be arranged as

word-wide memory. If possible in the system design, the ROM should be accessed

with PCMCIA cycles which execute faster than XT bus cycles yet can be adjusted to

meet the timing requirements of the ROM device.

Signals. Table 11 lists the F8680A chip signals provided by the ROM/PROM

interface to 8-bit devices. Refer to the ‘‘Signal Description’’ section of this manual

for signal descriptions.

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Table 11. Pin Assignments - ROM/PROM Interface Signals

Address Bus Data Bus Control Bus

Pin Signal Pin Signal Pin Signal

ADR0

ADR1

ADR2

ADR3

ADR4

ADR5

ADR6

ADR7

ADR8

ADR9

ADR10

ADR11

ADR12

ADR13

ADR14

ADR15

ADR16

ADR17

ADR18

ADR19

RD0

RD1

RD2

RD3

RD4

RD5

RD6

RD7

ROMCS*

MEMW*

MEMR*

Interface to 8-bit ROM Banks. Figure 9 illustrates the connections necessary to

interface a byte-wide bank of ROM.

Figure 9. Interface to 8-bit ROM

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PCMCIA-Standard Interface

The PC Memory Card International Association (PCMCIA) Release 2.0 standard

defines mass-storage memory cards and I/O cards in terms of their physical,

electrical, and programming interfaces. All cards that adhere to these standards can

use the same physical and electrical interfaces. Separate software drivers are usually

required for each card type. A description of the full PCMCIA standard is provided

in the PC Card Standard document available from PCMCIA. Refer to this

document for more complete and useful information about the PCMCIA standard.

Release 2.0 defines both memory and I/O card interfaces. Memory cards include

RAM cards, ROM cards, flash-type EPROM cards, and silicon disks. I/O cards

include hard disk cards, modem cards, and network adapter cards. The interface

signals differ between the two card types. The F8680A chip provides the M/IO bit

in CREGs 42-43h to select the card interface mode for each card slot in the system;

this bit determines how certain signals that are common to the two interfaces behave.

Signals. The F8680A chip provides control and status lines that conform to

PCMCIA guidelines. The PCMCIA signals and the signal pins to which they are

buffered on the F8680A chip are listed in Table 12. Refer to the ‘‘Signal

Description’’ section of this manual for signal descriptions.

Table 12. PCMCIA Signal Name Equivalents

Interface Signal Description PCMCIA Name Card A Name F8680A Pin Card B Name F8680A Pin

Common to

Memory

and I/O

Interfaces

Address Bus

Data Bus

Card Enable (even bytes)

Card Enable (odd bytes)

Attribute Memory Select

Output Enable

Write Enable/Program

Card Detect

Card Buffer Select

Buffer Direction

A25:0

D15:0

CE1*

CE2*

REG*

OE*

WE*/PGM*

CD1-2

----

ADR25:0

RD15:0

MCCE1*(A)

MCCE2*(A)

REG*(A)

OE0*

WE0*

MCCD1,2(A)

ENA*(A)

MDIR

----

93, 94

ADR25:0

RD15:0

MCCE1*(B)

MCCE2*(B)

REG*(B)

OE0*

WE0*

MCCD1,2(B)

ENA*(B)

MDIR

----

159, 160

Memory Only

Interface Ready/Busy

Write Protect

Program Voltage

Refresh

Card Detect

Battery Voltage Detect

RDY/BSY*

Vpp

RFSH

CD1-2

BVD1-2

MCRDY(A)

IOIS16*(A)

Note 1

REFRESH

MCCD1,2(A)

MCBAT1,2(A)

3 or 2

93, 94

95, 96

MCRDY(B)

IOIS16*(B)

Note 1

REFRESH

MCCD1,2(B)

MCBAT1,2(B)

159, 160

24, 20

I/O

Interface I/O Read

I/O Write

I/O Is 16-bit

Interrupt Request

Speaker Input

Status Change

IORD*

IOWR*

IOIS16*

IREQ*

SPKRIN*

STSCHG*

IOR*

IOW*

IOIS16*(A)

MCRDY(A)

MCBAT2(A)

MCBAT1(A)

3 or 2

IOR*

IOW*

IOIS16*(B)

MCRDY(B)

MCBAT2(B)

MCBAT1(B)

1 Programming voltage is usually applied by activating a power control device under PS pin or configuration latch control.

■ Functional Description F8680A PC/CHIP

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Memory Card Medium Types. The PCMCIA standard provides for MaskROM,

OTPROM, EPROM, EEPROM, Flash-EPROM, and SRAM as supported memory

media. These are all defined in versions with 250ns, 200ns, and 150ns access times.

100ns support is also provided, but for SRAM only.

PCMCIA cards come in a variety of speeds and sizes. When running memory cards

in the system, the polarity and timing of signals must be configured according to the

card type in use. CREG 13h is used to make these PCMCIA control signal line

settings for card slot A, and CREG 47h for card slot B.

The PCMCIA software driver must initially assume that the slowest card is being

used and program the F8680A chip for the longest access time. The card attribute

after reading this information can the access time be shortened. If two card slots are

provided, the access speed of each card must be set independently.

Chip Support for PCMCIA. The F8680A chip manages a 64MB address space, of

which the upper 48MB is often used for memory card access. The Bank Switch

Registers and/or Memory Window Registers allow accesses in certain areas of low

memory to be redirected anywhere in the 64MB address space. Low memory can

also be used for memory card access. This method might be used to implement a

system with no on-board RAM. In this case, the user would have to insert a

PCMCIA card containing RAM before using the system. Regardless of where the

PCMCIA card is accessed, the Bank Select Registers are used to choose PCMCIA

cycles in that bank of memory. The Bank Select Registers also determine whether

access will be 8-bit or 16-bit in all memory ranges.

Many of the F8680A chip pins can be programmed to change their function to

accommodate the needs of the PCMCIA interface. When a pin is programmed for

use with the PCMCIA interface, its original function is no longer available. This

document presents two general schemes for implementation of the PCMCIA 2.0

interface: a one-card application and a two-card application. The following sections

describe each of these schemes. The pin programming provided illustrates the most

general application and the most commonly chosen configurations. However, the

programming flexibility of the chip allows many variations on these schemes.

Connecting a Single Card. Figure 10 illustrates the chip pin functions that change

when programmed to implement support for a single PCMCIA card slot. DREQ3,

DACK0*, and IRQ2 from the XT bus cannot be used in this system because their pin

functions on the F8680A chip are replaced by PCMCIA functions. To obtain this

chip configuration, CREG 40h is written as 11110101b and CREG 41h is written as

00x0x000b (where the ‘x’ positions indicate ‘set as needed’----refer to the F8680A

PC/CHIP Programmer’s Reference Manual for complete details).

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Figure 10. Chip Pinout Changes for One-Card Configuration

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Figure 11 illustrates the circuit necessary for isolating the card slot so that it can be

powered down when not in use.

Figure 11. Connections for Fully Buffered One-Slot System

F8680A MCCE1*

MCCE2*

ENA*(A) [DACK0*]

RD15:0

MDIR [WE1*]

IOIS16* [IRQ2]

WAIT*(A) [DRQ3]

MCRDY

MCBAT1(A)

MCBAT2(A)

MCCD1*(A)

MCCD2*(A)

OE0*

WE0*

IOR*

IOW*

REG* [AEN]

ADR25:0

CRDAON* [PS3]

RESET(A) [CARDB]

MCCE1* CARD A

MCCE2*

D15:0

WP*/IOIS16*

WAIT*

RDY/IREQ*

BVD1/STSCHG*

BVD2/SPKRIN*

CD1*

CD2*

OE*

WE*/PGM*

IORD*

IOWR*

REG*

A25:0

RESET

DIR

F8680A PC/CHIP Functional Description ■

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Connecting Two Cards. Figure 12 illustrates the chip as programmed to implement

support for two PCMCIA card slots. DREQ1, DACK1*, DREQ3, DACK3*,

DACK0*, IRQ2, and IOCHCK* from the XT bus, as well as KBDATA* and

KBCLK*, cannot be used in this system because their pin functions on the F8680A

chip are replaced by PCMCIA functions. To obtain this chip configuration, CREG

40h is written as 11111010b and CREG 41h is written as 11x0x101b (where the ‘x’

positions indicate ‘set as needed’----refer to the F8680A PC/CHIP Programmer’s

Reference Manual for complete details).

Figure 12. Chip Pinout for Two-Card Configuration

A variation on this scheme allows the KBDATA* and KBCLK* pins to be reclaimed

by gating the MCCD1-2*(B) signals with the MCCD1-2*(A) signals. This

adjustment is effected by writing bit 0 of CREG 41h as a ‘0’ instead of as a ‘1’.

■ Functional Description F8680A PC/CHIP

44 P R E L I M I N A R Y -- Revision 2.0 -- 6/2/94 Chips and Technologies, Inc.

Figure 13 illustrates the circuit necessary for isolating each card slot individually so

that they can be powered down when not in use. Buffers are tri-state when not

enabled.

Figure 13. Connections for Fully Buffered Two-Slot System

F8680A ENA*(A) [DACK0*]

MCCE1*

MCCE2*

RD15:0

MDIR [WE1*]

WAIT* [IOCHRDY]

IOIS16* [IOCHCK*]

MCRDY

MCBAT1(A)

MCBAT2(A)

MCCD1*(A)

MCCD2*(A)

OE0*

WE0*

IOR*

IOW*

REG* [AEN]

ADR25:0

CRDAON* [PS3]

RESET(A) [CARDB]

ENA*(B) [DACK1*]

MCRDY(B) [IRQ2]

MCBAT1(B) [DRQ1]

MCBAT2(B) [DRQ3]

MCCD1*(B) [KBDATA*]

MCCD2*(B) [KBCLK*]

CRDBON* [PS4]

RESET(B) [DACK3*]

EN CARD B

MCCE1*

MCCE2*

D15:0

WAIT*

WP*/IOIS16*

RDY/IREQ*

BVD1/STSCHG*

BVD2/SPKRIN*

CD1*

CD2*

OE*

WE*/PGM*

IORD*

IOWR*

REG*

A25:0

RESET

DIR

EN CARD A

MCCE1*

MCCE2*

D15:0

WAIT*

WP*/IOIS16*

RDY/IREQ*

BVD1/STSCHG*

BVD2/SPKRIN*

CD1*

CD2*

OE*

WE*/PGM*

IORD*

IOWR*

REG*

A25:0

RESET

DIR

F8680A PC/CHIP Functional Description ■

Chips and Technologies, Inc. P R E L I M I N A R Y -- Revision 2.0 -- 6/2/94 45

Figure 14 shows the circuitry necessary when the KBDATA* and KBCLK* lines are

needed for an external keyboard. In this case, the card detect signals from each card

are ORed together so that each card requires only one input to the F8680A chip.

Figure 14. Circuitry Needed for Sharing the MCCD1-2* Inputs

F8680A

MCCD1*(A)

MCCD2*(A)

CARD B

CD1*

CD2*

CARD A

CD1*

CD2*

■ Functional Description F8680A PC/CHIP

46 P R E L I M I N A R Y -- Revision 2.0 -- 6/2/94 Chips and Technologies, Inc.

CGA-Compatible Graphics Controller

The graphics controller supports both CRT and LCD panel displays with a fully

CGA-compatible register set. It supports 80 x 25 and 40 x 25 text modes, as well as

640 pixel 2-color and 320 pixel 4-color graphics modes, at 200 lines of resolution.

For LCD panels, the graphics controller provides a pixel panning feature to support

non standard panel sizes.

When driving a CRT or a color LCD panel, the CGA-compatible graphics controller

displays colors. For monochrome panels the processing of the attributes is identical,

but the resulting colors are translated to gray levels. Up to 16 levels of gray can be

translated.

The Visual Map feature overcomes a problem that arises when monochrome LCD

panels are used with text mode applications written for a color display. Many

controllers map colors to shades of gray, but colors that are close in intensity are

barely distinguishable on a monochrome display. When text mode foreground and

background colors are mapped to the same shade of gray, the text disappears.

The Visual Map feature programs each possible foreground and background color

combination into a table as a specific combination of shades of gray. Each

combination provides contrast that is closer to that of a color display than simple

mapping techniques can achieve. The Visual Map feature works with any

application that displays in text mode. No application-specific tables are required.

The F8680A display controller options allows interfacing directly to an LCD panel

or CRT. Alternatively, the internal display controller can be disabled and an external

high-resolution display subsystem connected instead.

F8680A PC/CHIP Functional Description ■

Chips and Technologies, Inc. P R E L I M I N A R Y -- Revision 2.0 -- 6/2/94 47

SRAM Interface

To use the internal display controller, a 32k x 8 SRAM rated for 120ns or better

access time is required. The connection is straightforward and is illustrated in Figure

15.

Figure 15. Connection of Display SRAM

where: GRA14:0 Graphics Address (O) - address bus to graphics SRAM.

GRACS* Graphics Chip Select (O) - chip select to graphics SRAM.

GRAOE* Graphics Output Enable (O) - output enable to graphics SRAM.

GRAWE* Graphics Write Enable (O) - write enable to graphics SRAM.

GRD7:0 Graphics Data (O) - data bus to graphics SRAM.

■ Functional Description F8680A PC/CHIP

48 P R E L I M I N A R Y -- Revision 2.0 -- 6/2/94 Chips and Technologies, Inc.

LCD Panel Interface

The display controller circuit of the F8680A chip provides the signals shown in

Figure 16 for connection to a 640 pixel x 200 line LCD panel. These signals operate

as indicated only when the F8680A chip is programmed for LCD mode (through

CREG 11h).

Figure 16. Display Controller Signals to the LCD Panel

where: DOT3:0 Display Data (O) - pixel output to LCD panels.

DOTCLOCK Dot Clock (O) - output to LCD panels.

HS (LP) Horizontal Sync / Latch Pulse (O) - latch pulse signal when in

LCD mode.

VS (FLM) Vertical Sync / First Line Marker (O) - first line indicator signal

when in LCD mode.

For panels that require special consideration, the F8680A programmable pins

provide two display-related functions: alternative dot clock input and AC drive clock

output.

F8680A PC/CHIP Functional Description ■

Chips and Technologies, Inc. P R E L I M I N A R Y -- Revision 2.0 -- 6/2/94 49

Alternative Dot Clock Input on PS4. An LCD panel that requires a non-standard

dot clock rate can be used by providing the appropriate clock input to pin PS4. Note

that there is a relationship between the dot clock supplied and the speed of the

display SRAM selected: the SRAM access time must be less than twice the period of

the dot clock provided, or

Tacc < (2 x Tper) -- margin

For the standard 14.31818MHz input, Tper is 70ns; with a recommended margin of

20ns, Tacc becomes 120ns. If a 20MHz dot clock were chosen, using the same safety

margin as above would require 80ns or better SRAM.

The alternative dot clock function is available only on PS4, and is enabled through

code similar to the following:

LFEAT 8Ch,0 ; disable PS3 for output through CREG 88

LFEAT 11,11001000b ; enable dot clock as PS4, set LCD mode in CREG 11

Note that the byte written to CREG 11h must be adjusted according to the other

features that are also set through that CREG.

ACDCLK Output Option on PS2. LCD panels use an AC drive clock

(‘‘M’’ clock) signal to control the bias polarity of cells in the panel such that none of

the pixel cells is subjected to a non-zero average DC bias. Such a bias would cause

vertical lines to appear on the display, and could possibly damage the panel. While

many LCD panels provide their own on-board circuitry for generating the panel AC

drive clock signal, panels without this circuitry can be accommodated through pin

PS2.

The AC drive clock function ACDCLK is available only on PS2 and is programmed

through CREG 84h and CRT Controller register index 05 (only when in LCD mode).

Code similar to the following can be used to set up ACDCLK operation:

LFEAT 11h,10001000b ; set LCD mode in CREG 11

LFEAT 84h,01011110b ; enable ACDCLK output on PS2 through CREG 84

MOV DX,03D4h ; write CRT controller index

MOV AL,05 ; index 05 counts LPs per ACDCLK

OUT AL,DX

MOV DX,03D5h ; write CRT controller data

MOV AL, value ; how many LPs per ACDCLK?

OUT AL,DX

The value written depends on the frequency desired at PS2 for use as ACDCLK.

The value indicates the number of latch pulses (LP) to count before toggling PS2,

and should be an odd value because the panel uses an even number of lines. An

appropriate value can be determined by experimentation for the specific panel in use.

The AC drive clock signal produced will always have a 50 percent duty cycle.

■ Functional Description F8680A PC/CHIP

50 P R E L I M I N A R Y -- Revision 2.0 -- 6/2/94 Chips and Technologies, Inc.

As an alternative to using the ACDCLK function, a 256Hz frequency output can be

programmed on PS2 and externally latched with the Latch Pulse signal HS(LP) to

provide an alternating drive clock signal.

and CREG 11h be programmed. CREG 0E handles the hardware configuration as

follows:

•EDC, DCPH, and DCP enable the dot clock signal out of the F8680A chip on the

DOTCLOCK pin, and select signal phase and polarity.

•CP selects the signal polarity of the DOT3:0 pixel lines (to determine whether a

positive or a negative image is displayed).

•CHS and CVS select the signal polarity of Latch Pulse signal LP (pin HS/LP) and

First Line Marker signal FLM (pin VS/FLM).

•EGOUT enables all display controller output pins, or forces them to ground.

•GENB enables the graphics subsystem, or disables it so that an external display

controller can respond instead.

CREG 11h handles system software operational details, so they need not be

considered in the hardware design. However, note that CREG 11h holds the DCSEL

bit that chooses the source of the dot clock, either the internally generated clock or

the optional external dot clock input on PS3. CREG 11h also holds the LCD bit,

which must be set before LCD panel operation is possible.

The remaining registers, the CRT Controller registers, are all CGA-compatible in

their operation.

F8680A PC/CHIP Functional Description ■

Chips and Technologies, Inc. P R E L I M I N A R Y -- Revision 2.0 -- 6/2/94 51

CRT Interface

The display controller defaults to operation in CRT mode. Figure 17 shows the

signals available for driving a CRT.

Figure 17. Display Controller Signals to the CRT

where: DOT3(I)

DOT2(R)

DOT1(G)

DOT0(B)

Display Data (O) - used as output to CRTs.

HS Horizontal Sync (O) - horizontal synchronization signal to CRT

when programmed for CRT mode.

VS Vertical Sync (O) - vertical synchronization signal to CRT when

programmed for CRT mode.

■ Functional Description F8680A PC/CHIP

52 P R E L I M I N A R Y -- Revision 2.0 -- 6/2/94 Chips and Technologies, Inc.

DC Electrical Characteristics

The F8680A microchip operates in the range of 3.3V -10% to 5V +10%. Table 13

shows voltage levels and ambient temperature for both 3.3V and 5V operation.

Table 13. Operating Conditions

Symbol Parameter Min. Max. Unit

Vcc Supply Voltage

3.3V 4.5

3.0 5.5

3.6 V

TAAmbient Temperature 070 oC

TAAmbient Temperature Industrial -40 85 oC

Table 14 shows input, output, and I/O capacitance values for 5V operation.

Table 14. Capacitance

Symbol Parameter Max. Unit Note

Cin Input Capacitance 8pF Vcc = 5V

Cout Output Capacitance 8pF Vcc = 5V

CI/O I/O Capacitance 8pF Vcc = 5V

TrOutput Transition Time See Figures 18,19

Figures 18 and 19 show the typical and minimum transition times vs load

capacitance with Vcc=5.5V.

F8680A PC/CHIP DC Electrical Characteristics ■

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Figure 18. Typical Output Transition Time vs Load Capacitance

Figure 19. Minimum Output Transition Time vs Load Capacitance

■ DC Electrical Characteristics F8680A PC/CHIP

54 P R E L I M I N A R Y -- Revision 2.0 -- 6/2/94 Chips and Technologies, Inc.

Tables 15 and 16 and Figures 20 through 23 summarize the DC characteristics for

both 5V and 3V operation.

Table 15. DC Characteristics at 5V

Symbol Parameter Min. Typ. Max. Unit Note

Vil Input Low Voltage -0.3 -- 1.0 V

Vih Input High Voltage Vcc-1.0 -- Vcc+0.3 V

Vol Output Low Voltage -- -- 0.4 VAll outputs except

RD7:0, Iol=8mA

Vol Output Low Voltage -- -- 0.4 VRD7:0 outputs only,

Iol=16mA

Voh Output High Voltage 2.4 -- -- VIoh=8mA

Ioh Output Source Current See Figure 20

Iol Output Sink Current See Figure 21

Iil Input Leakage Current -- -- +10 µAVin=Vcc to 0V

Ioz Output Leakage Current -- -- +10 µAVout=Vcc to 0V

Iccac Vcc Supply Current -- 40 -- mA @8MHz

Iccsb Standby Pwr. Supply Current -- 50 -- µA32kHz clock only

Iccdc Quiescent Current -- 10 -- µANo clocks running

Figure 20. Output Source Current vs Output Voltage (@Vcc=4.5V)

F8680A PC/CHIP DC Electrical Characteristics ■

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Figure 21. Output Sink Current vs Output Voltage (@Vcc=4.5V)

Table 16. DC Characteristics at 3.3V

Symbol Parameter Min. Typ. Max. Unit Note

Vil Input Low Voltage -- 0.5 V

Vih Input High Voltage Vcc-0.5 -- V

Vol Output Low Voltage -- 0.4 VAll outputs except RD7:0,

Iol=4mA

Vol Output Low Voltage -- 0.4 VRD7:0 outputs only, Iol=8mA

Voh Output High Voltage 2.4 -- VIoh=4mA

Ioh Output Source Current See Figure 22

Iol Output Sink Current See Figure 23

Iil Input Leakage Current -- +10 µAVin=Vcc to 0V

Ioz Output Leakage Current -- +10 µAVout=Vcc to 0V

Iccac Vcc Supply Current -- 20 -- mA @8MHz

Iccsb Standby Pwr. Supply

Current -- 30 -- µA32kHz clock only

Iccdc Quiescent Current -- 10 -- µANo clocks running

■ DC Electrical Characteristics F8680A PC/CHIP

56 P R E L I M I N A R Y -- Revision 2.0 -- 6/2/94 Chips and Technologies, Inc.

Figure 22. Output Source Current vs Output Voltage (@Vcc=3V)

Figure 23. Output Sink Current vs Output Voltage (@Vcc=3V)

F8680A PC/CHIP DC Electrical Characteristics ■

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AC Specifications

The AC specifications for the F8680A consist of 12 parameters defining input setup

time, input hold time, and output valid delay time. All system timings are a function

of these parameters and the input frequency being used to clock the CPU.

The 12 timing parameters are defined in reference to an internal signal known as

LatchCLK. The LatchCLK signal is brought out of the chip through the CLK pin

(pin 28) when the XT bus is programmed for a bus clock speed of one clock cycle

per state (CREG 01 bits 1:0=11).

The functional timing diagrams can be used to determine on which LatchCLK edge

the various signals are generated or sampled. This information, along with the input

setup time, input hold time, and output delay time data, can be used to perform a

systems-level worst-case timing analysis.

Tables 17 through 32 and Figures 24 through 52 summarize the AC characteristics of

the F8680A microchip. All timings are in nanoseconds (ns) unless otherwise noted.

Table 17. Timing Symbols Associated with Signal Types

Symbol Signals

Output

Signal

Types

t101, t102 ADR25:0

t103, t104 IOW*, MEMW*, CS10-11*, CS20-22*, WE0-1*, ROMCS*, GRACS*,

GRAWE*, MCCE1-2*, MDIR

t105, t106 AEN, ALE, DACK0-3*, IOR*, MEMR*, TC, OE0-1*, REFRESH*,

DOT3:0, DOTCLOCK, GRA14:0, GRAOE*, GRD7:0, HS/LP, VS/FLM,

KBCLK*, KBDATA*, CARDB, PS1-4, OSCPW, DTR*, RTS*, Tx, SPKR

t107, t108 RD15:0

Input

Signal

Types

t109, t110 DRQ1-3, IOCHCK*, IOCHRDY, IRQ2-7, KBCLK*, KBDATA*,

MCBAT1-2, MCCD1-2*, MCRDY, PS1-4, PWRUP, CD*, CTS*, DSR*,

RI*, Rx, RESET, FLOAT*

t111, t112 RD15:0

■ AC Specifications F8680A PC/CHIP

58 P R E L I M I N A R Y -- Revision 2.0 -- 6/2/94 Chips and Technologies, Inc.

Table 18. Timing Parameters, Commercial (TA = 0 to +70 oC)

Symbol Parameter 3V/8Mhz 5V/8MHz 5V/14MHz

Min.Max. Min. Max. Min. Max. Note

t101 Output address valid delay from LatchCLK 15 ---- 12 ---- 12

t102 Output address valid hold delay from LatchCLK 18 ---- 18 ---- 18

t103 Controls active from LatchCLK -15 +12 -10 +12 -10 +12 1

t103a CS2x* active from LatchCLK 022 018 018 2

t104 Controls inactive from LatchCLK -8 +12 -3 +8 -3 +8

t105 Output valid delay from LatchCLK -6 +18 012 010 3

t105a OE0#, OE1# active from LatchCLK -3 +20 622 622

t106 Output valid hold delay from LatchCLK -10 +15 -6 15 -6 +15

t107 Write data valid delay from LatchCLK ---- 42 ---- 36 ---- 36

t107a Tracking spec, t107 - t103 ---- 50 ---- 28 ---- 28

t108 Write data valid hold delay from LatchCLK -8 15 012 012 4

t109 Input valid setup to LatchCLK 65 ---- 36 ---- 34 ----

t110 Input valid hold from LatchCLK -6 ---- 0---- 0----

t111 Read data valid setup to LatchCLK 50 ---- 27 ---- 20 ----

t112 Read data valid hold from LatchCLK -6 ---- -3 ---- -3 ----

Table 19. Timing Parameters, Industrial (TA = -40 to +85 oC)

Symbol Parameter 3V/8Mhz 5V/8MHz 5V/14MHz

Min.Max. Min. Max. Min. Max. Note

t101 Output address valid delay from LatchCLK 15 ---- 12 ---- 12

t102 Output address valid hold delay from LatchCLK 18 ---- 18 ---- 18

t103 Controls active from LatchCLK -15 +12 -10 +12 -10 +12 1

t103a CS2x* active from LatchCLK 022 018 018 2

t104 Controls inactive from LatchCLK -8 +12 -3 +8 -3 +8

t105 Output valid delay from LatchCLK -6 +18 012 010 3

t105a OE0#, OE1# active from LatchCLK -3 +22 622 622

t106 Output valid hold delay from LatchCLK -10 +15 -6 15 -6 +15

t107 Write data valid delay from LatchCLK ---- 44 ---- 36 ---- 36

t107a Tracking spec, t107 - t103 ---- 50 ---- 28 ---- 28

t108 Write data valid hold delay from LatchCLK -8 15 012 012 4

t109 Input valid setup to LatchCLK 65 ---- 36 ---- 34 ----

t110 Input valid hold from LatchCLK -6 ---- 0---- 0----

t111 Read data valid setup to LatchCLK 50 ---- 27 ---- 20 ----

t112 Read data valid hold from LatchCLK -6 ---- -3 ---- -3 ----

Note: For Tables 18 and 19 above.

1. t103 applies to IOW*, MEMW*, CS1x*, WE*. ROMCS*, GRACS*, GRAWE* MCCEx*.

2. t103a is greater than t101 under all operating conditions.

3. t105 applies to AEN, ALE, DACKx*, IOR*, MEMR*, TC, REFRESH*.

4. t108 is greater than t104 for WE* under all operating conditions.

F8680A PC/CHIP AC Specifications ■

Chips and Technologies, Inc. P R E L I M I N A R Y -- Revision 2.0 -- 6/2/94 59

Table 20. AC Characteristics - System Clock Timings (all 50% duty cycle)

Symbol Parameter Min. Max. Figure No. Note

t1 CPUCLK period 125 ---- 26 1, 8

t2 CPUCLK high time 50 75 26 2, 8

t3 CPUCLK low time 50 75 26 2, 8

t4 CPUCLK rise time 030 26 8

t5 CPUCLK fall time 030 26

t6 CLK14 period 69 ---- 26 3

t7 CLK14 high time 28 49 26 4

t8 CLK14 low time 20 42 26 4

t9 CLK14 rise time 010 26

t10 CLK14 fall time 010 26

t11 CLK32K period 30518 ---- 26 5

t12 CLK32K high time 5340 21362 26 6

t13 CLK32K low time 4270 21362 26 6

t14 CLK32K rise time 03350 26 6

t15 CLK32K fall time 02500 26 6

t16 UARTCLK period 542 ---- 26 7

t17 UARTCLK high time 140 379 26 7

t18 UARTCLK low time 60 379 26 7

t19 UARTCLK rise time 080 26 7

t20 UARTCLK fall time 0130 26 7

Note: 1. No maximum period.

2. When period is 125ns.

3. For DOS Timers compatibility, CLK14 should be 14.31818MHz.

4. When clock period is 69 ns.

5. For proper operation of time of day and sleep mode refresh, 32.768Khz is needed. Tested to 1Mhz.

6. When CLK32K is 32.768Khz.

7. UARTCLK should be 1.832 MHz for PC compatibility. Test to 5 MHz.

8. These numbers are for operation at 8 MHz, and the chip can also operate at 14.318 MHz.

F8680A PC/CHIP AC Specifications ■

Chips and Technologies, Inc. P R E L I M I N A R Y -- Revision 2.0 -- 6/2/94 61

Figure 26. Timing for System Clocks

■ AC Specifications F8680A PC/CHIP

62 P R E L I M I N A R Y -- Revision 2.0 -- 6/2/94 Chips and Technologies, Inc.

Mechanical Specifications

The F8680A microchip is packaged in a 160-pin plastic quad flat pack. The

dimensions are shown in Figure 50.

Figure 50. 160-Pin Plastic Flat Pack

F8680A PC/CHIP Mechanical Specifications ■

Chips and Technologies, Inc. P R E L I M I N A R Y -- Revision 2.0 -- 6/2/94 79

Chips and Technologies, Inc

2950 Zanker Road

San Jose, California 95134

Phone: 408-434-0600

FAX: 408-894-2080

Title: F8680A Data Sheet

Publication No.: DS171

Stock No.: 010171-000

Revision No.: 2.0

Date: 6/2/94