MP1010B Cold Cathode Fluorescent Lamp Driver The Future of Analog IC Technology DESCRIPTION FEATURES The MP1010B is a power solution IC that offers a true complete solution for driving a Cold Cathode Fluorescent Lamps (CCFL). This Power IC converts unregulated DC voltage to a nearly pure sine wave required to ignite and operate the CCFL. Based on proprietary power topology and control techniques it greatly increases the power conversion efficiency. * * * * * * * * * * * EVALUATION BOARD REFERENCE Board Number Dimensions EV1010B-00A 3.75"X x 0.4"Y x 0.25"Z Integrated Power Switches 6.0V to 23V Variable Supply Voltage with Regulated Lamp Current. Rated 12W Power Output at 12V Input Open Lamp Regulation Current and Voltage Feedback Control Logic Level Burst Mode Control Supports Open/Short Lamp Protection Soft-Start Short Circuit Protected Output High Energy Start Pulse Analog and Burst Mode Dimming APPLICATIONS * * LCD Backlight Inverter for Notebook Computers Web Pads, GPS, Desktop Displays, Portable DVD, Car Video Display Systems "MPS" and "The Future of Analog IC Technology" are Registered Trademarks of Monolithic Power Systems, Inc. The MP1010B is covered by US Patents 6,633,138, 6,316,881, 6,114,814. CbaR Cref Cft1 11 HV BSTR 12 PGND 13 OUTR 14 IN 16 15 REF 1 T1 Cs1 BSTL 2 CN1 CbtL 10 PGND 9 OUTL 8 7 IN DR 6 T/B EN 5 BOS 4 3 2 IL BR 1 Cabr Cdrv DBRT 4 N1 N/A MP1010B J1 Rabr COMP FT 17 18 Rbosc ABRT 5 Rdamp CbtR Cp OL 19 FB AGND 20 Rft Rs Ccomp Cft2 TYPICAL APPLICATION N/A Cs2 Risb Rsfb Csfb Rbleed CbaL Cdbr Cbosc Resd Cen Ren2 Cisb Ren1 Rlfb Rbdr EN 3 VBATT 1 Cba2 F1 / 1A Cba1 GND 2 FUSE MP1010B Rev. 2.2 6/30/2009 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. (c) 2009 MPS. All Rights Reserved. 1 MP1010B - COLD CATHODE FLUORESCENT LAMP DRIVER ABSOLUTE MAXIMUM RATINGS (1) PACKAGE REFERENCE TOP VIEW BR 1 20 AGND IL 2 19 FB BOS 3 18 OL T/B 4 17 FT EN 5 16 COMP DR 6 15 REF IN 7 14 IN OUTL 8 13 OUTR PGND 9 12 PGND BSTL 10 11 BSTR Exposed Pad for TSSOP20E Only. Connect to AGND. Recommended Operating Conditions Package Temperature MP1010BEM TSSOP20 -20C to +85C MP1010BEF TSSOP20E -20C to +85C For Tape & Reel, add suffix -Z (eg. MP1010BEM-Z) For RoHS Compliant Packaging, add suffix -LF (eg. MP1010BEM-LF-Z) (2) Input Voltage (VIN) .............................. 6V to 23V Analog Brightness Voltage (VBR) ....... 0V to 1.9V Digital Brightness Voltage (VT/B) ........ 0V to 1.8V Enable (VEN) ......................................... 0V to 5V Operating Frequency (Typical) ................ 60KHz Ambient Operating Temp .............-20C to +85C Thermal Resistance Part Number* * Input Voltage (VIN) ...................................... 25V IL, FB Input Voltages (VIL, VFB) .....................6V OL Input Voltage (VOL)................. -0.3V to +12V Logic Input Voltages ................... -0.3V to +6.8V Power Dissipation...................................... 1.0W Operating Frequency............................. 150KHz Junction Temperature...............................150C Lead Temperature (Solder) ........ 260C Storage Temperature ..............-55C to +150C (3) JA JC TSSOP20 .............................. 90 .....25.... C/W TSSOP20E ............................ 40 ......6..... C/W Notes: 1) Exceeding these ratings may damage the device. 2) The device is not guaranteed to function outside of its operating conditions. 3) Measured on approximately 1" square of 1 oz copper. ELECTRICAL CHARACTERISTICS VIN = 12V, TA = +25C, unless otherwise noted. Parameter Reference Voltage Output Voltage Reference Current Line Regulation Load Regulation Output Drivers Switch On Resistance (4) Short Circuit Current Minimum On Time Minimum On Time Battery Supply Supply Current (Quiescent) Supply Current (Operating) MP1010B Rev. 2.2 6/30/2009 Symbol Condition VREF IREF IREF = 3mA Min Typ Max Units 4.75 5.0 5.25 3.0 30 30 V mA mV mV 0.08 0.11 4 435 1750 0.14 550 2100 A ns ns 1.8 10 2.5 A mA 6.5V < VIN < 23V 0mA < IREF < 3.0mA R(ON) ISC TON(MIN) VCOMP = 0V, VIN = 23V TON(MIN) VCOMP = 0V, VIN = 6V ICC(OFF) ICC(ON) VIN = 23V www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. (c) 2009 MPS. All Rights Reserved. 2 MP1010B - COLD CATHODE FLUORESCENT LAMP DRIVER ELECTRICAL CHARACTERISTICS (continued) VIN = 12V, TA = +25C, unless otherwise noted. Parameter Brightness Control Sense Full Brightness Sense Full Dim Lamp Current Regulation Burst Oscillator Peak Voltage Digital Brightness Offset Voltage Fault Detect Open Lamp Threshold Secondary Current Threshold Fault Mode COMP Current Shutdown Logic Fault Timer Threshold Fault Timer Sink Current Fault Timer Source Current Open Lamp Secondary Overload Enable Voltage Low Enable Voltage High Symbol Condition Min Typ Max Units 360 105 379 117 2 400 130 5 mV mV % VBOS 1.70 1.78 1.86 V V(OS) T/B -50 5 50 mV VIL_MAX VIL_MIN VBR = 2.0V VBR = 0V 7V < VIN < 23V V(TH)OL 0 V(TH)FB ICOMP 1.1 VOL < 0V, VFB > 1.2V V(TH)FT V(L)EN V(H)EN 1.3 475 V A 1.1 1.2 1 1.3 V A 0.5 90 1 120 1.5 160 0.5 A A V V VOL > 0, VFB < 1.2V VOL < 0, VFB < 1.2V VFB > 1.2V 1.2 V 2.0 Note: 4) This parameter is guaranteed by design. MP1010B Rev. 2.2 6/30/2009 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. (c) 2009 MPS. All Rights Reserved. 3 MP1010B - COLD CATHODE FLUORESCENT LAMP DRIVER PIN FUNCTIONS Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name Description BR IL BOS T/B EN DR IN OUTL PGND BSTL BSTR PGND OUTR IN REF COMP FT OL FB AGND Analog Dimming. Lamp Current Feedback Sense Input. Burst Oscillator Timing. Test/Burst Mode Dimming. Chip Enable. Do not float this pin. Internally Generated MOSFET Gate Drive Supply Voltage (6V). Power Supply Input. Output to Load (Tank Circuit). Power Ground. Regulated Output Voltage for Bootstrap Capacitor on Phase L. Regulated Output Voltage for Bootstrap Capacitor on Phase R. Power Ground. Output to Load (Tank Circuit). Power Supply Input. Internally Generated Reference Voltage Output (5V). Loop Compensation Capacitor. Fault Timer. Open Lamp Detect (Lamp Voltage Feedback). Shorted Lamp Detect (Secondary Current Feedback). Small Signal Ground (5). Note: 5) For the MP1010BEF, connect the exposed paddle to AGND (Pin 20). MP1010B Rev. 2.2 6/30/2009 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. (c) 2009 MPS. All Rights Reserved. 4 MP1010B - COLD CATHODE FLUORESCENT LAMP DRIVER BLOCK DIAGRAM REF 15 T/B 4 BOS 3 INTERNAL REGULATORS BURST DIMMING RAMP OSCILLATOR + 5 EN 20 AGND -- 10 BSTL BURST DIMMING CLOCK 7 IN 8 OUTL + -+ -CONTROL LOGIC 9, 12 PGND -+ 13 OUTR -+ 14 IN 11 BSTR 6 SHORT CIRCUIT FT 17 PROTECTION + -- 19 FB 1.2V OPEN LAMP FAULT (OLF) + -- COMP 16 COMP DR 18 OL -GM HALF WAVE RECTIFIER + 2 IL 1 BR Figure 1--Functional Block Diagram MP1010B Rev. 2.2 6/30/2009 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. (c) 2009 MPS. All Rights Reserved. 5 MP1010B - COLD CATHODE FLUORESCENT LAMP DRIVER APPLICATION INFORMATION For an application with either Analog Mode or no dimming, the BOSC pin can be shorted to Analog GND to simplify the circuit. Brightness Control The maximum lamp current is set by Rlfb: Rlfb = 2.2 x VIL _ MAX ILAMP _ RMS Where VIL_MAX = 379mV, typically. For a 6mARMS lamp current, Rlfb = 139. Use a 140 1% resistor for the application. The MP1010B can adjust the lamp brightness in three operating modes: Analog Mode, Burst Mode with a DC input, or Burst Mode with external PWM. The Burst Mode with a DC input is not recommended if the dimming steps required are more than 10. For such applications, please select the MP1016 or MP1028. The three modes are dependent on the pin connections as per the table below. Table 1--Dimming Mode Selection Options Burst Mode with PWM Input Analog Mode with DC Input Burst Mode with DC Input Pin 1 Pin 4 (ABRT) (DBRT) Pin 3 (BOSC) Rbosc Cbosc VREF PWM 220k 100k 0V to 1.9V VREF 220k 100k/ 47nF VREF 0V to 1.8V 220k 47nF The PWM signal should be 200Hz (50Hz) for the best possible performance. For different panels, the burst frequency may need adjusting to avoid possible interference with the LCD horizontal scan frequency. The PWM signal High level should be larger than 1.7V but less than 5V. The Low level should be smaller than 0.7V but higher than 0V. It is recommended that the PWM minimum pulse be longer than 250s, and that the pulse rising and falling edges be less than 0.5s. The PWM signal should be connected to the DBRT pin directly (Rdbr = 0 and remove Cdbr). MP1010B Rev. 2.2 6/30/2009 For analog dimming, a voltage between 1.9V and 5V sets the maximum brightness. 0V sets the minimal brightness, wherein lamp current is 1/3 of the maximum value. Most applications need a RC filter to eradicate noises before the DC signal reaches the ABRT pin. The suggested values are Rabr=47k, Cabr=0.1F. For burst dimming with a DC input, a voltage between 1.8V and 5V sets the maximum duty cycle (100%). 0V sets the minimum duty cycle, which is related to the design of Rbosc and Cbosc. Again, most applications need a RC filter to eradicate noises before the DC signal reaches the DBRT pin. The suggested values are Rdbr=47k, Cdbr=0.1F. Select Rbosc and Cbosc based on the following: 1. Select a burst frequency fBOSC for the panel. 2. Design the minimal duty cycle to meet the minimal pulse request for the lamp. D MIN 250s x fBOSC 3. Determine Rbosc by the formula: Rbosc 1.68 0.42 x D MIN x 350 x 10 -6 4. Determine Cbosc by the formula: Cbosc For a typical C1=47nF. (1 - D MIN ) 0.42 x Rbosc x fBOSC design, www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. (c) 2009 MPS. All Rights Reserved. Rbosc=220k and 6 MP1010B - COLD CATHODE FLUORESCENT LAMP DRIVER Fault Protection Open Lamp: The OL Pin (#18) is used to detect whether an open lamp condition has occurred. A capacitor divider (Cs1 and Cs2) is used to feedback the lamp voltage to OL with a DC bias of VREF through Rs. During normal operation the OL pin is typically at 5V DC with an AC swing of less than 4V in amplitude. If an open lamp condition exists, the AC voltage on the OL line will swing below zero volts. When that occurs, the IC regulates the OL voltage to 10V p-p and a 1A current source will inject into the FT pin. If the voltage at the FT pin exceeds 1.2V, then the chip will shut down. Accordingly, the open lamp voltage can be set using the capacitor divider. Cs1 must be rated at 3KV or above. Its value is typically between 10pF to 22pF. Cs2 = Cs1 x VSTRIKE _ MAX 3 .5 V Where VSTRIKE_MAX is the required maximum lamp striking voltage in RMS value. The value of Rs is typically 100k. It is not critical as long as the resistance is much larger than the impedance of Cs2. Excessive Secondary Current (Shorted Lamp and UL safety specs): The FB pin (#19) is used to detect whether excessive secondary current has occurred. During normal operation the peak FB voltage is below 1.2V. If a fault condition occurs that increases the secondary current, then the voltage at FB will be greater than 1.2V. When that occurs, a 120A current source will inject into the FT pin. If the voltage at the FT pin exceeds 1.2V, then the chip will shut down. The following is the design reference for the secondary winding current. Sensing network: Rsfb, Risb, Csfb and Cisb. Rsfb > 1 .2 V = 1.7k 0.7mA The recommended value is 3.9k to 10k (typically 4.7k). Csfb < MP1010B Rev. 2.2 6/30/2009 0.7 mA Select a capacitor with less than 93nF capacitance for Csfb and make the FB pin voltage peak value around 0.7V in normal operation. The 0.7mA DC and 0.7mA/KHz AC current values are taken from the UL60950 safety requirement. Cisb and Risb make up a high-pass filter, wherein the corner frequency should be between 1KHz and 2KHz so as to minimize the attenuation of the AC signal. The recommended value for Risb is 100k. 1 > Cisb 2 x Risb x 1KHz 1 Cisb > = 0.8nF 2 x Risb x 2KHz 1.6nF = A typical value for Cisb is 1.2nF. Fault Timer: The timing for the fault timer will depend on the sourcing current, as described above, and the capacitor on the FT pin. The user can program the time for the voltage to rise before the chip detects a "real" fault. When a fault is triggered, then the internal drive voltage (VDr) will collapse to 0V. Rft, Cft2 and Cft1 form the fault timer circuit. The recommended value for Rft is 100k. For open lamp time: T(open _ lamp ) = Cft 2(F) x 1.2V 1A For secondary short turn off time: T(short ) = Cft1(F) x 1.2V 120A A typical value for Cft2 is 1F. Cft1 should be much smaller than Cft2, which makes the short circuit protection speed very fast. The recommended value for Cft1 is between 1nF and 10nF. If the protection speed for the secondary short is not critical, the fault timer circuit can be simplified as a single 1F capacitor connected to the FT pin. KHz = 93nF 1 . 2 V x 2 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. (c) 2009 MPS. All Rights Reserved. 7 MP1010B - COLD CATHODE FLUORESCENT LAMP DRIVER Lamp Startup The strike voltage of the lamp will always be guaranteed at any temperature because the MP1010B uses a resonant topology for switching the outputs. The device will continue to switch at the resonant frequency of the tank until the strike voltage is achieved. This eliminates the need for external ramp timing circuits to ensure startup. Chip Enable The chip has an on/off function, which is controlled by the En pin (pin #5, cannot be left floating). The enable signal goes directly to a Schmitt trigger. The chip will turn ON when En is High (>2V) and OFF when it is Low (<0.5V). It is recommended that power be applied to the MP1010B via the IN pins (#7 and #14) a minimum of 3ms prior to the En pin (#5) being switched high. V Input Voltage t 0 V 0 t 3ms Figure 2--Input Voltage vs. Enable Sequence Cref is the bypass capacitor for the internal 5V supply. Cdrv is the bypass cap for the 6.2V gate drive supply. Cref and Cdrv should be 0.1F, X7R (16V) ceramic capacitors. These capacitors must be placed as close as possible to the related pin. CbaL and CbaR are bypass capacitors for the inverter input power. These capacitors will absorb most of the input switching current of the inverter and will require adequate current ripple rating. The typical current rating for these caps is >500mARMS. The typical value is 1F to 2.2F, X7R (25V) ceramic with low ESR value. These capacitors must be placed as close as possible to the related pin and with wide copper traces for the connection. Cba1 and Cba2 are also bypass capacitors for the inverter input power. Their major role is for input filtering. The typical value is 2.2F to 4.7F. X5R or Y5U (25V) ceramic capacitors can be used. CbtR and CbtL are bootstrap capacitors for the upper switches' gate drive. 10nF, X7R (16V) ceramic capacitors are recommended. These capacitors must be placed as close as possible to the related pin. >2V Enable Voltage Design Guidelines Ccomp is the system compensation capacitor that connects COMP and AGND. A 1.5nF or 2.2nF X7R ceramic cap is recommended. Its value affects the lamp current soft-on rising time and soft-off falling time in burst mode. This capacitor must be placed as close as possible to the related pin. Cp is the DC blocking cap in the transformer primary side. It conducts large winding current (typically 0.8ARMS), so low ESR X7R/X5R ceramic is required. The capacitance value is typically 0.47F to 2.2F. The voltage rating needs to be 16V or higher. It is better to use two parallel caps for minimal ESR losses. The OUTL and OUTR pins are the bridge outputs, which conduct typically 0.8ARMS current. Wide copper traces should be used for the connections from IC pins to the transformer. In addition, the connection loop should be minimized to avoid the high dv/dt impact to other circuits. MP1010B Rev. 2.2 6/30/2009 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. (c) 2009 MPS. All Rights Reserved. 8 MP1010B - COLD CATHODE FLUORESCENT LAMP DRIVER Rdamp and Rbleed are used to ensure that the bridge outputs are 0V prior to startup. Typically Rbleed=4.3k and Rdamp=1k. Resd is highly recommended to minimize the possibility of ESD damage in case of mishandling of the IC during board level assembly and test. A typical value is 1k. For most transformers, one terminal connection of the secondary winding is on the side of the primary winding. This side must be connected to the lamp cold side since it cannot handle high voltages. The transformer secondary winding leakage inductance LLK2 is typically 250mH to 350mH (measured with primary winding shorted). The turns ratio is roughly: n VLAMP _ RMS VIN _ MIN x 1. 1 Where VLAMP is the lamp voltage in normal operation conditions and VIN_MIN is the minimum input voltage for the inverter. The open lamp resonant frequency is: f OPEN = 1 2 x L LK 2 x Cs1 It is recommended that the resonant tank (transformer and Cs1) be designed so that fOPEN is less than 100KHz. This is to avoid possible transformer arcing during open lamp conditions. For better thermal performance, please use MP1010BEF (with exposed pad). Normally, there will be a large copper area for ground in the bottom PCB layer which can be used for heat dissipation. Connect the paddle to this ground. Many vias are needed in order to reduce the thermal impedance from the paddle to the bottom ground. For the ground layout, it is better that the analog ground be connect with the power ground at a single point, at the AGND pin or the exposed pad. If the power ground in the bottom layer has sufficient surface area, this connection will not be as critical. Please contact MPS for assistance with the resonant tank design if needed. MP1010B Rev. 2.2 6/30/2009 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. (c) 2009 MPS. All Rights Reserved. 9 MP1010B - COLD CATHODE FLUORESCENT LAMP DRIVER PACKAGE INFORMATION TSSOP20 OR TSSOP20E (EXPOSED PAD) 4.40 TYP 0.40 TYP 6.40 6.60 20 0.65 BSC 11 1.60 TYP 4.30 4.50 PIN 1 ID 1 3.20 TYP 6.20 6.60 5.80 TYP 10 TOP VIEW RECOMMENDED LAND PATTERN 0.80 1.05 1.20 MAX SEATING PLANE 0.19 0.30 0.65 BSC 0.00 0.15 0.09 0.20 SEE DETAIL "A" SIDE VIEW FRONT VIEW GAUGE PLANE 0.25 BSC 3.80 4.30 0o-8o 0.45 0.75 DETAIL A 2.60 3.10 BOTTOM VIEW NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURR. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.10 MILLIMETERS MAX. 5) DRAWING CONFORMS TO JEDEC MO-153, VARIATION ACT. 6) DRAWING IS NOT TO SCALE. NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP1010B Rev. 2.2 6/30/2009 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. (c) 2009 MPS. All Rights Reserved. 10